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sys/dev/bge/if_bge.c
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1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 84 #include <net/if.h> 85 #include <net/if_arp.h> 86 #include <net/ethernet.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 90 #include <net/bpf.h> 91 92 #include <net/if_types.h> 93 #include <net/if_vlan_var.h> 94 95 #include <netinet/in_systm.h> 96 #include <netinet/in.h> 97 #include <netinet/ip.h> 98 99 #include <machine/bus.h> 100 #include <machine/resource.h> 101 #include <sys/bus.h> 102 #include <sys/rman.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 #include "miidevs.h" 107 #include <dev/mii/brgphyreg.h> 108 109 #ifdef __sparc64__ 110 #include <dev/ofw/ofw_bus.h> 111 #include <dev/ofw/openfirm.h> 112 #include <machine/ofw_machdep.h> 113 #include <machine/ver.h> 114 #endif 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 119 #include <dev/bge/if_bgereg.h> 120 121 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 122 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 123 124 MODULE_DEPEND(bge, pci, 1, 1, 1); 125 MODULE_DEPEND(bge, ether, 1, 1, 1); 126 MODULE_DEPEND(bge, miibus, 1, 1, 1); 127 128 /* "device miibus" required. See GENERIC if you get errors here. */ 129 #include "miibus_if.h" 130 131 /* 132 * Various supported device vendors/types and their names. Note: the 133 * spec seems to indicate that the hardware still has Alteon's vendor 134 * ID burned into it, though it will always be overriden by the vendor 135 * ID in the EEPROM. Just to be safe, we cover all possibilities. 136 */ 137 static const struct bge_type { 138 uint16_t bge_vid; 139 uint16_t bge_did; 140 } bge_devs[] = { 141 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 142 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 143 144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 145 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 147 148 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 149 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 201 202 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 203 204 { TC_VENDORID, TC_DEVICEID_3C996 }, 205 206 { 0, 0 } 207 }; 208 209 static const struct bge_vendor { 210 uint16_t v_id; 211 const char *v_name; 212 } bge_vendors[] = { 213 { ALTEON_VENDORID, "Alteon" }, 214 { ALTIMA_VENDORID, "Altima" }, 215 { APPLE_VENDORID, "Apple" }, 216 { BCOM_VENDORID, "Broadcom" }, 217 { SK_VENDORID, "SysKonnect" }, 218 { TC_VENDORID, "3Com" }, 219 220 { 0, NULL } 221 }; 222 223 static const struct bge_revision { 224 uint32_t br_chipid; 225 const char *br_name; 226 } bge_revisions[] = { 227 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 228 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 229 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 230 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 231 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 232 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 233 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 234 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 235 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 236 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 237 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 238 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 239 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 240 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 241 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 242 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 243 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 244 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 245 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 246 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 247 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 248 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 249 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 250 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 251 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 252 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 253 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 254 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 255 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 256 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 257 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 258 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 259 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 260 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 261 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 262 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 263 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 264 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 265 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 266 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 267 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 268 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 269 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 270 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 271 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 272 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 273 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 274 /* 5754 and 5787 share the same ASIC ID */ 275 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 276 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 277 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 278 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 279 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 280 281 { 0, NULL } 282 }; 283 284 /* 285 * Some defaults for major revisions, so that newer steppings 286 * that we don't know about have a shot at working. 287 */ 288 static const struct bge_revision bge_majorrevs[] = { 289 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 290 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 291 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 292 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 293 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 294 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 295 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 296 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 297 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 298 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 299 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 300 /* 5754 and 5787 share the same ASIC ID */ 301 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 302 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 303 304 { 0, NULL } 305 }; 306 307 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 308 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 309 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 310 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 311 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 312 313 const struct bge_revision * bge_lookup_rev(uint32_t); 314 const struct bge_vendor * bge_lookup_vendor(uint16_t); 315 316 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 317 318 static int bge_probe(device_t); 319 static int bge_attach(device_t); 320 static int bge_detach(device_t); 321 static int bge_suspend(device_t); 322 static int bge_resume(device_t); 323 static void bge_release_resources(struct bge_softc *); 324 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 325 static int bge_dma_alloc(device_t); 326 static void bge_dma_free(struct bge_softc *); 327 328 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 329 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 330 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 331 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 332 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 333 334 static void bge_txeof(struct bge_softc *); 335 static void bge_rxeof(struct bge_softc *); 336 337 static void bge_asf_driver_up (struct bge_softc *); 338 static void bge_tick(void *); 339 static void bge_stats_update(struct bge_softc *); 340 static void bge_stats_update_regs(struct bge_softc *); 341 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 342 343 static void bge_intr(void *); 344 static void bge_start_locked(struct ifnet *); 345 static void bge_start(struct ifnet *); 346 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 347 static void bge_init_locked(struct bge_softc *); 348 static void bge_init(void *); 349 static void bge_stop(struct bge_softc *); 350 static void bge_watchdog(struct bge_softc *); 351 static int bge_shutdown(device_t); 352 static int bge_ifmedia_upd_locked(struct ifnet *); 353 static int bge_ifmedia_upd(struct ifnet *); 354 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 355 356 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 357 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 358 359 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 360 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 361 362 static void bge_setpromisc(struct bge_softc *); 363 static void bge_setmulti(struct bge_softc *); 364 365 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *); 366 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 367 static int bge_init_rx_ring_std(struct bge_softc *); 368 static void bge_free_rx_ring_std(struct bge_softc *); 369 static int bge_init_rx_ring_jumbo(struct bge_softc *); 370 static void bge_free_rx_ring_jumbo(struct bge_softc *); 371 static void bge_free_tx_ring(struct bge_softc *); 372 static int bge_init_tx_ring(struct bge_softc *); 373 374 static int bge_chipinit(struct bge_softc *); 375 static int bge_blockinit(struct bge_softc *); 376 377 static int bge_has_eaddr(struct bge_softc *); 378 static uint32_t bge_readmem_ind(struct bge_softc *, int); 379 static void bge_writemem_ind(struct bge_softc *, int, int); 380 static void bge_writembx(struct bge_softc *, int, int); 381 #ifdef notdef 382 static uint32_t bge_readreg_ind(struct bge_softc *, int); 383 #endif 384 static void bge_writemem_direct(struct bge_softc *, int, int); 385 static void bge_writereg_ind(struct bge_softc *, int, int); 386 static void bge_set_max_readrq(struct bge_softc *, int); 387 388 static int bge_miibus_readreg(device_t, int, int); 389 static int bge_miibus_writereg(device_t, int, int, int); 390 static void bge_miibus_statchg(device_t); 391 #ifdef DEVICE_POLLING 392 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 393 #endif 394 395 #define BGE_RESET_START 1 396 #define BGE_RESET_STOP 2 397 static void bge_sig_post_reset(struct bge_softc *, int); 398 static void bge_sig_legacy(struct bge_softc *, int); 399 static void bge_sig_pre_reset(struct bge_softc *, int); 400 static int bge_reset(struct bge_softc *); 401 static void bge_link_upd(struct bge_softc *); 402 403 /* 404 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 405 * leak information to untrusted users. It is also known to cause alignment 406 * traps on certain architectures. 407 */ 408 #ifdef BGE_REGISTER_DEBUG 409 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 410 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 411 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 412 #endif 413 static void bge_add_sysctls(struct bge_softc *); 414 415 static device_method_t bge_methods[] = { 416 /* Device interface */ 417 DEVMETHOD(device_probe, bge_probe), 418 DEVMETHOD(device_attach, bge_attach), 419 DEVMETHOD(device_detach, bge_detach), 420 DEVMETHOD(device_shutdown, bge_shutdown), 421 DEVMETHOD(device_suspend, bge_suspend), 422 DEVMETHOD(device_resume, bge_resume), 423 424 /* bus interface */ 425 DEVMETHOD(bus_print_child, bus_generic_print_child), 426 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 427 428 /* MII interface */ 429 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 430 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 431 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 432 433 { 0, 0 } 434 }; 435 436 static driver_t bge_driver = { 437 "bge", 438 bge_methods, 439 sizeof(struct bge_softc) 440 }; 441 442 static devclass_t bge_devclass; 443 444 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 445 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 446 447 static int bge_allow_asf = 0; 448 449 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 450 451 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 452 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 453 "Allow ASF mode if available"); 454 455 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 456 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 457 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 458 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 459 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 460 461 static int 462 bge_has_eaddr(struct bge_softc *sc) 463 { 464 #ifdef __sparc64__ 465 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 466 device_t dev; 467 uint32_t subvendor; 468 469 dev = sc->bge_dev; 470 471 /* 472 * The on-board BGEs found in sun4u machines aren't fitted with 473 * an EEPROM which means that we have to obtain the MAC address 474 * via OFW and that some tests will always fail. We distinguish 475 * such BGEs by the subvendor ID, which also has to be obtained 476 * from OFW instead of the PCI configuration space as the latter 477 * indicates Broadcom as the subvendor of the netboot interface. 478 * For early Blade 1500 and 2500 we even have to check the OFW 479 * device path as the subvendor ID always defaults to Broadcom 480 * there. 481 */ 482 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 483 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 484 subvendor == SUN_VENDORID) 485 return (0); 486 memset(buf, 0, sizeof(buf)); 487 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 488 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 489 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 490 return (0); 491 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 492 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 493 return (0); 494 } 495 #endif 496 return (1); 497 } 498 499 static uint32_t 500 bge_readmem_ind(struct bge_softc *sc, int off) 501 { 502 device_t dev; 503 uint32_t val; 504 505 dev = sc->bge_dev; 506 507 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 508 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 509 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 510 return (val); 511 } 512 513 static void 514 bge_writemem_ind(struct bge_softc *sc, int off, int val) 515 { 516 device_t dev; 517 518 dev = sc->bge_dev; 519 520 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 521 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 522 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 523 } 524 525 /* 526 * PCI Express only 527 */ 528 static void 529 bge_set_max_readrq(struct bge_softc *sc, int expr_ptr) 530 { 531 device_t dev; 532 uint16_t val; 533 534 KASSERT((sc->bge_flags & BGE_FLAG_PCIE) && expr_ptr != 0, 535 ("%s: not applicable", __func__)); 536 537 dev = sc->bge_dev; 538 539 val = pci_read_config(dev, expr_ptr + BGE_PCIE_DEVCTL, 2); 540 if ((val & BGE_PCIE_DEVCTL_MAX_READRQ_MASK) != 541 BGE_PCIE_DEVCTL_MAX_READRQ_4096) { 542 if (bootverbose) 543 device_printf(dev, "adjust device control 0x%04x ", 544 val); 545 val &= ~BGE_PCIE_DEVCTL_MAX_READRQ_MASK; 546 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 547 pci_write_config(dev, expr_ptr + BGE_PCIE_DEVCTL, val, 2); 548 if (bootverbose) 549 printf("-> 0x%04x\n", val); 550 } 551 } 552 553 #ifdef notdef 554 static uint32_t 555 bge_readreg_ind(struct bge_softc *sc, int off) 556 { 557 device_t dev; 558 559 dev = sc->bge_dev; 560 561 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 562 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 563 } 564 #endif 565 566 static void 567 bge_writereg_ind(struct bge_softc *sc, int off, int val) 568 { 569 device_t dev; 570 571 dev = sc->bge_dev; 572 573 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 574 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 575 } 576 577 static void 578 bge_writemem_direct(struct bge_softc *sc, int off, int val) 579 { 580 CSR_WRITE_4(sc, off, val); 581 } 582 583 static void 584 bge_writembx(struct bge_softc *sc, int off, int val) 585 { 586 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 587 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 588 589 CSR_WRITE_4(sc, off, val); 590 } 591 592 /* 593 * Map a single buffer address. 594 */ 595 596 static void 597 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 598 { 599 struct bge_dmamap_arg *ctx; 600 601 if (error) 602 return; 603 604 ctx = arg; 605 606 if (nseg > ctx->bge_maxsegs) { 607 ctx->bge_maxsegs = 0; 608 return; 609 } 610 611 ctx->bge_busaddr = segs->ds_addr; 612 } 613 614 static uint8_t 615 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 616 { 617 uint32_t access, byte = 0; 618 int i; 619 620 /* Lock. */ 621 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 622 for (i = 0; i < 8000; i++) { 623 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 624 break; 625 DELAY(20); 626 } 627 if (i == 8000) 628 return (1); 629 630 /* Enable access. */ 631 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 632 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 633 634 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 635 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 636 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 637 DELAY(10); 638 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 639 DELAY(10); 640 break; 641 } 642 } 643 644 if (i == BGE_TIMEOUT * 10) { 645 if_printf(sc->bge_ifp, "nvram read timed out\n"); 646 return (1); 647 } 648 649 /* Get result. */ 650 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 651 652 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 653 654 /* Disable access. */ 655 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 656 657 /* Unlock. */ 658 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 659 CSR_READ_4(sc, BGE_NVRAM_SWARB); 660 661 return (0); 662 } 663 664 /* 665 * Read a sequence of bytes from NVRAM. 666 */ 667 static int 668 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 669 { 670 int err = 0, i; 671 uint8_t byte = 0; 672 673 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 674 return (1); 675 676 for (i = 0; i < cnt; i++) { 677 err = bge_nvram_getbyte(sc, off + i, &byte); 678 if (err) 679 break; 680 *(dest + i) = byte; 681 } 682 683 return (err ? 1 : 0); 684 } 685 686 /* 687 * Read a byte of data stored in the EEPROM at address 'addr.' The 688 * BCM570x supports both the traditional bitbang interface and an 689 * auto access interface for reading the EEPROM. We use the auto 690 * access method. 691 */ 692 static uint8_t 693 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 694 { 695 int i; 696 uint32_t byte = 0; 697 698 /* 699 * Enable use of auto EEPROM access so we can avoid 700 * having to use the bitbang method. 701 */ 702 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 703 704 /* Reset the EEPROM, load the clock period. */ 705 CSR_WRITE_4(sc, BGE_EE_ADDR, 706 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 707 DELAY(20); 708 709 /* Issue the read EEPROM command. */ 710 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 711 712 /* Wait for completion */ 713 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 714 DELAY(10); 715 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 716 break; 717 } 718 719 if (i == BGE_TIMEOUT * 10) { 720 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 721 return (1); 722 } 723 724 /* Get result. */ 725 byte = CSR_READ_4(sc, BGE_EE_DATA); 726 727 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 728 729 return (0); 730 } 731 732 /* 733 * Read a sequence of bytes from the EEPROM. 734 */ 735 static int 736 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 737 { 738 int i, error = 0; 739 uint8_t byte = 0; 740 741 for (i = 0; i < cnt; i++) { 742 error = bge_eeprom_getbyte(sc, off + i, &byte); 743 if (error) 744 break; 745 *(dest + i) = byte; 746 } 747 748 return (error ? 1 : 0); 749 } 750 751 static int 752 bge_miibus_readreg(device_t dev, int phy, int reg) 753 { 754 struct bge_softc *sc; 755 uint32_t val, autopoll; 756 int i; 757 758 sc = device_get_softc(dev); 759 760 /* 761 * Broadcom's own driver always assumes the internal 762 * PHY is at GMII address 1. On some chips, the PHY responds 763 * to accesses at all addresses, which could cause us to 764 * bogusly attach the PHY 32 times at probe type. Always 765 * restricting the lookup to address 1 is simpler than 766 * trying to figure out which chips revisions should be 767 * special-cased. 768 */ 769 if (phy != 1) 770 return (0); 771 772 /* Reading with autopolling on may trigger PCI errors */ 773 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 774 if (autopoll & BGE_MIMODE_AUTOPOLL) { 775 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 776 DELAY(40); 777 } 778 779 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 780 BGE_MIPHY(phy) | BGE_MIREG(reg)); 781 782 for (i = 0; i < BGE_TIMEOUT; i++) { 783 DELAY(10); 784 val = CSR_READ_4(sc, BGE_MI_COMM); 785 if (!(val & BGE_MICOMM_BUSY)) 786 break; 787 } 788 789 if (i == BGE_TIMEOUT) { 790 device_printf(sc->bge_dev, 791 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 792 phy, reg, val); 793 val = 0; 794 goto done; 795 } 796 797 DELAY(5); 798 val = CSR_READ_4(sc, BGE_MI_COMM); 799 800 done: 801 if (autopoll & BGE_MIMODE_AUTOPOLL) { 802 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 803 DELAY(40); 804 } 805 806 if (val & BGE_MICOMM_READFAIL) 807 return (0); 808 809 return (val & 0xFFFF); 810 } 811 812 static int 813 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 814 { 815 struct bge_softc *sc; 816 uint32_t autopoll; 817 int i; 818 819 sc = device_get_softc(dev); 820 821 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 822 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 823 return(0); 824 825 /* Reading with autopolling on may trigger PCI errors */ 826 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 827 if (autopoll & BGE_MIMODE_AUTOPOLL) { 828 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 829 DELAY(40); 830 } 831 832 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 833 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 834 835 for (i = 0; i < BGE_TIMEOUT; i++) { 836 DELAY(10); 837 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 838 DELAY(5); 839 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 840 break; 841 } 842 } 843 844 if (i == BGE_TIMEOUT) { 845 device_printf(sc->bge_dev, 846 "PHY write timed out (phy %d, reg %d, val %d)\n", 847 phy, reg, val); 848 return (0); 849 } 850 851 if (autopoll & BGE_MIMODE_AUTOPOLL) { 852 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 853 DELAY(40); 854 } 855 856 857 return (0); 858 } 859 860 static void 861 bge_miibus_statchg(device_t dev) 862 { 863 struct bge_softc *sc; 864 struct mii_data *mii; 865 sc = device_get_softc(dev); 866 mii = device_get_softc(sc->bge_miibus); 867 868 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 869 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 870 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 871 else 872 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 873 874 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 875 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 876 else 877 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 878 } 879 880 /* 881 * Intialize a standard receive ring descriptor. 882 */ 883 static int 884 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m) 885 { 886 struct mbuf *m_new = NULL; 887 struct bge_rx_bd *r; 888 struct bge_dmamap_arg ctx; 889 int error; 890 891 if (m == NULL) { 892 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 893 if (m_new == NULL) 894 return (ENOBUFS); 895 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 896 } else { 897 m_new = m; 898 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 899 m_new->m_data = m_new->m_ext.ext_buf; 900 } 901 902 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 903 m_adj(m_new, ETHER_ALIGN); 904 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 905 r = &sc->bge_ldata.bge_rx_std_ring[i]; 906 ctx.bge_maxsegs = 1; 907 ctx.sc = sc; 908 error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 909 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 910 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 911 if (error || ctx.bge_maxsegs == 0) { 912 if (m == NULL) { 913 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 914 m_freem(m_new); 915 } 916 return (ENOMEM); 917 } 918 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr); 919 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr); 920 r->bge_flags = BGE_RXBDFLAG_END; 921 r->bge_len = m_new->m_len; 922 r->bge_idx = i; 923 924 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 925 sc->bge_cdata.bge_rx_std_dmamap[i], 926 BUS_DMASYNC_PREREAD); 927 928 return (0); 929 } 930 931 /* 932 * Initialize a jumbo receive ring descriptor. This allocates 933 * a jumbo buffer from the pool managed internally by the driver. 934 */ 935 static int 936 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 937 { 938 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 939 struct bge_extrx_bd *r; 940 struct mbuf *m_new = NULL; 941 int nsegs; 942 int error; 943 944 if (m == NULL) { 945 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 946 if (m_new == NULL) 947 return (ENOBUFS); 948 949 m_cljget(m_new, M_DONTWAIT, MJUM9BYTES); 950 if (!(m_new->m_flags & M_EXT)) { 951 m_freem(m_new); 952 return (ENOBUFS); 953 } 954 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 955 } else { 956 m_new = m; 957 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 958 m_new->m_data = m_new->m_ext.ext_buf; 959 } 960 961 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 962 m_adj(m_new, ETHER_ALIGN); 963 964 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 965 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 966 m_new, segs, &nsegs, BUS_DMA_NOWAIT); 967 if (error) { 968 if (m == NULL) 969 m_freem(m_new); 970 return (error); 971 } 972 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 973 974 /* 975 * Fill in the extended RX buffer descriptor. 976 */ 977 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 978 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 979 r->bge_idx = i; 980 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 981 switch (nsegs) { 982 case 4: 983 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 984 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 985 r->bge_len3 = segs[3].ds_len; 986 case 3: 987 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 988 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 989 r->bge_len2 = segs[2].ds_len; 990 case 2: 991 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 992 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 993 r->bge_len1 = segs[1].ds_len; 994 case 1: 995 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 996 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 997 r->bge_len0 = segs[0].ds_len; 998 break; 999 default: 1000 panic("%s: %d segments\n", __func__, nsegs); 1001 } 1002 1003 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 1004 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1005 BUS_DMASYNC_PREREAD); 1006 1007 return (0); 1008 } 1009 1010 /* 1011 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1012 * that's 1MB or memory, which is a lot. For now, we fill only the first 1013 * 256 ring entries and hope that our CPU is fast enough to keep up with 1014 * the NIC. 1015 */ 1016 static int 1017 bge_init_rx_ring_std(struct bge_softc *sc) 1018 { 1019 int i; 1020 1021 for (i = 0; i < BGE_SSLOTS; i++) { 1022 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 1023 return (ENOBUFS); 1024 }; 1025 1026 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1027 sc->bge_cdata.bge_rx_std_ring_map, 1028 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1029 1030 sc->bge_std = i - 1; 1031 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1032 1033 return (0); 1034 } 1035 1036 static void 1037 bge_free_rx_ring_std(struct bge_softc *sc) 1038 { 1039 int i; 1040 1041 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1042 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1043 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 1044 sc->bge_cdata.bge_rx_std_dmamap[i], 1045 BUS_DMASYNC_POSTREAD); 1046 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1047 sc->bge_cdata.bge_rx_std_dmamap[i]); 1048 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1049 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1050 } 1051 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1052 sizeof(struct bge_rx_bd)); 1053 } 1054 } 1055 1056 static int 1057 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1058 { 1059 struct bge_rcb *rcb; 1060 int i; 1061 1062 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1063 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1064 return (ENOBUFS); 1065 }; 1066 1067 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1068 sc->bge_cdata.bge_rx_jumbo_ring_map, 1069 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1070 1071 sc->bge_jumbo = i - 1; 1072 1073 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1074 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1075 BGE_RCB_FLAG_USE_EXT_RX_BD); 1076 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1077 1078 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1079 1080 return (0); 1081 } 1082 1083 static void 1084 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1085 { 1086 int i; 1087 1088 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1089 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1090 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1091 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1092 BUS_DMASYNC_POSTREAD); 1093 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1094 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1095 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1096 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1097 } 1098 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1099 sizeof(struct bge_extrx_bd)); 1100 } 1101 } 1102 1103 static void 1104 bge_free_tx_ring(struct bge_softc *sc) 1105 { 1106 int i; 1107 1108 if (sc->bge_ldata.bge_tx_ring == NULL) 1109 return; 1110 1111 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1112 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1113 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 1114 sc->bge_cdata.bge_tx_dmamap[i], 1115 BUS_DMASYNC_POSTWRITE); 1116 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1117 sc->bge_cdata.bge_tx_dmamap[i]); 1118 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1119 sc->bge_cdata.bge_tx_chain[i] = NULL; 1120 } 1121 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1122 sizeof(struct bge_tx_bd)); 1123 } 1124 } 1125 1126 static int 1127 bge_init_tx_ring(struct bge_softc *sc) 1128 { 1129 sc->bge_txcnt = 0; 1130 sc->bge_tx_saved_considx = 0; 1131 1132 /* Initialize transmit producer index for host-memory send ring. */ 1133 sc->bge_tx_prodidx = 0; 1134 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1135 1136 /* 5700 b2 errata */ 1137 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1138 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1139 1140 /* NIC-memory send ring not used; initialize to zero. */ 1141 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1142 /* 5700 b2 errata */ 1143 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1144 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1145 1146 return (0); 1147 } 1148 1149 static void 1150 bge_setpromisc(struct bge_softc *sc) 1151 { 1152 struct ifnet *ifp; 1153 1154 BGE_LOCK_ASSERT(sc); 1155 1156 ifp = sc->bge_ifp; 1157 1158 /* Enable or disable promiscuous mode as needed. */ 1159 if (ifp->if_flags & IFF_PROMISC) 1160 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1161 else 1162 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1163 } 1164 1165 static void 1166 bge_setmulti(struct bge_softc *sc) 1167 { 1168 struct ifnet *ifp; 1169 struct ifmultiaddr *ifma; 1170 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1171 int h, i; 1172 1173 BGE_LOCK_ASSERT(sc); 1174 1175 ifp = sc->bge_ifp; 1176 1177 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1178 for (i = 0; i < 4; i++) 1179 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1180 return; 1181 } 1182 1183 /* First, zot all the existing filters. */ 1184 for (i = 0; i < 4; i++) 1185 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1186 1187 /* Now program new ones. */ 1188 IF_ADDR_LOCK(ifp); 1189 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1190 if (ifma->ifma_addr->sa_family != AF_LINK) 1191 continue; 1192 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1193 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1194 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1195 } 1196 IF_ADDR_UNLOCK(ifp); 1197 1198 for (i = 0; i < 4; i++) 1199 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1200 } 1201 1202 static void 1203 bge_sig_pre_reset(sc, type) 1204 struct bge_softc *sc; 1205 int type; 1206 { 1207 /* 1208 * Some chips don't like this so only do this if ASF is enabled 1209 */ 1210 if (sc->bge_asf_mode) 1211 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1212 1213 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1214 switch (type) { 1215 case BGE_RESET_START: 1216 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1217 break; 1218 case BGE_RESET_STOP: 1219 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1220 break; 1221 } 1222 } 1223 } 1224 1225 static void 1226 bge_sig_post_reset(sc, type) 1227 struct bge_softc *sc; 1228 int type; 1229 { 1230 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1231 switch (type) { 1232 case BGE_RESET_START: 1233 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1234 /* START DONE */ 1235 break; 1236 case BGE_RESET_STOP: 1237 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1238 break; 1239 } 1240 } 1241 } 1242 1243 static void 1244 bge_sig_legacy(sc, type) 1245 struct bge_softc *sc; 1246 int type; 1247 { 1248 if (sc->bge_asf_mode) { 1249 switch (type) { 1250 case BGE_RESET_START: 1251 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1252 break; 1253 case BGE_RESET_STOP: 1254 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1255 break; 1256 } 1257 } 1258 } 1259 1260 void bge_stop_fw(struct bge_softc *); 1261 void 1262 bge_stop_fw(sc) 1263 struct bge_softc *sc; 1264 { 1265 int i; 1266 1267 if (sc->bge_asf_mode) { 1268 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1269 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1270 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1271 1272 for (i = 0; i < 100; i++ ) { 1273 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1274 break; 1275 DELAY(10); 1276 } 1277 } 1278 } 1279 1280 /* 1281 * Do endian, PCI and DMA initialization. 1282 */ 1283 static int 1284 bge_chipinit(struct bge_softc *sc) 1285 { 1286 uint32_t dma_rw_ctl; 1287 int i; 1288 1289 /* Set endianness before we access any non-PCI registers. */ 1290 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 1291 1292 /* Clear the MAC control register */ 1293 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1294 1295 /* 1296 * Clear the MAC statistics block in the NIC's 1297 * internal memory. 1298 */ 1299 for (i = BGE_STATS_BLOCK; 1300 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1301 BGE_MEMWIN_WRITE(sc, i, 0); 1302 1303 for (i = BGE_STATUS_BLOCK; 1304 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1305 BGE_MEMWIN_WRITE(sc, i, 0); 1306 1307 /* Set up the PCI DMA control register. */ 1308 if (sc->bge_flags & BGE_FLAG_PCIE) { 1309 /* PCI Express bus */ 1310 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1311 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0xF) | 1312 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x2); 1313 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1314 /* PCI-X bus */ 1315 if (BGE_IS_5714_FAMILY(sc)) { 1316 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1317 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1318 /* XXX magic values, Broadcom-supplied Linux driver */ 1319 dma_rw_ctl |= (1 << 20) | (1 << 18); 1320 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) 1321 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1322 else 1323 dma_rw_ctl |= 1 << 15; 1324 1325 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1326 /* 1327 * The 5704 uses a different encoding of read/write 1328 * watermarks. 1329 */ 1330 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1331 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) | 1332 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3); 1333 else 1334 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1335 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x3) | 1336 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3) | 1337 0x0F; 1338 1339 /* 1340 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1341 * for hardware bugs. 1342 */ 1343 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1344 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1345 uint32_t tmp; 1346 1347 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1348 if (tmp == 0x6 || tmp == 0x7) 1349 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1350 } 1351 } else 1352 /* Conventional PCI bus */ 1353 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1354 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) | 1355 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x7) | 1356 0x0F; 1357 1358 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1359 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1360 sc->bge_asicrev == BGE_ASICREV_BCM5705) 1361 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1362 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1363 1364 /* 1365 * Set up general mode register. 1366 */ 1367 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1368 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1369 BGE_MODECTL_TX_NO_PHDR_CSUM); 1370 1371 /* 1372 * BCM5701 B5 have a bug causing data corruption when using 1373 * 64-bit DMA reads, which can be terminated early and then 1374 * completed later as 32-bit accesses, in combination with 1375 * certain bridges. 1376 */ 1377 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1378 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1379 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1380 1381 /* 1382 * Tell the firmware the driver is running 1383 */ 1384 if (sc->bge_asf_mode & ASF_STACKUP) 1385 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1386 1387 /* 1388 * Disable memory write invalidate. Apparently it is not supported 1389 * properly by these devices. Also ensure that INTx isn't disabled, 1390 * as these chips need it even when using MSI. 1391 */ 1392 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1393 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1394 1395 #ifdef __brokenalpha__ 1396 /* 1397 * Must insure that we do not cross an 8K (bytes) boundary 1398 * for DMA reads. Our highest limit is 1K bytes. This is a 1399 * restriction on some ALPHA platforms with early revision 1400 * 21174 PCI chipsets, such as the AlphaPC 164lx 1401 */ 1402 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1403 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1404 #endif 1405 1406 /* Set the timer prescaler (always 66Mhz) */ 1407 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1408 1409 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1410 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1411 DELAY(40); /* XXX */ 1412 1413 /* Put PHY into ready state */ 1414 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1415 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1416 DELAY(40); 1417 } 1418 1419 return (0); 1420 } 1421 1422 static int 1423 bge_blockinit(struct bge_softc *sc) 1424 { 1425 struct bge_rcb *rcb; 1426 bus_size_t vrcb; 1427 bge_hostaddr taddr; 1428 uint32_t val; 1429 int i; 1430 1431 /* 1432 * Initialize the memory window pointer register so that 1433 * we can access the first 32K of internal NIC RAM. This will 1434 * allow us to set up the TX send ring RCBs and the RX return 1435 * ring RCBs, plus other things which live in NIC memory. 1436 */ 1437 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1438 1439 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1440 1441 if (!(BGE_IS_5705_PLUS(sc))) { 1442 /* Configure mbuf memory pool */ 1443 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1444 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1445 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1446 else 1447 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1448 1449 /* Configure DMA resource pool */ 1450 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1451 BGE_DMA_DESCRIPTORS); 1452 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1453 } 1454 1455 /* Configure mbuf pool watermarks */ 1456 if (!BGE_IS_5705_PLUS(sc)) { 1457 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1458 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1459 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1460 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1461 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1462 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1463 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1464 } else { 1465 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1466 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1467 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1468 } 1469 1470 /* Configure DMA resource watermarks */ 1471 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1472 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1473 1474 /* Enable buffer manager */ 1475 if (!(BGE_IS_5705_PLUS(sc))) { 1476 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1477 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1478 1479 /* Poll for buffer manager start indication */ 1480 for (i = 0; i < BGE_TIMEOUT; i++) { 1481 DELAY(10); 1482 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1483 break; 1484 } 1485 1486 if (i == BGE_TIMEOUT) { 1487 device_printf(sc->bge_dev, 1488 "buffer manager failed to start\n"); 1489 return (ENXIO); 1490 } 1491 } 1492 1493 /* Enable flow-through queues */ 1494 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1495 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1496 1497 /* Wait until queue initialization is complete */ 1498 for (i = 0; i < BGE_TIMEOUT; i++) { 1499 DELAY(10); 1500 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1501 break; 1502 } 1503 1504 if (i == BGE_TIMEOUT) { 1505 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1506 return (ENXIO); 1507 } 1508 1509 /* Initialize the standard RX ring control block */ 1510 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1511 rcb->bge_hostaddr.bge_addr_lo = 1512 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1513 rcb->bge_hostaddr.bge_addr_hi = 1514 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1515 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1516 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1517 if (BGE_IS_5705_PLUS(sc)) 1518 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1519 else 1520 rcb->bge_maxlen_flags = 1521 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1522 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1523 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1524 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1525 1526 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1527 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1528 1529 /* 1530 * Initialize the jumbo RX ring control block 1531 * We set the 'ring disabled' bit in the flags 1532 * field until we're actually ready to start 1533 * using this ring (i.e. once we set the MTU 1534 * high enough to require it). 1535 */ 1536 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1537 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1538 1539 rcb->bge_hostaddr.bge_addr_lo = 1540 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1541 rcb->bge_hostaddr.bge_addr_hi = 1542 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1543 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1544 sc->bge_cdata.bge_rx_jumbo_ring_map, 1545 BUS_DMASYNC_PREREAD); 1546 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1547 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1548 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1549 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1550 rcb->bge_hostaddr.bge_addr_hi); 1551 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1552 rcb->bge_hostaddr.bge_addr_lo); 1553 1554 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1555 rcb->bge_maxlen_flags); 1556 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1557 1558 /* Set up dummy disabled mini ring RCB */ 1559 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1560 rcb->bge_maxlen_flags = 1561 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1562 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1563 rcb->bge_maxlen_flags); 1564 } 1565 1566 /* 1567 * Set the BD ring replentish thresholds. The recommended 1568 * values are 1/8th the number of descriptors allocated to 1569 * each ring. 1570 * XXX The 5754 requires a lower threshold, so it might be a 1571 * requirement of all 575x family chips. The Linux driver sets 1572 * the lower threshold for all 5705 family chips as well, but there 1573 * are reports that it might not need to be so strict. 1574 * 1575 * XXX Linux does some extra fiddling here for the 5906 parts as 1576 * well. 1577 */ 1578 if (BGE_IS_5705_PLUS(sc)) 1579 val = 8; 1580 else 1581 val = BGE_STD_RX_RING_CNT / 8; 1582 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1583 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1584 1585 /* 1586 * Disable all unused send rings by setting the 'ring disabled' 1587 * bit in the flags field of all the TX send ring control blocks. 1588 * These are located in NIC memory. 1589 */ 1590 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1591 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1592 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1593 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1594 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1595 vrcb += sizeof(struct bge_rcb); 1596 } 1597 1598 /* Configure TX RCB 0 (we use only the first ring) */ 1599 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1600 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1601 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1602 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1603 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1604 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1605 if (!(BGE_IS_5705_PLUS(sc))) 1606 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1607 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1608 1609 /* Disable all unused RX return rings */ 1610 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1611 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1612 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1613 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1614 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1615 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1616 BGE_RCB_FLAG_RING_DISABLED)); 1617 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1618 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1619 (i * (sizeof(uint64_t))), 0); 1620 vrcb += sizeof(struct bge_rcb); 1621 } 1622 1623 /* Initialize RX ring indexes */ 1624 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1625 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1626 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1627 1628 /* 1629 * Set up RX return ring 0 1630 * Note that the NIC address for RX return rings is 0x00000000. 1631 * The return rings live entirely within the host, so the 1632 * nicaddr field in the RCB isn't used. 1633 */ 1634 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1635 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1636 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1637 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1638 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); 1639 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1640 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1641 1642 /* Set random backoff seed for TX */ 1643 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1644 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1645 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1646 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1647 BGE_TX_BACKOFF_SEED_MASK); 1648 1649 /* Set inter-packet gap */ 1650 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1651 1652 /* 1653 * Specify which ring to use for packets that don't match 1654 * any RX rules. 1655 */ 1656 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1657 1658 /* 1659 * Configure number of RX lists. One interrupt distribution 1660 * list, sixteen active lists, one bad frames class. 1661 */ 1662 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1663 1664 /* Inialize RX list placement stats mask. */ 1665 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1666 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1667 1668 /* Disable host coalescing until we get it set up */ 1669 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1670 1671 /* Poll to make sure it's shut down. */ 1672 for (i = 0; i < BGE_TIMEOUT; i++) { 1673 DELAY(10); 1674 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1675 break; 1676 } 1677 1678 if (i == BGE_TIMEOUT) { 1679 device_printf(sc->bge_dev, 1680 "host coalescing engine failed to idle\n"); 1681 return (ENXIO); 1682 } 1683 1684 /* Set up host coalescing defaults */ 1685 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1686 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1687 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1688 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1689 if (!(BGE_IS_5705_PLUS(sc))) { 1690 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1691 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1692 } 1693 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1694 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1695 1696 /* Set up address of statistics block */ 1697 if (!(BGE_IS_5705_PLUS(sc))) { 1698 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1699 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1700 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1701 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1702 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1703 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1704 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1705 } 1706 1707 /* Set up address of status block */ 1708 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1709 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1710 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1711 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1712 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1713 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1714 1715 /* Turn on host coalescing state machine */ 1716 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1717 1718 /* Turn on RX BD completion state machine and enable attentions */ 1719 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1720 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1721 1722 /* Turn on RX list placement state machine */ 1723 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1724 1725 /* Turn on RX list selector state machine. */ 1726 if (!(BGE_IS_5705_PLUS(sc))) 1727 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1728 1729 /* Turn on DMA, clear stats */ 1730 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB | 1731 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR | 1732 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB | 1733 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB | 1734 ((sc->bge_flags & BGE_FLAG_TBI) ? 1735 BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1736 1737 /* Set misc. local control, enable interrupts on attentions */ 1738 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1739 1740 #ifdef notdef 1741 /* Assert GPIO pins for PHY reset */ 1742 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 1743 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 1744 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 1745 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 1746 #endif 1747 1748 /* Turn on DMA completion state machine */ 1749 if (!(BGE_IS_5705_PLUS(sc))) 1750 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1751 1752 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 1753 1754 /* Enable host coalescing bug fix. */ 1755 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 1756 sc->bge_asicrev == BGE_ASICREV_BCM5787) 1757 val |= 1 << 29; 1758 1759 /* Turn on write DMA state machine */ 1760 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1761 DELAY(40); 1762 1763 /* Turn on read DMA state machine */ 1764 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1765 if (sc->bge_flags & BGE_FLAG_PCIE) 1766 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 1767 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 1768 DELAY(40); 1769 1770 /* Turn on RX data completion state machine */ 1771 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1772 1773 /* Turn on RX BD initiator state machine */ 1774 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1775 1776 /* Turn on RX data and RX BD initiator state machine */ 1777 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1778 1779 /* Turn on Mbuf cluster free state machine */ 1780 if (!(BGE_IS_5705_PLUS(sc))) 1781 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1782 1783 /* Turn on send BD completion state machine */ 1784 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1785 1786 /* Turn on send data completion state machine */ 1787 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1788 1789 /* Turn on send data initiator state machine */ 1790 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1791 1792 /* Turn on send BD initiator state machine */ 1793 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1794 1795 /* Turn on send BD selector state machine */ 1796 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1797 1798 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1799 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1800 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 1801 1802 /* ack/clear link change events */ 1803 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1804 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1805 BGE_MACSTAT_LINK_CHANGED); 1806 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1807 1808 /* Enable PHY auto polling (for MII/GMII only) */ 1809 if (sc->bge_flags & BGE_FLAG_TBI) { 1810 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1811 } else { 1812 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 1813 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1814 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 1815 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1816 BGE_EVTENB_MI_INTERRUPT); 1817 } 1818 1819 /* 1820 * Clear any pending link state attention. 1821 * Otherwise some link state change events may be lost until attention 1822 * is cleared by bge_intr() -> bge_link_upd() sequence. 1823 * It's not necessary on newer BCM chips - perhaps enabling link 1824 * state change attentions implies clearing pending attention. 1825 */ 1826 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1827 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1828 BGE_MACSTAT_LINK_CHANGED); 1829 1830 /* Enable link state change attentions. */ 1831 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1832 1833 return (0); 1834 } 1835 1836 const struct bge_revision * 1837 bge_lookup_rev(uint32_t chipid) 1838 { 1839 const struct bge_revision *br; 1840 1841 for (br = bge_revisions; br->br_name != NULL; br++) { 1842 if (br->br_chipid == chipid) 1843 return (br); 1844 } 1845 1846 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1847 if (br->br_chipid == BGE_ASICREV(chipid)) 1848 return (br); 1849 } 1850 1851 return (NULL); 1852 } 1853 1854 const struct bge_vendor * 1855 bge_lookup_vendor(uint16_t vid) 1856 { 1857 const struct bge_vendor *v; 1858 1859 for (v = bge_vendors; v->v_name != NULL; v++) 1860 if (v->v_id == vid) 1861 return (v); 1862 1863 panic("%s: unknown vendor %d", __func__, vid); 1864 return (NULL); 1865 } 1866 1867 /* 1868 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1869 * against our list and return its name if we find a match. 1870 * 1871 * Note that since the Broadcom controller contains VPD support, we 1872 * try to get the device name string from the controller itself instead 1873 * of the compiled-in string. It guarantees we'll always announce the 1874 * right product name. We fall back to the compiled-in string when 1875 * VPD is unavailable or corrupt. 1876 */ 1877 static int 1878 bge_probe(device_t dev) 1879 { 1880 const struct bge_type *t = bge_devs; 1881 struct bge_softc *sc = device_get_softc(dev); 1882 uint16_t vid, did; 1883 1884 sc->bge_dev = dev; 1885 vid = pci_get_vendor(dev); 1886 did = pci_get_device(dev); 1887 while(t->bge_vid != 0) { 1888 if ((vid == t->bge_vid) && (did == t->bge_did)) { 1889 char model[64], buf[96]; 1890 const struct bge_revision *br; 1891 const struct bge_vendor *v; 1892 uint32_t id; 1893 1894 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1895 BGE_PCIMISCCTL_ASICREV; 1896 br = bge_lookup_rev(id); 1897 v = bge_lookup_vendor(vid); 1898 { 1899 #if __FreeBSD_version > 700024 1900 const char *pname; 1901 1902 if (bge_has_eaddr(sc) && 1903 pci_get_vpd_ident(dev, &pname) == 0) 1904 snprintf(model, 64, "%s", pname); 1905 else 1906 #endif 1907 snprintf(model, 64, "%s %s", 1908 v->v_name, 1909 br != NULL ? br->br_name : 1910 "NetXtreme Ethernet Controller"); 1911 } 1912 snprintf(buf, 96, "%s, %sASIC rev. %#04x", model, 1913 br != NULL ? "" : "unknown ", id >> 16); 1914 device_set_desc_copy(dev, buf); 1915 if (pci_get_subvendor(dev) == DELL_VENDORID) 1916 sc->bge_flags |= BGE_FLAG_NO_3LED; 1917 if (did == BCOM_DEVICEID_BCM5755M) 1918 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM; 1919 return (0); 1920 } 1921 t++; 1922 } 1923 1924 return (ENXIO); 1925 } 1926 1927 static void 1928 bge_dma_free(struct bge_softc *sc) 1929 { 1930 int i; 1931 1932 /* Destroy DMA maps for RX buffers. */ 1933 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1934 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1935 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1936 sc->bge_cdata.bge_rx_std_dmamap[i]); 1937 } 1938 1939 /* Destroy DMA maps for jumbo RX buffers. */ 1940 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1941 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1942 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1943 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1944 } 1945 1946 /* Destroy DMA maps for TX buffers. */ 1947 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1948 if (sc->bge_cdata.bge_tx_dmamap[i]) 1949 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1950 sc->bge_cdata.bge_tx_dmamap[i]); 1951 } 1952 1953 if (sc->bge_cdata.bge_mtag) 1954 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1955 1956 1957 /* Destroy standard RX ring. */ 1958 if (sc->bge_cdata.bge_rx_std_ring_map) 1959 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1960 sc->bge_cdata.bge_rx_std_ring_map); 1961 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 1962 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1963 sc->bge_ldata.bge_rx_std_ring, 1964 sc->bge_cdata.bge_rx_std_ring_map); 1965 1966 if (sc->bge_cdata.bge_rx_std_ring_tag) 1967 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1968 1969 /* Destroy jumbo RX ring. */ 1970 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 1971 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1972 sc->bge_cdata.bge_rx_jumbo_ring_map); 1973 1974 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 1975 sc->bge_ldata.bge_rx_jumbo_ring) 1976 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1977 sc->bge_ldata.bge_rx_jumbo_ring, 1978 sc->bge_cdata.bge_rx_jumbo_ring_map); 1979 1980 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1981 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1982 1983 /* Destroy RX return ring. */ 1984 if (sc->bge_cdata.bge_rx_return_ring_map) 1985 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1986 sc->bge_cdata.bge_rx_return_ring_map); 1987 1988 if (sc->bge_cdata.bge_rx_return_ring_map && 1989 sc->bge_ldata.bge_rx_return_ring) 1990 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1991 sc->bge_ldata.bge_rx_return_ring, 1992 sc->bge_cdata.bge_rx_return_ring_map); 1993 1994 if (sc->bge_cdata.bge_rx_return_ring_tag) 1995 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1996 1997 /* Destroy TX ring. */ 1998 if (sc->bge_cdata.bge_tx_ring_map) 1999 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2000 sc->bge_cdata.bge_tx_ring_map); 2001 2002 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2003 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2004 sc->bge_ldata.bge_tx_ring, 2005 sc->bge_cdata.bge_tx_ring_map); 2006 2007 if (sc->bge_cdata.bge_tx_ring_tag) 2008 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2009 2010 /* Destroy status block. */ 2011 if (sc->bge_cdata.bge_status_map) 2012 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2013 sc->bge_cdata.bge_status_map); 2014 2015 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2016 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2017 sc->bge_ldata.bge_status_block, 2018 sc->bge_cdata.bge_status_map); 2019 2020 if (sc->bge_cdata.bge_status_tag) 2021 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2022 2023 /* Destroy statistics block. */ 2024 if (sc->bge_cdata.bge_stats_map) 2025 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2026 sc->bge_cdata.bge_stats_map); 2027 2028 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2029 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2030 sc->bge_ldata.bge_stats, 2031 sc->bge_cdata.bge_stats_map); 2032 2033 if (sc->bge_cdata.bge_stats_tag) 2034 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2035 2036 /* Destroy the parent tag. */ 2037 if (sc->bge_cdata.bge_parent_tag) 2038 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2039 } 2040 2041 static int 2042 bge_dma_alloc(device_t dev) 2043 { 2044 struct bge_dmamap_arg ctx; 2045 struct bge_softc *sc; 2046 int i, error; 2047 2048 sc = device_get_softc(dev); 2049 2050 /* 2051 * Allocate the parent bus DMA tag appropriate for PCI. 2052 */ 2053 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2054 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2055 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2056 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2057 2058 if (error != 0) { 2059 device_printf(sc->bge_dev, 2060 "could not allocate parent dma tag\n"); 2061 return (ENOMEM); 2062 } 2063 2064 /* 2065 * Create tag for mbufs. 2066 */ 2067 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 2068 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2069 NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES, 2070 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag); 2071 2072 if (error) { 2073 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2074 return (ENOMEM); 2075 } 2076 2077 /* Create DMA maps for RX buffers. */ 2078 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2079 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 2080 &sc->bge_cdata.bge_rx_std_dmamap[i]); 2081 if (error) { 2082 device_printf(sc->bge_dev, 2083 "can't create DMA map for RX\n"); 2084 return (ENOMEM); 2085 } 2086 } 2087 2088 /* Create DMA maps for TX buffers. */ 2089 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2090 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 2091 &sc->bge_cdata.bge_tx_dmamap[i]); 2092 if (error) { 2093 device_printf(sc->bge_dev, 2094 "can't create DMA map for RX\n"); 2095 return (ENOMEM); 2096 } 2097 } 2098 2099 /* Create tag for standard RX ring. */ 2100 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2101 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2102 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 2103 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 2104 2105 if (error) { 2106 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2107 return (ENOMEM); 2108 } 2109 2110 /* Allocate DMA'able memory for standard RX ring. */ 2111 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 2112 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 2113 &sc->bge_cdata.bge_rx_std_ring_map); 2114 if (error) 2115 return (ENOMEM); 2116 2117 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 2118 2119 /* Load the address of the standard RX ring. */ 2120 ctx.bge_maxsegs = 1; 2121 ctx.sc = sc; 2122 2123 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 2124 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 2125 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2126 2127 if (error) 2128 return (ENOMEM); 2129 2130 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 2131 2132 /* Create tags for jumbo mbufs. */ 2133 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2134 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2135 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2136 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 2137 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2138 if (error) { 2139 device_printf(sc->bge_dev, 2140 "could not allocate jumbo dma tag\n"); 2141 return (ENOMEM); 2142 } 2143 2144 /* Create tag for jumbo RX ring. */ 2145 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2146 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2147 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2148 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2149 2150 if (error) { 2151 device_printf(sc->bge_dev, 2152 "could not allocate jumbo ring dma tag\n"); 2153 return (ENOMEM); 2154 } 2155 2156 /* Allocate DMA'able memory for jumbo RX ring. */ 2157 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2158 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, 2159 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2160 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2161 if (error) 2162 return (ENOMEM); 2163 2164 /* Load the address of the jumbo RX ring. */ 2165 ctx.bge_maxsegs = 1; 2166 ctx.sc = sc; 2167 2168 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2169 sc->bge_cdata.bge_rx_jumbo_ring_map, 2170 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2171 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2172 2173 if (error) 2174 return (ENOMEM); 2175 2176 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2177 2178 /* Create DMA maps for jumbo RX buffers. */ 2179 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2180 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2181 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2182 if (error) { 2183 device_printf(sc->bge_dev, 2184 "can't create DMA map for jumbo RX\n"); 2185 return (ENOMEM); 2186 } 2187 } 2188 2189 } 2190 2191 /* Create tag for RX return ring. */ 2192 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2193 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2194 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2195 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2196 2197 if (error) { 2198 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2199 return (ENOMEM); 2200 } 2201 2202 /* Allocate DMA'able memory for RX return ring. */ 2203 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2204 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2205 &sc->bge_cdata.bge_rx_return_ring_map); 2206 if (error) 2207 return (ENOMEM); 2208 2209 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2210 BGE_RX_RTN_RING_SZ(sc)); 2211 2212 /* Load the address of the RX return ring. */ 2213 ctx.bge_maxsegs = 1; 2214 ctx.sc = sc; 2215 2216 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2217 sc->bge_cdata.bge_rx_return_ring_map, 2218 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2219 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2220 2221 if (error) 2222 return (ENOMEM); 2223 2224 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2225 2226 /* Create tag for TX ring. */ 2227 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2228 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2229 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2230 &sc->bge_cdata.bge_tx_ring_tag); 2231 2232 if (error) { 2233 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2234 return (ENOMEM); 2235 } 2236 2237 /* Allocate DMA'able memory for TX ring. */ 2238 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2239 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2240 &sc->bge_cdata.bge_tx_ring_map); 2241 if (error) 2242 return (ENOMEM); 2243 2244 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2245 2246 /* Load the address of the TX ring. */ 2247 ctx.bge_maxsegs = 1; 2248 ctx.sc = sc; 2249 2250 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2251 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2252 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2253 2254 if (error) 2255 return (ENOMEM); 2256 2257 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2258 2259 /* Create tag for status block. */ 2260 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2261 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2262 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 2263 NULL, NULL, &sc->bge_cdata.bge_status_tag); 2264 2265 if (error) { 2266 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2267 return (ENOMEM); 2268 } 2269 2270 /* Allocate DMA'able memory for status block. */ 2271 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2272 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2273 &sc->bge_cdata.bge_status_map); 2274 if (error) 2275 return (ENOMEM); 2276 2277 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2278 2279 /* Load the address of the status block. */ 2280 ctx.sc = sc; 2281 ctx.bge_maxsegs = 1; 2282 2283 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2284 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2285 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2286 2287 if (error) 2288 return (ENOMEM); 2289 2290 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2291 2292 /* Create tag for statistics block. */ 2293 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2294 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2295 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2296 &sc->bge_cdata.bge_stats_tag); 2297 2298 if (error) { 2299 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2300 return (ENOMEM); 2301 } 2302 2303 /* Allocate DMA'able memory for statistics block. */ 2304 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2305 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2306 &sc->bge_cdata.bge_stats_map); 2307 if (error) 2308 return (ENOMEM); 2309 2310 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2311 2312 /* Load the address of the statstics block. */ 2313 ctx.sc = sc; 2314 ctx.bge_maxsegs = 1; 2315 2316 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2317 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2318 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2319 2320 if (error) 2321 return (ENOMEM); 2322 2323 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2324 2325 return (0); 2326 } 2327 2328 #if __FreeBSD_version > 602105 2329 /* 2330 * Return true if this device has more than one port. 2331 */ 2332 static int 2333 bge_has_multiple_ports(struct bge_softc *sc) 2334 { 2335 device_t dev = sc->bge_dev; 2336 u_int b, s, f, fscan; 2337 2338 b = pci_get_bus(dev); 2339 s = pci_get_slot(dev); 2340 f = pci_get_function(dev); 2341 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2342 if (fscan != f && pci_find_bsf(b, s, fscan) != NULL) 2343 return (1); 2344 return (0); 2345 } 2346 2347 /* 2348 * Return true if MSI can be used with this device. 2349 */ 2350 static int 2351 bge_can_use_msi(struct bge_softc *sc) 2352 { 2353 int can_use_msi = 0; 2354 2355 switch (sc->bge_asicrev) { 2356 case BGE_ASICREV_BCM5714_A0: 2357 case BGE_ASICREV_BCM5714: 2358 /* 2359 * Apparently, MSI doesn't work when these chips are 2360 * configured in single-port mode. 2361 */ 2362 if (bge_has_multiple_ports(sc)) 2363 can_use_msi = 1; 2364 break; 2365 case BGE_ASICREV_BCM5750: 2366 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2367 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2368 can_use_msi = 1; 2369 break; 2370 default: 2371 if (BGE_IS_575X_PLUS(sc)) 2372 can_use_msi = 1; 2373 } 2374 return (can_use_msi); 2375 } 2376 #endif 2377 2378 static int 2379 bge_attach(device_t dev) 2380 { 2381 struct ifnet *ifp; 2382 struct bge_softc *sc; 2383 uint32_t hwcfg = 0; 2384 u_char eaddr[ETHER_ADDR_LEN]; 2385 int error, reg, rid, trys; 2386 2387 sc = device_get_softc(dev); 2388 sc->bge_dev = dev; 2389 2390 /* 2391 * Map control/status registers. 2392 */ 2393 pci_enable_busmaster(dev); 2394 2395 rid = BGE_PCI_BAR0; 2396 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2397 RF_ACTIVE | PCI_RF_DENSE); 2398 2399 if (sc->bge_res == NULL) { 2400 device_printf (sc->bge_dev, "couldn't map memory\n"); 2401 error = ENXIO; 2402 goto fail; 2403 } 2404 2405 sc->bge_btag = rman_get_bustag(sc->bge_res); 2406 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2407 2408 /* Save various chip information. */ 2409 sc->bge_chipid = 2410 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2411 BGE_PCIMISCCTL_ASICREV; 2412 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2413 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2414 2415 /* 2416 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2417 * 5705 A0 and A1 chips. 2418 */ 2419 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 2420 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2421 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2422 sc->bge_chipid != BGE_CHIPID_BCM5705_A1) 2423 sc->bge_flags |= BGE_FLAG_WIRESPEED; 2424 2425 if (bge_has_eaddr(sc)) 2426 sc->bge_flags |= BGE_FLAG_EADDR; 2427 2428 /* Save chipset family. */ 2429 switch (sc->bge_asicrev) { 2430 case BGE_ASICREV_BCM5700: 2431 case BGE_ASICREV_BCM5701: 2432 case BGE_ASICREV_BCM5703: 2433 case BGE_ASICREV_BCM5704: 2434 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2435 break; 2436 case BGE_ASICREV_BCM5714_A0: 2437 case BGE_ASICREV_BCM5780: 2438 case BGE_ASICREV_BCM5714: 2439 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; 2440 /* FALLTHRU */ 2441 case BGE_ASICREV_BCM5750: 2442 case BGE_ASICREV_BCM5752: 2443 case BGE_ASICREV_BCM5755: 2444 case BGE_ASICREV_BCM5787: 2445 case BGE_ASICREV_BCM5906: 2446 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2447 /* FALLTHRU */ 2448 case BGE_ASICREV_BCM5705: 2449 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2450 break; 2451 } 2452 2453 /* Set various bug flags. */ 2454 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2455 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2456 sc->bge_flags |= BGE_FLAG_CRC_BUG; 2457 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2458 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2459 sc->bge_flags |= BGE_FLAG_ADC_BUG; 2460 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2461 sc->bge_flags |= BGE_FLAG_5704_A0_BUG; 2462 if (BGE_IS_5705_PLUS(sc) && 2463 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 2464 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2465 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2466 if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0) 2467 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2468 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 2469 sc->bge_flags |= BGE_FLAG_BER_BUG; 2470 } 2471 2472 /* 2473 * Check if this is a PCI-X or PCI Express device. 2474 */ 2475 #if __FreeBSD_version > 602101 2476 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 2477 /* 2478 * Found a PCI Express capabilities register, this 2479 * must be a PCI Express device. 2480 */ 2481 if (reg != 0) { 2482 sc->bge_flags |= BGE_FLAG_PCIE; 2483 #else 2484 if (BGE_IS_5705_PLUS(sc)) { 2485 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4); 2486 if ((reg & 0xFF) == BGE_PCIE_CAPID) { 2487 sc->bge_flags |= BGE_FLAG_PCIE; 2488 reg = BGE_PCIE_CAPID; 2489 #endif 2490 bge_set_max_readrq(sc, reg); 2491 } 2492 } else { 2493 /* 2494 * Check if the device is in PCI-X Mode. 2495 * (This bit is not valid on PCI Express controllers.) 2496 */ 2497 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2498 BGE_PCISTATE_PCI_BUSMODE) == 0) 2499 sc->bge_flags |= BGE_FLAG_PCIX; 2500 } 2501 2502 #if __FreeBSD_version > 602105 2503 { 2504 int msicount; 2505 2506 /* 2507 * Allocate the interrupt, using MSI if possible. These devices 2508 * support 8 MSI messages, but only the first one is used in 2509 * normal operation. 2510 */ 2511 if (bge_can_use_msi(sc)) { 2512 msicount = pci_msi_count(dev); 2513 if (msicount > 1) 2514 msicount = 1; 2515 } else 2516 msicount = 0; 2517 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2518 rid = 1; 2519 sc->bge_flags |= BGE_FLAG_MSI; 2520 } else 2521 rid = 0; 2522 } 2523 #else 2524 rid = 0; 2525 #endif 2526 2527 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2528 RF_SHAREABLE | RF_ACTIVE); 2529 2530 if (sc->bge_irq == NULL) { 2531 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2532 error = ENXIO; 2533 goto fail; 2534 } 2535 2536 if (bootverbose) 2537 device_printf(dev, 2538 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", 2539 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, 2540 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" : 2541 ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI")); 2542 2543 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2544 2545 /* Try to reset the chip. */ 2546 if (bge_reset(sc)) { 2547 device_printf(sc->bge_dev, "chip reset failed\n"); 2548 error = ENXIO; 2549 goto fail; 2550 } 2551 2552 sc->bge_asf_mode = 0; 2553 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2554 == BGE_MAGIC_NUMBER)) { 2555 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2556 & BGE_HWCFG_ASF) { 2557 sc->bge_asf_mode |= ASF_ENABLE; 2558 sc->bge_asf_mode |= ASF_STACKUP; 2559 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) { 2560 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2561 } 2562 } 2563 } 2564 2565 /* Try to reset the chip again the nice way. */ 2566 bge_stop_fw(sc); 2567 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2568 if (bge_reset(sc)) { 2569 device_printf(sc->bge_dev, "chip reset failed\n"); 2570 error = ENXIO; 2571 goto fail; 2572 } 2573 2574 bge_sig_legacy(sc, BGE_RESET_STOP); 2575 bge_sig_post_reset(sc, BGE_RESET_STOP); 2576 2577 if (bge_chipinit(sc)) { 2578 device_printf(sc->bge_dev, "chip initialization failed\n"); 2579 error = ENXIO; 2580 goto fail; 2581 } 2582 2583 error = bge_get_eaddr(sc, eaddr); 2584 if (error) { 2585 device_printf(sc->bge_dev, 2586 "failed to read station address\n"); 2587 error = ENXIO; 2588 goto fail; 2589 } 2590 2591 /* 5705 limits RX return ring to 512 entries. */ 2592 if (BGE_IS_5705_PLUS(sc)) 2593 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2594 else 2595 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2596 2597 if (bge_dma_alloc(dev)) { 2598 device_printf(sc->bge_dev, 2599 "failed to allocate DMA resources\n"); 2600 error = ENXIO; 2601 goto fail; 2602 } 2603 2604 /* Set default tuneable values. */ 2605 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2606 sc->bge_rx_coal_ticks = 150; 2607 sc->bge_tx_coal_ticks = 150; 2608 sc->bge_rx_max_coal_bds = 10; 2609 sc->bge_tx_max_coal_bds = 10; 2610 2611 /* Set up ifnet structure */ 2612 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2613 if (ifp == NULL) { 2614 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2615 error = ENXIO; 2616 goto fail; 2617 } 2618 ifp->if_softc = sc; 2619 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2620 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2621 ifp->if_ioctl = bge_ioctl; 2622 ifp->if_start = bge_start; 2623 ifp->if_init = bge_init; 2624 ifp->if_mtu = ETHERMTU; 2625 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 2626 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2627 IFQ_SET_READY(&ifp->if_snd); 2628 ifp->if_hwassist = BGE_CSUM_FEATURES; 2629 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2630 IFCAP_VLAN_MTU; 2631 #ifdef IFCAP_VLAN_HWCSUM 2632 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 2633 #endif 2634 ifp->if_capenable = ifp->if_capabilities; 2635 #ifdef DEVICE_POLLING 2636 ifp->if_capabilities |= IFCAP_POLLING; 2637 #endif 2638 2639 /* 2640 * 5700 B0 chips do not support checksumming correctly due 2641 * to hardware bugs. 2642 */ 2643 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2644 ifp->if_capabilities &= ~IFCAP_HWCSUM; 2645 ifp->if_capenable &= IFCAP_HWCSUM; 2646 ifp->if_hwassist = 0; 2647 } 2648 2649 /* 2650 * Figure out what sort of media we have by checking the 2651 * hardware config word in the first 32k of NIC internal memory, 2652 * or fall back to examining the EEPROM if necessary. 2653 * Note: on some BCM5700 cards, this value appears to be unset. 2654 * If that's the case, we have to rely on identifying the NIC 2655 * by its PCI subsystem ID, as we do below for the SysKonnect 2656 * SK-9D41. 2657 */ 2658 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2659 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2660 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 2661 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2662 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2663 sizeof(hwcfg))) { 2664 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2665 error = ENXIO; 2666 goto fail; 2667 } 2668 hwcfg = ntohl(hwcfg); 2669 } 2670 2671 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2672 sc->bge_flags |= BGE_FLAG_TBI; 2673 2674 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2675 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2676 sc->bge_flags |= BGE_FLAG_TBI; 2677 2678 if (sc->bge_flags & BGE_FLAG_TBI) { 2679 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2680 bge_ifmedia_sts); 2681 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 2682 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2683 0, NULL); 2684 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2685 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2686 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2687 } else { 2688 /* 2689 * Do transceiver setup and tell the firmware the 2690 * driver is down so we can try to get access the 2691 * probe if ASF is running. Retry a couple of times 2692 * if we get a conflict with the ASF firmware accessing 2693 * the PHY. 2694 */ 2695 trys = 0; 2696 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2697 again: 2698 bge_asf_driver_up(sc); 2699 2700 if (mii_phy_probe(dev, &sc->bge_miibus, 2701 bge_ifmedia_upd, bge_ifmedia_sts)) { 2702 if (trys++ < 4) { 2703 device_printf(sc->bge_dev, "Try again\n"); 2704 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 2705 BMCR_RESET); 2706 goto again; 2707 } 2708 2709 device_printf(sc->bge_dev, "MII without any PHY!\n"); 2710 error = ENXIO; 2711 goto fail; 2712 } 2713 2714 /* 2715 * Now tell the firmware we are going up after probing the PHY 2716 */ 2717 if (sc->bge_asf_mode & ASF_STACKUP) 2718 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2719 } 2720 2721 /* 2722 * When using the BCM5701 in PCI-X mode, data corruption has 2723 * been observed in the first few bytes of some received packets. 2724 * Aligning the packet buffer in memory eliminates the corruption. 2725 * Unfortunately, this misaligns the packet payloads. On platforms 2726 * which do not support unaligned accesses, we will realign the 2727 * payloads by copying the received packets. 2728 */ 2729 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2730 sc->bge_flags & BGE_FLAG_PCIX) 2731 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2732 2733 /* 2734 * Call MI attach routine. 2735 */ 2736 ether_ifattach(ifp, eaddr); 2737 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 2738 2739 /* 2740 * Hookup IRQ last. 2741 */ 2742 #if __FreeBSD_version > 700030 2743 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2744 NULL, bge_intr, sc, &sc->bge_intrhand); 2745 #else 2746 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2747 bge_intr, sc, &sc->bge_intrhand); 2748 #endif 2749 2750 if (error) { 2751 bge_detach(dev); 2752 device_printf(sc->bge_dev, "couldn't set up irq\n"); 2753 } 2754 2755 bge_add_sysctls(sc); 2756 2757 return (0); 2758 2759 fail: 2760 bge_release_resources(sc); 2761 2762 return (error); 2763 } 2764 2765 static int 2766 bge_detach(device_t dev) 2767 { 2768 struct bge_softc *sc; 2769 struct ifnet *ifp; 2770 2771 sc = device_get_softc(dev); 2772 ifp = sc->bge_ifp; 2773 2774 #ifdef DEVICE_POLLING 2775 if (ifp->if_capenable & IFCAP_POLLING) 2776 ether_poll_deregister(ifp); 2777 #endif 2778 2779 BGE_LOCK(sc); 2780 bge_stop(sc); 2781 bge_reset(sc); 2782 BGE_UNLOCK(sc); 2783 2784 callout_drain(&sc->bge_stat_ch); 2785 2786 ether_ifdetach(ifp); 2787 2788 if (sc->bge_flags & BGE_FLAG_TBI) { 2789 ifmedia_removeall(&sc->bge_ifmedia); 2790 } else { 2791 bus_generic_detach(dev); 2792 device_delete_child(dev, sc->bge_miibus); 2793 } 2794 2795 bge_release_resources(sc); 2796 2797 return (0); 2798 } 2799 2800 static void 2801 bge_release_resources(struct bge_softc *sc) 2802 { 2803 device_t dev; 2804 2805 dev = sc->bge_dev; 2806 2807 if (sc->bge_intrhand != NULL) 2808 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2809 2810 if (sc->bge_irq != NULL) 2811 bus_release_resource(dev, SYS_RES_IRQ, 2812 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 2813 2814 #if __FreeBSD_version > 602105 2815 if (sc->bge_flags & BGE_FLAG_MSI) 2816 pci_release_msi(dev); 2817 #endif 2818 2819 if (sc->bge_res != NULL) 2820 bus_release_resource(dev, SYS_RES_MEMORY, 2821 BGE_PCI_BAR0, sc->bge_res); 2822 2823 if (sc->bge_ifp != NULL) 2824 if_free(sc->bge_ifp); 2825 2826 bge_dma_free(sc); 2827 2828 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 2829 BGE_LOCK_DESTROY(sc); 2830 } 2831 2832 static int 2833 bge_reset(struct bge_softc *sc) 2834 { 2835 device_t dev; 2836 uint32_t cachesize, command, pcistate, reset, val; 2837 void (*write_op)(struct bge_softc *, int, int); 2838 int i; 2839 2840 dev = sc->bge_dev; 2841 2842 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 2843 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2844 if (sc->bge_flags & BGE_FLAG_PCIE) 2845 write_op = bge_writemem_direct; 2846 else 2847 write_op = bge_writemem_ind; 2848 } else 2849 write_op = bge_writereg_ind; 2850 2851 /* Save some important PCI state. */ 2852 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2853 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2854 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2855 2856 pci_write_config(dev, BGE_PCI_MISC_CTL, 2857 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2858 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2859 2860 /* Disable fastboot on controllers that support it. */ 2861 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 2862 sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2863 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2864 if (bootverbose) 2865 device_printf(sc->bge_dev, "Disabling fastboot\n"); 2866 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 2867 } 2868 2869 /* 2870 * Write the magic number to SRAM at offset 0xB50. 2871 * When firmware finishes its initialization it will 2872 * write ~BGE_MAGIC_NUMBER to the same location. 2873 */ 2874 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2875 2876 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 2877 2878 /* XXX: Broadcom Linux driver. */ 2879 if (sc->bge_flags & BGE_FLAG_PCIE) { 2880 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 2881 CSR_WRITE_4(sc, 0x7E2C, 0x20); 2882 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2883 /* Prevent PCIE link training during global reset */ 2884 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2885 reset |= 1 << 29; 2886 } 2887 } 2888 2889 /* 2890 * Set GPHY Power Down Override to leave GPHY 2891 * powered up in D0 uninitialized. 2892 */ 2893 if (BGE_IS_5705_PLUS(sc)) 2894 reset |= 0x04000000; 2895 2896 /* Issue global reset */ 2897 write_op(sc, BGE_MISC_CFG, reset); 2898 2899 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2900 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2901 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2902 val | BGE_VCPU_STATUS_DRV_RESET); 2903 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2904 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2905 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2906 } 2907 2908 DELAY(1000); 2909 2910 /* XXX: Broadcom Linux driver. */ 2911 if (sc->bge_flags & BGE_FLAG_PCIE) { 2912 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2913 DELAY(500000); /* wait for link training to complete */ 2914 val = pci_read_config(dev, 0xC4, 4); 2915 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 2916 } 2917 /* 2918 * Set PCIE max payload size to 128 bytes and clear error 2919 * status. 2920 */ 2921 pci_write_config(dev, 0xD8, 0xF5000, 4); 2922 } 2923 2924 /* Reset some of the PCI state that got zapped by reset. */ 2925 pci_write_config(dev, BGE_PCI_MISC_CTL, 2926 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2927 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2928 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2929 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2930 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2931 2932 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 2933 if (BGE_IS_5714_FAMILY(sc)) { 2934 /* This chip disables MSI on reset. */ 2935 if (sc->bge_flags & BGE_FLAG_MSI) { 2936 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2); 2937 pci_write_config(dev, BGE_PCI_MSI_CTL, 2938 val | PCIM_MSICTRL_MSI_ENABLE, 2); 2939 val = CSR_READ_4(sc, BGE_MSI_MODE); 2940 CSR_WRITE_4(sc, BGE_MSI_MODE, 2941 val | BGE_MSIMODE_ENABLE); 2942 } 2943 val = CSR_READ_4(sc, BGE_MARB_MODE); 2944 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 2945 } else 2946 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2947 2948 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2949 for (i = 0; i < BGE_TIMEOUT; i++) { 2950 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2951 if (val & BGE_VCPU_STATUS_INIT_DONE) 2952 break; 2953 DELAY(100); 2954 } 2955 if (i == BGE_TIMEOUT) { 2956 device_printf(sc->bge_dev, "reset timed out\n"); 2957 return (1); 2958 } 2959 } else { 2960 /* 2961 * Poll until we see the 1's complement of the magic number. 2962 * This indicates that the firmware initialization is complete. 2963 * We expect this to fail if no chip containing the Ethernet 2964 * address is fitted though. 2965 */ 2966 for (i = 0; i < BGE_TIMEOUT; i++) { 2967 DELAY(10); 2968 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2969 if (val == ~BGE_MAGIC_NUMBER) 2970 break; 2971 } 2972 2973 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 2974 device_printf(sc->bge_dev, "firmware handshake timed out, " 2975 "found 0x%08x\n", val); 2976 } 2977 2978 /* 2979 * XXX Wait for the value of the PCISTATE register to 2980 * return to its original pre-reset state. This is a 2981 * fairly good indicator of reset completion. If we don't 2982 * wait for the reset to fully complete, trying to read 2983 * from the device's non-PCI registers may yield garbage 2984 * results. 2985 */ 2986 for (i = 0; i < BGE_TIMEOUT; i++) { 2987 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2988 break; 2989 DELAY(10); 2990 } 2991 2992 if (sc->bge_flags & BGE_FLAG_PCIE) { 2993 reset = bge_readmem_ind(sc, 0x7C00); 2994 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25)); 2995 } 2996 2997 /* Fix up byte swapping. */ 2998 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 2999 BGE_MODECTL_BYTESWAP_DATA); 3000 3001 /* Tell the ASF firmware we are up */ 3002 if (sc->bge_asf_mode & ASF_STACKUP) 3003 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3004 3005 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3006 3007 /* 3008 * The 5704 in TBI mode apparently needs some special 3009 * adjustment to insure the SERDES drive level is set 3010 * to 1.2V. 3011 */ 3012 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 3013 sc->bge_flags & BGE_FLAG_TBI) { 3014 val = CSR_READ_4(sc, BGE_SERDES_CFG); 3015 val = (val & ~0xFFF) | 0x880; 3016 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 3017 } 3018 3019 /* XXX: Broadcom Linux driver. */ 3020 if (sc->bge_flags & BGE_FLAG_PCIE && 3021 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3022 val = CSR_READ_4(sc, 0x7C00); 3023 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 3024 } 3025 DELAY(10000); 3026 3027 return(0); 3028 } 3029 3030 /* 3031 * Frame reception handling. This is called if there's a frame 3032 * on the receive return list. 3033 * 3034 * Note: we have to be able to handle two possibilities here: 3035 * 1) the frame is from the jumbo receive ring 3036 * 2) the frame is from the standard receive ring 3037 */ 3038 3039 static void 3040 bge_rxeof(struct bge_softc *sc) 3041 { 3042 struct ifnet *ifp; 3043 int stdcnt = 0, jumbocnt = 0; 3044 3045 BGE_LOCK_ASSERT(sc); 3046 3047 /* Nothing to do. */ 3048 if (sc->bge_rx_saved_considx == 3049 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) 3050 return; 3051 3052 ifp = sc->bge_ifp; 3053 3054 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3055 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3056 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3057 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 3058 if (BGE_IS_JUMBO_CAPABLE(sc)) 3059 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3060 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD); 3061 3062 while(sc->bge_rx_saved_considx != 3063 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 3064 struct bge_rx_bd *cur_rx; 3065 uint32_t rxidx; 3066 struct mbuf *m = NULL; 3067 uint16_t vlan_tag = 0; 3068 int have_tag = 0; 3069 3070 #ifdef DEVICE_POLLING 3071 if (ifp->if_capenable & IFCAP_POLLING) { 3072 if (sc->rxcycles <= 0) 3073 break; 3074 sc->rxcycles--; 3075 } 3076 #endif 3077 3078 cur_rx = 3079 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 3080 3081 rxidx = cur_rx->bge_idx; 3082 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 3083 3084 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3085 have_tag = 1; 3086 vlan_tag = cur_rx->bge_vlan_tag; 3087 } 3088 3089 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3090 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3091 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 3092 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 3093 BUS_DMASYNC_POSTREAD); 3094 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 3095 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 3096 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3097 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3098 jumbocnt++; 3099 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3100 ifp->if_ierrors++; 3101 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3102 continue; 3103 } 3104 if (bge_newbuf_jumbo(sc, 3105 sc->bge_jumbo, NULL) == ENOBUFS) { 3106 ifp->if_ierrors++; 3107 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3108 continue; 3109 } 3110 } else { 3111 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3112 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 3113 sc->bge_cdata.bge_rx_std_dmamap[rxidx], 3114 BUS_DMASYNC_POSTREAD); 3115 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 3116 sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 3117 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3118 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3119 stdcnt++; 3120 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3121 ifp->if_ierrors++; 3122 bge_newbuf_std(sc, sc->bge_std, m); 3123 continue; 3124 } 3125 if (bge_newbuf_std(sc, sc->bge_std, 3126 NULL) == ENOBUFS) { 3127 ifp->if_ierrors++; 3128 bge_newbuf_std(sc, sc->bge_std, m); 3129 continue; 3130 } 3131 } 3132 3133 ifp->if_ipackets++; 3134 #ifndef __NO_STRICT_ALIGNMENT 3135 /* 3136 * For architectures with strict alignment we must make sure 3137 * the payload is aligned. 3138 */ 3139 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3140 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3141 cur_rx->bge_len); 3142 m->m_data += ETHER_ALIGN; 3143 } 3144 #endif 3145 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3146 m->m_pkthdr.rcvif = ifp; 3147 3148 if (ifp->if_capenable & IFCAP_RXCSUM) { 3149 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3150 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3151 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 3152 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3153 } 3154 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3155 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 3156 m->m_pkthdr.csum_data = 3157 cur_rx->bge_tcp_udp_csum; 3158 m->m_pkthdr.csum_flags |= 3159 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 3160 } 3161 } 3162 3163 /* 3164 * If we received a packet with a vlan tag, 3165 * attach that information to the packet. 3166 */ 3167 if (have_tag) { 3168 #if __FreeBSD_version > 700022 3169 m->m_pkthdr.ether_vtag = vlan_tag; 3170 m->m_flags |= M_VLANTAG; 3171 #else 3172 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); 3173 if (m == NULL) 3174 continue; 3175 #endif 3176 } 3177 3178 BGE_UNLOCK(sc); 3179 (*ifp->if_input)(ifp, m); 3180 BGE_LOCK(sc); 3181 } 3182 3183 if (stdcnt > 0) 3184 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3185 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3186 3187 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) 3188 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3189 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3190 3191 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3192 if (stdcnt) 3193 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3194 if (jumbocnt) 3195 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3196 #ifdef notyet 3197 /* 3198 * This register wraps very quickly under heavy packet drops. 3199 * If you need correct statistics, you can enable this check. 3200 */ 3201 if (BGE_IS_5705_PLUS(sc)) 3202 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3203 #endif 3204 } 3205 3206 static void 3207 bge_txeof(struct bge_softc *sc) 3208 { 3209 struct bge_tx_bd *cur_tx = NULL; 3210 struct ifnet *ifp; 3211 3212 BGE_LOCK_ASSERT(sc); 3213 3214 /* Nothing to do. */ 3215 if (sc->bge_tx_saved_considx == 3216 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) 3217 return; 3218 3219 ifp = sc->bge_ifp; 3220 3221 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 3222 sc->bge_cdata.bge_tx_ring_map, 3223 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3224 /* 3225 * Go through our tx ring and free mbufs for those 3226 * frames that have been sent. 3227 */ 3228 while (sc->bge_tx_saved_considx != 3229 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 3230 uint32_t idx = 0; 3231 3232 idx = sc->bge_tx_saved_considx; 3233 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3234 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3235 ifp->if_opackets++; 3236 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3237 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 3238 sc->bge_cdata.bge_tx_dmamap[idx], 3239 BUS_DMASYNC_POSTWRITE); 3240 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 3241 sc->bge_cdata.bge_tx_dmamap[idx]); 3242 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3243 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3244 } 3245 sc->bge_txcnt--; 3246 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3247 } 3248 3249 if (cur_tx != NULL) 3250 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3251 if (sc->bge_txcnt == 0) 3252 sc->bge_timer = 0; 3253 } 3254 3255 #ifdef DEVICE_POLLING 3256 static void 3257 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3258 { 3259 struct bge_softc *sc = ifp->if_softc; 3260 uint32_t statusword; 3261 3262 BGE_LOCK(sc); 3263 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3264 BGE_UNLOCK(sc); 3265 return; 3266 } 3267 3268 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3269 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3270 3271 statusword = atomic_readandclear_32( 3272 &sc->bge_ldata.bge_status_block->bge_status); 3273 3274 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3275 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3276 3277 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3278 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3279 sc->bge_link_evt++; 3280 3281 if (cmd == POLL_AND_CHECK_STATUS) 3282 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3283 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3284 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3285 bge_link_upd(sc); 3286 3287 sc->rxcycles = count; 3288 bge_rxeof(sc); 3289 bge_txeof(sc); 3290 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3291 bge_start_locked(ifp); 3292 3293 BGE_UNLOCK(sc); 3294 } 3295 #endif /* DEVICE_POLLING */ 3296 3297 static void 3298 bge_intr(void *xsc) 3299 { 3300 struct bge_softc *sc; 3301 struct ifnet *ifp; 3302 uint32_t statusword; 3303 3304 sc = xsc; 3305 3306 BGE_LOCK(sc); 3307 3308 ifp = sc->bge_ifp; 3309 3310 #ifdef DEVICE_POLLING 3311 if (ifp->if_capenable & IFCAP_POLLING) { 3312 BGE_UNLOCK(sc); 3313 return; 3314 } 3315 #endif 3316 3317 /* 3318 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3319 * disable interrupts by writing nonzero like we used to, since with 3320 * our current organization this just gives complications and 3321 * pessimizations for re-enabling interrupts. We used to have races 3322 * instead of the necessary complications. Disabling interrupts 3323 * would just reduce the chance of a status update while we are 3324 * running (by switching to the interrupt-mode coalescence 3325 * parameters), but this chance is already very low so it is more 3326 * efficient to get another interrupt than prevent it. 3327 * 3328 * We do the ack first to ensure another interrupt if there is a 3329 * status update after the ack. We don't check for the status 3330 * changing later because it is more efficient to get another 3331 * interrupt than prevent it, not quite as above (not checking is 3332 * a smaller optimization than not toggling the interrupt enable, 3333 * since checking doesn't involve PCI accesses and toggling require 3334 * the status check). So toggling would probably be a pessimization 3335 * even with MSI. It would only be needed for using a task queue. 3336 */ 3337 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3338 3339 /* 3340 * Do the mandatory PCI flush as well as get the link status. 3341 */ 3342 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3343 3344 /* Make sure the descriptor ring indexes are coherent. */ 3345 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3346 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3347 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3348 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3349 3350 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3351 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3352 statusword || sc->bge_link_evt) 3353 bge_link_upd(sc); 3354 3355 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3356 /* Check RX return ring producer/consumer. */ 3357 bge_rxeof(sc); 3358 3359 /* Check TX ring producer/consumer. */ 3360 bge_txeof(sc); 3361 } 3362 3363 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3364 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3365 bge_start_locked(ifp); 3366 3367 BGE_UNLOCK(sc); 3368 } 3369 3370 static void 3371 bge_asf_driver_up(struct bge_softc *sc) 3372 { 3373 if (sc->bge_asf_mode & ASF_STACKUP) { 3374 /* Send ASF heartbeat aprox. every 2s */ 3375 if (sc->bge_asf_count) 3376 sc->bge_asf_count --; 3377 else { 3378 sc->bge_asf_count = 5; 3379 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3380 BGE_FW_DRV_ALIVE); 3381 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3382 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3383 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3384 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3385 } 3386 } 3387 } 3388 3389 static void 3390 bge_tick(void *xsc) 3391 { 3392 struct bge_softc *sc = xsc; 3393 struct mii_data *mii = NULL; 3394 3395 BGE_LOCK_ASSERT(sc); 3396 3397 /* Synchronize with possible callout reset/stop. */ 3398 if (callout_pending(&sc->bge_stat_ch) || 3399 !callout_active(&sc->bge_stat_ch)) 3400 return; 3401 3402 if (BGE_IS_5705_PLUS(sc)) 3403 bge_stats_update_regs(sc); 3404 else 3405 bge_stats_update(sc); 3406 3407 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 3408 mii = device_get_softc(sc->bge_miibus); 3409 /* 3410 * Do not touch PHY if we have link up. This could break 3411 * IPMI/ASF mode or produce extra input errors 3412 * (extra errors was reported for bcm5701 & bcm5704). 3413 */ 3414 if (!sc->bge_link) 3415 mii_tick(mii); 3416 } else { 3417 /* 3418 * Since in TBI mode auto-polling can't be used we should poll 3419 * link status manually. Here we register pending link event 3420 * and trigger interrupt. 3421 */ 3422 #ifdef DEVICE_POLLING 3423 /* In polling mode we poll link state in bge_poll(). */ 3424 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 3425 #endif 3426 { 3427 sc->bge_link_evt++; 3428 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3429 } 3430 } 3431 3432 bge_asf_driver_up(sc); 3433 bge_watchdog(sc); 3434 3435 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3436 } 3437 3438 static void 3439 bge_stats_update_regs(struct bge_softc *sc) 3440 { 3441 struct ifnet *ifp; 3442 3443 ifp = sc->bge_ifp; 3444 3445 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3446 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3447 3448 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3449 } 3450 3451 static void 3452 bge_stats_update(struct bge_softc *sc) 3453 { 3454 struct ifnet *ifp; 3455 bus_size_t stats; 3456 uint32_t cnt; /* current register value */ 3457 3458 ifp = sc->bge_ifp; 3459 3460 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3461 3462 #define READ_STAT(sc, stats, stat) \ 3463 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3464 3465 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 3466 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 3467 sc->bge_tx_collisions = cnt; 3468 3469 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 3470 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 3471 sc->bge_rx_discards = cnt; 3472 3473 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 3474 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 3475 sc->bge_tx_discards = cnt; 3476 3477 #undef READ_STAT 3478 } 3479 3480 /* 3481 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3482 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3483 * but when such padded frames employ the bge IP/TCP checksum offload, 3484 * the hardware checksum assist gives incorrect results (possibly 3485 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3486 * If we pad such runts with zeros, the onboard checksum comes out correct. 3487 */ 3488 static __inline int 3489 bge_cksum_pad(struct mbuf *m) 3490 { 3491 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 3492 struct mbuf *last; 3493 3494 /* If there's only the packet-header and we can pad there, use it. */ 3495 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 3496 M_TRAILINGSPACE(m) >= padlen) { 3497 last = m; 3498 } else { 3499 /* 3500 * Walk packet chain to find last mbuf. We will either 3501 * pad there, or append a new mbuf and pad it. 3502 */ 3503 for (last = m; last->m_next != NULL; last = last->m_next); 3504 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 3505 /* Allocate new empty mbuf, pad it. Compact later. */ 3506 struct mbuf *n; 3507 3508 MGET(n, M_DONTWAIT, MT_DATA); 3509 if (n == NULL) 3510 return (ENOBUFS); 3511 n->m_len = 0; 3512 last->m_next = n; 3513 last = n; 3514 } 3515 } 3516 3517 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 3518 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3519 last->m_len += padlen; 3520 m->m_pkthdr.len += padlen; 3521 3522 return (0); 3523 } 3524 3525 /* 3526 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3527 * pointers to descriptors. 3528 */ 3529 static int 3530 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 3531 { 3532 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3533 bus_dmamap_t map; 3534 struct bge_tx_bd *d; 3535 struct mbuf *m = *m_head; 3536 uint32_t idx = *txidx; 3537 uint16_t csum_flags; 3538 int nsegs, i, error; 3539 3540 csum_flags = 0; 3541 if (m->m_pkthdr.csum_flags) { 3542 if (m->m_pkthdr.csum_flags & CSUM_IP) 3543 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3544 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 3545 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3546 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 3547 (error = bge_cksum_pad(m)) != 0) { 3548 m_freem(m); 3549 *m_head = NULL; 3550 return (error); 3551 } 3552 } 3553 if (m->m_flags & M_LASTFRAG) 3554 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3555 else if (m->m_flags & M_FRAG) 3556 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3557 } 3558 3559 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3560 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs, 3561 &nsegs, BUS_DMA_NOWAIT); 3562 if (error == EFBIG) { 3563 m = m_defrag(m, M_DONTWAIT); 3564 if (m == NULL) { 3565 m_freem(*m_head); 3566 *m_head = NULL; 3567 return (ENOBUFS); 3568 } 3569 *m_head = m; 3570 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, 3571 segs, &nsegs, BUS_DMA_NOWAIT); 3572 if (error) { 3573 m_freem(m); 3574 *m_head = NULL; 3575 return (error); 3576 } 3577 } else if (error != 0) 3578 return (error); 3579 3580 /* 3581 * Sanity check: avoid coming within 16 descriptors 3582 * of the end of the ring. 3583 */ 3584 if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3585 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map); 3586 return (ENOBUFS); 3587 } 3588 3589 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE); 3590 3591 for (i = 0; ; i++) { 3592 d = &sc->bge_ldata.bge_tx_ring[idx]; 3593 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3594 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3595 d->bge_len = segs[i].ds_len; 3596 d->bge_flags = csum_flags; 3597 if (i == nsegs - 1) 3598 break; 3599 BGE_INC(idx, BGE_TX_RING_CNT); 3600 } 3601 3602 /* Mark the last segment as end of packet... */ 3603 d->bge_flags |= BGE_TXBDFLAG_END; 3604 3605 /* ... and put VLAN tag into first segment. */ 3606 d = &sc->bge_ldata.bge_tx_ring[*txidx]; 3607 #if __FreeBSD_version > 700022 3608 if (m->m_flags & M_VLANTAG) { 3609 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3610 d->bge_vlan_tag = m->m_pkthdr.ether_vtag; 3611 } else 3612 d->bge_vlan_tag = 0; 3613 #else 3614 { 3615 struct m_tag *mtag; 3616 3617 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { 3618 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3619 d->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3620 } else 3621 d->bge_vlan_tag = 0; 3622 } 3623 #endif 3624 3625 /* 3626 * Insure that the map for this transmission 3627 * is placed at the array index of the last descriptor 3628 * in this chain. 3629 */ 3630 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 3631 sc->bge_cdata.bge_tx_dmamap[idx] = map; 3632 sc->bge_cdata.bge_tx_chain[idx] = m; 3633 sc->bge_txcnt += nsegs; 3634 3635 BGE_INC(idx, BGE_TX_RING_CNT); 3636 *txidx = idx; 3637 3638 return (0); 3639 } 3640 3641 /* 3642 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3643 * to the mbuf data regions directly in the transmit descriptors. 3644 */ 3645 static void 3646 bge_start_locked(struct ifnet *ifp) 3647 { 3648 struct bge_softc *sc; 3649 struct mbuf *m_head = NULL; 3650 uint32_t prodidx; 3651 int count = 0; 3652 3653 sc = ifp->if_softc; 3654 3655 if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3656 return; 3657 3658 prodidx = sc->bge_tx_prodidx; 3659 3660 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3661 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3662 if (m_head == NULL) 3663 break; 3664 3665 /* 3666 * XXX 3667 * The code inside the if() block is never reached since we 3668 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 3669 * requests to checksum TCP/UDP in a fragmented packet. 3670 * 3671 * XXX 3672 * safety overkill. If this is a fragmented packet chain 3673 * with delayed TCP/UDP checksums, then only encapsulate 3674 * it if we have enough descriptors to handle the entire 3675 * chain at once. 3676 * (paranoia -- may not actually be needed) 3677 */ 3678 if (m_head->m_flags & M_FIRSTFRAG && 3679 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3680 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3681 m_head->m_pkthdr.csum_data + 16) { 3682 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3683 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3684 break; 3685 } 3686 } 3687 3688 /* 3689 * Pack the data into the transmit ring. If we 3690 * don't have room, set the OACTIVE flag and wait 3691 * for the NIC to drain the ring. 3692 */ 3693 if (bge_encap(sc, &m_head, &prodidx)) { 3694 if (m_head == NULL) 3695 break; 3696 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3697 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3698 break; 3699 } 3700 ++count; 3701 3702 /* 3703 * If there's a BPF listener, bounce a copy of this frame 3704 * to him. 3705 */ 3706 #ifdef ETHER_BPF_MTAP 3707 ETHER_BPF_MTAP(ifp, m_head); 3708 #else 3709 BPF_MTAP(ifp, m_head); 3710 #endif 3711 } 3712 3713 if (count == 0) 3714 /* No packets were dequeued. */ 3715 return; 3716 3717 /* Transmit. */ 3718 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3719 /* 5700 b2 errata */ 3720 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3721 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3722 3723 sc->bge_tx_prodidx = prodidx; 3724 3725 /* 3726 * Set a timeout in case the chip goes out to lunch. 3727 */ 3728 sc->bge_timer = 5; 3729 } 3730 3731 /* 3732 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3733 * to the mbuf data regions directly in the transmit descriptors. 3734 */ 3735 static void 3736 bge_start(struct ifnet *ifp) 3737 { 3738 struct bge_softc *sc; 3739 3740 sc = ifp->if_softc; 3741 BGE_LOCK(sc); 3742 bge_start_locked(ifp); 3743 BGE_UNLOCK(sc); 3744 } 3745 3746 static void 3747 bge_init_locked(struct bge_softc *sc) 3748 { 3749 struct ifnet *ifp; 3750 uint16_t *m; 3751 3752 BGE_LOCK_ASSERT(sc); 3753 3754 ifp = sc->bge_ifp; 3755 3756 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3757 return; 3758 3759 /* Cancel pending I/O and flush buffers. */ 3760 bge_stop(sc); 3761 3762 bge_stop_fw(sc); 3763 bge_sig_pre_reset(sc, BGE_RESET_START); 3764 bge_reset(sc); 3765 bge_sig_legacy(sc, BGE_RESET_START); 3766 bge_sig_post_reset(sc, BGE_RESET_START); 3767 3768 bge_chipinit(sc); 3769 3770 /* 3771 * Init the various state machines, ring 3772 * control blocks and firmware. 3773 */ 3774 if (bge_blockinit(sc)) { 3775 device_printf(sc->bge_dev, "initialization failure\n"); 3776 return; 3777 } 3778 3779 ifp = sc->bge_ifp; 3780 3781 /* Specify MTU. */ 3782 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3783 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3784 3785 /* Load our MAC address. */ 3786 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 3787 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3788 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3789 3790 /* Program promiscuous mode. */ 3791 bge_setpromisc(sc); 3792 3793 /* Program multicast filter. */ 3794 bge_setmulti(sc); 3795 3796 /* Init RX ring. */ 3797 bge_init_rx_ring_std(sc); 3798 3799 /* 3800 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3801 * memory to insure that the chip has in fact read the first 3802 * entry of the ring. 3803 */ 3804 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3805 uint32_t v, i; 3806 for (i = 0; i < 10; i++) { 3807 DELAY(20); 3808 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3809 if (v == (MCLBYTES - ETHER_ALIGN)) 3810 break; 3811 } 3812 if (i == 10) 3813 device_printf (sc->bge_dev, 3814 "5705 A0 chip failed to load RX ring\n"); 3815 } 3816 3817 /* Init jumbo RX ring. */ 3818 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3819 bge_init_rx_ring_jumbo(sc); 3820 3821 /* Init our RX return ring index. */ 3822 sc->bge_rx_saved_considx = 0; 3823 3824 /* Init our RX/TX stat counters. */ 3825 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 3826 3827 /* Init TX ring. */ 3828 bge_init_tx_ring(sc); 3829 3830 /* Turn on transmitter. */ 3831 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3832 3833 /* Turn on receiver. */ 3834 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3835 3836 /* Tell firmware we're alive. */ 3837 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3838 3839 #ifdef DEVICE_POLLING 3840 /* Disable interrupts if we are polling. */ 3841 if (ifp->if_capenable & IFCAP_POLLING) { 3842 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3843 BGE_PCIMISCCTL_MASK_PCI_INTR); 3844 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3845 } else 3846 #endif 3847 3848 /* Enable host interrupts. */ 3849 { 3850 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3851 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3852 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3853 } 3854 3855 bge_ifmedia_upd_locked(ifp); 3856 3857 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3858 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3859 3860 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3861 } 3862 3863 static void 3864 bge_init(void *xsc) 3865 { 3866 struct bge_softc *sc = xsc; 3867 3868 BGE_LOCK(sc); 3869 bge_init_locked(sc); 3870 BGE_UNLOCK(sc); 3871 } 3872 3873 /* 3874 * Set media options. 3875 */ 3876 static int 3877 bge_ifmedia_upd(struct ifnet *ifp) 3878 { 3879 struct bge_softc *sc = ifp->if_softc; 3880 int res; 3881 3882 BGE_LOCK(sc); 3883 res = bge_ifmedia_upd_locked(ifp); 3884 BGE_UNLOCK(sc); 3885 3886 return (res); 3887 } 3888 3889 static int 3890 bge_ifmedia_upd_locked(struct ifnet *ifp) 3891 { 3892 struct bge_softc *sc = ifp->if_softc; 3893 struct mii_data *mii; 3894 struct mii_softc *miisc; 3895 struct ifmedia *ifm; 3896 3897 BGE_LOCK_ASSERT(sc); 3898 3899 ifm = &sc->bge_ifmedia; 3900 3901 /* If this is a 1000baseX NIC, enable the TBI port. */ 3902 if (sc->bge_flags & BGE_FLAG_TBI) { 3903 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3904 return (EINVAL); 3905 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3906 case IFM_AUTO: 3907 /* 3908 * The BCM5704 ASIC appears to have a special 3909 * mechanism for programming the autoneg 3910 * advertisement registers in TBI mode. 3911 */ 3912 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3913 uint32_t sgdig; 3914 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 3915 if (sgdig & BGE_SGDIGSTS_DONE) { 3916 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3917 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3918 sgdig |= BGE_SGDIGCFG_AUTO | 3919 BGE_SGDIGCFG_PAUSE_CAP | 3920 BGE_SGDIGCFG_ASYM_PAUSE; 3921 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3922 sgdig | BGE_SGDIGCFG_SEND); 3923 DELAY(5); 3924 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3925 } 3926 } 3927 break; 3928 case IFM_1000_SX: 3929 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3930 BGE_CLRBIT(sc, BGE_MAC_MODE, 3931 BGE_MACMODE_HALF_DUPLEX); 3932 } else { 3933 BGE_SETBIT(sc, BGE_MAC_MODE, 3934 BGE_MACMODE_HALF_DUPLEX); 3935 } 3936 break; 3937 default: 3938 return (EINVAL); 3939 } 3940 return (0); 3941 } 3942 3943 sc->bge_link_evt++; 3944 mii = device_get_softc(sc->bge_miibus); 3945 if (mii->mii_instance) 3946 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3947 mii_phy_reset(miisc); 3948 mii_mediachg(mii); 3949 3950 return (0); 3951 } 3952 3953 /* 3954 * Report current media status. 3955 */ 3956 static void 3957 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3958 { 3959 struct bge_softc *sc = ifp->if_softc; 3960 struct mii_data *mii; 3961 3962 BGE_LOCK(sc); 3963 3964 if (sc->bge_flags & BGE_FLAG_TBI) { 3965 ifmr->ifm_status = IFM_AVALID; 3966 ifmr->ifm_active = IFM_ETHER; 3967 if (CSR_READ_4(sc, BGE_MAC_STS) & 3968 BGE_MACSTAT_TBI_PCS_SYNCHED) 3969 ifmr->ifm_status |= IFM_ACTIVE; 3970 else { 3971 ifmr->ifm_active |= IFM_NONE; 3972 BGE_UNLOCK(sc); 3973 return; 3974 } 3975 ifmr->ifm_active |= IFM_1000_SX; 3976 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3977 ifmr->ifm_active |= IFM_HDX; 3978 else 3979 ifmr->ifm_active |= IFM_FDX; 3980 BGE_UNLOCK(sc); 3981 return; 3982 } 3983 3984 mii = device_get_softc(sc->bge_miibus); 3985 mii_pollstat(mii); 3986 ifmr->ifm_active = mii->mii_media_active; 3987 ifmr->ifm_status = mii->mii_media_status; 3988 3989 BGE_UNLOCK(sc); 3990 } 3991 3992 static int 3993 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3994 { 3995 struct bge_softc *sc = ifp->if_softc; 3996 struct ifreq *ifr = (struct ifreq *) data; 3997 struct mii_data *mii; 3998 int flags, mask, error = 0; 3999 4000 switch (command) { 4001 case SIOCSIFMTU: 4002 if (ifr->ifr_mtu < ETHERMIN || 4003 ((BGE_IS_JUMBO_CAPABLE(sc)) && 4004 ifr->ifr_mtu > BGE_JUMBO_MTU) || 4005 ((!BGE_IS_JUMBO_CAPABLE(sc)) && 4006 ifr->ifr_mtu > ETHERMTU)) 4007 error = EINVAL; 4008 else if (ifp->if_mtu != ifr->ifr_mtu) { 4009 ifp->if_mtu = ifr->ifr_mtu; 4010 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4011 bge_init(sc); 4012 } 4013 break; 4014 case SIOCSIFFLAGS: 4015 BGE_LOCK(sc); 4016 if (ifp->if_flags & IFF_UP) { 4017 /* 4018 * If only the state of the PROMISC flag changed, 4019 * then just use the 'set promisc mode' command 4020 * instead of reinitializing the entire NIC. Doing 4021 * a full re-init means reloading the firmware and 4022 * waiting for it to start up, which may take a 4023 * second or two. Similarly for ALLMULTI. 4024 */ 4025 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4026 flags = ifp->if_flags ^ sc->bge_if_flags; 4027 if (flags & IFF_PROMISC) 4028 bge_setpromisc(sc); 4029 if (flags & IFF_ALLMULTI) 4030 bge_setmulti(sc); 4031 } else 4032 bge_init_locked(sc); 4033 } else { 4034 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4035 bge_stop(sc); 4036 } 4037 } 4038 sc->bge_if_flags = ifp->if_flags; 4039 BGE_UNLOCK(sc); 4040 error = 0; 4041 break; 4042 case SIOCADDMULTI: 4043 case SIOCDELMULTI: 4044 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4045 BGE_LOCK(sc); 4046 bge_setmulti(sc); 4047 BGE_UNLOCK(sc); 4048 error = 0; 4049 } 4050 break; 4051 case SIOCSIFMEDIA: 4052 case SIOCGIFMEDIA: 4053 if (sc->bge_flags & BGE_FLAG_TBI) { 4054 error = ifmedia_ioctl(ifp, ifr, 4055 &sc->bge_ifmedia, command); 4056 } else { 4057 mii = device_get_softc(sc->bge_miibus); 4058 error = ifmedia_ioctl(ifp, ifr, 4059 &mii->mii_media, command); 4060 } 4061 break; 4062 case SIOCSIFCAP: 4063 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 4064 #ifdef DEVICE_POLLING 4065 if (mask & IFCAP_POLLING) { 4066 if (ifr->ifr_reqcap & IFCAP_POLLING) { 4067 error = ether_poll_register(bge_poll, ifp); 4068 if (error) 4069 return (error); 4070 BGE_LOCK(sc); 4071 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4072 BGE_PCIMISCCTL_MASK_PCI_INTR); 4073 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4074 ifp->if_capenable |= IFCAP_POLLING; 4075 BGE_UNLOCK(sc); 4076 } else { 4077 error = ether_poll_deregister(ifp); 4078 /* Enable interrupt even in error case */ 4079 BGE_LOCK(sc); 4080 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 4081 BGE_PCIMISCCTL_MASK_PCI_INTR); 4082 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4083 ifp->if_capenable &= ~IFCAP_POLLING; 4084 BGE_UNLOCK(sc); 4085 } 4086 } 4087 #endif 4088 if (mask & IFCAP_HWCSUM) { 4089 ifp->if_capenable ^= IFCAP_HWCSUM; 4090 if (IFCAP_HWCSUM & ifp->if_capenable && 4091 IFCAP_HWCSUM & ifp->if_capabilities) 4092 ifp->if_hwassist = BGE_CSUM_FEATURES; 4093 else 4094 ifp->if_hwassist = 0; 4095 #ifdef VLAN_CAPABILITIES 4096 VLAN_CAPABILITIES(ifp); 4097 #endif 4098 } 4099 break; 4100 default: 4101 error = ether_ioctl(ifp, command, data); 4102 break; 4103 } 4104 4105 return (error); 4106 } 4107 4108 static void 4109 bge_watchdog(struct bge_softc *sc) 4110 { 4111 struct ifnet *ifp; 4112 4113 BGE_LOCK_ASSERT(sc); 4114 4115 if (sc->bge_timer == 0 || --sc->bge_timer) 4116 return; 4117 4118 ifp = sc->bge_ifp; 4119 4120 if_printf(ifp, "watchdog timeout -- resetting\n"); 4121 4122 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4123 bge_init_locked(sc); 4124 4125 ifp->if_oerrors++; 4126 } 4127 4128 /* 4129 * Stop the adapter and free any mbufs allocated to the 4130 * RX and TX lists. 4131 */ 4132 static void 4133 bge_stop(struct bge_softc *sc) 4134 { 4135 struct ifnet *ifp; 4136 struct ifmedia_entry *ifm; 4137 struct mii_data *mii = NULL; 4138 int mtmp, itmp; 4139 4140 BGE_LOCK_ASSERT(sc); 4141 4142 ifp = sc->bge_ifp; 4143 4144 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) 4145 mii = device_get_softc(sc->bge_miibus); 4146 4147 callout_stop(&sc->bge_stat_ch); 4148 4149 /* Disable host interrupts. */ 4150 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4151 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4152 4153 /* 4154 * Tell firmware we're shutting down. 4155 */ 4156 bge_stop_fw(sc); 4157 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4158 4159 /* 4160 * Disable all of the receiver blocks. 4161 */ 4162 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4163 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4164 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4165 if (!(BGE_IS_5705_PLUS(sc))) 4166 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4167 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4168 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4169 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4170 4171 /* 4172 * Disable all of the transmit blocks. 4173 */ 4174 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4175 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4176 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4177 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4178 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4179 if (!(BGE_IS_5705_PLUS(sc))) 4180 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4181 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4182 4183 /* 4184 * Shut down all of the memory managers and related 4185 * state machines. 4186 */ 4187 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4188 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4189 if (!(BGE_IS_5705_PLUS(sc))) 4190 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4191 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4192 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4193 if (!(BGE_IS_5705_PLUS(sc))) { 4194 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4195 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4196 } 4197 4198 bge_reset(sc); 4199 bge_sig_legacy(sc, BGE_RESET_STOP); 4200 bge_sig_post_reset(sc, BGE_RESET_STOP); 4201 4202 /* 4203 * Keep the ASF firmware running if up. 4204 */ 4205 if (sc->bge_asf_mode & ASF_STACKUP) 4206 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4207 else 4208 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4209 4210 /* Free the RX lists. */ 4211 bge_free_rx_ring_std(sc); 4212 4213 /* Free jumbo RX list. */ 4214 if (BGE_IS_JUMBO_CAPABLE(sc)) 4215 bge_free_rx_ring_jumbo(sc); 4216 4217 /* Free TX buffers. */ 4218 bge_free_tx_ring(sc); 4219 4220 /* 4221 * Isolate/power down the PHY, but leave the media selection 4222 * unchanged so that things will be put back to normal when 4223 * we bring the interface back up. 4224 */ 4225 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4226 itmp = ifp->if_flags; 4227 ifp->if_flags |= IFF_UP; 4228 /* 4229 * If we are called from bge_detach(), mii is already NULL. 4230 */ 4231 if (mii != NULL) { 4232 ifm = mii->mii_media.ifm_cur; 4233 mtmp = ifm->ifm_media; 4234 ifm->ifm_media = IFM_ETHER | IFM_NONE; 4235 mii_mediachg(mii); 4236 ifm->ifm_media = mtmp; 4237 } 4238 ifp->if_flags = itmp; 4239 } 4240 4241 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4242 4243 /* Clear MAC's link state (PHY may still have link UP). */ 4244 if (bootverbose && sc->bge_link) 4245 if_printf(sc->bge_ifp, "link DOWN\n"); 4246 sc->bge_link = 0; 4247 4248 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4249 } 4250 4251 /* 4252 * Stop all chip I/O so that the kernel's probe routines don't 4253 * get confused by errant DMAs when rebooting. 4254 */ 4255 static int 4256 bge_shutdown(device_t dev) 4257 { 4258 struct bge_softc *sc; 4259 4260 sc = device_get_softc(dev); 4261 BGE_LOCK(sc); 4262 bge_stop(sc); 4263 bge_reset(sc); 4264 BGE_UNLOCK(sc); 4265 4266 return (0); 4267 } 4268 4269 static int 4270 bge_suspend(device_t dev) 4271 { 4272 struct bge_softc *sc; 4273 4274 sc = device_get_softc(dev); 4275 BGE_LOCK(sc); 4276 bge_stop(sc); 4277 BGE_UNLOCK(sc); 4278 4279 return (0); 4280 } 4281 4282 static int 4283 bge_resume(device_t dev) 4284 { 4285 struct bge_softc *sc; 4286 struct ifnet *ifp; 4287 4288 sc = device_get_softc(dev); 4289 BGE_LOCK(sc); 4290 ifp = sc->bge_ifp; 4291 if (ifp->if_flags & IFF_UP) { 4292 bge_init_locked(sc); 4293 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4294 bge_start_locked(ifp); 4295 } 4296 BGE_UNLOCK(sc); 4297 4298 return (0); 4299 } 4300 4301 static void 4302 bge_link_upd(struct bge_softc *sc) 4303 { 4304 struct mii_data *mii; 4305 uint32_t link, status; 4306 4307 BGE_LOCK_ASSERT(sc); 4308 4309 /* Clear 'pending link event' flag. */ 4310 sc->bge_link_evt = 0; 4311 4312 /* 4313 * Process link state changes. 4314 * Grrr. The link status word in the status block does 4315 * not work correctly on the BCM5700 rev AX and BX chips, 4316 * according to all available information. Hence, we have 4317 * to enable MII interrupts in order to properly obtain 4318 * async link changes. Unfortunately, this also means that 4319 * we have to read the MAC status register to detect link 4320 * changes, thereby adding an additional register access to 4321 * the interrupt handler. 4322 * 4323 * XXX: perhaps link state detection procedure used for 4324 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4325 */ 4326 4327 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4328 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 4329 status = CSR_READ_4(sc, BGE_MAC_STS); 4330 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4331 mii = device_get_softc(sc->bge_miibus); 4332 mii_pollstat(mii); 4333 if (!sc->bge_link && 4334 mii->mii_media_status & IFM_ACTIVE && 4335 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4336 sc->bge_link++; 4337 if (bootverbose) 4338 if_printf(sc->bge_ifp, "link UP\n"); 4339 } else if (sc->bge_link && 4340 (!(mii->mii_media_status & IFM_ACTIVE) || 4341 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4342 sc->bge_link = 0; 4343 if (bootverbose) 4344 if_printf(sc->bge_ifp, "link DOWN\n"); 4345 } 4346 4347 /* Clear the interrupt. */ 4348 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4349 BGE_EVTENB_MI_INTERRUPT); 4350 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4351 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4352 BRGPHY_INTRS); 4353 } 4354 return; 4355 } 4356 4357 if (sc->bge_flags & BGE_FLAG_TBI) { 4358 status = CSR_READ_4(sc, BGE_MAC_STS); 4359 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4360 if (!sc->bge_link) { 4361 sc->bge_link++; 4362 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 4363 BGE_CLRBIT(sc, BGE_MAC_MODE, 4364 BGE_MACMODE_TBI_SEND_CFGS); 4365 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4366 if (bootverbose) 4367 if_printf(sc->bge_ifp, "link UP\n"); 4368 if_link_state_change(sc->bge_ifp, 4369 LINK_STATE_UP); 4370 } 4371 } else if (sc->bge_link) { 4372 sc->bge_link = 0; 4373 if (bootverbose) 4374 if_printf(sc->bge_ifp, "link DOWN\n"); 4375 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 4376 } 4377 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { 4378 /* 4379 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 4380 * in status word always set. Workaround this bug by reading 4381 * PHY link status directly. 4382 */ 4383 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 4384 4385 if (link != sc->bge_link || 4386 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 4387 mii = device_get_softc(sc->bge_miibus); 4388 mii_pollstat(mii); 4389 if (!sc->bge_link && 4390 mii->mii_media_status & IFM_ACTIVE && 4391 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4392 sc->bge_link++; 4393 if (bootverbose) 4394 if_printf(sc->bge_ifp, "link UP\n"); 4395 } else if (sc->bge_link && 4396 (!(mii->mii_media_status & IFM_ACTIVE) || 4397 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4398 sc->bge_link = 0; 4399 if (bootverbose) 4400 if_printf(sc->bge_ifp, "link DOWN\n"); 4401 } 4402 } 4403 } else { 4404 /* 4405 * Discard link events for MII/GMII controllers 4406 * if MI auto-polling is disabled. 4407 */ 4408 } 4409 4410 /* Clear the attention. */ 4411 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4412 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4413 BGE_MACSTAT_LINK_CHANGED); 4414 } 4415 4416 static void 4417 bge_add_sysctls(struct bge_softc *sc) 4418 { 4419 struct sysctl_ctx_list *ctx; 4420 struct sysctl_oid_list *children; 4421 4422 ctx = device_get_sysctl_ctx(sc->bge_dev); 4423 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 4424 4425 #ifdef BGE_REGISTER_DEBUG 4426 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 4427 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 4428 "Debug Information"); 4429 4430 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 4431 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 4432 "Register Read"); 4433 4434 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 4435 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 4436 "Memory Read"); 4437 4438 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "stat_IfHcInOctets", 4439 CTLFLAG_RD, 4440 &sc->bge_ldata.bge_stats->rxstats.ifHCInOctets.bge_addr_lo, 4441 "Bytes received"); 4442 4443 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "stat_IfHcOutOctets", 4444 CTLFLAG_RD, 4445 &sc->bge_ldata.bge_stats->txstats.ifHCOutOctets.bge_addr_lo, 4446 "Bytes received"); 4447 #endif 4448 } 4449 4450 #ifdef BGE_REGISTER_DEBUG 4451 static int 4452 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4453 { 4454 struct bge_softc *sc; 4455 uint16_t *sbdata; 4456 int error; 4457 int result; 4458 int i, j; 4459 4460 result = -1; 4461 error = sysctl_handle_int(oidp, &result, 0, req); 4462 if (error || (req->newptr == NULL)) 4463 return (error); 4464 4465 if (result == 1) { 4466 sc = (struct bge_softc *)arg1; 4467 4468 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 4469 printf("Status Block:\n"); 4470 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 4471 printf("%06x:", i); 4472 for (j = 0; j < 8; j++) { 4473 printf(" %04x", sbdata[i]); 4474 i += 4; 4475 } 4476 printf("\n"); 4477 } 4478 4479 printf("Registers:\n"); 4480 for (i = 0x800; i < 0xA00; ) { 4481 printf("%06x:", i); 4482 for (j = 0; j < 8; j++) { 4483 printf(" %08x", CSR_READ_4(sc, i)); 4484 i += 4; 4485 } 4486 printf("\n"); 4487 } 4488 4489 printf("Hardware Flags:\n"); 4490 if (BGE_IS_575X_PLUS(sc)) 4491 printf(" - 575X Plus\n"); 4492 if (BGE_IS_5705_PLUS(sc)) 4493 printf(" - 5705 Plus\n"); 4494 if (BGE_IS_5714_FAMILY(sc)) 4495 printf(" - 5714 Family\n"); 4496 if (BGE_IS_5700_FAMILY(sc)) 4497 printf(" - 5700 Family\n"); 4498 if (sc->bge_flags & BGE_FLAG_JUMBO) 4499 printf(" - Supports Jumbo Frames\n"); 4500 if (sc->bge_flags & BGE_FLAG_PCIX) 4501 printf(" - PCI-X Bus\n"); 4502 if (sc->bge_flags & BGE_FLAG_PCIE) 4503 printf(" - PCI Express Bus\n"); 4504 if (sc->bge_flags & BGE_FLAG_NO_3LED) 4505 printf(" - No 3 LEDs\n"); 4506 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 4507 printf(" - RX Alignment Bug\n"); 4508 } 4509 4510 return (error); 4511 } 4512 4513 static int 4514 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 4515 { 4516 struct bge_softc *sc; 4517 int error; 4518 uint16_t result; 4519 uint32_t val; 4520 4521 result = -1; 4522 error = sysctl_handle_int(oidp, &result, 0, req); 4523 if (error || (req->newptr == NULL)) 4524 return (error); 4525 4526 if (result < 0x8000) { 4527 sc = (struct bge_softc *)arg1; 4528 val = CSR_READ_4(sc, result); 4529 printf("reg 0x%06X = 0x%08X\n", result, val); 4530 } 4531 4532 return (error); 4533 } 4534 4535 static int 4536 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 4537 { 4538 struct bge_softc *sc; 4539 int error; 4540 uint16_t result; 4541 uint32_t val; 4542 4543 result = -1; 4544 error = sysctl_handle_int(oidp, &result, 0, req); 4545 if (error || (req->newptr == NULL)) 4546 return (error); 4547 4548 if (result < 0x8000) { 4549 sc = (struct bge_softc *)arg1; 4550 val = bge_readmem_ind(sc, result); 4551 printf("mem 0x%06X = 0x%08X\n", result, val); 4552 } 4553 4554 return (error); 4555 } 4556 #endif 4557 4558 static int 4559 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 4560 { 4561 4562 if (sc->bge_flags & BGE_FLAG_EADDR) 4563 return (1); 4564 4565 #ifdef __sparc64__ 4566 OF_getetheraddr(sc->bge_dev, ether_addr); 4567 return (0); 4568 #endif 4569 return (1); 4570 } 4571 4572 static int 4573 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4574 { 4575 uint32_t mac_addr; 4576 4577 mac_addr = bge_readmem_ind(sc, 0x0c14); 4578 if ((mac_addr >> 16) == 0x484b) { 4579 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4580 ether_addr[1] = (uint8_t)mac_addr; 4581 mac_addr = bge_readmem_ind(sc, 0x0c18); 4582 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4583 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4584 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4585 ether_addr[5] = (uint8_t)mac_addr; 4586 return (0); 4587 } 4588 return (1); 4589 } 4590 4591 static int 4592 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4593 { 4594 int mac_offset = BGE_EE_MAC_OFFSET; 4595 4596 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4597 mac_offset = BGE_EE_MAC_OFFSET_5906; 4598 4599 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4600 ETHER_ADDR_LEN)); 4601 } 4602 4603 static int 4604 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4605 { 4606 4607 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 4608 return (1); 4609 4610 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4611 ETHER_ADDR_LEN)); 4612 } 4613 4614 static int 4615 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4616 { 4617 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4618 /* NOTE: Order is critical */ 4619 bge_get_eaddr_fw, 4620 bge_get_eaddr_mem, 4621 bge_get_eaddr_nvram, 4622 bge_get_eaddr_eeprom, 4623 NULL 4624 }; 4625 const bge_eaddr_fcn_t *func; 4626 4627 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4628 if ((*func)(sc, eaddr) == 0) 4629 break; 4630 } 4631 return (*func == NULL ? ENXIO : 0); 4632 }
Cache object: f0969a9d845b6e4bd0a3c34f6813747d
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