Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/bge/if_bge.c
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1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 84 #include <net/if.h> 85 #include <net/if_arp.h> 86 #include <net/ethernet.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 90 #include <net/bpf.h> 91 92 #include <net/if_types.h> 93 #include <net/if_vlan_var.h> 94 95 #include <netinet/in_systm.h> 96 #include <netinet/in.h> 97 #include <netinet/ip.h> 98 99 #include <machine/bus.h> 100 #include <machine/resource.h> 101 #include <sys/bus.h> 102 #include <sys/rman.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 #include "miidevs.h" 107 #include <dev/mii/brgphyreg.h> 108 109 #ifdef __sparc64__ 110 #include <dev/ofw/ofw_bus.h> 111 #include <dev/ofw/openfirm.h> 112 #include <machine/ofw_machdep.h> 113 #include <machine/ver.h> 114 #endif 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 119 #include <dev/bge/if_bgereg.h> 120 121 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 122 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 123 124 MODULE_DEPEND(bge, pci, 1, 1, 1); 125 MODULE_DEPEND(bge, ether, 1, 1, 1); 126 MODULE_DEPEND(bge, miibus, 1, 1, 1); 127 128 /* "device miibus" required. See GENERIC if you get errors here. */ 129 #include "miibus_if.h" 130 131 /* 132 * Various supported device vendors/types and their names. Note: the 133 * spec seems to indicate that the hardware still has Alteon's vendor 134 * ID burned into it, though it will always be overriden by the vendor 135 * ID in the EEPROM. Just to be safe, we cover all possibilities. 136 */ 137 static struct bge_type { 138 uint16_t bge_vid; 139 uint16_t bge_did; 140 } bge_devs[] = { 141 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 142 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 143 144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 145 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 147 148 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 149 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 198 199 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 200 201 { TC_VENDORID, TC_DEVICEID_3C996 }, 202 203 { 0, 0 } 204 }; 205 206 static const struct bge_vendor { 207 uint16_t v_id; 208 const char *v_name; 209 } bge_vendors[] = { 210 { ALTEON_VENDORID, "Alteon" }, 211 { ALTIMA_VENDORID, "Altima" }, 212 { APPLE_VENDORID, "Apple" }, 213 { BCOM_VENDORID, "Broadcom" }, 214 { SK_VENDORID, "SysKonnect" }, 215 { TC_VENDORID, "3Com" }, 216 217 { 0, NULL } 218 }; 219 220 static const struct bge_revision { 221 uint32_t br_chipid; 222 const char *br_name; 223 } bge_revisions[] = { 224 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 225 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 226 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 227 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 228 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 229 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 230 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 231 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 232 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 233 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 234 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 235 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 236 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 237 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 238 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 239 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 240 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 241 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 242 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 243 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 244 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 245 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 246 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 247 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 248 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 249 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 250 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 251 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 252 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 253 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 254 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 255 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 256 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 257 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 258 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 259 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 260 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 261 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 262 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 263 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 264 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 265 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 266 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 267 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 268 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 269 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 270 /* 5754 and 5787 share the same ASIC ID */ 271 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 272 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 273 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 274 275 { 0, NULL } 276 }; 277 278 /* 279 * Some defaults for major revisions, so that newer steppings 280 * that we don't know about have a shot at working. 281 */ 282 static const struct bge_revision bge_majorrevs[] = { 283 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 284 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 285 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 286 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 287 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 288 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 289 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 290 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 291 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 292 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 293 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 294 /* 5754 and 5787 share the same ASIC ID */ 295 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 296 297 { 0, NULL } 298 }; 299 300 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 301 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 302 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 303 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 304 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 305 306 const struct bge_revision * bge_lookup_rev(uint32_t); 307 const struct bge_vendor * bge_lookup_vendor(uint16_t); 308 static int bge_probe(device_t); 309 static int bge_attach(device_t); 310 static int bge_detach(device_t); 311 static int bge_suspend(device_t); 312 static int bge_resume(device_t); 313 static void bge_release_resources(struct bge_softc *); 314 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 315 static int bge_dma_alloc(device_t); 316 static void bge_dma_free(struct bge_softc *); 317 318 static void bge_txeof(struct bge_softc *); 319 static void bge_rxeof(struct bge_softc *); 320 321 static void bge_asf_driver_up (struct bge_softc *); 322 static void bge_tick(void *); 323 static void bge_stats_update(struct bge_softc *); 324 static void bge_stats_update_regs(struct bge_softc *); 325 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 326 327 static void bge_intr(void *); 328 static void bge_start_locked(struct ifnet *); 329 static void bge_start(struct ifnet *); 330 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 331 static void bge_init_locked(struct bge_softc *); 332 static void bge_init(void *); 333 static void bge_stop(struct bge_softc *); 334 static void bge_watchdog(struct bge_softc *); 335 static void bge_shutdown(device_t); 336 static int bge_ifmedia_upd_locked(struct ifnet *); 337 static int bge_ifmedia_upd(struct ifnet *); 338 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 339 340 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 341 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 342 343 static void bge_setpromisc(struct bge_softc *); 344 static void bge_setmulti(struct bge_softc *); 345 static void bge_setvlan(struct bge_softc *); 346 347 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *); 348 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 349 static int bge_init_rx_ring_std(struct bge_softc *); 350 static void bge_free_rx_ring_std(struct bge_softc *); 351 static int bge_init_rx_ring_jumbo(struct bge_softc *); 352 static void bge_free_rx_ring_jumbo(struct bge_softc *); 353 static void bge_free_tx_ring(struct bge_softc *); 354 static int bge_init_tx_ring(struct bge_softc *); 355 356 static int bge_chipinit(struct bge_softc *); 357 static int bge_blockinit(struct bge_softc *); 358 359 static int bge_has_eeprom(struct bge_softc *); 360 static uint32_t bge_readmem_ind(struct bge_softc *, int); 361 static void bge_writemem_ind(struct bge_softc *, int, int); 362 #ifdef notdef 363 static uint32_t bge_readreg_ind(struct bge_softc *, int); 364 #endif 365 static void bge_writemem_direct(struct bge_softc *, int, int); 366 static void bge_writereg_ind(struct bge_softc *, int, int); 367 368 static int bge_miibus_readreg(device_t, int, int); 369 static int bge_miibus_writereg(device_t, int, int, int); 370 static void bge_miibus_statchg(device_t); 371 #ifdef DEVICE_POLLING 372 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 373 #endif 374 375 #define BGE_RESET_START 1 376 #define BGE_RESET_STOP 2 377 static void bge_sig_post_reset(struct bge_softc *, int); 378 static void bge_sig_legacy(struct bge_softc *, int); 379 static void bge_sig_pre_reset(struct bge_softc *, int); 380 static int bge_reset(struct bge_softc *); 381 static void bge_link_upd(struct bge_softc *); 382 383 /* 384 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 385 * leak information to untrusted users. It is also known to cause alignment 386 * traps on certain architectures. 387 */ 388 #ifdef BGE_REGISTER_DEBUG 389 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 390 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 391 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 392 #endif 393 static void bge_add_sysctls(struct bge_softc *); 394 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 395 396 static device_method_t bge_methods[] = { 397 /* Device interface */ 398 DEVMETHOD(device_probe, bge_probe), 399 DEVMETHOD(device_attach, bge_attach), 400 DEVMETHOD(device_detach, bge_detach), 401 DEVMETHOD(device_shutdown, bge_shutdown), 402 DEVMETHOD(device_suspend, bge_suspend), 403 DEVMETHOD(device_resume, bge_resume), 404 405 /* bus interface */ 406 DEVMETHOD(bus_print_child, bus_generic_print_child), 407 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 408 409 /* MII interface */ 410 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 411 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 412 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 413 414 { 0, 0 } 415 }; 416 417 static driver_t bge_driver = { 418 "bge", 419 bge_methods, 420 sizeof(struct bge_softc) 421 }; 422 423 static devclass_t bge_devclass; 424 425 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 426 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 427 428 static int bge_allow_asf = 0; 429 430 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 431 432 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 433 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 434 "Allow ASF mode if available"); 435 436 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 437 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 438 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 439 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 440 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 441 442 static int 443 bge_has_eeprom(struct bge_softc *sc) 444 { 445 #ifdef __sparc64__ 446 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 447 device_t dev; 448 uint32_t subvendor; 449 450 dev = sc->bge_dev; 451 452 /* 453 * The on-board BGEs found in sun4u machines aren't fitted with 454 * an EEPROM which means that we have to obtain the MAC address 455 * via OFW and that some tests will always fail. We distinguish 456 * such BGEs by the subvendor ID, which also has to be obtained 457 * from OFW instead of the PCI configuration space as the latter 458 * indicates Broadcom as the subvendor of the netboot interface. 459 * For early Blade 1500 and 2500 we even have to check the OFW 460 * device path as the subvendor ID always defaults to Broadcom 461 * there. 462 */ 463 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 464 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 465 subvendor == SUN_VENDORID) 466 return (0); 467 memset(buf, 0, sizeof(buf)); 468 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 469 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 470 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 471 return (0); 472 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 473 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 474 return (0); 475 } 476 #endif 477 return (1); 478 } 479 480 static uint32_t 481 bge_readmem_ind(struct bge_softc *sc, int off) 482 { 483 device_t dev; 484 uint32_t val; 485 486 dev = sc->bge_dev; 487 488 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 489 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 490 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 491 return (val); 492 } 493 494 static void 495 bge_writemem_ind(struct bge_softc *sc, int off, int val) 496 { 497 device_t dev; 498 499 dev = sc->bge_dev; 500 501 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 502 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 503 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 504 } 505 506 #ifdef notdef 507 static uint32_t 508 bge_readreg_ind(struct bge_softc *sc, int off) 509 { 510 device_t dev; 511 512 dev = sc->bge_dev; 513 514 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 515 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 516 } 517 #endif 518 519 static void 520 bge_writereg_ind(struct bge_softc *sc, int off, int val) 521 { 522 device_t dev; 523 524 dev = sc->bge_dev; 525 526 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 527 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 528 } 529 530 static void 531 bge_writemem_direct(struct bge_softc *sc, int off, int val) 532 { 533 CSR_WRITE_4(sc, off, val); 534 } 535 536 /* 537 * Map a single buffer address. 538 */ 539 540 static void 541 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 542 { 543 struct bge_dmamap_arg *ctx; 544 545 if (error) 546 return; 547 548 ctx = arg; 549 550 if (nseg > ctx->bge_maxsegs) { 551 ctx->bge_maxsegs = 0; 552 return; 553 } 554 555 ctx->bge_busaddr = segs->ds_addr; 556 } 557 558 /* 559 * Read a byte of data stored in the EEPROM at address 'addr.' The 560 * BCM570x supports both the traditional bitbang interface and an 561 * auto access interface for reading the EEPROM. We use the auto 562 * access method. 563 */ 564 static uint8_t 565 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 566 { 567 int i; 568 uint32_t byte = 0; 569 570 /* 571 * Enable use of auto EEPROM access so we can avoid 572 * having to use the bitbang method. 573 */ 574 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 575 576 /* Reset the EEPROM, load the clock period. */ 577 CSR_WRITE_4(sc, BGE_EE_ADDR, 578 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 579 DELAY(20); 580 581 /* Issue the read EEPROM command. */ 582 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 583 584 /* Wait for completion */ 585 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 586 DELAY(10); 587 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 588 break; 589 } 590 591 if (i == BGE_TIMEOUT * 10) { 592 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 593 return (1); 594 } 595 596 /* Get result. */ 597 byte = CSR_READ_4(sc, BGE_EE_DATA); 598 599 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 600 601 return (0); 602 } 603 604 /* 605 * Read a sequence of bytes from the EEPROM. 606 */ 607 static int 608 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 609 { 610 int i, error = 0; 611 uint8_t byte = 0; 612 613 for (i = 0; i < cnt; i++) { 614 error = bge_eeprom_getbyte(sc, off + i, &byte); 615 if (error) 616 break; 617 *(dest + i) = byte; 618 } 619 620 return (error ? 1 : 0); 621 } 622 623 static int 624 bge_miibus_readreg(device_t dev, int phy, int reg) 625 { 626 struct bge_softc *sc; 627 uint32_t val, autopoll; 628 int i; 629 630 sc = device_get_softc(dev); 631 632 /* 633 * Broadcom's own driver always assumes the internal 634 * PHY is at GMII address 1. On some chips, the PHY responds 635 * to accesses at all addresses, which could cause us to 636 * bogusly attach the PHY 32 times at probe type. Always 637 * restricting the lookup to address 1 is simpler than 638 * trying to figure out which chips revisions should be 639 * special-cased. 640 */ 641 if (phy != 1) 642 return (0); 643 644 /* Reading with autopolling on may trigger PCI errors */ 645 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 646 if (autopoll & BGE_MIMODE_AUTOPOLL) { 647 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 648 DELAY(40); 649 } 650 651 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 652 BGE_MIPHY(phy) | BGE_MIREG(reg)); 653 654 for (i = 0; i < BGE_TIMEOUT; i++) { 655 DELAY(10); 656 val = CSR_READ_4(sc, BGE_MI_COMM); 657 if (!(val & BGE_MICOMM_BUSY)) 658 break; 659 } 660 661 if (i == BGE_TIMEOUT) { 662 device_printf(sc->bge_dev, "PHY read timed out\n"); 663 val = 0; 664 goto done; 665 } 666 667 val = CSR_READ_4(sc, BGE_MI_COMM); 668 669 done: 670 if (autopoll & BGE_MIMODE_AUTOPOLL) { 671 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 672 DELAY(40); 673 } 674 675 if (val & BGE_MICOMM_READFAIL) 676 return (0); 677 678 return (val & 0xFFFF); 679 } 680 681 static int 682 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 683 { 684 struct bge_softc *sc; 685 uint32_t autopoll; 686 int i; 687 688 sc = device_get_softc(dev); 689 690 /* Reading with autopolling on may trigger PCI errors */ 691 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 692 if (autopoll & BGE_MIMODE_AUTOPOLL) { 693 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 694 DELAY(40); 695 } 696 697 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 698 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 699 700 for (i = 0; i < BGE_TIMEOUT; i++) { 701 DELAY(10); 702 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 703 break; 704 } 705 706 if (i == BGE_TIMEOUT) { 707 device_printf(sc->bge_dev, "PHY write timed out\n"); 708 return (0); 709 } 710 711 if (autopoll & BGE_MIMODE_AUTOPOLL) { 712 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 713 DELAY(40); 714 } 715 716 return (0); 717 } 718 719 static void 720 bge_miibus_statchg(device_t dev) 721 { 722 struct bge_softc *sc; 723 struct mii_data *mii; 724 sc = device_get_softc(dev); 725 mii = device_get_softc(sc->bge_miibus); 726 727 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 728 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 729 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 730 else 731 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 732 733 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 734 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 735 else 736 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 737 } 738 739 /* 740 * Intialize a standard receive ring descriptor. 741 */ 742 static int 743 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m) 744 { 745 struct mbuf *m_new = NULL; 746 struct bge_rx_bd *r; 747 struct bge_dmamap_arg ctx; 748 int error; 749 750 if (m == NULL) { 751 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 752 if (m_new == NULL) 753 return (ENOBUFS); 754 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 755 } else { 756 m_new = m; 757 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 758 m_new->m_data = m_new->m_ext.ext_buf; 759 } 760 761 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 762 m_adj(m_new, ETHER_ALIGN); 763 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 764 r = &sc->bge_ldata.bge_rx_std_ring[i]; 765 ctx.bge_maxsegs = 1; 766 ctx.sc = sc; 767 error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 768 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 769 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 770 if (error || ctx.bge_maxsegs == 0) { 771 if (m == NULL) { 772 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 773 m_freem(m_new); 774 } 775 return (ENOMEM); 776 } 777 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr); 778 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr); 779 r->bge_flags = BGE_RXBDFLAG_END; 780 r->bge_len = m_new->m_len; 781 r->bge_idx = i; 782 783 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 784 sc->bge_cdata.bge_rx_std_dmamap[i], 785 BUS_DMASYNC_PREREAD); 786 787 return (0); 788 } 789 790 /* 791 * Initialize a jumbo receive ring descriptor. This allocates 792 * a jumbo buffer from the pool managed internally by the driver. 793 */ 794 static int 795 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 796 { 797 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 798 struct bge_extrx_bd *r; 799 struct mbuf *m_new = NULL; 800 int nsegs; 801 int error; 802 803 if (m == NULL) { 804 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 805 if (m_new == NULL) 806 return (ENOBUFS); 807 808 m_cljget(m_new, M_DONTWAIT, MJUM9BYTES); 809 if (!(m_new->m_flags & M_EXT)) { 810 m_freem(m_new); 811 return (ENOBUFS); 812 } 813 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 814 } else { 815 m_new = m; 816 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 817 m_new->m_data = m_new->m_ext.ext_buf; 818 } 819 820 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 821 m_adj(m_new, ETHER_ALIGN); 822 823 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 824 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 825 m_new, segs, &nsegs, BUS_DMA_NOWAIT); 826 if (error) { 827 if (m == NULL) 828 m_freem(m_new); 829 return (error); 830 } 831 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 832 833 /* 834 * Fill in the extended RX buffer descriptor. 835 */ 836 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 837 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 838 r->bge_idx = i; 839 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 840 switch (nsegs) { 841 case 4: 842 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 843 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 844 r->bge_len3 = segs[3].ds_len; 845 case 3: 846 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 847 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 848 r->bge_len2 = segs[2].ds_len; 849 case 2: 850 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 851 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 852 r->bge_len1 = segs[1].ds_len; 853 case 1: 854 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 855 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 856 r->bge_len0 = segs[0].ds_len; 857 break; 858 default: 859 panic("%s: %d segments\n", __func__, nsegs); 860 } 861 862 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 863 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 864 BUS_DMASYNC_PREREAD); 865 866 return (0); 867 } 868 869 /* 870 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 871 * that's 1MB or memory, which is a lot. For now, we fill only the first 872 * 256 ring entries and hope that our CPU is fast enough to keep up with 873 * the NIC. 874 */ 875 static int 876 bge_init_rx_ring_std(struct bge_softc *sc) 877 { 878 int i; 879 880 for (i = 0; i < BGE_SSLOTS; i++) { 881 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 882 return (ENOBUFS); 883 }; 884 885 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 886 sc->bge_cdata.bge_rx_std_ring_map, 887 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 888 889 sc->bge_std = i - 1; 890 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 891 892 return (0); 893 } 894 895 static void 896 bge_free_rx_ring_std(struct bge_softc *sc) 897 { 898 int i; 899 900 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 901 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 902 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 903 sc->bge_cdata.bge_rx_std_dmamap[i], 904 BUS_DMASYNC_POSTREAD); 905 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 906 sc->bge_cdata.bge_rx_std_dmamap[i]); 907 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 908 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 909 } 910 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 911 sizeof(struct bge_rx_bd)); 912 } 913 } 914 915 static int 916 bge_init_rx_ring_jumbo(struct bge_softc *sc) 917 { 918 struct bge_rcb *rcb; 919 int i; 920 921 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 922 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 923 return (ENOBUFS); 924 }; 925 926 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 927 sc->bge_cdata.bge_rx_jumbo_ring_map, 928 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 929 930 sc->bge_jumbo = i - 1; 931 932 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 933 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 934 BGE_RCB_FLAG_USE_EXT_RX_BD); 935 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 936 937 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 938 939 return (0); 940 } 941 942 static void 943 bge_free_rx_ring_jumbo(struct bge_softc *sc) 944 { 945 int i; 946 947 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 948 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 949 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 950 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 951 BUS_DMASYNC_POSTREAD); 952 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 953 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 954 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 955 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 956 } 957 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 958 sizeof(struct bge_extrx_bd)); 959 } 960 } 961 962 static void 963 bge_free_tx_ring(struct bge_softc *sc) 964 { 965 int i; 966 967 if (sc->bge_ldata.bge_tx_ring == NULL) 968 return; 969 970 for (i = 0; i < BGE_TX_RING_CNT; i++) { 971 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 972 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 973 sc->bge_cdata.bge_tx_dmamap[i], 974 BUS_DMASYNC_POSTWRITE); 975 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 976 sc->bge_cdata.bge_tx_dmamap[i]); 977 m_freem(sc->bge_cdata.bge_tx_chain[i]); 978 sc->bge_cdata.bge_tx_chain[i] = NULL; 979 } 980 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 981 sizeof(struct bge_tx_bd)); 982 } 983 } 984 985 static int 986 bge_init_tx_ring(struct bge_softc *sc) 987 { 988 sc->bge_txcnt = 0; 989 sc->bge_tx_saved_considx = 0; 990 991 /* Initialize transmit producer index for host-memory send ring. */ 992 sc->bge_tx_prodidx = 0; 993 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 994 995 /* 5700 b2 errata */ 996 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 997 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 998 999 /* NIC-memory send ring not used; initialize to zero. */ 1000 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1001 /* 5700 b2 errata */ 1002 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1003 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1004 1005 return (0); 1006 } 1007 1008 static void 1009 bge_setpromisc(struct bge_softc *sc) 1010 { 1011 struct ifnet *ifp; 1012 1013 BGE_LOCK_ASSERT(sc); 1014 1015 ifp = sc->bge_ifp; 1016 1017 /* Enable or disable promiscuous mode as needed. */ 1018 if (ifp->if_flags & IFF_PROMISC) 1019 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1020 else 1021 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1022 } 1023 1024 static void 1025 bge_setmulti(struct bge_softc *sc) 1026 { 1027 struct ifnet *ifp; 1028 struct ifmultiaddr *ifma; 1029 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1030 int h, i; 1031 1032 BGE_LOCK_ASSERT(sc); 1033 1034 ifp = sc->bge_ifp; 1035 1036 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1037 for (i = 0; i < 4; i++) 1038 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1039 return; 1040 } 1041 1042 /* First, zot all the existing filters. */ 1043 for (i = 0; i < 4; i++) 1044 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1045 1046 /* Now program new ones. */ 1047 IF_ADDR_LOCK(ifp); 1048 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1049 if (ifma->ifma_addr->sa_family != AF_LINK) 1050 continue; 1051 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1052 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1053 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1054 } 1055 IF_ADDR_UNLOCK(ifp); 1056 1057 for (i = 0; i < 4; i++) 1058 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1059 } 1060 1061 static void 1062 bge_setvlan(struct bge_softc *sc) 1063 { 1064 struct ifnet *ifp; 1065 1066 BGE_LOCK_ASSERT(sc); 1067 1068 ifp = sc->bge_ifp; 1069 1070 /* Enable or disable VLAN tag stripping as needed. */ 1071 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1072 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1073 else 1074 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1075 } 1076 1077 static void 1078 bge_sig_pre_reset(sc, type) 1079 struct bge_softc *sc; 1080 int type; 1081 { 1082 /* 1083 * Some chips don't like this so only do this if ASF is enabled 1084 */ 1085 if (sc->bge_asf_mode) 1086 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1087 1088 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1089 switch (type) { 1090 case BGE_RESET_START: 1091 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1092 break; 1093 case BGE_RESET_STOP: 1094 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1095 break; 1096 } 1097 } 1098 } 1099 1100 static void 1101 bge_sig_post_reset(sc, type) 1102 struct bge_softc *sc; 1103 int type; 1104 { 1105 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1106 switch (type) { 1107 case BGE_RESET_START: 1108 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1109 /* START DONE */ 1110 break; 1111 case BGE_RESET_STOP: 1112 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1113 break; 1114 } 1115 } 1116 } 1117 1118 static void 1119 bge_sig_legacy(sc, type) 1120 struct bge_softc *sc; 1121 int type; 1122 { 1123 if (sc->bge_asf_mode) { 1124 switch (type) { 1125 case BGE_RESET_START: 1126 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1127 break; 1128 case BGE_RESET_STOP: 1129 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1130 break; 1131 } 1132 } 1133 } 1134 1135 void bge_stop_fw(struct bge_softc *); 1136 void 1137 bge_stop_fw(sc) 1138 struct bge_softc *sc; 1139 { 1140 int i; 1141 1142 if (sc->bge_asf_mode) { 1143 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1144 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1145 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1146 1147 for (i = 0; i < 100; i++ ) { 1148 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1149 break; 1150 DELAY(10); 1151 } 1152 } 1153 } 1154 1155 /* 1156 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1157 * self-test results. 1158 */ 1159 static int 1160 bge_chipinit(struct bge_softc *sc) 1161 { 1162 uint32_t dma_rw_ctl; 1163 int i; 1164 1165 /* Set endianness before we access any non-PCI registers. */ 1166 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 1167 1168 /* 1169 * Check the 'ROM failed' bit on the RX CPU to see if 1170 * self-tests passed. Skip this check when there's no 1171 * EEPROM fitted, since in that case it will always 1172 * fail. 1173 */ 1174 if ((sc->bge_flags & BGE_FLAG_EEPROM) && 1175 CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1176 device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n"); 1177 return (ENODEV); 1178 } 1179 1180 /* Clear the MAC control register */ 1181 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1182 1183 /* 1184 * Clear the MAC statistics block in the NIC's 1185 * internal memory. 1186 */ 1187 for (i = BGE_STATS_BLOCK; 1188 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1189 BGE_MEMWIN_WRITE(sc, i, 0); 1190 1191 for (i = BGE_STATUS_BLOCK; 1192 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1193 BGE_MEMWIN_WRITE(sc, i, 0); 1194 1195 /* 1196 * Set up the PCI DMA control register. 1197 */ 1198 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1199 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1200 if (sc->bge_flags & BGE_FLAG_PCIE) { 1201 /* Read watermark not used, 128 bytes for write. */ 1202 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1203 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1204 if (BGE_IS_5714_FAMILY(sc)) { 1205 /* 256 bytes for read and write. */ 1206 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1207 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1208 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1209 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1210 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1211 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1212 /* 1536 bytes for read, 384 bytes for write. */ 1213 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1214 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1215 } else { 1216 /* 384 bytes for read and write. */ 1217 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1218 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1219 0x0F; 1220 } 1221 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1222 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1223 uint32_t tmp; 1224 1225 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1226 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1227 if (tmp == 6 || tmp == 7) 1228 dma_rw_ctl |= 1229 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1230 1231 /* Set PCI-X DMA write workaround. */ 1232 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1233 } 1234 } else { 1235 /* Conventional PCI bus: 256 bytes for read and write. */ 1236 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1237 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1238 1239 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1240 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1241 dma_rw_ctl |= 0x0F; 1242 } 1243 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1244 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1245 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1246 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1247 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1248 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1249 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1250 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1251 1252 /* 1253 * Set up general mode register. 1254 */ 1255 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1256 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1257 BGE_MODECTL_TX_NO_PHDR_CSUM); 1258 1259 /* 1260 * Tell the firmware the driver is running 1261 */ 1262 if (sc->bge_asf_mode & ASF_STACKUP) 1263 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1264 1265 /* 1266 * Disable memory write invalidate. Apparently it is not supported 1267 * properly by these devices. 1268 */ 1269 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1270 1271 /* Set the timer prescaler (always 66Mhz) */ 1272 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1273 1274 return (0); 1275 } 1276 1277 static int 1278 bge_blockinit(struct bge_softc *sc) 1279 { 1280 struct bge_rcb *rcb; 1281 bus_size_t vrcb; 1282 bge_hostaddr taddr; 1283 uint32_t val; 1284 int i; 1285 1286 /* 1287 * Initialize the memory window pointer register so that 1288 * we can access the first 32K of internal NIC RAM. This will 1289 * allow us to set up the TX send ring RCBs and the RX return 1290 * ring RCBs, plus other things which live in NIC memory. 1291 */ 1292 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1293 1294 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1295 1296 if (!(BGE_IS_5705_PLUS(sc))) { 1297 /* Configure mbuf memory pool */ 1298 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1299 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1300 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1301 else 1302 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1303 1304 /* Configure DMA resource pool */ 1305 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1306 BGE_DMA_DESCRIPTORS); 1307 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1308 } 1309 1310 /* Configure mbuf pool watermarks */ 1311 if (BGE_IS_5705_PLUS(sc)) { 1312 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1313 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1314 } else { 1315 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1316 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1317 } 1318 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1319 1320 /* Configure DMA resource watermarks */ 1321 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1322 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1323 1324 /* Enable buffer manager */ 1325 if (!(BGE_IS_5705_PLUS(sc))) { 1326 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1327 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1328 1329 /* Poll for buffer manager start indication */ 1330 for (i = 0; i < BGE_TIMEOUT; i++) { 1331 DELAY(10); 1332 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1333 break; 1334 } 1335 1336 if (i == BGE_TIMEOUT) { 1337 device_printf(sc->bge_dev, 1338 "buffer manager failed to start\n"); 1339 return (ENXIO); 1340 } 1341 } 1342 1343 /* Enable flow-through queues */ 1344 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1345 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1346 1347 /* Wait until queue initialization is complete */ 1348 for (i = 0; i < BGE_TIMEOUT; i++) { 1349 DELAY(10); 1350 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1351 break; 1352 } 1353 1354 if (i == BGE_TIMEOUT) { 1355 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1356 return (ENXIO); 1357 } 1358 1359 /* Initialize the standard RX ring control block */ 1360 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1361 rcb->bge_hostaddr.bge_addr_lo = 1362 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1363 rcb->bge_hostaddr.bge_addr_hi = 1364 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1365 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1366 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1367 if (BGE_IS_5705_PLUS(sc)) 1368 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1369 else 1370 rcb->bge_maxlen_flags = 1371 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1372 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1373 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1374 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1375 1376 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1377 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1378 1379 /* 1380 * Initialize the jumbo RX ring control block 1381 * We set the 'ring disabled' bit in the flags 1382 * field until we're actually ready to start 1383 * using this ring (i.e. once we set the MTU 1384 * high enough to require it). 1385 */ 1386 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1387 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1388 1389 rcb->bge_hostaddr.bge_addr_lo = 1390 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1391 rcb->bge_hostaddr.bge_addr_hi = 1392 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1393 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1394 sc->bge_cdata.bge_rx_jumbo_ring_map, 1395 BUS_DMASYNC_PREREAD); 1396 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1397 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1398 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1399 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1400 rcb->bge_hostaddr.bge_addr_hi); 1401 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1402 rcb->bge_hostaddr.bge_addr_lo); 1403 1404 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1405 rcb->bge_maxlen_flags); 1406 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1407 1408 /* Set up dummy disabled mini ring RCB */ 1409 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1410 rcb->bge_maxlen_flags = 1411 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1412 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1413 rcb->bge_maxlen_flags); 1414 } 1415 1416 /* 1417 * Set the BD ring replentish thresholds. The recommended 1418 * values are 1/8th the number of descriptors allocated to 1419 * each ring. 1420 * XXX The 5754 requires a lower threshold, so it might be a 1421 * requirement of all 575x family chips. The Linux driver sets 1422 * the lower threshold for all 5705 family chips as well, but there 1423 * are reports that it might not need to be so strict. 1424 */ 1425 if (BGE_IS_5705_PLUS(sc)) 1426 val = 8; 1427 else 1428 val = BGE_STD_RX_RING_CNT / 8; 1429 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1430 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1431 1432 /* 1433 * Disable all unused send rings by setting the 'ring disabled' 1434 * bit in the flags field of all the TX send ring control blocks. 1435 * These are located in NIC memory. 1436 */ 1437 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1438 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1439 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1440 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1441 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1442 vrcb += sizeof(struct bge_rcb); 1443 } 1444 1445 /* Configure TX RCB 0 (we use only the first ring) */ 1446 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1447 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1448 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1449 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1450 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1451 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1452 if (!(BGE_IS_5705_PLUS(sc))) 1453 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1454 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1455 1456 /* Disable all unused RX return rings */ 1457 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1458 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1459 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1460 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1461 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1462 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1463 BGE_RCB_FLAG_RING_DISABLED)); 1464 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1465 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1466 (i * (sizeof(uint64_t))), 0); 1467 vrcb += sizeof(struct bge_rcb); 1468 } 1469 1470 /* Initialize RX ring indexes */ 1471 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1472 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1473 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1474 1475 /* 1476 * Set up RX return ring 0 1477 * Note that the NIC address for RX return rings is 0x00000000. 1478 * The return rings live entirely within the host, so the 1479 * nicaddr field in the RCB isn't used. 1480 */ 1481 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1482 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1483 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1484 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1485 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); 1486 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1487 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1488 1489 /* Set random backoff seed for TX */ 1490 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1491 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1492 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1493 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1494 BGE_TX_BACKOFF_SEED_MASK); 1495 1496 /* Set inter-packet gap */ 1497 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1498 1499 /* 1500 * Specify which ring to use for packets that don't match 1501 * any RX rules. 1502 */ 1503 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1504 1505 /* 1506 * Configure number of RX lists. One interrupt distribution 1507 * list, sixteen active lists, one bad frames class. 1508 */ 1509 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1510 1511 /* Inialize RX list placement stats mask. */ 1512 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1513 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1514 1515 /* Disable host coalescing until we get it set up */ 1516 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1517 1518 /* Poll to make sure it's shut down. */ 1519 for (i = 0; i < BGE_TIMEOUT; i++) { 1520 DELAY(10); 1521 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1522 break; 1523 } 1524 1525 if (i == BGE_TIMEOUT) { 1526 device_printf(sc->bge_dev, 1527 "host coalescing engine failed to idle\n"); 1528 return (ENXIO); 1529 } 1530 1531 /* Set up host coalescing defaults */ 1532 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1533 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1534 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1535 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1536 if (!(BGE_IS_5705_PLUS(sc))) { 1537 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1538 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1539 } 1540 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1541 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1542 1543 /* Set up address of statistics block */ 1544 if (!(BGE_IS_5705_PLUS(sc))) { 1545 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1546 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1547 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1548 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1549 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1550 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1551 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1552 } 1553 1554 /* Set up address of status block */ 1555 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1556 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1557 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1558 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1559 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1560 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1561 1562 /* Turn on host coalescing state machine */ 1563 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1564 1565 /* Turn on RX BD completion state machine and enable attentions */ 1566 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1567 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1568 1569 /* Turn on RX list placement state machine */ 1570 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1571 1572 /* Turn on RX list selector state machine. */ 1573 if (!(BGE_IS_5705_PLUS(sc))) 1574 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1575 1576 /* Turn on DMA, clear stats */ 1577 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB | 1578 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR | 1579 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB | 1580 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB | 1581 ((sc->bge_flags & BGE_FLAG_TBI) ? 1582 BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1583 1584 /* Set misc. local control, enable interrupts on attentions */ 1585 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1586 1587 #ifdef notdef 1588 /* Assert GPIO pins for PHY reset */ 1589 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 1590 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 1591 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 1592 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 1593 #endif 1594 1595 /* Turn on DMA completion state machine */ 1596 if (!(BGE_IS_5705_PLUS(sc))) 1597 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1598 1599 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 1600 1601 /* Enable host coalescing bug fix. */ 1602 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 1603 sc->bge_asicrev == BGE_ASICREV_BCM5787) 1604 val |= 1 << 29; 1605 1606 /* Turn on write DMA state machine */ 1607 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1608 1609 /* Turn on read DMA state machine */ 1610 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1611 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS); 1612 1613 /* Turn on RX data completion state machine */ 1614 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1615 1616 /* Turn on RX BD initiator state machine */ 1617 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1618 1619 /* Turn on RX data and RX BD initiator state machine */ 1620 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1621 1622 /* Turn on Mbuf cluster free state machine */ 1623 if (!(BGE_IS_5705_PLUS(sc))) 1624 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1625 1626 /* Turn on send BD completion state machine */ 1627 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1628 1629 /* Turn on send data completion state machine */ 1630 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1631 1632 /* Turn on send data initiator state machine */ 1633 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1634 1635 /* Turn on send BD initiator state machine */ 1636 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1637 1638 /* Turn on send BD selector state machine */ 1639 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1640 1641 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1642 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1643 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 1644 1645 /* ack/clear link change events */ 1646 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1647 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1648 BGE_MACSTAT_LINK_CHANGED); 1649 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1650 1651 /* Enable PHY auto polling (for MII/GMII only) */ 1652 if (sc->bge_flags & BGE_FLAG_TBI) { 1653 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1654 } else { 1655 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 1656 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1657 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 1658 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1659 BGE_EVTENB_MI_INTERRUPT); 1660 } 1661 1662 /* 1663 * Clear any pending link state attention. 1664 * Otherwise some link state change events may be lost until attention 1665 * is cleared by bge_intr() -> bge_link_upd() sequence. 1666 * It's not necessary on newer BCM chips - perhaps enabling link 1667 * state change attentions implies clearing pending attention. 1668 */ 1669 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1670 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1671 BGE_MACSTAT_LINK_CHANGED); 1672 1673 /* Enable link state change attentions. */ 1674 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1675 1676 return (0); 1677 } 1678 1679 const struct bge_revision * 1680 bge_lookup_rev(uint32_t chipid) 1681 { 1682 const struct bge_revision *br; 1683 1684 for (br = bge_revisions; br->br_name != NULL; br++) { 1685 if (br->br_chipid == chipid) 1686 return (br); 1687 } 1688 1689 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1690 if (br->br_chipid == BGE_ASICREV(chipid)) 1691 return (br); 1692 } 1693 1694 return (NULL); 1695 } 1696 1697 const struct bge_vendor * 1698 bge_lookup_vendor(uint16_t vid) 1699 { 1700 const struct bge_vendor *v; 1701 1702 for (v = bge_vendors; v->v_name != NULL; v++) 1703 if (v->v_id == vid) 1704 return (v); 1705 1706 panic("%s: unknown vendor %d", __func__, vid); 1707 return (NULL); 1708 } 1709 1710 /* 1711 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1712 * against our list and return its name if we find a match. 1713 * 1714 * Note that since the Broadcom controller contains VPD support, we 1715 * try to get the device name string from the controller itself instead 1716 * of the compiled-in string. It guarantees we'll always announce the 1717 * right product name. We fall back to the compiled-in string when 1718 * VPD is unavailable or corrupt. 1719 */ 1720 static int 1721 bge_probe(device_t dev) 1722 { 1723 struct bge_type *t = bge_devs; 1724 struct bge_softc *sc = device_get_softc(dev); 1725 uint16_t vid, did; 1726 1727 sc->bge_dev = dev; 1728 vid = pci_get_vendor(dev); 1729 did = pci_get_device(dev); 1730 while(t->bge_vid != 0) { 1731 if ((vid == t->bge_vid) && (did == t->bge_did)) { 1732 char model[64], buf[96]; 1733 const struct bge_revision *br; 1734 const struct bge_vendor *v; 1735 uint32_t id; 1736 1737 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1738 BGE_PCIMISCCTL_ASICREV; 1739 br = bge_lookup_rev(id); 1740 v = bge_lookup_vendor(vid); 1741 { 1742 #if __FreeBSD_version > 700024 1743 const char *pname; 1744 1745 if (pci_get_vpd_ident(dev, &pname) == 0) 1746 snprintf(model, 64, "%s", pname); 1747 else 1748 #endif 1749 snprintf(model, 64, "%s %s", 1750 v->v_name, 1751 br != NULL ? br->br_name : 1752 "NetXtreme Ethernet Controller"); 1753 } 1754 snprintf(buf, 96, "%s, %sASIC rev. %#04x", model, 1755 br != NULL ? "" : "unknown ", id >> 16); 1756 device_set_desc_copy(dev, buf); 1757 if (pci_get_subvendor(dev) == DELL_VENDORID) 1758 sc->bge_flags |= BGE_FLAG_NO_3LED; 1759 if (did == BCOM_DEVICEID_BCM5755M) 1760 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM; 1761 return (0); 1762 } 1763 t++; 1764 } 1765 1766 return (ENXIO); 1767 } 1768 1769 static void 1770 bge_dma_free(struct bge_softc *sc) 1771 { 1772 int i; 1773 1774 /* Destroy DMA maps for RX buffers. */ 1775 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1776 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1777 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1778 sc->bge_cdata.bge_rx_std_dmamap[i]); 1779 } 1780 1781 /* Destroy DMA maps for jumbo RX buffers. */ 1782 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1783 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1784 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1785 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1786 } 1787 1788 /* Destroy DMA maps for TX buffers. */ 1789 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1790 if (sc->bge_cdata.bge_tx_dmamap[i]) 1791 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1792 sc->bge_cdata.bge_tx_dmamap[i]); 1793 } 1794 1795 if (sc->bge_cdata.bge_mtag) 1796 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1797 1798 1799 /* Destroy standard RX ring. */ 1800 if (sc->bge_cdata.bge_rx_std_ring_map) 1801 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1802 sc->bge_cdata.bge_rx_std_ring_map); 1803 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 1804 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1805 sc->bge_ldata.bge_rx_std_ring, 1806 sc->bge_cdata.bge_rx_std_ring_map); 1807 1808 if (sc->bge_cdata.bge_rx_std_ring_tag) 1809 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1810 1811 /* Destroy jumbo RX ring. */ 1812 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 1813 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1814 sc->bge_cdata.bge_rx_jumbo_ring_map); 1815 1816 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 1817 sc->bge_ldata.bge_rx_jumbo_ring) 1818 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1819 sc->bge_ldata.bge_rx_jumbo_ring, 1820 sc->bge_cdata.bge_rx_jumbo_ring_map); 1821 1822 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1823 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1824 1825 /* Destroy RX return ring. */ 1826 if (sc->bge_cdata.bge_rx_return_ring_map) 1827 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1828 sc->bge_cdata.bge_rx_return_ring_map); 1829 1830 if (sc->bge_cdata.bge_rx_return_ring_map && 1831 sc->bge_ldata.bge_rx_return_ring) 1832 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1833 sc->bge_ldata.bge_rx_return_ring, 1834 sc->bge_cdata.bge_rx_return_ring_map); 1835 1836 if (sc->bge_cdata.bge_rx_return_ring_tag) 1837 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1838 1839 /* Destroy TX ring. */ 1840 if (sc->bge_cdata.bge_tx_ring_map) 1841 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 1842 sc->bge_cdata.bge_tx_ring_map); 1843 1844 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 1845 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 1846 sc->bge_ldata.bge_tx_ring, 1847 sc->bge_cdata.bge_tx_ring_map); 1848 1849 if (sc->bge_cdata.bge_tx_ring_tag) 1850 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 1851 1852 /* Destroy status block. */ 1853 if (sc->bge_cdata.bge_status_map) 1854 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 1855 sc->bge_cdata.bge_status_map); 1856 1857 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 1858 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 1859 sc->bge_ldata.bge_status_block, 1860 sc->bge_cdata.bge_status_map); 1861 1862 if (sc->bge_cdata.bge_status_tag) 1863 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 1864 1865 /* Destroy statistics block. */ 1866 if (sc->bge_cdata.bge_stats_map) 1867 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 1868 sc->bge_cdata.bge_stats_map); 1869 1870 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 1871 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 1872 sc->bge_ldata.bge_stats, 1873 sc->bge_cdata.bge_stats_map); 1874 1875 if (sc->bge_cdata.bge_stats_tag) 1876 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 1877 1878 /* Destroy the parent tag. */ 1879 if (sc->bge_cdata.bge_parent_tag) 1880 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 1881 } 1882 1883 static int 1884 bge_dma_alloc(device_t dev) 1885 { 1886 struct bge_dmamap_arg ctx; 1887 struct bge_softc *sc; 1888 int i, error; 1889 1890 sc = device_get_softc(dev); 1891 1892 /* 1893 * Allocate the parent bus DMA tag appropriate for PCI. 1894 */ 1895 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), /* parent */ 1896 1, 0, /* alignment, boundary */ 1897 BUS_SPACE_MAXADDR, /* lowaddr */ 1898 BUS_SPACE_MAXADDR, /* highaddr */ 1899 NULL, NULL, /* filter, filterarg */ 1900 MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ 1901 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1902 0, /* flags */ 1903 NULL, NULL, /* lockfunc, lockarg */ 1904 &sc->bge_cdata.bge_parent_tag); 1905 1906 if (error != 0) { 1907 device_printf(sc->bge_dev, 1908 "could not allocate parent dma tag\n"); 1909 return (ENOMEM); 1910 } 1911 1912 /* 1913 * Create tag for RX mbufs. 1914 */ 1915 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 1916 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1917 NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES, 1918 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag); 1919 1920 if (error) { 1921 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 1922 return (ENOMEM); 1923 } 1924 1925 /* Create DMA maps for RX buffers. */ 1926 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1927 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1928 &sc->bge_cdata.bge_rx_std_dmamap[i]); 1929 if (error) { 1930 device_printf(sc->bge_dev, 1931 "can't create DMA map for RX\n"); 1932 return (ENOMEM); 1933 } 1934 } 1935 1936 /* Create DMA maps for TX buffers. */ 1937 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1938 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1939 &sc->bge_cdata.bge_tx_dmamap[i]); 1940 if (error) { 1941 device_printf(sc->bge_dev, 1942 "can't create DMA map for RX\n"); 1943 return (ENOMEM); 1944 } 1945 } 1946 1947 /* Create tag for standard RX ring. */ 1948 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1949 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1950 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 1951 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 1952 1953 if (error) { 1954 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 1955 return (ENOMEM); 1956 } 1957 1958 /* Allocate DMA'able memory for standard RX ring. */ 1959 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 1960 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 1961 &sc->bge_cdata.bge_rx_std_ring_map); 1962 if (error) 1963 return (ENOMEM); 1964 1965 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1966 1967 /* Load the address of the standard RX ring. */ 1968 ctx.bge_maxsegs = 1; 1969 ctx.sc = sc; 1970 1971 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 1972 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 1973 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1974 1975 if (error) 1976 return (ENOMEM); 1977 1978 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 1979 1980 /* Create tags for jumbo mbufs. */ 1981 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1982 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1983 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1984 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 1985 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 1986 if (error) { 1987 device_printf(sc->bge_dev, 1988 "could not allocate jumbo dma tag\n"); 1989 return (ENOMEM); 1990 } 1991 1992 /* Create tag for jumbo RX ring. */ 1993 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1994 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1995 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 1996 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 1997 1998 if (error) { 1999 device_printf(sc->bge_dev, 2000 "could not allocate jumbo ring dma tag\n"); 2001 return (ENOMEM); 2002 } 2003 2004 /* Allocate DMA'able memory for jumbo RX ring. */ 2005 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2006 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, 2007 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2008 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2009 if (error) 2010 return (ENOMEM); 2011 2012 /* Load the address of the jumbo RX ring. */ 2013 ctx.bge_maxsegs = 1; 2014 ctx.sc = sc; 2015 2016 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2017 sc->bge_cdata.bge_rx_jumbo_ring_map, 2018 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2019 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2020 2021 if (error) 2022 return (ENOMEM); 2023 2024 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2025 2026 /* Create DMA maps for jumbo RX buffers. */ 2027 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2028 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2029 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2030 if (error) { 2031 device_printf(sc->bge_dev, 2032 "can't create DMA map for jumbo RX\n"); 2033 return (ENOMEM); 2034 } 2035 } 2036 2037 } 2038 2039 /* Create tag for RX return ring. */ 2040 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2041 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2042 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2043 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2044 2045 if (error) { 2046 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2047 return (ENOMEM); 2048 } 2049 2050 /* Allocate DMA'able memory for RX return ring. */ 2051 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2052 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2053 &sc->bge_cdata.bge_rx_return_ring_map); 2054 if (error) 2055 return (ENOMEM); 2056 2057 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2058 BGE_RX_RTN_RING_SZ(sc)); 2059 2060 /* Load the address of the RX return ring. */ 2061 ctx.bge_maxsegs = 1; 2062 ctx.sc = sc; 2063 2064 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2065 sc->bge_cdata.bge_rx_return_ring_map, 2066 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2067 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2068 2069 if (error) 2070 return (ENOMEM); 2071 2072 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2073 2074 /* Create tag for TX ring. */ 2075 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2076 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2077 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2078 &sc->bge_cdata.bge_tx_ring_tag); 2079 2080 if (error) { 2081 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2082 return (ENOMEM); 2083 } 2084 2085 /* Allocate DMA'able memory for TX ring. */ 2086 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2087 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2088 &sc->bge_cdata.bge_tx_ring_map); 2089 if (error) 2090 return (ENOMEM); 2091 2092 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2093 2094 /* Load the address of the TX ring. */ 2095 ctx.bge_maxsegs = 1; 2096 ctx.sc = sc; 2097 2098 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2099 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2100 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2101 2102 if (error) 2103 return (ENOMEM); 2104 2105 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2106 2107 /* Create tag for status block. */ 2108 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2109 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2110 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 2111 NULL, NULL, &sc->bge_cdata.bge_status_tag); 2112 2113 if (error) { 2114 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2115 return (ENOMEM); 2116 } 2117 2118 /* Allocate DMA'able memory for status block. */ 2119 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2120 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2121 &sc->bge_cdata.bge_status_map); 2122 if (error) 2123 return (ENOMEM); 2124 2125 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2126 2127 /* Load the address of the status block. */ 2128 ctx.sc = sc; 2129 ctx.bge_maxsegs = 1; 2130 2131 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2132 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2133 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2134 2135 if (error) 2136 return (ENOMEM); 2137 2138 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2139 2140 /* Create tag for statistics block. */ 2141 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2142 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2143 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2144 &sc->bge_cdata.bge_stats_tag); 2145 2146 if (error) { 2147 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2148 return (ENOMEM); 2149 } 2150 2151 /* Allocate DMA'able memory for statistics block. */ 2152 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2153 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2154 &sc->bge_cdata.bge_stats_map); 2155 if (error) 2156 return (ENOMEM); 2157 2158 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2159 2160 /* Load the address of the statstics block. */ 2161 ctx.sc = sc; 2162 ctx.bge_maxsegs = 1; 2163 2164 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2165 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2166 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2167 2168 if (error) 2169 return (ENOMEM); 2170 2171 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2172 2173 return (0); 2174 } 2175 2176 #if __FreeBSD_version > 602105 2177 /* 2178 * Return true if this device has more than one port. 2179 */ 2180 static int 2181 bge_has_multiple_ports(struct bge_softc *sc) 2182 { 2183 device_t dev = sc->bge_dev; 2184 u_int b, d, f, fscan, s; 2185 2186 d = pci_get_domain(dev); 2187 b = pci_get_bus(dev); 2188 s = pci_get_slot(dev); 2189 f = pci_get_function(dev); 2190 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2191 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2192 return (1); 2193 return (0); 2194 } 2195 2196 /* 2197 * Return true if MSI can be used with this device. 2198 */ 2199 static int 2200 bge_can_use_msi(struct bge_softc *sc) 2201 { 2202 int can_use_msi = 0; 2203 2204 switch (sc->bge_asicrev) { 2205 case BGE_ASICREV_BCM5714: 2206 /* 2207 * Apparently, MSI doesn't work when this chip is configured 2208 * in single-port mode. 2209 */ 2210 if (bge_has_multiple_ports(sc)) 2211 can_use_msi = 1; 2212 break; 2213 case BGE_ASICREV_BCM5750: 2214 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2215 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2216 can_use_msi = 1; 2217 break; 2218 case BGE_ASICREV_BCM5752: 2219 case BGE_ASICREV_BCM5780: 2220 can_use_msi = 1; 2221 break; 2222 } 2223 return (can_use_msi); 2224 } 2225 #endif 2226 2227 static int 2228 bge_attach(device_t dev) 2229 { 2230 struct ifnet *ifp; 2231 struct bge_softc *sc; 2232 uint32_t hwcfg = 0; 2233 uint32_t mac_tmp = 0; 2234 u_char eaddr[ETHER_ADDR_LEN]; 2235 int error, reg, rid, trys; 2236 2237 sc = device_get_softc(dev); 2238 sc->bge_dev = dev; 2239 2240 /* 2241 * Map control/status registers. 2242 */ 2243 pci_enable_busmaster(dev); 2244 2245 rid = BGE_PCI_BAR0; 2246 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2247 RF_ACTIVE | PCI_RF_DENSE); 2248 2249 if (sc->bge_res == NULL) { 2250 device_printf (sc->bge_dev, "couldn't map memory\n"); 2251 error = ENXIO; 2252 goto fail; 2253 } 2254 2255 sc->bge_btag = rman_get_bustag(sc->bge_res); 2256 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2257 2258 /* Save ASIC rev. */ 2259 2260 sc->bge_chipid = 2261 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2262 BGE_PCIMISCCTL_ASICREV; 2263 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2264 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2265 2266 if (bge_has_eeprom(sc)) 2267 sc->bge_flags |= BGE_FLAG_EEPROM; 2268 2269 /* Save chipset family. */ 2270 switch (sc->bge_asicrev) { 2271 case BGE_ASICREV_BCM5700: 2272 case BGE_ASICREV_BCM5701: 2273 case BGE_ASICREV_BCM5703: 2274 case BGE_ASICREV_BCM5704: 2275 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2276 break; 2277 case BGE_ASICREV_BCM5714_A0: 2278 case BGE_ASICREV_BCM5780: 2279 case BGE_ASICREV_BCM5714: 2280 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; 2281 /* FALLTHRU */ 2282 case BGE_ASICREV_BCM5750: 2283 case BGE_ASICREV_BCM5752: 2284 case BGE_ASICREV_BCM5755: 2285 case BGE_ASICREV_BCM5787: 2286 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2287 /* FALLTHRU */ 2288 case BGE_ASICREV_BCM5705: 2289 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2290 break; 2291 } 2292 2293 /* Set various bug flags. */ 2294 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2295 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2296 sc->bge_flags |= BGE_FLAG_CRC_BUG; 2297 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2298 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2299 sc->bge_flags |= BGE_FLAG_ADC_BUG; 2300 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2301 sc->bge_flags |= BGE_FLAG_5704_A0_BUG; 2302 if (BGE_IS_5705_PLUS(sc) && 2303 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 2304 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2305 sc->bge_asicrev == BGE_ASICREV_BCM5787) 2306 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2307 else 2308 sc->bge_flags |= BGE_FLAG_BER_BUG; 2309 } 2310 2311 /* 2312 * Check if this is a PCI-X or PCI Express device. 2313 */ 2314 #if __FreeBSD_version > 602101 2315 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 2316 /* 2317 * Found a PCI Express capabilities register, this 2318 * must be a PCI Express device. 2319 */ 2320 if (reg != 0) 2321 sc->bge_flags |= BGE_FLAG_PCIE; 2322 } else if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { 2323 if (reg != 0) 2324 sc->bge_flags |= BGE_FLAG_PCIX; 2325 } 2326 2327 #else 2328 if (BGE_IS_5705_PLUS(sc)) { 2329 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4); 2330 if ((reg & 0xFF) == BGE_PCIE_CAPID) 2331 sc->bge_flags |= BGE_FLAG_PCIE; 2332 } else { 2333 /* 2334 * Check if the device is in PCI-X Mode. 2335 * (This bit is not valid on PCI Express controllers.) 2336 */ 2337 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 2338 BGE_PCISTATE_PCI_BUSMODE) == 0) 2339 sc->bge_flags |= BGE_FLAG_PCIX; 2340 } 2341 #endif 2342 2343 #if __FreeBSD_version > 602105 2344 { 2345 int msicount; 2346 2347 /* 2348 * Allocate the interrupt, using MSI if possible. These devices 2349 * support 8 MSI messages, but only the first one is used in 2350 * normal operation. 2351 */ 2352 if (bge_can_use_msi(sc)) { 2353 msicount = pci_msi_count(dev); 2354 if (msicount > 1) 2355 msicount = 1; 2356 } else 2357 msicount = 0; 2358 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2359 rid = 1; 2360 sc->bge_flags |= BGE_FLAG_MSI; 2361 } else 2362 rid = 0; 2363 } 2364 #else 2365 rid = 0; 2366 #endif 2367 2368 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2369 RF_SHAREABLE | RF_ACTIVE); 2370 2371 if (sc->bge_irq == NULL) { 2372 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2373 error = ENXIO; 2374 goto fail; 2375 } 2376 2377 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2378 2379 /* Try to reset the chip. */ 2380 if (bge_reset(sc)) { 2381 device_printf(sc->bge_dev, "chip reset failed\n"); 2382 error = ENXIO; 2383 goto fail; 2384 } 2385 2386 sc->bge_asf_mode = 0; 2387 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2388 == BGE_MAGIC_NUMBER)) { 2389 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2390 & BGE_HWCFG_ASF) { 2391 sc->bge_asf_mode |= ASF_ENABLE; 2392 sc->bge_asf_mode |= ASF_STACKUP; 2393 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) { 2394 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2395 } 2396 } 2397 } 2398 2399 /* Try to reset the chip again the nice way. */ 2400 bge_stop_fw(sc); 2401 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2402 if (bge_reset(sc)) { 2403 device_printf(sc->bge_dev, "chip reset failed\n"); 2404 error = ENXIO; 2405 goto fail; 2406 } 2407 2408 bge_sig_legacy(sc, BGE_RESET_STOP); 2409 bge_sig_post_reset(sc, BGE_RESET_STOP); 2410 2411 if (bge_chipinit(sc)) { 2412 device_printf(sc->bge_dev, "chip initialization failed\n"); 2413 error = ENXIO; 2414 goto fail; 2415 } 2416 2417 #ifdef __sparc64__ 2418 if ((sc->bge_flags & BGE_FLAG_EEPROM) == 0) 2419 OF_getetheraddr(dev, eaddr); 2420 else 2421 #endif 2422 { 2423 mac_tmp = bge_readmem_ind(sc, 0x0C14); 2424 if ((mac_tmp >> 16) == 0x484B) { 2425 eaddr[0] = (u_char)(mac_tmp >> 8); 2426 eaddr[1] = (u_char)mac_tmp; 2427 mac_tmp = bge_readmem_ind(sc, 0x0C18); 2428 eaddr[2] = (u_char)(mac_tmp >> 24); 2429 eaddr[3] = (u_char)(mac_tmp >> 16); 2430 eaddr[4] = (u_char)(mac_tmp >> 8); 2431 eaddr[5] = (u_char)mac_tmp; 2432 } else if (bge_read_eeprom(sc, eaddr, 2433 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2434 device_printf(sc->bge_dev, 2435 "failed to read station address\n"); 2436 error = ENXIO; 2437 goto fail; 2438 } 2439 } 2440 2441 /* 5705 limits RX return ring to 512 entries. */ 2442 if (BGE_IS_5705_PLUS(sc)) 2443 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2444 else 2445 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2446 2447 if (bge_dma_alloc(dev)) { 2448 device_printf(sc->bge_dev, 2449 "failed to allocate DMA resources\n"); 2450 error = ENXIO; 2451 goto fail; 2452 } 2453 2454 /* Set default tuneable values. */ 2455 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2456 sc->bge_rx_coal_ticks = 150; 2457 sc->bge_tx_coal_ticks = 150; 2458 sc->bge_rx_max_coal_bds = 10; 2459 sc->bge_tx_max_coal_bds = 10; 2460 2461 /* Set up ifnet structure */ 2462 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2463 if (ifp == NULL) { 2464 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2465 error = ENXIO; 2466 goto fail; 2467 } 2468 ifp->if_softc = sc; 2469 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2470 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2471 ifp->if_ioctl = bge_ioctl; 2472 ifp->if_start = bge_start; 2473 ifp->if_init = bge_init; 2474 ifp->if_mtu = ETHERMTU; 2475 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 2476 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2477 IFQ_SET_READY(&ifp->if_snd); 2478 ifp->if_hwassist = BGE_CSUM_FEATURES; 2479 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2480 IFCAP_VLAN_MTU; 2481 #ifdef IFCAP_VLAN_HWCSUM 2482 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 2483 #endif 2484 ifp->if_capenable = ifp->if_capabilities; 2485 #ifdef DEVICE_POLLING 2486 ifp->if_capabilities |= IFCAP_POLLING; 2487 #endif 2488 2489 /* 2490 * 5700 B0 chips do not support checksumming correctly due 2491 * to hardware bugs. 2492 */ 2493 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2494 ifp->if_capabilities &= ~IFCAP_HWCSUM; 2495 ifp->if_capenable &= IFCAP_HWCSUM; 2496 ifp->if_hwassist = 0; 2497 } 2498 2499 /* 2500 * Figure out what sort of media we have by checking the 2501 * hardware config word in the first 32k of NIC internal memory, 2502 * or fall back to examining the EEPROM if necessary. 2503 * Note: on some BCM5700 cards, this value appears to be unset. 2504 * If that's the case, we have to rely on identifying the NIC 2505 * by its PCI subsystem ID, as we do below for the SysKonnect 2506 * SK-9D41. 2507 */ 2508 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2509 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2510 else if (sc->bge_flags & BGE_FLAG_EEPROM) { 2511 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2512 sizeof(hwcfg))) { 2513 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2514 error = ENXIO; 2515 goto fail; 2516 } 2517 hwcfg = ntohl(hwcfg); 2518 } 2519 2520 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2521 sc->bge_flags |= BGE_FLAG_TBI; 2522 2523 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2524 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2525 sc->bge_flags |= BGE_FLAG_TBI; 2526 2527 if (sc->bge_flags & BGE_FLAG_TBI) { 2528 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2529 bge_ifmedia_sts); 2530 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 2531 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2532 0, NULL); 2533 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2534 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2535 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2536 } else { 2537 /* 2538 * Do transceiver setup and tell the firmware the 2539 * driver is down so we can try to get access the 2540 * probe if ASF is running. Retry a couple of times 2541 * if we get a conflict with the ASF firmware accessing 2542 * the PHY. 2543 */ 2544 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2545 again: 2546 bge_asf_driver_up(sc); 2547 2548 trys = 0; 2549 if (mii_phy_probe(dev, &sc->bge_miibus, 2550 bge_ifmedia_upd, bge_ifmedia_sts)) { 2551 if (trys++ < 4) { 2552 device_printf(sc->bge_dev, "Try again\n"); 2553 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 2554 BMCR_RESET); 2555 goto again; 2556 } 2557 2558 device_printf(sc->bge_dev, "MII without any PHY!\n"); 2559 error = ENXIO; 2560 goto fail; 2561 } 2562 2563 /* 2564 * Now tell the firmware we are going up after probing the PHY 2565 */ 2566 if (sc->bge_asf_mode & ASF_STACKUP) 2567 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2568 } 2569 2570 /* 2571 * When using the BCM5701 in PCI-X mode, data corruption has 2572 * been observed in the first few bytes of some received packets. 2573 * Aligning the packet buffer in memory eliminates the corruption. 2574 * Unfortunately, this misaligns the packet payloads. On platforms 2575 * which do not support unaligned accesses, we will realign the 2576 * payloads by copying the received packets. 2577 */ 2578 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2579 sc->bge_flags & BGE_FLAG_PCIX) 2580 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2581 2582 /* 2583 * Call MI attach routine. 2584 */ 2585 ether_ifattach(ifp, eaddr); 2586 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 2587 2588 /* 2589 * Hookup IRQ last. 2590 */ 2591 #if __FreeBSD_version > 700030 2592 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2593 NULL, bge_intr, sc, &sc->bge_intrhand); 2594 #else 2595 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2596 bge_intr, sc, &sc->bge_intrhand); 2597 #endif 2598 2599 if (error) { 2600 bge_detach(dev); 2601 device_printf(sc->bge_dev, "couldn't set up irq\n"); 2602 } 2603 2604 bge_add_sysctls(sc); 2605 2606 return (0); 2607 2608 fail: 2609 bge_release_resources(sc); 2610 2611 return (error); 2612 } 2613 2614 static int 2615 bge_detach(device_t dev) 2616 { 2617 struct bge_softc *sc; 2618 struct ifnet *ifp; 2619 2620 sc = device_get_softc(dev); 2621 ifp = sc->bge_ifp; 2622 2623 #ifdef DEVICE_POLLING 2624 if (ifp->if_capenable & IFCAP_POLLING) 2625 ether_poll_deregister(ifp); 2626 #endif 2627 2628 BGE_LOCK(sc); 2629 bge_stop(sc); 2630 bge_reset(sc); 2631 BGE_UNLOCK(sc); 2632 2633 callout_drain(&sc->bge_stat_ch); 2634 2635 ether_ifdetach(ifp); 2636 2637 if (sc->bge_flags & BGE_FLAG_TBI) { 2638 ifmedia_removeall(&sc->bge_ifmedia); 2639 } else { 2640 bus_generic_detach(dev); 2641 device_delete_child(dev, sc->bge_miibus); 2642 } 2643 2644 bge_release_resources(sc); 2645 2646 return (0); 2647 } 2648 2649 static void 2650 bge_release_resources(struct bge_softc *sc) 2651 { 2652 device_t dev; 2653 2654 dev = sc->bge_dev; 2655 2656 if (sc->bge_intrhand != NULL) 2657 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2658 2659 if (sc->bge_irq != NULL) 2660 bus_release_resource(dev, SYS_RES_IRQ, 2661 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 2662 2663 #if __FreeBSD_version > 602105 2664 if (sc->bge_flags & BGE_FLAG_MSI) 2665 pci_release_msi(dev); 2666 #endif 2667 2668 if (sc->bge_res != NULL) 2669 bus_release_resource(dev, SYS_RES_MEMORY, 2670 BGE_PCI_BAR0, sc->bge_res); 2671 2672 if (sc->bge_ifp != NULL) 2673 if_free(sc->bge_ifp); 2674 2675 bge_dma_free(sc); 2676 2677 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 2678 BGE_LOCK_DESTROY(sc); 2679 } 2680 2681 static int 2682 bge_reset(struct bge_softc *sc) 2683 { 2684 device_t dev; 2685 uint32_t cachesize, command, pcistate, reset; 2686 void (*write_op)(struct bge_softc *, int, int); 2687 int i, val = 0; 2688 2689 dev = sc->bge_dev; 2690 2691 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) { 2692 if (sc->bge_flags & BGE_FLAG_PCIE) 2693 write_op = bge_writemem_direct; 2694 else 2695 write_op = bge_writemem_ind; 2696 } else 2697 write_op = bge_writereg_ind; 2698 2699 /* Save some important PCI state. */ 2700 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2701 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2702 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2703 2704 pci_write_config(dev, BGE_PCI_MISC_CTL, 2705 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2706 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2707 2708 /* Disable fastboot on controllers that support it. */ 2709 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 2710 sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2711 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2712 if (bootverbose) 2713 device_printf(sc->bge_dev, "Disabling fastboot\n"); 2714 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 2715 } 2716 2717 /* 2718 * Write the magic number to SRAM at offset 0xB50. 2719 * When firmware finishes its initialization it will 2720 * write ~BGE_MAGIC_NUMBER to the same location. 2721 */ 2722 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2723 2724 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 2725 2726 /* XXX: Broadcom Linux driver. */ 2727 if (sc->bge_flags & BGE_FLAG_PCIE) { 2728 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 2729 CSR_WRITE_4(sc, 0x7E2C, 0x20); 2730 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2731 /* Prevent PCIE link training during global reset */ 2732 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2733 reset |= 1 << 29; 2734 } 2735 } 2736 2737 /* 2738 * Set GPHY Power Down Override to leave GPHY 2739 * powered up in D0 uninitialized. 2740 */ 2741 if (BGE_IS_5705_PLUS(sc)) 2742 reset |= 0x04000000; 2743 2744 /* Issue global reset */ 2745 write_op(sc, BGE_MISC_CFG, reset); 2746 2747 DELAY(1000); 2748 2749 /* XXX: Broadcom Linux driver. */ 2750 if (sc->bge_flags & BGE_FLAG_PCIE) { 2751 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2752 uint32_t v; 2753 2754 DELAY(500000); /* wait for link training to complete */ 2755 v = pci_read_config(dev, 0xC4, 4); 2756 pci_write_config(dev, 0xC4, v | (1 << 15), 4); 2757 } 2758 /* 2759 * Set PCIE max payload size to 128 bytes and clear error 2760 * status. 2761 */ 2762 pci_write_config(dev, 0xD8, 0xF5000, 4); 2763 } 2764 2765 /* Reset some of the PCI state that got zapped by reset. */ 2766 pci_write_config(dev, BGE_PCI_MISC_CTL, 2767 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2768 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2769 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2770 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2771 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2772 2773 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 2774 if (BGE_IS_5714_FAMILY(sc)) { 2775 uint32_t val; 2776 2777 /* This chip disables MSI on reset. */ 2778 if (sc->bge_flags & BGE_FLAG_MSI) { 2779 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2); 2780 pci_write_config(dev, BGE_PCI_MSI_CTL, 2781 val | PCIM_MSICTRL_MSI_ENABLE, 2); 2782 val = CSR_READ_4(sc, BGE_MSI_MODE); 2783 CSR_WRITE_4(sc, BGE_MSI_MODE, 2784 val | BGE_MSIMODE_ENABLE); 2785 } 2786 val = CSR_READ_4(sc, BGE_MARB_MODE); 2787 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 2788 } else 2789 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2790 2791 /* 2792 * Poll until we see the 1's complement of the magic number. 2793 * This indicates that the firmware initialization is complete. 2794 * We expect this to fail if no EEPROM is fitted though. 2795 */ 2796 for (i = 0; i < BGE_TIMEOUT; i++) { 2797 DELAY(10); 2798 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2799 if (val == ~BGE_MAGIC_NUMBER) 2800 break; 2801 } 2802 2803 if ((sc->bge_flags & BGE_FLAG_EEPROM) && i == BGE_TIMEOUT) 2804 device_printf(sc->bge_dev, "firmware handshake timed out, " 2805 "found 0x%08x\n", val); 2806 2807 /* 2808 * XXX Wait for the value of the PCISTATE register to 2809 * return to its original pre-reset state. This is a 2810 * fairly good indicator of reset completion. If we don't 2811 * wait for the reset to fully complete, trying to read 2812 * from the device's non-PCI registers may yield garbage 2813 * results. 2814 */ 2815 for (i = 0; i < BGE_TIMEOUT; i++) { 2816 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2817 break; 2818 DELAY(10); 2819 } 2820 2821 if (sc->bge_flags & BGE_FLAG_PCIE) { 2822 reset = bge_readmem_ind(sc, 0x7C00); 2823 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25)); 2824 } 2825 2826 /* Fix up byte swapping. */ 2827 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 2828 BGE_MODECTL_BYTESWAP_DATA); 2829 2830 /* Tell the ASF firmware we are up */ 2831 if (sc->bge_asf_mode & ASF_STACKUP) 2832 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2833 2834 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2835 2836 /* 2837 * The 5704 in TBI mode apparently needs some special 2838 * adjustment to insure the SERDES drive level is set 2839 * to 1.2V. 2840 */ 2841 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 2842 sc->bge_flags & BGE_FLAG_TBI) { 2843 uint32_t serdescfg; 2844 2845 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2846 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2847 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2848 } 2849 2850 /* XXX: Broadcom Linux driver. */ 2851 if (sc->bge_flags & BGE_FLAG_PCIE && 2852 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2853 uint32_t v; 2854 2855 v = CSR_READ_4(sc, 0x7C00); 2856 CSR_WRITE_4(sc, 0x7C00, v | (1 << 25)); 2857 } 2858 DELAY(10000); 2859 2860 return(0); 2861 } 2862 2863 /* 2864 * Frame reception handling. This is called if there's a frame 2865 * on the receive return list. 2866 * 2867 * Note: we have to be able to handle two possibilities here: 2868 * 1) the frame is from the jumbo receive ring 2869 * 2) the frame is from the standard receive ring 2870 */ 2871 2872 static void 2873 bge_rxeof(struct bge_softc *sc) 2874 { 2875 struct ifnet *ifp; 2876 int stdcnt = 0, jumbocnt = 0; 2877 2878 BGE_LOCK_ASSERT(sc); 2879 2880 /* Nothing to do. */ 2881 if (sc->bge_rx_saved_considx == 2882 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) 2883 return; 2884 2885 ifp = sc->bge_ifp; 2886 2887 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2888 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 2889 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2890 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 2891 if (BGE_IS_JUMBO_CAPABLE(sc)) 2892 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2893 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD); 2894 2895 while(sc->bge_rx_saved_considx != 2896 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 2897 struct bge_rx_bd *cur_rx; 2898 uint32_t rxidx; 2899 struct mbuf *m = NULL; 2900 uint16_t vlan_tag = 0; 2901 int have_tag = 0; 2902 2903 #ifdef DEVICE_POLLING 2904 if (ifp->if_capenable & IFCAP_POLLING) { 2905 if (sc->rxcycles <= 0) 2906 break; 2907 sc->rxcycles--; 2908 } 2909 #endif 2910 2911 cur_rx = 2912 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 2913 2914 rxidx = cur_rx->bge_idx; 2915 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2916 2917 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 2918 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2919 have_tag = 1; 2920 vlan_tag = cur_rx->bge_vlan_tag; 2921 } 2922 2923 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2924 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2925 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 2926 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 2927 BUS_DMASYNC_POSTREAD); 2928 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 2929 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 2930 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2931 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2932 jumbocnt++; 2933 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2934 ifp->if_ierrors++; 2935 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2936 continue; 2937 } 2938 if (bge_newbuf_jumbo(sc, 2939 sc->bge_jumbo, NULL) == ENOBUFS) { 2940 ifp->if_ierrors++; 2941 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2942 continue; 2943 } 2944 } else { 2945 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2946 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 2947 sc->bge_cdata.bge_rx_std_dmamap[rxidx], 2948 BUS_DMASYNC_POSTREAD); 2949 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2950 sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 2951 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2952 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2953 stdcnt++; 2954 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2955 ifp->if_ierrors++; 2956 bge_newbuf_std(sc, sc->bge_std, m); 2957 continue; 2958 } 2959 if (bge_newbuf_std(sc, sc->bge_std, 2960 NULL) == ENOBUFS) { 2961 ifp->if_ierrors++; 2962 bge_newbuf_std(sc, sc->bge_std, m); 2963 continue; 2964 } 2965 } 2966 2967 ifp->if_ipackets++; 2968 #ifndef __NO_STRICT_ALIGNMENT 2969 /* 2970 * For architectures with strict alignment we must make sure 2971 * the payload is aligned. 2972 */ 2973 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 2974 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2975 cur_rx->bge_len); 2976 m->m_data += ETHER_ALIGN; 2977 } 2978 #endif 2979 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2980 m->m_pkthdr.rcvif = ifp; 2981 2982 if (ifp->if_capenable & IFCAP_RXCSUM) { 2983 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 2984 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2985 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 2986 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2987 } 2988 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2989 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 2990 m->m_pkthdr.csum_data = 2991 cur_rx->bge_tcp_udp_csum; 2992 m->m_pkthdr.csum_flags |= 2993 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2994 } 2995 } 2996 2997 /* 2998 * If we received a packet with a vlan tag, 2999 * attach that information to the packet. 3000 */ 3001 if (have_tag) { 3002 #if __FreeBSD_version > 700022 3003 m->m_pkthdr.ether_vtag = vlan_tag; 3004 m->m_flags |= M_VLANTAG; 3005 #else 3006 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); 3007 if (m == NULL) 3008 continue; 3009 #endif 3010 } 3011 3012 BGE_UNLOCK(sc); 3013 (*ifp->if_input)(ifp, m); 3014 BGE_LOCK(sc); 3015 } 3016 3017 if (stdcnt > 0) 3018 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3019 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3020 3021 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) 3022 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3023 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3024 3025 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3026 if (stdcnt) 3027 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3028 if (jumbocnt) 3029 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3030 #ifdef notyet 3031 /* 3032 * This register wraps very quickly under heavy packet drops. 3033 * If you need correct statistics, you can enable this check. 3034 */ 3035 if (BGE_IS_5705_PLUS(sc)) 3036 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3037 #endif 3038 } 3039 3040 static void 3041 bge_txeof(struct bge_softc *sc) 3042 { 3043 struct bge_tx_bd *cur_tx = NULL; 3044 struct ifnet *ifp; 3045 3046 BGE_LOCK_ASSERT(sc); 3047 3048 /* Nothing to do. */ 3049 if (sc->bge_tx_saved_considx == 3050 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) 3051 return; 3052 3053 ifp = sc->bge_ifp; 3054 3055 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 3056 sc->bge_cdata.bge_tx_ring_map, 3057 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3058 /* 3059 * Go through our tx ring and free mbufs for those 3060 * frames that have been sent. 3061 */ 3062 while (sc->bge_tx_saved_considx != 3063 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 3064 uint32_t idx = 0; 3065 3066 idx = sc->bge_tx_saved_considx; 3067 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3068 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3069 ifp->if_opackets++; 3070 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3071 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 3072 sc->bge_cdata.bge_tx_dmamap[idx], 3073 BUS_DMASYNC_POSTWRITE); 3074 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 3075 sc->bge_cdata.bge_tx_dmamap[idx]); 3076 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3077 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3078 } 3079 sc->bge_txcnt--; 3080 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3081 } 3082 3083 if (cur_tx != NULL) 3084 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3085 if (sc->bge_txcnt == 0) 3086 sc->bge_timer = 0; 3087 } 3088 3089 #ifdef DEVICE_POLLING 3090 static void 3091 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3092 { 3093 struct bge_softc *sc = ifp->if_softc; 3094 uint32_t statusword; 3095 3096 BGE_LOCK(sc); 3097 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3098 BGE_UNLOCK(sc); 3099 return; 3100 } 3101 3102 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3103 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3104 3105 statusword = atomic_readandclear_32( 3106 &sc->bge_ldata.bge_status_block->bge_status); 3107 3108 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3109 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3110 3111 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3112 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3113 sc->bge_link_evt++; 3114 3115 if (cmd == POLL_AND_CHECK_STATUS) 3116 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3117 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3118 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3119 bge_link_upd(sc); 3120 3121 sc->rxcycles = count; 3122 bge_rxeof(sc); 3123 bge_txeof(sc); 3124 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3125 bge_start_locked(ifp); 3126 3127 BGE_UNLOCK(sc); 3128 } 3129 #endif /* DEVICE_POLLING */ 3130 3131 static void 3132 bge_intr(void *xsc) 3133 { 3134 struct bge_softc *sc; 3135 struct ifnet *ifp; 3136 uint32_t statusword; 3137 3138 sc = xsc; 3139 3140 BGE_LOCK(sc); 3141 3142 ifp = sc->bge_ifp; 3143 3144 #ifdef DEVICE_POLLING 3145 if (ifp->if_capenable & IFCAP_POLLING) { 3146 BGE_UNLOCK(sc); 3147 return; 3148 } 3149 #endif 3150 3151 /* 3152 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3153 * disable interrupts by writing nonzero like we used to, since with 3154 * our current organization this just gives complications and 3155 * pessimizations for re-enabling interrupts. We used to have races 3156 * instead of the necessary complications. Disabling interrupts 3157 * would just reduce the chance of a status update while we are 3158 * running (by switching to the interrupt-mode coalescence 3159 * parameters), but this chance is already very low so it is more 3160 * efficient to get another interrupt than prevent it. 3161 * 3162 * We do the ack first to ensure another interrupt if there is a 3163 * status update after the ack. We don't check for the status 3164 * changing later because it is more efficient to get another 3165 * interrupt than prevent it, not quite as above (not checking is 3166 * a smaller optimization than not toggling the interrupt enable, 3167 * since checking doesn't involve PCI accesses and toggling require 3168 * the status check). So toggling would probably be a pessimization 3169 * even with MSI. It would only be needed for using a task queue. 3170 */ 3171 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3172 3173 /* 3174 * Do the mandatory PCI flush as well as get the link status. 3175 */ 3176 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3177 3178 /* Make sure the descriptor ring indexes are coherent. */ 3179 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3180 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3181 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3182 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3183 3184 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3185 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3186 statusword || sc->bge_link_evt) 3187 bge_link_upd(sc); 3188 3189 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3190 /* Check RX return ring producer/consumer. */ 3191 bge_rxeof(sc); 3192 3193 /* Check TX ring producer/consumer. */ 3194 bge_txeof(sc); 3195 } 3196 3197 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3198 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3199 bge_start_locked(ifp); 3200 3201 BGE_UNLOCK(sc); 3202 } 3203 3204 static void 3205 bge_asf_driver_up(struct bge_softc *sc) 3206 { 3207 if (sc->bge_asf_mode & ASF_STACKUP) { 3208 /* Send ASF heartbeat aprox. every 2s */ 3209 if (sc->bge_asf_count) 3210 sc->bge_asf_count --; 3211 else { 3212 sc->bge_asf_count = 5; 3213 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3214 BGE_FW_DRV_ALIVE); 3215 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3216 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3217 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3218 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3219 } 3220 } 3221 } 3222 3223 static void 3224 bge_tick(void *xsc) 3225 { 3226 struct bge_softc *sc = xsc; 3227 struct mii_data *mii = NULL; 3228 3229 BGE_LOCK_ASSERT(sc); 3230 3231 /* Synchronize with possible callout reset/stop. */ 3232 if (callout_pending(&sc->bge_stat_ch) || 3233 !callout_active(&sc->bge_stat_ch)) 3234 return; 3235 3236 if (BGE_IS_5705_PLUS(sc)) 3237 bge_stats_update_regs(sc); 3238 else 3239 bge_stats_update(sc); 3240 3241 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 3242 mii = device_get_softc(sc->bge_miibus); 3243 /* Don't mess with the PHY in IPMI/ASF mode */ 3244 if (!((sc->bge_asf_mode & ASF_STACKUP) && (sc->bge_link))) 3245 mii_tick(mii); 3246 } else { 3247 /* 3248 * Since in TBI mode auto-polling can't be used we should poll 3249 * link status manually. Here we register pending link event 3250 * and trigger interrupt. 3251 */ 3252 #ifdef DEVICE_POLLING 3253 /* In polling mode we poll link state in bge_poll(). */ 3254 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 3255 #endif 3256 { 3257 sc->bge_link_evt++; 3258 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3259 } 3260 } 3261 3262 bge_asf_driver_up(sc); 3263 bge_watchdog(sc); 3264 3265 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3266 } 3267 3268 static void 3269 bge_stats_update_regs(struct bge_softc *sc) 3270 { 3271 struct ifnet *ifp; 3272 3273 ifp = sc->bge_ifp; 3274 3275 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3276 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3277 3278 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3279 } 3280 3281 static void 3282 bge_stats_update(struct bge_softc *sc) 3283 { 3284 struct ifnet *ifp; 3285 bus_size_t stats; 3286 uint32_t cnt; /* current register value */ 3287 3288 ifp = sc->bge_ifp; 3289 3290 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3291 3292 #define READ_STAT(sc, stats, stat) \ 3293 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3294 3295 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 3296 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 3297 sc->bge_tx_collisions = cnt; 3298 3299 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 3300 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 3301 sc->bge_rx_discards = cnt; 3302 3303 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 3304 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 3305 sc->bge_tx_discards = cnt; 3306 3307 #undef READ_STAT 3308 } 3309 3310 /* 3311 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3312 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3313 * but when such padded frames employ the bge IP/TCP checksum offload, 3314 * the hardware checksum assist gives incorrect results (possibly 3315 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3316 * If we pad such runts with zeros, the onboard checksum comes out correct. 3317 */ 3318 static __inline int 3319 bge_cksum_pad(struct mbuf *m) 3320 { 3321 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 3322 struct mbuf *last; 3323 3324 /* If there's only the packet-header and we can pad there, use it. */ 3325 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 3326 M_TRAILINGSPACE(m) >= padlen) { 3327 last = m; 3328 } else { 3329 /* 3330 * Walk packet chain to find last mbuf. We will either 3331 * pad there, or append a new mbuf and pad it. 3332 */ 3333 for (last = m; last->m_next != NULL; last = last->m_next); 3334 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 3335 /* Allocate new empty mbuf, pad it. Compact later. */ 3336 struct mbuf *n; 3337 3338 MGET(n, M_DONTWAIT, MT_DATA); 3339 if (n == NULL) 3340 return (ENOBUFS); 3341 n->m_len = 0; 3342 last->m_next = n; 3343 last = n; 3344 } 3345 } 3346 3347 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 3348 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3349 last->m_len += padlen; 3350 m->m_pkthdr.len += padlen; 3351 3352 return (0); 3353 } 3354 3355 /* 3356 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3357 * pointers to descriptors. 3358 */ 3359 static int 3360 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 3361 { 3362 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3363 bus_dmamap_t map; 3364 struct bge_tx_bd *d; 3365 struct mbuf *m = *m_head; 3366 uint32_t idx = *txidx; 3367 uint16_t csum_flags; 3368 int nsegs, i, error; 3369 3370 csum_flags = 0; 3371 if (m->m_pkthdr.csum_flags) { 3372 if (m->m_pkthdr.csum_flags & CSUM_IP) 3373 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3374 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 3375 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3376 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 3377 (error = bge_cksum_pad(m)) != 0) { 3378 m_freem(m); 3379 *m_head = NULL; 3380 return (error); 3381 } 3382 } 3383 if (m->m_flags & M_LASTFRAG) 3384 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3385 else if (m->m_flags & M_FRAG) 3386 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3387 } 3388 3389 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3390 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs, 3391 &nsegs, BUS_DMA_NOWAIT); 3392 if (error == EFBIG) { 3393 m = m_defrag(m, M_DONTWAIT); 3394 if (m == NULL) { 3395 m_freem(*m_head); 3396 *m_head = NULL; 3397 return (ENOBUFS); 3398 } 3399 *m_head = m; 3400 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, 3401 segs, &nsegs, BUS_DMA_NOWAIT); 3402 if (error) { 3403 m_freem(m); 3404 *m_head = NULL; 3405 return (error); 3406 } 3407 } else if (error != 0) 3408 return (error); 3409 3410 /* 3411 * Sanity check: avoid coming within 16 descriptors 3412 * of the end of the ring. 3413 */ 3414 if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3415 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map); 3416 return (ENOBUFS); 3417 } 3418 3419 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE); 3420 3421 for (i = 0; ; i++) { 3422 d = &sc->bge_ldata.bge_tx_ring[idx]; 3423 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3424 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3425 d->bge_len = segs[i].ds_len; 3426 d->bge_flags = csum_flags; 3427 if (i == nsegs - 1) 3428 break; 3429 BGE_INC(idx, BGE_TX_RING_CNT); 3430 } 3431 3432 /* Mark the last segment as end of packet... */ 3433 d->bge_flags |= BGE_TXBDFLAG_END; 3434 3435 /* ... and put VLAN tag into first segment. */ 3436 d = &sc->bge_ldata.bge_tx_ring[*txidx]; 3437 #if __FreeBSD_version > 700022 3438 if (m->m_flags & M_VLANTAG) { 3439 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3440 d->bge_vlan_tag = m->m_pkthdr.ether_vtag; 3441 } else 3442 d->bge_vlan_tag = 0; 3443 #else 3444 { 3445 struct m_tag *mtag; 3446 3447 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { 3448 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3449 d->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3450 } else 3451 d->bge_vlan_tag = 0; 3452 } 3453 #endif 3454 3455 /* 3456 * Insure that the map for this transmission 3457 * is placed at the array index of the last descriptor 3458 * in this chain. 3459 */ 3460 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 3461 sc->bge_cdata.bge_tx_dmamap[idx] = map; 3462 sc->bge_cdata.bge_tx_chain[idx] = m; 3463 sc->bge_txcnt += nsegs; 3464 3465 BGE_INC(idx, BGE_TX_RING_CNT); 3466 *txidx = idx; 3467 3468 return (0); 3469 } 3470 3471 /* 3472 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3473 * to the mbuf data regions directly in the transmit descriptors. 3474 */ 3475 static void 3476 bge_start_locked(struct ifnet *ifp) 3477 { 3478 struct bge_softc *sc; 3479 struct mbuf *m_head = NULL; 3480 uint32_t prodidx; 3481 int count = 0; 3482 3483 sc = ifp->if_softc; 3484 3485 if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3486 return; 3487 3488 prodidx = sc->bge_tx_prodidx; 3489 3490 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3491 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3492 if (m_head == NULL) 3493 break; 3494 3495 /* 3496 * XXX 3497 * The code inside the if() block is never reached since we 3498 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 3499 * requests to checksum TCP/UDP in a fragmented packet. 3500 * 3501 * XXX 3502 * safety overkill. If this is a fragmented packet chain 3503 * with delayed TCP/UDP checksums, then only encapsulate 3504 * it if we have enough descriptors to handle the entire 3505 * chain at once. 3506 * (paranoia -- may not actually be needed) 3507 */ 3508 if (m_head->m_flags & M_FIRSTFRAG && 3509 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3510 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3511 m_head->m_pkthdr.csum_data + 16) { 3512 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3513 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3514 break; 3515 } 3516 } 3517 3518 /* 3519 * Pack the data into the transmit ring. If we 3520 * don't have room, set the OACTIVE flag and wait 3521 * for the NIC to drain the ring. 3522 */ 3523 if (bge_encap(sc, &m_head, &prodidx)) { 3524 if (m_head == NULL) 3525 break; 3526 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3527 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3528 break; 3529 } 3530 ++count; 3531 3532 /* 3533 * If there's a BPF listener, bounce a copy of this frame 3534 * to him. 3535 */ 3536 #ifdef ETHER_BPF_MTAP 3537 ETHER_BPF_MTAP(ifp, m_head); 3538 #else 3539 BPF_MTAP(ifp, m_head); 3540 #endif 3541 } 3542 3543 if (count == 0) 3544 /* No packets were dequeued. */ 3545 return; 3546 3547 /* Transmit. */ 3548 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3549 /* 5700 b2 errata */ 3550 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3551 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3552 3553 sc->bge_tx_prodidx = prodidx; 3554 3555 /* 3556 * Set a timeout in case the chip goes out to lunch. 3557 */ 3558 sc->bge_timer = 5; 3559 } 3560 3561 /* 3562 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3563 * to the mbuf data regions directly in the transmit descriptors. 3564 */ 3565 static void 3566 bge_start(struct ifnet *ifp) 3567 { 3568 struct bge_softc *sc; 3569 3570 sc = ifp->if_softc; 3571 BGE_LOCK(sc); 3572 bge_start_locked(ifp); 3573 BGE_UNLOCK(sc); 3574 } 3575 3576 static void 3577 bge_init_locked(struct bge_softc *sc) 3578 { 3579 struct ifnet *ifp; 3580 uint16_t *m; 3581 3582 BGE_LOCK_ASSERT(sc); 3583 3584 ifp = sc->bge_ifp; 3585 3586 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3587 return; 3588 3589 /* Cancel pending I/O and flush buffers. */ 3590 bge_stop(sc); 3591 3592 bge_stop_fw(sc); 3593 bge_sig_pre_reset(sc, BGE_RESET_START); 3594 bge_reset(sc); 3595 bge_sig_legacy(sc, BGE_RESET_START); 3596 bge_sig_post_reset(sc, BGE_RESET_START); 3597 3598 bge_chipinit(sc); 3599 3600 /* 3601 * Init the various state machines, ring 3602 * control blocks and firmware. 3603 */ 3604 if (bge_blockinit(sc)) { 3605 device_printf(sc->bge_dev, "initialization failure\n"); 3606 return; 3607 } 3608 3609 ifp = sc->bge_ifp; 3610 3611 /* Specify MTU. */ 3612 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3613 ETHER_HDR_LEN + ETHER_CRC_LEN + 3614 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 3615 3616 /* Load our MAC address. */ 3617 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 3618 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3619 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3620 3621 /* Program promiscuous mode. */ 3622 bge_setpromisc(sc); 3623 3624 /* Program multicast filter. */ 3625 bge_setmulti(sc); 3626 3627 /* Program VLAN tag stripping. */ 3628 bge_setvlan(sc); 3629 3630 /* Init RX ring. */ 3631 bge_init_rx_ring_std(sc); 3632 3633 /* 3634 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3635 * memory to insure that the chip has in fact read the first 3636 * entry of the ring. 3637 */ 3638 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3639 uint32_t v, i; 3640 for (i = 0; i < 10; i++) { 3641 DELAY(20); 3642 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3643 if (v == (MCLBYTES - ETHER_ALIGN)) 3644 break; 3645 } 3646 if (i == 10) 3647 device_printf (sc->bge_dev, 3648 "5705 A0 chip failed to load RX ring\n"); 3649 } 3650 3651 /* Init jumbo RX ring. */ 3652 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3653 bge_init_rx_ring_jumbo(sc); 3654 3655 /* Init our RX return ring index. */ 3656 sc->bge_rx_saved_considx = 0; 3657 3658 /* Init our RX/TX stat counters. */ 3659 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 3660 3661 /* Init TX ring. */ 3662 bge_init_tx_ring(sc); 3663 3664 /* Turn on transmitter. */ 3665 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3666 3667 /* Turn on receiver. */ 3668 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3669 3670 /* Tell firmware we're alive. */ 3671 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3672 3673 #ifdef DEVICE_POLLING 3674 /* Disable interrupts if we are polling. */ 3675 if (ifp->if_capenable & IFCAP_POLLING) { 3676 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3677 BGE_PCIMISCCTL_MASK_PCI_INTR); 3678 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3679 } else 3680 #endif 3681 3682 /* Enable host interrupts. */ 3683 { 3684 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3685 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3686 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3687 } 3688 3689 bge_ifmedia_upd_locked(ifp); 3690 3691 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3692 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3693 3694 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3695 } 3696 3697 static void 3698 bge_init(void *xsc) 3699 { 3700 struct bge_softc *sc = xsc; 3701 3702 BGE_LOCK(sc); 3703 bge_init_locked(sc); 3704 BGE_UNLOCK(sc); 3705 } 3706 3707 /* 3708 * Set media options. 3709 */ 3710 static int 3711 bge_ifmedia_upd(struct ifnet *ifp) 3712 { 3713 struct bge_softc *sc = ifp->if_softc; 3714 int res; 3715 3716 BGE_LOCK(sc); 3717 res = bge_ifmedia_upd_locked(ifp); 3718 BGE_UNLOCK(sc); 3719 3720 return (res); 3721 } 3722 3723 static int 3724 bge_ifmedia_upd_locked(struct ifnet *ifp) 3725 { 3726 struct bge_softc *sc = ifp->if_softc; 3727 struct mii_data *mii; 3728 struct ifmedia *ifm; 3729 3730 BGE_LOCK_ASSERT(sc); 3731 3732 ifm = &sc->bge_ifmedia; 3733 3734 /* If this is a 1000baseX NIC, enable the TBI port. */ 3735 if (sc->bge_flags & BGE_FLAG_TBI) { 3736 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3737 return (EINVAL); 3738 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3739 case IFM_AUTO: 3740 /* 3741 * The BCM5704 ASIC appears to have a special 3742 * mechanism for programming the autoneg 3743 * advertisement registers in TBI mode. 3744 */ 3745 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3746 uint32_t sgdig; 3747 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 3748 if (sgdig & BGE_SGDIGSTS_DONE) { 3749 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3750 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3751 sgdig |= BGE_SGDIGCFG_AUTO | 3752 BGE_SGDIGCFG_PAUSE_CAP | 3753 BGE_SGDIGCFG_ASYM_PAUSE; 3754 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3755 sgdig | BGE_SGDIGCFG_SEND); 3756 DELAY(5); 3757 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3758 } 3759 } 3760 break; 3761 case IFM_1000_SX: 3762 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3763 BGE_CLRBIT(sc, BGE_MAC_MODE, 3764 BGE_MACMODE_HALF_DUPLEX); 3765 } else { 3766 BGE_SETBIT(sc, BGE_MAC_MODE, 3767 BGE_MACMODE_HALF_DUPLEX); 3768 } 3769 break; 3770 default: 3771 return (EINVAL); 3772 } 3773 return (0); 3774 } 3775 3776 sc->bge_link_evt++; 3777 mii = device_get_softc(sc->bge_miibus); 3778 if (mii->mii_instance) { 3779 struct mii_softc *miisc; 3780 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3781 miisc = LIST_NEXT(miisc, mii_list)) 3782 mii_phy_reset(miisc); 3783 } 3784 mii_mediachg(mii); 3785 3786 return (0); 3787 } 3788 3789 /* 3790 * Report current media status. 3791 */ 3792 static void 3793 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3794 { 3795 struct bge_softc *sc = ifp->if_softc; 3796 struct mii_data *mii; 3797 3798 BGE_LOCK(sc); 3799 3800 if (sc->bge_flags & BGE_FLAG_TBI) { 3801 ifmr->ifm_status = IFM_AVALID; 3802 ifmr->ifm_active = IFM_ETHER; 3803 if (CSR_READ_4(sc, BGE_MAC_STS) & 3804 BGE_MACSTAT_TBI_PCS_SYNCHED) 3805 ifmr->ifm_status |= IFM_ACTIVE; 3806 else { 3807 ifmr->ifm_active |= IFM_NONE; 3808 BGE_UNLOCK(sc); 3809 return; 3810 } 3811 ifmr->ifm_active |= IFM_1000_SX; 3812 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3813 ifmr->ifm_active |= IFM_HDX; 3814 else 3815 ifmr->ifm_active |= IFM_FDX; 3816 BGE_UNLOCK(sc); 3817 return; 3818 } 3819 3820 mii = device_get_softc(sc->bge_miibus); 3821 mii_pollstat(mii); 3822 ifmr->ifm_active = mii->mii_media_active; 3823 ifmr->ifm_status = mii->mii_media_status; 3824 3825 BGE_UNLOCK(sc); 3826 } 3827 3828 static int 3829 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3830 { 3831 struct bge_softc *sc = ifp->if_softc; 3832 struct ifreq *ifr = (struct ifreq *) data; 3833 struct mii_data *mii; 3834 int flags, mask, error = 0; 3835 3836 switch (command) { 3837 case SIOCSIFMTU: 3838 if (ifr->ifr_mtu < ETHERMIN || 3839 ((BGE_IS_JUMBO_CAPABLE(sc)) && 3840 ifr->ifr_mtu > BGE_JUMBO_MTU) || 3841 ((!BGE_IS_JUMBO_CAPABLE(sc)) && 3842 ifr->ifr_mtu > ETHERMTU)) 3843 error = EINVAL; 3844 else if (ifp->if_mtu != ifr->ifr_mtu) { 3845 ifp->if_mtu = ifr->ifr_mtu; 3846 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3847 bge_init(sc); 3848 } 3849 break; 3850 case SIOCSIFFLAGS: 3851 BGE_LOCK(sc); 3852 if (ifp->if_flags & IFF_UP) { 3853 /* 3854 * If only the state of the PROMISC flag changed, 3855 * then just use the 'set promisc mode' command 3856 * instead of reinitializing the entire NIC. Doing 3857 * a full re-init means reloading the firmware and 3858 * waiting for it to start up, which may take a 3859 * second or two. Similarly for ALLMULTI. 3860 */ 3861 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3862 flags = ifp->if_flags ^ sc->bge_if_flags; 3863 if (flags & IFF_PROMISC) 3864 bge_setpromisc(sc); 3865 if (flags & IFF_ALLMULTI) 3866 bge_setmulti(sc); 3867 } else 3868 bge_init_locked(sc); 3869 } else { 3870 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3871 bge_stop(sc); 3872 } 3873 } 3874 sc->bge_if_flags = ifp->if_flags; 3875 BGE_UNLOCK(sc); 3876 error = 0; 3877 break; 3878 case SIOCADDMULTI: 3879 case SIOCDELMULTI: 3880 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3881 BGE_LOCK(sc); 3882 bge_setmulti(sc); 3883 BGE_UNLOCK(sc); 3884 error = 0; 3885 } 3886 break; 3887 case SIOCSIFMEDIA: 3888 case SIOCGIFMEDIA: 3889 if (sc->bge_flags & BGE_FLAG_TBI) { 3890 error = ifmedia_ioctl(ifp, ifr, 3891 &sc->bge_ifmedia, command); 3892 } else { 3893 mii = device_get_softc(sc->bge_miibus); 3894 error = ifmedia_ioctl(ifp, ifr, 3895 &mii->mii_media, command); 3896 } 3897 break; 3898 case SIOCSIFCAP: 3899 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3900 #ifdef DEVICE_POLLING 3901 if (mask & IFCAP_POLLING) { 3902 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3903 error = ether_poll_register(bge_poll, ifp); 3904 if (error) 3905 return (error); 3906 BGE_LOCK(sc); 3907 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3908 BGE_PCIMISCCTL_MASK_PCI_INTR); 3909 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3910 ifp->if_capenable |= IFCAP_POLLING; 3911 BGE_UNLOCK(sc); 3912 } else { 3913 error = ether_poll_deregister(ifp); 3914 /* Enable interrupt even in error case */ 3915 BGE_LOCK(sc); 3916 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 3917 BGE_PCIMISCCTL_MASK_PCI_INTR); 3918 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3919 ifp->if_capenable &= ~IFCAP_POLLING; 3920 BGE_UNLOCK(sc); 3921 } 3922 } 3923 #endif 3924 if (mask & IFCAP_HWCSUM) { 3925 ifp->if_capenable ^= IFCAP_HWCSUM; 3926 if (IFCAP_HWCSUM & ifp->if_capenable && 3927 IFCAP_HWCSUM & ifp->if_capabilities) 3928 ifp->if_hwassist = BGE_CSUM_FEATURES; 3929 else 3930 ifp->if_hwassist = 0; 3931 #ifdef VLAN_CAPABILITIES 3932 VLAN_CAPABILITIES(ifp); 3933 #endif 3934 } 3935 3936 if (mask & IFCAP_VLAN_MTU) { 3937 ifp->if_capenable ^= IFCAP_VLAN_MTU; 3938 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3939 bge_init(sc); 3940 } 3941 3942 if (mask & IFCAP_VLAN_HWTAGGING) { 3943 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3944 BGE_LOCK(sc); 3945 bge_setvlan(sc); 3946 BGE_UNLOCK(sc); 3947 #ifdef VLAN_CAPABILITIES 3948 VLAN_CAPABILITIES(ifp); 3949 #endif 3950 } 3951 3952 break; 3953 default: 3954 error = ether_ioctl(ifp, command, data); 3955 break; 3956 } 3957 3958 return (error); 3959 } 3960 3961 static void 3962 bge_watchdog(struct bge_softc *sc) 3963 { 3964 struct ifnet *ifp; 3965 3966 BGE_LOCK_ASSERT(sc); 3967 3968 if (sc->bge_timer == 0 || --sc->bge_timer) 3969 return; 3970 3971 ifp = sc->bge_ifp; 3972 3973 if_printf(ifp, "watchdog timeout -- resetting\n"); 3974 3975 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3976 bge_init_locked(sc); 3977 3978 ifp->if_oerrors++; 3979 } 3980 3981 /* 3982 * Stop the adapter and free any mbufs allocated to the 3983 * RX and TX lists. 3984 */ 3985 static void 3986 bge_stop(struct bge_softc *sc) 3987 { 3988 struct ifnet *ifp; 3989 struct ifmedia_entry *ifm; 3990 struct mii_data *mii = NULL; 3991 int mtmp, itmp; 3992 3993 BGE_LOCK_ASSERT(sc); 3994 3995 ifp = sc->bge_ifp; 3996 3997 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) 3998 mii = device_get_softc(sc->bge_miibus); 3999 4000 callout_stop(&sc->bge_stat_ch); 4001 4002 /* 4003 * Disable all of the receiver blocks. 4004 */ 4005 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4006 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4007 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4008 if (!(BGE_IS_5705_PLUS(sc))) 4009 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4010 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4011 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4012 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4013 4014 /* 4015 * Disable all of the transmit blocks. 4016 */ 4017 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4018 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4019 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4020 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4021 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4022 if (!(BGE_IS_5705_PLUS(sc))) 4023 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4024 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4025 4026 /* 4027 * Shut down all of the memory managers and related 4028 * state machines. 4029 */ 4030 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4031 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4032 if (!(BGE_IS_5705_PLUS(sc))) 4033 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4034 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4035 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4036 if (!(BGE_IS_5705_PLUS(sc))) { 4037 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4038 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4039 } 4040 4041 /* Disable host interrupts. */ 4042 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4043 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 4044 4045 /* 4046 * Tell firmware we're shutting down. 4047 */ 4048 4049 bge_stop_fw(sc); 4050 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4051 bge_reset(sc); 4052 bge_sig_legacy(sc, BGE_RESET_STOP); 4053 bge_sig_post_reset(sc, BGE_RESET_STOP); 4054 4055 /* 4056 * Keep the ASF firmware running if up. 4057 */ 4058 if (sc->bge_asf_mode & ASF_STACKUP) 4059 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4060 else 4061 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4062 4063 /* Free the RX lists. */ 4064 bge_free_rx_ring_std(sc); 4065 4066 /* Free jumbo RX list. */ 4067 if (BGE_IS_JUMBO_CAPABLE(sc)) 4068 bge_free_rx_ring_jumbo(sc); 4069 4070 /* Free TX buffers. */ 4071 bge_free_tx_ring(sc); 4072 4073 /* 4074 * Isolate/power down the PHY, but leave the media selection 4075 * unchanged so that things will be put back to normal when 4076 * we bring the interface back up. 4077 */ 4078 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4079 itmp = ifp->if_flags; 4080 ifp->if_flags |= IFF_UP; 4081 /* 4082 * If we are called from bge_detach(), mii is already NULL. 4083 */ 4084 if (mii != NULL) { 4085 ifm = mii->mii_media.ifm_cur; 4086 mtmp = ifm->ifm_media; 4087 ifm->ifm_media = IFM_ETHER | IFM_NONE; 4088 mii_mediachg(mii); 4089 ifm->ifm_media = mtmp; 4090 } 4091 ifp->if_flags = itmp; 4092 } 4093 4094 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4095 4096 /* Clear MAC's link state (PHY may still have link UP). */ 4097 if (bootverbose && sc->bge_link) 4098 if_printf(sc->bge_ifp, "link DOWN\n"); 4099 sc->bge_link = 0; 4100 4101 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4102 } 4103 4104 /* 4105 * Stop all chip I/O so that the kernel's probe routines don't 4106 * get confused by errant DMAs when rebooting. 4107 */ 4108 static void 4109 bge_shutdown(device_t dev) 4110 { 4111 struct bge_softc *sc; 4112 4113 sc = device_get_softc(dev); 4114 4115 BGE_LOCK(sc); 4116 bge_stop(sc); 4117 bge_reset(sc); 4118 BGE_UNLOCK(sc); 4119 } 4120 4121 static int 4122 bge_suspend(device_t dev) 4123 { 4124 struct bge_softc *sc; 4125 4126 sc = device_get_softc(dev); 4127 BGE_LOCK(sc); 4128 bge_stop(sc); 4129 BGE_UNLOCK(sc); 4130 4131 return (0); 4132 } 4133 4134 static int 4135 bge_resume(device_t dev) 4136 { 4137 struct bge_softc *sc; 4138 struct ifnet *ifp; 4139 4140 sc = device_get_softc(dev); 4141 BGE_LOCK(sc); 4142 ifp = sc->bge_ifp; 4143 if (ifp->if_flags & IFF_UP) { 4144 bge_init_locked(sc); 4145 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4146 bge_start_locked(ifp); 4147 } 4148 BGE_UNLOCK(sc); 4149 4150 return (0); 4151 } 4152 4153 static void 4154 bge_link_upd(struct bge_softc *sc) 4155 { 4156 struct mii_data *mii; 4157 uint32_t link, status; 4158 4159 BGE_LOCK_ASSERT(sc); 4160 4161 /* Clear 'pending link event' flag. */ 4162 sc->bge_link_evt = 0; 4163 4164 /* 4165 * Process link state changes. 4166 * Grrr. The link status word in the status block does 4167 * not work correctly on the BCM5700 rev AX and BX chips, 4168 * according to all available information. Hence, we have 4169 * to enable MII interrupts in order to properly obtain 4170 * async link changes. Unfortunately, this also means that 4171 * we have to read the MAC status register to detect link 4172 * changes, thereby adding an additional register access to 4173 * the interrupt handler. 4174 * 4175 * XXX: perhaps link state detection procedure used for 4176 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4177 */ 4178 4179 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4180 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 4181 status = CSR_READ_4(sc, BGE_MAC_STS); 4182 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4183 mii = device_get_softc(sc->bge_miibus); 4184 mii_pollstat(mii); 4185 if (!sc->bge_link && 4186 mii->mii_media_status & IFM_ACTIVE && 4187 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4188 sc->bge_link++; 4189 if (bootverbose) 4190 if_printf(sc->bge_ifp, "link UP\n"); 4191 } else if (sc->bge_link && 4192 (!(mii->mii_media_status & IFM_ACTIVE) || 4193 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4194 sc->bge_link = 0; 4195 if (bootverbose) 4196 if_printf(sc->bge_ifp, "link DOWN\n"); 4197 } 4198 4199 /* Clear the interrupt. */ 4200 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4201 BGE_EVTENB_MI_INTERRUPT); 4202 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4203 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4204 BRGPHY_INTRS); 4205 } 4206 return; 4207 } 4208 4209 if (sc->bge_flags & BGE_FLAG_TBI) { 4210 status = CSR_READ_4(sc, BGE_MAC_STS); 4211 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4212 if (!sc->bge_link) { 4213 sc->bge_link++; 4214 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 4215 BGE_CLRBIT(sc, BGE_MAC_MODE, 4216 BGE_MACMODE_TBI_SEND_CFGS); 4217 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4218 if (bootverbose) 4219 if_printf(sc->bge_ifp, "link UP\n"); 4220 if_link_state_change(sc->bge_ifp, 4221 LINK_STATE_UP); 4222 } 4223 } else if (sc->bge_link) { 4224 sc->bge_link = 0; 4225 if (bootverbose) 4226 if_printf(sc->bge_ifp, "link DOWN\n"); 4227 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 4228 } 4229 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { 4230 /* 4231 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 4232 * in status word always set. Workaround this bug by reading 4233 * PHY link status directly. 4234 */ 4235 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 4236 4237 if (link != sc->bge_link || 4238 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 4239 mii = device_get_softc(sc->bge_miibus); 4240 mii_pollstat(mii); 4241 if (!sc->bge_link && 4242 mii->mii_media_status & IFM_ACTIVE && 4243 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4244 sc->bge_link++; 4245 if (bootverbose) 4246 if_printf(sc->bge_ifp, "link UP\n"); 4247 } else if (sc->bge_link && 4248 (!(mii->mii_media_status & IFM_ACTIVE) || 4249 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4250 sc->bge_link = 0; 4251 if (bootverbose) 4252 if_printf(sc->bge_ifp, "link DOWN\n"); 4253 } 4254 } 4255 } else { 4256 /* 4257 * Discard link events for MII/GMII controllers 4258 * if MI auto-polling is disabled. 4259 */ 4260 } 4261 4262 /* Clear the attention. */ 4263 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4264 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4265 BGE_MACSTAT_LINK_CHANGED); 4266 } 4267 4268 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 4269 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 4270 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 4271 desc) 4272 4273 static void 4274 bge_add_sysctls(struct bge_softc *sc) 4275 { 4276 struct sysctl_ctx_list *ctx; 4277 struct sysctl_oid_list *children, *schildren; 4278 struct sysctl_oid *tree; 4279 4280 ctx = device_get_sysctl_ctx(sc->bge_dev); 4281 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 4282 4283 #ifdef BGE_REGISTER_DEBUG 4284 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 4285 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 4286 "Debug Information"); 4287 4288 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 4289 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 4290 "Register Read"); 4291 4292 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 4293 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 4294 "Memory Read"); 4295 4296 #endif 4297 4298 if (BGE_IS_5705_PLUS(sc)) 4299 return; 4300 4301 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 4302 NULL, "BGE Statistics"); 4303 schildren = children = SYSCTL_CHILDREN(tree); 4304 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 4305 children, COSFramesDroppedDueToFilters, 4306 "FramesDroppedDueToFilters"); 4307 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 4308 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 4309 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 4310 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 4311 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 4312 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 4313 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 4314 children, ifInDiscards, "InputDiscards"); 4315 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 4316 children, ifInErrors, "InputErrors"); 4317 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 4318 children, nicRecvThresholdHit, "RecvThresholdHit"); 4319 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 4320 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 4321 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 4322 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 4323 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 4324 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 4325 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 4326 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 4327 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 4328 children, nicRingStatusUpdate, "RingStatusUpdate"); 4329 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 4330 children, nicInterrupts, "Interrupts"); 4331 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 4332 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 4333 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 4334 children, nicSendThresholdHit, "SendThresholdHit"); 4335 4336 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 4337 NULL, "BGE RX Statistics"); 4338 children = SYSCTL_CHILDREN(tree); 4339 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 4340 children, rxstats.ifHCInOctets, "Octets"); 4341 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 4342 children, rxstats.etherStatsFragments, "Fragments"); 4343 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 4344 children, rxstats.ifHCInUcastPkts, "UcastPkts"); 4345 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 4346 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 4347 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 4348 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 4349 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 4350 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 4351 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 4352 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 4353 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 4354 children, rxstats.xoffPauseFramesReceived, 4355 "xoffPauseFramesReceived"); 4356 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 4357 children, rxstats.macControlFramesReceived, 4358 "ControlFramesReceived"); 4359 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 4360 children, rxstats.xoffStateEntered, "xoffStateEntered"); 4361 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 4362 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 4363 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 4364 children, rxstats.etherStatsJabbers, "Jabbers"); 4365 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 4366 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 4367 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 4368 children, rxstats.inRangeLengthError, "inRangeLengthError"); 4369 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 4370 children, rxstats.outRangeLengthError, "outRangeLengthError"); 4371 4372 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 4373 NULL, "BGE TX Statistics"); 4374 children = SYSCTL_CHILDREN(tree); 4375 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 4376 children, txstats.ifHCOutOctets, "Octets"); 4377 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 4378 children, txstats.etherStatsCollisions, "Collisions"); 4379 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 4380 children, txstats.outXonSent, "XonSent"); 4381 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 4382 children, txstats.outXoffSent, "XoffSent"); 4383 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 4384 children, txstats.flowControlDone, "flowControlDone"); 4385 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 4386 children, txstats.dot3StatsInternalMacTransmitErrors, 4387 "InternalMacTransmitErrors"); 4388 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 4389 children, txstats.dot3StatsSingleCollisionFrames, 4390 "SingleCollisionFrames"); 4391 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 4392 children, txstats.dot3StatsMultipleCollisionFrames, 4393 "MultipleCollisionFrames"); 4394 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 4395 children, txstats.dot3StatsDeferredTransmissions, 4396 "DeferredTransmissions"); 4397 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 4398 children, txstats.dot3StatsExcessiveCollisions, 4399 "ExcessiveCollisions"); 4400 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 4401 children, txstats.dot3StatsLateCollisions, 4402 "LateCollisions"); 4403 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 4404 children, txstats.ifHCOutUcastPkts, "UcastPkts"); 4405 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 4406 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 4407 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 4408 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 4409 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 4410 children, txstats.dot3StatsCarrierSenseErrors, 4411 "CarrierSenseErrors"); 4412 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 4413 children, txstats.ifOutDiscards, "Discards"); 4414 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 4415 children, txstats.ifOutErrors, "Errors"); 4416 } 4417 4418 static int 4419 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 4420 { 4421 struct bge_softc *sc; 4422 uint32_t result; 4423 int offset; 4424 4425 sc = (struct bge_softc *)arg1; 4426 offset = arg2; 4427 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 4428 offsetof(bge_hostaddr, bge_addr_lo)); 4429 return (sysctl_handle_int(oidp, &result, 0, req)); 4430 } 4431 4432 #ifdef BGE_REGISTER_DEBUG 4433 static int 4434 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4435 { 4436 struct bge_softc *sc; 4437 uint16_t *sbdata; 4438 int error; 4439 int result; 4440 int i, j; 4441 4442 result = -1; 4443 error = sysctl_handle_int(oidp, &result, 0, req); 4444 if (error || (req->newptr == NULL)) 4445 return (error); 4446 4447 if (result == 1) { 4448 sc = (struct bge_softc *)arg1; 4449 4450 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 4451 printf("Status Block:\n"); 4452 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 4453 printf("%06x:", i); 4454 for (j = 0; j < 8; j++) { 4455 printf(" %04x", sbdata[i]); 4456 i += 4; 4457 } 4458 printf("\n"); 4459 } 4460 4461 printf("Registers:\n"); 4462 for (i = 0x800; i < 0xA00; ) { 4463 printf("%06x:", i); 4464 for (j = 0; j < 8; j++) { 4465 printf(" %08x", CSR_READ_4(sc, i)); 4466 i += 4; 4467 } 4468 printf("\n"); 4469 } 4470 4471 printf("Hardware Flags:\n"); 4472 if (BGE_IS_575X_PLUS(sc)) 4473 printf(" - 575X Plus\n"); 4474 if (BGE_IS_5705_PLUS(sc)) 4475 printf(" - 5705 Plus\n"); 4476 if (BGE_IS_5714_FAMILY(sc)) 4477 printf(" - 5714 Family\n"); 4478 if (BGE_IS_5700_FAMILY(sc)) 4479 printf(" - 5700 Family\n"); 4480 if (sc->bge_flags & BGE_FLAG_JUMBO) 4481 printf(" - Supports Jumbo Frames\n"); 4482 if (sc->bge_flags & BGE_FLAG_PCIX) 4483 printf(" - PCI-X Bus\n"); 4484 if (sc->bge_flags & BGE_FLAG_PCIE) 4485 printf(" - PCI Express Bus\n"); 4486 if (sc->bge_flags & BGE_FLAG_NO_3LED) 4487 printf(" - No 3 LEDs\n"); 4488 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 4489 printf(" - RX Alignment Bug\n"); 4490 } 4491 4492 return (error); 4493 } 4494 4495 static int 4496 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 4497 { 4498 struct bge_softc *sc; 4499 int error; 4500 uint16_t result; 4501 uint32_t val; 4502 4503 result = -1; 4504 error = sysctl_handle_int(oidp, &result, 0, req); 4505 if (error || (req->newptr == NULL)) 4506 return (error); 4507 4508 if (result < 0x8000) { 4509 sc = (struct bge_softc *)arg1; 4510 val = CSR_READ_4(sc, result); 4511 printf("reg 0x%06X = 0x%08X\n", result, val); 4512 } 4513 4514 return (error); 4515 } 4516 4517 static int 4518 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 4519 { 4520 struct bge_softc *sc; 4521 int error; 4522 uint16_t result; 4523 uint32_t val; 4524 4525 result = -1; 4526 error = sysctl_handle_int(oidp, &result, 0, req); 4527 if (error || (req->newptr == NULL)) 4528 return (error); 4529 4530 if (result < 0x8000) { 4531 sc = (struct bge_softc *)arg1; 4532 val = bge_readmem_ind(sc, result); 4533 printf("mem 0x%06X = 0x%08X\n", result, val); 4534 } 4535 4536 return (error); 4537 } 4538 #endif
Cache object: fb1d58fee2830821c0856580100d4748
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