FreeBSD/Linux Kernel Cross Reference
sys/dev/bge/if_bge.c
1 /*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.42 2007/02/15 10:33:49 bde Exp $
34 */
35
36 /*
37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Engineer, Wind River Systems
41 */
42
43 /*
44 * The Broadcom BCM5700 is based on technology originally developed by
45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49 * frames, highly configurable RX filtering, and 16 RX and TX queues
50 * (which, along with RX filter rules, can be used for QOS applications).
51 * Other features, such as TCP segmentation, may be available as part
52 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53 * firmware images can be stored in hardware and need not be compiled
54 * into the driver.
55 *
56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
58 *
59 * The BCM5701 is a single-chip solution incorporating both the BCM5700
60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61 * does not support external SSRAM.
62 *
63 * Broadcom also produces a variation of the BCM5700 under the "Altima"
64 * brand name, which is functionally similar but lacks PCI-X support.
65 *
66 * Without external SSRAM, you can only have at most 4 TX rings,
67 * and the use of the mini RX ring is disabled. This seems to imply
68 * that these features are simply not available on the BCM5701. As a
69 * result, this driver does not implement any support for the mini RX
70 * ring.
71 */
72
73 #include <sys/param.h>
74 #include <sys/systm.h>
75 #include <sys/sockio.h>
76 #include <sys/mbuf.h>
77 #include <sys/malloc.h>
78 #include <sys/kernel.h>
79 #include <sys/socket.h>
80 #include <sys/queue.h>
81
82 #include <net/if.h>
83 #include <net/if_arp.h>
84 #include <net/ethernet.h>
85 #include <net/if_dl.h>
86 #include <net/if_media.h>
87
88 #include <net/bpf.h>
89
90 #include <net/if_types.h>
91 #include <net/if_vlan_var.h>
92
93 #include <netinet/in_systm.h>
94 #include <netinet/in.h>
95 #include <netinet/ip.h>
96
97 #include <vm/vm.h> /* for vtophys */
98 #include <vm/pmap.h> /* for vtophys */
99 #include <machine/atomic.h> /* for atomic_readandclear_32 */
100 #include <machine/clock.h> /* for DELAY */
101 #include <machine/bus_memio.h>
102 #include <machine/bus.h>
103 #include <machine/resource.h>
104 #include <sys/bus.h>
105 #include <sys/rman.h>
106
107 #include <dev/mii/mii.h>
108 #include <dev/mii/miivar.h>
109 #include <dev/mii/miidevs.h>
110 #include <dev/mii/brgphyreg.h>
111
112 #include <pci/pcireg.h>
113 #include <pci/pcivar.h>
114
115 #include <dev/bge/if_bgereg.h>
116
117 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
118
119 /* "controller miibus0" required. See GENERIC if you get errors here. */
120 #include "miibus_if.h"
121
122 #if !defined(lint)
123 static const char rcsid[] =
124 "$FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.42 2007/02/15 10:33:49 bde Exp $";
125 #endif
126
127 /*
128 * Various supported device vendors/types and their names. Note: the
129 * spec seems to indicate that the hardware still has Alteon's vendor
130 * ID burned into it, though it will always be overriden by the vendor
131 * ID in the EEPROM. Just to be safe, we cover all possibilities.
132 */
133 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */
134
135 static struct bge_type bge_devs[] = {
136 { ALT_VENDORID, ALT_DEVICEID_BCM5700,
137 "Broadcom BCM5700 Gigabit Ethernet" },
138 { ALT_VENDORID, ALT_DEVICEID_BCM5701,
139 "Broadcom BCM5701 Gigabit Ethernet" },
140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700,
141 "Broadcom BCM5700 Gigabit Ethernet" },
142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701,
143 "Broadcom BCM5701 Gigabit Ethernet" },
144 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702,
145 "Broadcom BCM5702 Gigabit Ethernet" },
146 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X,
147 "Broadcom BCM5702X Gigabit Ethernet" },
148 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703,
149 "Broadcom BCM5703 Gigabit Ethernet" },
150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X,
151 "Broadcom BCM5703X Gigabit Ethernet" },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C,
153 "Broadcom BCM5704C Dual Gigabit Ethernet" },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S,
155 "Broadcom BCM5704S Dual Gigabit Ethernet" },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705,
157 "Broadcom BCM5705 Gigabit Ethernet" },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K,
159 "Broadcom BCM5705K Gigabit Ethernet" },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M,
161 "Broadcom BCM5705M Gigabit Ethernet" },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT,
163 "Broadcom BCM5705M Gigabit Ethernet" },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C,
165 "Broadcom BCM5714C Gigabit Ethernet" },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721,
167 "Broadcom BCM5721 Gigabit Ethernet" },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750,
169 "Broadcom BCM5750 Gigabit Ethernet" },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M,
171 "Broadcom BCM5750M Gigabit Ethernet" },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751,
173 "Broadcom BCM5751 Gigabit Ethernet" },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M,
175 "Broadcom BCM5751M Gigabit Ethernet" },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782,
177 "Broadcom BCM5782 Gigabit Ethernet" },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788,
179 "Broadcom BCM5788 Gigabit Ethernet" },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789,
181 "Broadcom BCM5789 Gigabit Ethernet" },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901,
183 "Broadcom BCM5901 Fast Ethernet" },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2,
185 "Broadcom BCM5901A2 Fast Ethernet" },
186 { SK_VENDORID, SK_DEVICEID_ALTIMA,
187 "SysKonnect Gigabit Ethernet" },
188 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000,
189 "Altima AC1000 Gigabit Ethernet" },
190 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002,
191 "Altima AC1002 Gigabit Ethernet" },
192 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100,
193 "Altima AC9100 Gigabit Ethernet" },
194 { 0, 0, NULL }
195 };
196
197 static int bge_probe __P((device_t));
198 static int bge_attach __P((device_t));
199 static int bge_detach __P((device_t));
200 static void bge_release_resources
201 __P((struct bge_softc *));
202 static void bge_txeof __P((struct bge_softc *));
203 static void bge_rxeof __P((struct bge_softc *));
204
205 static void bge_tick __P((void *));
206 static void bge_stats_update __P((struct bge_softc *));
207 static void bge_stats_update_regs
208 __P((struct bge_softc *));
209 static int bge_encap __P((struct bge_softc *, struct mbuf *,
210 u_int32_t *));
211
212 static void bge_intr __P((void *));
213 static void bge_start __P((struct ifnet *));
214 static int bge_ioctl __P((struct ifnet *, u_long, caddr_t));
215 static void bge_init __P((void *));
216 static void bge_stop __P((struct bge_softc *));
217 static void bge_watchdog __P((struct ifnet *));
218 static void bge_shutdown __P((device_t));
219 static int bge_ifmedia_upd __P((struct ifnet *));
220 static void bge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
221
222 static u_int8_t bge_eeprom_getbyte __P((struct bge_softc *,
223 int, u_int8_t *));
224 static int bge_read_eeprom __P((struct bge_softc *, caddr_t, int, int));
225
226 static u_int32_t bge_crc __P((caddr_t));
227 static void bge_setmulti __P((struct bge_softc *));
228
229 static void bge_handle_events __P((struct bge_softc *));
230 static int bge_alloc_jumbo_mem __P((struct bge_softc *));
231 static void bge_free_jumbo_mem __P((struct bge_softc *));
232 static void *bge_jalloc __P((struct bge_softc *));
233 static void bge_jfree __P((caddr_t, u_int));
234 static void bge_jref __P((caddr_t, u_int));
235 static int bge_newbuf_std __P((struct bge_softc *, int, struct mbuf *));
236 static int bge_newbuf_jumbo __P((struct bge_softc *, int, struct mbuf *));
237 static int bge_init_rx_ring_std __P((struct bge_softc *));
238 static void bge_free_rx_ring_std __P((struct bge_softc *));
239 static int bge_init_rx_ring_jumbo __P((struct bge_softc *));
240 static void bge_free_rx_ring_jumbo __P((struct bge_softc *));
241 static void bge_free_tx_ring __P((struct bge_softc *));
242 static int bge_init_tx_ring __P((struct bge_softc *));
243
244 static int bge_chipinit __P((struct bge_softc *));
245 static int bge_blockinit __P((struct bge_softc *));
246
247 #ifdef notdef
248 static u_int8_t bge_vpd_readbyte __P((struct bge_softc *, int));
249 static void bge_vpd_read_res __P((struct bge_softc *,
250 struct vpd_res *, int));
251 static void bge_vpd_read __P((struct bge_softc *));
252 #endif
253
254 static u_int32_t bge_readmem_ind
255 __P((struct bge_softc *, int));
256 static void bge_writemem_ind __P((struct bge_softc *, int, int));
257 #ifdef notdef
258 static u_int32_t bge_readreg_ind
259 __P((struct bge_softc *, int));
260 #endif
261 static void bge_writereg_ind __P((struct bge_softc *, int, int));
262
263 static int bge_miibus_readreg __P((device_t, int, int));
264 static int bge_miibus_writereg __P((device_t, int, int, int));
265 static void bge_miibus_statchg __P((device_t));
266
267 static void bge_reset __P((struct bge_softc *));
268
269 static device_method_t bge_methods[] = {
270 /* Device interface */
271 DEVMETHOD(device_probe, bge_probe),
272 DEVMETHOD(device_attach, bge_attach),
273 DEVMETHOD(device_detach, bge_detach),
274 DEVMETHOD(device_shutdown, bge_shutdown),
275
276 /* bus interface */
277 DEVMETHOD(bus_print_child, bus_generic_print_child),
278 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
279
280 /* MII interface */
281 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
282 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
283 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
284
285 { 0, 0 }
286 };
287
288 static driver_t bge_driver = {
289 "bge",
290 bge_methods,
291 sizeof(struct bge_softc)
292 };
293
294 static devclass_t bge_devclass;
295
296 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
297 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
298
299 static u_int32_t
300 bge_readmem_ind(sc, off)
301 struct bge_softc *sc;
302 int off;
303 {
304 device_t dev;
305
306 dev = sc->bge_dev;
307
308 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
309 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
310 }
311
312 static void
313 bge_writemem_ind(sc, off, val)
314 struct bge_softc *sc;
315 int off, val;
316 {
317 device_t dev;
318
319 dev = sc->bge_dev;
320
321 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
322 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
323
324 return;
325 }
326
327 #ifdef notdef
328 static u_int32_t
329 bge_readreg_ind(sc, off)
330 struct bge_softc *sc;
331 int off;
332 {
333 device_t dev;
334
335 dev = sc->bge_dev;
336
337 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
338 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
339 }
340 #endif
341
342 static void
343 bge_writereg_ind(sc, off, val)
344 struct bge_softc *sc;
345 int off, val;
346 {
347 device_t dev;
348
349 dev = sc->bge_dev;
350
351 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
352 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
353
354 return;
355 }
356
357 #ifdef notdef
358 static u_int8_t
359 bge_vpd_readbyte(sc, addr)
360 struct bge_softc *sc;
361 int addr;
362 {
363 int i;
364 device_t dev;
365 u_int32_t val;
366
367 dev = sc->bge_dev;
368 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
369 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
370 DELAY(10);
371 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
372 break;
373 }
374
375 if (i == BGE_TIMEOUT) {
376 printf("bge%d: VPD read timed out\n", sc->bge_unit);
377 return(0);
378 }
379
380 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
381
382 return((val >> ((addr % 4) * 8)) & 0xFF);
383 }
384
385 static void
386 bge_vpd_read_res(sc, res, addr)
387 struct bge_softc *sc;
388 struct vpd_res *res;
389 int addr;
390 {
391 int i;
392 u_int8_t *ptr;
393
394 ptr = (u_int8_t *)res;
395 for (i = 0; i < sizeof(struct vpd_res); i++)
396 ptr[i] = bge_vpd_readbyte(sc, i + addr);
397
398 return;
399 }
400
401 static void
402 bge_vpd_read(sc)
403 struct bge_softc *sc;
404 {
405 int pos = 0, i;
406 struct vpd_res res;
407
408 if (sc->bge_vpd_prodname != NULL)
409 free(sc->bge_vpd_prodname, M_DEVBUF);
410 if (sc->bge_vpd_readonly != NULL)
411 free(sc->bge_vpd_readonly, M_DEVBUF);
412 sc->bge_vpd_prodname = NULL;
413 sc->bge_vpd_readonly = NULL;
414
415 bge_vpd_read_res(sc, &res, pos);
416
417 if (res.vr_id != VPD_RES_ID) {
418 printf("bge%d: bad VPD resource id: expected %x got %x\n",
419 sc->bge_unit, VPD_RES_ID, res.vr_id);
420 return;
421 }
422
423 pos += sizeof(res);
424 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
425 for (i = 0; i < res.vr_len; i++)
426 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
427 sc->bge_vpd_prodname[i] = '\0';
428 pos += i;
429
430 bge_vpd_read_res(sc, &res, pos);
431
432 if (res.vr_id != VPD_RES_READ) {
433 printf("bge%d: bad VPD resource id: expected %x got %x\n",
434 sc->bge_unit, VPD_RES_READ, res.vr_id);
435 return;
436 }
437
438 pos += sizeof(res);
439 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
440 for (i = 0; i < res.vr_len + 1; i++)
441 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
442
443 return;
444 }
445 #endif
446
447 /*
448 * Read a byte of data stored in the EEPROM at address 'addr.' The
449 * BCM570x supports both the traditional bitbang interface and an
450 * auto access interface for reading the EEPROM. We use the auto
451 * access method.
452 */
453 static u_int8_t
454 bge_eeprom_getbyte(sc, addr, dest)
455 struct bge_softc *sc;
456 int addr;
457 u_int8_t *dest;
458 {
459 int i;
460 u_int32_t byte = 0;
461
462 /*
463 * Enable use of auto EEPROM access so we can avoid
464 * having to use the bitbang method.
465 */
466 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
467
468 /* Reset the EEPROM, load the clock period. */
469 CSR_WRITE_4(sc, BGE_EE_ADDR,
470 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
471 DELAY(20);
472
473 /* Issue the read EEPROM command. */
474 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
475
476 /* Wait for completion */
477 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
478 DELAY(10);
479 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
480 break;
481 }
482
483 if (i == BGE_TIMEOUT) {
484 printf("bge%d: eeprom read timed out\n", sc->bge_unit);
485 return(0);
486 }
487
488 /* Get result. */
489 byte = CSR_READ_4(sc, BGE_EE_DATA);
490
491 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
492
493 return(0);
494 }
495
496 /*
497 * Read a sequence of bytes from the EEPROM.
498 */
499 static int
500 bge_read_eeprom(sc, dest, off, cnt)
501 struct bge_softc *sc;
502 caddr_t dest;
503 int off;
504 int cnt;
505 {
506 int err = 0, i;
507 u_int8_t byte = 0;
508
509 for (i = 0; i < cnt; i++) {
510 err = bge_eeprom_getbyte(sc, off + i, &byte);
511 if (err)
512 break;
513 *(dest + i) = byte;
514 }
515
516 return(err ? 1 : 0);
517 }
518
519 static int
520 bge_miibus_readreg(dev, phy, reg)
521 device_t dev;
522 int phy, reg;
523 {
524 struct bge_softc *sc;
525 struct ifnet *ifp;
526 u_int32_t val, autopoll;
527 int i;
528
529 sc = device_get_softc(dev);
530 ifp = &sc->arpcom.ac_if;
531
532 /*
533 * Broadcom's own driver always assumes the internal
534 * PHY is at GMII address 1. On some chips, the PHY responds
535 * to accesses at all addresses, which could cause us to
536 * bogusly attach the PHY 32 times at probe type. Always
537 * restricting the lookup to address 1 is simpler than
538 * trying to figure out which chips revisions should be
539 * special-cased.
540 */
541 if (phy != 1)
542 return(0);
543
544 /* Reading with autopolling on may trigger PCI errors */
545 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
546 if (autopoll & BGE_MIMODE_AUTOPOLL) {
547 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
548 DELAY(40);
549 }
550
551 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
552 BGE_MIPHY(phy)|BGE_MIREG(reg));
553
554 for (i = 0; i < BGE_TIMEOUT; i++) {
555 val = CSR_READ_4(sc, BGE_MI_COMM);
556 if (!(val & BGE_MICOMM_BUSY))
557 break;
558 }
559
560 if (i == BGE_TIMEOUT) {
561 printf("bge%d: PHY read timed out\n", sc->bge_unit);
562 val = 0;
563 goto done;
564 }
565
566 val = CSR_READ_4(sc, BGE_MI_COMM);
567
568 done:
569 if (autopoll & BGE_MIMODE_AUTOPOLL) {
570 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
571 DELAY(40);
572 }
573
574 if (val & BGE_MICOMM_READFAIL)
575 return(0);
576
577 return(val & 0xFFFF);
578 }
579
580 static int
581 bge_miibus_writereg(dev, phy, reg, val)
582 device_t dev;
583 int phy, reg, val;
584 {
585 struct bge_softc *sc;
586 u_int32_t autopoll;
587 int i;
588
589 sc = device_get_softc(dev);
590
591 /* Reading with autopolling on may trigger PCI errors */
592 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
593 if (autopoll & BGE_MIMODE_AUTOPOLL) {
594 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
595 DELAY(40);
596 }
597
598 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
599 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
600
601 for (i = 0; i < BGE_TIMEOUT; i++) {
602 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
603 break;
604 }
605
606 if (autopoll & BGE_MIMODE_AUTOPOLL) {
607 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
608 DELAY(40);
609 }
610
611 if (i == BGE_TIMEOUT) {
612 printf("bge%d: PHY read timed out\n", sc->bge_unit);
613 return(0);
614 }
615
616 return(0);
617 }
618
619 static void
620 bge_miibus_statchg(dev)
621 device_t dev;
622 {
623 struct bge_softc *sc;
624 struct mii_data *mii;
625
626 sc = device_get_softc(dev);
627 mii = device_get_softc(sc->bge_miibus);
628
629 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
630 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) {
631 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
632 } else {
633 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
634 }
635
636 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
637 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
638 } else {
639 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
640 }
641
642 return;
643 }
644
645 /*
646 * Handle events that have triggered interrupts.
647 */
648 static void
649 bge_handle_events(sc)
650 struct bge_softc *sc;
651 {
652
653 return;
654 }
655
656 /*
657 * Memory management for jumbo frames.
658 */
659
660 static int
661 bge_alloc_jumbo_mem(sc)
662 struct bge_softc *sc;
663 {
664 caddr_t ptr;
665 register int i;
666 struct bge_jpool_entry *entry;
667
668 /* Grab a big chunk o' storage. */
669 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
670 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
671
672 if (sc->bge_cdata.bge_jumbo_buf == NULL) {
673 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit);
674 return(ENOBUFS);
675 }
676
677 SLIST_INIT(&sc->bge_jfree_listhead);
678 SLIST_INIT(&sc->bge_jinuse_listhead);
679
680 /*
681 * Now divide it up into 9K pieces and save the addresses
682 * in an array. Note that we play an evil trick here by using
683 * the first few bytes in the buffer to hold the the address
684 * of the softc structure for this interface. This is because
685 * bge_jfree() needs it, but it is called by the mbuf management
686 * code which will not pass it to us explicitly.
687 */
688 ptr = sc->bge_cdata.bge_jumbo_buf;
689 for (i = 0; i < BGE_JSLOTS; i++) {
690 u_int64_t **aptr;
691 aptr = (u_int64_t **)ptr;
692 aptr[0] = (u_int64_t *)sc;
693 ptr += sizeof(u_int64_t);
694 sc->bge_cdata.bge_jslots[i].bge_buf = ptr;
695 sc->bge_cdata.bge_jslots[i].bge_inuse = 0;
696 ptr += (BGE_JLEN - sizeof(u_int64_t));
697 entry = malloc(sizeof(struct bge_jpool_entry),
698 M_DEVBUF, M_NOWAIT);
699 if (entry == NULL) {
700 contigfree(sc->bge_cdata.bge_jumbo_buf,
701 BGE_JMEM, M_DEVBUF);
702 sc->bge_cdata.bge_jumbo_buf = NULL;
703 printf("bge%d: no memory for jumbo "
704 "buffer queue!\n", sc->bge_unit);
705 return(ENOBUFS);
706 }
707 entry->slot = i;
708 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
709 entry, jpool_entries);
710 }
711
712 return(0);
713 }
714
715 static void
716 bge_free_jumbo_mem(sc)
717 struct bge_softc *sc;
718 {
719 int i;
720 struct bge_jpool_entry *entry;
721
722 for (i = 0; i < BGE_JSLOTS; i++) {
723 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
724 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
725 free(entry, M_DEVBUF);
726 }
727
728 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
729
730 return;
731 }
732
733 /*
734 * Allocate a jumbo buffer.
735 */
736 static void *
737 bge_jalloc(sc)
738 struct bge_softc *sc;
739 {
740 struct bge_jpool_entry *entry;
741
742 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
743
744 if (entry == NULL) {
745 printf("bge%d: no free jumbo buffers\n", sc->bge_unit);
746 return(NULL);
747 }
748
749 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
750 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
751 sc->bge_cdata.bge_jslots[entry->slot].bge_inuse = 1;
752 return(sc->bge_cdata.bge_jslots[entry->slot].bge_buf);
753 }
754
755 /*
756 * Adjust usage count on a jumbo buffer.
757 */
758 static void
759 bge_jref(buf, size)
760 caddr_t buf;
761 u_int size;
762 {
763 struct bge_softc *sc;
764 u_int64_t **aptr;
765 register int i;
766
767 /* Extract the softc struct pointer. */
768 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
769 sc = (struct bge_softc *)(aptr[0]);
770
771 if (sc == NULL)
772 panic("bge_jref: can't find softc pointer!");
773
774 if (size != BGE_JUMBO_FRAMELEN)
775 panic("bge_jref: adjusting refcount of buf of wrong size!");
776
777 /* calculate the slot this buffer belongs to */
778
779 i = ((vm_offset_t)aptr
780 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
781
782 if ((i < 0) || (i >= BGE_JSLOTS))
783 panic("bge_jref: asked to reference buffer "
784 "that we don't manage!");
785 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0)
786 panic("bge_jref: buffer already free!");
787 else
788 sc->bge_cdata.bge_jslots[i].bge_inuse++;
789
790 return;
791 }
792
793 /*
794 * Release a jumbo buffer.
795 */
796 static void
797 bge_jfree(buf, size)
798 caddr_t buf;
799 u_int size;
800 {
801 struct bge_softc *sc;
802 u_int64_t **aptr;
803 int i;
804 struct bge_jpool_entry *entry;
805
806 /* Extract the softc struct pointer. */
807 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
808 sc = (struct bge_softc *)(aptr[0]);
809
810 if (sc == NULL)
811 panic("bge_jfree: can't find softc pointer!");
812
813 if (size != BGE_JUMBO_FRAMELEN)
814 panic("bge_jfree: freeing buffer of wrong size!");
815
816 /* calculate the slot this buffer belongs to */
817
818 i = ((vm_offset_t)aptr
819 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
820
821 if ((i < 0) || (i >= BGE_JSLOTS))
822 panic("bge_jfree: asked to free buffer that we don't manage!");
823 else if (sc->bge_cdata.bge_jslots[i].bge_inuse == 0)
824 panic("bge_jfree: buffer already free!");
825 else {
826 sc->bge_cdata.bge_jslots[i].bge_inuse--;
827 if(sc->bge_cdata.bge_jslots[i].bge_inuse == 0) {
828 entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
829 if (entry == NULL)
830 panic("bge_jfree: buffer not in use!");
831 entry->slot = i;
832 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead,
833 jpool_entries);
834 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
835 entry, jpool_entries);
836 }
837 }
838
839 return;
840 }
841
842
843 /*
844 * Intialize a standard receive ring descriptor.
845 */
846 static int
847 bge_newbuf_std(sc, i, m)
848 struct bge_softc *sc;
849 int i;
850 struct mbuf *m;
851 {
852 struct mbuf *m_new = NULL;
853 struct bge_rx_bd *r;
854
855 if (m == NULL) {
856 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
857 if (m_new == NULL) {
858 return(ENOBUFS);
859 }
860
861 MCLGET(m_new, M_DONTWAIT);
862 if (!(m_new->m_flags & M_EXT)) {
863 m_freem(m_new);
864 return(ENOBUFS);
865 }
866 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
867 } else {
868 m_new = m;
869 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
870 m_new->m_data = m_new->m_ext.ext_buf;
871 }
872
873 if (!sc->bge_rx_alignment_bug)
874 m_adj(m_new, ETHER_ALIGN);
875 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
876 r = &sc->bge_rdata->bge_rx_std_ring[i];
877 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
878 r->bge_flags = BGE_RXBDFLAG_END;
879 r->bge_len = m_new->m_len;
880 r->bge_idx = i;
881
882 return(0);
883 }
884
885 /*
886 * Initialize a jumbo receive ring descriptor. This allocates
887 * a jumbo buffer from the pool managed internally by the driver.
888 */
889 static int
890 bge_newbuf_jumbo(sc, i, m)
891 struct bge_softc *sc;
892 int i;
893 struct mbuf *m;
894 {
895 struct mbuf *m_new = NULL;
896 struct bge_rx_bd *r;
897
898 if (m == NULL) {
899 caddr_t *buf = NULL;
900
901 /* Allocate the mbuf. */
902 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
903 if (m_new == NULL) {
904 return(ENOBUFS);
905 }
906
907 /* Allocate the jumbo buffer */
908 buf = bge_jalloc(sc);
909 if (buf == NULL) {
910 m_freem(m_new);
911 printf("bge%d: jumbo allocation failed "
912 "-- packet dropped!\n", sc->bge_unit);
913 return(ENOBUFS);
914 }
915
916 /* Attach the buffer to the mbuf. */
917 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
918 m_new->m_flags |= M_EXT;
919 m_new->m_len = m_new->m_pkthdr.len =
920 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
921 m_new->m_ext.ext_free = bge_jfree;
922 m_new->m_ext.ext_ref = bge_jref;
923 } else {
924 m_new = m;
925 m_new->m_data = m_new->m_ext.ext_buf;
926 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
927 }
928
929 if (!sc->bge_rx_alignment_bug)
930 m_adj(m_new, ETHER_ALIGN);
931 /* Set up the descriptor. */
932 r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
933 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
934 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
935 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
936 r->bge_len = m_new->m_len;
937 r->bge_idx = i;
938
939 return(0);
940 }
941
942 /*
943 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
944 * that's 1MB or memory, which is a lot. For now, we fill only the first
945 * 256 ring entries and hope that our CPU is fast enough to keep up with
946 * the NIC.
947 */
948 static int
949 bge_init_rx_ring_std(sc)
950 struct bge_softc *sc;
951 {
952 int i;
953
954 for (i = 0; i < BGE_SSLOTS; i++) {
955 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
956 return(ENOBUFS);
957 };
958
959 sc->bge_std = i - 1;
960 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
961
962 return(0);
963 }
964
965 static void
966 bge_free_rx_ring_std(sc)
967 struct bge_softc *sc;
968 {
969 int i;
970
971 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
972 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
973 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
974 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
975 }
976 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i],
977 sizeof(struct bge_rx_bd));
978 }
979
980 return;
981 }
982
983 static int
984 bge_init_rx_ring_jumbo(sc)
985 struct bge_softc *sc;
986 {
987 int i;
988 struct bge_rcb *rcb;
989
990 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
991 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
992 return(ENOBUFS);
993 };
994
995 sc->bge_jumbo = i - 1;
996
997 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
998 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
999 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1000
1001 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1002
1003 return(0);
1004 }
1005
1006 static void
1007 bge_free_rx_ring_jumbo(sc)
1008 struct bge_softc *sc;
1009 {
1010 int i;
1011
1012 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1013 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1014 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1015 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1016 }
1017 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i],
1018 sizeof(struct bge_rx_bd));
1019 }
1020
1021 return;
1022 }
1023
1024 static void
1025 bge_free_tx_ring(sc)
1026 struct bge_softc *sc;
1027 {
1028 int i;
1029
1030 if (sc->bge_rdata->bge_tx_ring == NULL)
1031 return;
1032
1033 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1034 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1035 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1036 sc->bge_cdata.bge_tx_chain[i] = NULL;
1037 }
1038 bzero((char *)&sc->bge_rdata->bge_tx_ring[i],
1039 sizeof(struct bge_tx_bd));
1040 }
1041
1042 return;
1043 }
1044
1045 static int
1046 bge_init_tx_ring(sc)
1047 struct bge_softc *sc;
1048 {
1049 sc->bge_txcnt = 0;
1050 sc->bge_tx_saved_considx = 0;
1051
1052 /* Initialize transmit producer index for host-memory send ring. */
1053 sc->bge_tx_prodidx = 0;
1054 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1055 /* 5700 b2 errata */
1056 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1057 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1058
1059 /* NIC-memory send ring not used; initialize to zero. */
1060 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1061 /* 5700 b2 errata */
1062 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1063 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1064
1065 return(0);
1066 }
1067
1068 #define BGE_POLY 0xEDB88320
1069
1070 static u_int32_t
1071 bge_crc(addr)
1072 caddr_t addr;
1073 {
1074 u_int32_t idx, bit, data, crc;
1075
1076 /* Compute CRC for the address value. */
1077 crc = 0xFFFFFFFF; /* initial value */
1078
1079 for (idx = 0; idx < 6; idx++) {
1080 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1081 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0);
1082 }
1083
1084 return(crc & 0x7F);
1085 }
1086
1087 static void
1088 bge_setmulti(sc)
1089 struct bge_softc *sc;
1090 {
1091 struct ifnet *ifp;
1092 struct ifmultiaddr *ifma;
1093 u_int32_t hashes[4] = { 0, 0, 0, 0 };
1094 int h, i;
1095
1096 ifp = &sc->arpcom.ac_if;
1097
1098 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1099 for (i = 0; i < 4; i++)
1100 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1101 return;
1102 }
1103
1104 /* First, zot all the existing filters. */
1105 for (i = 0; i < 4; i++)
1106 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1107
1108 /* Now program new ones. */
1109 for (ifma = ifp->if_multiaddrs.lh_first;
1110 ifma != NULL; ifma = ifma->ifma_link.le_next) {
1111 if (ifma->ifma_addr->sa_family != AF_LINK)
1112 continue;
1113 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1114 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1115 }
1116
1117 for (i = 0; i < 4; i++)
1118 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1119
1120 return;
1121 }
1122
1123 /*
1124 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1125 * self-test results.
1126 */
1127 static int
1128 bge_chipinit(sc)
1129 struct bge_softc *sc;
1130 {
1131 int i;
1132 u_int32_t dma_rw_ctl;
1133
1134 /* Set endianness before we access any non-PCI registers. */
1135 #if BYTE_ORDER == BIG_ENDIAN
1136 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1137 BGE_BIGENDIAN_INIT, 4);
1138 #else
1139 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1140 BGE_LITTLEENDIAN_INIT, 4);
1141 #endif
1142
1143 /*
1144 * Check the 'ROM failed' bit on the RX CPU to see if
1145 * self-tests passed.
1146 */
1147 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1148 printf("bge%d: RX CPU self-diagnostics failed!\n",
1149 sc->bge_unit);
1150 return(ENODEV);
1151 }
1152
1153 /* Clear the MAC control register */
1154 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1155
1156 /*
1157 * Clear the MAC statistics block in the NIC's
1158 * internal memory.
1159 */
1160 for (i = BGE_STATS_BLOCK;
1161 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
1162 BGE_MEMWIN_WRITE(sc, i, 0);
1163
1164 for (i = BGE_STATUS_BLOCK;
1165 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
1166 BGE_MEMWIN_WRITE(sc, i, 0);
1167
1168 /* Set up the PCI DMA control register. */
1169 if (sc->bge_pcie) {
1170 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1171 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1172 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1173 } else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1174 BGE_PCISTATE_PCI_BUSMODE) {
1175 /* Conventional PCI bus */
1176 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1177 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1178 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1179 (0x0F);
1180 } else {
1181 /* PCI-X bus */
1182 /*
1183 * The 5704 uses a different encoding of read/write
1184 * watermarks.
1185 */
1186 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1187 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1188 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1189 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1190 else
1191 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1192 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1193 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1194 (0x0F);
1195
1196 /*
1197 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1198 * for hardware bugs.
1199 */
1200 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1201 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1202 u_int32_t tmp;
1203
1204 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1205 if (tmp == 0x6 || tmp == 0x7)
1206 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1207 }
1208 }
1209
1210 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1211 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1212 sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1213 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1214 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1215 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1216
1217 /*
1218 * Set up general mode register.
1219 */
1220 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1221 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1222 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1223 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1224
1225 /*
1226 * Disable memory write invalidate. Apparently it is not supported
1227 * properly by these devices.
1228 */
1229 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1230
1231 #ifdef __brokenalpha__
1232 /*
1233 * Must insure that we do not cross an 8K (bytes) boundary
1234 * for DMA reads. Our highest limit is 1K bytes. This is a
1235 * restriction on some ALPHA platforms with early revision
1236 * 21174 PCI chipsets, such as the AlphaPC 164lx
1237 */
1238 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1239 BGE_PCI_READ_BNDRY_1024BYTES, 4);
1240 #endif
1241
1242 /* Set the timer prescaler (always 66Mhz) */
1243 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1244
1245 return(0);
1246 }
1247
1248 static int
1249 bge_blockinit(sc)
1250 struct bge_softc *sc;
1251 {
1252 struct bge_rcb *rcb;
1253 volatile struct bge_rcb *vrcb;
1254 int i;
1255
1256 /*
1257 * Initialize the memory window pointer register so that
1258 * we can access the first 32K of internal NIC RAM. This will
1259 * allow us to set up the TX send ring RCBs and the RX return
1260 * ring RCBs, plus other things which live in NIC memory.
1261 */
1262 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1263
1264 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1265
1266 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1267 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1268 /* Configure mbuf memory pool */
1269 if (sc->bge_extram) {
1270 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1271 BGE_EXT_SSRAM);
1272 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1273 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1274 else
1275 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1276 } else {
1277 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1278 BGE_BUFFPOOL_1);
1279 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1280 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1281 else
1282 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1283 }
1284
1285 /* Configure DMA resource pool */
1286 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1287 BGE_DMA_DESCRIPTORS);
1288 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1289 }
1290
1291 /* Configure mbuf pool watermarks */
1292 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1293 sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1294 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1295 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1296 } else {
1297 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1298 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1299 }
1300 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1301
1302 /* Configure DMA resource watermarks */
1303 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1304 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1305
1306 /* Enable buffer manager */
1307 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1308 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1309 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1310 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1311
1312 /* Poll for buffer manager start indication */
1313 for (i = 0; i < BGE_TIMEOUT; i++) {
1314 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1315 break;
1316 DELAY(10);
1317 }
1318
1319 if (i == BGE_TIMEOUT) {
1320 printf("bge%d: buffer manager failed to start\n",
1321 sc->bge_unit);
1322 return(ENXIO);
1323 }
1324 }
1325
1326 /* Enable flow-through queues */
1327 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1328 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1329
1330 /* Wait until queue initialization is complete */
1331 for (i = 0; i < BGE_TIMEOUT; i++) {
1332 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1333 break;
1334 DELAY(10);
1335 }
1336
1337 if (i == BGE_TIMEOUT) {
1338 printf("bge%d: flow-through queue init failed\n",
1339 sc->bge_unit);
1340 return(ENXIO);
1341 }
1342
1343 /* Initialize the standard RX ring control block */
1344 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1345 BGE_HOSTADDR(rcb->bge_hostaddr,
1346 vtophys(&sc->bge_rdata->bge_rx_std_ring));
1347 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1348 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1349 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1350 else
1351 rcb->bge_maxlen_flags =
1352 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1353 if (sc->bge_extram)
1354 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1355 else
1356 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1357 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1358 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1359 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1360 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1361
1362 /*
1363 * Initialize the jumbo RX ring control block
1364 * We set the 'ring disabled' bit in the flags
1365 * field until we're actually ready to start
1366 * using this ring (i.e. once we set the MTU
1367 * high enough to require it).
1368 */
1369 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1370 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1371 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1372 BGE_HOSTADDR(rcb->bge_hostaddr,
1373 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring));
1374 rcb->bge_maxlen_flags =
1375 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1376 BGE_RCB_FLAG_RING_DISABLED);
1377 if (sc->bge_extram)
1378 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1379 else
1380 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1381 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1382 rcb->bge_hostaddr.bge_addr_hi);
1383 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1384 rcb->bge_hostaddr.bge_addr_lo);
1385 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1386 rcb->bge_maxlen_flags);
1387 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1388
1389 /* Set up dummy disabled mini ring RCB */
1390 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1391 rcb->bge_maxlen_flags =
1392 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1393 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1394 rcb->bge_maxlen_flags);
1395 }
1396
1397 /*
1398 * Set the BD ring replentish thresholds. The recommended
1399 * values are 1/8th the number of descriptors allocated to
1400 * each ring.
1401 */
1402 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1403 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1404
1405 /*
1406 * Disable all unused send rings by setting the 'ring disabled'
1407 * bit in the flags field of all the TX send ring control blocks.
1408 * These are located in NIC memory.
1409 */
1410 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1411 BGE_SEND_RING_RCB);
1412 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1413 vrcb->bge_maxlen_flags =
1414 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1415 vrcb->bge_nicaddr = 0;
1416 vrcb++;
1417 }
1418
1419 /* Configure TX RCB 0 (we use only the first ring) */
1420 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1421 BGE_SEND_RING_RCB);
1422 vrcb->bge_hostaddr.bge_addr_hi = 0;
1423 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring));
1424 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1425 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1426 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1427 vrcb->bge_maxlen_flags =
1428 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1429
1430 /* Disable all unused RX return rings */
1431 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1432 BGE_RX_RETURN_RING_RCB);
1433 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1434 vrcb->bge_hostaddr.bge_addr_hi = 0;
1435 vrcb->bge_hostaddr.bge_addr_lo = 0;
1436 vrcb->bge_maxlen_flags =
1437 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1438 BGE_RCB_FLAG_RING_DISABLED);
1439 vrcb->bge_nicaddr = 0;
1440 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1441 (i * (sizeof(u_int64_t))), 0);
1442 vrcb++;
1443 }
1444
1445 /* Initialize RX ring indexes */
1446 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1447 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1448 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1449
1450 /*
1451 * Set up RX return ring 0
1452 * Note that the NIC address for RX return rings is 0x00000000.
1453 * The return rings live entirely within the host, so the
1454 * nicaddr field in the RCB isn't used.
1455 */
1456 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1457 BGE_RX_RETURN_RING_RCB);
1458 vrcb->bge_hostaddr.bge_addr_hi = 0;
1459 BGE_HOSTADDR(vrcb->bge_hostaddr,
1460 vtophys(&sc->bge_rdata->bge_rx_return_ring));
1461 vrcb->bge_nicaddr = 0x00000000;
1462 vrcb->bge_maxlen_flags =
1463 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
1464
1465 /* Set random backoff seed for TX */
1466 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1467 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1468 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1469 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1470 BGE_TX_BACKOFF_SEED_MASK);
1471
1472 /* Set inter-packet gap */
1473 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1474
1475 /*
1476 * Specify which ring to use for packets that don't match
1477 * any RX rules.
1478 */
1479 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1480
1481 /*
1482 * Configure number of RX lists. One interrupt distribution
1483 * list, sixteen active lists, one bad frames class.
1484 */
1485 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1486
1487 /* Inialize RX list placement stats mask. */
1488 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1489 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1490
1491 /* Disable host coalescing until we get it set up */
1492 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1493
1494 /* Poll to make sure it's shut down. */
1495 for (i = 0; i < BGE_TIMEOUT; i++) {
1496 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1497 break;
1498 DELAY(10);
1499 }
1500
1501 if (i == BGE_TIMEOUT) {
1502 printf("bge%d: host coalescing engine failed to idle\n",
1503 sc->bge_unit);
1504 return(ENXIO);
1505 }
1506
1507 /* Set up host coalescing defaults */
1508 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1509 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1510 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1511 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1512 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1513 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1514 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1515 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1516 }
1517 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1518 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1519
1520 /* Set up address of statistics block */
1521 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1522 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1523 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1524 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1525 vtophys(&sc->bge_rdata->bge_info.bge_stats));
1526
1527 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1528 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1529 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1530 }
1531
1532 /* Set up address of status block */
1533 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1534 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1535 vtophys(&sc->bge_rdata->bge_status_block));
1536
1537 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1538 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1539
1540 /* Turn on host coalescing state machine */
1541 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1542
1543 /* Turn on RX BD completion state machine and enable attentions */
1544 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1545 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1546
1547 /* Turn on RX list placement state machine */
1548 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1549
1550 /* Turn on RX list selector state machine. */
1551 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1552 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1553 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1554
1555 /* Turn on DMA, clear stats */
1556 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1557 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1558 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1559 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1560 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1561
1562 /* Set misc. local control, enable interrupts on attentions */
1563 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1564
1565 #ifdef notdef
1566 /* Assert GPIO pins for PHY reset */
1567 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1568 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1569 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1570 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1571 #endif
1572
1573 /* Turn on DMA completion state machine */
1574 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1575 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1576 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1577
1578 /* Turn on write DMA state machine */
1579 CSR_WRITE_4(sc, BGE_WDMA_MODE,
1580 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1581
1582 /* Turn on read DMA state machine */
1583 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1584 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1585
1586 /* Turn on RX data completion state machine */
1587 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1588
1589 /* Turn on RX BD initiator state machine */
1590 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1591
1592 /* Turn on RX data and RX BD initiator state machine */
1593 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1594
1595 /* Turn on Mbuf cluster free state machine */
1596 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1597 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1598 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1599
1600 /* Turn on send BD completion state machine */
1601 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1602
1603 /* Turn on send data completion state machine */
1604 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1605
1606 /* Turn on send data initiator state machine */
1607 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1608
1609 /* Turn on send BD initiator state machine */
1610 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1611
1612 /* Turn on send BD selector state machine */
1613 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1614
1615 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1616 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1617 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1618
1619 /* ack/clear link change events */
1620 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1621 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1622 BGE_MACSTAT_LINK_CHANGED);
1623
1624 /* Enable PHY auto polling (for MII/GMII only) */
1625 if (sc->bge_tbi) {
1626 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1627 } else {
1628 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1629 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1630 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1631 BGE_EVTENB_MI_INTERRUPT);
1632 }
1633
1634 /* Enable link state change attentions. */
1635 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1636
1637 return(0);
1638 }
1639
1640 /*
1641 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1642 * against our list and return its name if we find a match. Note
1643 * that since the Broadcom controller contains VPD support, we
1644 * can get the device name string from the controller itself instead
1645 * of the compiled-in string. This is a little slow, but it guarantees
1646 * we'll always announce the right product name.
1647 */
1648 static int
1649 bge_probe(dev)
1650 device_t dev;
1651 {
1652 struct bge_type *t;
1653 struct bge_softc *sc;
1654 char *descbuf;
1655
1656 t = bge_devs;
1657
1658 sc = device_get_softc(dev);
1659 bzero(sc, sizeof(struct bge_softc));
1660 sc->bge_unit = device_get_unit(dev);
1661 sc->bge_dev = dev;
1662
1663 while(t->bge_name != NULL) {
1664 if ((pci_get_vendor(dev) == t->bge_vid) &&
1665 (pci_get_device(dev) == t->bge_did)) {
1666 #ifdef notdef
1667 bge_vpd_read(sc);
1668 device_set_desc(dev, sc->bge_vpd_prodname);
1669 #endif
1670 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
1671 if (descbuf == NULL)
1672 return(ENOMEM);
1673 snprintf(descbuf, BGE_DEVDESC_MAX,
1674 "%s, ASIC rev. %#04x", t->bge_name,
1675 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1676 device_set_desc_copy(dev, descbuf);
1677 if (pci_get_subvendor(dev) == DELL_VENDORID)
1678 sc->bge_no_3_led = 1;
1679 free(descbuf, M_TEMP);
1680 return(0);
1681 }
1682 t++;
1683 }
1684
1685 return(ENXIO);
1686 }
1687
1688 static int
1689 bge_attach(dev)
1690 device_t dev;
1691 {
1692 int s;
1693 u_int32_t command;
1694 struct ifnet *ifp;
1695 struct bge_softc *sc;
1696 u_int32_t hwcfg = 0;
1697 u_int32_t mac_addr = 0;
1698 int unit, error = 0, rid;
1699
1700 s = splimp();
1701
1702 sc = device_get_softc(dev);
1703 unit = device_get_unit(dev);
1704 sc->bge_dev = dev;
1705 sc->bge_unit = unit;
1706
1707 /*
1708 * Map control/status registers.
1709 */
1710 command = pci_read_config(dev, PCIR_COMMAND, 4);
1711 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1712 pci_write_config(dev, PCIR_COMMAND, command, 4);
1713 command = pci_read_config(dev, PCIR_COMMAND, 4);
1714
1715 if (!(command & PCIM_CMD_MEMEN)) {
1716 printf("bge%d: failed to enable memory mapping!\n", unit);
1717 error = ENXIO;
1718 goto fail;
1719 }
1720
1721 rid = BGE_PCI_BAR0;
1722 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1723 0, ~0, 1, RF_ACTIVE);
1724
1725 if (sc->bge_res == NULL) {
1726 printf ("bge%d: couldn't map memory\n", unit);
1727 error = ENXIO;
1728 goto fail;
1729 }
1730
1731 sc->bge_btag = rman_get_bustag(sc->bge_res);
1732 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1733 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1734
1735 /*
1736 * XXX FIXME: rman_get_virtual() on the alpha is currently
1737 * broken and returns a physical address instead of a kernel
1738 * virtual address. Consequently, we need to do a little
1739 * extra mangling of the vhandle on the alpha. This should
1740 * eventually be fixed! The whole idea here is to get rid
1741 * of platform dependencies.
1742 */
1743 #ifdef __alpha__
1744 if (pci_cvt_to_bwx(sc->bge_vhandle))
1745 sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle);
1746 else
1747 sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle);
1748 sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle);
1749 #endif
1750
1751 /* Allocate interrupt */
1752 rid = 0;
1753
1754 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1755 RF_SHAREABLE | RF_ACTIVE);
1756
1757 if (sc->bge_irq == NULL) {
1758 printf("bge%d: couldn't map interrupt\n", unit);
1759 error = ENXIO;
1760 goto fail;
1761 }
1762
1763 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET,
1764 bge_intr, sc, &sc->bge_intrhand);
1765
1766 if (error) {
1767 bge_release_resources(sc);
1768 printf("bge%d: couldn't set up irq\n", unit);
1769 goto fail;
1770 }
1771
1772 sc->bge_unit = unit;
1773
1774 /* Save ASIC rev. */
1775
1776 sc->bge_chipid =
1777 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1778 BGE_PCIMISCCTL_ASICREV;
1779 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1780 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1781
1782 /*
1783 * Treat the 5714 like the 5750 until we have more info
1784 * on this chip.
1785 */
1786 if (sc->bge_asicrev == BGE_ASICREV_BCM5714)
1787 sc->bge_asicrev = BGE_ASICREV_BCM5750;
1788
1789 /*
1790 * XXX: Broadcom Linux driver. Not in specs or eratta.
1791 * PCI-Express?
1792 */
1793 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1794 u_int32_t v;
1795
1796 v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4);
1797 if (((v >> 8) & 0xff) == BGE_PCIE_CAPID_REG) {
1798 v = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
1799 if ((v & 0xff) == BGE_PCIE_CAPID)
1800 sc->bge_pcie = 1;
1801 }
1802 }
1803
1804 /* Try to reset the chip. */
1805 bge_reset(sc);
1806
1807 if (bge_chipinit(sc)) {
1808 printf("bge%d: chip initialization failed\n", sc->bge_unit);
1809 bge_release_resources(sc);
1810 error = ENXIO;
1811 goto fail;
1812 }
1813
1814 /*
1815 * Get station address from the EEPROM.
1816 */
1817 mac_addr = bge_readmem_ind(sc, 0x0c14);
1818 if ((mac_addr >> 16) == 0x484b) {
1819 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8);
1820 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr;
1821 mac_addr = bge_readmem_ind(sc, 0x0c18);
1822 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24);
1823 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16);
1824 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8);
1825 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr;
1826 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1827 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1828 printf("bge%d: failed to read station address\n", unit);
1829 bge_release_resources(sc);
1830 error = ENXIO;
1831 goto fail;
1832 }
1833
1834 /*
1835 * A Broadcom chip was detected. Inform the world.
1836 */
1837 printf("bge%d: Ethernet address: %6D\n", unit,
1838 sc->arpcom.ac_enaddr, ":");
1839
1840 /* Allocate the general information block and ring buffers. */
1841 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1842 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1843
1844 if (sc->bge_rdata == NULL) {
1845 bge_release_resources(sc);
1846 error = ENXIO;
1847 printf("bge%d: no memory for list buffers!\n", sc->bge_unit);
1848 goto fail;
1849 }
1850
1851 bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1852
1853 /* Save ASIC rev. */
1854
1855 sc->bge_chipid =
1856 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1857 BGE_PCIMISCCTL_ASICREV;
1858 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1859 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1860
1861 /*
1862 * Try to allocate memory for jumbo buffers.
1863 * The 5705 does not appear to support jumbo frames.
1864 */
1865 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1866 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1867 if (bge_alloc_jumbo_mem(sc)) {
1868 printf("bge%d: jumbo buffer allocation "
1869 "failed\n", sc->bge_unit);
1870 bge_release_resources(sc);
1871 error = ENXIO;
1872 goto fail;
1873 }
1874 }
1875
1876 /* Set default tuneable values. */
1877 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1878 sc->bge_rx_coal_ticks = 150;
1879 sc->bge_tx_coal_ticks = 150;
1880 sc->bge_rx_max_coal_bds = 64;
1881 sc->bge_tx_max_coal_bds = 128;
1882
1883 /* 5705 limits RX return ring to 512 entries. */
1884 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1885 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1886 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1887 else
1888 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1889
1890 /* Set up ifnet structure */
1891 ifp = &sc->arpcom.ac_if;
1892 ifp->if_softc = sc;
1893 ifp->if_unit = sc->bge_unit;
1894 ifp->if_name = "bge";
1895 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1896 ifp->if_ioctl = bge_ioctl;
1897 ifp->if_output = ether_output;
1898 ifp->if_start = bge_start;
1899 ifp->if_watchdog = bge_watchdog;
1900 ifp->if_init = bge_init;
1901 ifp->if_mtu = ETHERMTU;
1902 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1;
1903 ifp->if_hwassist = BGE_CSUM_FEATURES;
1904 ifp->if_capabilities = IFCAP_HWCSUM;
1905 #ifdef DEVICE_POLLING
1906 ifp->if_capabilities |= IFCAP_POLLING;
1907 #endif
1908 ifp->if_capenable = ifp->if_capabilities;
1909
1910 /*
1911 * Figure out what sort of media we have by checking the
1912 * hardware config word in the first 32k of NIC internal memory,
1913 * or fall back to examining the EEPROM if necessary.
1914 * Note: on some BCM5700 cards, this value appears to be unset.
1915 * If that's the case, we have to rely on identifying the NIC
1916 * by its PCI subsystem ID, as we do below for the SysKonnect
1917 * SK-9D41.
1918 */
1919 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1920 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1921 else {
1922 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1923 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1924 hwcfg = ntohl(hwcfg);
1925 }
1926
1927 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1928 sc->bge_tbi = 1;
1929
1930 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1931 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
1932 sc->bge_tbi = 1;
1933
1934 if (sc->bge_tbi) {
1935 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1936 bge_ifmedia_upd, bge_ifmedia_sts);
1937 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1938 ifmedia_add(&sc->bge_ifmedia,
1939 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1940 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1941 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1942 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1943 } else {
1944 /*
1945 * Do transceiver setup.
1946 */
1947 if (mii_phy_probe(dev, &sc->bge_miibus,
1948 bge_ifmedia_upd, bge_ifmedia_sts)) {
1949 printf("bge%d: MII without any PHY!\n", sc->bge_unit);
1950 bge_release_resources(sc);
1951 bge_free_jumbo_mem(sc);
1952 error = ENXIO;
1953 goto fail;
1954 }
1955 }
1956
1957 /*
1958 * When using the BCM5701 in PCI-X mode, data corruption has
1959 * been observed in the first few bytes of some received packets.
1960 * Aligning the packet buffer in memory eliminates the corruption.
1961 * Unfortunately, this misaligns the packet payloads. On platforms
1962 * which do not support unaligned accesses, we will realign the
1963 * payloads by copying the received packets.
1964 */
1965 switch (sc->bge_chipid) {
1966 case BGE_CHIPID_BCM5701_A0:
1967 case BGE_CHIPID_BCM5701_B0:
1968 case BGE_CHIPID_BCM5701_B2:
1969 case BGE_CHIPID_BCM5701_B5:
1970 /* If in PCI-X mode, work around the alignment bug. */
1971 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1972 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1973 BGE_PCISTATE_PCI_BUSSPEED)
1974 sc->bge_rx_alignment_bug = 1;
1975 break;
1976 }
1977
1978 /*
1979 * Call MI attach routine.
1980 */
1981 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1982 callout_handle_init(&sc->bge_stat_ch);
1983
1984 fail:
1985 splx(s);
1986
1987 return(error);
1988 }
1989
1990 static int
1991 bge_detach(dev)
1992 device_t dev;
1993 {
1994 struct bge_softc *sc;
1995 struct ifnet *ifp;
1996 int s;
1997
1998 s = splimp();
1999
2000 sc = device_get_softc(dev);
2001 ifp = &sc->arpcom.ac_if;
2002
2003 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
2004 bge_stop(sc);
2005 bge_reset(sc);
2006
2007 if (sc->bge_tbi) {
2008 ifmedia_removeall(&sc->bge_ifmedia);
2009 } else {
2010 bus_generic_detach(dev);
2011 device_delete_child(dev, sc->bge_miibus);
2012 }
2013
2014 bge_release_resources(sc);
2015 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2016 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2017 bge_free_jumbo_mem(sc);
2018
2019 splx(s);
2020
2021 return(0);
2022 }
2023
2024 static void
2025 bge_release_resources(sc)
2026 struct bge_softc *sc;
2027 {
2028 device_t dev;
2029
2030 dev = sc->bge_dev;
2031
2032 if (sc->bge_vpd_prodname != NULL)
2033 free(sc->bge_vpd_prodname, M_DEVBUF);
2034
2035 if (sc->bge_vpd_readonly != NULL)
2036 free(sc->bge_vpd_readonly, M_DEVBUF);
2037
2038 if (sc->bge_intrhand != NULL)
2039 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2040
2041 if (sc->bge_irq != NULL)
2042 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2043
2044 if (sc->bge_res != NULL)
2045 bus_release_resource(dev, SYS_RES_MEMORY,
2046 BGE_PCI_BAR0, sc->bge_res);
2047
2048 if (sc->bge_rdata != NULL)
2049 contigfree(sc->bge_rdata,
2050 sizeof(struct bge_ring_data), M_DEVBUF);
2051
2052 return;
2053 }
2054
2055 static void
2056 bge_reset(sc)
2057 struct bge_softc *sc;
2058 {
2059 device_t dev;
2060 u_int32_t cachesize, command, pcistate, reset;
2061 int i, val = 0;
2062
2063 dev = sc->bge_dev;
2064
2065 /* Save some important PCI state. */
2066 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2067 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2068 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2069
2070 pci_write_config(dev, BGE_PCI_MISC_CTL,
2071 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2072 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2073
2074 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2075
2076 /* XXX: Broadcom Linux driver. */
2077 if (sc->bge_pcie) {
2078 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2079 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2080 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2081 /* Prevent PCIE link training during global reset */
2082 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2083 reset |= (1<<29);
2084 }
2085 }
2086
2087 /* Issue global reset */
2088 bge_writereg_ind(sc, BGE_MISC_CFG, reset);
2089
2090 DELAY(1000);
2091
2092 /* XXX: Broadcom Linux driver. */
2093 if (sc->bge_pcie) {
2094 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2095 uint32_t v;
2096
2097 DELAY(500000); /* wait for link training to complete */
2098 v = pci_read_config(dev, 0xc4, 4);
2099 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2100 }
2101 /* Set PCIE max payload size and clear error status. */
2102 pci_write_config(dev, 0xd8, 0xf5000, 4);
2103 }
2104
2105 /* Reset some of the PCI state that got zapped by reset */
2106 pci_write_config(dev, BGE_PCI_MISC_CTL,
2107 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2108 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2109 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2110 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2111 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
2112
2113 /* Enable memory arbiter. */
2114 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2115 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2116 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2117
2118 /*
2119 * Prevent PXE restart: write a magic number to the
2120 * general communications memory at 0xB50.
2121 */
2122 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2123 /*
2124 * Poll the value location we just wrote until
2125 * we see the 1's complement of the magic number.
2126 * This indicates that the firmware initialization
2127 * is complete.
2128 */
2129 for (i = 0; i < BGE_TIMEOUT; i++) {
2130 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2131 if (val == ~BGE_MAGIC_NUMBER)
2132 break;
2133 DELAY(10);
2134 }
2135
2136 if (i == BGE_TIMEOUT) {
2137 printf("bge%d: firmware handshake timed out\n", sc->bge_unit);
2138 return;
2139 }
2140
2141 /*
2142 * XXX Wait for the value of the PCISTATE register to
2143 * return to its original pre-reset state. This is a
2144 * fairly good indicator of reset completion. If we don't
2145 * wait for the reset to fully complete, trying to read
2146 * from the device's non-PCI registers may yield garbage
2147 * results.
2148 */
2149 for (i = 0; i < BGE_TIMEOUT; i++) {
2150 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2151 break;
2152 DELAY(10);
2153 }
2154
2155 /* Fix up byte swapping */
2156 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
2157 BGE_MODECTL_BYTESWAP_DATA);
2158
2159 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2160
2161 /*
2162 * The 5704 in TBI mode apparently needs some special
2163 * adjustment to insure the SERDES drive level is set
2164 * to 1.2V.
2165 */
2166 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) {
2167 uint32_t serdescfg;
2168 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2169 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2170 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2171 }
2172
2173 /* XXX: Broadcom Linux driver. */
2174 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2175 uint32_t v;
2176
2177 v = CSR_READ_4(sc, 0x7c00);
2178 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2179 }
2180 DELAY(10000);
2181
2182 return;
2183 }
2184
2185 /*
2186 * Frame reception handling. This is called if there's a frame
2187 * on the receive return list.
2188 *
2189 * Note: we have to be able to handle two possibilities here:
2190 * 1) the frame is from the jumbo recieve ring
2191 * 2) the frame is from the standard receive ring
2192 */
2193
2194 static void
2195 bge_rxeof(sc)
2196 struct bge_softc *sc;
2197 {
2198 struct ifnet *ifp;
2199 int stdcnt = 0, jumbocnt = 0;
2200
2201 ifp = &sc->arpcom.ac_if;
2202
2203 while(sc->bge_rx_saved_considx !=
2204 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
2205 struct bge_rx_bd *cur_rx;
2206 u_int32_t rxidx;
2207 struct ether_header *eh;
2208 struct mbuf *m = NULL;
2209 u_int16_t vlan_tag = 0;
2210 int have_tag = 0;
2211
2212 #ifdef DEVICE_POLLING
2213 if (ifp->if_ipending & IFF_POLLING) {
2214 if (sc->rxcycles <= 0)
2215 break;
2216 sc->rxcycles--;
2217 }
2218 #endif /* DEVICE_POLLING */
2219
2220 cur_rx =
2221 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
2222
2223 rxidx = cur_rx->bge_idx;
2224 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2225
2226 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2227 have_tag = 1;
2228 vlan_tag = cur_rx->bge_vlan_tag;
2229 }
2230
2231 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2232 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2233 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2234 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2235 jumbocnt++;
2236 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2237 ifp->if_ierrors++;
2238 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2239 continue;
2240 }
2241 if (bge_newbuf_jumbo(sc,
2242 sc->bge_jumbo, NULL) == ENOBUFS) {
2243 ifp->if_ierrors++;
2244 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2245 continue;
2246 }
2247 } else {
2248 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2249 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2250 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2251 stdcnt++;
2252 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2253 ifp->if_ierrors++;
2254 bge_newbuf_std(sc, sc->bge_std, m);
2255 continue;
2256 }
2257 if (bge_newbuf_std(sc, sc->bge_std,
2258 NULL) == ENOBUFS) {
2259 ifp->if_ierrors++;
2260 bge_newbuf_std(sc, sc->bge_std, m);
2261 continue;
2262 }
2263 }
2264
2265 ifp->if_ipackets++;
2266 #ifndef __i386__
2267 /*
2268 * The i386 allows unaligned accesses, but for other
2269 * platforms we must make sure the payload is aligned.
2270 */
2271 if (sc->bge_rx_alignment_bug) {
2272 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2273 cur_rx->bge_len);
2274 m->m_data += ETHER_ALIGN;
2275 }
2276 #endif
2277 eh = mtod(m, struct ether_header *);
2278 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2279 m->m_pkthdr.rcvif = ifp;
2280
2281 /* Remove header from mbuf and pass it on. */
2282 m_adj(m, sizeof(struct ether_header));
2283
2284 #if 0 /* currently broken for some packets, possibly related to TCP options */
2285 if (ifp->if_hwassist) {
2286 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2287 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2288 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2289 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2290 m->m_pkthdr.csum_data =
2291 cur_rx->bge_tcp_udp_csum;
2292 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2293 }
2294 }
2295 #endif
2296
2297 /*
2298 * If we received a packet with a vlan tag, pass it
2299 * to vlan_input() instead of ether_input().
2300 */
2301 if (have_tag) {
2302 VLAN_INPUT_TAG(eh, m, vlan_tag);
2303 have_tag = vlan_tag = 0;
2304 continue;
2305 }
2306
2307 ether_input(ifp, eh, m);
2308 }
2309
2310 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2311 if (stdcnt)
2312 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2313 if (jumbocnt)
2314 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2315
2316 return;
2317 }
2318
2319 static void
2320 bge_txeof(sc)
2321 struct bge_softc *sc;
2322 {
2323 struct bge_tx_bd *cur_tx = NULL;
2324 struct ifnet *ifp;
2325
2326 ifp = &sc->arpcom.ac_if;
2327
2328 /*
2329 * Go through our tx ring and free mbufs for those
2330 * frames that have been sent.
2331 */
2332 while (sc->bge_tx_saved_considx !=
2333 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
2334 u_int32_t idx = 0;
2335
2336 idx = sc->bge_tx_saved_considx;
2337 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
2338 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2339 ifp->if_opackets++;
2340 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2341 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2342 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2343 }
2344 sc->bge_txcnt--;
2345 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2346 ifp->if_timer = 0;
2347 }
2348
2349 if (cur_tx != NULL)
2350 ifp->if_flags &= ~IFF_OACTIVE;
2351
2352 return;
2353 }
2354
2355 #ifdef DEVICE_POLLING
2356 static poll_handler_t bge_poll;
2357
2358 static void
2359 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2360 {
2361 struct bge_softc *sc = ifp->if_softc;
2362
2363 if (!(ifp->if_capenable & IFCAP_POLLING)) {
2364 ether_poll_deregister(ifp);
2365 cmd = POLL_DEREGISTER;
2366 }
2367 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
2368 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
2369 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
2370 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2371 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2372 return;
2373 }
2374
2375 sc->rxcycles = count;
2376
2377 if (!(ifp->if_flags & IFF_RUNNING))
2378 return;
2379
2380 bge_rxeof(sc);
2381 bge_txeof(sc);
2382 if (ifp->if_snd.ifq_head != NULL)
2383 bge_start(ifp);
2384
2385 if (cmd == POLL_AND_CHECK_STATUS) {
2386 u_int32_t statusword;
2387 u_int32_t status, mimode;
2388
2389 statusword =
2390 atomic_readandclear_32(&sc->bge_rdata->bge_status_block.bge_status);
2391
2392 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2393 status = CSR_READ_4(sc, BGE_MAC_STS);
2394 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2395 sc->bge_link = 0;
2396 untimeout(bge_tick, sc, sc->bge_stat_ch);
2397 bge_tick(sc);
2398 /* Clear the interrupt */
2399 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2400 BGE_EVTENB_MI_INTERRUPT);
2401 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2402 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2403 BRGPHY_INTRS);
2404 }
2405 } else {
2406 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) {
2407 status = CSR_READ_4(sc, BGE_MAC_STS);
2408 mimode = CSR_READ_4(sc, BGE_MI_MODE);
2409 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR|
2410 BGE_MACSTAT_MI_COMPLETE)) && (!sc->bge_tbi &&
2411 (mimode & BGE_MIMODE_AUTOPOLL))) {
2412 sc->bge_link = 0;
2413 untimeout(bge_tick, sc, sc->bge_stat_ch);
2414 bge_tick(sc);
2415 }
2416 /* Clear the interrupt */
2417 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2418 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2419 BGE_MACSTAT_LINK_CHANGED);
2420
2421 /* Force flush the status block cached by PCI bridge */
2422 CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2423 }
2424 }
2425 }
2426 }
2427 #endif /* DEVICE_POLLING */
2428
2429 static void
2430 bge_intr(xsc)
2431 void *xsc;
2432 {
2433 struct bge_softc *sc;
2434 struct ifnet *ifp;
2435 u_int32_t statusword;
2436 u_int32_t status, mimode;
2437
2438
2439 sc = xsc;
2440 ifp = &sc->arpcom.ac_if;
2441
2442 #ifdef DEVICE_POLLING
2443 if (ifp->if_ipending & IFF_POLLING)
2444 return;
2445 if ((ifp->if_capenable & IFCAP_POLLING) &&
2446 ether_poll_register(bge_poll, ifp)) { /* ok, disable interrupts */
2447 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2448 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2449 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2450 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2451 bge_poll(ifp, 0, 1);
2452 return;
2453 }
2454 #endif /* DEVICE_POLLING */
2455
2456 statusword =
2457 atomic_readandclear_32(&sc->bge_rdata->bge_status_block.bge_status);
2458
2459 #ifdef notdef
2460 /* Avoid this for now -- checking this register is expensive. */
2461 /* Make sure this is really our interrupt. */
2462 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2463 return;
2464 #endif
2465 /* Ack interrupt and stop others from occuring. */
2466 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2467
2468 /*
2469 * Process link state changes.
2470 * Grrr. The link status word in the status block does
2471 * not work correctly on the BCM5700 rev AX and BX chips,
2472 * according to all available information. Hence, we have
2473 * to enable MII interrupts in order to properly obtain
2474 * async link changes. Unfortunately, this also means that
2475 * we have to read the MAC status register to detect link
2476 * changes, thereby adding an additional register access to
2477 * the interrupt handler.
2478 */
2479
2480 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2481 status = CSR_READ_4(sc, BGE_MAC_STS);
2482 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2483 sc->bge_link = 0;
2484 untimeout(bge_tick, sc, sc->bge_stat_ch);
2485 bge_tick(sc);
2486 /* Clear the interrupt */
2487 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2488 BGE_EVTENB_MI_INTERRUPT);
2489 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2490 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2491 BRGPHY_INTRS);
2492 }
2493 } else {
2494 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) {
2495 /*
2496 * Sometimes PCS encoding errors are detected in
2497 * TBI mode (on fiber NICs), and for some reason
2498 * the chip will signal them as link changes.
2499 * If we get a link change event, but the 'PCS
2500 * encoding error' bit in the MAC status register
2501 * is set, don't bother doing a link check.
2502 * This avoids spurious "gigabit link up" messages
2503 * that sometimes appear on fiber NICs during
2504 * periods of heavy traffic. (There should be no
2505 * effect on copper NICs.)
2506 *
2507 * If we do have a copper NIC (bge_tbi == 0) then
2508 * check that the AUTOPOLL bit is set before
2509 * processing the event as a real link change.
2510 * Turning AUTOPOLL on and off in the MII read/write
2511 * functions will often trigger a link status
2512 * interrupt for no reason.
2513 */
2514 status = CSR_READ_4(sc, BGE_MAC_STS);
2515 mimode = CSR_READ_4(sc, BGE_MI_MODE);
2516 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR|
2517 BGE_MACSTAT_MI_COMPLETE)) && (!sc->bge_tbi &&
2518 (mimode & BGE_MIMODE_AUTOPOLL))) {
2519 sc->bge_link = 0;
2520 untimeout(bge_tick, sc, sc->bge_stat_ch);
2521 bge_tick(sc);
2522 }
2523 /* Clear the interrupt */
2524 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2525 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2526 BGE_MACSTAT_LINK_CHANGED);
2527
2528 /* Force flush the status block cached by PCI bridge */
2529 CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2530 }
2531 }
2532
2533 if (ifp->if_flags & IFF_RUNNING) {
2534 /* Check RX return ring producer/consumer */
2535 bge_rxeof(sc);
2536
2537 /* Check TX ring producer/consumer */
2538 bge_txeof(sc);
2539 }
2540
2541 bge_handle_events(sc);
2542
2543 /* Re-enable interrupts. */
2544 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2545
2546 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
2547 bge_start(ifp);
2548
2549 return;
2550 }
2551
2552 static void
2553 bge_tick(xsc)
2554 void *xsc;
2555 {
2556 struct bge_softc *sc;
2557 struct mii_data *mii = NULL;
2558 struct ifmedia *ifm = NULL;
2559 struct ifnet *ifp;
2560 int s;
2561
2562 sc = xsc;
2563 ifp = &sc->arpcom.ac_if;
2564
2565 s = splimp();
2566
2567 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2568 sc->bge_asicrev == BGE_ASICREV_BCM5750)
2569 bge_stats_update_regs(sc);
2570 else
2571 bge_stats_update(sc);
2572 sc->bge_stat_ch = timeout(bge_tick, sc, hz);
2573 if (sc->bge_link) {
2574 splx(s);
2575 return;
2576 }
2577
2578 if (sc->bge_tbi) {
2579 ifm = &sc->bge_ifmedia;
2580 if (CSR_READ_4(sc, BGE_MAC_STS) &
2581 BGE_MACSTAT_TBI_PCS_SYNCHED) {
2582 sc->bge_link++;
2583 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
2584 BGE_CLRBIT(sc, BGE_MAC_MODE,
2585 BGE_MACMODE_TBI_SEND_CFGS);
2586 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2587 printf("bge%d: gigabit link up\n", sc->bge_unit);
2588 if (ifp->if_snd.ifq_head != NULL)
2589 bge_start(ifp);
2590 }
2591 splx(s);
2592 return;
2593 }
2594
2595 mii = device_get_softc(sc->bge_miibus);
2596 mii_tick(mii);
2597
2598 if (!sc->bge_link) {
2599 mii_pollstat(mii);
2600 if (mii->mii_media_status & IFM_ACTIVE &&
2601 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2602 sc->bge_link++;
2603 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX ||
2604 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2605 printf("bge%d: gigabit link up\n",
2606 sc->bge_unit);
2607 if (ifp->if_snd.ifq_head != NULL)
2608 bge_start(ifp);
2609 }
2610 }
2611
2612 splx(s);
2613
2614 return;
2615 }
2616
2617 static void
2618 bge_stats_update_regs(sc)
2619 struct bge_softc *sc;
2620 {
2621 struct ifnet *ifp;
2622 struct bge_mac_stats_regs stats;
2623 u_int32_t *s;
2624 int i;
2625
2626 ifp = &sc->arpcom.ac_if;
2627
2628 s = (u_int32_t *)&stats;
2629 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2630 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2631 s++;
2632 }
2633
2634 ifp->if_collisions +=
2635 (stats.dot3StatsSingleCollisionFrames +
2636 stats.dot3StatsMultipleCollisionFrames +
2637 stats.dot3StatsExcessiveCollisions +
2638 stats.dot3StatsLateCollisions) -
2639 ifp->if_collisions;
2640
2641 return;
2642 }
2643
2644 static void
2645 bge_stats_update(sc)
2646 struct bge_softc *sc;
2647 {
2648 struct ifnet *ifp;
2649 struct bge_stats *stats;
2650
2651 ifp = &sc->arpcom.ac_if;
2652
2653 stats = (struct bge_stats *)(sc->bge_vhandle +
2654 BGE_MEMWIN_START + BGE_STATS_BLOCK);
2655
2656 ifp->if_collisions +=
2657 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
2658 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
2659 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
2660 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
2661 ifp->if_collisions;
2662
2663 #ifdef notdef
2664 ifp->if_collisions +=
2665 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2666 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2667 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2668 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2669 ifp->if_collisions;
2670 #endif
2671
2672 return;
2673 }
2674
2675 /*
2676 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2677 * pointers to descriptors.
2678 */
2679 static int
2680 bge_encap(sc, m_head, txidx)
2681 struct bge_softc *sc;
2682 struct mbuf *m_head;
2683 u_int32_t *txidx;
2684 {
2685 struct bge_tx_bd *f = NULL;
2686 struct mbuf *m;
2687 u_int32_t frag, cur, cnt = 0;
2688 u_int16_t csum_flags = 0;
2689 struct ifvlan *ifv = NULL;
2690
2691 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2692 m_head->m_pkthdr.rcvif != NULL &&
2693 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2694 ifv = m_head->m_pkthdr.rcvif->if_softc;
2695
2696 m = m_head;
2697 cur = frag = *txidx;
2698
2699 if (m_head->m_pkthdr.csum_flags) {
2700 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2701 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2702 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2703 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2704 if (m_head->m_flags & M_LASTFRAG)
2705 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2706 else if (m_head->m_flags & M_FRAG)
2707 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2708 }
2709 /*
2710 * Start packing the mbufs in this chain into
2711 * the fragment pointers. Stop when we run out
2712 * of fragments or hit the end of the mbuf chain.
2713 */
2714 for (m = m_head; m != NULL; m = m->m_next) {
2715 if (m->m_len != 0) {
2716 f = &sc->bge_rdata->bge_tx_ring[frag];
2717 if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2718 break;
2719 BGE_HOSTADDR(f->bge_addr,
2720 vtophys(mtod(m, vm_offset_t)));
2721 f->bge_len = m->m_len;
2722 f->bge_flags = csum_flags;
2723 if (ifv != NULL) {
2724 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2725 f->bge_vlan_tag = ifv->ifv_tag;
2726 } else {
2727 f->bge_vlan_tag = 0;
2728 }
2729 /*
2730 * Sanity check: avoid coming within 16 descriptors
2731 * of the end of the ring.
2732 */
2733 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2734 return(ENOBUFS);
2735 cur = frag;
2736 BGE_INC(frag, BGE_TX_RING_CNT);
2737 cnt++;
2738 }
2739 }
2740
2741 if (m != NULL)
2742 return(ENOBUFS);
2743
2744 if (frag == sc->bge_tx_saved_considx)
2745 return(ENOBUFS);
2746
2747 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2748 sc->bge_cdata.bge_tx_chain[cur] = m_head;
2749 sc->bge_txcnt += cnt;
2750
2751 *txidx = frag;
2752
2753 return(0);
2754 }
2755
2756 /*
2757 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2758 * to the mbuf data regions directly in the transmit descriptors.
2759 */
2760 static void
2761 bge_start(ifp)
2762 struct ifnet *ifp;
2763 {
2764 struct bge_softc *sc;
2765 struct mbuf *m_head = NULL;
2766 u_int32_t prodidx;
2767
2768 sc = ifp->if_softc;
2769
2770 if (!sc->bge_link && ifp->if_snd.ifq_len < 10)
2771 return;
2772
2773 prodidx = sc->bge_tx_prodidx;
2774
2775 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2776 IF_DEQUEUE(&ifp->if_snd, m_head);
2777 if (m_head == NULL)
2778 break;
2779
2780 /*
2781 * XXX
2782 * safety overkill. If this is a fragmented packet chain
2783 * with delayed TCP/UDP checksums, then only encapsulate
2784 * it if we have enough descriptors to handle the entire
2785 * chain at once.
2786 * (paranoia -- may not actually be needed)
2787 */
2788 if (m_head->m_flags & M_FIRSTFRAG &&
2789 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2790 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2791 m_head->m_pkthdr.csum_data + 16) {
2792 IF_PREPEND(&ifp->if_snd, m_head);
2793 ifp->if_flags |= IFF_OACTIVE;
2794 break;
2795 }
2796 }
2797
2798 /*
2799 * Pack the data into the transmit ring. If we
2800 * don't have room, set the OACTIVE flag and wait
2801 * for the NIC to drain the ring.
2802 */
2803 if (bge_encap(sc, m_head, &prodidx)) {
2804 IF_PREPEND(&ifp->if_snd, m_head);
2805 ifp->if_flags |= IFF_OACTIVE;
2806 break;
2807 }
2808
2809 /*
2810 * If there's a BPF listener, bounce a copy of this frame
2811 * to him.
2812 */
2813 if (ifp->if_bpf)
2814 bpf_mtap(ifp, m_head);
2815 }
2816
2817 /* Transmit */
2818 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2819 /* 5700 b2 errata */
2820 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2821 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2822 sc->bge_tx_prodidx = prodidx;
2823
2824 /*
2825 * Set a timeout in case the chip goes out to lunch.
2826 */
2827 ifp->if_timer = 5;
2828
2829 return;
2830 }
2831
2832 static void
2833 bge_init(xsc)
2834 void *xsc;
2835 {
2836 struct bge_softc *sc = xsc;
2837 struct ifnet *ifp;
2838 u_int16_t *m;
2839 int s;
2840
2841 s = splimp();
2842
2843 ifp = &sc->arpcom.ac_if;
2844
2845 if (ifp->if_flags & IFF_RUNNING) {
2846 splx(s);
2847 return;
2848 }
2849
2850 /* Cancel pending I/O and flush buffers. */
2851 bge_stop(sc);
2852 bge_reset(sc);
2853 bge_chipinit(sc);
2854
2855 /*
2856 * Init the various state machines, ring
2857 * control blocks and firmware.
2858 */
2859 if (bge_blockinit(sc)) {
2860 printf("bge%d: initialization failure\n", sc->bge_unit);
2861 splx(s);
2862 return;
2863 }
2864
2865 ifp = &sc->arpcom.ac_if;
2866
2867 /* Specify MTU. */
2868 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2869 ETHER_HDR_LEN + ETHER_CRC_LEN);
2870
2871 /* Load our MAC address. */
2872 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2873 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2874 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2875
2876 /* Enable or disable promiscuous mode as needed. */
2877 if (ifp->if_flags & IFF_PROMISC) {
2878 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2879 } else {
2880 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2881 }
2882
2883 /* Program multicast filter. */
2884 bge_setmulti(sc);
2885
2886 /* Init RX ring. */
2887 bge_init_rx_ring_std(sc);
2888
2889 /*
2890 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2891 * memory to insure that the chip has in fact read the first
2892 * entry of the ring.
2893 */
2894 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2895 u_int32_t v, i;
2896 for (i = 0; i < 10; i++) {
2897 DELAY(20);
2898 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2899 if (v == (MCLBYTES - ETHER_ALIGN))
2900 break;
2901 }
2902 if (i == 10)
2903 printf ("bge%d: 5705 A0 chip failed to load RX ring\n",
2904 sc->bge_unit);
2905 }
2906
2907 /* Init jumbo RX ring. */
2908 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2909 bge_init_rx_ring_jumbo(sc);
2910
2911 /* Init our RX return ring index */
2912 sc->bge_rx_saved_considx = 0;
2913
2914 /* Init TX ring. */
2915 bge_init_tx_ring(sc);
2916
2917 /* Turn on transmitter */
2918 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2919
2920 /* Turn on receiver */
2921 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2922
2923 /* Tell firmware we're alive. */
2924 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2925
2926 #ifdef DEVICE_POLLING
2927 /* Disable interrupts if we are polling. */
2928 if (ifp->if_ipending & IFF_POLLING) {
2929 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2930 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2931 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2932 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2933 } else
2934 #endif
2935 /* Enable host interrupts. */
2936 {
2937 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2938 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2939 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2940 }
2941
2942 bge_ifmedia_upd(ifp);
2943
2944 ifp->if_flags |= IFF_RUNNING;
2945 ifp->if_flags &= ~IFF_OACTIVE;
2946
2947 splx(s);
2948
2949 sc->bge_stat_ch = timeout(bge_tick, sc, hz);
2950
2951 return;
2952 }
2953
2954 /*
2955 * Set media options.
2956 */
2957 static int
2958 bge_ifmedia_upd(ifp)
2959 struct ifnet *ifp;
2960 {
2961 struct bge_softc *sc;
2962 struct mii_data *mii;
2963 struct ifmedia *ifm;
2964
2965 sc = ifp->if_softc;
2966 ifm = &sc->bge_ifmedia;
2967
2968 /* If this is a 1000baseX NIC, enable the TBI port. */
2969 if (sc->bge_tbi) {
2970 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2971 return(EINVAL);
2972 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2973 case IFM_AUTO:
2974 /*
2975 * The BCM5704 ASIC appears to have a special
2976 * mechanism for programming the autoneg
2977 * advertisement registers in TBI mode.
2978 */
2979 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2980 uint32_t sgdig;
2981 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2982 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2983 sgdig |= BGE_SGDIGCFG_AUTO|
2984 BGE_SGDIGCFG_PAUSE_CAP|
2985 BGE_SGDIGCFG_ASYM_PAUSE;
2986 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2987 sgdig|BGE_SGDIGCFG_SEND);
2988 DELAY(5);
2989 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2990 }
2991 break;
2992 case IFM_1000_SX:
2993 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2994 BGE_CLRBIT(sc, BGE_MAC_MODE,
2995 BGE_MACMODE_HALF_DUPLEX);
2996 } else {
2997 BGE_SETBIT(sc, BGE_MAC_MODE,
2998 BGE_MACMODE_HALF_DUPLEX);
2999 }
3000 break;
3001 default:
3002 return(EINVAL);
3003 }
3004 return(0);
3005 }
3006
3007 mii = device_get_softc(sc->bge_miibus);
3008 sc->bge_link = 0;
3009 if (mii->mii_instance) {
3010 struct mii_softc *miisc;
3011 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
3012 miisc = LIST_NEXT(miisc, mii_list))
3013 mii_phy_reset(miisc);
3014 }
3015 mii_mediachg(mii);
3016
3017 return(0);
3018 }
3019
3020 /*
3021 * Report current media status.
3022 */
3023 static void
3024 bge_ifmedia_sts(ifp, ifmr)
3025 struct ifnet *ifp;
3026 struct ifmediareq *ifmr;
3027 {
3028 struct bge_softc *sc;
3029 struct mii_data *mii;
3030
3031 sc = ifp->if_softc;
3032
3033 if (sc->bge_tbi) {
3034 ifmr->ifm_status = IFM_AVALID;
3035 ifmr->ifm_active = IFM_ETHER;
3036 if (CSR_READ_4(sc, BGE_MAC_STS) &
3037 BGE_MACSTAT_TBI_PCS_SYNCHED)
3038 ifmr->ifm_status |= IFM_ACTIVE;
3039 ifmr->ifm_active |= IFM_1000_SX;
3040 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3041 ifmr->ifm_active |= IFM_HDX;
3042 else
3043 ifmr->ifm_active |= IFM_FDX;
3044 return;
3045 }
3046
3047 mii = device_get_softc(sc->bge_miibus);
3048 mii_pollstat(mii);
3049 ifmr->ifm_active = mii->mii_media_active;
3050 ifmr->ifm_status = mii->mii_media_status;
3051
3052 return;
3053 }
3054
3055 static int
3056 bge_ioctl(ifp, command, data)
3057 struct ifnet *ifp;
3058 u_long command;
3059 caddr_t data;
3060 {
3061 struct bge_softc *sc = ifp->if_softc;
3062 struct ifreq *ifr = (struct ifreq *) data;
3063 int s, error = 0;
3064 struct mii_data *mii;
3065
3066 s = splimp();
3067
3068 switch(command) {
3069 case SIOCSIFADDR:
3070 case SIOCGIFADDR:
3071 error = ether_ioctl(ifp, command, data);
3072 break;
3073 case SIOCSIFMTU:
3074 /* Disallow jumbo frames on 5705. */
3075 if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
3076 sc->bge_asicrev == BGE_ASICREV_BCM5750) &&
3077 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
3078 error = EINVAL;
3079 else {
3080 ifp->if_mtu = ifr->ifr_mtu;
3081 ifp->if_flags &= ~IFF_RUNNING;
3082 bge_init(sc);
3083 }
3084 break;
3085 case SIOCSIFFLAGS:
3086 if (ifp->if_flags & IFF_UP) {
3087 /*
3088 * If only the state of the PROMISC flag changed,
3089 * then just use the 'set promisc mode' command
3090 * instead of reinitializing the entire NIC. Doing
3091 * a full re-init means reloading the firmware and
3092 * waiting for it to start up, which may take a
3093 * second or two. Similarly for ALLMULTI.
3094 */
3095 if (ifp->if_flags & IFF_RUNNING &&
3096 ifp->if_flags & IFF_PROMISC &&
3097 !(sc->bge_if_flags & IFF_PROMISC)) {
3098 BGE_SETBIT(sc, BGE_RX_MODE,
3099 BGE_RXMODE_RX_PROMISC);
3100 } else if (ifp->if_flags & IFF_RUNNING &&
3101 !(ifp->if_flags & IFF_PROMISC) &&
3102 sc->bge_if_flags & IFF_PROMISC) {
3103 BGE_CLRBIT(sc, BGE_RX_MODE,
3104 BGE_RXMODE_RX_PROMISC);
3105 } else if (ifp->if_flags & IFF_RUNNING &&
3106 (ifp->if_flags ^ sc->bge_if_flags) & IFF_ALLMULTI) {
3107 bge_setmulti(sc);
3108 } else
3109 bge_init(sc);
3110 } else {
3111 if (ifp->if_flags & IFF_RUNNING) {
3112 bge_stop(sc);
3113 }
3114 }
3115 sc->bge_if_flags = ifp->if_flags;
3116 error = 0;
3117 break;
3118 case SIOCADDMULTI:
3119 case SIOCDELMULTI:
3120 if (ifp->if_flags & IFF_RUNNING) {
3121 bge_setmulti(sc);
3122 error = 0;
3123 }
3124 break;
3125 case SIOCSIFMEDIA:
3126 case SIOCGIFMEDIA:
3127 if (sc->bge_tbi) {
3128 error = ifmedia_ioctl(ifp, ifr,
3129 &sc->bge_ifmedia, command);
3130 } else {
3131 mii = device_get_softc(sc->bge_miibus);
3132 error = ifmedia_ioctl(ifp, ifr,
3133 &mii->mii_media, command);
3134 }
3135 break;
3136 case SIOCSIFCAP:
3137 ifp->if_capenable = ifr->ifr_reqcap;
3138 break;
3139 default:
3140 error = EINVAL;
3141 break;
3142 }
3143
3144 (void)splx(s);
3145
3146 return(error);
3147 }
3148
3149 static void
3150 bge_watchdog(ifp)
3151 struct ifnet *ifp;
3152 {
3153 struct bge_softc *sc;
3154
3155 sc = ifp->if_softc;
3156
3157 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit);
3158
3159 ifp->if_flags &= ~IFF_RUNNING;
3160 bge_init(sc);
3161
3162 ifp->if_oerrors++;
3163
3164 return;
3165 }
3166
3167 /*
3168 * Stop the adapter and free any mbufs allocated to the
3169 * RX and TX lists.
3170 */
3171 static void
3172 bge_stop(sc)
3173 struct bge_softc *sc;
3174 {
3175 struct ifnet *ifp;
3176 struct ifmedia_entry *ifm;
3177 struct mii_data *mii = NULL;
3178 int mtmp, itmp;
3179
3180 ifp = &sc->arpcom.ac_if;
3181
3182 if (!sc->bge_tbi)
3183 mii = device_get_softc(sc->bge_miibus);
3184
3185 untimeout(bge_tick, sc, sc->bge_stat_ch);
3186 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3187 #ifdef DEVICE_POLLING
3188 ether_poll_deregister(ifp);
3189 #endif /* DEVICE_POLLING */
3190
3191 /*
3192 * Disable all of the receiver blocks
3193 */
3194 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3195 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3196 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3197 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
3198 sc->bge_asicrev != BGE_ASICREV_BCM5750)
3199 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3200 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3201 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3202 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3203
3204 /*
3205 * Disable all of the transmit blocks
3206 */
3207 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3208 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3209 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3210 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3211 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3212 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
3213 sc->bge_asicrev != BGE_ASICREV_BCM5750)
3214 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3215 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3216
3217 /*
3218 * Shut down all of the memory managers and related
3219 * state machines.
3220 */
3221 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3222 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3223 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
3224 sc->bge_asicrev != BGE_ASICREV_BCM5750)
3225 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3226 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3227 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3228 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
3229 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
3230 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3231 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3232 }
3233
3234 /* Disable host interrupts. */
3235 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3236 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3237
3238 /*
3239 * Tell firmware we're shutting down.
3240 */
3241 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3242
3243 /* Free the RX lists. */
3244 bge_free_rx_ring_std(sc);
3245
3246 /* Free jumbo RX list. */
3247 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
3248 sc->bge_asicrev != BGE_ASICREV_BCM5750)
3249 bge_free_rx_ring_jumbo(sc);
3250
3251 /* Free TX buffers. */
3252 bge_free_tx_ring(sc);
3253
3254 /*
3255 * Isolate/power down the PHY, but leave the media selection
3256 * unchanged so that things will be put back to normal when
3257 * we bring the interface back up.
3258 */
3259 if (!sc->bge_tbi) {
3260 itmp = ifp->if_flags;
3261 ifp->if_flags |= IFF_UP;
3262 ifm = mii->mii_media.ifm_cur;
3263 mtmp = ifm->ifm_media;
3264 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3265 mii_mediachg(mii);
3266 ifm->ifm_media = mtmp;
3267 ifp->if_flags = itmp;
3268 }
3269
3270 sc->bge_link = 0;
3271
3272 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3273
3274 return;
3275 }
3276
3277 /*
3278 * Stop all chip I/O so that the kernel's probe routines don't
3279 * get confused by errant DMAs when rebooting.
3280 */
3281 static void
3282 bge_shutdown(dev)
3283 device_t dev;
3284 {
3285 struct bge_softc *sc;
3286
3287 sc = device_get_softc(dev);
3288
3289 bge_stop(sc);
3290 bge_reset(sc);
3291
3292 return;
3293 }
Cache object: d1e325b1c6bbd0cff9fa662f940908af
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