FreeBSD/Linux Kernel Cross Reference
sys/dev/bge/if_bge.c
1 /*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: src/sys/dev/bge/if_bge.c,v 1.91.2.23 2007/05/08 16:18:21 jkim Exp $");
36
37 /*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45 * frames, highly configurable RX filtering, and 16 RX and TX queues
46 * (which, along with RX filter rules, can be used for QOS applications).
47 * Other features, such as TCP segmentation, may be available as part
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49 * firmware images can be stored in hardware and need not be compiled
50 * into the driver.
51 *
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
54 *
55 * The BCM5701 is a single-chip solution incorporating both the BCM5700
56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57 * does not support external SSRAM.
58 *
59 * Broadcom also produces a variation of the BCM5700 under the "Altima"
60 * brand name, which is functionally similar but lacks PCI-X support.
61 *
62 * Without external SSRAM, you can only have at most 4 TX rings,
63 * and the use of the mini RX ring is disabled. This seems to imply
64 * that these features are simply not available on the BCM5701. As a
65 * result, this driver does not implement any support for the mini RX
66 * ring.
67 */
68
69 #ifdef HAVE_KERNEL_OPTION_HEADERS
70 #include "opt_device_polling.h"
71 #endif
72
73 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
77 #include <sys/mbuf.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
82 #include <sys/sysctl.h>
83
84 #include <net/if.h>
85 #include <net/if_arp.h>
86 #include <net/ethernet.h>
87 #include <net/if_dl.h>
88 #include <net/if_media.h>
89
90 #include <net/bpf.h>
91
92 #include <net/if_types.h>
93 #include <net/if_vlan_var.h>
94
95 #include <netinet/in_systm.h>
96 #include <netinet/in.h>
97 #include <netinet/ip.h>
98
99 #include <machine/bus.h>
100 #include <machine/resource.h>
101 #include <sys/bus.h>
102 #include <sys/rman.h>
103
104 #include <dev/mii/mii.h>
105 #include <dev/mii/miivar.h>
106 #include "miidevs.h"
107 #include <dev/mii/brgphyreg.h>
108
109 #include <dev/pci/pcireg.h>
110 #include <dev/pci/pcivar.h>
111
112 #include <dev/bge/if_bgereg.h>
113
114 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
115 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
116
117 MODULE_DEPEND(bge, pci, 1, 1, 1);
118 MODULE_DEPEND(bge, ether, 1, 1, 1);
119 MODULE_DEPEND(bge, miibus, 1, 1, 1);
120
121 /* "device miibus" required. See GENERIC if you get errors here. */
122 #include "miibus_if.h"
123
124 /*
125 * Various supported device vendors/types and their names. Note: the
126 * spec seems to indicate that the hardware still has Alteon's vendor
127 * ID burned into it, though it will always be overriden by the vendor
128 * ID in the EEPROM. Just to be safe, we cover all possibilities.
129 */
130 static struct bge_type {
131 uint16_t bge_vid;
132 uint16_t bge_did;
133 } bge_devs[] = {
134 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
135 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
136
137 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
138 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
139 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
140
141 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
142
143 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
144 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
145 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
146 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
147 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
148 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
149 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
191
192 { SK_VENDORID, SK_DEVICEID_ALTIMA },
193
194 { TC_VENDORID, TC_DEVICEID_3C996 },
195
196 { 0, 0 }
197 };
198
199 static const struct bge_vendor {
200 uint16_t v_id;
201 const char *v_name;
202 } bge_vendors[] = {
203 { ALTEON_VENDORID, "Alteon" },
204 { ALTIMA_VENDORID, "Altima" },
205 { APPLE_VENDORID, "Apple" },
206 { BCOM_VENDORID, "Broadcom" },
207 { SK_VENDORID, "SysKonnect" },
208 { TC_VENDORID, "3Com" },
209
210 { 0, NULL }
211 };
212
213 static const struct bge_revision {
214 uint32_t br_chipid;
215 const char *br_name;
216 } bge_revisions[] = {
217 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
218 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
219 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
220 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
221 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
222 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
223 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
224 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
225 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
226 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
227 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
228 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
229 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
230 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
231 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
232 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
233 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
234 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
235 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
236 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
237 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
238 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
239 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
240 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
241 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
242 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
243 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
244 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
245 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
246 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
247 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
248 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
249 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
250 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
251 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
252 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
253 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
254 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
255 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
256 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
257 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
258 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
259 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
260 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
261 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
262 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
263 /* 5754 and 5787 share the same ASIC ID */
264 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
265 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
266 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
267
268 { 0, NULL }
269 };
270
271 /*
272 * Some defaults for major revisions, so that newer steppings
273 * that we don't know about have a shot at working.
274 */
275 static const struct bge_revision bge_majorrevs[] = {
276 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
277 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
278 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
279 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
280 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
281 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
282 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
283 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
284 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
285 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
286 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
287 /* 5754 and 5787 share the same ASIC ID */
288 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
289
290 { 0, NULL }
291 };
292
293 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
294 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
295 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
296 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
297 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
298
299 const struct bge_revision * bge_lookup_rev(uint32_t);
300 const struct bge_vendor * bge_lookup_vendor(uint16_t);
301 static int bge_probe(device_t);
302 static int bge_attach(device_t);
303 static int bge_detach(device_t);
304 static int bge_suspend(device_t);
305 static int bge_resume(device_t);
306 static void bge_release_resources(struct bge_softc *);
307 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
308 static int bge_dma_alloc(device_t);
309 static void bge_dma_free(struct bge_softc *);
310
311 static void bge_txeof(struct bge_softc *);
312 static void bge_rxeof(struct bge_softc *);
313
314 static void bge_asf_driver_up (struct bge_softc *);
315 static void bge_tick(void *);
316 static void bge_stats_update(struct bge_softc *);
317 static void bge_stats_update_regs(struct bge_softc *);
318 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
319
320 static void bge_intr(void *);
321 static void bge_start_locked(struct ifnet *);
322 static void bge_start(struct ifnet *);
323 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
324 static void bge_init_locked(struct bge_softc *);
325 static void bge_init(void *);
326 static void bge_stop(struct bge_softc *);
327 static void bge_watchdog(struct bge_softc *);
328 static void bge_shutdown(device_t);
329 static int bge_ifmedia_upd_locked(struct ifnet *);
330 static int bge_ifmedia_upd(struct ifnet *);
331 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
332
333 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
334 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
335
336 static void bge_setpromisc(struct bge_softc *);
337 static void bge_setmulti(struct bge_softc *);
338
339 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
340 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
341 static int bge_init_rx_ring_std(struct bge_softc *);
342 static void bge_free_rx_ring_std(struct bge_softc *);
343 static int bge_init_rx_ring_jumbo(struct bge_softc *);
344 static void bge_free_rx_ring_jumbo(struct bge_softc *);
345 static void bge_free_tx_ring(struct bge_softc *);
346 static int bge_init_tx_ring(struct bge_softc *);
347
348 static int bge_chipinit(struct bge_softc *);
349 static int bge_blockinit(struct bge_softc *);
350
351 static uint32_t bge_readmem_ind(struct bge_softc *, int);
352 static void bge_writemem_ind(struct bge_softc *, int, int);
353 #ifdef notdef
354 static uint32_t bge_readreg_ind(struct bge_softc *, int);
355 #endif
356 static void bge_writemem_direct(struct bge_softc *, int, int);
357 static void bge_writereg_ind(struct bge_softc *, int, int);
358
359 static int bge_miibus_readreg(device_t, int, int);
360 static int bge_miibus_writereg(device_t, int, int, int);
361 static void bge_miibus_statchg(device_t);
362 #ifdef DEVICE_POLLING
363 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
364 #endif
365
366 #define BGE_RESET_START 1
367 #define BGE_RESET_STOP 2
368 static void bge_sig_post_reset(struct bge_softc *, int);
369 static void bge_sig_legacy(struct bge_softc *, int);
370 static void bge_sig_pre_reset(struct bge_softc *, int);
371 static int bge_reset(struct bge_softc *);
372 static void bge_link_upd(struct bge_softc *);
373
374 /*
375 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
376 * leak information to untrusted users. It is also known to cause alignment
377 * traps on certain architectures.
378 */
379 #ifdef BGE_REGISTER_DEBUG
380 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
381 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
382 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
383 #endif
384 static void bge_add_sysctls(struct bge_softc *);
385
386 static device_method_t bge_methods[] = {
387 /* Device interface */
388 DEVMETHOD(device_probe, bge_probe),
389 DEVMETHOD(device_attach, bge_attach),
390 DEVMETHOD(device_detach, bge_detach),
391 DEVMETHOD(device_shutdown, bge_shutdown),
392 DEVMETHOD(device_suspend, bge_suspend),
393 DEVMETHOD(device_resume, bge_resume),
394
395 /* bus interface */
396 DEVMETHOD(bus_print_child, bus_generic_print_child),
397 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
398
399 /* MII interface */
400 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
401 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
402 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
403
404 { 0, 0 }
405 };
406
407 static driver_t bge_driver = {
408 "bge",
409 bge_methods,
410 sizeof(struct bge_softc)
411 };
412
413 static devclass_t bge_devclass;
414
415 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
416 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
417
418 static int bge_fake_autoneg = 0;
419 static int bge_allow_asf = 0;
420
421 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
422 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
423
424 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
425 SYSCTL_INT(_hw_bge, OID_AUTO, fake_autoneg, CTLFLAG_RD, &bge_fake_autoneg, 0,
426 "Enable fake autonegotiation for certain blade systems");
427 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
428 "Allow ASF mode if available");
429
430 static uint32_t
431 bge_readmem_ind(struct bge_softc *sc, int off)
432 {
433 device_t dev;
434 uint32_t val;
435
436 dev = sc->bge_dev;
437
438 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
439 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
440 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
441 return (val);
442 }
443
444 static void
445 bge_writemem_ind(struct bge_softc *sc, int off, int val)
446 {
447 device_t dev;
448
449 dev = sc->bge_dev;
450
451 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
452 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
453 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
454 }
455
456 #ifdef notdef
457 static uint32_t
458 bge_readreg_ind(struct bge_softc *sc, int off)
459 {
460 device_t dev;
461
462 dev = sc->bge_dev;
463
464 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
465 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
466 }
467 #endif
468
469 static void
470 bge_writereg_ind(struct bge_softc *sc, int off, int val)
471 {
472 device_t dev;
473
474 dev = sc->bge_dev;
475
476 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
477 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
478 }
479
480 static void
481 bge_writemem_direct(struct bge_softc *sc, int off, int val)
482 {
483 CSR_WRITE_4(sc, off, val);
484 }
485
486 /*
487 * Map a single buffer address.
488 */
489
490 static void
491 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
492 {
493 struct bge_dmamap_arg *ctx;
494
495 if (error)
496 return;
497
498 ctx = arg;
499
500 if (nseg > ctx->bge_maxsegs) {
501 ctx->bge_maxsegs = 0;
502 return;
503 }
504
505 ctx->bge_busaddr = segs->ds_addr;
506 }
507
508 /*
509 * Read a byte of data stored in the EEPROM at address 'addr.' The
510 * BCM570x supports both the traditional bitbang interface and an
511 * auto access interface for reading the EEPROM. We use the auto
512 * access method.
513 */
514 static uint8_t
515 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
516 {
517 int i;
518 uint32_t byte = 0;
519
520 /*
521 * Enable use of auto EEPROM access so we can avoid
522 * having to use the bitbang method.
523 */
524 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
525
526 /* Reset the EEPROM, load the clock period. */
527 CSR_WRITE_4(sc, BGE_EE_ADDR,
528 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
529 DELAY(20);
530
531 /* Issue the read EEPROM command. */
532 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
533
534 /* Wait for completion */
535 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
536 DELAY(10);
537 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
538 break;
539 }
540
541 if (i == BGE_TIMEOUT) {
542 device_printf(sc->bge_dev, "EEPROM read timed out\n");
543 return (1);
544 }
545
546 /* Get result. */
547 byte = CSR_READ_4(sc, BGE_EE_DATA);
548
549 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
550
551 return (0);
552 }
553
554 /*
555 * Read a sequence of bytes from the EEPROM.
556 */
557 static int
558 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
559 {
560 int i, error = 0;
561 uint8_t byte = 0;
562
563 for (i = 0; i < cnt; i++) {
564 error = bge_eeprom_getbyte(sc, off + i, &byte);
565 if (error)
566 break;
567 *(dest + i) = byte;
568 }
569
570 return (error ? 1 : 0);
571 }
572
573 static int
574 bge_miibus_readreg(device_t dev, int phy, int reg)
575 {
576 struct bge_softc *sc;
577 uint32_t val, autopoll;
578 int i;
579
580 sc = device_get_softc(dev);
581
582 /*
583 * Broadcom's own driver always assumes the internal
584 * PHY is at GMII address 1. On some chips, the PHY responds
585 * to accesses at all addresses, which could cause us to
586 * bogusly attach the PHY 32 times at probe type. Always
587 * restricting the lookup to address 1 is simpler than
588 * trying to figure out which chips revisions should be
589 * special-cased.
590 */
591 if (phy != 1)
592 return (0);
593
594 /* Reading with autopolling on may trigger PCI errors */
595 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
596 if (autopoll & BGE_MIMODE_AUTOPOLL) {
597 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
598 DELAY(40);
599 }
600
601 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
602 BGE_MIPHY(phy) | BGE_MIREG(reg));
603
604 for (i = 0; i < BGE_TIMEOUT; i++) {
605 val = CSR_READ_4(sc, BGE_MI_COMM);
606 if (!(val & BGE_MICOMM_BUSY))
607 break;
608 }
609
610 if (i == BGE_TIMEOUT) {
611 device_printf(sc->bge_dev, "PHY read timed out\n");
612 val = 0;
613 goto done;
614 }
615
616 val = CSR_READ_4(sc, BGE_MI_COMM);
617
618 done:
619 if (autopoll & BGE_MIMODE_AUTOPOLL) {
620 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
621 DELAY(40);
622 }
623
624 if (val & BGE_MICOMM_READFAIL)
625 return (0);
626
627 return (val & 0xFFFF);
628 }
629
630 static int
631 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
632 {
633 struct bge_softc *sc;
634 uint32_t autopoll;
635 int i;
636
637 sc = device_get_softc(dev);
638
639 /* Reading with autopolling on may trigger PCI errors */
640 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
641 if (autopoll & BGE_MIMODE_AUTOPOLL) {
642 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
643 DELAY(40);
644 }
645
646 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
647 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
648
649 for (i = 0; i < BGE_TIMEOUT; i++) {
650 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
651 break;
652 }
653
654 if (autopoll & BGE_MIMODE_AUTOPOLL) {
655 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
656 DELAY(40);
657 }
658
659 if (i == BGE_TIMEOUT) {
660 device_printf(sc->bge_dev, "PHY read timed out\n");
661 return (0);
662 }
663
664 return (0);
665 }
666
667 static void
668 bge_miibus_statchg(device_t dev)
669 {
670 struct bge_softc *sc;
671 struct mii_data *mii;
672 sc = device_get_softc(dev);
673 mii = device_get_softc(sc->bge_miibus);
674
675 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
676 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
677 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
678 else
679 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
680
681 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
682 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
683 else
684 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
685 }
686
687 /*
688 * Intialize a standard receive ring descriptor.
689 */
690 static int
691 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
692 {
693 struct mbuf *m_new = NULL;
694 struct bge_rx_bd *r;
695 struct bge_dmamap_arg ctx;
696 int error;
697
698 if (m == NULL) {
699 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
700 if (m_new == NULL)
701 return (ENOBUFS);
702 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
703 } else {
704 m_new = m;
705 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
706 m_new->m_data = m_new->m_ext.ext_buf;
707 }
708
709 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
710 m_adj(m_new, ETHER_ALIGN);
711 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
712 r = &sc->bge_ldata.bge_rx_std_ring[i];
713 ctx.bge_maxsegs = 1;
714 ctx.sc = sc;
715 error = bus_dmamap_load(sc->bge_cdata.bge_mtag,
716 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *),
717 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
718 if (error || ctx.bge_maxsegs == 0) {
719 if (m == NULL) {
720 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
721 m_freem(m_new);
722 }
723 return (ENOMEM);
724 }
725 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr);
726 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr);
727 r->bge_flags = BGE_RXBDFLAG_END;
728 r->bge_len = m_new->m_len;
729 r->bge_idx = i;
730
731 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
732 sc->bge_cdata.bge_rx_std_dmamap[i],
733 BUS_DMASYNC_PREREAD);
734
735 return (0);
736 }
737
738 /*
739 * Initialize a jumbo receive ring descriptor. This allocates
740 * a jumbo buffer from the pool managed internally by the driver.
741 */
742 static int
743 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
744 {
745 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
746 struct bge_extrx_bd *r;
747 struct mbuf *m_new = NULL;
748 int nsegs;
749 int error;
750
751 if (m == NULL) {
752 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
753 if (m_new == NULL)
754 return (ENOBUFS);
755
756 m_cljget(m_new, M_DONTWAIT, MJUM9BYTES);
757 if (!(m_new->m_flags & M_EXT)) {
758 m_freem(m_new);
759 return (ENOBUFS);
760 }
761 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES;
762 } else {
763 m_new = m;
764 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES;
765 m_new->m_data = m_new->m_ext.ext_buf;
766 }
767
768 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
769 m_adj(m_new, ETHER_ALIGN);
770
771 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
772 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
773 m_new, segs, &nsegs, BUS_DMA_NOWAIT);
774 if (error) {
775 if (m == NULL)
776 m_freem(m_new);
777 return (error);
778 }
779 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
780
781 /*
782 * Fill in the extended RX buffer descriptor.
783 */
784 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
785 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
786 r->bge_idx = i;
787 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
788 switch (nsegs) {
789 case 4:
790 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
791 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
792 r->bge_len3 = segs[3].ds_len;
793 case 3:
794 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
795 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
796 r->bge_len2 = segs[2].ds_len;
797 case 2:
798 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
799 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
800 r->bge_len1 = segs[1].ds_len;
801 case 1:
802 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
803 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
804 r->bge_len0 = segs[0].ds_len;
805 break;
806 default:
807 panic("%s: %d segments\n", __func__, nsegs);
808 }
809
810 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
811 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
812 BUS_DMASYNC_PREREAD);
813
814 return (0);
815 }
816
817 /*
818 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
819 * that's 1MB or memory, which is a lot. For now, we fill only the first
820 * 256 ring entries and hope that our CPU is fast enough to keep up with
821 * the NIC.
822 */
823 static int
824 bge_init_rx_ring_std(struct bge_softc *sc)
825 {
826 int i;
827
828 for (i = 0; i < BGE_SSLOTS; i++) {
829 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
830 return (ENOBUFS);
831 };
832
833 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
834 sc->bge_cdata.bge_rx_std_ring_map,
835 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
836
837 sc->bge_std = i - 1;
838 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
839
840 return (0);
841 }
842
843 static void
844 bge_free_rx_ring_std(struct bge_softc *sc)
845 {
846 int i;
847
848 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
849 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
850 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
851 sc->bge_cdata.bge_rx_std_dmamap[i],
852 BUS_DMASYNC_POSTREAD);
853 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
854 sc->bge_cdata.bge_rx_std_dmamap[i]);
855 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
856 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
857 }
858 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
859 sizeof(struct bge_rx_bd));
860 }
861 }
862
863 static int
864 bge_init_rx_ring_jumbo(struct bge_softc *sc)
865 {
866 struct bge_rcb *rcb;
867 int i;
868
869 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
870 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
871 return (ENOBUFS);
872 };
873
874 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
875 sc->bge_cdata.bge_rx_jumbo_ring_map,
876 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
877
878 sc->bge_jumbo = i - 1;
879
880 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
881 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
882 BGE_RCB_FLAG_USE_EXT_RX_BD);
883 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
884
885 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
886
887 return (0);
888 }
889
890 static void
891 bge_free_rx_ring_jumbo(struct bge_softc *sc)
892 {
893 int i;
894
895 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
896 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
897 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
898 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
899 BUS_DMASYNC_POSTREAD);
900 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
901 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
902 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
903 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
904 }
905 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
906 sizeof(struct bge_extrx_bd));
907 }
908 }
909
910 static void
911 bge_free_tx_ring(struct bge_softc *sc)
912 {
913 int i;
914
915 if (sc->bge_ldata.bge_tx_ring == NULL)
916 return;
917
918 for (i = 0; i < BGE_TX_RING_CNT; i++) {
919 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
920 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
921 sc->bge_cdata.bge_tx_dmamap[i],
922 BUS_DMASYNC_POSTWRITE);
923 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
924 sc->bge_cdata.bge_tx_dmamap[i]);
925 m_freem(sc->bge_cdata.bge_tx_chain[i]);
926 sc->bge_cdata.bge_tx_chain[i] = NULL;
927 }
928 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
929 sizeof(struct bge_tx_bd));
930 }
931 }
932
933 static int
934 bge_init_tx_ring(struct bge_softc *sc)
935 {
936 sc->bge_txcnt = 0;
937 sc->bge_tx_saved_considx = 0;
938
939 /* Initialize transmit producer index for host-memory send ring. */
940 sc->bge_tx_prodidx = 0;
941 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
942
943 /* 5700 b2 errata */
944 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
945 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
946
947 /* NIC-memory send ring not used; initialize to zero. */
948 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
949 /* 5700 b2 errata */
950 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
951 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
952
953 return (0);
954 }
955
956 static void
957 bge_setpromisc(struct bge_softc *sc)
958 {
959 struct ifnet *ifp;
960
961 BGE_LOCK_ASSERT(sc);
962
963 ifp = sc->bge_ifp;
964
965 /* Enable or disable promiscuous mode as needed. */
966 if (ifp->if_flags & IFF_PROMISC)
967 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
968 else
969 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
970 }
971
972 static void
973 bge_setmulti(struct bge_softc *sc)
974 {
975 struct ifnet *ifp;
976 struct ifmultiaddr *ifma;
977 uint32_t hashes[4] = { 0, 0, 0, 0 };
978 int h, i;
979
980 BGE_LOCK_ASSERT(sc);
981
982 ifp = sc->bge_ifp;
983
984 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
985 for (i = 0; i < 4; i++)
986 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
987 return;
988 }
989
990 /* First, zot all the existing filters. */
991 for (i = 0; i < 4; i++)
992 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
993
994 /* Now program new ones. */
995 IF_ADDR_LOCK(ifp);
996 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
997 if (ifma->ifma_addr->sa_family != AF_LINK)
998 continue;
999 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1000 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1001 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1002 }
1003 IF_ADDR_UNLOCK(ifp);
1004
1005 for (i = 0; i < 4; i++)
1006 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1007 }
1008
1009 static void
1010 bge_sig_pre_reset(sc, type)
1011 struct bge_softc *sc;
1012 int type;
1013 {
1014 /*
1015 * Some chips don't like this so only do this if ASF is enabled
1016 */
1017 if (sc->bge_asf_mode)
1018 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1019
1020 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1021 switch (type) {
1022 case BGE_RESET_START:
1023 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1024 break;
1025 case BGE_RESET_STOP:
1026 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1027 break;
1028 }
1029 }
1030 }
1031
1032 static void
1033 bge_sig_post_reset(sc, type)
1034 struct bge_softc *sc;
1035 int type;
1036 {
1037 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1038 switch (type) {
1039 case BGE_RESET_START:
1040 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1041 /* START DONE */
1042 break;
1043 case BGE_RESET_STOP:
1044 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1045 break;
1046 }
1047 }
1048 }
1049
1050 static void
1051 bge_sig_legacy(sc, type)
1052 struct bge_softc *sc;
1053 int type;
1054 {
1055 if (sc->bge_asf_mode) {
1056 switch (type) {
1057 case BGE_RESET_START:
1058 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1059 break;
1060 case BGE_RESET_STOP:
1061 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1062 break;
1063 }
1064 }
1065 }
1066
1067 void bge_stop_fw(struct bge_softc *);
1068 void
1069 bge_stop_fw(sc)
1070 struct bge_softc *sc;
1071 {
1072 int i;
1073
1074 if (sc->bge_asf_mode) {
1075 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1076 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1077 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1078
1079 for (i = 0; i < 100; i++ ) {
1080 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1081 break;
1082 DELAY(10);
1083 }
1084 }
1085 }
1086
1087 /*
1088 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1089 * self-test results.
1090 */
1091 static int
1092 bge_chipinit(struct bge_softc *sc)
1093 {
1094 uint32_t dma_rw_ctl;
1095 int i;
1096
1097 /* Set endianness before we access any non-PCI registers. */
1098 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1099
1100 /*
1101 * Check the 'ROM failed' bit on the RX CPU to see if
1102 * self-tests passed.
1103 */
1104 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1105 device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n");
1106 return (ENODEV);
1107 }
1108
1109 /* Clear the MAC control register */
1110 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1111
1112 /*
1113 * Clear the MAC statistics block in the NIC's
1114 * internal memory.
1115 */
1116 for (i = BGE_STATS_BLOCK;
1117 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1118 BGE_MEMWIN_WRITE(sc, i, 0);
1119
1120 for (i = BGE_STATUS_BLOCK;
1121 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1122 BGE_MEMWIN_WRITE(sc, i, 0);
1123
1124 /* Set up the PCI DMA control register. */
1125 if (sc->bge_flags & BGE_FLAG_PCIE) {
1126 /* PCI Express bus */
1127 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1128 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0xF) |
1129 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x2);
1130 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1131 /* PCI-X bus */
1132 if (BGE_IS_5714_FAMILY(sc)) {
1133 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
1134 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1135 /* XXX magic values, Broadcom-supplied Linux driver */
1136 dma_rw_ctl |= (1 << 20) | (1 << 18);
1137 if (sc->bge_asicrev == BGE_ASICREV_BCM5780)
1138 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1139 else
1140 dma_rw_ctl |= 1 << 15;
1141
1142 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1143 /*
1144 * The 5704 uses a different encoding of read/write
1145 * watermarks.
1146 */
1147 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1148 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) |
1149 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3);
1150 else
1151 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1152 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x3) |
1153 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3) |
1154 0x0F;
1155
1156 /*
1157 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1158 * for hardware bugs.
1159 */
1160 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1161 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1162 uint32_t tmp;
1163
1164 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1165 if (tmp == 0x6 || tmp == 0x7)
1166 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1167 }
1168 } else
1169 /* Conventional PCI bus */
1170 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1171 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) |
1172 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x7) |
1173 0x0F;
1174
1175 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1176 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1177 sc->bge_asicrev == BGE_ASICREV_BCM5705)
1178 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1179 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1180
1181 /*
1182 * Set up general mode register.
1183 */
1184 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1185 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1186 BGE_MODECTL_TX_NO_PHDR_CSUM);
1187
1188 /*
1189 * Tell the firmware the driver is running
1190 */
1191 if (sc->bge_asf_mode & ASF_STACKUP)
1192 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1193
1194 /*
1195 * Disable memory write invalidate. Apparently it is not supported
1196 * properly by these devices.
1197 */
1198 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1199
1200 #ifdef __brokenalpha__
1201 /*
1202 * Must insure that we do not cross an 8K (bytes) boundary
1203 * for DMA reads. Our highest limit is 1K bytes. This is a
1204 * restriction on some ALPHA platforms with early revision
1205 * 21174 PCI chipsets, such as the AlphaPC 164lx
1206 */
1207 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1208 BGE_PCI_READ_BNDRY_1024BYTES, 4);
1209 #endif
1210
1211 /* Set the timer prescaler (always 66Mhz) */
1212 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1213
1214 return (0);
1215 }
1216
1217 static int
1218 bge_blockinit(struct bge_softc *sc)
1219 {
1220 struct bge_rcb *rcb;
1221 bus_size_t vrcb;
1222 bge_hostaddr taddr;
1223 uint32_t val;
1224 int i;
1225
1226 /*
1227 * Initialize the memory window pointer register so that
1228 * we can access the first 32K of internal NIC RAM. This will
1229 * allow us to set up the TX send ring RCBs and the RX return
1230 * ring RCBs, plus other things which live in NIC memory.
1231 */
1232 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1233
1234 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1235
1236 if (!(BGE_IS_5705_PLUS(sc))) {
1237 /* Configure mbuf memory pool */
1238 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1239 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1240 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1241 else
1242 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1243
1244 /* Configure DMA resource pool */
1245 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1246 BGE_DMA_DESCRIPTORS);
1247 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1248 }
1249
1250 /* Configure mbuf pool watermarks */
1251 if (!(BGE_IS_5705_PLUS(sc))) {
1252 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1253 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1254 } else {
1255 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1256 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1257 }
1258 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1259
1260 /* Configure DMA resource watermarks */
1261 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1262 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1263
1264 /* Enable buffer manager */
1265 if (!(BGE_IS_5705_PLUS(sc))) {
1266 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1267 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1268
1269 /* Poll for buffer manager start indication */
1270 for (i = 0; i < BGE_TIMEOUT; i++) {
1271 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1272 break;
1273 DELAY(10);
1274 }
1275
1276 if (i == BGE_TIMEOUT) {
1277 device_printf(sc->bge_dev,
1278 "buffer manager failed to start\n");
1279 return (ENXIO);
1280 }
1281 }
1282
1283 /* Enable flow-through queues */
1284 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1285 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1286
1287 /* Wait until queue initialization is complete */
1288 for (i = 0; i < BGE_TIMEOUT; i++) {
1289 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1290 break;
1291 DELAY(10);
1292 }
1293
1294 if (i == BGE_TIMEOUT) {
1295 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1296 return (ENXIO);
1297 }
1298
1299 /* Initialize the standard RX ring control block */
1300 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1301 rcb->bge_hostaddr.bge_addr_lo =
1302 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1303 rcb->bge_hostaddr.bge_addr_hi =
1304 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1305 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1306 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1307 if (BGE_IS_5705_PLUS(sc))
1308 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1309 else
1310 rcb->bge_maxlen_flags =
1311 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1312 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1313 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1314 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1315
1316 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1317 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1318
1319 /*
1320 * Initialize the jumbo RX ring control block
1321 * We set the 'ring disabled' bit in the flags
1322 * field until we're actually ready to start
1323 * using this ring (i.e. once we set the MTU
1324 * high enough to require it).
1325 */
1326 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1327 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1328
1329 rcb->bge_hostaddr.bge_addr_lo =
1330 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1331 rcb->bge_hostaddr.bge_addr_hi =
1332 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1333 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1334 sc->bge_cdata.bge_rx_jumbo_ring_map,
1335 BUS_DMASYNC_PREREAD);
1336 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1337 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1338 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1339 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1340 rcb->bge_hostaddr.bge_addr_hi);
1341 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1342 rcb->bge_hostaddr.bge_addr_lo);
1343
1344 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1345 rcb->bge_maxlen_flags);
1346 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1347
1348 /* Set up dummy disabled mini ring RCB */
1349 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1350 rcb->bge_maxlen_flags =
1351 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1352 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1353 rcb->bge_maxlen_flags);
1354 }
1355
1356 /*
1357 * Set the BD ring replentish thresholds. The recommended
1358 * values are 1/8th the number of descriptors allocated to
1359 * each ring.
1360 * XXX The 5754 requires a lower threshold, so it might be a
1361 * requirement of all 575x family chips. The Linux driver sets
1362 * the lower threshold for all 5705 family chips as well, but there
1363 * are reports that it might not need to be so strict.
1364 */
1365 if (BGE_IS_5705_PLUS(sc))
1366 val = 8;
1367 else
1368 val = BGE_STD_RX_RING_CNT / 8;
1369 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1370 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1371
1372 /*
1373 * Disable all unused send rings by setting the 'ring disabled'
1374 * bit in the flags field of all the TX send ring control blocks.
1375 * These are located in NIC memory.
1376 */
1377 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1378 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1379 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1380 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1381 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1382 vrcb += sizeof(struct bge_rcb);
1383 }
1384
1385 /* Configure TX RCB 0 (we use only the first ring) */
1386 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1387 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1388 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1389 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1390 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1391 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1392 if (!(BGE_IS_5705_PLUS(sc)))
1393 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1394 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1395
1396 /* Disable all unused RX return rings */
1397 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1398 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1399 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1400 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1401 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1402 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1403 BGE_RCB_FLAG_RING_DISABLED));
1404 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1405 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1406 (i * (sizeof(uint64_t))), 0);
1407 vrcb += sizeof(struct bge_rcb);
1408 }
1409
1410 /* Initialize RX ring indexes */
1411 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1412 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1413 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1414
1415 /*
1416 * Set up RX return ring 0
1417 * Note that the NIC address for RX return rings is 0x00000000.
1418 * The return rings live entirely within the host, so the
1419 * nicaddr field in the RCB isn't used.
1420 */
1421 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1422 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1423 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1424 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1425 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1426 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1427 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1428
1429 /* Set random backoff seed for TX */
1430 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1431 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1432 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1433 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1434 BGE_TX_BACKOFF_SEED_MASK);
1435
1436 /* Set inter-packet gap */
1437 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1438
1439 /*
1440 * Specify which ring to use for packets that don't match
1441 * any RX rules.
1442 */
1443 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1444
1445 /*
1446 * Configure number of RX lists. One interrupt distribution
1447 * list, sixteen active lists, one bad frames class.
1448 */
1449 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1450
1451 /* Inialize RX list placement stats mask. */
1452 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1453 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1454
1455 /* Disable host coalescing until we get it set up */
1456 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1457
1458 /* Poll to make sure it's shut down. */
1459 for (i = 0; i < BGE_TIMEOUT; i++) {
1460 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1461 break;
1462 DELAY(10);
1463 }
1464
1465 if (i == BGE_TIMEOUT) {
1466 device_printf(sc->bge_dev,
1467 "host coalescing engine failed to idle\n");
1468 return (ENXIO);
1469 }
1470
1471 /* Set up host coalescing defaults */
1472 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1473 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1474 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1475 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1476 if (!(BGE_IS_5705_PLUS(sc))) {
1477 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1478 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1479 }
1480 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1481 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1482
1483 /* Set up address of statistics block */
1484 if (!(BGE_IS_5705_PLUS(sc))) {
1485 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1486 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1487 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1488 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1489 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1490 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1491 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1492 }
1493
1494 /* Set up address of status block */
1495 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1496 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1497 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1498 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1499 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1500 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1501
1502 /* Turn on host coalescing state machine */
1503 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1504
1505 /* Turn on RX BD completion state machine and enable attentions */
1506 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1507 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1508
1509 /* Turn on RX list placement state machine */
1510 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1511
1512 /* Turn on RX list selector state machine. */
1513 if (!(BGE_IS_5705_PLUS(sc)))
1514 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1515
1516 /* Turn on DMA, clear stats */
1517 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB |
1518 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR |
1519 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB |
1520 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB |
1521 ((sc->bge_flags & BGE_FLAG_TBI) ?
1522 BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1523
1524 /* Set misc. local control, enable interrupts on attentions */
1525 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1526
1527 #ifdef notdef
1528 /* Assert GPIO pins for PHY reset */
1529 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1530 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1531 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1532 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1533 #endif
1534
1535 /* Turn on DMA completion state machine */
1536 if (!(BGE_IS_5705_PLUS(sc)))
1537 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1538
1539 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1540
1541 /* Enable host coalescing bug fix. */
1542 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1543 sc->bge_asicrev == BGE_ASICREV_BCM5787)
1544 val |= 1 << 29;
1545
1546 /* Turn on write DMA state machine */
1547 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1548
1549 /* Turn on read DMA state machine */
1550 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1551 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS);
1552
1553 /* Turn on RX data completion state machine */
1554 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1555
1556 /* Turn on RX BD initiator state machine */
1557 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1558
1559 /* Turn on RX data and RX BD initiator state machine */
1560 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1561
1562 /* Turn on Mbuf cluster free state machine */
1563 if (!(BGE_IS_5705_PLUS(sc)))
1564 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1565
1566 /* Turn on send BD completion state machine */
1567 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1568
1569 /* Turn on send data completion state machine */
1570 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1571
1572 /* Turn on send data initiator state machine */
1573 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1574
1575 /* Turn on send BD initiator state machine */
1576 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1577
1578 /* Turn on send BD selector state machine */
1579 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1580
1581 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1582 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1583 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1584
1585 /* ack/clear link change events */
1586 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1587 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1588 BGE_MACSTAT_LINK_CHANGED);
1589 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1590
1591 /* Enable PHY auto polling (for MII/GMII only) */
1592 if (sc->bge_flags & BGE_FLAG_TBI) {
1593 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1594 } else {
1595 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1596 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1597 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1598 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1599 BGE_EVTENB_MI_INTERRUPT);
1600 }
1601
1602 /*
1603 * Clear any pending link state attention.
1604 * Otherwise some link state change events may be lost until attention
1605 * is cleared by bge_intr() -> bge_link_upd() sequence.
1606 * It's not necessary on newer BCM chips - perhaps enabling link
1607 * state change attentions implies clearing pending attention.
1608 */
1609 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1610 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1611 BGE_MACSTAT_LINK_CHANGED);
1612
1613 /* Enable link state change attentions. */
1614 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1615
1616 return (0);
1617 }
1618
1619 const struct bge_revision *
1620 bge_lookup_rev(uint32_t chipid)
1621 {
1622 const struct bge_revision *br;
1623
1624 for (br = bge_revisions; br->br_name != NULL; br++) {
1625 if (br->br_chipid == chipid)
1626 return (br);
1627 }
1628
1629 for (br = bge_majorrevs; br->br_name != NULL; br++) {
1630 if (br->br_chipid == BGE_ASICREV(chipid))
1631 return (br);
1632 }
1633
1634 return (NULL);
1635 }
1636
1637 const struct bge_vendor *
1638 bge_lookup_vendor(uint16_t vid)
1639 {
1640 const struct bge_vendor *v;
1641
1642 for (v = bge_vendors; v->v_name != NULL; v++)
1643 if (v->v_id == vid)
1644 return (v);
1645
1646 panic("%s: unknown vendor %d", __func__, vid);
1647 return (NULL);
1648 }
1649
1650 /*
1651 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1652 * against our list and return its name if we find a match.
1653 *
1654 * Note that since the Broadcom controller contains VPD support, we
1655 * try to get the device name string from the controller itself instead
1656 * of the compiled-in string. It guarantees we'll always announce the
1657 * right product name. We fall back to the compiled-in string when
1658 * VPD is unavailable or corrupt.
1659 */
1660 static int
1661 bge_probe(device_t dev)
1662 {
1663 struct bge_type *t = bge_devs;
1664 struct bge_softc *sc = device_get_softc(dev);
1665 uint16_t vid, did;
1666
1667 sc->bge_dev = dev;
1668 vid = pci_get_vendor(dev);
1669 did = pci_get_device(dev);
1670 while(t->bge_vid != 0) {
1671 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1672 char model[64], buf[96];
1673 const struct bge_revision *br;
1674 const struct bge_vendor *v;
1675 uint32_t id;
1676
1677 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1678 BGE_PCIMISCCTL_ASICREV;
1679 br = bge_lookup_rev(id);
1680 v = bge_lookup_vendor(vid);
1681 {
1682 #if __FreeBSD_version > 700024
1683 const char *pname;
1684
1685 if (pci_get_vpd_ident(dev, &pname) == 0)
1686 snprintf(model, 64, "%s", pname);
1687 else
1688 #endif
1689 snprintf(model, 64, "%s %s",
1690 v->v_name,
1691 br != NULL ? br->br_name :
1692 "NetXtreme Ethernet Controller");
1693 }
1694 snprintf(buf, 96, "%s, %sASIC rev. %#04x", model,
1695 br != NULL ? "" : "unknown ", id >> 16);
1696 device_set_desc_copy(dev, buf);
1697 if (pci_get_subvendor(dev) == DELL_VENDORID)
1698 sc->bge_flags |= BGE_FLAG_NO_3LED;
1699 if (did == BCOM_DEVICEID_BCM5755M)
1700 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1701 return (0);
1702 }
1703 t++;
1704 }
1705
1706 return (ENXIO);
1707 }
1708
1709 static void
1710 bge_dma_free(struct bge_softc *sc)
1711 {
1712 int i;
1713
1714 /* Destroy DMA maps for RX buffers. */
1715 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1716 if (sc->bge_cdata.bge_rx_std_dmamap[i])
1717 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
1718 sc->bge_cdata.bge_rx_std_dmamap[i]);
1719 }
1720
1721 /* Destroy DMA maps for jumbo RX buffers. */
1722 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1723 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
1724 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
1725 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1726 }
1727
1728 /* Destroy DMA maps for TX buffers. */
1729 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1730 if (sc->bge_cdata.bge_tx_dmamap[i])
1731 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
1732 sc->bge_cdata.bge_tx_dmamap[i]);
1733 }
1734
1735 if (sc->bge_cdata.bge_mtag)
1736 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
1737
1738
1739 /* Destroy standard RX ring. */
1740 if (sc->bge_cdata.bge_rx_std_ring_map)
1741 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
1742 sc->bge_cdata.bge_rx_std_ring_map);
1743 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
1744 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
1745 sc->bge_ldata.bge_rx_std_ring,
1746 sc->bge_cdata.bge_rx_std_ring_map);
1747
1748 if (sc->bge_cdata.bge_rx_std_ring_tag)
1749 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
1750
1751 /* Destroy jumbo RX ring. */
1752 if (sc->bge_cdata.bge_rx_jumbo_ring_map)
1753 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1754 sc->bge_cdata.bge_rx_jumbo_ring_map);
1755
1756 if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
1757 sc->bge_ldata.bge_rx_jumbo_ring)
1758 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1759 sc->bge_ldata.bge_rx_jumbo_ring,
1760 sc->bge_cdata.bge_rx_jumbo_ring_map);
1761
1762 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
1763 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
1764
1765 /* Destroy RX return ring. */
1766 if (sc->bge_cdata.bge_rx_return_ring_map)
1767 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
1768 sc->bge_cdata.bge_rx_return_ring_map);
1769
1770 if (sc->bge_cdata.bge_rx_return_ring_map &&
1771 sc->bge_ldata.bge_rx_return_ring)
1772 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
1773 sc->bge_ldata.bge_rx_return_ring,
1774 sc->bge_cdata.bge_rx_return_ring_map);
1775
1776 if (sc->bge_cdata.bge_rx_return_ring_tag)
1777 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
1778
1779 /* Destroy TX ring. */
1780 if (sc->bge_cdata.bge_tx_ring_map)
1781 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
1782 sc->bge_cdata.bge_tx_ring_map);
1783
1784 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
1785 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
1786 sc->bge_ldata.bge_tx_ring,
1787 sc->bge_cdata.bge_tx_ring_map);
1788
1789 if (sc->bge_cdata.bge_tx_ring_tag)
1790 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
1791
1792 /* Destroy status block. */
1793 if (sc->bge_cdata.bge_status_map)
1794 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
1795 sc->bge_cdata.bge_status_map);
1796
1797 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
1798 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
1799 sc->bge_ldata.bge_status_block,
1800 sc->bge_cdata.bge_status_map);
1801
1802 if (sc->bge_cdata.bge_status_tag)
1803 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
1804
1805 /* Destroy statistics block. */
1806 if (sc->bge_cdata.bge_stats_map)
1807 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
1808 sc->bge_cdata.bge_stats_map);
1809
1810 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
1811 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
1812 sc->bge_ldata.bge_stats,
1813 sc->bge_cdata.bge_stats_map);
1814
1815 if (sc->bge_cdata.bge_stats_tag)
1816 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
1817
1818 /* Destroy the parent tag. */
1819 if (sc->bge_cdata.bge_parent_tag)
1820 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
1821 }
1822
1823 static int
1824 bge_dma_alloc(device_t dev)
1825 {
1826 struct bge_dmamap_arg ctx;
1827 struct bge_softc *sc;
1828 int i, error;
1829
1830 sc = device_get_softc(dev);
1831
1832 /*
1833 * Allocate the parent bus DMA tag appropriate for PCI.
1834 */
1835 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), /* parent */
1836 1, 0, /* alignment, boundary */
1837 BUS_SPACE_MAXADDR, /* lowaddr */
1838 BUS_SPACE_MAXADDR, /* highaddr */
1839 NULL, NULL, /* filter, filterarg */
1840 MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */
1841 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1842 0, /* flags */
1843 NULL, NULL, /* lockfunc, lockarg */
1844 &sc->bge_cdata.bge_parent_tag);
1845
1846 if (error != 0) {
1847 device_printf(sc->bge_dev,
1848 "could not allocate parent dma tag\n");
1849 return (ENOMEM);
1850 }
1851
1852 /*
1853 * Create tag for RX mbufs.
1854 */
1855 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
1856 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1857 NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES,
1858 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag);
1859
1860 if (error) {
1861 device_printf(sc->bge_dev, "could not allocate dma tag\n");
1862 return (ENOMEM);
1863 }
1864
1865 /* Create DMA maps for RX buffers. */
1866 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1867 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
1868 &sc->bge_cdata.bge_rx_std_dmamap[i]);
1869 if (error) {
1870 device_printf(sc->bge_dev,
1871 "can't create DMA map for RX\n");
1872 return (ENOMEM);
1873 }
1874 }
1875
1876 /* Create DMA maps for TX buffers. */
1877 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1878 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
1879 &sc->bge_cdata.bge_tx_dmamap[i]);
1880 if (error) {
1881 device_printf(sc->bge_dev,
1882 "can't create DMA map for RX\n");
1883 return (ENOMEM);
1884 }
1885 }
1886
1887 /* Create tag for standard RX ring. */
1888 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
1889 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1890 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
1891 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
1892
1893 if (error) {
1894 device_printf(sc->bge_dev, "could not allocate dma tag\n");
1895 return (ENOMEM);
1896 }
1897
1898 /* Allocate DMA'able memory for standard RX ring. */
1899 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
1900 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
1901 &sc->bge_cdata.bge_rx_std_ring_map);
1902 if (error)
1903 return (ENOMEM);
1904
1905 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1906
1907 /* Load the address of the standard RX ring. */
1908 ctx.bge_maxsegs = 1;
1909 ctx.sc = sc;
1910
1911 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
1912 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
1913 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
1914
1915 if (error)
1916 return (ENOMEM);
1917
1918 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
1919
1920 /* Create tags for jumbo mbufs. */
1921 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1922 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
1923 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1924 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
1925 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
1926 if (error) {
1927 device_printf(sc->bge_dev,
1928 "could not allocate jumbo dma tag\n");
1929 return (ENOMEM);
1930 }
1931
1932 /* Create tag for jumbo RX ring. */
1933 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
1934 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1935 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
1936 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
1937
1938 if (error) {
1939 device_printf(sc->bge_dev,
1940 "could not allocate jumbo ring dma tag\n");
1941 return (ENOMEM);
1942 }
1943
1944 /* Allocate DMA'able memory for jumbo RX ring. */
1945 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1946 (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
1947 BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1948 &sc->bge_cdata.bge_rx_jumbo_ring_map);
1949 if (error)
1950 return (ENOMEM);
1951
1952 /* Load the address of the jumbo RX ring. */
1953 ctx.bge_maxsegs = 1;
1954 ctx.sc = sc;
1955
1956 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1957 sc->bge_cdata.bge_rx_jumbo_ring_map,
1958 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
1959 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
1960
1961 if (error)
1962 return (ENOMEM);
1963
1964 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
1965
1966 /* Create DMA maps for jumbo RX buffers. */
1967 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1968 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
1969 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1970 if (error) {
1971 device_printf(sc->bge_dev,
1972 "can't create DMA map for jumbo RX\n");
1973 return (ENOMEM);
1974 }
1975 }
1976
1977 }
1978
1979 /* Create tag for RX return ring. */
1980 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
1981 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1982 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
1983 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
1984
1985 if (error) {
1986 device_printf(sc->bge_dev, "could not allocate dma tag\n");
1987 return (ENOMEM);
1988 }
1989
1990 /* Allocate DMA'able memory for RX return ring. */
1991 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
1992 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
1993 &sc->bge_cdata.bge_rx_return_ring_map);
1994 if (error)
1995 return (ENOMEM);
1996
1997 bzero((char *)sc->bge_ldata.bge_rx_return_ring,
1998 BGE_RX_RTN_RING_SZ(sc));
1999
2000 /* Load the address of the RX return ring. */
2001 ctx.bge_maxsegs = 1;
2002 ctx.sc = sc;
2003
2004 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2005 sc->bge_cdata.bge_rx_return_ring_map,
2006 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2007 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2008
2009 if (error)
2010 return (ENOMEM);
2011
2012 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2013
2014 /* Create tag for TX ring. */
2015 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2016 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2017 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2018 &sc->bge_cdata.bge_tx_ring_tag);
2019
2020 if (error) {
2021 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2022 return (ENOMEM);
2023 }
2024
2025 /* Allocate DMA'able memory for TX ring. */
2026 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2027 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2028 &sc->bge_cdata.bge_tx_ring_map);
2029 if (error)
2030 return (ENOMEM);
2031
2032 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2033
2034 /* Load the address of the TX ring. */
2035 ctx.bge_maxsegs = 1;
2036 ctx.sc = sc;
2037
2038 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2039 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2040 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2041
2042 if (error)
2043 return (ENOMEM);
2044
2045 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2046
2047 /* Create tag for status block. */
2048 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2049 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2050 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0,
2051 NULL, NULL, &sc->bge_cdata.bge_status_tag);
2052
2053 if (error) {
2054 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2055 return (ENOMEM);
2056 }
2057
2058 /* Allocate DMA'able memory for status block. */
2059 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2060 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2061 &sc->bge_cdata.bge_status_map);
2062 if (error)
2063 return (ENOMEM);
2064
2065 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2066
2067 /* Load the address of the status block. */
2068 ctx.sc = sc;
2069 ctx.bge_maxsegs = 1;
2070
2071 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2072 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2073 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2074
2075 if (error)
2076 return (ENOMEM);
2077
2078 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2079
2080 /* Create tag for statistics block. */
2081 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2082 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2083 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2084 &sc->bge_cdata.bge_stats_tag);
2085
2086 if (error) {
2087 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2088 return (ENOMEM);
2089 }
2090
2091 /* Allocate DMA'able memory for statistics block. */
2092 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2093 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2094 &sc->bge_cdata.bge_stats_map);
2095 if (error)
2096 return (ENOMEM);
2097
2098 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2099
2100 /* Load the address of the statstics block. */
2101 ctx.sc = sc;
2102 ctx.bge_maxsegs = 1;
2103
2104 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2105 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2106 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2107
2108 if (error)
2109 return (ENOMEM);
2110
2111 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2112
2113 return (0);
2114 }
2115
2116 #if __FreeBSD_version > 602105
2117 /*
2118 * Return true if this device has more than one port.
2119 */
2120 static int
2121 bge_has_multiple_ports(struct bge_softc *sc)
2122 {
2123 device_t dev = sc->bge_dev;
2124 u_int b, s, f, fscan;
2125
2126 b = pci_get_bus(dev);
2127 s = pci_get_slot(dev);
2128 f = pci_get_function(dev);
2129 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2130 if (fscan != f && pci_find_bsf(b, s, fscan) != NULL)
2131 return (1);
2132 return (0);
2133 }
2134
2135 /*
2136 * Return true if MSI can be used with this device.
2137 */
2138 static int
2139 bge_can_use_msi(struct bge_softc *sc)
2140 {
2141 int can_use_msi = 0;
2142
2143 switch (sc->bge_asicrev) {
2144 case BGE_ASICREV_BCM5714:
2145 /*
2146 * Apparently, MSI doesn't work when this chip is configured
2147 * in single-port mode.
2148 */
2149 if (bge_has_multiple_ports(sc))
2150 can_use_msi = 1;
2151 break;
2152 case BGE_ASICREV_BCM5750:
2153 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2154 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2155 can_use_msi = 1;
2156 break;
2157 case BGE_ASICREV_BCM5752:
2158 case BGE_ASICREV_BCM5780:
2159 can_use_msi = 1;
2160 break;
2161 }
2162 return (can_use_msi);
2163 }
2164 #endif
2165
2166 static int
2167 bge_attach(device_t dev)
2168 {
2169 struct ifnet *ifp;
2170 struct bge_softc *sc;
2171 uint32_t hwcfg = 0;
2172 uint32_t mac_tmp = 0;
2173 u_char eaddr[6];
2174 int error = 0, rid, trys, reg;
2175
2176 sc = device_get_softc(dev);
2177 sc->bge_dev = dev;
2178
2179 /*
2180 * Map control/status registers.
2181 */
2182 pci_enable_busmaster(dev);
2183
2184 rid = BGE_PCI_BAR0;
2185 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2186 RF_ACTIVE | PCI_RF_DENSE);
2187
2188 if (sc->bge_res == NULL) {
2189 device_printf (sc->bge_dev, "couldn't map memory\n");
2190 error = ENXIO;
2191 goto fail;
2192 }
2193
2194 sc->bge_btag = rman_get_bustag(sc->bge_res);
2195 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
2196
2197 /* Save ASIC rev. */
2198
2199 sc->bge_chipid =
2200 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
2201 BGE_PCIMISCCTL_ASICREV;
2202 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2203 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2204
2205 /* Save chipset family. */
2206 switch (sc->bge_asicrev) {
2207 case BGE_ASICREV_BCM5700:
2208 case BGE_ASICREV_BCM5701:
2209 case BGE_ASICREV_BCM5703:
2210 case BGE_ASICREV_BCM5704:
2211 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2212 break;
2213 case BGE_ASICREV_BCM5714_A0:
2214 case BGE_ASICREV_BCM5780:
2215 case BGE_ASICREV_BCM5714:
2216 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2217 /* FALLTHRU */
2218 case BGE_ASICREV_BCM5750:
2219 case BGE_ASICREV_BCM5752:
2220 case BGE_ASICREV_BCM5755:
2221 case BGE_ASICREV_BCM5787:
2222 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2223 /* FALLTHRU */
2224 case BGE_ASICREV_BCM5705:
2225 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2226 break;
2227 }
2228
2229 /* Set various bug flags. */
2230 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2231 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2232 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2233 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2234 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2235 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2236 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2237 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2238 if (BGE_IS_5705_PLUS(sc) &&
2239 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2240 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2241 sc->bge_asicrev == BGE_ASICREV_BCM5787)
2242 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2243 else
2244 sc->bge_flags |= BGE_FLAG_BER_BUG;
2245 }
2246
2247 /*
2248 * Check if this is a PCI-X or PCI Express device.
2249 */
2250 #if __FreeBSD_version > 602101
2251 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
2252 /*
2253 * Found a PCI Express capabilities register, this
2254 * must be a PCI Express device.
2255 */
2256 if (reg != 0)
2257 sc->bge_flags |= BGE_FLAG_PCIE;
2258 } else if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) {
2259 if (reg != 0)
2260 sc->bge_flags |= BGE_FLAG_PCIX;
2261 }
2262
2263 #else
2264 if (BGE_IS_5705_PLUS(sc)) {
2265 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
2266 if ((reg & 0xFF) == BGE_PCIE_CAPID)
2267 sc->bge_flags |= BGE_FLAG_PCIE;
2268 } else {
2269 /*
2270 * Check if the device is in PCI-X Mode.
2271 * (This bit is not valid on PCI Express controllers.)
2272 */
2273 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2274 BGE_PCISTATE_PCI_BUSMODE) == 0)
2275 sc->bge_flags |= BGE_FLAG_PCIX;
2276 }
2277 #endif
2278
2279 #if __FreeBSD_version > 602105
2280 {
2281 int msicount;
2282
2283 /*
2284 * Allocate the interrupt, using MSI if possible. These devices
2285 * support 8 MSI messages, but only the first one is used in
2286 * normal operation.
2287 */
2288 if (bge_can_use_msi(sc)) {
2289 msicount = pci_msi_count(dev);
2290 if (msicount > 1)
2291 msicount = 1;
2292 } else
2293 msicount = 0;
2294 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2295 rid = 1;
2296 sc->bge_flags |= BGE_FLAG_MSI;
2297 } else
2298 rid = 0;
2299 }
2300 #else
2301 rid = 0;
2302 #endif
2303
2304 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2305 RF_SHAREABLE | RF_ACTIVE);
2306
2307 if (sc->bge_irq == NULL) {
2308 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2309 error = ENXIO;
2310 goto fail;
2311 }
2312
2313 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2314
2315 /* Try to reset the chip. */
2316 if (bge_reset(sc)) {
2317 device_printf(sc->bge_dev, "chip reset failed\n");
2318 bge_release_resources(sc);
2319 error = ENXIO;
2320 goto fail;
2321 }
2322
2323 sc->bge_asf_mode = 0;
2324 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2325 == BGE_MAGIC_NUMBER)) {
2326 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2327 & BGE_HWCFG_ASF) {
2328 sc->bge_asf_mode |= ASF_ENABLE;
2329 sc->bge_asf_mode |= ASF_STACKUP;
2330 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
2331 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2332 }
2333 }
2334 }
2335
2336 /* Try to reset the chip again the nice way. */
2337 bge_stop_fw(sc);
2338 bge_sig_pre_reset(sc, BGE_RESET_STOP);
2339 if (bge_reset(sc)) {
2340 device_printf(sc->bge_dev, "chip reset failed\n");
2341 bge_release_resources(sc);
2342 error = ENXIO;
2343 goto fail;
2344 }
2345
2346 bge_sig_legacy(sc, BGE_RESET_STOP);
2347 bge_sig_post_reset(sc, BGE_RESET_STOP);
2348
2349 if (bge_chipinit(sc)) {
2350 device_printf(sc->bge_dev, "chip initialization failed\n");
2351 bge_release_resources(sc);
2352 error = ENXIO;
2353 goto fail;
2354 }
2355
2356 /*
2357 * Get station address from the EEPROM.
2358 */
2359 mac_tmp = bge_readmem_ind(sc, 0x0C14);
2360 if ((mac_tmp >> 16) == 0x484B) {
2361 eaddr[0] = (u_char)(mac_tmp >> 8);
2362 eaddr[1] = (u_char)mac_tmp;
2363 mac_tmp = bge_readmem_ind(sc, 0x0C18);
2364 eaddr[2] = (u_char)(mac_tmp >> 24);
2365 eaddr[3] = (u_char)(mac_tmp >> 16);
2366 eaddr[4] = (u_char)(mac_tmp >> 8);
2367 eaddr[5] = (u_char)mac_tmp;
2368 } else if (bge_read_eeprom(sc, eaddr,
2369 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2370 device_printf(sc->bge_dev, "failed to read station address\n");
2371 bge_release_resources(sc);
2372 error = ENXIO;
2373 goto fail;
2374 }
2375
2376 /* 5705 limits RX return ring to 512 entries. */
2377 if (BGE_IS_5705_PLUS(sc))
2378 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2379 else
2380 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2381
2382 if (bge_dma_alloc(dev)) {
2383 device_printf(sc->bge_dev,
2384 "failed to allocate DMA resources\n");
2385 bge_release_resources(sc);
2386 error = ENXIO;
2387 goto fail;
2388 }
2389
2390 /* Set default tuneable values. */
2391 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2392 sc->bge_rx_coal_ticks = 150;
2393 sc->bge_tx_coal_ticks = 150;
2394 sc->bge_rx_max_coal_bds = 10;
2395 sc->bge_tx_max_coal_bds = 10;
2396
2397 /* Set up ifnet structure */
2398 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2399 if (ifp == NULL) {
2400 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2401 bge_release_resources(sc);
2402 error = ENXIO;
2403 goto fail;
2404 }
2405 ifp->if_softc = sc;
2406 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2407 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2408 ifp->if_ioctl = bge_ioctl;
2409 ifp->if_start = bge_start;
2410 ifp->if_init = bge_init;
2411 ifp->if_mtu = ETHERMTU;
2412 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2413 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2414 IFQ_SET_READY(&ifp->if_snd);
2415 ifp->if_hwassist = BGE_CSUM_FEATURES;
2416 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2417 IFCAP_VLAN_MTU;
2418 #ifdef IFCAP_VLAN_HWCSUM
2419 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2420 #endif
2421 ifp->if_capenable = ifp->if_capabilities;
2422 #ifdef DEVICE_POLLING
2423 ifp->if_capabilities |= IFCAP_POLLING;
2424 #endif
2425
2426 /*
2427 * 5700 B0 chips do not support checksumming correctly due
2428 * to hardware bugs.
2429 */
2430 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2431 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2432 ifp->if_capenable &= IFCAP_HWCSUM;
2433 ifp->if_hwassist = 0;
2434 }
2435
2436 /*
2437 * Figure out what sort of media we have by checking the
2438 * hardware config word in the first 32k of NIC internal memory,
2439 * or fall back to examining the EEPROM if necessary.
2440 * Note: on some BCM5700 cards, this value appears to be unset.
2441 * If that's the case, we have to rely on identifying the NIC
2442 * by its PCI subsystem ID, as we do below for the SysKonnect
2443 * SK-9D41.
2444 */
2445 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2446 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2447 else {
2448 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2449 sizeof(hwcfg))) {
2450 device_printf(sc->bge_dev, "failed to read EEPROM\n");
2451 bge_release_resources(sc);
2452 error = ENXIO;
2453 goto fail;
2454 }
2455 hwcfg = ntohl(hwcfg);
2456 }
2457
2458 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2459 sc->bge_flags |= BGE_FLAG_TBI;
2460
2461 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2462 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
2463 sc->bge_flags |= BGE_FLAG_TBI;
2464
2465 if (sc->bge_flags & BGE_FLAG_TBI) {
2466 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2467 bge_ifmedia_sts);
2468 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2469 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2470 0, NULL);
2471 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2472 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2473 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2474 } else {
2475 /*
2476 * Do transceiver setup and tell the firmware the
2477 * driver is down so we can try to get access the
2478 * probe if ASF is running. Retry a couple of times
2479 * if we get a conflict with the ASF firmware accessing
2480 * the PHY.
2481 */
2482 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2483 again:
2484 bge_asf_driver_up(sc);
2485
2486 trys = 0;
2487 if (mii_phy_probe(dev, &sc->bge_miibus,
2488 bge_ifmedia_upd, bge_ifmedia_sts)) {
2489 if (trys++ < 4) {
2490 device_printf(sc->bge_dev, "Try again\n");
2491 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2492 BMCR_RESET);
2493 goto again;
2494 }
2495
2496 device_printf(sc->bge_dev, "MII without any PHY!\n");
2497 bge_release_resources(sc);
2498 error = ENXIO;
2499 goto fail;
2500 }
2501
2502 /*
2503 * Now tell the firmware we are going up after probing the PHY
2504 */
2505 if (sc->bge_asf_mode & ASF_STACKUP)
2506 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2507 }
2508
2509 /*
2510 * When using the BCM5701 in PCI-X mode, data corruption has
2511 * been observed in the first few bytes of some received packets.
2512 * Aligning the packet buffer in memory eliminates the corruption.
2513 * Unfortunately, this misaligns the packet payloads. On platforms
2514 * which do not support unaligned accesses, we will realign the
2515 * payloads by copying the received packets.
2516 */
2517 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2518 sc->bge_flags & BGE_FLAG_PCIX)
2519 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2520
2521 /*
2522 * Call MI attach routine.
2523 */
2524 ether_ifattach(ifp, eaddr);
2525 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2526
2527 /*
2528 * Hookup IRQ last.
2529 */
2530 #if __FreeBSD_version > 700030
2531 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2532 NULL, bge_intr, sc, &sc->bge_intrhand);
2533 #else
2534 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2535 bge_intr, sc, &sc->bge_intrhand);
2536 #endif
2537
2538 if (error) {
2539 bge_detach(dev);
2540 device_printf(sc->bge_dev, "couldn't set up irq\n");
2541 }
2542
2543 bge_add_sysctls(sc);
2544
2545 fail:
2546 return (error);
2547 }
2548
2549 static int
2550 bge_detach(device_t dev)
2551 {
2552 struct bge_softc *sc;
2553 struct ifnet *ifp;
2554
2555 sc = device_get_softc(dev);
2556 ifp = sc->bge_ifp;
2557
2558 #ifdef DEVICE_POLLING
2559 if (ifp->if_capenable & IFCAP_POLLING)
2560 ether_poll_deregister(ifp);
2561 #endif
2562
2563 BGE_LOCK(sc);
2564 bge_stop(sc);
2565 bge_reset(sc);
2566 BGE_UNLOCK(sc);
2567
2568 callout_drain(&sc->bge_stat_ch);
2569
2570 ether_ifdetach(ifp);
2571
2572 if (sc->bge_flags & BGE_FLAG_TBI) {
2573 ifmedia_removeall(&sc->bge_ifmedia);
2574 } else {
2575 bus_generic_detach(dev);
2576 device_delete_child(dev, sc->bge_miibus);
2577 }
2578
2579 bge_release_resources(sc);
2580
2581 return (0);
2582 }
2583
2584 static void
2585 bge_release_resources(struct bge_softc *sc)
2586 {
2587 device_t dev;
2588
2589 dev = sc->bge_dev;
2590
2591 if (sc->bge_intrhand != NULL)
2592 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2593
2594 if (sc->bge_irq != NULL)
2595 bus_release_resource(dev, SYS_RES_IRQ,
2596 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
2597
2598 #if __FreeBSD_version > 602105
2599 if (sc->bge_flags & BGE_FLAG_MSI)
2600 pci_release_msi(dev);
2601 #endif
2602
2603 if (sc->bge_res != NULL)
2604 bus_release_resource(dev, SYS_RES_MEMORY,
2605 BGE_PCI_BAR0, sc->bge_res);
2606
2607 if (sc->bge_ifp != NULL)
2608 if_free(sc->bge_ifp);
2609
2610 bge_dma_free(sc);
2611
2612 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
2613 BGE_LOCK_DESTROY(sc);
2614 }
2615
2616 static int
2617 bge_reset(struct bge_softc *sc)
2618 {
2619 device_t dev;
2620 uint32_t cachesize, command, pcistate, reset;
2621 void (*write_op)(struct bge_softc *, int, int);
2622 int i, val = 0;
2623
2624 dev = sc->bge_dev;
2625
2626 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
2627 if (sc->bge_flags & BGE_FLAG_PCIE)
2628 write_op = bge_writemem_direct;
2629 else
2630 write_op = bge_writemem_ind;
2631 } else
2632 write_op = bge_writereg_ind;
2633
2634 /* Save some important PCI state. */
2635 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2636 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2637 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2638
2639 pci_write_config(dev, BGE_PCI_MISC_CTL,
2640 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
2641 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
2642
2643 /* Disable fastboot on controllers that support it. */
2644 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2645 sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2646 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2647 if (bootverbose)
2648 device_printf(sc->bge_dev, "Disabling fastboot\n");
2649 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2650 }
2651
2652 /*
2653 * Write the magic number to SRAM at offset 0xB50.
2654 * When firmware finishes its initialization it will
2655 * write ~BGE_MAGIC_NUMBER to the same location.
2656 */
2657 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2658
2659 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
2660
2661 /* XXX: Broadcom Linux driver. */
2662 if (sc->bge_flags & BGE_FLAG_PCIE) {
2663 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
2664 CSR_WRITE_4(sc, 0x7E2C, 0x20);
2665 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2666 /* Prevent PCIE link training during global reset */
2667 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
2668 reset |= 1 << 29;
2669 }
2670 }
2671
2672 /*
2673 * Set GPHY Power Down Override to leave GPHY
2674 * powered up in D0 uninitialized.
2675 */
2676 if (BGE_IS_5705_PLUS(sc))
2677 reset |= 0x04000000;
2678
2679 /* Issue global reset */
2680 write_op(sc, BGE_MISC_CFG, reset);
2681
2682 DELAY(1000);
2683
2684 /* XXX: Broadcom Linux driver. */
2685 if (sc->bge_flags & BGE_FLAG_PCIE) {
2686 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2687 uint32_t v;
2688
2689 DELAY(500000); /* wait for link training to complete */
2690 v = pci_read_config(dev, 0xC4, 4);
2691 pci_write_config(dev, 0xC4, v | (1 << 15), 4);
2692 }
2693 /*
2694 * Set PCIE max payload size to 128 bytes and clear error
2695 * status.
2696 */
2697 pci_write_config(dev, 0xD8, 0xF5000, 4);
2698 }
2699
2700 /* Reset some of the PCI state that got zapped by reset. */
2701 pci_write_config(dev, BGE_PCI_MISC_CTL,
2702 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
2703 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
2704 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2705 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2706 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
2707
2708 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
2709 if (BGE_IS_5714_FAMILY(sc)) {
2710 uint32_t val;
2711
2712 /* This chip disables MSI on reset. */
2713 if (sc->bge_flags & BGE_FLAG_MSI) {
2714 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2);
2715 pci_write_config(dev, BGE_PCI_MSI_CTL,
2716 val | PCIM_MSICTRL_MSI_ENABLE, 2);
2717 val = CSR_READ_4(sc, BGE_MSI_MODE);
2718 CSR_WRITE_4(sc, BGE_MSI_MODE,
2719 val | BGE_MSIMODE_ENABLE);
2720 }
2721 val = CSR_READ_4(sc, BGE_MARB_MODE);
2722 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2723 } else
2724 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2725
2726 /*
2727 * Poll until we see the 1's complement of the magic number.
2728 * This indicates that the firmware initialization
2729 * is complete.
2730 */
2731 for (i = 0; i < BGE_TIMEOUT; i++) {
2732 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2733 if (val == ~BGE_MAGIC_NUMBER)
2734 break;
2735 DELAY(10);
2736 }
2737
2738 if (i == BGE_TIMEOUT) {
2739 device_printf(sc->bge_dev, "firmware handshake timed out, "
2740 "found 0x%08x\n", val);
2741 }
2742
2743 /*
2744 * XXX Wait for the value of the PCISTATE register to
2745 * return to its original pre-reset state. This is a
2746 * fairly good indicator of reset completion. If we don't
2747 * wait for the reset to fully complete, trying to read
2748 * from the device's non-PCI registers may yield garbage
2749 * results.
2750 */
2751 for (i = 0; i < BGE_TIMEOUT; i++) {
2752 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2753 break;
2754 DELAY(10);
2755 }
2756
2757 if (sc->bge_flags & BGE_FLAG_PCIE) {
2758 reset = bge_readmem_ind(sc, 0x7C00);
2759 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
2760 }
2761
2762 /* Fix up byte swapping. */
2763 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2764 BGE_MODECTL_BYTESWAP_DATA);
2765
2766 /* Tell the ASF firmware we are up */
2767 if (sc->bge_asf_mode & ASF_STACKUP)
2768 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2769
2770 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2771
2772 /*
2773 * The 5704 in TBI mode apparently needs some special
2774 * adjustment to insure the SERDES drive level is set
2775 * to 1.2V.
2776 */
2777 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2778 sc->bge_flags & BGE_FLAG_TBI) {
2779 uint32_t serdescfg;
2780
2781 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2782 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2783 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2784 }
2785
2786 /* XXX: Broadcom Linux driver. */
2787 if (sc->bge_flags & BGE_FLAG_PCIE &&
2788 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2789 uint32_t v;
2790
2791 v = CSR_READ_4(sc, 0x7C00);
2792 CSR_WRITE_4(sc, 0x7C00, v | (1 << 25));
2793 }
2794 DELAY(10000);
2795
2796 return(0);
2797 }
2798
2799 /*
2800 * Frame reception handling. This is called if there's a frame
2801 * on the receive return list.
2802 *
2803 * Note: we have to be able to handle two possibilities here:
2804 * 1) the frame is from the jumbo receive ring
2805 * 2) the frame is from the standard receive ring
2806 */
2807
2808 static void
2809 bge_rxeof(struct bge_softc *sc)
2810 {
2811 struct ifnet *ifp;
2812 int stdcnt = 0, jumbocnt = 0;
2813
2814 BGE_LOCK_ASSERT(sc);
2815
2816 /* Nothing to do. */
2817 if (sc->bge_rx_saved_considx ==
2818 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2819 return;
2820
2821 ifp = sc->bge_ifp;
2822
2823 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2824 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
2825 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2826 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD);
2827 if (BGE_IS_JUMBO_CAPABLE(sc))
2828 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2829 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD);
2830
2831 while(sc->bge_rx_saved_considx !=
2832 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2833 struct bge_rx_bd *cur_rx;
2834 uint32_t rxidx;
2835 struct mbuf *m = NULL;
2836 uint16_t vlan_tag = 0;
2837 int have_tag = 0;
2838
2839 #ifdef DEVICE_POLLING
2840 if (ifp->if_capenable & IFCAP_POLLING) {
2841 if (sc->rxcycles <= 0)
2842 break;
2843 sc->rxcycles--;
2844 }
2845 #endif
2846
2847 cur_rx =
2848 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2849
2850 rxidx = cur_rx->bge_idx;
2851 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2852
2853 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2854 have_tag = 1;
2855 vlan_tag = cur_rx->bge_vlan_tag;
2856 }
2857
2858 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2859 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2860 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
2861 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx],
2862 BUS_DMASYNC_POSTREAD);
2863 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
2864 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]);
2865 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2866 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2867 jumbocnt++;
2868 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2869 ifp->if_ierrors++;
2870 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2871 continue;
2872 }
2873 if (bge_newbuf_jumbo(sc,
2874 sc->bge_jumbo, NULL) == ENOBUFS) {
2875 ifp->if_ierrors++;
2876 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2877 continue;
2878 }
2879 } else {
2880 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2881 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2882 sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2883 BUS_DMASYNC_POSTREAD);
2884 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2885 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2886 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2887 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2888 stdcnt++;
2889 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2890 ifp->if_ierrors++;
2891 bge_newbuf_std(sc, sc->bge_std, m);
2892 continue;
2893 }
2894 if (bge_newbuf_std(sc, sc->bge_std,
2895 NULL) == ENOBUFS) {
2896 ifp->if_ierrors++;
2897 bge_newbuf_std(sc, sc->bge_std, m);
2898 continue;
2899 }
2900 }
2901
2902 ifp->if_ipackets++;
2903 #ifndef __NO_STRICT_ALIGNMENT
2904 /*
2905 * For architectures with strict alignment we must make sure
2906 * the payload is aligned.
2907 */
2908 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2909 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2910 cur_rx->bge_len);
2911 m->m_data += ETHER_ALIGN;
2912 }
2913 #endif
2914 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2915 m->m_pkthdr.rcvif = ifp;
2916
2917 if (ifp->if_capenable & IFCAP_RXCSUM) {
2918 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2919 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2920 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
2921 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2922 }
2923 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
2924 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
2925 m->m_pkthdr.csum_data =
2926 cur_rx->bge_tcp_udp_csum;
2927 m->m_pkthdr.csum_flags |=
2928 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2929 }
2930 }
2931
2932 /*
2933 * If we received a packet with a vlan tag,
2934 * attach that information to the packet.
2935 */
2936 if (have_tag) {
2937 #if __FreeBSD_version > 700022
2938 m->m_pkthdr.ether_vtag = vlan_tag;
2939 m->m_flags |= M_VLANTAG;
2940 #else
2941 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
2942 if (m == NULL)
2943 continue;
2944 #endif
2945 }
2946
2947 BGE_UNLOCK(sc);
2948 (*ifp->if_input)(ifp, m);
2949 BGE_LOCK(sc);
2950 }
2951
2952 if (stdcnt > 0)
2953 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2954 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
2955
2956 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0)
2957 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2958 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
2959
2960 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2961 if (stdcnt)
2962 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2963 if (jumbocnt)
2964 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2965 #ifdef notyet
2966 /*
2967 * This register wraps very quickly under heavy packet drops.
2968 * If you need correct statistics, you can enable this check.
2969 */
2970 if (BGE_IS_5705_PLUS(sc))
2971 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
2972 #endif
2973 }
2974
2975 static void
2976 bge_txeof(struct bge_softc *sc)
2977 {
2978 struct bge_tx_bd *cur_tx = NULL;
2979 struct ifnet *ifp;
2980
2981 BGE_LOCK_ASSERT(sc);
2982
2983 /* Nothing to do. */
2984 if (sc->bge_tx_saved_considx ==
2985 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2986 return;
2987
2988 ifp = sc->bge_ifp;
2989
2990 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2991 sc->bge_cdata.bge_tx_ring_map,
2992 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2993 /*
2994 * Go through our tx ring and free mbufs for those
2995 * frames that have been sent.
2996 */
2997 while (sc->bge_tx_saved_considx !=
2998 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2999 uint32_t idx = 0;
3000
3001 idx = sc->bge_tx_saved_considx;
3002 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3003 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3004 ifp->if_opackets++;
3005 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3006 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
3007 sc->bge_cdata.bge_tx_dmamap[idx],
3008 BUS_DMASYNC_POSTWRITE);
3009 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
3010 sc->bge_cdata.bge_tx_dmamap[idx]);
3011 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3012 sc->bge_cdata.bge_tx_chain[idx] = NULL;
3013 }
3014 sc->bge_txcnt--;
3015 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3016 }
3017
3018 if (cur_tx != NULL)
3019 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3020 if (sc->bge_txcnt == 0)
3021 sc->bge_timer = 0;
3022 }
3023
3024 #ifdef DEVICE_POLLING
3025 static void
3026 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3027 {
3028 struct bge_softc *sc = ifp->if_softc;
3029 uint32_t statusword;
3030
3031 BGE_LOCK(sc);
3032 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3033 BGE_UNLOCK(sc);
3034 return;
3035 }
3036
3037 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3038 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
3039
3040 statusword = atomic_readandclear_32(
3041 &sc->bge_ldata.bge_status_block->bge_status);
3042
3043 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3044 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
3045
3046 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3047 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3048 sc->bge_link_evt++;
3049
3050 if (cmd == POLL_AND_CHECK_STATUS)
3051 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3052 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3053 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3054 bge_link_upd(sc);
3055
3056 sc->rxcycles = count;
3057 bge_rxeof(sc);
3058 bge_txeof(sc);
3059 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3060 bge_start_locked(ifp);
3061
3062 BGE_UNLOCK(sc);
3063 }
3064 #endif /* DEVICE_POLLING */
3065
3066 static void
3067 bge_intr(void *xsc)
3068 {
3069 struct bge_softc *sc;
3070 struct ifnet *ifp;
3071 uint32_t statusword;
3072
3073 sc = xsc;
3074
3075 BGE_LOCK(sc);
3076
3077 ifp = sc->bge_ifp;
3078
3079 #ifdef DEVICE_POLLING
3080 if (ifp->if_capenable & IFCAP_POLLING) {
3081 BGE_UNLOCK(sc);
3082 return;
3083 }
3084 #endif
3085
3086 /*
3087 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
3088 * disable interrupts by writing nonzero like we used to, since with
3089 * our current organization this just gives complications and
3090 * pessimizations for re-enabling interrupts. We used to have races
3091 * instead of the necessary complications. Disabling interrupts
3092 * would just reduce the chance of a status update while we are
3093 * running (by switching to the interrupt-mode coalescence
3094 * parameters), but this chance is already very low so it is more
3095 * efficient to get another interrupt than prevent it.
3096 *
3097 * We do the ack first to ensure another interrupt if there is a
3098 * status update after the ack. We don't check for the status
3099 * changing later because it is more efficient to get another
3100 * interrupt than prevent it, not quite as above (not checking is
3101 * a smaller optimization than not toggling the interrupt enable,
3102 * since checking doesn't involve PCI accesses and toggling require
3103 * the status check). So toggling would probably be a pessimization
3104 * even with MSI. It would only be needed for using a task queue.
3105 */
3106 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3107
3108 /*
3109 * Do the mandatory PCI flush as well as get the link status.
3110 */
3111 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3112
3113 /* Make sure the descriptor ring indexes are coherent. */
3114 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3115 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
3116 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3117 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
3118
3119 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3120 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3121 statusword || sc->bge_link_evt)
3122 bge_link_upd(sc);
3123
3124 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3125 /* Check RX return ring producer/consumer. */
3126 bge_rxeof(sc);
3127
3128 /* Check TX ring producer/consumer. */
3129 bge_txeof(sc);
3130 }
3131
3132 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3133 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3134 bge_start_locked(ifp);
3135
3136 BGE_UNLOCK(sc);
3137 }
3138
3139 static void
3140 bge_asf_driver_up(struct bge_softc *sc)
3141 {
3142 if (sc->bge_asf_mode & ASF_STACKUP) {
3143 /* Send ASF heartbeat aprox. every 2s */
3144 if (sc->bge_asf_count)
3145 sc->bge_asf_count --;
3146 else {
3147 sc->bge_asf_count = 5;
3148 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3149 BGE_FW_DRV_ALIVE);
3150 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3151 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3152 CSR_WRITE_4(sc, BGE_CPU_EVENT,
3153 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3154 }
3155 }
3156 }
3157
3158 static void
3159 bge_tick(void *xsc)
3160 {
3161 struct bge_softc *sc = xsc;
3162 struct mii_data *mii = NULL;
3163
3164 BGE_LOCK_ASSERT(sc);
3165
3166 /* Synchronize with possible callout reset/stop. */
3167 if (callout_pending(&sc->bge_stat_ch) ||
3168 !callout_active(&sc->bge_stat_ch))
3169 return;
3170
3171 if (BGE_IS_5705_PLUS(sc))
3172 bge_stats_update_regs(sc);
3173 else
3174 bge_stats_update(sc);
3175
3176 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3177 mii = device_get_softc(sc->bge_miibus);
3178 /* Don't mess with the PHY in IPMI/ASF mode */
3179 if (!((sc->bge_asf_mode & ASF_STACKUP) && (sc->bge_link)))
3180 mii_tick(mii);
3181 } else {
3182 /*
3183 * Since in TBI mode auto-polling can't be used we should poll
3184 * link status manually. Here we register pending link event
3185 * and trigger interrupt.
3186 */
3187 #ifdef DEVICE_POLLING
3188 /* In polling mode we poll link state in bge_poll(). */
3189 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3190 #endif
3191 {
3192 sc->bge_link_evt++;
3193 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3194 }
3195 }
3196
3197 bge_asf_driver_up(sc);
3198 bge_watchdog(sc);
3199
3200 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3201 }
3202
3203 static void
3204 bge_stats_update_regs(struct bge_softc *sc)
3205 {
3206 struct ifnet *ifp;
3207
3208 ifp = sc->bge_ifp;
3209
3210 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3211 offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3212
3213 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3214 }
3215
3216 static void
3217 bge_stats_update(struct bge_softc *sc)
3218 {
3219 struct ifnet *ifp;
3220 bus_size_t stats;
3221 uint32_t cnt; /* current register value */
3222
3223 ifp = sc->bge_ifp;
3224
3225 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3226
3227 #define READ_STAT(sc, stats, stat) \
3228 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3229
3230 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3231 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3232 sc->bge_tx_collisions = cnt;
3233
3234 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3235 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3236 sc->bge_rx_discards = cnt;
3237
3238 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3239 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3240 sc->bge_tx_discards = cnt;
3241
3242 #undef READ_STAT
3243 }
3244
3245 /*
3246 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3247 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3248 * but when such padded frames employ the bge IP/TCP checksum offload,
3249 * the hardware checksum assist gives incorrect results (possibly
3250 * from incorporating its own padding into the UDP/TCP checksum; who knows).
3251 * If we pad such runts with zeros, the onboard checksum comes out correct.
3252 */
3253 static __inline int
3254 bge_cksum_pad(struct mbuf *m)
3255 {
3256 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3257 struct mbuf *last;
3258
3259 /* If there's only the packet-header and we can pad there, use it. */
3260 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3261 M_TRAILINGSPACE(m) >= padlen) {
3262 last = m;
3263 } else {
3264 /*
3265 * Walk packet chain to find last mbuf. We will either
3266 * pad there, or append a new mbuf and pad it.
3267 */
3268 for (last = m; last->m_next != NULL; last = last->m_next);
3269 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3270 /* Allocate new empty mbuf, pad it. Compact later. */
3271 struct mbuf *n;
3272
3273 MGET(n, M_DONTWAIT, MT_DATA);
3274 if (n == NULL)
3275 return (ENOBUFS);
3276 n->m_len = 0;
3277 last->m_next = n;
3278 last = n;
3279 }
3280 }
3281
3282 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3283 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3284 last->m_len += padlen;
3285 m->m_pkthdr.len += padlen;
3286
3287 return (0);
3288 }
3289
3290 /*
3291 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3292 * pointers to descriptors.
3293 */
3294 static int
3295 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3296 {
3297 bus_dma_segment_t segs[BGE_NSEG_NEW];
3298 bus_dmamap_t map;
3299 struct bge_tx_bd *d;
3300 struct mbuf *m = *m_head;
3301 uint32_t idx = *txidx;
3302 uint16_t csum_flags;
3303 int nsegs, i, error;
3304
3305 csum_flags = 0;
3306 if (m->m_pkthdr.csum_flags) {
3307 if (m->m_pkthdr.csum_flags & CSUM_IP)
3308 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3309 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3310 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3311 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3312 (error = bge_cksum_pad(m)) != 0) {
3313 m_freem(m);
3314 *m_head = NULL;
3315 return (error);
3316 }
3317 }
3318 if (m->m_flags & M_LASTFRAG)
3319 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3320 else if (m->m_flags & M_FRAG)
3321 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3322 }
3323
3324 map = sc->bge_cdata.bge_tx_dmamap[idx];
3325 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs,
3326 &nsegs, BUS_DMA_NOWAIT);
3327 if (error == EFBIG) {
3328 m = m_defrag(m, M_DONTWAIT);
3329 if (m == NULL) {
3330 m_freem(*m_head);
3331 *m_head = NULL;
3332 return (ENOBUFS);
3333 }
3334 *m_head = m;
3335 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m,
3336 segs, &nsegs, BUS_DMA_NOWAIT);
3337 if (error) {
3338 m_freem(m);
3339 *m_head = NULL;
3340 return (error);
3341 }
3342 } else if (error != 0)
3343 return (error);
3344
3345 /*
3346 * Sanity check: avoid coming within 16 descriptors
3347 * of the end of the ring.
3348 */
3349 if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) {
3350 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
3351 return (ENOBUFS);
3352 }
3353
3354 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
3355
3356 for (i = 0; ; i++) {
3357 d = &sc->bge_ldata.bge_tx_ring[idx];
3358 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3359 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3360 d->bge_len = segs[i].ds_len;
3361 d->bge_flags = csum_flags;
3362 if (i == nsegs - 1)
3363 break;
3364 BGE_INC(idx, BGE_TX_RING_CNT);
3365 }
3366
3367 /* Mark the last segment as end of packet... */
3368 d->bge_flags |= BGE_TXBDFLAG_END;
3369
3370 /* ... and put VLAN tag into first segment. */
3371 d = &sc->bge_ldata.bge_tx_ring[*txidx];
3372 #if __FreeBSD_version > 700022
3373 if (m->m_flags & M_VLANTAG) {
3374 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3375 d->bge_vlan_tag = m->m_pkthdr.ether_vtag;
3376 } else
3377 d->bge_vlan_tag = 0;
3378 #else
3379 {
3380 struct m_tag *mtag;
3381
3382 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
3383 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3384 d->bge_vlan_tag = VLAN_TAG_VALUE(mtag);
3385 } else
3386 d->bge_vlan_tag = 0;
3387 }
3388 #endif
3389
3390 /*
3391 * Insure that the map for this transmission
3392 * is placed at the array index of the last descriptor
3393 * in this chain.
3394 */
3395 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3396 sc->bge_cdata.bge_tx_dmamap[idx] = map;
3397 sc->bge_cdata.bge_tx_chain[idx] = m;
3398 sc->bge_txcnt += nsegs;
3399
3400 BGE_INC(idx, BGE_TX_RING_CNT);
3401 *txidx = idx;
3402
3403 return (0);
3404 }
3405
3406 /*
3407 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3408 * to the mbuf data regions directly in the transmit descriptors.
3409 */
3410 static void
3411 bge_start_locked(struct ifnet *ifp)
3412 {
3413 struct bge_softc *sc;
3414 struct mbuf *m_head = NULL;
3415 uint32_t prodidx;
3416 int count = 0;
3417
3418 sc = ifp->if_softc;
3419
3420 if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3421 return;
3422
3423 prodidx = sc->bge_tx_prodidx;
3424
3425 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3426 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3427 if (m_head == NULL)
3428 break;
3429
3430 /*
3431 * XXX
3432 * The code inside the if() block is never reached since we
3433 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3434 * requests to checksum TCP/UDP in a fragmented packet.
3435 *
3436 * XXX
3437 * safety overkill. If this is a fragmented packet chain
3438 * with delayed TCP/UDP checksums, then only encapsulate
3439 * it if we have enough descriptors to handle the entire
3440 * chain at once.
3441 * (paranoia -- may not actually be needed)
3442 */
3443 if (m_head->m_flags & M_FIRSTFRAG &&
3444 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3445 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3446 m_head->m_pkthdr.csum_data + 16) {
3447 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3448 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3449 break;
3450 }
3451 }
3452
3453 /*
3454 * Pack the data into the transmit ring. If we
3455 * don't have room, set the OACTIVE flag and wait
3456 * for the NIC to drain the ring.
3457 */
3458 if (bge_encap(sc, &m_head, &prodidx)) {
3459 if (m_head == NULL)
3460 break;
3461 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3462 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3463 break;
3464 }
3465 ++count;
3466
3467 /*
3468 * If there's a BPF listener, bounce a copy of this frame
3469 * to him.
3470 */
3471 #ifdef ETHER_BPF_MTAP
3472 ETHER_BPF_MTAP(ifp, m_head);
3473 #else
3474 BPF_MTAP(ifp, m_head);
3475 #endif
3476 }
3477
3478 if (count == 0)
3479 /* No packets were dequeued. */
3480 return;
3481
3482 /* Transmit. */
3483 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3484 /* 5700 b2 errata */
3485 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3486 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3487
3488 sc->bge_tx_prodidx = prodidx;
3489
3490 /*
3491 * Set a timeout in case the chip goes out to lunch.
3492 */
3493 sc->bge_timer = 5;
3494 }
3495
3496 /*
3497 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3498 * to the mbuf data regions directly in the transmit descriptors.
3499 */
3500 static void
3501 bge_start(struct ifnet *ifp)
3502 {
3503 struct bge_softc *sc;
3504
3505 sc = ifp->if_softc;
3506 BGE_LOCK(sc);
3507 bge_start_locked(ifp);
3508 BGE_UNLOCK(sc);
3509 }
3510
3511 static void
3512 bge_init_locked(struct bge_softc *sc)
3513 {
3514 struct ifnet *ifp;
3515 uint16_t *m;
3516
3517 BGE_LOCK_ASSERT(sc);
3518
3519 ifp = sc->bge_ifp;
3520
3521 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3522 return;
3523
3524 /* Cancel pending I/O and flush buffers. */
3525 bge_stop(sc);
3526
3527 bge_stop_fw(sc);
3528 bge_sig_pre_reset(sc, BGE_RESET_START);
3529 bge_reset(sc);
3530 bge_sig_legacy(sc, BGE_RESET_START);
3531 bge_sig_post_reset(sc, BGE_RESET_START);
3532
3533 bge_chipinit(sc);
3534
3535 /*
3536 * Init the various state machines, ring
3537 * control blocks and firmware.
3538 */
3539 if (bge_blockinit(sc)) {
3540 device_printf(sc->bge_dev, "initialization failure\n");
3541 return;
3542 }
3543
3544 ifp = sc->bge_ifp;
3545
3546 /* Specify MTU. */
3547 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3548 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3549
3550 /* Load our MAC address. */
3551 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
3552 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3553 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3554
3555 /* Program promiscuous mode. */
3556 bge_setpromisc(sc);
3557
3558 /* Program multicast filter. */
3559 bge_setmulti(sc);
3560
3561 /* Init RX ring. */
3562 bge_init_rx_ring_std(sc);
3563
3564 /*
3565 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3566 * memory to insure that the chip has in fact read the first
3567 * entry of the ring.
3568 */
3569 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3570 uint32_t v, i;
3571 for (i = 0; i < 10; i++) {
3572 DELAY(20);
3573 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3574 if (v == (MCLBYTES - ETHER_ALIGN))
3575 break;
3576 }
3577 if (i == 10)
3578 device_printf (sc->bge_dev,
3579 "5705 A0 chip failed to load RX ring\n");
3580 }
3581
3582 /* Init jumbo RX ring. */
3583 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3584 bge_init_rx_ring_jumbo(sc);
3585
3586 /* Init our RX return ring index. */
3587 sc->bge_rx_saved_considx = 0;
3588
3589 /* Init our RX/TX stat counters. */
3590 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
3591
3592 /* Init TX ring. */
3593 bge_init_tx_ring(sc);
3594
3595 /* Turn on transmitter. */
3596 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3597
3598 /* Turn on receiver. */
3599 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3600
3601 /* Tell firmware we're alive. */
3602 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3603
3604 #ifdef DEVICE_POLLING
3605 /* Disable interrupts if we are polling. */
3606 if (ifp->if_capenable & IFCAP_POLLING) {
3607 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
3608 BGE_PCIMISCCTL_MASK_PCI_INTR);
3609 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3610 } else
3611 #endif
3612
3613 /* Enable host interrupts. */
3614 {
3615 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3616 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3617 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3618 }
3619
3620 bge_ifmedia_upd_locked(ifp);
3621
3622 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3623 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3624
3625 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3626 }
3627
3628 static void
3629 bge_init(void *xsc)
3630 {
3631 struct bge_softc *sc = xsc;
3632
3633 BGE_LOCK(sc);
3634 bge_init_locked(sc);
3635 BGE_UNLOCK(sc);
3636 }
3637
3638 /*
3639 * Set media options.
3640 */
3641 static int
3642 bge_ifmedia_upd(struct ifnet *ifp)
3643 {
3644 struct bge_softc *sc = ifp->if_softc;
3645 int res;
3646
3647 BGE_LOCK(sc);
3648 res = bge_ifmedia_upd_locked(ifp);
3649 BGE_UNLOCK(sc);
3650
3651 return (res);
3652 }
3653
3654 static int
3655 bge_ifmedia_upd_locked(struct ifnet *ifp)
3656 {
3657 struct bge_softc *sc = ifp->if_softc;
3658 struct mii_data *mii;
3659 struct ifmedia *ifm;
3660
3661 BGE_LOCK_ASSERT(sc);
3662
3663 ifm = &sc->bge_ifmedia;
3664
3665 /* If this is a 1000baseX NIC, enable the TBI port. */
3666 if (sc->bge_flags & BGE_FLAG_TBI) {
3667 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3668 return (EINVAL);
3669 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3670 case IFM_AUTO:
3671 /*
3672 * The BCM5704 ASIC appears to have a special
3673 * mechanism for programming the autoneg
3674 * advertisement registers in TBI mode.
3675 */
3676 if (bge_fake_autoneg == 0 &&
3677 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3678 uint32_t sgdig;
3679 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3680 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3681 sgdig |= BGE_SGDIGCFG_AUTO |
3682 BGE_SGDIGCFG_PAUSE_CAP |
3683 BGE_SGDIGCFG_ASYM_PAUSE;
3684 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3685 sgdig | BGE_SGDIGCFG_SEND);
3686 DELAY(5);
3687 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3688 }
3689 break;
3690 case IFM_1000_SX:
3691 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3692 BGE_CLRBIT(sc, BGE_MAC_MODE,
3693 BGE_MACMODE_HALF_DUPLEX);
3694 } else {
3695 BGE_SETBIT(sc, BGE_MAC_MODE,
3696 BGE_MACMODE_HALF_DUPLEX);
3697 }
3698 break;
3699 default:
3700 return (EINVAL);
3701 }
3702 return (0);
3703 }
3704
3705 sc->bge_link_evt++;
3706 mii = device_get_softc(sc->bge_miibus);
3707 if (mii->mii_instance) {
3708 struct mii_softc *miisc;
3709 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
3710 miisc = LIST_NEXT(miisc, mii_list))
3711 mii_phy_reset(miisc);
3712 }
3713 mii_mediachg(mii);
3714
3715 return (0);
3716 }
3717
3718 /*
3719 * Report current media status.
3720 */
3721 static void
3722 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3723 {
3724 struct bge_softc *sc = ifp->if_softc;
3725 struct mii_data *mii;
3726
3727 BGE_LOCK(sc);
3728
3729 if (sc->bge_flags & BGE_FLAG_TBI) {
3730 ifmr->ifm_status = IFM_AVALID;
3731 ifmr->ifm_active = IFM_ETHER;
3732 if (CSR_READ_4(sc, BGE_MAC_STS) &
3733 BGE_MACSTAT_TBI_PCS_SYNCHED)
3734 ifmr->ifm_status |= IFM_ACTIVE;
3735 else {
3736 ifmr->ifm_active |= IFM_NONE;
3737 BGE_UNLOCK(sc);
3738 return;
3739 }
3740 ifmr->ifm_active |= IFM_1000_SX;
3741 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3742 ifmr->ifm_active |= IFM_HDX;
3743 else
3744 ifmr->ifm_active |= IFM_FDX;
3745 BGE_UNLOCK(sc);
3746 return;
3747 }
3748
3749 mii = device_get_softc(sc->bge_miibus);
3750 mii_pollstat(mii);
3751 ifmr->ifm_active = mii->mii_media_active;
3752 ifmr->ifm_status = mii->mii_media_status;
3753
3754 BGE_UNLOCK(sc);
3755 }
3756
3757 static int
3758 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3759 {
3760 struct bge_softc *sc = ifp->if_softc;
3761 struct ifreq *ifr = (struct ifreq *) data;
3762 struct mii_data *mii;
3763 int flags, mask, error = 0;
3764
3765 switch (command) {
3766 case SIOCSIFMTU:
3767 if (ifr->ifr_mtu < ETHERMIN ||
3768 ((BGE_IS_JUMBO_CAPABLE(sc)) &&
3769 ifr->ifr_mtu > BGE_JUMBO_MTU) ||
3770 ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
3771 ifr->ifr_mtu > ETHERMTU))
3772 error = EINVAL;
3773 else if (ifp->if_mtu != ifr->ifr_mtu) {
3774 ifp->if_mtu = ifr->ifr_mtu;
3775 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3776 bge_init(sc);
3777 }
3778 break;
3779 case SIOCSIFFLAGS:
3780 BGE_LOCK(sc);
3781 if (ifp->if_flags & IFF_UP) {
3782 /*
3783 * If only the state of the PROMISC flag changed,
3784 * then just use the 'set promisc mode' command
3785 * instead of reinitializing the entire NIC. Doing
3786 * a full re-init means reloading the firmware and
3787 * waiting for it to start up, which may take a
3788 * second or two. Similarly for ALLMULTI.
3789 */
3790 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3791 flags = ifp->if_flags ^ sc->bge_if_flags;
3792 if (flags & IFF_PROMISC)
3793 bge_setpromisc(sc);
3794 if (flags & IFF_ALLMULTI)
3795 bge_setmulti(sc);
3796 } else
3797 bge_init_locked(sc);
3798 } else {
3799 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3800 bge_stop(sc);
3801 }
3802 }
3803 sc->bge_if_flags = ifp->if_flags;
3804 BGE_UNLOCK(sc);
3805 error = 0;
3806 break;
3807 case SIOCADDMULTI:
3808 case SIOCDELMULTI:
3809 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3810 BGE_LOCK(sc);
3811 bge_setmulti(sc);
3812 BGE_UNLOCK(sc);
3813 error = 0;
3814 }
3815 break;
3816 case SIOCSIFMEDIA:
3817 case SIOCGIFMEDIA:
3818 if (sc->bge_flags & BGE_FLAG_TBI) {
3819 error = ifmedia_ioctl(ifp, ifr,
3820 &sc->bge_ifmedia, command);
3821 } else {
3822 mii = device_get_softc(sc->bge_miibus);
3823 error = ifmedia_ioctl(ifp, ifr,
3824 &mii->mii_media, command);
3825 }
3826 break;
3827 case SIOCSIFCAP:
3828 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3829 #ifdef DEVICE_POLLING
3830 if (mask & IFCAP_POLLING) {
3831 if (ifr->ifr_reqcap & IFCAP_POLLING) {
3832 error = ether_poll_register(bge_poll, ifp);
3833 if (error)
3834 return (error);
3835 BGE_LOCK(sc);
3836 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
3837 BGE_PCIMISCCTL_MASK_PCI_INTR);
3838 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3839 ifp->if_capenable |= IFCAP_POLLING;
3840 BGE_UNLOCK(sc);
3841 } else {
3842 error = ether_poll_deregister(ifp);
3843 /* Enable interrupt even in error case */
3844 BGE_LOCK(sc);
3845 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
3846 BGE_PCIMISCCTL_MASK_PCI_INTR);
3847 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3848 ifp->if_capenable &= ~IFCAP_POLLING;
3849 BGE_UNLOCK(sc);
3850 }
3851 }
3852 #endif
3853 if (mask & IFCAP_HWCSUM) {
3854 ifp->if_capenable ^= IFCAP_HWCSUM;
3855 if (IFCAP_HWCSUM & ifp->if_capenable &&
3856 IFCAP_HWCSUM & ifp->if_capabilities)
3857 ifp->if_hwassist = BGE_CSUM_FEATURES;
3858 else
3859 ifp->if_hwassist = 0;
3860 #ifdef VLAN_CAPABILITIES
3861 VLAN_CAPABILITIES(ifp);
3862 #endif
3863 }
3864 break;
3865 default:
3866 error = ether_ioctl(ifp, command, data);
3867 break;
3868 }
3869
3870 return (error);
3871 }
3872
3873 static void
3874 bge_watchdog(struct bge_softc *sc)
3875 {
3876 struct ifnet *ifp;
3877
3878 BGE_LOCK_ASSERT(sc);
3879
3880 if (sc->bge_timer == 0 || --sc->bge_timer)
3881 return;
3882
3883 ifp = sc->bge_ifp;
3884
3885 if_printf(ifp, "watchdog timeout -- resetting\n");
3886
3887 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3888 bge_init_locked(sc);
3889
3890 ifp->if_oerrors++;
3891 }
3892
3893 /*
3894 * Stop the adapter and free any mbufs allocated to the
3895 * RX and TX lists.
3896 */
3897 static void
3898 bge_stop(struct bge_softc *sc)
3899 {
3900 struct ifnet *ifp;
3901 struct ifmedia_entry *ifm;
3902 struct mii_data *mii = NULL;
3903 int mtmp, itmp;
3904
3905 BGE_LOCK_ASSERT(sc);
3906
3907 ifp = sc->bge_ifp;
3908
3909 if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3910 mii = device_get_softc(sc->bge_miibus);
3911
3912 callout_stop(&sc->bge_stat_ch);
3913
3914 /*
3915 * Disable all of the receiver blocks.
3916 */
3917 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3918 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3919 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3920 if (!(BGE_IS_5705_PLUS(sc)))
3921 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3922 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3923 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3924 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3925
3926 /*
3927 * Disable all of the transmit blocks.
3928 */
3929 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3930 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3931 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3932 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3933 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3934 if (!(BGE_IS_5705_PLUS(sc)))
3935 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3936 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3937
3938 /*
3939 * Shut down all of the memory managers and related
3940 * state machines.
3941 */
3942 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3943 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3944 if (!(BGE_IS_5705_PLUS(sc)))
3945 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3946 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3947 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3948 if (!(BGE_IS_5705_PLUS(sc))) {
3949 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3950 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3951 }
3952
3953 /* Disable host interrupts. */
3954 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3955 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3956
3957 /*
3958 * Tell firmware we're shutting down.
3959 */
3960
3961 bge_stop_fw(sc);
3962 bge_sig_pre_reset(sc, BGE_RESET_STOP);
3963 bge_reset(sc);
3964 bge_sig_legacy(sc, BGE_RESET_STOP);
3965 bge_sig_post_reset(sc, BGE_RESET_STOP);
3966
3967 /*
3968 * Keep the ASF firmware running if up.
3969 */
3970 if (sc->bge_asf_mode & ASF_STACKUP)
3971 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3972 else
3973 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3974
3975 /* Free the RX lists. */
3976 bge_free_rx_ring_std(sc);
3977
3978 /* Free jumbo RX list. */
3979 if (BGE_IS_JUMBO_CAPABLE(sc))
3980 bge_free_rx_ring_jumbo(sc);
3981
3982 /* Free TX buffers. */
3983 bge_free_tx_ring(sc);
3984
3985 /*
3986 * Isolate/power down the PHY, but leave the media selection
3987 * unchanged so that things will be put back to normal when
3988 * we bring the interface back up.
3989 */
3990 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3991 itmp = ifp->if_flags;
3992 ifp->if_flags |= IFF_UP;
3993 /*
3994 * If we are called from bge_detach(), mii is already NULL.
3995 */
3996 if (mii != NULL) {
3997 ifm = mii->mii_media.ifm_cur;
3998 mtmp = ifm->ifm_media;
3999 ifm->ifm_media = IFM_ETHER | IFM_NONE;
4000 mii_mediachg(mii);
4001 ifm->ifm_media = mtmp;
4002 }
4003 ifp->if_flags = itmp;
4004 }
4005
4006 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4007
4008 /* Clear MAC's link state (PHY may still have link UP). */
4009 if (bootverbose && sc->bge_link)
4010 if_printf(sc->bge_ifp, "link DOWN\n");
4011 sc->bge_link = 0;
4012
4013 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4014 }
4015
4016 /*
4017 * Stop all chip I/O so that the kernel's probe routines don't
4018 * get confused by errant DMAs when rebooting.
4019 */
4020 static void
4021 bge_shutdown(device_t dev)
4022 {
4023 struct bge_softc *sc;
4024
4025 sc = device_get_softc(dev);
4026
4027 BGE_LOCK(sc);
4028 bge_stop(sc);
4029 bge_reset(sc);
4030 BGE_UNLOCK(sc);
4031 }
4032
4033 static int
4034 bge_suspend(device_t dev)
4035 {
4036 struct bge_softc *sc;
4037
4038 sc = device_get_softc(dev);
4039 BGE_LOCK(sc);
4040 bge_stop(sc);
4041 BGE_UNLOCK(sc);
4042
4043 return (0);
4044 }
4045
4046 static int
4047 bge_resume(device_t dev)
4048 {
4049 struct bge_softc *sc;
4050 struct ifnet *ifp;
4051
4052 sc = device_get_softc(dev);
4053 BGE_LOCK(sc);
4054 ifp = sc->bge_ifp;
4055 if (ifp->if_flags & IFF_UP) {
4056 bge_init_locked(sc);
4057 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4058 bge_start_locked(ifp);
4059 }
4060 BGE_UNLOCK(sc);
4061
4062 return (0);
4063 }
4064
4065 static void
4066 bge_link_upd(struct bge_softc *sc)
4067 {
4068 struct mii_data *mii;
4069 uint32_t link, status;
4070
4071 BGE_LOCK_ASSERT(sc);
4072
4073 /* Clear 'pending link event' flag. */
4074 sc->bge_link_evt = 0;
4075
4076 /*
4077 * Process link state changes.
4078 * Grrr. The link status word in the status block does
4079 * not work correctly on the BCM5700 rev AX and BX chips,
4080 * according to all available information. Hence, we have
4081 * to enable MII interrupts in order to properly obtain
4082 * async link changes. Unfortunately, this also means that
4083 * we have to read the MAC status register to detect link
4084 * changes, thereby adding an additional register access to
4085 * the interrupt handler.
4086 *
4087 * XXX: perhaps link state detection procedure used for
4088 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4089 */
4090
4091 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4092 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4093 status = CSR_READ_4(sc, BGE_MAC_STS);
4094 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4095 mii = device_get_softc(sc->bge_miibus);
4096 mii_pollstat(mii);
4097 if (!sc->bge_link &&
4098 mii->mii_media_status & IFM_ACTIVE &&
4099 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4100 sc->bge_link++;
4101 if (bootverbose)
4102 if_printf(sc->bge_ifp, "link UP\n");
4103 } else if (sc->bge_link &&
4104 (!(mii->mii_media_status & IFM_ACTIVE) ||
4105 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4106 sc->bge_link = 0;
4107 if (bootverbose)
4108 if_printf(sc->bge_ifp, "link DOWN\n");
4109 }
4110
4111 /* Clear the interrupt. */
4112 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4113 BGE_EVTENB_MI_INTERRUPT);
4114 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4115 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4116 BRGPHY_INTRS);
4117 }
4118 return;
4119 }
4120
4121 if (sc->bge_flags & BGE_FLAG_TBI) {
4122 status = CSR_READ_4(sc, BGE_MAC_STS);
4123 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4124 if (!sc->bge_link) {
4125 sc->bge_link++;
4126 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4127 BGE_CLRBIT(sc, BGE_MAC_MODE,
4128 BGE_MACMODE_TBI_SEND_CFGS);
4129 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4130 if (bootverbose)
4131 if_printf(sc->bge_ifp, "link UP\n");
4132 if_link_state_change(sc->bge_ifp,
4133 LINK_STATE_UP);
4134 }
4135 } else if (sc->bge_link) {
4136 sc->bge_link = 0;
4137 if (bootverbose)
4138 if_printf(sc->bge_ifp, "link DOWN\n");
4139 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4140 }
4141 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4142 /*
4143 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4144 * in status word always set. Workaround this bug by reading
4145 * PHY link status directly.
4146 */
4147 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4148
4149 if (link != sc->bge_link ||
4150 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4151 mii = device_get_softc(sc->bge_miibus);
4152 mii_pollstat(mii);
4153 if (!sc->bge_link &&
4154 mii->mii_media_status & IFM_ACTIVE &&
4155 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4156 sc->bge_link++;
4157 if (bootverbose)
4158 if_printf(sc->bge_ifp, "link UP\n");
4159 } else if (sc->bge_link &&
4160 (!(mii->mii_media_status & IFM_ACTIVE) ||
4161 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4162 sc->bge_link = 0;
4163 if (bootverbose)
4164 if_printf(sc->bge_ifp, "link DOWN\n");
4165 }
4166 }
4167 } else {
4168 /*
4169 * Discard link events for MII/GMII controllers
4170 * if MI auto-polling is disabled.
4171 */
4172 }
4173
4174 /* Clear the attention. */
4175 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4176 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4177 BGE_MACSTAT_LINK_CHANGED);
4178 }
4179
4180 static void
4181 bge_add_sysctls(struct bge_softc *sc)
4182 {
4183 struct sysctl_ctx_list *ctx;
4184 struct sysctl_oid_list *children;
4185
4186 ctx = device_get_sysctl_ctx(sc->bge_dev);
4187 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4188
4189 #ifdef BGE_REGISTER_DEBUG
4190 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4191 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4192 "Debug Information");
4193
4194 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4195 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4196 "Register Read");
4197
4198 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4199 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4200 "Memory Read");
4201
4202 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "stat_IfHcInOctets",
4203 CTLFLAG_RD,
4204 &sc->bge_ldata.bge_stats->rxstats.ifHCInOctets.bge_addr_lo,
4205 "Bytes received");
4206
4207 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "stat_IfHcOutOctets",
4208 CTLFLAG_RD,
4209 &sc->bge_ldata.bge_stats->txstats.ifHCOutOctets.bge_addr_lo,
4210 "Bytes received");
4211 #endif
4212 }
4213
4214 #ifdef BGE_REGISTER_DEBUG
4215 static int
4216 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4217 {
4218 struct bge_softc *sc;
4219 uint16_t *sbdata;
4220 int error;
4221 int result;
4222 int i, j;
4223
4224 result = -1;
4225 error = sysctl_handle_int(oidp, &result, 0, req);
4226 if (error || (req->newptr == NULL))
4227 return (error);
4228
4229 if (result == 1) {
4230 sc = (struct bge_softc *)arg1;
4231
4232 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
4233 printf("Status Block:\n");
4234 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
4235 printf("%06x:", i);
4236 for (j = 0; j < 8; j++) {
4237 printf(" %04x", sbdata[i]);
4238 i += 4;
4239 }
4240 printf("\n");
4241 }
4242
4243 printf("Registers:\n");
4244 for (i = 0x800; i < 0xA00; ) {
4245 printf("%06x:", i);
4246 for (j = 0; j < 8; j++) {
4247 printf(" %08x", CSR_READ_4(sc, i));
4248 i += 4;
4249 }
4250 printf("\n");
4251 }
4252
4253 printf("Hardware Flags:\n");
4254 if (BGE_IS_575X_PLUS(sc))
4255 printf(" - 575X Plus\n");
4256 if (BGE_IS_5705_PLUS(sc))
4257 printf(" - 5705 Plus\n");
4258 if (BGE_IS_5714_FAMILY(sc))
4259 printf(" - 5714 Family\n");
4260 if (BGE_IS_5700_FAMILY(sc))
4261 printf(" - 5700 Family\n");
4262 if (sc->bge_flags & BGE_FLAG_JUMBO)
4263 printf(" - Supports Jumbo Frames\n");
4264 if (sc->bge_flags & BGE_FLAG_PCIX)
4265 printf(" - PCI-X Bus\n");
4266 if (sc->bge_flags & BGE_FLAG_PCIE)
4267 printf(" - PCI Express Bus\n");
4268 if (sc->bge_flags & BGE_FLAG_NO_3LED)
4269 printf(" - No 3 LEDs\n");
4270 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
4271 printf(" - RX Alignment Bug\n");
4272 }
4273
4274 return (error);
4275 }
4276
4277 static int
4278 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
4279 {
4280 struct bge_softc *sc;
4281 int error;
4282 uint16_t result;
4283 uint32_t val;
4284
4285 result = -1;
4286 error = sysctl_handle_int(oidp, &result, 0, req);
4287 if (error || (req->newptr == NULL))
4288 return (error);
4289
4290 if (result < 0x8000) {
4291 sc = (struct bge_softc *)arg1;
4292 val = CSR_READ_4(sc, result);
4293 printf("reg 0x%06X = 0x%08X\n", result, val);
4294 }
4295
4296 return (error);
4297 }
4298
4299 static int
4300 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
4301 {
4302 struct bge_softc *sc;
4303 int error;
4304 uint16_t result;
4305 uint32_t val;
4306
4307 result = -1;
4308 error = sysctl_handle_int(oidp, &result, 0, req);
4309 if (error || (req->newptr == NULL))
4310 return (error);
4311
4312 if (result < 0x8000) {
4313 sc = (struct bge_softc *)arg1;
4314 val = bge_readmem_ind(sc, result);
4315 printf("mem 0x%06X = 0x%08X\n", result, val);
4316 }
4317
4318 return (error);
4319 }
4320 #endif
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