FreeBSD/Linux Kernel Cross Reference
sys/dev/bge/if_bge.c
1 /*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36
37 /*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45 * frames, highly configurable RX filtering, and 16 RX and TX queues
46 * (which, along with RX filter rules, can be used for QOS applications).
47 * Other features, such as TCP segmentation, may be available as part
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49 * firmware images can be stored in hardware and need not be compiled
50 * into the driver.
51 *
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
54 *
55 * The BCM5701 is a single-chip solution incorporating both the BCM5700
56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57 * does not support external SSRAM.
58 *
59 * Broadcom also produces a variation of the BCM5700 under the "Altima"
60 * brand name, which is functionally similar but lacks PCI-X support.
61 *
62 * Without external SSRAM, you can only have at most 4 TX rings,
63 * and the use of the mini RX ring is disabled. This seems to imply
64 * that these features are simply not available on the BCM5701. As a
65 * result, this driver does not implement any support for the mini RX
66 * ring.
67 */
68
69 #ifdef HAVE_KERNEL_OPTION_HEADERS
70 #include "opt_device_polling.h"
71 #endif
72
73 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
77 #include <sys/mbuf.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
82 #include <sys/sysctl.h>
83
84 #include <net/if.h>
85 #include <net/if_arp.h>
86 #include <net/ethernet.h>
87 #include <net/if_dl.h>
88 #include <net/if_media.h>
89
90 #include <net/bpf.h>
91
92 #include <net/if_types.h>
93 #include <net/if_vlan_var.h>
94
95 #include <netinet/in_systm.h>
96 #include <netinet/in.h>
97 #include <netinet/ip.h>
98
99 #include <machine/bus.h>
100 #include <machine/resource.h>
101 #include <sys/bus.h>
102 #include <sys/rman.h>
103
104 #include <dev/mii/mii.h>
105 #include <dev/mii/miivar.h>
106 #include "miidevs.h"
107 #include <dev/mii/brgphyreg.h>
108
109 #ifdef __sparc64__
110 #include <dev/ofw/ofw_bus.h>
111 #include <dev/ofw/openfirm.h>
112 #include <machine/ofw_machdep.h>
113 #include <machine/ver.h>
114 #endif
115
116 #include <dev/pci/pcireg.h>
117 #include <dev/pci/pcivar.h>
118
119 #include <dev/bge/if_bgereg.h>
120
121 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
122 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
123
124 MODULE_DEPEND(bge, pci, 1, 1, 1);
125 MODULE_DEPEND(bge, ether, 1, 1, 1);
126 MODULE_DEPEND(bge, miibus, 1, 1, 1);
127
128 /* "device miibus" required. See GENERIC if you get errors here. */
129 #include "miibus_if.h"
130
131 /*
132 * Various supported device vendors/types and their names. Note: the
133 * spec seems to indicate that the hardware still has Alteon's vendor
134 * ID burned into it, though it will always be overriden by the vendor
135 * ID in the EEPROM. Just to be safe, we cover all possibilities.
136 */
137 static struct bge_type {
138 uint16_t bge_vid;
139 uint16_t bge_did;
140 } bge_devs[] = {
141 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
142 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
143
144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
145 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
147
148 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
149
150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
201
202 { SK_VENDORID, SK_DEVICEID_ALTIMA },
203
204 { TC_VENDORID, TC_DEVICEID_3C996 },
205
206 { 0, 0 }
207 };
208
209 static const struct bge_vendor {
210 uint16_t v_id;
211 const char *v_name;
212 } bge_vendors[] = {
213 { ALTEON_VENDORID, "Alteon" },
214 { ALTIMA_VENDORID, "Altima" },
215 { APPLE_VENDORID, "Apple" },
216 { BCOM_VENDORID, "Broadcom" },
217 { SK_VENDORID, "SysKonnect" },
218 { TC_VENDORID, "3Com" },
219
220 { 0, NULL }
221 };
222
223 static const struct bge_revision {
224 uint32_t br_chipid;
225 const char *br_name;
226 } bge_revisions[] = {
227 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
228 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
229 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
230 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
231 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
232 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
233 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
234 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
235 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
236 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
237 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
238 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
239 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
240 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
241 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
242 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
243 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
244 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
245 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
246 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
247 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
248 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
249 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
250 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
251 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
252 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
253 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
254 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
255 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
256 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
257 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
258 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
259 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
260 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
261 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
262 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
263 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
264 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
265 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
266 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
267 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
268 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
269 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
270 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
271 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
272 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
273 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
274 /* 5754 and 5787 share the same ASIC ID */
275 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
276 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
277 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
278 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
279 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
280
281 { 0, NULL }
282 };
283
284 /*
285 * Some defaults for major revisions, so that newer steppings
286 * that we don't know about have a shot at working.
287 */
288 static const struct bge_revision bge_majorrevs[] = {
289 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
290 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
291 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
292 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
293 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
294 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
295 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
296 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
297 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
298 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
299 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
300 /* 5754 and 5787 share the same ASIC ID */
301 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
302 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
303
304 { 0, NULL }
305 };
306
307 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
308 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
309 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
310 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
311 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
312
313 const struct bge_revision * bge_lookup_rev(uint32_t);
314 const struct bge_vendor * bge_lookup_vendor(uint16_t);
315
316 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
317
318 static int bge_probe(device_t);
319 static int bge_attach(device_t);
320 static int bge_detach(device_t);
321 static int bge_suspend(device_t);
322 static int bge_resume(device_t);
323 static void bge_release_resources(struct bge_softc *);
324 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
325 static int bge_dma_alloc(device_t);
326 static void bge_dma_free(struct bge_softc *);
327
328 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
329 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
330 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
331 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
332 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
333
334 static void bge_txeof(struct bge_softc *);
335 static void bge_rxeof(struct bge_softc *);
336
337 static void bge_asf_driver_up (struct bge_softc *);
338 static void bge_tick(void *);
339 static void bge_stats_update(struct bge_softc *);
340 static void bge_stats_update_regs(struct bge_softc *);
341 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
342
343 static void bge_intr(void *);
344 static void bge_start_locked(struct ifnet *);
345 static void bge_start(struct ifnet *);
346 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
347 static void bge_init_locked(struct bge_softc *);
348 static void bge_init(void *);
349 static void bge_stop(struct bge_softc *);
350 static void bge_watchdog(struct bge_softc *);
351 static void bge_shutdown(device_t);
352 static int bge_ifmedia_upd_locked(struct ifnet *);
353 static int bge_ifmedia_upd(struct ifnet *);
354 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
355
356 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
357 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
358
359 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
360 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
361
362 static void bge_setpromisc(struct bge_softc *);
363 static void bge_setmulti(struct bge_softc *);
364 static void bge_setvlan(struct bge_softc *);
365
366 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
367 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
368 static int bge_init_rx_ring_std(struct bge_softc *);
369 static void bge_free_rx_ring_std(struct bge_softc *);
370 static int bge_init_rx_ring_jumbo(struct bge_softc *);
371 static void bge_free_rx_ring_jumbo(struct bge_softc *);
372 static void bge_free_tx_ring(struct bge_softc *);
373 static int bge_init_tx_ring(struct bge_softc *);
374
375 static int bge_chipinit(struct bge_softc *);
376 static int bge_blockinit(struct bge_softc *);
377
378 static int bge_has_eaddr(struct bge_softc *);
379 static uint32_t bge_readmem_ind(struct bge_softc *, int);
380 static void bge_writemem_ind(struct bge_softc *, int, int);
381 static void bge_writembx(struct bge_softc *, int, int);
382 #ifdef notdef
383 static uint32_t bge_readreg_ind(struct bge_softc *, int);
384 #endif
385 static void bge_writemem_direct(struct bge_softc *, int, int);
386 static void bge_writereg_ind(struct bge_softc *, int, int);
387
388 static int bge_miibus_readreg(device_t, int, int);
389 static int bge_miibus_writereg(device_t, int, int, int);
390 static void bge_miibus_statchg(device_t);
391 #ifdef DEVICE_POLLING
392 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
393 #endif
394
395 #define BGE_RESET_START 1
396 #define BGE_RESET_STOP 2
397 static void bge_sig_post_reset(struct bge_softc *, int);
398 static void bge_sig_legacy(struct bge_softc *, int);
399 static void bge_sig_pre_reset(struct bge_softc *, int);
400 static int bge_reset(struct bge_softc *);
401 static void bge_link_upd(struct bge_softc *);
402
403 /*
404 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
405 * leak information to untrusted users. It is also known to cause alignment
406 * traps on certain architectures.
407 */
408 #ifdef BGE_REGISTER_DEBUG
409 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
410 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
411 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
412 #endif
413 static void bge_add_sysctls(struct bge_softc *);
414 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
415
416 static device_method_t bge_methods[] = {
417 /* Device interface */
418 DEVMETHOD(device_probe, bge_probe),
419 DEVMETHOD(device_attach, bge_attach),
420 DEVMETHOD(device_detach, bge_detach),
421 DEVMETHOD(device_shutdown, bge_shutdown),
422 DEVMETHOD(device_suspend, bge_suspend),
423 DEVMETHOD(device_resume, bge_resume),
424
425 /* bus interface */
426 DEVMETHOD(bus_print_child, bus_generic_print_child),
427 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
428
429 /* MII interface */
430 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
431 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
432 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
433
434 { 0, 0 }
435 };
436
437 static driver_t bge_driver = {
438 "bge",
439 bge_methods,
440 sizeof(struct bge_softc)
441 };
442
443 static devclass_t bge_devclass;
444
445 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
446 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
447
448 static int bge_allow_asf = 0;
449
450 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
451
452 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
453 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
454 "Allow ASF mode if available");
455
456 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500"
457 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2"
458 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500"
459 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3"
460 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id"
461
462 static int
463 bge_has_eaddr(struct bge_softc *sc)
464 {
465 #ifdef __sparc64__
466 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
467 device_t dev;
468 uint32_t subvendor;
469
470 dev = sc->bge_dev;
471
472 /*
473 * The on-board BGEs found in sun4u machines aren't fitted with
474 * an EEPROM which means that we have to obtain the MAC address
475 * via OFW and that some tests will always fail. We distinguish
476 * such BGEs by the subvendor ID, which also has to be obtained
477 * from OFW instead of the PCI configuration space as the latter
478 * indicates Broadcom as the subvendor of the netboot interface.
479 * For early Blade 1500 and 2500 we even have to check the OFW
480 * device path as the subvendor ID always defaults to Broadcom
481 * there.
482 */
483 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
484 &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
485 subvendor == SUN_VENDORID)
486 return (0);
487 memset(buf, 0, sizeof(buf));
488 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
489 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
490 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
491 return (0);
492 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
493 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
494 return (0);
495 }
496 #endif
497 return (1);
498 }
499
500 static uint32_t
501 bge_readmem_ind(struct bge_softc *sc, int off)
502 {
503 device_t dev;
504 uint32_t val;
505
506 dev = sc->bge_dev;
507
508 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
509 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
510 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
511 return (val);
512 }
513
514 static void
515 bge_writemem_ind(struct bge_softc *sc, int off, int val)
516 {
517 device_t dev;
518
519 dev = sc->bge_dev;
520
521 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
522 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
523 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
524 }
525
526 #ifdef notdef
527 static uint32_t
528 bge_readreg_ind(struct bge_softc *sc, int off)
529 {
530 device_t dev;
531
532 dev = sc->bge_dev;
533
534 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
535 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
536 }
537 #endif
538
539 static void
540 bge_writereg_ind(struct bge_softc *sc, int off, int val)
541 {
542 device_t dev;
543
544 dev = sc->bge_dev;
545
546 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
547 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
548 }
549
550 static void
551 bge_writemem_direct(struct bge_softc *sc, int off, int val)
552 {
553 CSR_WRITE_4(sc, off, val);
554 }
555
556 static void
557 bge_writembx(struct bge_softc *sc, int off, int val)
558 {
559 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
560 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
561
562 CSR_WRITE_4(sc, off, val);
563 }
564
565 /*
566 * Map a single buffer address.
567 */
568
569 static void
570 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
571 {
572 struct bge_dmamap_arg *ctx;
573
574 if (error)
575 return;
576
577 ctx = arg;
578
579 if (nseg > ctx->bge_maxsegs) {
580 ctx->bge_maxsegs = 0;
581 return;
582 }
583
584 ctx->bge_busaddr = segs->ds_addr;
585 }
586
587 static uint8_t
588 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
589 {
590 uint32_t access, byte = 0;
591 int i;
592
593 /* Lock. */
594 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
595 for (i = 0; i < 8000; i++) {
596 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
597 break;
598 DELAY(20);
599 }
600 if (i == 8000)
601 return (1);
602
603 /* Enable access. */
604 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
605 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
606
607 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
608 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
609 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
610 DELAY(10);
611 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
612 DELAY(10);
613 break;
614 }
615 }
616
617 if (i == BGE_TIMEOUT * 10) {
618 if_printf(sc->bge_ifp, "nvram read timed out\n");
619 return (1);
620 }
621
622 /* Get result. */
623 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
624
625 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
626
627 /* Disable access. */
628 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
629
630 /* Unlock. */
631 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
632 CSR_READ_4(sc, BGE_NVRAM_SWARB);
633
634 return (0);
635 }
636
637 /*
638 * Read a sequence of bytes from NVRAM.
639 */
640 static int
641 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
642 {
643 int err = 0, i;
644 uint8_t byte = 0;
645
646 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
647 return (1);
648
649 for (i = 0; i < cnt; i++) {
650 err = bge_nvram_getbyte(sc, off + i, &byte);
651 if (err)
652 break;
653 *(dest + i) = byte;
654 }
655
656 return (err ? 1 : 0);
657 }
658
659 /*
660 * Read a byte of data stored in the EEPROM at address 'addr.' The
661 * BCM570x supports both the traditional bitbang interface and an
662 * auto access interface for reading the EEPROM. We use the auto
663 * access method.
664 */
665 static uint8_t
666 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
667 {
668 int i;
669 uint32_t byte = 0;
670
671 /*
672 * Enable use of auto EEPROM access so we can avoid
673 * having to use the bitbang method.
674 */
675 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
676
677 /* Reset the EEPROM, load the clock period. */
678 CSR_WRITE_4(sc, BGE_EE_ADDR,
679 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
680 DELAY(20);
681
682 /* Issue the read EEPROM command. */
683 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
684
685 /* Wait for completion */
686 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
687 DELAY(10);
688 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
689 break;
690 }
691
692 if (i == BGE_TIMEOUT * 10) {
693 device_printf(sc->bge_dev, "EEPROM read timed out\n");
694 return (1);
695 }
696
697 /* Get result. */
698 byte = CSR_READ_4(sc, BGE_EE_DATA);
699
700 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
701
702 return (0);
703 }
704
705 /*
706 * Read a sequence of bytes from the EEPROM.
707 */
708 static int
709 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
710 {
711 int i, error = 0;
712 uint8_t byte = 0;
713
714 for (i = 0; i < cnt; i++) {
715 error = bge_eeprom_getbyte(sc, off + i, &byte);
716 if (error)
717 break;
718 *(dest + i) = byte;
719 }
720
721 return (error ? 1 : 0);
722 }
723
724 static int
725 bge_miibus_readreg(device_t dev, int phy, int reg)
726 {
727 struct bge_softc *sc;
728 uint32_t val, autopoll;
729 int i;
730
731 sc = device_get_softc(dev);
732
733 /*
734 * Broadcom's own driver always assumes the internal
735 * PHY is at GMII address 1. On some chips, the PHY responds
736 * to accesses at all addresses, which could cause us to
737 * bogusly attach the PHY 32 times at probe type. Always
738 * restricting the lookup to address 1 is simpler than
739 * trying to figure out which chips revisions should be
740 * special-cased.
741 */
742 if (phy != 1)
743 return (0);
744
745 /* Reading with autopolling on may trigger PCI errors */
746 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
747 if (autopoll & BGE_MIMODE_AUTOPOLL) {
748 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
749 DELAY(40);
750 }
751
752 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
753 BGE_MIPHY(phy) | BGE_MIREG(reg));
754
755 for (i = 0; i < BGE_TIMEOUT; i++) {
756 DELAY(10);
757 val = CSR_READ_4(sc, BGE_MI_COMM);
758 if (!(val & BGE_MICOMM_BUSY))
759 break;
760 }
761
762 if (i == BGE_TIMEOUT) {
763 device_printf(sc->bge_dev,
764 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
765 phy, reg, val);
766 val = 0;
767 goto done;
768 }
769
770 DELAY(5);
771 val = CSR_READ_4(sc, BGE_MI_COMM);
772
773 done:
774 if (autopoll & BGE_MIMODE_AUTOPOLL) {
775 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
776 DELAY(40);
777 }
778
779 if (val & BGE_MICOMM_READFAIL)
780 return (0);
781
782 return (val & 0xFFFF);
783 }
784
785 static int
786 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
787 {
788 struct bge_softc *sc;
789 uint32_t autopoll;
790 int i;
791
792 sc = device_get_softc(dev);
793
794 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
795 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
796 return(0);
797
798 /* Reading with autopolling on may trigger PCI errors */
799 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
800 if (autopoll & BGE_MIMODE_AUTOPOLL) {
801 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
802 DELAY(40);
803 }
804
805 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
806 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
807
808 for (i = 0; i < BGE_TIMEOUT; i++) {
809 DELAY(10);
810 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
811 DELAY(5);
812 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
813 break;
814 }
815 }
816
817 if (i == BGE_TIMEOUT) {
818 device_printf(sc->bge_dev,
819 "PHY write timed out (phy %d, reg %d, val %d)\n",
820 phy, reg, val);
821 return (0);
822 }
823
824 if (autopoll & BGE_MIMODE_AUTOPOLL) {
825 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
826 DELAY(40);
827 }
828
829 return (0);
830 }
831
832 static void
833 bge_miibus_statchg(device_t dev)
834 {
835 struct bge_softc *sc;
836 struct mii_data *mii;
837 sc = device_get_softc(dev);
838 mii = device_get_softc(sc->bge_miibus);
839
840 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
841 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
842 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
843 else
844 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
845
846 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
847 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
848 else
849 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
850 }
851
852 /*
853 * Intialize a standard receive ring descriptor.
854 */
855 static int
856 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
857 {
858 struct mbuf *m_new = NULL;
859 struct bge_rx_bd *r;
860 struct bge_dmamap_arg ctx;
861 int error;
862
863 if (m == NULL) {
864 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
865 if (m_new == NULL)
866 return (ENOBUFS);
867 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
868 } else {
869 m_new = m;
870 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
871 m_new->m_data = m_new->m_ext.ext_buf;
872 }
873
874 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
875 m_adj(m_new, ETHER_ALIGN);
876 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
877 r = &sc->bge_ldata.bge_rx_std_ring[i];
878 ctx.bge_maxsegs = 1;
879 ctx.sc = sc;
880 error = bus_dmamap_load(sc->bge_cdata.bge_mtag,
881 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *),
882 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
883 if (error || ctx.bge_maxsegs == 0) {
884 if (m == NULL) {
885 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
886 m_freem(m_new);
887 }
888 return (ENOMEM);
889 }
890 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr);
891 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr);
892 r->bge_flags = BGE_RXBDFLAG_END;
893 r->bge_len = m_new->m_len;
894 r->bge_idx = i;
895
896 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
897 sc->bge_cdata.bge_rx_std_dmamap[i],
898 BUS_DMASYNC_PREREAD);
899
900 return (0);
901 }
902
903 /*
904 * Initialize a jumbo receive ring descriptor. This allocates
905 * a jumbo buffer from the pool managed internally by the driver.
906 */
907 static int
908 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
909 {
910 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
911 struct bge_extrx_bd *r;
912 struct mbuf *m_new = NULL;
913 int nsegs;
914 int error;
915
916 if (m == NULL) {
917 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
918 if (m_new == NULL)
919 return (ENOBUFS);
920
921 m_cljget(m_new, M_DONTWAIT, MJUM9BYTES);
922 if (!(m_new->m_flags & M_EXT)) {
923 m_freem(m_new);
924 return (ENOBUFS);
925 }
926 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES;
927 } else {
928 m_new = m;
929 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES;
930 m_new->m_data = m_new->m_ext.ext_buf;
931 }
932
933 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
934 m_adj(m_new, ETHER_ALIGN);
935
936 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
937 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
938 m_new, segs, &nsegs, BUS_DMA_NOWAIT);
939 if (error) {
940 if (m == NULL)
941 m_freem(m_new);
942 return (error);
943 }
944 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
945
946 /*
947 * Fill in the extended RX buffer descriptor.
948 */
949 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
950 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
951 r->bge_idx = i;
952 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
953 switch (nsegs) {
954 case 4:
955 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
956 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
957 r->bge_len3 = segs[3].ds_len;
958 case 3:
959 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
960 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
961 r->bge_len2 = segs[2].ds_len;
962 case 2:
963 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
964 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
965 r->bge_len1 = segs[1].ds_len;
966 case 1:
967 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
968 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
969 r->bge_len0 = segs[0].ds_len;
970 break;
971 default:
972 panic("%s: %d segments\n", __func__, nsegs);
973 }
974
975 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
976 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
977 BUS_DMASYNC_PREREAD);
978
979 return (0);
980 }
981
982 /*
983 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
984 * that's 1MB or memory, which is a lot. For now, we fill only the first
985 * 256 ring entries and hope that our CPU is fast enough to keep up with
986 * the NIC.
987 */
988 static int
989 bge_init_rx_ring_std(struct bge_softc *sc)
990 {
991 int i;
992
993 for (i = 0; i < BGE_SSLOTS; i++) {
994 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
995 return (ENOBUFS);
996 };
997
998 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
999 sc->bge_cdata.bge_rx_std_ring_map,
1000 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1001
1002 sc->bge_std = i - 1;
1003 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1004
1005 return (0);
1006 }
1007
1008 static void
1009 bge_free_rx_ring_std(struct bge_softc *sc)
1010 {
1011 int i;
1012
1013 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1014 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1015 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
1016 sc->bge_cdata.bge_rx_std_dmamap[i],
1017 BUS_DMASYNC_POSTREAD);
1018 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1019 sc->bge_cdata.bge_rx_std_dmamap[i]);
1020 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1021 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1022 }
1023 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1024 sizeof(struct bge_rx_bd));
1025 }
1026 }
1027
1028 static int
1029 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1030 {
1031 struct bge_rcb *rcb;
1032 int i;
1033
1034 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1035 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1036 return (ENOBUFS);
1037 };
1038
1039 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1040 sc->bge_cdata.bge_rx_jumbo_ring_map,
1041 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1042
1043 sc->bge_jumbo = i - 1;
1044
1045 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1046 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1047 BGE_RCB_FLAG_USE_EXT_RX_BD);
1048 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1049
1050 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1051
1052 return (0);
1053 }
1054
1055 static void
1056 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1057 {
1058 int i;
1059
1060 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1061 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1062 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1063 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1064 BUS_DMASYNC_POSTREAD);
1065 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1066 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1067 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1068 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1069 }
1070 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1071 sizeof(struct bge_extrx_bd));
1072 }
1073 }
1074
1075 static void
1076 bge_free_tx_ring(struct bge_softc *sc)
1077 {
1078 int i;
1079
1080 if (sc->bge_ldata.bge_tx_ring == NULL)
1081 return;
1082
1083 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1084 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1085 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
1086 sc->bge_cdata.bge_tx_dmamap[i],
1087 BUS_DMASYNC_POSTWRITE);
1088 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1089 sc->bge_cdata.bge_tx_dmamap[i]);
1090 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1091 sc->bge_cdata.bge_tx_chain[i] = NULL;
1092 }
1093 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1094 sizeof(struct bge_tx_bd));
1095 }
1096 }
1097
1098 static int
1099 bge_init_tx_ring(struct bge_softc *sc)
1100 {
1101 sc->bge_txcnt = 0;
1102 sc->bge_tx_saved_considx = 0;
1103
1104 /* Initialize transmit producer index for host-memory send ring. */
1105 sc->bge_tx_prodidx = 0;
1106 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1107
1108 /* 5700 b2 errata */
1109 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1110 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1111
1112 /* NIC-memory send ring not used; initialize to zero. */
1113 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1114 /* 5700 b2 errata */
1115 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1116 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1117
1118 return (0);
1119 }
1120
1121 static void
1122 bge_setpromisc(struct bge_softc *sc)
1123 {
1124 struct ifnet *ifp;
1125
1126 BGE_LOCK_ASSERT(sc);
1127
1128 ifp = sc->bge_ifp;
1129
1130 /* Enable or disable promiscuous mode as needed. */
1131 if (ifp->if_flags & IFF_PROMISC)
1132 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1133 else
1134 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1135 }
1136
1137 static void
1138 bge_setmulti(struct bge_softc *sc)
1139 {
1140 struct ifnet *ifp;
1141 struct ifmultiaddr *ifma;
1142 uint32_t hashes[4] = { 0, 0, 0, 0 };
1143 int h, i;
1144
1145 BGE_LOCK_ASSERT(sc);
1146
1147 ifp = sc->bge_ifp;
1148
1149 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1150 for (i = 0; i < 4; i++)
1151 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1152 return;
1153 }
1154
1155 /* First, zot all the existing filters. */
1156 for (i = 0; i < 4; i++)
1157 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1158
1159 /* Now program new ones. */
1160 IF_ADDR_LOCK(ifp);
1161 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1162 if (ifma->ifma_addr->sa_family != AF_LINK)
1163 continue;
1164 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1165 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1166 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1167 }
1168 IF_ADDR_UNLOCK(ifp);
1169
1170 for (i = 0; i < 4; i++)
1171 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1172 }
1173
1174 static void
1175 bge_setvlan(struct bge_softc *sc)
1176 {
1177 struct ifnet *ifp;
1178
1179 BGE_LOCK_ASSERT(sc);
1180
1181 ifp = sc->bge_ifp;
1182
1183 /* Enable or disable VLAN tag stripping as needed. */
1184 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1185 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1186 else
1187 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1188 }
1189
1190 static void
1191 bge_sig_pre_reset(sc, type)
1192 struct bge_softc *sc;
1193 int type;
1194 {
1195 /*
1196 * Some chips don't like this so only do this if ASF is enabled
1197 */
1198 if (sc->bge_asf_mode)
1199 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1200
1201 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1202 switch (type) {
1203 case BGE_RESET_START:
1204 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1205 break;
1206 case BGE_RESET_STOP:
1207 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1208 break;
1209 }
1210 }
1211 }
1212
1213 static void
1214 bge_sig_post_reset(sc, type)
1215 struct bge_softc *sc;
1216 int type;
1217 {
1218 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1219 switch (type) {
1220 case BGE_RESET_START:
1221 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1222 /* START DONE */
1223 break;
1224 case BGE_RESET_STOP:
1225 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1226 break;
1227 }
1228 }
1229 }
1230
1231 static void
1232 bge_sig_legacy(sc, type)
1233 struct bge_softc *sc;
1234 int type;
1235 {
1236 if (sc->bge_asf_mode) {
1237 switch (type) {
1238 case BGE_RESET_START:
1239 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1240 break;
1241 case BGE_RESET_STOP:
1242 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1243 break;
1244 }
1245 }
1246 }
1247
1248 void bge_stop_fw(struct bge_softc *);
1249 void
1250 bge_stop_fw(sc)
1251 struct bge_softc *sc;
1252 {
1253 int i;
1254
1255 if (sc->bge_asf_mode) {
1256 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1257 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1258 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1259
1260 for (i = 0; i < 100; i++ ) {
1261 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1262 break;
1263 DELAY(10);
1264 }
1265 }
1266 }
1267
1268 /*
1269 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1270 * self-test results.
1271 */
1272 static int
1273 bge_chipinit(struct bge_softc *sc)
1274 {
1275 uint32_t dma_rw_ctl;
1276 int i;
1277
1278 /* Set endianness before we access any non-PCI registers. */
1279 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1280
1281 /*
1282 * Check the 'ROM failed' bit on the RX CPU to see if
1283 * self-tests passed. Skip this check when there's no
1284 * chip containing the Ethernet address fitted, since
1285 * in that case it will always fail.
1286 */
1287 if ((sc->bge_flags & BGE_FLAG_EADDR) &&
1288 CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1289 device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n");
1290 return (ENODEV);
1291 }
1292
1293 /* Clear the MAC control register */
1294 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1295
1296 /*
1297 * Clear the MAC statistics block in the NIC's
1298 * internal memory.
1299 */
1300 for (i = BGE_STATS_BLOCK;
1301 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1302 BGE_MEMWIN_WRITE(sc, i, 0);
1303
1304 for (i = BGE_STATUS_BLOCK;
1305 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1306 BGE_MEMWIN_WRITE(sc, i, 0);
1307
1308 /*
1309 * Set up the PCI DMA control register.
1310 */
1311 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1312 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1313 if (sc->bge_flags & BGE_FLAG_PCIE) {
1314 /* Read watermark not used, 128 bytes for write. */
1315 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1316 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1317 if (BGE_IS_5714_FAMILY(sc)) {
1318 /* 256 bytes for read and write. */
1319 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1320 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1321 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1322 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1323 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1324 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1325 /* 1536 bytes for read, 384 bytes for write. */
1326 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1327 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1328 } else {
1329 /* 384 bytes for read and write. */
1330 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1331 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1332 0x0F;
1333 }
1334 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1335 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1336 uint32_t tmp;
1337
1338 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1339 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1340 if (tmp == 6 || tmp == 7)
1341 dma_rw_ctl |=
1342 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1343
1344 /* Set PCI-X DMA write workaround. */
1345 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1346 }
1347 } else {
1348 /* Conventional PCI bus: 256 bytes for read and write. */
1349 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1350 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1351
1352 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1353 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1354 dma_rw_ctl |= 0x0F;
1355 }
1356 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1357 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1358 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1359 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1360 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1361 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1362 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1363 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1364
1365 /*
1366 * Set up general mode register.
1367 */
1368 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1369 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1370 BGE_MODECTL_TX_NO_PHDR_CSUM);
1371
1372 /*
1373 * BCM5701 B5 have a bug causing data corruption when using
1374 * 64-bit DMA reads, which can be terminated early and then
1375 * completed later as 32-bit accesses, in combination with
1376 * certain bridges.
1377 */
1378 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1379 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1380 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1381
1382 /*
1383 * Tell the firmware the driver is running
1384 */
1385 if (sc->bge_asf_mode & ASF_STACKUP)
1386 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1387
1388 /*
1389 * Disable memory write invalidate. Apparently it is not supported
1390 * properly by these devices.
1391 */
1392 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1393
1394 /* Set the timer prescaler (always 66Mhz) */
1395 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1396
1397 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1398 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1399 DELAY(40); /* XXX */
1400
1401 /* Put PHY into ready state */
1402 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1403 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1404 DELAY(40);
1405 }
1406
1407 return (0);
1408 }
1409
1410 static int
1411 bge_blockinit(struct bge_softc *sc)
1412 {
1413 struct bge_rcb *rcb;
1414 bus_size_t vrcb;
1415 bge_hostaddr taddr;
1416 uint32_t val;
1417 int i;
1418
1419 /*
1420 * Initialize the memory window pointer register so that
1421 * we can access the first 32K of internal NIC RAM. This will
1422 * allow us to set up the TX send ring RCBs and the RX return
1423 * ring RCBs, plus other things which live in NIC memory.
1424 */
1425 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1426
1427 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1428
1429 if (!(BGE_IS_5705_PLUS(sc))) {
1430 /* Configure mbuf memory pool */
1431 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1432 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1433 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1434 else
1435 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1436
1437 /* Configure DMA resource pool */
1438 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1439 BGE_DMA_DESCRIPTORS);
1440 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1441 }
1442
1443 /* Configure mbuf pool watermarks */
1444 if (!BGE_IS_5705_PLUS(sc)) {
1445 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1446 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1447 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1448 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1449 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1450 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1451 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1452 } else {
1453 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1454 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1455 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1456 }
1457
1458 /* Configure DMA resource watermarks */
1459 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1460 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1461
1462 /* Enable buffer manager */
1463 if (!(BGE_IS_5705_PLUS(sc))) {
1464 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1465 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1466
1467 /* Poll for buffer manager start indication */
1468 for (i = 0; i < BGE_TIMEOUT; i++) {
1469 DELAY(10);
1470 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1471 break;
1472 }
1473
1474 if (i == BGE_TIMEOUT) {
1475 device_printf(sc->bge_dev,
1476 "buffer manager failed to start\n");
1477 return (ENXIO);
1478 }
1479 }
1480
1481 /* Enable flow-through queues */
1482 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1483 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1484
1485 /* Wait until queue initialization is complete */
1486 for (i = 0; i < BGE_TIMEOUT; i++) {
1487 DELAY(10);
1488 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1489 break;
1490 }
1491
1492 if (i == BGE_TIMEOUT) {
1493 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1494 return (ENXIO);
1495 }
1496
1497 /* Initialize the standard RX ring control block */
1498 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1499 rcb->bge_hostaddr.bge_addr_lo =
1500 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1501 rcb->bge_hostaddr.bge_addr_hi =
1502 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1503 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1504 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1505 if (BGE_IS_5705_PLUS(sc))
1506 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1507 else
1508 rcb->bge_maxlen_flags =
1509 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1510 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1511 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1512 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1513
1514 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1515 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1516
1517 /*
1518 * Initialize the jumbo RX ring control block
1519 * We set the 'ring disabled' bit in the flags
1520 * field until we're actually ready to start
1521 * using this ring (i.e. once we set the MTU
1522 * high enough to require it).
1523 */
1524 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1525 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1526
1527 rcb->bge_hostaddr.bge_addr_lo =
1528 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1529 rcb->bge_hostaddr.bge_addr_hi =
1530 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1531 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1532 sc->bge_cdata.bge_rx_jumbo_ring_map,
1533 BUS_DMASYNC_PREREAD);
1534 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1535 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1536 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1537 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1538 rcb->bge_hostaddr.bge_addr_hi);
1539 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1540 rcb->bge_hostaddr.bge_addr_lo);
1541
1542 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1543 rcb->bge_maxlen_flags);
1544 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1545
1546 /* Set up dummy disabled mini ring RCB */
1547 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1548 rcb->bge_maxlen_flags =
1549 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1550 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1551 rcb->bge_maxlen_flags);
1552 }
1553
1554 /*
1555 * Set the BD ring replentish thresholds. The recommended
1556 * values are 1/8th the number of descriptors allocated to
1557 * each ring.
1558 * XXX The 5754 requires a lower threshold, so it might be a
1559 * requirement of all 575x family chips. The Linux driver sets
1560 * the lower threshold for all 5705 family chips as well, but there
1561 * are reports that it might not need to be so strict.
1562 *
1563 * XXX Linux does some extra fiddling here for the 5906 parts as
1564 * well.
1565 */
1566 if (BGE_IS_5705_PLUS(sc))
1567 val = 8;
1568 else
1569 val = BGE_STD_RX_RING_CNT / 8;
1570 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1571 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1572
1573 /*
1574 * Disable all unused send rings by setting the 'ring disabled'
1575 * bit in the flags field of all the TX send ring control blocks.
1576 * These are located in NIC memory.
1577 */
1578 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1579 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1580 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1581 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1582 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1583 vrcb += sizeof(struct bge_rcb);
1584 }
1585
1586 /* Configure TX RCB 0 (we use only the first ring) */
1587 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1588 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1589 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1590 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1591 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1592 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1593 if (!(BGE_IS_5705_PLUS(sc)))
1594 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1595 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1596
1597 /* Disable all unused RX return rings */
1598 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1599 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1600 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1601 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1602 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1603 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1604 BGE_RCB_FLAG_RING_DISABLED));
1605 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1606 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1607 (i * (sizeof(uint64_t))), 0);
1608 vrcb += sizeof(struct bge_rcb);
1609 }
1610
1611 /* Initialize RX ring indexes */
1612 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1613 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1614 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1615
1616 /*
1617 * Set up RX return ring 0
1618 * Note that the NIC address for RX return rings is 0x00000000.
1619 * The return rings live entirely within the host, so the
1620 * nicaddr field in the RCB isn't used.
1621 */
1622 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1623 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1624 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1625 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1626 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1627 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1628 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1629
1630 /* Set random backoff seed for TX */
1631 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1632 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1633 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1634 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1635 BGE_TX_BACKOFF_SEED_MASK);
1636
1637 /* Set inter-packet gap */
1638 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1639
1640 /*
1641 * Specify which ring to use for packets that don't match
1642 * any RX rules.
1643 */
1644 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1645
1646 /*
1647 * Configure number of RX lists. One interrupt distribution
1648 * list, sixteen active lists, one bad frames class.
1649 */
1650 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1651
1652 /* Inialize RX list placement stats mask. */
1653 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1654 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1655
1656 /* Disable host coalescing until we get it set up */
1657 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1658
1659 /* Poll to make sure it's shut down. */
1660 for (i = 0; i < BGE_TIMEOUT; i++) {
1661 DELAY(10);
1662 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1663 break;
1664 }
1665
1666 if (i == BGE_TIMEOUT) {
1667 device_printf(sc->bge_dev,
1668 "host coalescing engine failed to idle\n");
1669 return (ENXIO);
1670 }
1671
1672 /* Set up host coalescing defaults */
1673 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1674 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1675 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1676 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1677 if (!(BGE_IS_5705_PLUS(sc))) {
1678 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1679 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1680 }
1681 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1682 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1683
1684 /* Set up address of statistics block */
1685 if (!(BGE_IS_5705_PLUS(sc))) {
1686 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1687 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1688 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1689 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1690 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1691 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1692 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1693 }
1694
1695 /* Set up address of status block */
1696 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1697 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1698 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1699 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1700 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1701 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1702
1703 /* Turn on host coalescing state machine */
1704 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1705
1706 /* Turn on RX BD completion state machine and enable attentions */
1707 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1708 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1709
1710 /* Turn on RX list placement state machine */
1711 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1712
1713 /* Turn on RX list selector state machine. */
1714 if (!(BGE_IS_5705_PLUS(sc)))
1715 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1716
1717 /* Turn on DMA, clear stats */
1718 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB |
1719 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR |
1720 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB |
1721 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB |
1722 ((sc->bge_flags & BGE_FLAG_TBI) ?
1723 BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1724
1725 /* Set misc. local control, enable interrupts on attentions */
1726 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1727
1728 #ifdef notdef
1729 /* Assert GPIO pins for PHY reset */
1730 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1731 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1732 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1733 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1734 #endif
1735
1736 /* Turn on DMA completion state machine */
1737 if (!(BGE_IS_5705_PLUS(sc)))
1738 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1739
1740 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1741
1742 /* Enable host coalescing bug fix. */
1743 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1744 sc->bge_asicrev == BGE_ASICREV_BCM5787)
1745 val |= 1 << 29;
1746
1747 /* Turn on write DMA state machine */
1748 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1749
1750 /* Turn on read DMA state machine */
1751 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1752 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS);
1753
1754 /* Turn on RX data completion state machine */
1755 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1756
1757 /* Turn on RX BD initiator state machine */
1758 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1759
1760 /* Turn on RX data and RX BD initiator state machine */
1761 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1762
1763 /* Turn on Mbuf cluster free state machine */
1764 if (!(BGE_IS_5705_PLUS(sc)))
1765 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1766
1767 /* Turn on send BD completion state machine */
1768 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1769
1770 /* Turn on send data completion state machine */
1771 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1772
1773 /* Turn on send data initiator state machine */
1774 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1775
1776 /* Turn on send BD initiator state machine */
1777 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1778
1779 /* Turn on send BD selector state machine */
1780 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1781
1782 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1783 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1784 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1785
1786 /* ack/clear link change events */
1787 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1788 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1789 BGE_MACSTAT_LINK_CHANGED);
1790 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1791
1792 /* Enable PHY auto polling (for MII/GMII only) */
1793 if (sc->bge_flags & BGE_FLAG_TBI) {
1794 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1795 } else {
1796 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1797 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1798 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1799 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1800 BGE_EVTENB_MI_INTERRUPT);
1801 }
1802
1803 /*
1804 * Clear any pending link state attention.
1805 * Otherwise some link state change events may be lost until attention
1806 * is cleared by bge_intr() -> bge_link_upd() sequence.
1807 * It's not necessary on newer BCM chips - perhaps enabling link
1808 * state change attentions implies clearing pending attention.
1809 */
1810 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1811 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1812 BGE_MACSTAT_LINK_CHANGED);
1813
1814 /* Enable link state change attentions. */
1815 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1816
1817 return (0);
1818 }
1819
1820 const struct bge_revision *
1821 bge_lookup_rev(uint32_t chipid)
1822 {
1823 const struct bge_revision *br;
1824
1825 for (br = bge_revisions; br->br_name != NULL; br++) {
1826 if (br->br_chipid == chipid)
1827 return (br);
1828 }
1829
1830 for (br = bge_majorrevs; br->br_name != NULL; br++) {
1831 if (br->br_chipid == BGE_ASICREV(chipid))
1832 return (br);
1833 }
1834
1835 return (NULL);
1836 }
1837
1838 const struct bge_vendor *
1839 bge_lookup_vendor(uint16_t vid)
1840 {
1841 const struct bge_vendor *v;
1842
1843 for (v = bge_vendors; v->v_name != NULL; v++)
1844 if (v->v_id == vid)
1845 return (v);
1846
1847 panic("%s: unknown vendor %d", __func__, vid);
1848 return (NULL);
1849 }
1850
1851 /*
1852 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1853 * against our list and return its name if we find a match.
1854 *
1855 * Note that since the Broadcom controller contains VPD support, we
1856 * try to get the device name string from the controller itself instead
1857 * of the compiled-in string. It guarantees we'll always announce the
1858 * right product name. We fall back to the compiled-in string when
1859 * VPD is unavailable or corrupt.
1860 */
1861 static int
1862 bge_probe(device_t dev)
1863 {
1864 struct bge_type *t = bge_devs;
1865 struct bge_softc *sc = device_get_softc(dev);
1866 uint16_t vid, did;
1867
1868 sc->bge_dev = dev;
1869 vid = pci_get_vendor(dev);
1870 did = pci_get_device(dev);
1871 while(t->bge_vid != 0) {
1872 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1873 char model[64], buf[96];
1874 const struct bge_revision *br;
1875 const struct bge_vendor *v;
1876 uint32_t id;
1877
1878 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1879 BGE_PCIMISCCTL_ASICREV;
1880 br = bge_lookup_rev(id);
1881 v = bge_lookup_vendor(vid);
1882 {
1883 #if __FreeBSD_version > 700024
1884 const char *pname;
1885
1886 if (pci_get_vpd_ident(dev, &pname) == 0)
1887 snprintf(model, 64, "%s", pname);
1888 else
1889 #endif
1890 snprintf(model, 64, "%s %s",
1891 v->v_name,
1892 br != NULL ? br->br_name :
1893 "NetXtreme Ethernet Controller");
1894 }
1895 snprintf(buf, 96, "%s, %sASIC rev. %#04x", model,
1896 br != NULL ? "" : "unknown ", id >> 16);
1897 device_set_desc_copy(dev, buf);
1898 if (pci_get_subvendor(dev) == DELL_VENDORID)
1899 sc->bge_flags |= BGE_FLAG_NO_3LED;
1900 if (did == BCOM_DEVICEID_BCM5755M)
1901 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1902 return (0);
1903 }
1904 t++;
1905 }
1906
1907 return (ENXIO);
1908 }
1909
1910 static void
1911 bge_dma_free(struct bge_softc *sc)
1912 {
1913 int i;
1914
1915 /* Destroy DMA maps for RX buffers. */
1916 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1917 if (sc->bge_cdata.bge_rx_std_dmamap[i])
1918 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
1919 sc->bge_cdata.bge_rx_std_dmamap[i]);
1920 }
1921
1922 /* Destroy DMA maps for jumbo RX buffers. */
1923 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1924 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
1925 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
1926 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1927 }
1928
1929 /* Destroy DMA maps for TX buffers. */
1930 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1931 if (sc->bge_cdata.bge_tx_dmamap[i])
1932 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
1933 sc->bge_cdata.bge_tx_dmamap[i]);
1934 }
1935
1936 if (sc->bge_cdata.bge_mtag)
1937 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
1938
1939
1940 /* Destroy standard RX ring. */
1941 if (sc->bge_cdata.bge_rx_std_ring_map)
1942 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
1943 sc->bge_cdata.bge_rx_std_ring_map);
1944 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
1945 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
1946 sc->bge_ldata.bge_rx_std_ring,
1947 sc->bge_cdata.bge_rx_std_ring_map);
1948
1949 if (sc->bge_cdata.bge_rx_std_ring_tag)
1950 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
1951
1952 /* Destroy jumbo RX ring. */
1953 if (sc->bge_cdata.bge_rx_jumbo_ring_map)
1954 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1955 sc->bge_cdata.bge_rx_jumbo_ring_map);
1956
1957 if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
1958 sc->bge_ldata.bge_rx_jumbo_ring)
1959 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1960 sc->bge_ldata.bge_rx_jumbo_ring,
1961 sc->bge_cdata.bge_rx_jumbo_ring_map);
1962
1963 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
1964 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
1965
1966 /* Destroy RX return ring. */
1967 if (sc->bge_cdata.bge_rx_return_ring_map)
1968 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
1969 sc->bge_cdata.bge_rx_return_ring_map);
1970
1971 if (sc->bge_cdata.bge_rx_return_ring_map &&
1972 sc->bge_ldata.bge_rx_return_ring)
1973 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
1974 sc->bge_ldata.bge_rx_return_ring,
1975 sc->bge_cdata.bge_rx_return_ring_map);
1976
1977 if (sc->bge_cdata.bge_rx_return_ring_tag)
1978 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
1979
1980 /* Destroy TX ring. */
1981 if (sc->bge_cdata.bge_tx_ring_map)
1982 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
1983 sc->bge_cdata.bge_tx_ring_map);
1984
1985 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
1986 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
1987 sc->bge_ldata.bge_tx_ring,
1988 sc->bge_cdata.bge_tx_ring_map);
1989
1990 if (sc->bge_cdata.bge_tx_ring_tag)
1991 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
1992
1993 /* Destroy status block. */
1994 if (sc->bge_cdata.bge_status_map)
1995 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
1996 sc->bge_cdata.bge_status_map);
1997
1998 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
1999 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2000 sc->bge_ldata.bge_status_block,
2001 sc->bge_cdata.bge_status_map);
2002
2003 if (sc->bge_cdata.bge_status_tag)
2004 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2005
2006 /* Destroy statistics block. */
2007 if (sc->bge_cdata.bge_stats_map)
2008 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2009 sc->bge_cdata.bge_stats_map);
2010
2011 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2012 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2013 sc->bge_ldata.bge_stats,
2014 sc->bge_cdata.bge_stats_map);
2015
2016 if (sc->bge_cdata.bge_stats_tag)
2017 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2018
2019 /* Destroy the parent tag. */
2020 if (sc->bge_cdata.bge_parent_tag)
2021 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2022 }
2023
2024 static int
2025 bge_dma_alloc(device_t dev)
2026 {
2027 struct bge_dmamap_arg ctx;
2028 struct bge_softc *sc;
2029 int i, error;
2030
2031 sc = device_get_softc(dev);
2032
2033 /*
2034 * Allocate the parent bus DMA tag appropriate for PCI.
2035 */
2036 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2037 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2038 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2039 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2040
2041 if (error != 0) {
2042 device_printf(sc->bge_dev,
2043 "could not allocate parent dma tag\n");
2044 return (ENOMEM);
2045 }
2046
2047 /*
2048 * Create tag for mbufs.
2049 */
2050 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
2051 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2052 NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES,
2053 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag);
2054
2055 if (error) {
2056 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2057 return (ENOMEM);
2058 }
2059
2060 /* Create DMA maps for RX buffers. */
2061 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2062 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
2063 &sc->bge_cdata.bge_rx_std_dmamap[i]);
2064 if (error) {
2065 device_printf(sc->bge_dev,
2066 "can't create DMA map for RX\n");
2067 return (ENOMEM);
2068 }
2069 }
2070
2071 /* Create DMA maps for TX buffers. */
2072 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2073 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
2074 &sc->bge_cdata.bge_tx_dmamap[i]);
2075 if (error) {
2076 device_printf(sc->bge_dev,
2077 "can't create DMA map for RX\n");
2078 return (ENOMEM);
2079 }
2080 }
2081
2082 /* Create tag for standard RX ring. */
2083 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2084 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2085 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
2086 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
2087
2088 if (error) {
2089 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2090 return (ENOMEM);
2091 }
2092
2093 /* Allocate DMA'able memory for standard RX ring. */
2094 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
2095 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
2096 &sc->bge_cdata.bge_rx_std_ring_map);
2097 if (error)
2098 return (ENOMEM);
2099
2100 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
2101
2102 /* Load the address of the standard RX ring. */
2103 ctx.bge_maxsegs = 1;
2104 ctx.sc = sc;
2105
2106 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
2107 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
2108 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2109
2110 if (error)
2111 return (ENOMEM);
2112
2113 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2114
2115 /* Create tags for jumbo mbufs. */
2116 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2117 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2118 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2119 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2120 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2121 if (error) {
2122 device_printf(sc->bge_dev,
2123 "could not allocate jumbo dma tag\n");
2124 return (ENOMEM);
2125 }
2126
2127 /* Create tag for jumbo RX ring. */
2128 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2129 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2130 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2131 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2132
2133 if (error) {
2134 device_printf(sc->bge_dev,
2135 "could not allocate jumbo ring dma tag\n");
2136 return (ENOMEM);
2137 }
2138
2139 /* Allocate DMA'able memory for jumbo RX ring. */
2140 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2141 (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2142 BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2143 &sc->bge_cdata.bge_rx_jumbo_ring_map);
2144 if (error)
2145 return (ENOMEM);
2146
2147 /* Load the address of the jumbo RX ring. */
2148 ctx.bge_maxsegs = 1;
2149 ctx.sc = sc;
2150
2151 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2152 sc->bge_cdata.bge_rx_jumbo_ring_map,
2153 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2154 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2155
2156 if (error)
2157 return (ENOMEM);
2158
2159 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2160
2161 /* Create DMA maps for jumbo RX buffers. */
2162 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2163 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2164 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2165 if (error) {
2166 device_printf(sc->bge_dev,
2167 "can't create DMA map for jumbo RX\n");
2168 return (ENOMEM);
2169 }
2170 }
2171
2172 }
2173
2174 /* Create tag for RX return ring. */
2175 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2176 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2177 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2178 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2179
2180 if (error) {
2181 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2182 return (ENOMEM);
2183 }
2184
2185 /* Allocate DMA'able memory for RX return ring. */
2186 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2187 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2188 &sc->bge_cdata.bge_rx_return_ring_map);
2189 if (error)
2190 return (ENOMEM);
2191
2192 bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2193 BGE_RX_RTN_RING_SZ(sc));
2194
2195 /* Load the address of the RX return ring. */
2196 ctx.bge_maxsegs = 1;
2197 ctx.sc = sc;
2198
2199 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2200 sc->bge_cdata.bge_rx_return_ring_map,
2201 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2202 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2203
2204 if (error)
2205 return (ENOMEM);
2206
2207 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2208
2209 /* Create tag for TX ring. */
2210 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2211 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2212 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2213 &sc->bge_cdata.bge_tx_ring_tag);
2214
2215 if (error) {
2216 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2217 return (ENOMEM);
2218 }
2219
2220 /* Allocate DMA'able memory for TX ring. */
2221 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2222 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2223 &sc->bge_cdata.bge_tx_ring_map);
2224 if (error)
2225 return (ENOMEM);
2226
2227 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2228
2229 /* Load the address of the TX ring. */
2230 ctx.bge_maxsegs = 1;
2231 ctx.sc = sc;
2232
2233 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2234 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2235 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2236
2237 if (error)
2238 return (ENOMEM);
2239
2240 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2241
2242 /* Create tag for status block. */
2243 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2244 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2245 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0,
2246 NULL, NULL, &sc->bge_cdata.bge_status_tag);
2247
2248 if (error) {
2249 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2250 return (ENOMEM);
2251 }
2252
2253 /* Allocate DMA'able memory for status block. */
2254 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2255 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2256 &sc->bge_cdata.bge_status_map);
2257 if (error)
2258 return (ENOMEM);
2259
2260 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2261
2262 /* Load the address of the status block. */
2263 ctx.sc = sc;
2264 ctx.bge_maxsegs = 1;
2265
2266 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2267 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2268 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2269
2270 if (error)
2271 return (ENOMEM);
2272
2273 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2274
2275 /* Create tag for statistics block. */
2276 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2277 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2278 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2279 &sc->bge_cdata.bge_stats_tag);
2280
2281 if (error) {
2282 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2283 return (ENOMEM);
2284 }
2285
2286 /* Allocate DMA'able memory for statistics block. */
2287 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2288 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2289 &sc->bge_cdata.bge_stats_map);
2290 if (error)
2291 return (ENOMEM);
2292
2293 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2294
2295 /* Load the address of the statstics block. */
2296 ctx.sc = sc;
2297 ctx.bge_maxsegs = 1;
2298
2299 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2300 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2301 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2302
2303 if (error)
2304 return (ENOMEM);
2305
2306 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2307
2308 return (0);
2309 }
2310
2311 #if __FreeBSD_version > 602105
2312 /*
2313 * Return true if this device has more than one port.
2314 */
2315 static int
2316 bge_has_multiple_ports(struct bge_softc *sc)
2317 {
2318 device_t dev = sc->bge_dev;
2319 u_int b, d, f, fscan, s;
2320
2321 d = pci_get_domain(dev);
2322 b = pci_get_bus(dev);
2323 s = pci_get_slot(dev);
2324 f = pci_get_function(dev);
2325 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2326 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2327 return (1);
2328 return (0);
2329 }
2330
2331 /*
2332 * Return true if MSI can be used with this device.
2333 */
2334 static int
2335 bge_can_use_msi(struct bge_softc *sc)
2336 {
2337 int can_use_msi = 0;
2338
2339 switch (sc->bge_asicrev) {
2340 case BGE_ASICREV_BCM5714:
2341 /*
2342 * Apparently, MSI doesn't work when this chip is configured
2343 * in single-port mode.
2344 */
2345 if (bge_has_multiple_ports(sc))
2346 can_use_msi = 1;
2347 break;
2348 case BGE_ASICREV_BCM5750:
2349 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2350 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2351 can_use_msi = 1;
2352 break;
2353 case BGE_ASICREV_BCM5752:
2354 case BGE_ASICREV_BCM5780:
2355 can_use_msi = 1;
2356 break;
2357 }
2358 return (can_use_msi);
2359 }
2360 #endif
2361
2362 static int
2363 bge_attach(device_t dev)
2364 {
2365 struct ifnet *ifp;
2366 struct bge_softc *sc;
2367 uint32_t hwcfg = 0, misccfg;
2368 u_char eaddr[ETHER_ADDR_LEN];
2369 int error, reg, rid, trys;
2370
2371 sc = device_get_softc(dev);
2372 sc->bge_dev = dev;
2373
2374 /*
2375 * Map control/status registers.
2376 */
2377 pci_enable_busmaster(dev);
2378
2379 rid = BGE_PCI_BAR0;
2380 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2381 RF_ACTIVE | PCI_RF_DENSE);
2382
2383 if (sc->bge_res == NULL) {
2384 device_printf (sc->bge_dev, "couldn't map memory\n");
2385 error = ENXIO;
2386 goto fail;
2387 }
2388
2389 sc->bge_btag = rman_get_bustag(sc->bge_res);
2390 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
2391
2392 /* Save ASIC rev. */
2393
2394 sc->bge_chipid =
2395 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
2396 BGE_PCIMISCCTL_ASICREV;
2397 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2398 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2399
2400 /*
2401 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2402 * 5705 A0 and A1 chips.
2403 */
2404 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2405 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2406 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2407 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2408 sc->bge_flags |= BGE_FLAG_WIRESPEED;
2409
2410 if (bge_has_eaddr(sc))
2411 sc->bge_flags |= BGE_FLAG_EADDR;
2412
2413 /* Save chipset family. */
2414 switch (sc->bge_asicrev) {
2415 case BGE_ASICREV_BCM5700:
2416 case BGE_ASICREV_BCM5701:
2417 case BGE_ASICREV_BCM5703:
2418 case BGE_ASICREV_BCM5704:
2419 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2420 break;
2421 case BGE_ASICREV_BCM5714_A0:
2422 case BGE_ASICREV_BCM5780:
2423 case BGE_ASICREV_BCM5714:
2424 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2425 /* FALLTHRU */
2426 case BGE_ASICREV_BCM5750:
2427 case BGE_ASICREV_BCM5752:
2428 case BGE_ASICREV_BCM5755:
2429 case BGE_ASICREV_BCM5787:
2430 case BGE_ASICREV_BCM5906:
2431 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2432 /* FALLTHRU */
2433 case BGE_ASICREV_BCM5705:
2434 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2435 break;
2436 }
2437
2438 /* Set various bug flags. */
2439 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2440 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2441 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2442 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2443 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2444 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2445 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2446 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2447 if (BGE_IS_5705_PLUS(sc) &&
2448 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2449 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2450 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2451 if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0)
2452 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2453 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
2454 sc->bge_flags |= BGE_FLAG_BER_BUG;
2455 }
2456
2457
2458 /*
2459 * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe()
2460 * but I do not know the DEVICEID for the 5788M.
2461 */
2462 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2463 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2464 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2465 sc->bge_flags |= BGE_FLAG_5788;
2466
2467 /*
2468 * Check if this is a PCI-X or PCI Express device.
2469 */
2470 #if __FreeBSD_version > 602101
2471 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
2472 /*
2473 * Found a PCI Express capabilities register, this
2474 * must be a PCI Express device.
2475 */
2476 if (reg != 0)
2477 sc->bge_flags |= BGE_FLAG_PCIE;
2478 #else
2479 if (BGE_IS_5705_PLUS(sc)) {
2480 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
2481 if ((reg & 0xFF) == BGE_PCIE_CAPID)
2482 sc->bge_flags |= BGE_FLAG_PCIE;
2483 #endif
2484 } else {
2485 /*
2486 * Check if the device is in PCI-X Mode.
2487 * (This bit is not valid on PCI Express controllers.)
2488 */
2489 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
2490 BGE_PCISTATE_PCI_BUSMODE) == 0)
2491 sc->bge_flags |= BGE_FLAG_PCIX;
2492 }
2493
2494 #if __FreeBSD_version > 602105
2495 {
2496 int msicount;
2497
2498 /*
2499 * Allocate the interrupt, using MSI if possible. These devices
2500 * support 8 MSI messages, but only the first one is used in
2501 * normal operation.
2502 */
2503 if (bge_can_use_msi(sc)) {
2504 msicount = pci_msi_count(dev);
2505 if (msicount > 1)
2506 msicount = 1;
2507 } else
2508 msicount = 0;
2509 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2510 rid = 1;
2511 sc->bge_flags |= BGE_FLAG_MSI;
2512 } else
2513 rid = 0;
2514 }
2515 #else
2516 rid = 0;
2517 #endif
2518
2519 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2520 RF_SHAREABLE | RF_ACTIVE);
2521
2522 if (sc->bge_irq == NULL) {
2523 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2524 error = ENXIO;
2525 goto fail;
2526 }
2527
2528 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2529
2530 /* Try to reset the chip. */
2531 if (bge_reset(sc)) {
2532 device_printf(sc->bge_dev, "chip reset failed\n");
2533 error = ENXIO;
2534 goto fail;
2535 }
2536
2537 sc->bge_asf_mode = 0;
2538 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2539 == BGE_MAGIC_NUMBER)) {
2540 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2541 & BGE_HWCFG_ASF) {
2542 sc->bge_asf_mode |= ASF_ENABLE;
2543 sc->bge_asf_mode |= ASF_STACKUP;
2544 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
2545 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2546 }
2547 }
2548 }
2549
2550 /* Try to reset the chip again the nice way. */
2551 bge_stop_fw(sc);
2552 bge_sig_pre_reset(sc, BGE_RESET_STOP);
2553 if (bge_reset(sc)) {
2554 device_printf(sc->bge_dev, "chip reset failed\n");
2555 error = ENXIO;
2556 goto fail;
2557 }
2558
2559 bge_sig_legacy(sc, BGE_RESET_STOP);
2560 bge_sig_post_reset(sc, BGE_RESET_STOP);
2561
2562 if (bge_chipinit(sc)) {
2563 device_printf(sc->bge_dev, "chip initialization failed\n");
2564 error = ENXIO;
2565 goto fail;
2566 }
2567
2568 error = bge_get_eaddr(sc, eaddr);
2569 if (error) {
2570 device_printf(sc->bge_dev,
2571 "failed to read station address\n");
2572 error = ENXIO;
2573 goto fail;
2574 }
2575
2576 /* 5705 limits RX return ring to 512 entries. */
2577 if (BGE_IS_5705_PLUS(sc))
2578 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2579 else
2580 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2581
2582 if (bge_dma_alloc(dev)) {
2583 device_printf(sc->bge_dev,
2584 "failed to allocate DMA resources\n");
2585 error = ENXIO;
2586 goto fail;
2587 }
2588
2589 /* Set default tuneable values. */
2590 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2591 sc->bge_rx_coal_ticks = 150;
2592 sc->bge_tx_coal_ticks = 150;
2593 sc->bge_rx_max_coal_bds = 10;
2594 sc->bge_tx_max_coal_bds = 10;
2595
2596 /* Set up ifnet structure */
2597 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2598 if (ifp == NULL) {
2599 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2600 error = ENXIO;
2601 goto fail;
2602 }
2603 ifp->if_softc = sc;
2604 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2605 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2606 ifp->if_ioctl = bge_ioctl;
2607 ifp->if_start = bge_start;
2608 ifp->if_init = bge_init;
2609 ifp->if_mtu = ETHERMTU;
2610 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2611 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2612 IFQ_SET_READY(&ifp->if_snd);
2613 ifp->if_hwassist = BGE_CSUM_FEATURES;
2614 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2615 IFCAP_VLAN_MTU;
2616 #ifdef IFCAP_VLAN_HWCSUM
2617 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2618 #endif
2619 ifp->if_capenable = ifp->if_capabilities;
2620 #ifdef DEVICE_POLLING
2621 ifp->if_capabilities |= IFCAP_POLLING;
2622 #endif
2623
2624 /*
2625 * 5700 B0 chips do not support checksumming correctly due
2626 * to hardware bugs.
2627 */
2628 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2629 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2630 ifp->if_capenable &= IFCAP_HWCSUM;
2631 ifp->if_hwassist = 0;
2632 }
2633
2634 /*
2635 * Figure out what sort of media we have by checking the
2636 * hardware config word in the first 32k of NIC internal memory,
2637 * or fall back to examining the EEPROM if necessary.
2638 * Note: on some BCM5700 cards, this value appears to be unset.
2639 * If that's the case, we have to rely on identifying the NIC
2640 * by its PCI subsystem ID, as we do below for the SysKonnect
2641 * SK-9D41.
2642 */
2643 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2644 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2645 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
2646 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2647 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2648 sizeof(hwcfg))) {
2649 device_printf(sc->bge_dev, "failed to read EEPROM\n");
2650 error = ENXIO;
2651 goto fail;
2652 }
2653 hwcfg = ntohl(hwcfg);
2654 }
2655
2656 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2657 sc->bge_flags |= BGE_FLAG_TBI;
2658
2659 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2660 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
2661 sc->bge_flags |= BGE_FLAG_TBI;
2662
2663 if (sc->bge_flags & BGE_FLAG_TBI) {
2664 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2665 bge_ifmedia_sts);
2666 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2667 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2668 0, NULL);
2669 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2670 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2671 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2672 } else {
2673 /*
2674 * Do transceiver setup and tell the firmware the
2675 * driver is down so we can try to get access the
2676 * probe if ASF is running. Retry a couple of times
2677 * if we get a conflict with the ASF firmware accessing
2678 * the PHY.
2679 */
2680 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2681 again:
2682 bge_asf_driver_up(sc);
2683
2684 trys = 0;
2685 if (mii_phy_probe(dev, &sc->bge_miibus,
2686 bge_ifmedia_upd, bge_ifmedia_sts)) {
2687 if (trys++ < 4) {
2688 device_printf(sc->bge_dev, "Try again\n");
2689 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2690 BMCR_RESET);
2691 goto again;
2692 }
2693
2694 device_printf(sc->bge_dev, "MII without any PHY!\n");
2695 error = ENXIO;
2696 goto fail;
2697 }
2698
2699 /*
2700 * Now tell the firmware we are going up after probing the PHY
2701 */
2702 if (sc->bge_asf_mode & ASF_STACKUP)
2703 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2704 }
2705
2706 /*
2707 * When using the BCM5701 in PCI-X mode, data corruption has
2708 * been observed in the first few bytes of some received packets.
2709 * Aligning the packet buffer in memory eliminates the corruption.
2710 * Unfortunately, this misaligns the packet payloads. On platforms
2711 * which do not support unaligned accesses, we will realign the
2712 * payloads by copying the received packets.
2713 */
2714 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2715 sc->bge_flags & BGE_FLAG_PCIX)
2716 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2717
2718 /*
2719 * Call MI attach routine.
2720 */
2721 ether_ifattach(ifp, eaddr);
2722 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2723
2724 /*
2725 * Hookup IRQ last.
2726 */
2727 #if __FreeBSD_version > 700030
2728 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2729 NULL, bge_intr, sc, &sc->bge_intrhand);
2730 #else
2731 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2732 bge_intr, sc, &sc->bge_intrhand);
2733 #endif
2734
2735 if (error) {
2736 bge_detach(dev);
2737 device_printf(sc->bge_dev, "couldn't set up irq\n");
2738 }
2739
2740 bge_add_sysctls(sc);
2741
2742 return (0);
2743
2744 fail:
2745 bge_release_resources(sc);
2746
2747 return (error);
2748 }
2749
2750 static int
2751 bge_detach(device_t dev)
2752 {
2753 struct bge_softc *sc;
2754 struct ifnet *ifp;
2755
2756 sc = device_get_softc(dev);
2757 ifp = sc->bge_ifp;
2758
2759 #ifdef DEVICE_POLLING
2760 if (ifp->if_capenable & IFCAP_POLLING)
2761 ether_poll_deregister(ifp);
2762 #endif
2763
2764 BGE_LOCK(sc);
2765 bge_stop(sc);
2766 bge_reset(sc);
2767 BGE_UNLOCK(sc);
2768
2769 callout_drain(&sc->bge_stat_ch);
2770
2771 ether_ifdetach(ifp);
2772
2773 if (sc->bge_flags & BGE_FLAG_TBI) {
2774 ifmedia_removeall(&sc->bge_ifmedia);
2775 } else {
2776 bus_generic_detach(dev);
2777 device_delete_child(dev, sc->bge_miibus);
2778 }
2779
2780 bge_release_resources(sc);
2781
2782 return (0);
2783 }
2784
2785 static void
2786 bge_release_resources(struct bge_softc *sc)
2787 {
2788 device_t dev;
2789
2790 dev = sc->bge_dev;
2791
2792 if (sc->bge_intrhand != NULL)
2793 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2794
2795 if (sc->bge_irq != NULL)
2796 bus_release_resource(dev, SYS_RES_IRQ,
2797 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
2798
2799 #if __FreeBSD_version > 602105
2800 if (sc->bge_flags & BGE_FLAG_MSI)
2801 pci_release_msi(dev);
2802 #endif
2803
2804 if (sc->bge_res != NULL)
2805 bus_release_resource(dev, SYS_RES_MEMORY,
2806 BGE_PCI_BAR0, sc->bge_res);
2807
2808 if (sc->bge_ifp != NULL)
2809 if_free(sc->bge_ifp);
2810
2811 bge_dma_free(sc);
2812
2813 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
2814 BGE_LOCK_DESTROY(sc);
2815 }
2816
2817 static int
2818 bge_reset(struct bge_softc *sc)
2819 {
2820 device_t dev;
2821 uint32_t cachesize, command, pcistate, reset, val;
2822 void (*write_op)(struct bge_softc *, int, int);
2823 int i;
2824
2825 dev = sc->bge_dev;
2826
2827 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2828 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2829 if (sc->bge_flags & BGE_FLAG_PCIE)
2830 write_op = bge_writemem_direct;
2831 else
2832 write_op = bge_writemem_ind;
2833 } else
2834 write_op = bge_writereg_ind;
2835
2836 /* Save some important PCI state. */
2837 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2838 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2839 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2840
2841 pci_write_config(dev, BGE_PCI_MISC_CTL,
2842 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
2843 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
2844
2845 /* Disable fastboot on controllers that support it. */
2846 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2847 sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2848 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2849 if (bootverbose)
2850 device_printf(sc->bge_dev, "Disabling fastboot\n");
2851 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2852 }
2853
2854 /*
2855 * Write the magic number to SRAM at offset 0xB50.
2856 * When firmware finishes its initialization it will
2857 * write ~BGE_MAGIC_NUMBER to the same location.
2858 */
2859 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2860
2861 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
2862
2863 /* XXX: Broadcom Linux driver. */
2864 if (sc->bge_flags & BGE_FLAG_PCIE) {
2865 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
2866 CSR_WRITE_4(sc, 0x7E2C, 0x20);
2867 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2868 /* Prevent PCIE link training during global reset */
2869 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
2870 reset |= 1 << 29;
2871 }
2872 }
2873
2874 /*
2875 * Set GPHY Power Down Override to leave GPHY
2876 * powered up in D0 uninitialized.
2877 */
2878 if (BGE_IS_5705_PLUS(sc))
2879 reset |= 0x04000000;
2880
2881 /* Issue global reset */
2882 write_op(sc, BGE_MISC_CFG, reset);
2883
2884 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2885 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2886 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2887 val | BGE_VCPU_STATUS_DRV_RESET);
2888 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2889 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2890 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2891 }
2892
2893 DELAY(1000);
2894
2895 /* XXX: Broadcom Linux driver. */
2896 if (sc->bge_flags & BGE_FLAG_PCIE) {
2897 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2898 DELAY(500000); /* wait for link training to complete */
2899 val = pci_read_config(dev, 0xC4, 4);
2900 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
2901 }
2902 /*
2903 * Set PCIE max payload size to 128 bytes and clear error
2904 * status.
2905 */
2906 pci_write_config(dev, 0xD8, 0xF5000, 4);
2907 }
2908
2909 /* Reset some of the PCI state that got zapped by reset. */
2910 pci_write_config(dev, BGE_PCI_MISC_CTL,
2911 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
2912 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
2913 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2914 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2915 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
2916
2917 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
2918 if (BGE_IS_5714_FAMILY(sc)) {
2919 /* This chip disables MSI on reset. */
2920 if (sc->bge_flags & BGE_FLAG_MSI) {
2921 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2);
2922 pci_write_config(dev, BGE_PCI_MSI_CTL,
2923 val | PCIM_MSICTRL_MSI_ENABLE, 2);
2924 val = CSR_READ_4(sc, BGE_MSI_MODE);
2925 CSR_WRITE_4(sc, BGE_MSI_MODE,
2926 val | BGE_MSIMODE_ENABLE);
2927 }
2928 val = CSR_READ_4(sc, BGE_MARB_MODE);
2929 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2930 } else
2931 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2932
2933 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2934 for (i = 0; i < BGE_TIMEOUT; i++) {
2935 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2936 if (val & BGE_VCPU_STATUS_INIT_DONE)
2937 break;
2938 DELAY(100);
2939 }
2940 if (i == BGE_TIMEOUT) {
2941 device_printf(sc->bge_dev, "reset timed out\n");
2942 return (1);
2943 }
2944 } else {
2945 /*
2946 * Poll until we see the 1's complement of the magic number.
2947 * This indicates that the firmware initialization is complete.
2948 * We expect this to fail if no chip containing the Ethernet
2949 * address is fitted though.
2950 */
2951 for (i = 0; i < BGE_TIMEOUT; i++) {
2952 DELAY(10);
2953 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2954 if (val == ~BGE_MAGIC_NUMBER)
2955 break;
2956 }
2957
2958 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
2959 device_printf(sc->bge_dev, "firmware handshake timed out, "
2960 "found 0x%08x\n", val);
2961 }
2962
2963 /*
2964 * XXX Wait for the value of the PCISTATE register to
2965 * return to its original pre-reset state. This is a
2966 * fairly good indicator of reset completion. If we don't
2967 * wait for the reset to fully complete, trying to read
2968 * from the device's non-PCI registers may yield garbage
2969 * results.
2970 */
2971 for (i = 0; i < BGE_TIMEOUT; i++) {
2972 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2973 break;
2974 DELAY(10);
2975 }
2976
2977 if (sc->bge_flags & BGE_FLAG_PCIE) {
2978 reset = bge_readmem_ind(sc, 0x7C00);
2979 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
2980 }
2981
2982 /* Fix up byte swapping. */
2983 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2984 BGE_MODECTL_BYTESWAP_DATA);
2985
2986 /* Tell the ASF firmware we are up */
2987 if (sc->bge_asf_mode & ASF_STACKUP)
2988 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2989
2990 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2991
2992 /*
2993 * The 5704 in TBI mode apparently needs some special
2994 * adjustment to insure the SERDES drive level is set
2995 * to 1.2V.
2996 */
2997 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2998 sc->bge_flags & BGE_FLAG_TBI) {
2999 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3000 val = (val & ~0xFFF) | 0x880;
3001 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3002 }
3003
3004 /* XXX: Broadcom Linux driver. */
3005 if (sc->bge_flags & BGE_FLAG_PCIE &&
3006 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3007 val = CSR_READ_4(sc, 0x7C00);
3008 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3009 }
3010 DELAY(10000);
3011
3012 return(0);
3013 }
3014
3015 /*
3016 * Frame reception handling. This is called if there's a frame
3017 * on the receive return list.
3018 *
3019 * Note: we have to be able to handle two possibilities here:
3020 * 1) the frame is from the jumbo receive ring
3021 * 2) the frame is from the standard receive ring
3022 */
3023
3024 static void
3025 bge_rxeof(struct bge_softc *sc)
3026 {
3027 struct ifnet *ifp;
3028 int stdcnt = 0, jumbocnt = 0;
3029
3030 BGE_LOCK_ASSERT(sc);
3031
3032 /* Nothing to do. */
3033 if (sc->bge_rx_saved_considx ==
3034 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
3035 return;
3036
3037 ifp = sc->bge_ifp;
3038
3039 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3040 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3041 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3042 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD);
3043 if (BGE_IS_JUMBO_CAPABLE(sc))
3044 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3045 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD);
3046
3047 while(sc->bge_rx_saved_considx !=
3048 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
3049 struct bge_rx_bd *cur_rx;
3050 uint32_t rxidx;
3051 struct mbuf *m = NULL;
3052 uint16_t vlan_tag = 0;
3053 int have_tag = 0;
3054
3055 #ifdef DEVICE_POLLING
3056 if (ifp->if_capenable & IFCAP_POLLING) {
3057 if (sc->rxcycles <= 0)
3058 break;
3059 sc->rxcycles--;
3060 }
3061 #endif
3062
3063 cur_rx =
3064 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
3065
3066 rxidx = cur_rx->bge_idx;
3067 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
3068
3069 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3070 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3071 have_tag = 1;
3072 vlan_tag = cur_rx->bge_vlan_tag;
3073 }
3074
3075 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3076 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3077 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
3078 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx],
3079 BUS_DMASYNC_POSTREAD);
3080 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
3081 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]);
3082 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3083 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
3084 jumbocnt++;
3085 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3086 ifp->if_ierrors++;
3087 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
3088 continue;
3089 }
3090 if (bge_newbuf_jumbo(sc,
3091 sc->bge_jumbo, NULL) == ENOBUFS) {
3092 ifp->if_ierrors++;
3093 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
3094 continue;
3095 }
3096 } else {
3097 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3098 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
3099 sc->bge_cdata.bge_rx_std_dmamap[rxidx],
3100 BUS_DMASYNC_POSTREAD);
3101 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
3102 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
3103 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3104 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
3105 stdcnt++;
3106 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3107 ifp->if_ierrors++;
3108 bge_newbuf_std(sc, sc->bge_std, m);
3109 continue;
3110 }
3111 if (bge_newbuf_std(sc, sc->bge_std,
3112 NULL) == ENOBUFS) {
3113 ifp->if_ierrors++;
3114 bge_newbuf_std(sc, sc->bge_std, m);
3115 continue;
3116 }
3117 }
3118
3119 ifp->if_ipackets++;
3120 #ifndef __NO_STRICT_ALIGNMENT
3121 /*
3122 * For architectures with strict alignment we must make sure
3123 * the payload is aligned.
3124 */
3125 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3126 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3127 cur_rx->bge_len);
3128 m->m_data += ETHER_ALIGN;
3129 }
3130 #endif
3131 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3132 m->m_pkthdr.rcvif = ifp;
3133
3134 if (ifp->if_capenable & IFCAP_RXCSUM) {
3135 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3136 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3137 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3138 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3139 }
3140 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3141 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3142 m->m_pkthdr.csum_data =
3143 cur_rx->bge_tcp_udp_csum;
3144 m->m_pkthdr.csum_flags |=
3145 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3146 }
3147 }
3148
3149 /*
3150 * If we received a packet with a vlan tag,
3151 * attach that information to the packet.
3152 */
3153 if (have_tag) {
3154 #if __FreeBSD_version > 700022
3155 m->m_pkthdr.ether_vtag = vlan_tag;
3156 m->m_flags |= M_VLANTAG;
3157 #else
3158 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3159 if (m == NULL)
3160 continue;
3161 #endif
3162 }
3163
3164 BGE_UNLOCK(sc);
3165 (*ifp->if_input)(ifp, m);
3166 BGE_LOCK(sc);
3167 }
3168
3169 if (stdcnt > 0)
3170 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3171 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3172
3173 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0)
3174 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3175 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3176
3177 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3178 if (stdcnt)
3179 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3180 if (jumbocnt)
3181 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3182 #ifdef notyet
3183 /*
3184 * This register wraps very quickly under heavy packet drops.
3185 * If you need correct statistics, you can enable this check.
3186 */
3187 if (BGE_IS_5705_PLUS(sc))
3188 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3189 #endif
3190 }
3191
3192 static void
3193 bge_txeof(struct bge_softc *sc)
3194 {
3195 struct bge_tx_bd *cur_tx = NULL;
3196 struct ifnet *ifp;
3197
3198 BGE_LOCK_ASSERT(sc);
3199
3200 /* Nothing to do. */
3201 if (sc->bge_tx_saved_considx ==
3202 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
3203 return;
3204
3205 ifp = sc->bge_ifp;
3206
3207 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3208 sc->bge_cdata.bge_tx_ring_map,
3209 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3210 /*
3211 * Go through our tx ring and free mbufs for those
3212 * frames that have been sent.
3213 */
3214 while (sc->bge_tx_saved_considx !=
3215 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
3216 uint32_t idx = 0;
3217
3218 idx = sc->bge_tx_saved_considx;
3219 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3220 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3221 ifp->if_opackets++;
3222 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3223 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
3224 sc->bge_cdata.bge_tx_dmamap[idx],
3225 BUS_DMASYNC_POSTWRITE);
3226 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
3227 sc->bge_cdata.bge_tx_dmamap[idx]);
3228 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3229 sc->bge_cdata.bge_tx_chain[idx] = NULL;
3230 }
3231 sc->bge_txcnt--;
3232 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3233 }
3234
3235 if (cur_tx != NULL)
3236 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3237 if (sc->bge_txcnt == 0)
3238 sc->bge_timer = 0;
3239 }
3240
3241 #ifdef DEVICE_POLLING
3242 static void
3243 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3244 {
3245 struct bge_softc *sc = ifp->if_softc;
3246 uint32_t statusword;
3247
3248 BGE_LOCK(sc);
3249 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3250 BGE_UNLOCK(sc);
3251 return;
3252 }
3253
3254 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3255 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
3256
3257 statusword = atomic_readandclear_32(
3258 &sc->bge_ldata.bge_status_block->bge_status);
3259
3260 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3261 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
3262
3263 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3264 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3265 sc->bge_link_evt++;
3266
3267 if (cmd == POLL_AND_CHECK_STATUS)
3268 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3269 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3270 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3271 bge_link_upd(sc);
3272
3273 sc->rxcycles = count;
3274 bge_rxeof(sc);
3275 bge_txeof(sc);
3276 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3277 bge_start_locked(ifp);
3278
3279 BGE_UNLOCK(sc);
3280 }
3281 #endif /* DEVICE_POLLING */
3282
3283 static void
3284 bge_intr(void *xsc)
3285 {
3286 struct bge_softc *sc;
3287 struct ifnet *ifp;
3288 uint32_t statusword;
3289
3290 sc = xsc;
3291
3292 BGE_LOCK(sc);
3293
3294 ifp = sc->bge_ifp;
3295
3296 #ifdef DEVICE_POLLING
3297 if (ifp->if_capenable & IFCAP_POLLING) {
3298 BGE_UNLOCK(sc);
3299 return;
3300 }
3301 #endif
3302
3303 /*
3304 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
3305 * disable interrupts by writing nonzero like we used to, since with
3306 * our current organization this just gives complications and
3307 * pessimizations for re-enabling interrupts. We used to have races
3308 * instead of the necessary complications. Disabling interrupts
3309 * would just reduce the chance of a status update while we are
3310 * running (by switching to the interrupt-mode coalescence
3311 * parameters), but this chance is already very low so it is more
3312 * efficient to get another interrupt than prevent it.
3313 *
3314 * We do the ack first to ensure another interrupt if there is a
3315 * status update after the ack. We don't check for the status
3316 * changing later because it is more efficient to get another
3317 * interrupt than prevent it, not quite as above (not checking is
3318 * a smaller optimization than not toggling the interrupt enable,
3319 * since checking doesn't involve PCI accesses and toggling require
3320 * the status check). So toggling would probably be a pessimization
3321 * even with MSI. It would only be needed for using a task queue.
3322 */
3323 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3324
3325 /*
3326 * Do the mandatory PCI flush as well as get the link status.
3327 */
3328 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3329
3330 /* Make sure the descriptor ring indexes are coherent. */
3331 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3332 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
3333 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3334 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
3335
3336 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3337 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3338 statusword || sc->bge_link_evt)
3339 bge_link_upd(sc);
3340
3341 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3342 /* Check RX return ring producer/consumer. */
3343 bge_rxeof(sc);
3344
3345 /* Check TX ring producer/consumer. */
3346 bge_txeof(sc);
3347 }
3348
3349 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3350 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3351 bge_start_locked(ifp);
3352
3353 BGE_UNLOCK(sc);
3354 }
3355
3356 static void
3357 bge_asf_driver_up(struct bge_softc *sc)
3358 {
3359 if (sc->bge_asf_mode & ASF_STACKUP) {
3360 /* Send ASF heartbeat aprox. every 2s */
3361 if (sc->bge_asf_count)
3362 sc->bge_asf_count --;
3363 else {
3364 sc->bge_asf_count = 5;
3365 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3366 BGE_FW_DRV_ALIVE);
3367 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3368 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3369 CSR_WRITE_4(sc, BGE_CPU_EVENT,
3370 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3371 }
3372 }
3373 }
3374
3375 static void
3376 bge_tick(void *xsc)
3377 {
3378 struct bge_softc *sc = xsc;
3379 struct mii_data *mii = NULL;
3380
3381 BGE_LOCK_ASSERT(sc);
3382
3383 /* Synchronize with possible callout reset/stop. */
3384 if (callout_pending(&sc->bge_stat_ch) ||
3385 !callout_active(&sc->bge_stat_ch))
3386 return;
3387
3388 if (BGE_IS_5705_PLUS(sc))
3389 bge_stats_update_regs(sc);
3390 else
3391 bge_stats_update(sc);
3392
3393 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3394 mii = device_get_softc(sc->bge_miibus);
3395 /*
3396 * Do not touch PHY if we have link up. This could break
3397 * IPMI/ASF mode or produce extra input errors
3398 * (extra errors was reported for bcm5701 & bcm5704).
3399 */
3400 if (!sc->bge_link)
3401 mii_tick(mii);
3402 } else {
3403 /*
3404 * Since in TBI mode auto-polling can't be used we should poll
3405 * link status manually. Here we register pending link event
3406 * and trigger interrupt.
3407 */
3408 #ifdef DEVICE_POLLING
3409 /* In polling mode we poll link state in bge_poll(). */
3410 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3411 #endif
3412 {
3413 sc->bge_link_evt++;
3414 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3415 sc->bge_flags & BGE_FLAG_5788)
3416 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3417 else
3418 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3419 }
3420 }
3421
3422 bge_asf_driver_up(sc);
3423 bge_watchdog(sc);
3424
3425 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3426 }
3427
3428 static void
3429 bge_stats_update_regs(struct bge_softc *sc)
3430 {
3431 struct ifnet *ifp;
3432
3433 ifp = sc->bge_ifp;
3434
3435 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3436 offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3437
3438 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3439 }
3440
3441 static void
3442 bge_stats_update(struct bge_softc *sc)
3443 {
3444 struct ifnet *ifp;
3445 bus_size_t stats;
3446 uint32_t cnt; /* current register value */
3447
3448 ifp = sc->bge_ifp;
3449
3450 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3451
3452 #define READ_STAT(sc, stats, stat) \
3453 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3454
3455 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3456 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3457 sc->bge_tx_collisions = cnt;
3458
3459 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3460 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3461 sc->bge_rx_discards = cnt;
3462
3463 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3464 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3465 sc->bge_tx_discards = cnt;
3466
3467 #undef READ_STAT
3468 }
3469
3470 /*
3471 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3472 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3473 * but when such padded frames employ the bge IP/TCP checksum offload,
3474 * the hardware checksum assist gives incorrect results (possibly
3475 * from incorporating its own padding into the UDP/TCP checksum; who knows).
3476 * If we pad such runts with zeros, the onboard checksum comes out correct.
3477 */
3478 static __inline int
3479 bge_cksum_pad(struct mbuf *m)
3480 {
3481 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3482 struct mbuf *last;
3483
3484 /* If there's only the packet-header and we can pad there, use it. */
3485 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3486 M_TRAILINGSPACE(m) >= padlen) {
3487 last = m;
3488 } else {
3489 /*
3490 * Walk packet chain to find last mbuf. We will either
3491 * pad there, or append a new mbuf and pad it.
3492 */
3493 for (last = m; last->m_next != NULL; last = last->m_next);
3494 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3495 /* Allocate new empty mbuf, pad it. Compact later. */
3496 struct mbuf *n;
3497
3498 MGET(n, M_DONTWAIT, MT_DATA);
3499 if (n == NULL)
3500 return (ENOBUFS);
3501 n->m_len = 0;
3502 last->m_next = n;
3503 last = n;
3504 }
3505 }
3506
3507 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3508 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3509 last->m_len += padlen;
3510 m->m_pkthdr.len += padlen;
3511
3512 return (0);
3513 }
3514
3515 /*
3516 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3517 * pointers to descriptors.
3518 */
3519 static int
3520 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3521 {
3522 bus_dma_segment_t segs[BGE_NSEG_NEW];
3523 bus_dmamap_t map;
3524 struct bge_tx_bd *d;
3525 struct mbuf *m = *m_head;
3526 uint32_t idx = *txidx;
3527 uint16_t csum_flags;
3528 int nsegs, i, error;
3529
3530 csum_flags = 0;
3531 if (m->m_pkthdr.csum_flags) {
3532 if (m->m_pkthdr.csum_flags & CSUM_IP)
3533 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3534 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3535 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3536 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3537 (error = bge_cksum_pad(m)) != 0) {
3538 m_freem(m);
3539 *m_head = NULL;
3540 return (error);
3541 }
3542 }
3543 if (m->m_flags & M_LASTFRAG)
3544 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3545 else if (m->m_flags & M_FRAG)
3546 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3547 }
3548
3549 map = sc->bge_cdata.bge_tx_dmamap[idx];
3550 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs,
3551 &nsegs, BUS_DMA_NOWAIT);
3552 if (error == EFBIG) {
3553 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
3554 if (m == NULL) {
3555 m_freem(*m_head);
3556 *m_head = NULL;
3557 return (ENOBUFS);
3558 }
3559 *m_head = m;
3560 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m,
3561 segs, &nsegs, BUS_DMA_NOWAIT);
3562 if (error) {
3563 m_freem(m);
3564 *m_head = NULL;
3565 return (error);
3566 }
3567 } else if (error != 0)
3568 return (error);
3569
3570 /*
3571 * Sanity check: avoid coming within 16 descriptors
3572 * of the end of the ring.
3573 */
3574 if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) {
3575 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
3576 return (ENOBUFS);
3577 }
3578
3579 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
3580
3581 for (i = 0; ; i++) {
3582 d = &sc->bge_ldata.bge_tx_ring[idx];
3583 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3584 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3585 d->bge_len = segs[i].ds_len;
3586 d->bge_flags = csum_flags;
3587 if (i == nsegs - 1)
3588 break;
3589 BGE_INC(idx, BGE_TX_RING_CNT);
3590 }
3591
3592 /* Mark the last segment as end of packet... */
3593 d->bge_flags |= BGE_TXBDFLAG_END;
3594
3595 /* ... and put VLAN tag into first segment. */
3596 d = &sc->bge_ldata.bge_tx_ring[*txidx];
3597 #if __FreeBSD_version > 700022
3598 if (m->m_flags & M_VLANTAG) {
3599 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3600 d->bge_vlan_tag = m->m_pkthdr.ether_vtag;
3601 } else
3602 d->bge_vlan_tag = 0;
3603 #else
3604 {
3605 struct m_tag *mtag;
3606
3607 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
3608 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3609 d->bge_vlan_tag = VLAN_TAG_VALUE(mtag);
3610 } else
3611 d->bge_vlan_tag = 0;
3612 }
3613 #endif
3614
3615 /*
3616 * Insure that the map for this transmission
3617 * is placed at the array index of the last descriptor
3618 * in this chain.
3619 */
3620 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3621 sc->bge_cdata.bge_tx_dmamap[idx] = map;
3622 sc->bge_cdata.bge_tx_chain[idx] = m;
3623 sc->bge_txcnt += nsegs;
3624
3625 BGE_INC(idx, BGE_TX_RING_CNT);
3626 *txidx = idx;
3627
3628 return (0);
3629 }
3630
3631 /*
3632 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3633 * to the mbuf data regions directly in the transmit descriptors.
3634 */
3635 static void
3636 bge_start_locked(struct ifnet *ifp)
3637 {
3638 struct bge_softc *sc;
3639 struct mbuf *m_head = NULL;
3640 uint32_t prodidx;
3641 int count = 0;
3642
3643 sc = ifp->if_softc;
3644
3645 if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3646 return;
3647
3648 prodidx = sc->bge_tx_prodidx;
3649
3650 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3651 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3652 if (m_head == NULL)
3653 break;
3654
3655 /*
3656 * XXX
3657 * The code inside the if() block is never reached since we
3658 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3659 * requests to checksum TCP/UDP in a fragmented packet.
3660 *
3661 * XXX
3662 * safety overkill. If this is a fragmented packet chain
3663 * with delayed TCP/UDP checksums, then only encapsulate
3664 * it if we have enough descriptors to handle the entire
3665 * chain at once.
3666 * (paranoia -- may not actually be needed)
3667 */
3668 if (m_head->m_flags & M_FIRSTFRAG &&
3669 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
3670 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3671 m_head->m_pkthdr.csum_data + 16) {
3672 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3673 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3674 break;
3675 }
3676 }
3677
3678 /*
3679 * Pack the data into the transmit ring. If we
3680 * don't have room, set the OACTIVE flag and wait
3681 * for the NIC to drain the ring.
3682 */
3683 if (bge_encap(sc, &m_head, &prodidx)) {
3684 if (m_head == NULL)
3685 break;
3686 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3687 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3688 break;
3689 }
3690 ++count;
3691
3692 /*
3693 * If there's a BPF listener, bounce a copy of this frame
3694 * to him.
3695 */
3696 #ifdef ETHER_BPF_MTAP
3697 ETHER_BPF_MTAP(ifp, m_head);
3698 #else
3699 BPF_MTAP(ifp, m_head);
3700 #endif
3701 }
3702
3703 if (count == 0)
3704 /* No packets were dequeued. */
3705 return;
3706
3707 /* Transmit. */
3708 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3709 /* 5700 b2 errata */
3710 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3711 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3712
3713 sc->bge_tx_prodidx = prodidx;
3714
3715 /*
3716 * Set a timeout in case the chip goes out to lunch.
3717 */
3718 sc->bge_timer = 5;
3719 }
3720
3721 /*
3722 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3723 * to the mbuf data regions directly in the transmit descriptors.
3724 */
3725 static void
3726 bge_start(struct ifnet *ifp)
3727 {
3728 struct bge_softc *sc;
3729
3730 sc = ifp->if_softc;
3731 BGE_LOCK(sc);
3732 bge_start_locked(ifp);
3733 BGE_UNLOCK(sc);
3734 }
3735
3736 static void
3737 bge_init_locked(struct bge_softc *sc)
3738 {
3739 struct ifnet *ifp;
3740 uint16_t *m;
3741
3742 BGE_LOCK_ASSERT(sc);
3743
3744 ifp = sc->bge_ifp;
3745
3746 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3747 return;
3748
3749 /* Cancel pending I/O and flush buffers. */
3750 bge_stop(sc);
3751
3752 bge_stop_fw(sc);
3753 bge_sig_pre_reset(sc, BGE_RESET_START);
3754 bge_reset(sc);
3755 bge_sig_legacy(sc, BGE_RESET_START);
3756 bge_sig_post_reset(sc, BGE_RESET_START);
3757
3758 bge_chipinit(sc);
3759
3760 /*
3761 * Init the various state machines, ring
3762 * control blocks and firmware.
3763 */
3764 if (bge_blockinit(sc)) {
3765 device_printf(sc->bge_dev, "initialization failure\n");
3766 return;
3767 }
3768
3769 ifp = sc->bge_ifp;
3770
3771 /* Specify MTU. */
3772 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3773 ETHER_HDR_LEN + ETHER_CRC_LEN +
3774 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
3775
3776 /* Load our MAC address. */
3777 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
3778 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3779 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3780
3781 /* Program promiscuous mode. */
3782 bge_setpromisc(sc);
3783
3784 /* Program multicast filter. */
3785 bge_setmulti(sc);
3786
3787 /* Program VLAN tag stripping. */
3788 bge_setvlan(sc);
3789
3790 /* Init RX ring. */
3791 bge_init_rx_ring_std(sc);
3792
3793 /*
3794 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3795 * memory to insure that the chip has in fact read the first
3796 * entry of the ring.
3797 */
3798 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3799 uint32_t v, i;
3800 for (i = 0; i < 10; i++) {
3801 DELAY(20);
3802 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3803 if (v == (MCLBYTES - ETHER_ALIGN))
3804 break;
3805 }
3806 if (i == 10)
3807 device_printf (sc->bge_dev,
3808 "5705 A0 chip failed to load RX ring\n");
3809 }
3810
3811 /* Init jumbo RX ring. */
3812 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3813 bge_init_rx_ring_jumbo(sc);
3814
3815 /* Init our RX return ring index. */
3816 sc->bge_rx_saved_considx = 0;
3817
3818 /* Init our RX/TX stat counters. */
3819 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
3820
3821 /* Init TX ring. */
3822 bge_init_tx_ring(sc);
3823
3824 /* Turn on transmitter. */
3825 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3826
3827 /* Turn on receiver. */
3828 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3829
3830 /* Tell firmware we're alive. */
3831 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3832
3833 #ifdef DEVICE_POLLING
3834 /* Disable interrupts if we are polling. */
3835 if (ifp->if_capenable & IFCAP_POLLING) {
3836 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
3837 BGE_PCIMISCCTL_MASK_PCI_INTR);
3838 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3839 } else
3840 #endif
3841
3842 /* Enable host interrupts. */
3843 {
3844 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3845 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3846 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3847 }
3848
3849 bge_ifmedia_upd_locked(ifp);
3850
3851 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3852 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3853
3854 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3855 }
3856
3857 static void
3858 bge_init(void *xsc)
3859 {
3860 struct bge_softc *sc = xsc;
3861
3862 BGE_LOCK(sc);
3863 bge_init_locked(sc);
3864 BGE_UNLOCK(sc);
3865 }
3866
3867 /*
3868 * Set media options.
3869 */
3870 static int
3871 bge_ifmedia_upd(struct ifnet *ifp)
3872 {
3873 struct bge_softc *sc = ifp->if_softc;
3874 int res;
3875
3876 BGE_LOCK(sc);
3877 res = bge_ifmedia_upd_locked(ifp);
3878 BGE_UNLOCK(sc);
3879
3880 return (res);
3881 }
3882
3883 static int
3884 bge_ifmedia_upd_locked(struct ifnet *ifp)
3885 {
3886 struct bge_softc *sc = ifp->if_softc;
3887 struct mii_data *mii;
3888 struct ifmedia *ifm;
3889
3890 BGE_LOCK_ASSERT(sc);
3891
3892 ifm = &sc->bge_ifmedia;
3893
3894 /* If this is a 1000baseX NIC, enable the TBI port. */
3895 if (sc->bge_flags & BGE_FLAG_TBI) {
3896 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3897 return (EINVAL);
3898 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3899 case IFM_AUTO:
3900 /*
3901 * The BCM5704 ASIC appears to have a special
3902 * mechanism for programming the autoneg
3903 * advertisement registers in TBI mode.
3904 */
3905 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3906 uint32_t sgdig;
3907 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
3908 if (sgdig & BGE_SGDIGSTS_DONE) {
3909 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3910 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3911 sgdig |= BGE_SGDIGCFG_AUTO |
3912 BGE_SGDIGCFG_PAUSE_CAP |
3913 BGE_SGDIGCFG_ASYM_PAUSE;
3914 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3915 sgdig | BGE_SGDIGCFG_SEND);
3916 DELAY(5);
3917 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3918 }
3919 }
3920 break;
3921 case IFM_1000_SX:
3922 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3923 BGE_CLRBIT(sc, BGE_MAC_MODE,
3924 BGE_MACMODE_HALF_DUPLEX);
3925 } else {
3926 BGE_SETBIT(sc, BGE_MAC_MODE,
3927 BGE_MACMODE_HALF_DUPLEX);
3928 }
3929 break;
3930 default:
3931 return (EINVAL);
3932 }
3933 return (0);
3934 }
3935
3936 sc->bge_link_evt++;
3937 mii = device_get_softc(sc->bge_miibus);
3938 if (mii->mii_instance) {
3939 struct mii_softc *miisc;
3940 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
3941 miisc = LIST_NEXT(miisc, mii_list))
3942 mii_phy_reset(miisc);
3943 }
3944 mii_mediachg(mii);
3945
3946 /*
3947 * Force an interrupt so that we will call bge_link_upd
3948 * if needed and clear any pending link state attention.
3949 * Without this we are not getting any further interrupts
3950 * for link state changes and thus will not UP the link and
3951 * not be able to send in bge_start_locked. The only
3952 * way to get things working was to receive a packet and
3953 * get an RX intr.
3954 * bge_tick should help for fiber cards and we might not
3955 * need to do this here if BGE_FLAG_TBI is set but as
3956 * we poll for fiber anyway it should not harm.
3957 */
3958 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3959 sc->bge_flags & BGE_FLAG_5788)
3960 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3961 else
3962 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3963
3964 return (0);
3965 }
3966
3967 /*
3968 * Report current media status.
3969 */
3970 static void
3971 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3972 {
3973 struct bge_softc *sc = ifp->if_softc;
3974 struct mii_data *mii;
3975
3976 BGE_LOCK(sc);
3977
3978 if (sc->bge_flags & BGE_FLAG_TBI) {
3979 ifmr->ifm_status = IFM_AVALID;
3980 ifmr->ifm_active = IFM_ETHER;
3981 if (CSR_READ_4(sc, BGE_MAC_STS) &
3982 BGE_MACSTAT_TBI_PCS_SYNCHED)
3983 ifmr->ifm_status |= IFM_ACTIVE;
3984 else {
3985 ifmr->ifm_active |= IFM_NONE;
3986 BGE_UNLOCK(sc);
3987 return;
3988 }
3989 ifmr->ifm_active |= IFM_1000_SX;
3990 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3991 ifmr->ifm_active |= IFM_HDX;
3992 else
3993 ifmr->ifm_active |= IFM_FDX;
3994 BGE_UNLOCK(sc);
3995 return;
3996 }
3997
3998 mii = device_get_softc(sc->bge_miibus);
3999 mii_pollstat(mii);
4000 ifmr->ifm_active = mii->mii_media_active;
4001 ifmr->ifm_status = mii->mii_media_status;
4002
4003 BGE_UNLOCK(sc);
4004 }
4005
4006 static int
4007 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4008 {
4009 struct bge_softc *sc = ifp->if_softc;
4010 struct ifreq *ifr = (struct ifreq *) data;
4011 struct mii_data *mii;
4012 int flags, mask, error = 0;
4013
4014 switch (command) {
4015 case SIOCSIFMTU:
4016 if (ifr->ifr_mtu < ETHERMIN ||
4017 ((BGE_IS_JUMBO_CAPABLE(sc)) &&
4018 ifr->ifr_mtu > BGE_JUMBO_MTU) ||
4019 ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
4020 ifr->ifr_mtu > ETHERMTU))
4021 error = EINVAL;
4022 else if (ifp->if_mtu != ifr->ifr_mtu) {
4023 ifp->if_mtu = ifr->ifr_mtu;
4024 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4025 bge_init(sc);
4026 }
4027 break;
4028 case SIOCSIFFLAGS:
4029 BGE_LOCK(sc);
4030 if (ifp->if_flags & IFF_UP) {
4031 /*
4032 * If only the state of the PROMISC flag changed,
4033 * then just use the 'set promisc mode' command
4034 * instead of reinitializing the entire NIC. Doing
4035 * a full re-init means reloading the firmware and
4036 * waiting for it to start up, which may take a
4037 * second or two. Similarly for ALLMULTI.
4038 */
4039 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4040 flags = ifp->if_flags ^ sc->bge_if_flags;
4041 if (flags & IFF_PROMISC)
4042 bge_setpromisc(sc);
4043 if (flags & IFF_ALLMULTI)
4044 bge_setmulti(sc);
4045 } else
4046 bge_init_locked(sc);
4047 } else {
4048 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4049 bge_stop(sc);
4050 }
4051 }
4052 sc->bge_if_flags = ifp->if_flags;
4053 BGE_UNLOCK(sc);
4054 error = 0;
4055 break;
4056 case SIOCADDMULTI:
4057 case SIOCDELMULTI:
4058 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4059 BGE_LOCK(sc);
4060 bge_setmulti(sc);
4061 BGE_UNLOCK(sc);
4062 error = 0;
4063 }
4064 break;
4065 case SIOCSIFMEDIA:
4066 case SIOCGIFMEDIA:
4067 if (sc->bge_flags & BGE_FLAG_TBI) {
4068 error = ifmedia_ioctl(ifp, ifr,
4069 &sc->bge_ifmedia, command);
4070 } else {
4071 mii = device_get_softc(sc->bge_miibus);
4072 error = ifmedia_ioctl(ifp, ifr,
4073 &mii->mii_media, command);
4074 }
4075 break;
4076 case SIOCSIFCAP:
4077 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4078 #ifdef DEVICE_POLLING
4079 if (mask & IFCAP_POLLING) {
4080 if (ifr->ifr_reqcap & IFCAP_POLLING) {
4081 error = ether_poll_register(bge_poll, ifp);
4082 if (error)
4083 return (error);
4084 BGE_LOCK(sc);
4085 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4086 BGE_PCIMISCCTL_MASK_PCI_INTR);
4087 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4088 ifp->if_capenable |= IFCAP_POLLING;
4089 BGE_UNLOCK(sc);
4090 } else {
4091 error = ether_poll_deregister(ifp);
4092 /* Enable interrupt even in error case */
4093 BGE_LOCK(sc);
4094 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
4095 BGE_PCIMISCCTL_MASK_PCI_INTR);
4096 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4097 ifp->if_capenable &= ~IFCAP_POLLING;
4098 BGE_UNLOCK(sc);
4099 }
4100 }
4101 #endif
4102 if (mask & IFCAP_HWCSUM) {
4103 ifp->if_capenable ^= IFCAP_HWCSUM;
4104 if (IFCAP_HWCSUM & ifp->if_capenable &&
4105 IFCAP_HWCSUM & ifp->if_capabilities)
4106 ifp->if_hwassist = BGE_CSUM_FEATURES;
4107 else
4108 ifp->if_hwassist = 0;
4109 #ifdef VLAN_CAPABILITIES
4110 VLAN_CAPABILITIES(ifp);
4111 #endif
4112 }
4113
4114 if (mask & IFCAP_VLAN_MTU) {
4115 ifp->if_capenable ^= IFCAP_VLAN_MTU;
4116 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4117 bge_init(sc);
4118 }
4119
4120 if (mask & IFCAP_VLAN_HWTAGGING) {
4121 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4122 BGE_LOCK(sc);
4123 bge_setvlan(sc);
4124 BGE_UNLOCK(sc);
4125 #ifdef VLAN_CAPABILITIES
4126 VLAN_CAPABILITIES(ifp);
4127 #endif
4128 }
4129
4130 break;
4131 default:
4132 error = ether_ioctl(ifp, command, data);
4133 break;
4134 }
4135
4136 return (error);
4137 }
4138
4139 static void
4140 bge_watchdog(struct bge_softc *sc)
4141 {
4142 struct ifnet *ifp;
4143
4144 BGE_LOCK_ASSERT(sc);
4145
4146 if (sc->bge_timer == 0 || --sc->bge_timer)
4147 return;
4148
4149 ifp = sc->bge_ifp;
4150
4151 if_printf(ifp, "watchdog timeout -- resetting\n");
4152
4153 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4154 bge_init_locked(sc);
4155
4156 ifp->if_oerrors++;
4157 }
4158
4159 /*
4160 * Stop the adapter and free any mbufs allocated to the
4161 * RX and TX lists.
4162 */
4163 static void
4164 bge_stop(struct bge_softc *sc)
4165 {
4166 struct ifnet *ifp;
4167 struct ifmedia_entry *ifm;
4168 struct mii_data *mii = NULL;
4169 int mtmp, itmp;
4170
4171 BGE_LOCK_ASSERT(sc);
4172
4173 ifp = sc->bge_ifp;
4174
4175 if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
4176 mii = device_get_softc(sc->bge_miibus);
4177
4178 callout_stop(&sc->bge_stat_ch);
4179
4180 /*
4181 * Disable all of the receiver blocks.
4182 */
4183 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4184 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4185 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4186 if (!(BGE_IS_5705_PLUS(sc)))
4187 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4188 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4189 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4190 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4191
4192 /*
4193 * Disable all of the transmit blocks.
4194 */
4195 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4196 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4197 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4198 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4199 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4200 if (!(BGE_IS_5705_PLUS(sc)))
4201 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4202 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4203
4204 /*
4205 * Shut down all of the memory managers and related
4206 * state machines.
4207 */
4208 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4209 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4210 if (!(BGE_IS_5705_PLUS(sc)))
4211 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4212 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4213 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4214 if (!(BGE_IS_5705_PLUS(sc))) {
4215 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4216 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4217 }
4218
4219 /* Disable host interrupts. */
4220 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4221 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4222
4223 /*
4224 * Tell firmware we're shutting down.
4225 */
4226
4227 bge_stop_fw(sc);
4228 bge_sig_pre_reset(sc, BGE_RESET_STOP);
4229 bge_reset(sc);
4230 bge_sig_legacy(sc, BGE_RESET_STOP);
4231 bge_sig_post_reset(sc, BGE_RESET_STOP);
4232
4233 /*
4234 * Keep the ASF firmware running if up.
4235 */
4236 if (sc->bge_asf_mode & ASF_STACKUP)
4237 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4238 else
4239 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4240
4241 /* Free the RX lists. */
4242 bge_free_rx_ring_std(sc);
4243
4244 /* Free jumbo RX list. */
4245 if (BGE_IS_JUMBO_CAPABLE(sc))
4246 bge_free_rx_ring_jumbo(sc);
4247
4248 /* Free TX buffers. */
4249 bge_free_tx_ring(sc);
4250
4251 /*
4252 * Isolate/power down the PHY, but leave the media selection
4253 * unchanged so that things will be put back to normal when
4254 * we bring the interface back up.
4255 */
4256 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4257 itmp = ifp->if_flags;
4258 ifp->if_flags |= IFF_UP;
4259 /*
4260 * If we are called from bge_detach(), mii is already NULL.
4261 */
4262 if (mii != NULL) {
4263 ifm = mii->mii_media.ifm_cur;
4264 mtmp = ifm->ifm_media;
4265 ifm->ifm_media = IFM_ETHER | IFM_NONE;
4266 mii_mediachg(mii);
4267 ifm->ifm_media = mtmp;
4268 }
4269 ifp->if_flags = itmp;
4270 }
4271
4272 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4273
4274 /* Clear MAC's link state (PHY may still have link UP). */
4275 if (bootverbose && sc->bge_link)
4276 if_printf(sc->bge_ifp, "link DOWN\n");
4277 sc->bge_link = 0;
4278
4279 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4280 }
4281
4282 /*
4283 * Stop all chip I/O so that the kernel's probe routines don't
4284 * get confused by errant DMAs when rebooting.
4285 */
4286 static void
4287 bge_shutdown(device_t dev)
4288 {
4289 struct bge_softc *sc;
4290
4291 sc = device_get_softc(dev);
4292
4293 BGE_LOCK(sc);
4294 bge_stop(sc);
4295 bge_reset(sc);
4296 BGE_UNLOCK(sc);
4297 }
4298
4299 static int
4300 bge_suspend(device_t dev)
4301 {
4302 struct bge_softc *sc;
4303
4304 sc = device_get_softc(dev);
4305 BGE_LOCK(sc);
4306 bge_stop(sc);
4307 BGE_UNLOCK(sc);
4308
4309 return (0);
4310 }
4311
4312 static int
4313 bge_resume(device_t dev)
4314 {
4315 struct bge_softc *sc;
4316 struct ifnet *ifp;
4317
4318 sc = device_get_softc(dev);
4319 BGE_LOCK(sc);
4320 ifp = sc->bge_ifp;
4321 if (ifp->if_flags & IFF_UP) {
4322 bge_init_locked(sc);
4323 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4324 bge_start_locked(ifp);
4325 }
4326 BGE_UNLOCK(sc);
4327
4328 return (0);
4329 }
4330
4331 static void
4332 bge_link_upd(struct bge_softc *sc)
4333 {
4334 struct mii_data *mii;
4335 uint32_t link, status;
4336
4337 BGE_LOCK_ASSERT(sc);
4338
4339 /* Clear 'pending link event' flag. */
4340 sc->bge_link_evt = 0;
4341
4342 /*
4343 * Process link state changes.
4344 * Grrr. The link status word in the status block does
4345 * not work correctly on the BCM5700 rev AX and BX chips,
4346 * according to all available information. Hence, we have
4347 * to enable MII interrupts in order to properly obtain
4348 * async link changes. Unfortunately, this also means that
4349 * we have to read the MAC status register to detect link
4350 * changes, thereby adding an additional register access to
4351 * the interrupt handler.
4352 *
4353 * XXX: perhaps link state detection procedure used for
4354 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4355 */
4356
4357 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4358 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4359 status = CSR_READ_4(sc, BGE_MAC_STS);
4360 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4361 mii = device_get_softc(sc->bge_miibus);
4362 mii_pollstat(mii);
4363 if (!sc->bge_link &&
4364 mii->mii_media_status & IFM_ACTIVE &&
4365 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4366 sc->bge_link++;
4367 if (bootverbose)
4368 if_printf(sc->bge_ifp, "link UP\n");
4369 } else if (sc->bge_link &&
4370 (!(mii->mii_media_status & IFM_ACTIVE) ||
4371 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4372 sc->bge_link = 0;
4373 if (bootverbose)
4374 if_printf(sc->bge_ifp, "link DOWN\n");
4375 }
4376
4377 /* Clear the interrupt. */
4378 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4379 BGE_EVTENB_MI_INTERRUPT);
4380 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4381 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4382 BRGPHY_INTRS);
4383 }
4384 return;
4385 }
4386
4387 if (sc->bge_flags & BGE_FLAG_TBI) {
4388 status = CSR_READ_4(sc, BGE_MAC_STS);
4389 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4390 if (!sc->bge_link) {
4391 sc->bge_link++;
4392 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4393 BGE_CLRBIT(sc, BGE_MAC_MODE,
4394 BGE_MACMODE_TBI_SEND_CFGS);
4395 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4396 if (bootverbose)
4397 if_printf(sc->bge_ifp, "link UP\n");
4398 if_link_state_change(sc->bge_ifp,
4399 LINK_STATE_UP);
4400 }
4401 } else if (sc->bge_link) {
4402 sc->bge_link = 0;
4403 if (bootverbose)
4404 if_printf(sc->bge_ifp, "link DOWN\n");
4405 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4406 }
4407 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4408 /*
4409 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4410 * in status word always set. Workaround this bug by reading
4411 * PHY link status directly.
4412 */
4413 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4414
4415 if (link != sc->bge_link ||
4416 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4417 mii = device_get_softc(sc->bge_miibus);
4418 mii_pollstat(mii);
4419 if (!sc->bge_link &&
4420 mii->mii_media_status & IFM_ACTIVE &&
4421 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4422 sc->bge_link++;
4423 if (bootverbose)
4424 if_printf(sc->bge_ifp, "link UP\n");
4425 } else if (sc->bge_link &&
4426 (!(mii->mii_media_status & IFM_ACTIVE) ||
4427 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4428 sc->bge_link = 0;
4429 if (bootverbose)
4430 if_printf(sc->bge_ifp, "link DOWN\n");
4431 }
4432 }
4433 } else {
4434 /*
4435 * Discard link events for MII/GMII controllers
4436 * if MI auto-polling is disabled.
4437 */
4438 }
4439
4440 /* Clear the attention. */
4441 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4442 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4443 BGE_MACSTAT_LINK_CHANGED);
4444 }
4445
4446 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4447 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4448 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4449 desc)
4450
4451 static void
4452 bge_add_sysctls(struct bge_softc *sc)
4453 {
4454 struct sysctl_ctx_list *ctx;
4455 struct sysctl_oid_list *children, *schildren;
4456 struct sysctl_oid *tree;
4457
4458 ctx = device_get_sysctl_ctx(sc->bge_dev);
4459 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4460
4461 #ifdef BGE_REGISTER_DEBUG
4462 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4463 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4464 "Debug Information");
4465
4466 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4467 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4468 "Register Read");
4469
4470 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4471 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4472 "Memory Read");
4473
4474 #endif
4475
4476 if (BGE_IS_5705_PLUS(sc))
4477 return;
4478
4479 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4480 NULL, "BGE Statistics");
4481 schildren = children = SYSCTL_CHILDREN(tree);
4482 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4483 children, COSFramesDroppedDueToFilters,
4484 "FramesDroppedDueToFilters");
4485 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4486 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4487 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4488 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4489 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4490 children, nicNoMoreRxBDs, "NoMoreRxBDs");
4491 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4492 children, ifInDiscards, "InputDiscards");
4493 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4494 children, ifInErrors, "InputErrors");
4495 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4496 children, nicRecvThresholdHit, "RecvThresholdHit");
4497 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4498 children, nicDmaReadQueueFull, "DmaReadQueueFull");
4499 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4500 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4501 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4502 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4503 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4504 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4505 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4506 children, nicRingStatusUpdate, "RingStatusUpdate");
4507 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4508 children, nicInterrupts, "Interrupts");
4509 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4510 children, nicAvoidedInterrupts, "AvoidedInterrupts");
4511 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4512 children, nicSendThresholdHit, "SendThresholdHit");
4513
4514 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
4515 NULL, "BGE RX Statistics");
4516 children = SYSCTL_CHILDREN(tree);
4517 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
4518 children, rxstats.ifHCInOctets, "Octets");
4519 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
4520 children, rxstats.etherStatsFragments, "Fragments");
4521 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
4522 children, rxstats.ifHCInUcastPkts, "UcastPkts");
4523 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
4524 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
4525 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
4526 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
4527 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
4528 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
4529 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
4530 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
4531 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
4532 children, rxstats.xoffPauseFramesReceived,
4533 "xoffPauseFramesReceived");
4534 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
4535 children, rxstats.macControlFramesReceived,
4536 "ControlFramesReceived");
4537 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
4538 children, rxstats.xoffStateEntered, "xoffStateEntered");
4539 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
4540 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
4541 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
4542 children, rxstats.etherStatsJabbers, "Jabbers");
4543 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
4544 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
4545 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
4546 children, rxstats.inRangeLengthError, "inRangeLengthError");
4547 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
4548 children, rxstats.outRangeLengthError, "outRangeLengthError");
4549
4550 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
4551 NULL, "BGE TX Statistics");
4552 children = SYSCTL_CHILDREN(tree);
4553 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
4554 children, txstats.ifHCOutOctets, "Octets");
4555 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
4556 children, txstats.etherStatsCollisions, "Collisions");
4557 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
4558 children, txstats.outXonSent, "XonSent");
4559 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
4560 children, txstats.outXoffSent, "XoffSent");
4561 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
4562 children, txstats.flowControlDone, "flowControlDone");
4563 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
4564 children, txstats.dot3StatsInternalMacTransmitErrors,
4565 "InternalMacTransmitErrors");
4566 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
4567 children, txstats.dot3StatsSingleCollisionFrames,
4568 "SingleCollisionFrames");
4569 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
4570 children, txstats.dot3StatsMultipleCollisionFrames,
4571 "MultipleCollisionFrames");
4572 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
4573 children, txstats.dot3StatsDeferredTransmissions,
4574 "DeferredTransmissions");
4575 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
4576 children, txstats.dot3StatsExcessiveCollisions,
4577 "ExcessiveCollisions");
4578 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
4579 children, txstats.dot3StatsLateCollisions,
4580 "LateCollisions");
4581 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
4582 children, txstats.ifHCOutUcastPkts, "UcastPkts");
4583 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
4584 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
4585 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
4586 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
4587 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
4588 children, txstats.dot3StatsCarrierSenseErrors,
4589 "CarrierSenseErrors");
4590 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
4591 children, txstats.ifOutDiscards, "Discards");
4592 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
4593 children, txstats.ifOutErrors, "Errors");
4594 }
4595
4596 static int
4597 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
4598 {
4599 struct bge_softc *sc;
4600 uint32_t result;
4601 int offset;
4602
4603 sc = (struct bge_softc *)arg1;
4604 offset = arg2;
4605 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
4606 offsetof(bge_hostaddr, bge_addr_lo));
4607 return (sysctl_handle_int(oidp, &result, 0, req));
4608 }
4609
4610 #ifdef BGE_REGISTER_DEBUG
4611 static int
4612 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4613 {
4614 struct bge_softc *sc;
4615 uint16_t *sbdata;
4616 int error;
4617 int result;
4618 int i, j;
4619
4620 result = -1;
4621 error = sysctl_handle_int(oidp, &result, 0, req);
4622 if (error || (req->newptr == NULL))
4623 return (error);
4624
4625 if (result == 1) {
4626 sc = (struct bge_softc *)arg1;
4627
4628 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
4629 printf("Status Block:\n");
4630 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
4631 printf("%06x:", i);
4632 for (j = 0; j < 8; j++) {
4633 printf(" %04x", sbdata[i]);
4634 i += 4;
4635 }
4636 printf("\n");
4637 }
4638
4639 printf("Registers:\n");
4640 for (i = 0x800; i < 0xA00; ) {
4641 printf("%06x:", i);
4642 for (j = 0; j < 8; j++) {
4643 printf(" %08x", CSR_READ_4(sc, i));
4644 i += 4;
4645 }
4646 printf("\n");
4647 }
4648
4649 printf("Hardware Flags:\n");
4650 if (BGE_IS_575X_PLUS(sc))
4651 printf(" - 575X Plus\n");
4652 if (BGE_IS_5705_PLUS(sc))
4653 printf(" - 5705 Plus\n");
4654 if (BGE_IS_5714_FAMILY(sc))
4655 printf(" - 5714 Family\n");
4656 if (BGE_IS_5700_FAMILY(sc))
4657 printf(" - 5700 Family\n");
4658 if (sc->bge_flags & BGE_FLAG_JUMBO)
4659 printf(" - Supports Jumbo Frames\n");
4660 if (sc->bge_flags & BGE_FLAG_PCIX)
4661 printf(" - PCI-X Bus\n");
4662 if (sc->bge_flags & BGE_FLAG_PCIE)
4663 printf(" - PCI Express Bus\n");
4664 if (sc->bge_flags & BGE_FLAG_NO_3LED)
4665 printf(" - No 3 LEDs\n");
4666 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
4667 printf(" - RX Alignment Bug\n");
4668 }
4669
4670 return (error);
4671 }
4672
4673 static int
4674 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
4675 {
4676 struct bge_softc *sc;
4677 int error;
4678 uint16_t result;
4679 uint32_t val;
4680
4681 result = -1;
4682 error = sysctl_handle_int(oidp, &result, 0, req);
4683 if (error || (req->newptr == NULL))
4684 return (error);
4685
4686 if (result < 0x8000) {
4687 sc = (struct bge_softc *)arg1;
4688 val = CSR_READ_4(sc, result);
4689 printf("reg 0x%06X = 0x%08X\n", result, val);
4690 }
4691
4692 return (error);
4693 }
4694
4695 static int
4696 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
4697 {
4698 struct bge_softc *sc;
4699 int error;
4700 uint16_t result;
4701 uint32_t val;
4702
4703 result = -1;
4704 error = sysctl_handle_int(oidp, &result, 0, req);
4705 if (error || (req->newptr == NULL))
4706 return (error);
4707
4708 if (result < 0x8000) {
4709 sc = (struct bge_softc *)arg1;
4710 val = bge_readmem_ind(sc, result);
4711 printf("mem 0x%06X = 0x%08X\n", result, val);
4712 }
4713
4714 return (error);
4715 }
4716 #endif
4717
4718 static int
4719 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
4720 {
4721
4722 if (sc->bge_flags & BGE_FLAG_EADDR)
4723 return (1);
4724
4725 #ifdef __sparc64__
4726 OF_getetheraddr(sc->bge_dev, ether_addr);
4727 return (0);
4728 #endif
4729 return (1);
4730 }
4731
4732 static int
4733 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4734 {
4735 uint32_t mac_addr;
4736
4737 mac_addr = bge_readmem_ind(sc, 0x0c14);
4738 if ((mac_addr >> 16) == 0x484b) {
4739 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4740 ether_addr[1] = (uint8_t)mac_addr;
4741 mac_addr = bge_readmem_ind(sc, 0x0c18);
4742 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4743 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4744 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4745 ether_addr[5] = (uint8_t)mac_addr;
4746 return (0);
4747 }
4748 return (1);
4749 }
4750
4751 static int
4752 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4753 {
4754 int mac_offset = BGE_EE_MAC_OFFSET;
4755
4756 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4757 mac_offset = BGE_EE_MAC_OFFSET_5906;
4758
4759 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
4760 ETHER_ADDR_LEN));
4761 }
4762
4763 static int
4764 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4765 {
4766
4767 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4768 return (1);
4769
4770 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4771 ETHER_ADDR_LEN));
4772 }
4773
4774 static int
4775 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4776 {
4777 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4778 /* NOTE: Order is critical */
4779 bge_get_eaddr_fw,
4780 bge_get_eaddr_mem,
4781 bge_get_eaddr_nvram,
4782 bge_get_eaddr_eeprom,
4783 NULL
4784 };
4785 const bge_eaddr_fcn_t *func;
4786
4787 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4788 if ((*func)(sc, eaddr) == 0)
4789 break;
4790 }
4791 return (*func == NULL ? ENXIO : 0);
4792 }
Cache object: 5069a19955542e3759934e88f7f61097
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