1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2001 Wind River Systems
5 * Copyright (c) 1997, 1998, 1999, 2001
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD$
36 */
37
38 /*
39 * BCM570x memory map. The internal memory layout varies somewhat
40 * depending on whether or not we have external SSRAM attached.
41 * The BCM5700 can have up to 16MB of external memory. The BCM5701
42 * is apparently not designed to use external SSRAM. The mappings
43 * up to the first 4 send rings are the same for both internal and
44 * external memory configurations. Note that mini RX ring space is
45 * only available with external SSRAM configurations, which means
46 * the mini RX ring is not supported on the BCM5701.
47 *
48 * The NIC's memory can be accessed by the host in one of 3 ways:
49 *
50 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
51 * registers in PCI config space can be used to read any 32-bit
52 * address within the NIC's memory.
53 *
54 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
55 * space can be used in conjunction with the memory window in the
56 * device register space at offset 0x8000 to read any 32K chunk
57 * of NIC memory.
58 *
59 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
60 * set, the device I/O mapping consumes 32MB of host address space,
61 * allowing all of the registers and internal NIC memory to be
62 * accessed directly. NIC memory addresses are offset by 0x01000000.
63 * Flat mode consumes so much host address space that it is not
64 * recommended.
65 */
66 #define BGE_PAGE_ZERO 0x00000000
67 #define BGE_PAGE_ZERO_END 0x000000FF
68 #define BGE_SEND_RING_RCB 0x00000100
69 #define BGE_SEND_RING_RCB_END 0x000001FF
70 #define BGE_RX_RETURN_RING_RCB 0x00000200
71 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
72 #define BGE_STATS_BLOCK 0x00000300
73 #define BGE_STATS_BLOCK_END 0x00000AFF
74 #define BGE_STATUS_BLOCK 0x00000B00
75 #define BGE_STATUS_BLOCK_END 0x00000B4F
76 #define BGE_SRAM_FW_MB 0x00000B50
77 #define BGE_SRAM_DATA_SIG 0x00000B54
78 #define BGE_SRAM_DATA_CFG 0x00000B58
79 #define BGE_SRAM_FW_CMD_MB 0x00000B78
80 #define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C
81 #define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80
82 #define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04
83 #define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14
84 #define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18
85 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
86 #define BGE_UNMAPPED 0x00001000
87 #define BGE_UNMAPPED_END 0x00001FFF
88 #define BGE_DMA_DESCRIPTORS 0x00002000
89 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF
90 #define BGE_SEND_RING_5717 0x00004000
91 #define BGE_SEND_RING_1_TO_4 0x00004000
92 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF
93
94 /* Firmware interface */
95 #define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */
96
97 #define BGE_FW_CMD_DRV_ALIVE 0x00000001
98 #define BGE_FW_CMD_PAUSE 0x00000002
99 #define BGE_FW_CMD_IPV4_ADDR_CHANGE 0x00000003
100 #define BGE_FW_CMD_IPV6_ADDR_CHANGE 0x00000004
101 #define BGE_FW_CMD_LINK_UPDATE 0x0000000C
102 #define BGE_FW_CMD_DRV_ALIVE2 0x0000000D
103 #define BGE_FW_CMD_DRV_ALIVE3 0x0000000E
104
105 #define BGE_FW_HB_TIMEOUT_SEC 3
106
107 #define BGE_FW_DRV_STATE_START 0x00000001
108 #define BGE_FW_DRV_STATE_START_DONE 0x80000001
109 #define BGE_FW_DRV_STATE_UNLOAD 0x00000002
110 #define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002
111 #define BGE_FW_DRV_STATE_WOL 0x00000003
112 #define BGE_FW_DRV_STATE_SUSPEND 0x00000004
113
114 /* Mappings for internal memory configuration */
115 #define BGE_STD_RX_RINGS 0x00006000
116 #define BGE_STD_RX_RINGS_END 0x00006FFF
117 #define BGE_JUMBO_RX_RINGS 0x00007000
118 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF
119 #define BGE_BUFFPOOL_1 0x00008000
120 #define BGE_BUFFPOOL_1_END 0x0000FFFF
121 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */
122 #define BGE_BUFFPOOL_2_END 0x00017FFF
123 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */
124 #define BGE_BUFFPOOL_3_END 0x0001FFFF
125 #define BGE_STD_RX_RINGS_5717 0x00040000
126 #define BGE_JUMBO_RX_RINGS_5717 0x00044400
127
128 /* Mappings for external SSRAM configurations */
129 #define BGE_SEND_RING_5_TO_6 0x00006000
130 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF
131 #define BGE_SEND_RING_7_TO_8 0x00007000
132 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF
133 #define BGE_SEND_RING_9_TO_16 0x00008000
134 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF
135 #define BGE_EXT_STD_RX_RINGS 0x0000C000
136 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF
137 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000
138 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF
139 #define BGE_MINI_RX_RINGS 0x0000E000
140 #define BGE_MINI_RX_RINGS_END 0x0000FFFF
141 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */
142 #define BGE_AVAIL_REGION1_END 0x00017FFF
143 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */
144 #define BGE_AVAIL_REGION2_END 0x0001FFFF
145 #define BGE_EXT_SSRAM 0x00020000
146 #define BGE_EXT_SSRAM_END 0x000FFFFF
147
148 /*
149 * BCM570x register offsets. These are memory mapped registers
150 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
151 * Each register must be accessed using 32 bit operations.
152 *
153 * All registers are accessed through a 32K shared memory block.
154 * The first group of registers are actually copies of the PCI
155 * configuration space registers.
156 */
157
158 /*
159 * PCI registers defined in the PCI 2.2 spec.
160 */
161 #define BGE_PCI_VID 0x00
162 #define BGE_PCI_DID 0x02
163 #define BGE_PCI_CMD 0x04
164 #define BGE_PCI_STS 0x06
165 #define BGE_PCI_REV 0x08
166 #define BGE_PCI_CLASS 0x09
167 #define BGE_PCI_CACHESZ 0x0C
168 #define BGE_PCI_LATTIMER 0x0D
169 #define BGE_PCI_HDRTYPE 0x0E
170 #define BGE_PCI_BIST 0x0F
171 #define BGE_PCI_BAR0 0x10
172 #define BGE_PCI_BAR1 0x14
173 #define BGE_PCI_SUBSYS 0x2C
174 #define BGE_PCI_SUBVID 0x2E
175 #define BGE_PCI_ROMBASE 0x30
176 #define BGE_PCI_CAPPTR 0x34
177 #define BGE_PCI_INTLINE 0x3C
178 #define BGE_PCI_INTPIN 0x3D
179 #define BGE_PCI_MINGNT 0x3E
180 #define BGE_PCI_MAXLAT 0x3F
181 #define BGE_PCI_PCIXCAP 0x40
182 #define BGE_PCI_NEXTPTR_PM 0x41
183 #define BGE_PCI_PCIX_CMD 0x42
184 #define BGE_PCI_PCIX_STS 0x44
185 #define BGE_PCI_PWRMGMT_CAPID 0x48
186 #define BGE_PCI_NEXTPTR_VPD 0x49
187 #define BGE_PCI_PWRMGMT_CAPS 0x4A
188 #define BGE_PCI_PWRMGMT_CMD 0x4C
189 #define BGE_PCI_PWRMGMT_STS 0x4D
190 #define BGE_PCI_PWRMGMT_DATA 0x4F
191 #define BGE_PCI_VPD_CAPID 0x50
192 #define BGE_PCI_NEXTPTR_MSI 0x51
193 #define BGE_PCI_VPD_ADDR 0x52
194 #define BGE_PCI_VPD_DATA 0x54
195 #define BGE_PCI_MSI_CAPID 0x58
196 #define BGE_PCI_NEXTPTR_NONE 0x59
197 #define BGE_PCI_MSI_CTL 0x5A
198 #define BGE_PCI_MSI_ADDR_HI 0x5C
199 #define BGE_PCI_MSI_ADDR_LO 0x60
200 #define BGE_PCI_MSI_DATA 0x64
201
202 /*
203 * PCI Express definitions
204 * According to
205 * PCI Express base specification, REV. 1.0a
206 */
207
208 /* PCI Express device control, 16bits */
209 #define BGE_PCIE_DEVCTL 0x08
210 #define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000
211 #define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000
212 #define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000
213 #define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000
214 #define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000
215 #define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000
216 #define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000
217
218 /* PCI MSI. ??? */
219 #define BGE_PCIE_CAPID_REG 0xD0
220 #define BGE_PCIE_CAPID 0x10
221
222 /*
223 * PCI registers specific to the BCM570x family.
224 */
225 #define BGE_PCI_MISC_CTL 0x68
226 #define BGE_PCI_DMA_RW_CTL 0x6C
227 #define BGE_PCI_PCISTATE 0x70
228 #define BGE_PCI_CLKCTL 0x74
229 #define BGE_PCI_REG_BASEADDR 0x78
230 #define BGE_PCI_MEMWIN_BASEADDR 0x7C
231 #define BGE_PCI_REG_DATA 0x80
232 #define BGE_PCI_MEMWIN_DATA 0x84
233 #define BGE_PCI_MODECTL 0x88
234 #define BGE_PCI_MISC_CFG 0x8C
235 #define BGE_PCI_MISC_LOCALCTL 0x90
236 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98
237 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C
238 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0
239 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4
240 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8
241 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
242 #define BGE_PCI_ISR_MBX_HI 0xB0
243 #define BGE_PCI_ISR_MBX_LO 0xB4
244 #define BGE_PCI_PRODID_ASICREV 0xBC
245 #define BGE_PCI_GEN2_PRODID_ASICREV 0xF4
246 #define BGE_PCI_GEN15_PRODID_ASICREV 0xFC
247
248 /* PCI Misc. Host control register */
249 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
250 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
251 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004
252 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008
253 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010
254 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020
255 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
256 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
257 #define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200
258 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
259 #define BGE_PCIMISCCTL_ASICREV_SHIFT 16
260
261 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP)
262
263 #define BGE_INIT \
264 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \
265 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
266
267 #define BGE_CHIPID_TIGON_I 0x4000
268 #define BGE_CHIPID_TIGON_II 0x6000
269 #define BGE_CHIPID_BCM5700_A0 0x7000
270 #define BGE_CHIPID_BCM5700_A1 0x7001
271 #define BGE_CHIPID_BCM5700_B0 0x7100
272 #define BGE_CHIPID_BCM5700_B1 0x7101
273 #define BGE_CHIPID_BCM5700_B2 0x7102
274 #define BGE_CHIPID_BCM5700_B3 0x7103
275 #define BGE_CHIPID_BCM5700_ALTIMA 0x7104
276 #define BGE_CHIPID_BCM5700_C0 0x7200
277 #define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */
278 #define BGE_CHIPID_BCM5701_B0 0x0100
279 #define BGE_CHIPID_BCM5701_B2 0x0102
280 #define BGE_CHIPID_BCM5701_B5 0x0105
281 #define BGE_CHIPID_BCM5703_A0 0x1000
282 #define BGE_CHIPID_BCM5703_A1 0x1001
283 #define BGE_CHIPID_BCM5703_A2 0x1002
284 #define BGE_CHIPID_BCM5703_A3 0x1003
285 #define BGE_CHIPID_BCM5703_B0 0x1100
286 #define BGE_CHIPID_BCM5704_A0 0x2000
287 #define BGE_CHIPID_BCM5704_A1 0x2001
288 #define BGE_CHIPID_BCM5704_A2 0x2002
289 #define BGE_CHIPID_BCM5704_A3 0x2003
290 #define BGE_CHIPID_BCM5704_B0 0x2100
291 #define BGE_CHIPID_BCM5705_A0 0x3000
292 #define BGE_CHIPID_BCM5705_A1 0x3001
293 #define BGE_CHIPID_BCM5705_A2 0x3002
294 #define BGE_CHIPID_BCM5705_A3 0x3003
295 #define BGE_CHIPID_BCM5750_A0 0x4000
296 #define BGE_CHIPID_BCM5750_A1 0x4001
297 #define BGE_CHIPID_BCM5750_A3 0x4000
298 #define BGE_CHIPID_BCM5750_B0 0x4100
299 #define BGE_CHIPID_BCM5750_B1 0x4101
300 #define BGE_CHIPID_BCM5750_C0 0x4200
301 #define BGE_CHIPID_BCM5750_C1 0x4201
302 #define BGE_CHIPID_BCM5750_C2 0x4202
303 #define BGE_CHIPID_BCM5714_A0 0x5000
304 #define BGE_CHIPID_BCM5752_A0 0x6000
305 #define BGE_CHIPID_BCM5752_A1 0x6001
306 #define BGE_CHIPID_BCM5752_A2 0x6002
307 #define BGE_CHIPID_BCM5714_B0 0x8000
308 #define BGE_CHIPID_BCM5714_B3 0x8003
309 #define BGE_CHIPID_BCM5715_A0 0x9000
310 #define BGE_CHIPID_BCM5715_A1 0x9001
311 #define BGE_CHIPID_BCM5715_A3 0x9003
312 #define BGE_CHIPID_BCM5755_A0 0xa000
313 #define BGE_CHIPID_BCM5755_A1 0xa001
314 #define BGE_CHIPID_BCM5755_A2 0xa002
315 #define BGE_CHIPID_BCM5722_A0 0xa200
316 #define BGE_CHIPID_BCM5754_A0 0xb000
317 #define BGE_CHIPID_BCM5754_A1 0xb001
318 #define BGE_CHIPID_BCM5754_A2 0xb002
319 #define BGE_CHIPID_BCM5761_A0 0x5761000
320 #define BGE_CHIPID_BCM5761_A1 0x5761100
321 #define BGE_CHIPID_BCM5784_A0 0x5784000
322 #define BGE_CHIPID_BCM5784_A1 0x5784100
323 #define BGE_CHIPID_BCM5787_A0 0xb000
324 #define BGE_CHIPID_BCM5787_A1 0xb001
325 #define BGE_CHIPID_BCM5787_A2 0xb002
326 #define BGE_CHIPID_BCM5906_A0 0xc000
327 #define BGE_CHIPID_BCM5906_A1 0xc001
328 #define BGE_CHIPID_BCM5906_A2 0xc002
329 #define BGE_CHIPID_BCM57780_A0 0x57780000
330 #define BGE_CHIPID_BCM57780_A1 0x57780001
331 #define BGE_CHIPID_BCM5717_A0 0x05717000
332 #define BGE_CHIPID_BCM5717_B0 0x05717100
333 #define BGE_CHIPID_BCM5717_C0 0x05717200
334 #define BGE_CHIPID_BCM5719_A0 0x05719000
335 #define BGE_CHIPID_BCM5720_A0 0x05720000
336 #define BGE_CHIPID_BCM5762_A0 0x05762000
337 #define BGE_CHIPID_BCM57765_A0 0x57785000
338 #define BGE_CHIPID_BCM57765_B0 0x57785100
339
340 /* shorthand one */
341 #define BGE_ASICREV(x) ((x) >> 12)
342 #define BGE_ASICREV_BCM5701 0x00
343 #define BGE_ASICREV_BCM5703 0x01
344 #define BGE_ASICREV_BCM5704 0x02
345 #define BGE_ASICREV_BCM5705 0x03
346 #define BGE_ASICREV_BCM5750 0x04
347 #define BGE_ASICREV_BCM5714_A0 0x05
348 #define BGE_ASICREV_BCM5752 0x06
349 #define BGE_ASICREV_BCM5700 0x07
350 #define BGE_ASICREV_BCM5780 0x08
351 #define BGE_ASICREV_BCM5714 0x09
352 #define BGE_ASICREV_BCM5755 0x0a
353 #define BGE_ASICREV_BCM5754 0x0b
354 #define BGE_ASICREV_BCM5787 0x0b
355 #define BGE_ASICREV_BCM5906 0x0c
356 /* Should consult BGE_PCI_PRODID_ASICREV for ChipID */
357 #define BGE_ASICREV_USE_PRODID_REG 0x0f
358 /* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */
359 #define BGE_ASICREV_BCM5717 0x5717
360 #define BGE_ASICREV_BCM5719 0x5719
361 #define BGE_ASICREV_BCM5720 0x5720
362 #define BGE_ASICREV_BCM5761 0x5761
363 #define BGE_ASICREV_BCM5762 0x5762
364 #define BGE_ASICREV_BCM5784 0x5784
365 #define BGE_ASICREV_BCM5785 0x5785
366 #define BGE_ASICREV_BCM57765 0x57785
367 #define BGE_ASICREV_BCM57766 0x57766
368 #define BGE_ASICREV_BCM57780 0x57780
369
370 /* chip revisions */
371 #define BGE_CHIPREV(x) ((x) >> 8)
372 #define BGE_CHIPREV_5700_AX 0x70
373 #define BGE_CHIPREV_5700_BX 0x71
374 #define BGE_CHIPREV_5700_CX 0x72
375 #define BGE_CHIPREV_5701_AX 0x00
376 #define BGE_CHIPREV_5703_AX 0x10
377 #define BGE_CHIPREV_5704_AX 0x20
378 #define BGE_CHIPREV_5704_BX 0x21
379 #define BGE_CHIPREV_5750_AX 0x40
380 #define BGE_CHIPREV_5750_BX 0x41
381 /* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */
382 #define BGE_CHIPREV_5717_AX 0x57170
383 #define BGE_CHIPREV_5717_BX 0x57171
384 #define BGE_CHIPREV_5761_AX 0x57611
385 #define BGE_CHIPREV_57765_AX 0x577850
386 #define BGE_CHIPREV_5784_AX 0x57841
387
388 /* PCI DMA Read/Write Control register */
389 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF
390 #define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001
391 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
392 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
393 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000
394 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000
395 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000
396 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000
397 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000
398 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000
399 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
400 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
401 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
402
403 #define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16)
404 #define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19)
405 #define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24)
406 #define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28)
407
408 #define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080
409 #define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380
410
411 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
412 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
413 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
414 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300
415 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400
416 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500
417 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600
418 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700
419
420 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000
421 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800
422 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000
423 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800
424 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000
425 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800
426 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000
427 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800
428
429 /*
430 * PCI state register -- note, this register is read only
431 * unless the PCISTATE_WR bit of the PCI Misc. Host Control
432 * register is set.
433 */
434 #define BGE_PCISTATE_FORCE_RESET 0x00000001
435 #define BGE_PCISTATE_INTR_STATE 0x00000002
436 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
437 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */
438 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
439 #define BGE_PCISTATE_ROM_ENABLE 0x00000020
440 #define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040
441 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
442 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
443 #define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000
444 #define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
445 #define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
446 #define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000
447
448 /*
449 * PCI Clock Control register -- note, this register is read only
450 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
451 * register is set.
452 */
453 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F
454 #define BGE_PCICLOCKCTL_M66EN 0x00000080
455 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200
456 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400
457 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800
458 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000
459 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000
460 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000
461 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
462 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
463
464 #ifndef PCIM_CMD_MWIEN
465 #define PCIM_CMD_MWIEN 0x0010
466 #endif
467 #ifndef PCIM_CMD_INTxDIS
468 #define PCIM_CMD_INTxDIS 0x0400
469 #endif
470
471 /* BAR0 (MAC) Register Definitions */
472
473 /*
474 * High priority mailbox registers
475 * Each mailbox is 64-bits wide, though we only use the
476 * lower 32 bits. To write a 64-bit value, write the upper 32 bits
477 * first. The NIC will load the mailbox after the lower 32 bit word
478 * has been updated.
479 */
480 #define BGE_MBX_IRQ0_HI 0x0200
481 #define BGE_MBX_IRQ0_LO 0x0204
482 #define BGE_MBX_IRQ1_HI 0x0208
483 #define BGE_MBX_IRQ1_LO 0x020C
484 #define BGE_MBX_IRQ2_HI 0x0210
485 #define BGE_MBX_IRQ2_LO 0x0214
486 #define BGE_MBX_IRQ3_HI 0x0218
487 #define BGE_MBX_IRQ3_LO 0x021C
488 #define BGE_MBX_GEN0_HI 0x0220
489 #define BGE_MBX_GEN0_LO 0x0224
490 #define BGE_MBX_GEN1_HI 0x0228
491 #define BGE_MBX_GEN1_LO 0x022C
492 #define BGE_MBX_GEN2_HI 0x0230
493 #define BGE_MBX_GEN2_LO 0x0234
494 #define BGE_MBX_GEN3_HI 0x0228
495 #define BGE_MBX_GEN3_LO 0x022C
496 #define BGE_MBX_GEN4_HI 0x0240
497 #define BGE_MBX_GEN4_LO 0x0244
498 #define BGE_MBX_GEN5_HI 0x0248
499 #define BGE_MBX_GEN5_LO 0x024C
500 #define BGE_MBX_GEN6_HI 0x0250
501 #define BGE_MBX_GEN6_LO 0x0254
502 #define BGE_MBX_GEN7_HI 0x0258
503 #define BGE_MBX_GEN7_LO 0x025C
504 #define BGE_MBX_RELOAD_STATS_HI 0x0260
505 #define BGE_MBX_RELOAD_STATS_LO 0x0264
506 #define BGE_MBX_RX_STD_PROD_HI 0x0268
507 #define BGE_MBX_RX_STD_PROD_LO 0x026C
508 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270
509 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274
510 #define BGE_MBX_RX_MINI_PROD_HI 0x0278
511 #define BGE_MBX_RX_MINI_PROD_LO 0x027C
512 #define BGE_MBX_RX_CONS0_HI 0x0280
513 #define BGE_MBX_RX_CONS0_LO 0x0284
514 #define BGE_MBX_RX_CONS1_HI 0x0288
515 #define BGE_MBX_RX_CONS1_LO 0x028C
516 #define BGE_MBX_RX_CONS2_HI 0x0290
517 #define BGE_MBX_RX_CONS2_LO 0x0294
518 #define BGE_MBX_RX_CONS3_HI 0x0298
519 #define BGE_MBX_RX_CONS3_LO 0x029C
520 #define BGE_MBX_RX_CONS4_HI 0x02A0
521 #define BGE_MBX_RX_CONS4_LO 0x02A4
522 #define BGE_MBX_RX_CONS5_HI 0x02A8
523 #define BGE_MBX_RX_CONS5_LO 0x02AC
524 #define BGE_MBX_RX_CONS6_HI 0x02B0
525 #define BGE_MBX_RX_CONS6_LO 0x02B4
526 #define BGE_MBX_RX_CONS7_HI 0x02B8
527 #define BGE_MBX_RX_CONS7_LO 0x02BC
528 #define BGE_MBX_RX_CONS8_HI 0x02C0
529 #define BGE_MBX_RX_CONS8_LO 0x02C4
530 #define BGE_MBX_RX_CONS9_HI 0x02C8
531 #define BGE_MBX_RX_CONS9_LO 0x02CC
532 #define BGE_MBX_RX_CONS10_HI 0x02D0
533 #define BGE_MBX_RX_CONS10_LO 0x02D4
534 #define BGE_MBX_RX_CONS11_HI 0x02D8
535 #define BGE_MBX_RX_CONS11_LO 0x02DC
536 #define BGE_MBX_RX_CONS12_HI 0x02E0
537 #define BGE_MBX_RX_CONS12_LO 0x02E4
538 #define BGE_MBX_RX_CONS13_HI 0x02E8
539 #define BGE_MBX_RX_CONS13_LO 0x02EC
540 #define BGE_MBX_RX_CONS14_HI 0x02F0
541 #define BGE_MBX_RX_CONS14_LO 0x02F4
542 #define BGE_MBX_RX_CONS15_HI 0x02F8
543 #define BGE_MBX_RX_CONS15_LO 0x02FC
544 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300
545 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304
546 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308
547 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C
548 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310
549 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314
550 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318
551 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C
552 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320
553 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324
554 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328
555 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C
556 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330
557 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334
558 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338
559 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C
560 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340
561 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344
562 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348
563 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C
564 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350
565 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354
566 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358
567 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C
568 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360
569 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364
570 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368
571 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C
572 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370
573 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374
574 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378
575 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C
576 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380
577 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384
578 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388
579 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C
580 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390
581 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394
582 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398
583 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C
584 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0
585 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4
586 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8
587 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC
588 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0
589 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4
590 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8
591 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC
592 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0
593 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4
594 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8
595 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC
596 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0
597 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4
598 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8
599 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC
600 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0
601 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4
602 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8
603 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC
604 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0
605 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4
606 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
607 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
608
609 #define BGE_TX_RINGS_MAX 4
610 #define BGE_TX_RINGS_EXTSSRAM_MAX 16
611 #define BGE_RX_RINGS_MAX 16
612 #define BGE_RX_RINGS_MAX_5717 17
613
614 /* Ethernet MAC control registers */
615 #define BGE_MAC_MODE 0x0400
616 #define BGE_MAC_STS 0x0404
617 #define BGE_MAC_EVT_ENB 0x0408
618 #define BGE_MAC_LED_CTL 0x040C
619 #define BGE_MAC_ADDR1_LO 0x0410
620 #define BGE_MAC_ADDR1_HI 0x0414
621 #define BGE_MAC_ADDR2_LO 0x0418
622 #define BGE_MAC_ADDR2_HI 0x041C
623 #define BGE_MAC_ADDR3_LO 0x0420
624 #define BGE_MAC_ADDR3_HI 0x0424
625 #define BGE_MAC_ADDR4_LO 0x0428
626 #define BGE_MAC_ADDR4_HI 0x042C
627 #define BGE_WOL_PATPTR 0x0430
628 #define BGE_WOL_PATCFG 0x0434
629 #define BGE_TX_RANDOM_BACKOFF 0x0438
630 #define BGE_RX_MTU 0x043C
631 #define BGE_GBIT_PCS_TEST 0x0440
632 #define BGE_TX_TBI_AUTONEG 0x0444
633 #define BGE_RX_TBI_AUTONEG 0x0448
634 #define BGE_MI_COMM 0x044C
635 #define BGE_MI_STS 0x0450
636 #define BGE_MI_MODE 0x0454
637 #define BGE_AUTOPOLL_STS 0x0458
638 #define BGE_TX_MODE 0x045C
639 #define BGE_TX_STS 0x0460
640 #define BGE_TX_LENGTHS 0x0464
641 #define BGE_RX_MODE 0x0468
642 #define BGE_RX_STS 0x046C
643 #define BGE_MAR0 0x0470
644 #define BGE_MAR1 0x0474
645 #define BGE_MAR2 0x0478
646 #define BGE_MAR3 0x047C
647 #define BGE_RX_BD_RULES_CTL0 0x0480
648 #define BGE_RX_BD_RULES_MASKVAL0 0x0484
649 #define BGE_RX_BD_RULES_CTL1 0x0488
650 #define BGE_RX_BD_RULES_MASKVAL1 0x048C
651 #define BGE_RX_BD_RULES_CTL2 0x0490
652 #define BGE_RX_BD_RULES_MASKVAL2 0x0494
653 #define BGE_RX_BD_RULES_CTL3 0x0498
654 #define BGE_RX_BD_RULES_MASKVAL3 0x049C
655 #define BGE_RX_BD_RULES_CTL4 0x04A0
656 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4
657 #define BGE_RX_BD_RULES_CTL5 0x04A8
658 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC
659 #define BGE_RX_BD_RULES_CTL6 0x04B0
660 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4
661 #define BGE_RX_BD_RULES_CTL7 0x04B8
662 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC
663 #define BGE_RX_BD_RULES_CTL8 0x04C0
664 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4
665 #define BGE_RX_BD_RULES_CTL9 0x04C8
666 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC
667 #define BGE_RX_BD_RULES_CTL10 0x04D0
668 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4
669 #define BGE_RX_BD_RULES_CTL11 0x04D8
670 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC
671 #define BGE_RX_BD_RULES_CTL12 0x04E0
672 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4
673 #define BGE_RX_BD_RULES_CTL13 0x04E8
674 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC
675 #define BGE_RX_BD_RULES_CTL14 0x04F0
676 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4
677 #define BGE_RX_BD_RULES_CTL15 0x04F8
678 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC
679 #define BGE_RX_RULES_CFG 0x0500
680 #define BGE_MAX_RX_FRAME_LOWAT 0x0504
681 #define BGE_SERDES_CFG 0x0590
682 #define BGE_SERDES_STS 0x0594
683 #define BGE_SGDIG_CFG 0x05B0
684 #define BGE_SGDIG_STS 0x05B4
685 #define BGE_TX_MAC_STATS_OCTETS 0x0800
686 #define BGE_TX_MAC_STATS_RESERVE_0 0x0804
687 #define BGE_TX_MAC_STATS_COLLS 0x0808
688 #define BGE_TX_MAC_STATS_XON_SENT 0x080C
689 #define BGE_TX_MAC_STATS_XOFF_SENT 0x0810
690 #define BGE_TX_MAC_STATS_RESERVE_1 0x0814
691 #define BGE_TX_MAC_STATS_ERRORS 0x0818
692 #define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C
693 #define BGE_TX_MAC_STATS_MULTI_COLL 0x0820
694 #define BGE_TX_MAC_STATS_DEFERRED 0x0824
695 #define BGE_TX_MAC_STATS_RESERVE_2 0x0828
696 #define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C
697 #define BGE_TX_MAC_STATS_LATE_COLL 0x0830
698 #define BGE_TX_MAC_STATS_RESERVE_3 0x0834
699 #define BGE_TX_MAC_STATS_RESERVE_4 0x0838
700 #define BGE_TX_MAC_STATS_RESERVE_5 0x083C
701 #define BGE_TX_MAC_STATS_RESERVE_6 0x0840
702 #define BGE_TX_MAC_STATS_RESERVE_7 0x0844
703 #define BGE_TX_MAC_STATS_RESERVE_8 0x0848
704 #define BGE_TX_MAC_STATS_RESERVE_9 0x084C
705 #define BGE_TX_MAC_STATS_RESERVE_10 0x0850
706 #define BGE_TX_MAC_STATS_RESERVE_11 0x0854
707 #define BGE_TX_MAC_STATS_RESERVE_12 0x0858
708 #define BGE_TX_MAC_STATS_RESERVE_13 0x085C
709 #define BGE_TX_MAC_STATS_RESERVE_14 0x0860
710 #define BGE_TX_MAC_STATS_RESERVE_15 0x0864
711 #define BGE_TX_MAC_STATS_RESERVE_16 0x0868
712 #define BGE_TX_MAC_STATS_UCAST 0x086C
713 #define BGE_TX_MAC_STATS_MCAST 0x0870
714 #define BGE_TX_MAC_STATS_BCAST 0x0874
715 #define BGE_TX_MAC_STATS_RESERVE_17 0x0878
716 #define BGE_TX_MAC_STATS_RESERVE_18 0x087C
717 #define BGE_RX_MAC_STATS_OCTESTS 0x0880
718 #define BGE_RX_MAC_STATS_RESERVE_0 0x0884
719 #define BGE_RX_MAC_STATS_FRAGMENTS 0x0888
720 #define BGE_RX_MAC_STATS_UCAST 0x088C
721 #define BGE_RX_MAC_STATS_MCAST 0x0890
722 #define BGE_RX_MAC_STATS_BCAST 0x0894
723 #define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898
724 #define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C
725 #define BGE_RX_MAC_STATS_XON_RCVD 0x08A0
726 #define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4
727 #define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8
728 #define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC
729 #define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0
730 #define BGE_RX_MAC_STATS_JABBERS 0x08B4
731 #define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8
732
733 /* Ethernet MAC Mode register */
734 #define BGE_MACMODE_RESET 0x00000001
735 #define BGE_MACMODE_HALF_DUPLEX 0x00000002
736 #define BGE_MACMODE_PORTMODE 0x0000000C
737 #define BGE_MACMODE_LOOPBACK 0x00000010
738 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080
739 #define BGE_MACMODE_TX_BURST_ENB 0x00000100
740 #define BGE_MACMODE_MAX_DEFER 0x00000200
741 #define BGE_MACMODE_LINK_POLARITY 0x00000400
742 #define BGE_MACMODE_RX_STATS_ENB 0x00000800
743 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000
744 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000
745 #define BGE_MACMODE_TX_STATS_ENB 0x00004000
746 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000
747 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000
748 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000
749 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000
750 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000
751 #define BGE_MACMODE_MIP_ENB 0x00100000
752 #define BGE_MACMODE_TXDMA_ENB 0x00200000
753 #define BGE_MACMODE_RXDMA_ENB 0x00400000
754 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
755 #define BGE_MACMODE_APE_RX_EN 0x08000000
756 #define BGE_MACMODE_APE_TX_EN 0x10000000
757
758 #define BGE_PORTMODE_NONE 0x00000000
759 #define BGE_PORTMODE_MII 0x00000004
760 #define BGE_PORTMODE_GMII 0x00000008
761 #define BGE_PORTMODE_TBI 0x0000000C
762
763 /* MAC Status register */
764 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001
765 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002
766 #define BGE_MACSTAT_RX_CFG 0x00000004
767 #define BGE_MACSTAT_CFG_CHANGED 0x00000008
768 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010
769 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400
770 #define BGE_MACSTAT_LINK_CHANGED 0x00001000
771 #define BGE_MACSTAT_MI_COMPLETE 0x00400000
772 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000
773 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000
774 #define BGE_MACSTAT_ODI_ERROR 0x02000000
775 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000
776 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000
777
778 /* MAC Event Enable Register */
779 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400
780 #define BGE_EVTENB_LINK_CHANGED 0x00001000
781 #define BGE_EVTENB_MI_COMPLETE 0x00400000
782 #define BGE_EVTENB_MI_INTERRUPT 0x00800000
783 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000
784 #define BGE_EVTENB_ODI_ERROR 0x02000000
785 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000
786 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000
787
788 /* LED Control Register */
789 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001
790 #define BGE_LEDCTL_1000MBPS_LED 0x00000002
791 #define BGE_LEDCTL_100MBPS_LED 0x00000004
792 #define BGE_LEDCTL_10MBPS_LED 0x00000008
793 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010
794 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020
795 #define BGE_LEDCTL_TRAFLED_BLINK_2 0x00000040
796 #define BGE_LEDCTL_1000MBPS_STS 0x00000080
797 #define BGE_LEDCTL_100MBPS_STS 0x00000100
798 #define BGE_LEDCTL_10MBPS_STS 0x00000200
799 #define BGE_LEDCTL_TRAFLED_STS 0x00000400
800 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000
801 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000
802
803 /* TX backoff seed register */
804 #define BGE_TX_BACKOFF_SEED_MASK 0x3FF
805
806 /* Autopoll status register */
807 #define BGE_AUTOPOLLSTS_ERROR 0x00000001
808
809 /* Transmit MAC mode register */
810 #define BGE_TXMODE_RESET 0x00000001
811 #define BGE_TXMODE_ENABLE 0x00000002
812 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010
813 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020
814 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040
815 #define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100
816 #define BGE_TXMODE_JMB_FRM_LEN 0x00400000
817 #define BGE_TXMODE_CNT_DN_MODE 0x00800000
818
819 /* Transmit MAC status register */
820 #define BGE_TXSTAT_RX_XOFFED 0x00000001
821 #define BGE_TXSTAT_SENT_XOFF 0x00000002
822 #define BGE_TXSTAT_SENT_XON 0x00000004
823 #define BGE_TXSTAT_LINK_UP 0x00000008
824 #define BGE_TXSTAT_ODI_UFLOW 0x00000010
825 #define BGE_TXSTAT_ODI_OFLOW 0x00000020
826
827 /* Transmit MAC lengths register */
828 #define BGE_TXLEN_SLOTTIME 0x000000FF
829 #define BGE_TXLEN_IPG 0x00000F00
830 #define BGE_TXLEN_CRS 0x00003000
831 #define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000
832 #define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000
833
834 /* Receive MAC mode register */
835 #define BGE_RXMODE_RESET 0x00000001
836 #define BGE_RXMODE_ENABLE 0x00000002
837 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004
838 #define BGE_RXMODE_RX_GIANTS 0x00000020
839 #define BGE_RXMODE_RX_RUNTS 0x00000040
840 #define BGE_RXMODE_8022_LENCHECK 0x00000080
841 #define BGE_RXMODE_RX_PROMISC 0x00000100
842 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
843 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
844 #define BGE_RXMODE_IPV6_ENABLE 0x01000000
845 #define BGE_RXMODE_IPV4_FRAG_FIX 0x02000000
846
847 /* Receive MAC status register */
848 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
849 #define BGE_RXSTAT_RCVD_XOFF 0x00000002
850 #define BGE_RXSTAT_RCVD_XON 0x00000004
851
852 /* Receive Rules Control register */
853 #define BGE_RXRULECTL_OFFSET 0x000000FF
854 #define BGE_RXRULECTL_CLASS 0x00001F00
855 #define BGE_RXRULECTL_HDRTYPE 0x0000E000
856 #define BGE_RXRULECTL_COMPARE_OP 0x00030000
857 #define BGE_RXRULECTL_MAP 0x01000000
858 #define BGE_RXRULECTL_DISCARD 0x02000000
859 #define BGE_RXRULECTL_MASK 0x04000000
860 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000
861 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000
862 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000
863 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000
864
865 /* Receive Rules Mask register */
866 #define BGE_RXRULEMASK_VALUE 0x0000FFFF
867 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000
868
869 /* SERDES configuration register */
870 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */
871 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */
872 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */
873 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */
874 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */
875 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */
876 #define BGE_SERDESCFG_TXMODE 0x00001000
877 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */
878 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */
879 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */
880 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */
881 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */
882 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */
883 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */
884 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */
885 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */
886
887 /* SERDES status register */
888 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */
889 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */
890
891 /* SGDIG config (not documented) */
892 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800
893 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000
894 #define BGE_SGDIGCFG_SEND 0x40000000
895 #define BGE_SGDIGCFG_AUTO 0x80000000
896
897 /* SGDIG status (not documented) */
898 #define BGE_SGDIGSTS_DONE 0x00000002
899 #define BGE_SGDIGSTS_IS_SERDES 0x00000100
900 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000
901 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000
902
903 /* MI communication register */
904 #define BGE_MICOMM_DATA 0x0000FFFF
905 #define BGE_MICOMM_REG 0x001F0000
906 #define BGE_MICOMM_PHY 0x03E00000
907 #define BGE_MICOMM_CMD 0x0C000000
908 #define BGE_MICOMM_READFAIL 0x10000000
909 #define BGE_MICOMM_BUSY 0x20000000
910
911 #define BGE_MIREG(x) ((x & 0x1F) << 16)
912 #define BGE_MIPHY(x) ((x & 0x1F) << 21)
913 #define BGE_MICMD_WRITE 0x04000000
914 #define BGE_MICMD_READ 0x08000000
915
916 /* MI status register */
917 #define BGE_MISTS_LINK 0x00000001
918 #define BGE_MISTS_10MBPS 0x00000002
919
920 #define BGE_MIMODE_CLK_10MHZ 0x00000001
921 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002
922 #define BGE_MIMODE_AUTOPOLL 0x00000010
923 #define BGE_MIMODE_CLKCNT 0x001F0000
924 #define BGE_MIMODE_500KHZ_CONST 0x00008000
925 #define BGE_MIMODE_BASE 0x000C0000
926
927 /*
928 * Send data initiator control registers.
929 */
930 #define BGE_SDI_MODE 0x0C00
931 #define BGE_SDI_STATUS 0x0C04
932 #define BGE_SDI_STATS_CTL 0x0C08
933 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C
934 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10
935 #define BGE_ISO_PKT_TX 0x0C20
936 #define BGE_LOCSTATS_COS0 0x0C80
937 #define BGE_LOCSTATS_COS1 0x0C84
938 #define BGE_LOCSTATS_COS2 0x0C88
939 #define BGE_LOCSTATS_COS3 0x0C8C
940 #define BGE_LOCSTATS_COS4 0x0C90
941 #define BGE_LOCSTATS_COS5 0x0C84
942 #define BGE_LOCSTATS_COS6 0x0C98
943 #define BGE_LOCSTATS_COS7 0x0C9C
944 #define BGE_LOCSTATS_COS8 0x0CA0
945 #define BGE_LOCSTATS_COS9 0x0CA4
946 #define BGE_LOCSTATS_COS10 0x0CA8
947 #define BGE_LOCSTATS_COS11 0x0CAC
948 #define BGE_LOCSTATS_COS12 0x0CB0
949 #define BGE_LOCSTATS_COS13 0x0CB4
950 #define BGE_LOCSTATS_COS14 0x0CB8
951 #define BGE_LOCSTATS_COS15 0x0CBC
952 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0
953 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4
954 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8
955 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC
956 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0
957 #define BGE_LOCSTATS_IRQS 0x0CD4
958 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8
959 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC
960
961 /* Send Data Initiator mode register */
962 #define BGE_SDIMODE_RESET 0x00000001
963 #define BGE_SDIMODE_ENABLE 0x00000002
964 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004
965 #define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008
966
967 /* Send Data Initiator stats register */
968 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004
969
970 /* Send Data Initiator stats control register */
971 #define BGE_SDISTATSCTL_ENABLE 0x00000001
972 #define BGE_SDISTATSCTL_FASTER 0x00000002
973 #define BGE_SDISTATSCTL_CLEAR 0x00000004
974 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008
975 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010
976
977 /*
978 * Send Data Completion Control registers
979 */
980 #define BGE_SDC_MODE 0x1000
981 #define BGE_SDC_STATUS 0x1004
982
983 /* Send Data completion mode register */
984 #define BGE_SDCMODE_RESET 0x00000001
985 #define BGE_SDCMODE_ENABLE 0x00000002
986 #define BGE_SDCMODE_ATTN 0x00000004
987 #define BGE_SDCMODE_CDELAY 0x00000010
988
989 /* Send Data completion status register */
990 #define BGE_SDCSTAT_ATTN 0x00000004
991
992 /*
993 * Send BD Ring Selector Control registers
994 */
995 #define BGE_SRS_MODE 0x1400
996 #define BGE_SRS_STATUS 0x1404
997 #define BGE_SRS_HWDIAG 0x1408
998 #define BGE_SRS_LOC_NIC_CONS0 0x1440
999 #define BGE_SRS_LOC_NIC_CONS1 0x1444
1000 #define BGE_SRS_LOC_NIC_CONS2 0x1448
1001 #define BGE_SRS_LOC_NIC_CONS3 0x144C
1002 #define BGE_SRS_LOC_NIC_CONS4 0x1450
1003 #define BGE_SRS_LOC_NIC_CONS5 0x1454
1004 #define BGE_SRS_LOC_NIC_CONS6 0x1458
1005 #define BGE_SRS_LOC_NIC_CONS7 0x145C
1006 #define BGE_SRS_LOC_NIC_CONS8 0x1460
1007 #define BGE_SRS_LOC_NIC_CONS9 0x1464
1008 #define BGE_SRS_LOC_NIC_CONS10 0x1468
1009 #define BGE_SRS_LOC_NIC_CONS11 0x146C
1010 #define BGE_SRS_LOC_NIC_CONS12 0x1470
1011 #define BGE_SRS_LOC_NIC_CONS13 0x1474
1012 #define BGE_SRS_LOC_NIC_CONS14 0x1478
1013 #define BGE_SRS_LOC_NIC_CONS15 0x147C
1014
1015 /* Send BD Ring Selector Mode register */
1016 #define BGE_SRSMODE_RESET 0x00000001
1017 #define BGE_SRSMODE_ENABLE 0x00000002
1018 #define BGE_SRSMODE_ATTN 0x00000004
1019
1020 /* Send BD Ring Selector Status register */
1021 #define BGE_SRSSTAT_ERROR 0x00000004
1022
1023 /* Send BD Ring Selector HW Diagnostics register */
1024 #define BGE_SRSHWDIAG_STATE 0x0000000F
1025 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0
1026 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00
1027 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000
1028
1029 /*
1030 * Send BD Initiator Selector Control registers
1031 */
1032 #define BGE_SBDI_MODE 0x1800
1033 #define BGE_SBDI_STATUS 0x1804
1034 #define BGE_SBDI_LOC_NIC_PROD0 0x1808
1035 #define BGE_SBDI_LOC_NIC_PROD1 0x180C
1036 #define BGE_SBDI_LOC_NIC_PROD2 0x1810
1037 #define BGE_SBDI_LOC_NIC_PROD3 0x1814
1038 #define BGE_SBDI_LOC_NIC_PROD4 0x1818
1039 #define BGE_SBDI_LOC_NIC_PROD5 0x181C
1040 #define BGE_SBDI_LOC_NIC_PROD6 0x1820
1041 #define BGE_SBDI_LOC_NIC_PROD7 0x1824
1042 #define BGE_SBDI_LOC_NIC_PROD8 0x1828
1043 #define BGE_SBDI_LOC_NIC_PROD9 0x182C
1044 #define BGE_SBDI_LOC_NIC_PROD10 0x1830
1045 #define BGE_SBDI_LOC_NIC_PROD11 0x1834
1046 #define BGE_SBDI_LOC_NIC_PROD12 0x1838
1047 #define BGE_SBDI_LOC_NIC_PROD13 0x183C
1048 #define BGE_SBDI_LOC_NIC_PROD14 0x1840
1049 #define BGE_SBDI_LOC_NIC_PROD15 0x1844
1050
1051 /* Send BD Initiator Mode register */
1052 #define BGE_SBDIMODE_RESET 0x00000001
1053 #define BGE_SBDIMODE_ENABLE 0x00000002
1054 #define BGE_SBDIMODE_ATTN 0x00000004
1055
1056 /* Send BD Initiator Status register */
1057 #define BGE_SBDISTAT_ERROR 0x00000004
1058
1059 /*
1060 * Send BD Completion Control registers
1061 */
1062 #define BGE_SBDC_MODE 0x1C00
1063 #define BGE_SBDC_STATUS 0x1C04
1064
1065 /* Send BD Completion Control Mode register */
1066 #define BGE_SBDCMODE_RESET 0x00000001
1067 #define BGE_SBDCMODE_ENABLE 0x00000002
1068 #define BGE_SBDCMODE_ATTN 0x00000004
1069
1070 /* Send BD Completion Control Status register */
1071 #define BGE_SBDCSTAT_ATTN 0x00000004
1072
1073 /*
1074 * Receive List Placement Control registers
1075 */
1076 #define BGE_RXLP_MODE 0x2000
1077 #define BGE_RXLP_STATUS 0x2004
1078 #define BGE_RXLP_SEL_LIST_LOCK 0x2008
1079 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C
1080 #define BGE_RXLP_CFG 0x2010
1081 #define BGE_RXLP_STATS_CTL 0x2014
1082 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018
1083 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C
1084 #define BGE_RXLP_HEAD0 0x2100
1085 #define BGE_RXLP_TAIL0 0x2104
1086 #define BGE_RXLP_COUNT0 0x2108
1087 #define BGE_RXLP_HEAD1 0x2110
1088 #define BGE_RXLP_TAIL1 0x2114
1089 #define BGE_RXLP_COUNT1 0x2118
1090 #define BGE_RXLP_HEAD2 0x2120
1091 #define BGE_RXLP_TAIL2 0x2124
1092 #define BGE_RXLP_COUNT2 0x2128
1093 #define BGE_RXLP_HEAD3 0x2130
1094 #define BGE_RXLP_TAIL3 0x2134
1095 #define BGE_RXLP_COUNT3 0x2138
1096 #define BGE_RXLP_HEAD4 0x2140
1097 #define BGE_RXLP_TAIL4 0x2144
1098 #define BGE_RXLP_COUNT4 0x2148
1099 #define BGE_RXLP_HEAD5 0x2150
1100 #define BGE_RXLP_TAIL5 0x2154
1101 #define BGE_RXLP_COUNT5 0x2158
1102 #define BGE_RXLP_HEAD6 0x2160
1103 #define BGE_RXLP_TAIL6 0x2164
1104 #define BGE_RXLP_COUNT6 0x2168
1105 #define BGE_RXLP_HEAD7 0x2170
1106 #define BGE_RXLP_TAIL7 0x2174
1107 #define BGE_RXLP_COUNT7 0x2178
1108 #define BGE_RXLP_HEAD8 0x2180
1109 #define BGE_RXLP_TAIL8 0x2184
1110 #define BGE_RXLP_COUNT8 0x2188
1111 #define BGE_RXLP_HEAD9 0x2190
1112 #define BGE_RXLP_TAIL9 0x2194
1113 #define BGE_RXLP_COUNT9 0x2198
1114 #define BGE_RXLP_HEAD10 0x21A0
1115 #define BGE_RXLP_TAIL10 0x21A4
1116 #define BGE_RXLP_COUNT10 0x21A8
1117 #define BGE_RXLP_HEAD11 0x21B0
1118 #define BGE_RXLP_TAIL11 0x21B4
1119 #define BGE_RXLP_COUNT11 0x21B8
1120 #define BGE_RXLP_HEAD12 0x21C0
1121 #define BGE_RXLP_TAIL12 0x21C4
1122 #define BGE_RXLP_COUNT12 0x21C8
1123 #define BGE_RXLP_HEAD13 0x21D0
1124 #define BGE_RXLP_TAIL13 0x21D4
1125 #define BGE_RXLP_COUNT13 0x21D8
1126 #define BGE_RXLP_HEAD14 0x21E0
1127 #define BGE_RXLP_TAIL14 0x21E4
1128 #define BGE_RXLP_COUNT14 0x21E8
1129 #define BGE_RXLP_HEAD15 0x21F0
1130 #define BGE_RXLP_TAIL15 0x21F4
1131 #define BGE_RXLP_COUNT15 0x21F8
1132 #define BGE_RXLP_LOCSTAT_COS0 0x2200
1133 #define BGE_RXLP_LOCSTAT_COS1 0x2204
1134 #define BGE_RXLP_LOCSTAT_COS2 0x2208
1135 #define BGE_RXLP_LOCSTAT_COS3 0x220C
1136 #define BGE_RXLP_LOCSTAT_COS4 0x2210
1137 #define BGE_RXLP_LOCSTAT_COS5 0x2214
1138 #define BGE_RXLP_LOCSTAT_COS6 0x2218
1139 #define BGE_RXLP_LOCSTAT_COS7 0x221C
1140 #define BGE_RXLP_LOCSTAT_COS8 0x2220
1141 #define BGE_RXLP_LOCSTAT_COS9 0x2224
1142 #define BGE_RXLP_LOCSTAT_COS10 0x2228
1143 #define BGE_RXLP_LOCSTAT_COS11 0x222C
1144 #define BGE_RXLP_LOCSTAT_COS12 0x2230
1145 #define BGE_RXLP_LOCSTAT_COS13 0x2234
1146 #define BGE_RXLP_LOCSTAT_COS14 0x2238
1147 #define BGE_RXLP_LOCSTAT_COS15 0x223C
1148 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240
1149 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244
1150 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248
1151 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C
1152 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250
1153 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
1154 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
1155
1156 /* Receive List Placement mode register */
1157 #define BGE_RXLPMODE_RESET 0x00000001
1158 #define BGE_RXLPMODE_ENABLE 0x00000002
1159 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004
1160 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008
1161 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010
1162
1163 /* Receive List Placement Status register */
1164 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004
1165 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008
1166 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010
1167
1168 /*
1169 * Receive Data and Receive BD Initiator Control Registers
1170 */
1171 #define BGE_RDBDI_MODE 0x2400
1172 #define BGE_RDBDI_STATUS 0x2404
1173 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440
1174 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444
1175 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448
1176 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C
1177 #define BGE_RX_STD_RCB_HADDR_HI 0x2450
1178 #define BGE_RX_STD_RCB_HADDR_LO 0x2454
1179 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458
1180 #define BGE_RX_STD_RCB_NICADDR 0x245C
1181 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460
1182 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464
1183 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468
1184 #define BGE_RX_MINI_RCB_NICADDR 0x246C
1185 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470
1186 #define BGE_RDBDI_STD_RX_CONS 0x2474
1187 #define BGE_RDBDI_MINI_RX_CONS 0x2478
1188 #define BGE_RDBDI_RETURN_PROD0 0x2480
1189 #define BGE_RDBDI_RETURN_PROD1 0x2484
1190 #define BGE_RDBDI_RETURN_PROD2 0x2488
1191 #define BGE_RDBDI_RETURN_PROD3 0x248C
1192 #define BGE_RDBDI_RETURN_PROD4 0x2490
1193 #define BGE_RDBDI_RETURN_PROD5 0x2494
1194 #define BGE_RDBDI_RETURN_PROD6 0x2498
1195 #define BGE_RDBDI_RETURN_PROD7 0x249C
1196 #define BGE_RDBDI_RETURN_PROD8 0x24A0
1197 #define BGE_RDBDI_RETURN_PROD9 0x24A4
1198 #define BGE_RDBDI_RETURN_PROD10 0x24A8
1199 #define BGE_RDBDI_RETURN_PROD11 0x24AC
1200 #define BGE_RDBDI_RETURN_PROD12 0x24B0
1201 #define BGE_RDBDI_RETURN_PROD13 0x24B4
1202 #define BGE_RDBDI_RETURN_PROD14 0x24B8
1203 #define BGE_RDBDI_RETURN_PROD15 0x24BC
1204 #define BGE_RDBDI_HWDIAG 0x24C0
1205
1206 /* Receive Data and Receive BD Initiator Mode register */
1207 #define BGE_RDBDIMODE_RESET 0x00000001
1208 #define BGE_RDBDIMODE_ENABLE 0x00000002
1209 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004
1210 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008
1211 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010
1212
1213 /* Receive Data and Receive BD Initiator Status register */
1214 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004
1215 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
1216 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
1217
1218 /*
1219 * Receive Data Completion Control registers
1220 */
1221 #define BGE_RDC_MODE 0x2800
1222
1223 /* Receive Data Completion Mode register */
1224 #define BGE_RDCMODE_RESET 0x00000001
1225 #define BGE_RDCMODE_ENABLE 0x00000002
1226 #define BGE_RDCMODE_ATTN 0x00000004
1227
1228 /*
1229 * Receive BD Initiator Control registers
1230 */
1231 #define BGE_RBDI_MODE 0x2C00
1232 #define BGE_RBDI_STATUS 0x2C04
1233 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08
1234 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C
1235 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10
1236 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14
1237 #define BGE_RBDI_STD_REPL_THRESH 0x2C18
1238 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C
1239
1240 #define BGE_STD_REPLENISH_LWM 0x2D00
1241 #define BGE_JMB_REPLENISH_LWM 0x2D04
1242
1243 /* Receive BD Initiator Mode register */
1244 #define BGE_RBDIMODE_RESET 0x00000001
1245 #define BGE_RBDIMODE_ENABLE 0x00000002
1246 #define BGE_RBDIMODE_ATTN 0x00000004
1247
1248 /* Receive BD Initiator Status register */
1249 #define BGE_RBDISTAT_ATTN 0x00000004
1250
1251 /*
1252 * Receive BD Completion Control registers
1253 */
1254 #define BGE_RBDC_MODE 0x3000
1255 #define BGE_RBDC_STATUS 0x3004
1256 #define BGE_RBDC_JUMBO_BD_PROD 0x3008
1257 #define BGE_RBDC_STD_BD_PROD 0x300C
1258 #define BGE_RBDC_MINI_BD_PROD 0x3010
1259
1260 /* Receive BD completion mode register */
1261 #define BGE_RBDCMODE_RESET 0x00000001
1262 #define BGE_RBDCMODE_ENABLE 0x00000002
1263 #define BGE_RBDCMODE_ATTN 0x00000004
1264
1265 /* Receive BD completion status register */
1266 #define BGE_RBDCSTAT_ERROR 0x00000004
1267
1268 /*
1269 * Receive List Selector Control registers
1270 */
1271 #define BGE_RXLS_MODE 0x3400
1272 #define BGE_RXLS_STATUS 0x3404
1273
1274 /* Receive List Selector Mode register */
1275 #define BGE_RXLSMODE_RESET 0x00000001
1276 #define BGE_RXLSMODE_ENABLE 0x00000002
1277 #define BGE_RXLSMODE_ATTN 0x00000004
1278
1279 /* Receive List Selector Status register */
1280 #define BGE_RXLSSTAT_ERROR 0x00000004
1281
1282 #define BGE_CPMU_CTRL 0x3600
1283 #define BGE_CPMU_LSPD_10MB_CLK 0x3604
1284 #define BGE_CPMU_LSPD_1000MB_CLK 0x360C
1285 #define BGE_CPMU_LNK_AWARE_PWRMD 0x3610
1286 #define BGE_CPMU_HST_ACC 0x361C
1287 #define BGE_CPMU_CLCK_ORIDE 0x3624
1288 #define BGE_CPMU_CLCK_STAT 0x3630
1289 #define BGE_CPMU_MUTEX_REQ 0x365C
1290 #define BGE_CPMU_MUTEX_GNT 0x3660
1291 #define BGE_CPMU_PHY_STRAP 0x3664
1292 #define BGE_CPMU_PADRNG_CTL 0x3668
1293
1294 /* Central Power Management Unit (CPMU) register */
1295 #define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1296 #define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400
1297 #define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000
1298 #define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
1299
1300 /* Link Speed 10MB/No Link Power Mode Clock Policy register */
1301 #define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000
1302 #define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1303
1304 /* Link Speed 1000MB Power Mode Clock Policy register */
1305 #define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1306 #define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1307 #define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000
1308
1309 /* Link Aware Power Mode Clock Policy register */
1310 #define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000
1311 #define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1312
1313 #define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000
1314 #define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000
1315
1316 /* Clock Speed Override Policy register */
1317 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1318
1319 /* CPMU Clock Status register */
1320 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000
1321 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1322 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1323 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1324
1325 /* CPMU Mutex Request register */
1326 #define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000
1327 #define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000
1328
1329 /* CPMU GPHY Strap register */
1330 #define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020
1331
1332 /* CPMU Padring Control register */
1333 #define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000
1334
1335 /*
1336 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
1337 */
1338 #define BGE_MBCF_MODE 0x3800
1339 #define BGE_MBCF_STATUS 0x3804
1340
1341 /* Mbuf Cluster Free mode register */
1342 #define BGE_MBCFMODE_RESET 0x00000001
1343 #define BGE_MBCFMODE_ENABLE 0x00000002
1344 #define BGE_MBCFMODE_ATTN 0x00000004
1345
1346 /* Mbuf Cluster Free status register */
1347 #define BGE_MBCFSTAT_ERROR 0x00000004
1348
1349 /*
1350 * Host Coalescing Control registers
1351 */
1352 #define BGE_HCC_MODE 0x3C00
1353 #define BGE_HCC_STATUS 0x3C04
1354 #define BGE_HCC_RX_COAL_TICKS 0x3C08
1355 #define BGE_HCC_TX_COAL_TICKS 0x3C0C
1356 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10
1357 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14
1358 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */
1359 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */
1360 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */
1361 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */
1362 #define BGE_HCC_STATS_TICKS 0x3C28
1363 #define BGE_HCC_STATS_ADDR_HI 0x3C30
1364 #define BGE_HCC_STATS_ADDR_LO 0x3C34
1365 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38
1366 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C
1367 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
1368 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
1369 #define BGE_FLOW_ATTN 0x3C48
1370 #define BGE_HCC_JUMBO_BD_CONS 0x3C50
1371 #define BGE_HCC_STD_BD_CONS 0x3C54
1372 #define BGE_HCC_MINI_BD_CONS 0x3C58
1373 #define BGE_HCC_RX_RETURN_PROD0 0x3C80
1374 #define BGE_HCC_RX_RETURN_PROD1 0x3C84
1375 #define BGE_HCC_RX_RETURN_PROD2 0x3C88
1376 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C
1377 #define BGE_HCC_RX_RETURN_PROD4 0x3C90
1378 #define BGE_HCC_RX_RETURN_PROD5 0x3C94
1379 #define BGE_HCC_RX_RETURN_PROD6 0x3C98
1380 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C
1381 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0
1382 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4
1383 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8
1384 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC
1385 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0
1386 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4
1387 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8
1388 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC
1389 #define BGE_HCC_TX_BD_CONS0 0x3CC0
1390 #define BGE_HCC_TX_BD_CONS1 0x3CC4
1391 #define BGE_HCC_TX_BD_CONS2 0x3CC8
1392 #define BGE_HCC_TX_BD_CONS3 0x3CCC
1393 #define BGE_HCC_TX_BD_CONS4 0x3CD0
1394 #define BGE_HCC_TX_BD_CONS5 0x3CD4
1395 #define BGE_HCC_TX_BD_CONS6 0x3CD8
1396 #define BGE_HCC_TX_BD_CONS7 0x3CDC
1397 #define BGE_HCC_TX_BD_CONS8 0x3CE0
1398 #define BGE_HCC_TX_BD_CONS9 0x3CE4
1399 #define BGE_HCC_TX_BD_CONS10 0x3CE8
1400 #define BGE_HCC_TX_BD_CONS11 0x3CEC
1401 #define BGE_HCC_TX_BD_CONS12 0x3CF0
1402 #define BGE_HCC_TX_BD_CONS13 0x3CF4
1403 #define BGE_HCC_TX_BD_CONS14 0x3CF8
1404 #define BGE_HCC_TX_BD_CONS15 0x3CFC
1405
1406 /* Host coalescing mode register */
1407 #define BGE_HCCMODE_RESET 0x00000001
1408 #define BGE_HCCMODE_ENABLE 0x00000002
1409 #define BGE_HCCMODE_ATTN 0x00000004
1410 #define BGE_HCCMODE_COAL_NOW 0x00000008
1411 #define BGE_HCCMODE_MSI_BITS 0x00000070
1412 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180
1413
1414 #define BGE_STATBLKSZ_FULL 0x00000000
1415 #define BGE_STATBLKSZ_64BYTE 0x00000080
1416 #define BGE_STATBLKSZ_32BYTE 0x00000100
1417
1418 /* Host coalescing status register */
1419 #define BGE_HCCSTAT_ERROR 0x00000004
1420
1421 /* Flow attention register */
1422 #define BGE_FLOWATTN_MB_LOWAT 0x00000040
1423 #define BGE_FLOWATTN_MEMARB 0x00000080
1424 #define BGE_FLOWATTN_HOSTCOAL 0x00008000
1425 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000
1426 #define BGE_FLOWATTN_RCB_INVAL 0x00020000
1427 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000
1428 #define BGE_FLOWATTN_RDBDI 0x00080000
1429 #define BGE_FLOWATTN_RXLS 0x00100000
1430 #define BGE_FLOWATTN_RXLP 0x00200000
1431 #define BGE_FLOWATTN_RBDC 0x00400000
1432 #define BGE_FLOWATTN_RBDI 0x00800000
1433 #define BGE_FLOWATTN_SDC 0x08000000
1434 #define BGE_FLOWATTN_SDI 0x10000000
1435 #define BGE_FLOWATTN_SRS 0x20000000
1436 #define BGE_FLOWATTN_SBDC 0x40000000
1437 #define BGE_FLOWATTN_SBDI 0x80000000
1438
1439 /*
1440 * Memory arbiter registers
1441 */
1442 #define BGE_MARB_MODE 0x4000
1443 #define BGE_MARB_STATUS 0x4004
1444 #define BGE_MARB_TRAPADDR_HI 0x4008
1445 #define BGE_MARB_TRAPADDR_LO 0x400C
1446
1447 /* Memory arbiter mode register */
1448 #define BGE_MARBMODE_RESET 0x00000001
1449 #define BGE_MARBMODE_ENABLE 0x00000002
1450 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004
1451 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008
1452 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010
1453 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020
1454 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040
1455 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080
1456 #define BGE_MARBMODE_PCI_TRAP 0x00000100
1457 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200
1458 #define BGE_MARBMODE_RXQ_TRAP 0x00000400
1459 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800
1460 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000
1461 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000
1462 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000
1463 #define BGE_MARBMODE_MBUF_TRAP 0x00008000
1464 #define BGE_MARBMODE_TXDI_TRAP 0x00010000
1465 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000
1466 #define BGE_MARBMODE_TXBD_TRAP 0x00040000
1467 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000
1468 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000
1469 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000
1470 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
1471 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000
1472 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000
1473 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000
1474
1475 /* Memory arbiter status register */
1476 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004
1477 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008
1478 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010
1479 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020
1480 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040
1481 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080
1482 #define BGE_MARBSTAT_PCI_TRAP 0x00000100
1483 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200
1484 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400
1485 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800
1486 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000
1487 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000
1488 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000
1489 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000
1490 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000
1491 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000
1492 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000
1493 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000
1494 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000
1495 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000
1496 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
1497 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000
1498 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000
1499 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000
1500
1501 /*
1502 * Buffer manager control registers
1503 */
1504 #define BGE_BMAN_MODE 0x4400
1505 #define BGE_BMAN_STATUS 0x4404
1506 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408
1507 #define BGE_BMAN_MBUFPOOL_LEN 0x440C
1508 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410
1509 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414
1510 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418
1511 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C
1512 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420
1513 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424
1514 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428
1515 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C
1516 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430
1517 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434
1518 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438
1519 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C
1520 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440
1521 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444
1522 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448
1523 #define BGE_BMAN_HWDIAG_1 0x444C
1524 #define BGE_BMAN_HWDIAG_2 0x4450
1525 #define BGE_BMAN_HWDIAG_3 0x4454
1526
1527 /* Buffer manager mode register */
1528 #define BGE_BMANMODE_RESET 0x00000001
1529 #define BGE_BMANMODE_ENABLE 0x00000002
1530 #define BGE_BMANMODE_ATTN 0x00000004
1531 #define BGE_BMANMODE_TESTMODE 0x00000008
1532 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010
1533 #define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000
1534
1535 /* Buffer manager status register */
1536 #define BGE_BMANSTAT_ERRO 0x00000004
1537 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
1538
1539 /*
1540 * Read DMA Control registers
1541 */
1542 #define BGE_RDMA_MODE 0x4800
1543 #define BGE_RDMA_STATUS 0x4804
1544 #define BGE_RDMA_RSRVCTRL_REG2 0x4890
1545 #define BGE_RDMA_LSO_CRPTEN_CTRL_REG2 0x48A0
1546 #define BGE_RDMA_RSRVCTRL 0x4900
1547 #define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910
1548
1549 /* Read DMA mode register */
1550 #define BGE_RDMAMODE_RESET 0x00000001
1551 #define BGE_RDMAMODE_ENABLE 0x00000002
1552 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1553 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1554 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010
1555 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1556 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1557 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1558 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1559 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
1560 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
1561 #define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800
1562 #define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000
1563 #define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000
1564 #define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000
1565 #define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000
1566 #define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000
1567 #define BGE_RDMAMODE_TSO4_ENABLE 0x08000000
1568 #define BGE_RDMAMODE_TSO6_ENABLE 0x10000000
1569 #define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000
1570
1571 /* Read DMA status register */
1572 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1573 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1574 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010
1575 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1576 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1577 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1578 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1579 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
1580
1581 /* Read DMA Reserved Control register */
1582 #define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
1583 #define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00
1584 #define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000
1585 #define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
1586 #define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0
1587 #define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000
1588 #define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000
1589
1590 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000
1591 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000
1592 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000
1593 #define BGE_RDMA_TX_LENGTH_WA_5719 0x02000000
1594 #define BGE_RDMA_TX_LENGTH_WA_5720 0x00200000
1595
1596 /* BD Read DMA Mode register */
1597 #define BGE_RDMA_BD_MODE 0x4A00
1598 /* BD Read DMA Mode status register */
1599 #define BGE_RDMA_BD_STATUS 0x4A04
1600
1601 #define BGE_RDMA_BD_MODE_RESET 0x00000001
1602 #define BGE_RDMA_BD_MODE_ENABLE 0x00000002
1603
1604 /* Non-LSO Read DMA Mode register */
1605 #define BGE_RDMA_NON_LSO_MODE 0x4B00
1606 /* Non-LSO Read DMA Mode status register */
1607 #define BGE_RDMA_NON_LSO_STATUS 0x4B04
1608
1609 #define BGE_RDMA_NON_LSO_MODE_RESET 0x00000001
1610 #define BGE_RDMA_NON_LSO_MODE_ENABLE 0x00000002
1611
1612 #define BGE_RDMA_LENGTH 0x4BE0
1613 #define BGE_NUM_RDMA_CHANNELS 4
1614
1615 /*
1616 * Write DMA control registers
1617 */
1618 #define BGE_WDMA_MODE 0x4C00
1619 #define BGE_WDMA_STATUS 0x4C04
1620
1621 /* Write DMA mode register */
1622 #define BGE_WDMAMODE_RESET 0x00000001
1623 #define BGE_WDMAMODE_ENABLE 0x00000002
1624 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1625 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1626 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010
1627 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1628 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1629 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1630 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1631 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
1632 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
1633 #define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000
1634 #define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000
1635
1636 /* Write DMA status register */
1637 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1638 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1639 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010
1640 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1641 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1642 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1643 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1644 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
1645
1646 /*
1647 * RX CPU registers
1648 */
1649 #define BGE_RXCPU_MODE 0x5000
1650 #define BGE_RXCPU_STATUS 0x5004
1651 #define BGE_RXCPU_PC 0x501C
1652
1653 /* RX CPU mode register */
1654 #define BGE_RXCPUMODE_RESET 0x00000001
1655 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002
1656 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004
1657 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1658 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010
1659 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020
1660 #define BGE_RXCPUMODE_ROMFAIL 0x00000040
1661 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080
1662 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100
1663 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1664 #define BGE_RXCPUMODE_HALTCPU 0x00000400
1665 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800
1666 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1667 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000
1668
1669 /* RX CPU status register */
1670 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001
1671 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1672 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004
1673 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008
1674 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010
1675 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020
1676 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1677 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080
1678 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100
1679 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200
1680 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000
1681 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000
1682 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1683 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1684 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1685 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1686 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000
1687
1688 /*
1689 * V? CPU registers
1690 */
1691 #define BGE_VCPU_STATUS 0x5100
1692 #define BGE_VCPU_EXT_CTRL 0x6890
1693
1694 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000
1695 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000
1696
1697 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1698 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1699
1700 /*
1701 * TX CPU registers
1702 */
1703 #define BGE_TXCPU_MODE 0x5400
1704 #define BGE_TXCPU_STATUS 0x5404
1705 #define BGE_TXCPU_PC 0x541C
1706
1707 /* TX CPU mode register */
1708 #define BGE_TXCPUMODE_RESET 0x00000001
1709 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002
1710 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004
1711 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1712 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010
1713 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020
1714 #define BGE_TXCPUMODE_ROMFAIL 0x00000040
1715 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080
1716 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100
1717 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1718 #define BGE_TXCPUMODE_HALTCPU 0x00000400
1719 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800
1720 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1721
1722 /* TX CPU status register */
1723 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001
1724 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1725 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004
1726 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008
1727 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010
1728 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020
1729 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1730 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080
1731 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100
1732 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200
1733 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000
1734 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000
1735 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1736 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1737 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1738 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1739 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
1740
1741 /*
1742 * Low priority mailbox registers
1743 */
1744 #define BGE_LPMBX_IRQ0_HI 0x5800
1745 #define BGE_LPMBX_IRQ0_LO 0x5804
1746 #define BGE_LPMBX_IRQ1_HI 0x5808
1747 #define BGE_LPMBX_IRQ1_LO 0x580C
1748 #define BGE_LPMBX_IRQ2_HI 0x5810
1749 #define BGE_LPMBX_IRQ2_LO 0x5814
1750 #define BGE_LPMBX_IRQ3_HI 0x5818
1751 #define BGE_LPMBX_IRQ3_LO 0x581C
1752 #define BGE_LPMBX_GEN0_HI 0x5820
1753 #define BGE_LPMBX_GEN0_LO 0x5824
1754 #define BGE_LPMBX_GEN1_HI 0x5828
1755 #define BGE_LPMBX_GEN1_LO 0x582C
1756 #define BGE_LPMBX_GEN2_HI 0x5830
1757 #define BGE_LPMBX_GEN2_LO 0x5834
1758 #define BGE_LPMBX_GEN3_HI 0x5828
1759 #define BGE_LPMBX_GEN3_LO 0x582C
1760 #define BGE_LPMBX_GEN4_HI 0x5840
1761 #define BGE_LPMBX_GEN4_LO 0x5844
1762 #define BGE_LPMBX_GEN5_HI 0x5848
1763 #define BGE_LPMBX_GEN5_LO 0x584C
1764 #define BGE_LPMBX_GEN6_HI 0x5850
1765 #define BGE_LPMBX_GEN6_LO 0x5854
1766 #define BGE_LPMBX_GEN7_HI 0x5858
1767 #define BGE_LPMBX_GEN7_LO 0x585C
1768 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860
1769 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864
1770 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868
1771 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C
1772 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870
1773 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874
1774 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878
1775 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C
1776 #define BGE_LPMBX_RX_CONS0_HI 0x5880
1777 #define BGE_LPMBX_RX_CONS0_LO 0x5884
1778 #define BGE_LPMBX_RX_CONS1_HI 0x5888
1779 #define BGE_LPMBX_RX_CONS1_LO 0x588C
1780 #define BGE_LPMBX_RX_CONS2_HI 0x5890
1781 #define BGE_LPMBX_RX_CONS2_LO 0x5894
1782 #define BGE_LPMBX_RX_CONS3_HI 0x5898
1783 #define BGE_LPMBX_RX_CONS3_LO 0x589C
1784 #define BGE_LPMBX_RX_CONS4_HI 0x58A0
1785 #define BGE_LPMBX_RX_CONS4_LO 0x58A4
1786 #define BGE_LPMBX_RX_CONS5_HI 0x58A8
1787 #define BGE_LPMBX_RX_CONS5_LO 0x58AC
1788 #define BGE_LPMBX_RX_CONS6_HI 0x58B0
1789 #define BGE_LPMBX_RX_CONS6_LO 0x58B4
1790 #define BGE_LPMBX_RX_CONS7_HI 0x58B8
1791 #define BGE_LPMBX_RX_CONS7_LO 0x58BC
1792 #define BGE_LPMBX_RX_CONS8_HI 0x58C0
1793 #define BGE_LPMBX_RX_CONS8_LO 0x58C4
1794 #define BGE_LPMBX_RX_CONS9_HI 0x58C8
1795 #define BGE_LPMBX_RX_CONS9_LO 0x58CC
1796 #define BGE_LPMBX_RX_CONS10_HI 0x58D0
1797 #define BGE_LPMBX_RX_CONS10_LO 0x58D4
1798 #define BGE_LPMBX_RX_CONS11_HI 0x58D8
1799 #define BGE_LPMBX_RX_CONS11_LO 0x58DC
1800 #define BGE_LPMBX_RX_CONS12_HI 0x58E0
1801 #define BGE_LPMBX_RX_CONS12_LO 0x58E4
1802 #define BGE_LPMBX_RX_CONS13_HI 0x58E8
1803 #define BGE_LPMBX_RX_CONS13_LO 0x58EC
1804 #define BGE_LPMBX_RX_CONS14_HI 0x58F0
1805 #define BGE_LPMBX_RX_CONS14_LO 0x58F4
1806 #define BGE_LPMBX_RX_CONS15_HI 0x58F8
1807 #define BGE_LPMBX_RX_CONS15_LO 0x58FC
1808 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900
1809 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904
1810 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908
1811 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C
1812 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910
1813 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914
1814 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918
1815 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C
1816 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920
1817 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924
1818 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928
1819 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C
1820 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930
1821 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934
1822 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938
1823 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C
1824 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940
1825 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944
1826 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948
1827 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C
1828 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950
1829 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954
1830 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958
1831 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C
1832 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960
1833 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964
1834 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968
1835 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C
1836 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970
1837 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974
1838 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978
1839 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C
1840 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980
1841 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984
1842 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988
1843 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C
1844 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990
1845 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994
1846 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998
1847 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C
1848 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0
1849 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4
1850 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8
1851 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC
1852 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0
1853 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4
1854 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8
1855 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC
1856 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0
1857 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4
1858 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8
1859 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC
1860 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0
1861 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4
1862 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8
1863 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC
1864 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0
1865 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4
1866 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8
1867 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC
1868 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0
1869 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4
1870 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8
1871 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC
1872
1873 /*
1874 * Flow throw Queue reset register
1875 */
1876 #define BGE_FTQ_RESET 0x5C00
1877
1878 #define BGE_FTQRESET_DMAREAD 0x00000002
1879 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004
1880 #define BGE_FTQRESET_DMADONE 0x00000010
1881 #define BGE_FTQRESET_SBDC 0x00000020
1882 #define BGE_FTQRESET_SDI 0x00000040
1883 #define BGE_FTQRESET_WDMA 0x00000080
1884 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100
1885 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200
1886 #define BGE_FTQRESET_SDC 0x00000400
1887 #define BGE_FTQRESET_HCC 0x00000800
1888 #define BGE_FTQRESET_TXFIFO 0x00001000
1889 #define BGE_FTQRESET_MBC 0x00002000
1890 #define BGE_FTQRESET_RBDC 0x00004000
1891 #define BGE_FTQRESET_RXLP 0x00008000
1892 #define BGE_FTQRESET_RDBDI 0x00010000
1893 #define BGE_FTQRESET_RDC 0x00020000
1894 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000
1895
1896 /*
1897 * Message Signaled Interrupt registers
1898 */
1899 #define BGE_MSI_MODE 0x6000
1900 #define BGE_MSI_STATUS 0x6004
1901 #define BGE_MSI_FIFOACCESS 0x6008
1902
1903 /* MSI mode register */
1904 #define BGE_MSIMODE_RESET 0x00000001
1905 #define BGE_MSIMODE_ENABLE 0x00000002
1906 #define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020
1907 #define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080
1908
1909 /* MSI status register */
1910 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
1911 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1912 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010
1913 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
1914 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
1915
1916 /*
1917 * DMA Completion registers
1918 */
1919 #define BGE_DMAC_MODE 0x6400
1920
1921 /* DMA Completion mode register */
1922 #define BGE_DMACMODE_RESET 0x00000001
1923 #define BGE_DMACMODE_ENABLE 0x00000002
1924
1925 /*
1926 * General control registers.
1927 */
1928 #define BGE_MODE_CTL 0x6800
1929 #define BGE_MISC_CFG 0x6804
1930 #define BGE_MISC_LOCAL_CTL 0x6808
1931 #define BGE_RX_CPU_EVENT 0x6810
1932 #define BGE_TX_CPU_EVENT 0x6820
1933 #define BGE_EE_ADDR 0x6838
1934 #define BGE_EE_DATA 0x683C
1935 #define BGE_EE_CTL 0x6840
1936 #define BGE_MDI_CTL 0x6844
1937 #define BGE_EE_DELAY 0x6848
1938 #define BGE_FASTBOOT_PC 0x6894
1939
1940 #define BGE_RX_CPU_DRV_EVENT 0x00004000
1941
1942 /*
1943 * NVRAM Control registers
1944 */
1945 #define BGE_NVRAM_CMD 0x7000
1946 #define BGE_NVRAM_STAT 0x7004
1947 #define BGE_NVRAM_WRDATA 0x7008
1948 #define BGE_NVRAM_ADDR 0x700c
1949 #define BGE_NVRAM_RDDATA 0x7010
1950 #define BGE_NVRAM_CFG1 0x7014
1951 #define BGE_NVRAM_CFG2 0x7018
1952 #define BGE_NVRAM_CFG3 0x701c
1953 #define BGE_NVRAM_SWARB 0x7020
1954 #define BGE_NVRAM_ACCESS 0x7024
1955 #define BGE_NVRAM_WRITE1 0x7028
1956
1957 #define BGE_NVRAMCMD_RESET 0x00000001
1958 #define BGE_NVRAMCMD_DONE 0x00000008
1959 #define BGE_NVRAMCMD_START 0x00000010
1960 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */
1961 #define BGE_NVRAMCMD_ERASE 0x00000040
1962 #define BGE_NVRAMCMD_FIRST 0x00000080
1963 #define BGE_NVRAMCMD_LAST 0x00000100
1964
1965 #define BGE_NVRAM_READCMD \
1966 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1967 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE)
1968 #define BGE_NVRAM_WRITECMD \
1969 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1970 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR)
1971
1972 #define BGE_NVRAMSWARB_SET0 0x00000001
1973 #define BGE_NVRAMSWARB_SET1 0x00000002
1974 #define BGE_NVRAMSWARB_SET2 0x00000003
1975 #define BGE_NVRAMSWARB_SET3 0x00000004
1976 #define BGE_NVRAMSWARB_CLR0 0x00000010
1977 #define BGE_NVRAMSWARB_CLR1 0x00000020
1978 #define BGE_NVRAMSWARB_CLR2 0x00000040
1979 #define BGE_NVRAMSWARB_CLR3 0x00000080
1980 #define BGE_NVRAMSWARB_GNT0 0x00000100
1981 #define BGE_NVRAMSWARB_GNT1 0x00000200
1982 #define BGE_NVRAMSWARB_GNT2 0x00000400
1983 #define BGE_NVRAMSWARB_GNT3 0x00000800
1984 #define BGE_NVRAMSWARB_REQ0 0x00001000
1985 #define BGE_NVRAMSWARB_REQ1 0x00002000
1986 #define BGE_NVRAMSWARB_REQ2 0x00004000
1987 #define BGE_NVRAMSWARB_REQ3 0x00008000
1988
1989 #define BGE_NVRAMACC_ENABLE 0x00000001
1990 #define BGE_NVRAMACC_WRENABLE 0x00000002
1991
1992 /* Mode control register */
1993 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
1994 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002
1995 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004
1996 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010
1997 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020
1998 #define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040
1999 #define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080
2000 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200
2001 #define BGE_MODECTL_NO_RX_CRC 0x00000400
2002 #define BGE_MODECTL_RX_BADFRAMES 0x00000800
2003 #define BGE_MODECTL_NO_TX_INTR 0x00002000
2004 #define BGE_MODECTL_NO_RX_INTR 0x00004000
2005 #define BGE_MODECTL_FORCE_PCI32 0x00008000
2006 #define BGE_MODECTL_B2HRX_ENABLE 0x00008000
2007 #define BGE_MODECTL_STACKUP 0x00010000
2008 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000
2009 #define BGE_MODECTL_HTX2B_ENABLE 0x00040000
2010 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000
2011 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000
2012 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000
2013 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000
2014 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000
2015 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000
2016 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000
2017 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000
2018 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000
2019
2020 /* Misc. config register */
2021 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001
2022 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE
2023 #define BGE_MISCCFG_BOARD_ID_MASK 0x0001E000
2024 #define BGE_MISCCFG_BOARD_ID_5704 0x00000000
2025 #define BGE_MISCCFG_BOARD_ID_5704CIOBE 0x00004000
2026 #define BGE_MISCCFG_BOARD_ID_5788 0x00010000
2027 #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000
2028 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000
2029 #define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000
2030
2031 #define BGE_32BITTIME_66MHZ (0x41 << 1)
2032
2033 /* Misc. Local Control */
2034 #define BGE_MLC_INTR_STATE 0x00000001
2035 #define BGE_MLC_INTR_CLR 0x00000002
2036 #define BGE_MLC_INTR_SET 0x00000004
2037 #define BGE_MLC_INTR_ONATTN 0x00000008
2038 #define BGE_MLC_MISCIO_IN0 0x00000100
2039 #define BGE_MLC_MISCIO_IN1 0x00000200
2040 #define BGE_MLC_MISCIO_IN2 0x00000400
2041 #define BGE_MLC_MISCIO_OUTEN0 0x00000800
2042 #define BGE_MLC_MISCIO_OUTEN1 0x00001000
2043 #define BGE_MLC_MISCIO_OUTEN2 0x00002000
2044 #define BGE_MLC_MISCIO_OUT0 0x00004000
2045 #define BGE_MLC_MISCIO_OUT1 0x00008000
2046 #define BGE_MLC_MISCIO_OUT2 0x00010000
2047 #define BGE_MLC_EXTRAM_ENB 0x00020000
2048 #define BGE_MLC_SRAM_SIZE 0x001C0000
2049 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */
2050 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */
2051 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000
2052 #define BGE_MLC_AUTO_EEPROM 0x01000000
2053
2054 #define BGE_SSRAMSIZE_256KB 0x00000000
2055 #define BGE_SSRAMSIZE_512KB 0x00040000
2056 #define BGE_SSRAMSIZE_1MB 0x00080000
2057 #define BGE_SSRAMSIZE_2MB 0x000C0000
2058 #define BGE_SSRAMSIZE_4MB 0x00100000
2059 #define BGE_SSRAMSIZE_8MB 0x00140000
2060 #define BGE_SSRAMSIZE_16M 0x00180000
2061
2062 /* EEPROM address register */
2063 #define BGE_EEADDR_ADDRESS 0x0000FFFC
2064 #define BGE_EEADDR_HALFCLK 0x01FF0000
2065 #define BGE_EEADDR_START 0x02000000
2066 #define BGE_EEADDR_DEVID 0x1C000000
2067 #define BGE_EEADDR_RESET 0x20000000
2068 #define BGE_EEADDR_DONE 0x40000000
2069 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */
2070
2071 #define BGE_EEDEVID(x) ((x & 7) << 26)
2072 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16)
2073 #define BGE_HALFCLK_384SCL 0x60
2074 #define BGE_EE_READCMD \
2075 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
2076 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
2077 #define BGE_EE_WRCMD \
2078 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
2079 BGE_EEADDR_START|BGE_EEADDR_DONE)
2080
2081 /* EEPROM Control register */
2082 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001
2083 #define BGE_EECTL_CLKOUT 0x00000002
2084 #define BGE_EECTL_CLKIN 0x00000004
2085 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008
2086 #define BGE_EECTL_DATAOUT 0x00000010
2087 #define BGE_EECTL_DATAIN 0x00000020
2088
2089 /* MDI (MII/GMII) access register */
2090 #define BGE_MDI_DATA 0x00000001
2091 #define BGE_MDI_DIR 0x00000002
2092 #define BGE_MDI_SEL 0x00000004
2093 #define BGE_MDI_CLK 0x00000008
2094
2095 #define BGE_MEMWIN_START 0x00008000
2096 #define BGE_MEMWIN_END 0x0000FFFF
2097
2098 /* BAR1 (APE) Register Definitions */
2099
2100 #define BGE_APE_GPIO_MSG 0x0008
2101 #define BGE_APE_EVENT 0x000C
2102 #define BGE_APE_LOCK_REQ 0x002C
2103 #define BGE_APE_LOCK_GRANT 0x004C
2104
2105 #define BGE_APE_GPIO_MSG_SHIFT 4
2106
2107 #define BGE_APE_EVENT_1 0x00000001
2108
2109 #define BGE_APE_LOCK_REQ_DRIVER0 0x00001000
2110
2111 #define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000
2112
2113 /* APE Shared Memory block (writable by APE only) */
2114 #define BGE_APE_SEG_SIG 0x4000
2115 #define BGE_APE_FW_STATUS 0x400C
2116 #define BGE_APE_FW_FEATURES 0x4010
2117 #define BGE_APE_FW_BEHAVIOR 0x4014
2118 #define BGE_APE_FW_VERSION 0x4018
2119 #define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024
2120 #define BGE_APE_FW_HEARTBEAT 0x4028
2121 #define BGE_APE_FW_ERROR_FLAGS 0x4074
2122
2123 #define BGE_APE_SEG_SIG_MAGIC 0x41504521
2124
2125 #define BGE_APE_FW_STATUS_READY 0x00000100
2126
2127 #define BGE_APE_FW_FEATURE_DASH 0x00000001
2128 #define BGE_APE_FW_FEATURE_NCSI 0x00000002
2129
2130 #define BGE_APE_FW_VERSION_MAJMSK 0xFF000000
2131 #define BGE_APE_FW_VERSION_MAJSFT 24
2132 #define BGE_APE_FW_VERSION_MINMSK 0x00FF0000
2133 #define BGE_APE_FW_VERSION_MINSFT 16
2134 #define BGE_APE_FW_VERSION_REVMSK 0x0000FF00
2135 #define BGE_APE_FW_VERSION_REVSFT 8
2136 #define BGE_APE_FW_VERSION_BLDMSK 0x000000FF
2137
2138 /* Host Shared Memory block (writable by host only) */
2139 #define BGE_APE_HOST_SEG_SIG 0x4200
2140 #define BGE_APE_HOST_SEG_LEN 0x4204
2141 #define BGE_APE_HOST_INIT_COUNT 0x4208
2142 #define BGE_APE_HOST_DRIVER_ID 0x420C
2143 #define BGE_APE_HOST_BEHAVIOR 0x4210
2144 #define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214
2145 #define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218
2146 #define BGE_APE_HOST_DRVR_STATE 0x421C
2147 #define BGE_APE_HOST_WOL_SPEED 0x4224
2148
2149 #define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354
2150
2151 #define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020
2152
2153 #define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000
2154 #define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \
2155 (BGE_APE_HOST_DRIVER_ID_FBSD | \
2156 ((maj) & 0xffd) << 16 | ((min) & 0xff) << 8)
2157
2158 #define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
2159
2160 #define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0
2161 #define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000
2162
2163 #define BGE_APE_HOST_DRVR_STATE_START 0x00000001
2164 #define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002
2165 #define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003
2166 #define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004
2167
2168 #define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000
2169
2170 #define BGE_APE_EVENT_STATUS 0x4300
2171
2172 #define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
2173 #define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500
2174 #define BGE_APE_EVENT_STATUS_STATE_START 0x00010000
2175 #define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
2176 #define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000
2177 #define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
2178 #define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000
2179
2180 #define BGE_APE_DEBUG_LOG 0x4E00
2181 #define BGE_APE_DEBUG_LOG_LEN 0x0100
2182
2183 #define BGE_APE_PER_LOCK_REQ 0x8400
2184 #define BGE_APE_PER_LOCK_GRANT 0x8420
2185
2186 #define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000
2187 #define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002
2188 #define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004
2189 #define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008
2190
2191 #define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000
2192 #define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002
2193 #define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004
2194 #define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008
2195
2196 /* APE Mutex Resources */
2197 #define BGE_APE_LOCK_PHY0 0
2198 #define BGE_APE_LOCK_GRC 1
2199 #define BGE_APE_LOCK_PHY1 2
2200 #define BGE_APE_LOCK_PHY2 3
2201 #define BGE_APE_LOCK_MEM 4
2202 #define BGE_APE_LOCK_PHY3 5
2203 #define BGE_APE_LOCK_GPIO 7
2204
2205 #define BGE_MEMWIN_READ(sc, x, val) \
2206 do { \
2207 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
2208 (0xFFFF0000 & x), 4); \
2209 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
2210 } while(0)
2211
2212 #define BGE_MEMWIN_WRITE(sc, x, val) \
2213 do { \
2214 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
2215 (0xFFFF0000 & x), 4); \
2216 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
2217 } while(0)
2218
2219 /*
2220 * This magic number is written to the firmware mailbox at 0xb50
2221 * before a software reset is issued. After the internal firmware
2222 * has completed its initialization it will write the opposite of
2223 * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location,
2224 * allowing the driver to synchronize with the firmware.
2225 */
2226 #define BGE_SRAM_FW_MB_MAGIC 0x4B657654
2227
2228 typedef struct {
2229 uint32_t bge_addr_hi;
2230 uint32_t bge_addr_lo;
2231 } bge_hostaddr;
2232
2233 #define BGE_HOSTADDR(x, y) \
2234 do { \
2235 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \
2236 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \
2237 } while(0)
2238
2239 #define BGE_ADDR_LO(y) \
2240 ((uint64_t) (y) & 0xFFFFFFFF)
2241 #define BGE_ADDR_HI(y) \
2242 ((uint64_t) (y) >> 32)
2243
2244 /* Ring control block structure */
2245 struct bge_rcb {
2246 bge_hostaddr bge_hostaddr;
2247 uint32_t bge_maxlen_flags;
2248 uint32_t bge_nicaddr;
2249 };
2250
2251 #define RCB_WRITE_4(sc, rcb, offset, val) \
2252 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val)
2253 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags))
2254
2255 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001
2256 #define BGE_RCB_FLAG_RING_DISABLED 0x0002
2257
2258 struct bge_tx_bd {
2259 bge_hostaddr bge_addr;
2260 #if BYTE_ORDER == LITTLE_ENDIAN
2261 uint16_t bge_flags;
2262 uint16_t bge_len;
2263 uint16_t bge_vlan_tag;
2264 uint16_t bge_mss;
2265 #else
2266 uint16_t bge_len;
2267 uint16_t bge_flags;
2268 uint16_t bge_mss;
2269 uint16_t bge_vlan_tag;
2270 #endif
2271 };
2272
2273 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001
2274 #define BGE_TXBDFLAG_IP_CSUM 0x0002
2275 #define BGE_TXBDFLAG_END 0x0004
2276 #define BGE_TXBDFLAG_IP_FRAG 0x0008
2277 #define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */
2278 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010
2279 #define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */
2280 #define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */
2281 #define BGE_TXBDFLAG_VLAN_TAG 0x0040
2282 #define BGE_TXBDFLAG_COAL_NOW 0x0080
2283 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100
2284 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200
2285 #define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */
2286 #define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */
2287 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000
2288 #define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */
2289 #define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */
2290 #define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */
2291 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000
2292 #define BGE_TXBDFLAG_NO_CRC 0x8000
2293
2294 #define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */
2295 /* Bits [1:0] of the MSS header length. */
2296 #define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */
2297
2298 #define BGE_NIC_TXRING_ADDR(ringno, size) \
2299 BGE_SEND_RING_1_TO_4 + \
2300 ((ringno * sizeof(struct bge_tx_bd) * size) / 4)
2301
2302 struct bge_rx_bd {
2303 bge_hostaddr bge_addr;
2304 #if BYTE_ORDER == LITTLE_ENDIAN
2305 uint16_t bge_len;
2306 uint16_t bge_idx;
2307 uint16_t bge_flags;
2308 uint16_t bge_type;
2309 uint16_t bge_tcp_udp_csum;
2310 uint16_t bge_ip_csum;
2311 uint16_t bge_vlan_tag;
2312 uint16_t bge_error_flag;
2313 #else
2314 uint16_t bge_idx;
2315 uint16_t bge_len;
2316 uint16_t bge_type;
2317 uint16_t bge_flags;
2318 uint16_t bge_ip_csum;
2319 uint16_t bge_tcp_udp_csum;
2320 uint16_t bge_error_flag;
2321 uint16_t bge_vlan_tag;
2322 #endif
2323 uint32_t bge_rsvd;
2324 uint32_t bge_opaque;
2325 };
2326
2327 struct bge_extrx_bd {
2328 bge_hostaddr bge_addr1;
2329 bge_hostaddr bge_addr2;
2330 bge_hostaddr bge_addr3;
2331 #if BYTE_ORDER == LITTLE_ENDIAN
2332 uint16_t bge_len2;
2333 uint16_t bge_len1;
2334 uint16_t bge_rsvd1;
2335 uint16_t bge_len3;
2336 #else
2337 uint16_t bge_len1;
2338 uint16_t bge_len2;
2339 uint16_t bge_len3;
2340 uint16_t bge_rsvd1;
2341 #endif
2342 bge_hostaddr bge_addr0;
2343 #if BYTE_ORDER == LITTLE_ENDIAN
2344 uint16_t bge_len0;
2345 uint16_t bge_idx;
2346 uint16_t bge_flags;
2347 uint16_t bge_type;
2348 uint16_t bge_tcp_udp_csum;
2349 uint16_t bge_ip_csum;
2350 uint16_t bge_vlan_tag;
2351 uint16_t bge_error_flag;
2352 #else
2353 uint16_t bge_idx;
2354 uint16_t bge_len0;
2355 uint16_t bge_type;
2356 uint16_t bge_flags;
2357 uint16_t bge_ip_csum;
2358 uint16_t bge_tcp_udp_csum;
2359 uint16_t bge_error_flag;
2360 uint16_t bge_vlan_tag;
2361 #endif
2362 uint32_t bge_rsvd0;
2363 uint32_t bge_opaque;
2364 };
2365
2366 #define BGE_RXBDFLAG_END 0x0004
2367 #define BGE_RXBDFLAG_JUMBO_RING 0x0020
2368 #define BGE_RXBDFLAG_VLAN_TAG 0x0040
2369 #define BGE_RXBDFLAG_ERROR 0x0400
2370 #define BGE_RXBDFLAG_MINI_RING 0x0800
2371 #define BGE_RXBDFLAG_IP_CSUM 0x1000
2372 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
2373 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
2374 #define BGE_RXBDFLAG_IPV6 0x8000
2375
2376 #define BGE_RXERRFLAG_BAD_CRC 0x0001
2377 #define BGE_RXERRFLAG_COLL_DETECT 0x0002
2378 #define BGE_RXERRFLAG_LINK_LOST 0x0004
2379 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008
2380 #define BGE_RXERRFLAG_MAC_ABORT 0x0010
2381 #define BGE_RXERRFLAG_RUNT 0x0020
2382 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
2383 #define BGE_RXERRFLAG_GIANT 0x0080
2384 #define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */
2385
2386 struct bge_sts_idx {
2387 #if BYTE_ORDER == LITTLE_ENDIAN
2388 uint16_t bge_rx_prod_idx;
2389 uint16_t bge_tx_cons_idx;
2390 #else
2391 uint16_t bge_tx_cons_idx;
2392 uint16_t bge_rx_prod_idx;
2393 #endif
2394 };
2395
2396 struct bge_status_block {
2397 uint32_t bge_status;
2398 uint32_t bge_status_tag;
2399 #if BYTE_ORDER == LITTLE_ENDIAN
2400 uint16_t bge_rx_jumbo_cons_idx;
2401 uint16_t bge_rx_std_cons_idx;
2402 uint16_t bge_rx_mini_cons_idx;
2403 uint16_t bge_rsvd1;
2404 #else
2405 uint16_t bge_rx_std_cons_idx;
2406 uint16_t bge_rx_jumbo_cons_idx;
2407 uint16_t bge_rsvd1;
2408 uint16_t bge_rx_mini_cons_idx;
2409 #endif
2410 struct bge_sts_idx bge_idx[16];
2411 };
2412
2413 #define BGE_STATFLAG_UPDATED 0x00000001
2414 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
2415 #define BGE_STATFLAG_ERROR 0x00000004
2416
2417 /*
2418 * Broadcom Vendor ID
2419 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID
2420 * even though they're now manufactured by Broadcom)
2421 */
2422 #define BCOM_VENDORID 0x14E4
2423 #define BCOM_DEVICEID_BCM5700 0x1644
2424 #define BCOM_DEVICEID_BCM5701 0x1645
2425 #define BCOM_DEVICEID_BCM5702 0x1646
2426 #define BCOM_DEVICEID_BCM5702X 0x16A6
2427 #define BCOM_DEVICEID_BCM5702_ALT 0x16C6
2428 #define BCOM_DEVICEID_BCM5703 0x1647
2429 #define BCOM_DEVICEID_BCM5703X 0x16A7
2430 #define BCOM_DEVICEID_BCM5703_ALT 0x16C7
2431 #define BCOM_DEVICEID_BCM5704C 0x1648
2432 #define BCOM_DEVICEID_BCM5704S 0x16A8
2433 #define BCOM_DEVICEID_BCM5704S_ALT 0x1649
2434 #define BCOM_DEVICEID_BCM5705 0x1653
2435 #define BCOM_DEVICEID_BCM5705K 0x1654
2436 #define BCOM_DEVICEID_BCM5705F 0x166E
2437 #define BCOM_DEVICEID_BCM5705M 0x165D
2438 #define BCOM_DEVICEID_BCM5705M_ALT 0x165E
2439 #define BCOM_DEVICEID_BCM5714C 0x1668
2440 #define BCOM_DEVICEID_BCM5714S 0x1669
2441 #define BCOM_DEVICEID_BCM5715 0x1678
2442 #define BCOM_DEVICEID_BCM5715S 0x1679
2443 #define BCOM_DEVICEID_BCM5717 0x1655
2444 #define BCOM_DEVICEID_BCM5717C 0x1665
2445 #define BCOM_DEVICEID_BCM5718 0x1656
2446 #define BCOM_DEVICEID_BCM5719 0x1657
2447 #define BCOM_DEVICEID_BCM5720_PP 0x1658 /* Not released to public. */
2448 #define BCOM_DEVICEID_BCM5720 0x165F
2449 #define BCOM_DEVICEID_BCM5721 0x1659
2450 #define BCOM_DEVICEID_BCM5722 0x165A
2451 #define BCOM_DEVICEID_BCM5723 0x165B
2452 #define BCOM_DEVICEID_BCM5725 0x1643
2453 #define BCOM_DEVICEID_BCM5727 0x16F3
2454 #define BCOM_DEVICEID_BCM5750 0x1676
2455 #define BCOM_DEVICEID_BCM5750M 0x167C
2456 #define BCOM_DEVICEID_BCM5751 0x1677
2457 #define BCOM_DEVICEID_BCM5751F 0x167E
2458 #define BCOM_DEVICEID_BCM5751M 0x167D
2459 #define BCOM_DEVICEID_BCM5752 0x1600
2460 #define BCOM_DEVICEID_BCM5752M 0x1601
2461 #define BCOM_DEVICEID_BCM5753 0x16F7
2462 #define BCOM_DEVICEID_BCM5753F 0x16FE
2463 #define BCOM_DEVICEID_BCM5753M 0x16FD
2464 #define BCOM_DEVICEID_BCM5754 0x167A
2465 #define BCOM_DEVICEID_BCM5754M 0x1672
2466 #define BCOM_DEVICEID_BCM5755 0x167B
2467 #define BCOM_DEVICEID_BCM5755M 0x1673
2468 #define BCOM_DEVICEID_BCM5756 0x1674
2469 #define BCOM_DEVICEID_BCM5761 0x1681
2470 #define BCOM_DEVICEID_BCM5761E 0x1680
2471 #define BCOM_DEVICEID_BCM5761S 0x1688
2472 #define BCOM_DEVICEID_BCM5761SE 0x1689
2473 #define BCOM_DEVICEID_BCM5762 0x1687
2474 #define BCOM_DEVICEID_BCM5764 0x1684
2475 #define BCOM_DEVICEID_BCM5780 0x166A
2476 #define BCOM_DEVICEID_BCM5780S 0x166B
2477 #define BCOM_DEVICEID_BCM5781 0x16DD
2478 #define BCOM_DEVICEID_BCM5782 0x1696
2479 #define BCOM_DEVICEID_BCM5784 0x1698
2480 #define BCOM_DEVICEID_BCM5785F 0x16a0
2481 #define BCOM_DEVICEID_BCM5785G 0x1699
2482 #define BCOM_DEVICEID_BCM5786 0x169A
2483 #define BCOM_DEVICEID_BCM5787 0x169B
2484 #define BCOM_DEVICEID_BCM5787M 0x1693
2485 #define BCOM_DEVICEID_BCM5787F 0x167f
2486 #define BCOM_DEVICEID_BCM5788 0x169C
2487 #define BCOM_DEVICEID_BCM5789 0x169D
2488 #define BCOM_DEVICEID_BCM5901 0x170D
2489 #define BCOM_DEVICEID_BCM5901A2 0x170E
2490 #define BCOM_DEVICEID_BCM5903M 0x16FF
2491 #define BCOM_DEVICEID_BCM5906 0x1712
2492 #define BCOM_DEVICEID_BCM5906M 0x1713
2493 #define BCOM_DEVICEID_BCM57760 0x1690
2494 #define BCOM_DEVICEID_BCM57761 0x16B0
2495 #define BCOM_DEVICEID_BCM57762 0x1682
2496 #define BCOM_DEVICEID_BCM57764 0x1642
2497 #define BCOM_DEVICEID_BCM57765 0x16B4
2498 #define BCOM_DEVICEID_BCM57766 0x1686
2499 #define BCOM_DEVICEID_BCM57767 0x1683
2500 #define BCOM_DEVICEID_BCM57780 0x1692
2501 #define BCOM_DEVICEID_BCM57781 0x16B1
2502 #define BCOM_DEVICEID_BCM57782 0x16B7
2503 #define BCOM_DEVICEID_BCM57785 0x16B5
2504 #define BCOM_DEVICEID_BCM57786 0x16B3
2505 #define BCOM_DEVICEID_BCM57787 0x1641
2506 #define BCOM_DEVICEID_BCM57788 0x1691
2507 #define BCOM_DEVICEID_BCM57790 0x1694
2508 #define BCOM_DEVICEID_BCM57791 0x16B2
2509 #define BCOM_DEVICEID_BCM57795 0x16B6
2510
2511 /*
2512 * Alteon AceNIC PCI vendor/device ID.
2513 */
2514 #define ALTEON_VENDORID 0x12AE
2515 #define ALTEON_DEVICEID_ACENIC 0x0001
2516 #define ALTEON_DEVICEID_ACENIC_COPPER 0x0002
2517 #define ALTEON_DEVICEID_BCM5700 0x0003
2518 #define ALTEON_DEVICEID_BCM5701 0x0004
2519
2520 /*
2521 * 3Com 3c996 PCI vendor/device ID.
2522 */
2523 #define TC_VENDORID 0x10B7
2524 #define TC_DEVICEID_3C996 0x0003
2525
2526 /*
2527 * SysKonnect PCI vendor ID
2528 */
2529 #define SK_VENDORID 0x1148
2530 #define SK_DEVICEID_ALTIMA 0x4400
2531 #define SK_SUBSYSID_9D21 0x4421
2532 #define SK_SUBSYSID_9D41 0x4441
2533
2534 /*
2535 * Altima PCI vendor/device ID.
2536 */
2537 #define ALTIMA_VENDORID 0x173b
2538 #define ALTIMA_DEVICE_AC1000 0x03e8
2539 #define ALTIMA_DEVICE_AC1002 0x03e9
2540 #define ALTIMA_DEVICE_AC9100 0x03ea
2541
2542 /*
2543 * Dell PCI vendor ID
2544 */
2545
2546 #define DELL_VENDORID 0x1028
2547
2548 /*
2549 * Apple PCI vendor ID.
2550 */
2551 #define APPLE_VENDORID 0x106b
2552 #define APPLE_DEVICE_BCM5701 0x1645
2553
2554 /*
2555 * Fujitsu vendor/device IDs
2556 */
2557 #define FJTSU_VENDORID 0x10cf
2558 #define FJTSU_DEVICEID_PW008GE5 0x11a1
2559 #define FJTSU_DEVICEID_PW008GE4 0x11a2
2560
2561 /*
2562 * Offset of MAC address inside EEPROM.
2563 */
2564 #define BGE_EE_MAC_OFFSET 0x7C
2565 #define BGE_EE_MAC_OFFSET_5906 0x10
2566 #define BGE_EE_HWCFG_OFFSET 0xC8
2567
2568 #define BGE_HWCFG_VOLTAGE 0x00000003
2569 #define BGE_HWCFG_PHYLED_MODE 0x0000000C
2570 #define BGE_HWCFG_MEDIA 0x00000030
2571 #define BGE_HWCFG_ASF 0x00000080
2572
2573 #define BGE_VOLTAGE_1POINT3 0x00000000
2574 #define BGE_VOLTAGE_1POINT8 0x00000001
2575
2576 #define BGE_PHYLEDMODE_UNSPEC 0x00000000
2577 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004
2578 #define BGE_PHYLEDMODE_SINGLELED 0x00000008
2579
2580 #define BGE_MEDIA_UNSPEC 0x00000000
2581 #define BGE_MEDIA_COPPER 0x00000010
2582 #define BGE_MEDIA_FIBER 0x00000020
2583
2584 #define BGE_TICKS_PER_SEC 1000000
2585
2586 /*
2587 * Ring size constants.
2588 */
2589 #define BGE_EVENT_RING_CNT 256
2590 #define BGE_CMD_RING_CNT 64
2591 #define BGE_STD_RX_RING_CNT 512
2592 #define BGE_JUMBO_RX_RING_CNT 256
2593 #define BGE_MINI_RX_RING_CNT 1024
2594 #define BGE_RETURN_RING_CNT 1024
2595
2596 /* 5705 has smaller return ring size */
2597
2598 #define BGE_RETURN_RING_CNT_5705 512
2599
2600 /*
2601 * Possible TX ring sizes.
2602 */
2603 #define BGE_TX_RING_CNT_128 128
2604 #define BGE_TX_RING_BASE_128 0x3800
2605
2606 #define BGE_TX_RING_CNT_256 256
2607 #define BGE_TX_RING_BASE_256 0x3000
2608
2609 #define BGE_TX_RING_CNT_512 512
2610 #define BGE_TX_RING_BASE_512 0x2000
2611
2612 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512
2613 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512
2614
2615 /*
2616 * Tigon III statistics counters.
2617 */
2618 /* Statistics maintained MAC Receive block. */
2619 struct bge_rx_mac_stats {
2620 bge_hostaddr ifHCInOctets;
2621 bge_hostaddr Reserved1;
2622 bge_hostaddr etherStatsFragments;
2623 bge_hostaddr ifHCInUcastPkts;
2624 bge_hostaddr ifHCInMulticastPkts;
2625 bge_hostaddr ifHCInBroadcastPkts;
2626 bge_hostaddr dot3StatsFCSErrors;
2627 bge_hostaddr dot3StatsAlignmentErrors;
2628 bge_hostaddr xonPauseFramesReceived;
2629 bge_hostaddr xoffPauseFramesReceived;
2630 bge_hostaddr macControlFramesReceived;
2631 bge_hostaddr xoffStateEntered;
2632 bge_hostaddr dot3StatsFramesTooLong;
2633 bge_hostaddr etherStatsJabbers;
2634 bge_hostaddr etherStatsUndersizePkts;
2635 bge_hostaddr inRangeLengthError;
2636 bge_hostaddr outRangeLengthError;
2637 bge_hostaddr etherStatsPkts64Octets;
2638 bge_hostaddr etherStatsPkts65Octetsto127Octets;
2639 bge_hostaddr etherStatsPkts128Octetsto255Octets;
2640 bge_hostaddr etherStatsPkts256Octetsto511Octets;
2641 bge_hostaddr etherStatsPkts512Octetsto1023Octets;
2642 bge_hostaddr etherStatsPkts1024Octetsto1522Octets;
2643 bge_hostaddr etherStatsPkts1523Octetsto2047Octets;
2644 bge_hostaddr etherStatsPkts2048Octetsto4095Octets;
2645 bge_hostaddr etherStatsPkts4096Octetsto8191Octets;
2646 bge_hostaddr etherStatsPkts8192Octetsto9022Octets;
2647 };
2648
2649 /* Statistics maintained MAC Transmit block. */
2650 struct bge_tx_mac_stats {
2651 bge_hostaddr ifHCOutOctets;
2652 bge_hostaddr Reserved2;
2653 bge_hostaddr etherStatsCollisions;
2654 bge_hostaddr outXonSent;
2655 bge_hostaddr outXoffSent;
2656 bge_hostaddr flowControlDone;
2657 bge_hostaddr dot3StatsInternalMacTransmitErrors;
2658 bge_hostaddr dot3StatsSingleCollisionFrames;
2659 bge_hostaddr dot3StatsMultipleCollisionFrames;
2660 bge_hostaddr dot3StatsDeferredTransmissions;
2661 bge_hostaddr Reserved3;
2662 bge_hostaddr dot3StatsExcessiveCollisions;
2663 bge_hostaddr dot3StatsLateCollisions;
2664 bge_hostaddr dot3Collided2Times;
2665 bge_hostaddr dot3Collided3Times;
2666 bge_hostaddr dot3Collided4Times;
2667 bge_hostaddr dot3Collided5Times;
2668 bge_hostaddr dot3Collided6Times;
2669 bge_hostaddr dot3Collided7Times;
2670 bge_hostaddr dot3Collided8Times;
2671 bge_hostaddr dot3Collided9Times;
2672 bge_hostaddr dot3Collided10Times;
2673 bge_hostaddr dot3Collided11Times;
2674 bge_hostaddr dot3Collided12Times;
2675 bge_hostaddr dot3Collided13Times;
2676 bge_hostaddr dot3Collided14Times;
2677 bge_hostaddr dot3Collided15Times;
2678 bge_hostaddr ifHCOutUcastPkts;
2679 bge_hostaddr ifHCOutMulticastPkts;
2680 bge_hostaddr ifHCOutBroadcastPkts;
2681 bge_hostaddr dot3StatsCarrierSenseErrors;
2682 bge_hostaddr ifOutDiscards;
2683 bge_hostaddr ifOutErrors;
2684 };
2685
2686 /* Stats counters access through registers */
2687 struct bge_mac_stats {
2688 /* TX MAC statistics */
2689 uint64_t ifHCOutOctets;
2690 uint64_t Reserved0;
2691 uint64_t etherStatsCollisions;
2692 uint64_t outXonSent;
2693 uint64_t outXoffSent;
2694 uint64_t Reserved1;
2695 uint64_t dot3StatsInternalMacTransmitErrors;
2696 uint64_t dot3StatsSingleCollisionFrames;
2697 uint64_t dot3StatsMultipleCollisionFrames;
2698 uint64_t dot3StatsDeferredTransmissions;
2699 uint64_t Reserved2;
2700 uint64_t dot3StatsExcessiveCollisions;
2701 uint64_t dot3StatsLateCollisions;
2702 uint64_t Reserved3[14];
2703 uint64_t ifHCOutUcastPkts;
2704 uint64_t ifHCOutMulticastPkts;
2705 uint64_t ifHCOutBroadcastPkts;
2706 uint64_t Reserved4[2];
2707 /* RX MAC statistics */
2708 uint64_t ifHCInOctets;
2709 uint64_t Reserved5;
2710 uint64_t etherStatsFragments;
2711 uint64_t ifHCInUcastPkts;
2712 uint64_t ifHCInMulticastPkts;
2713 uint64_t ifHCInBroadcastPkts;
2714 uint64_t dot3StatsFCSErrors;
2715 uint64_t dot3StatsAlignmentErrors;
2716 uint64_t xonPauseFramesReceived;
2717 uint64_t xoffPauseFramesReceived;
2718 uint64_t macControlFramesReceived;
2719 uint64_t xoffStateEntered;
2720 uint64_t dot3StatsFramesTooLong;
2721 uint64_t etherStatsJabbers;
2722 uint64_t etherStatsUndersizePkts;
2723 /* Receive List Placement control */
2724 uint64_t FramesDroppedDueToFilters;
2725 uint64_t DmaWriteQueueFull;
2726 uint64_t DmaWriteHighPriQueueFull;
2727 uint64_t NoMoreRxBDs;
2728 uint64_t InputDiscards;
2729 uint64_t InputErrors;
2730 uint64_t RecvThresholdHit;
2731 };
2732
2733 struct bge_stats {
2734 uint8_t Reserved0[256];
2735
2736 /* Statistics maintained by Receive MAC. */
2737 struct bge_rx_mac_stats rxstats;
2738
2739 bge_hostaddr Unused1[37];
2740
2741 /* Statistics maintained by Transmit MAC. */
2742 struct bge_tx_mac_stats txstats;
2743
2744 bge_hostaddr Unused2[31];
2745
2746 /* Statistics maintained by Receive List Placement. */
2747 bge_hostaddr COSIfHCInPkts[16];
2748 bge_hostaddr COSFramesDroppedDueToFilters;
2749 bge_hostaddr nicDmaWriteQueueFull;
2750 bge_hostaddr nicDmaWriteHighPriQueueFull;
2751 bge_hostaddr nicNoMoreRxBDs;
2752 bge_hostaddr ifInDiscards;
2753 bge_hostaddr ifInErrors;
2754 bge_hostaddr nicRecvThresholdHit;
2755
2756 bge_hostaddr Unused3[9];
2757
2758 /* Statistics maintained by Send Data Initiator. */
2759 bge_hostaddr COSIfHCOutPkts[16];
2760 bge_hostaddr nicDmaReadQueueFull;
2761 bge_hostaddr nicDmaReadHighPriQueueFull;
2762 bge_hostaddr nicSendDataCompQueueFull;
2763
2764 /* Statistics maintained by Host Coalescing. */
2765 bge_hostaddr nicRingSetSendProdIndex;
2766 bge_hostaddr nicRingStatusUpdate;
2767 bge_hostaddr nicInterrupts;
2768 bge_hostaddr nicAvoidedInterrupts;
2769 bge_hostaddr nicSendThresholdHit;
2770
2771 uint8_t Reserved4[320];
2772 };
2773
2774 /*
2775 * Tigon general information block. This resides in host memory
2776 * and contains the status counters, ring control blocks and
2777 * producer pointers.
2778 */
2779
2780 struct bge_gib {
2781 struct bge_stats bge_stats;
2782 struct bge_rcb bge_tx_rcb[16];
2783 struct bge_rcb bge_std_rx_rcb;
2784 struct bge_rcb bge_jumbo_rx_rcb;
2785 struct bge_rcb bge_mini_rx_rcb;
2786 struct bge_rcb bge_return_rcb;
2787 };
2788
2789 #define BGE_FRAMELEN 1518
2790 #define BGE_MAX_FRAMELEN 1536
2791 #define BGE_JUMBO_FRAMELEN 9018
2792 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2793 #define BGE_MIN_FRAMELEN 60
2794
2795 /*
2796 * Other utility macros.
2797 */
2798 #define BGE_INC(x, y) (x) = (x + 1) % y
2799
2800 /*
2801 * BAR0 MAC register access macros. The Tigon always uses memory mapped register
2802 * accesses and all registers must be accessed with 32 bit operations.
2803 */
2804
2805 #define CSR_WRITE_4(sc, reg, val) \
2806 bus_write_4(sc->bge_res, reg, val)
2807
2808 #define CSR_READ_4(sc, reg) \
2809 bus_read_4(sc->bge_res, reg)
2810
2811 #define BGE_SETBIT(sc, reg, x) \
2812 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
2813 #define BGE_CLRBIT(sc, reg, x) \
2814 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
2815
2816 /* BAR2 APE register access macros. */
2817 #define APE_WRITE_4(sc, reg, val) \
2818 bus_write_4(sc->bge_res2, reg, val)
2819
2820 #define APE_READ_4(sc, reg) \
2821 bus_read_4(sc->bge_res2, reg)
2822
2823 #define APE_SETBIT(sc, reg, x) \
2824 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x)))
2825 #define APE_CLRBIT(sc, reg, x) \
2826 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x)))
2827
2828 #define PCI_SETBIT(dev, reg, x, s) \
2829 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
2830 #define PCI_CLRBIT(dev, reg, x, s) \
2831 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
2832
2833 /*
2834 * Memory management stuff.
2835 */
2836
2837 #define BGE_NSEG_JUMBO 4
2838 #define BGE_NSEG_NEW 35
2839 #define BGE_TSOSEG_SZ 4096
2840
2841 /* Maximum DMA address for controllers that have 40bit DMA address bug. */
2842 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
2843 #define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR
2844 #else
2845 #define BGE_DMA_MAXADDR 0xFFFFFFFFFF
2846 #endif
2847
2848 #if (BUS_SPACE_MAXSIZE > 0xFFFFFFFF)
2849 #define BGE_DMA_BNDRY 0x100000000
2850 #else
2851 #define BGE_DMA_BNDRY 0
2852 #endif
2853
2854 /*
2855 * Ring structures. Most of these reside in host memory and we tell
2856 * the NIC where they are via the ring control blocks. The exceptions
2857 * are the tx and command rings, which live in NIC memory and which
2858 * we access via the shared memory window.
2859 */
2860
2861 struct bge_ring_data {
2862 struct bge_rx_bd *bge_rx_std_ring;
2863 bus_addr_t bge_rx_std_ring_paddr;
2864 struct bge_extrx_bd *bge_rx_jumbo_ring;
2865 bus_addr_t bge_rx_jumbo_ring_paddr;
2866 struct bge_rx_bd *bge_rx_return_ring;
2867 bus_addr_t bge_rx_return_ring_paddr;
2868 struct bge_tx_bd *bge_tx_ring;
2869 bus_addr_t bge_tx_ring_paddr;
2870 struct bge_status_block *bge_status_block;
2871 bus_addr_t bge_status_block_paddr;
2872 struct bge_stats *bge_stats;
2873 bus_addr_t bge_stats_paddr;
2874 struct bge_gib bge_info;
2875 };
2876
2877 #define BGE_STD_RX_RING_SZ \
2878 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
2879 #define BGE_JUMBO_RX_RING_SZ \
2880 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT)
2881 #define BGE_TX_RING_SZ \
2882 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
2883 #define BGE_RX_RTN_RING_SZ(x) \
2884 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
2885
2886 #define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block)
2887
2888 #define BGE_STATS_SZ sizeof (struct bge_stats)
2889
2890 /*
2891 * Mbuf pointers. We need these to keep track of the virtual addresses
2892 * of our mbuf chains since we can only convert from physical to virtual,
2893 * not the other way around.
2894 */
2895 struct bge_chain_data {
2896 bus_dma_tag_t bge_parent_tag;
2897 bus_dma_tag_t bge_buffer_tag;
2898 bus_dma_tag_t bge_rx_std_ring_tag;
2899 bus_dma_tag_t bge_rx_jumbo_ring_tag;
2900 bus_dma_tag_t bge_rx_return_ring_tag;
2901 bus_dma_tag_t bge_tx_ring_tag;
2902 bus_dma_tag_t bge_status_tag;
2903 bus_dma_tag_t bge_stats_tag;
2904 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */
2905 bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */
2906 bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */
2907 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT];
2908 bus_dmamap_t bge_rx_std_sparemap;
2909 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
2910 bus_dmamap_t bge_rx_jumbo_sparemap;
2911 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT];
2912 bus_dmamap_t bge_rx_std_ring_map;
2913 bus_dmamap_t bge_rx_jumbo_ring_map;
2914 bus_dmamap_t bge_tx_ring_map;
2915 bus_dmamap_t bge_rx_return_ring_map;
2916 bus_dmamap_t bge_status_map;
2917 bus_dmamap_t bge_stats_map;
2918 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT];
2919 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT];
2920 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
2921 int bge_rx_std_seglen[BGE_STD_RX_RING_CNT];
2922 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4];
2923 };
2924
2925 struct bge_dmamap_arg {
2926 bus_addr_t bge_busaddr;
2927 };
2928
2929 #define BGE_HWREV_TIGON 0x01
2930 #define BGE_HWREV_TIGON_II 0x02
2931 #define BGE_TIMEOUT 100000
2932 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
2933 #define BGE_TX_TIMEOUT 5
2934
2935 struct bge_bcom_hack {
2936 int reg;
2937 int val;
2938 };
2939
2940 #define ASF_ENABLE 1
2941 #define ASF_NEW_HANDSHAKE 2
2942 #define ASF_STACKUP 4
2943
2944 struct bge_softc {
2945 struct ifnet *bge_ifp; /* interface info */
2946 device_t bge_dev;
2947 struct mtx bge_mtx;
2948 device_t bge_miibus;
2949 void *bge_intrhand;
2950 struct resource *bge_irq;
2951 struct resource *bge_res; /* MAC mapped I/O */
2952 struct resource *bge_res2; /* APE mapped I/O */
2953 struct ifmedia bge_ifmedia; /* TBI media info */
2954 int bge_expcap;
2955 int bge_expmrq;
2956 int bge_msicap;
2957 int bge_pcixcap;
2958 uint32_t bge_flags;
2959 #define BGE_FLAG_TBI 0x00000001
2960 #define BGE_FLAG_JUMBO 0x00000002
2961 #define BGE_FLAG_JUMBO_STD 0x00000004
2962 #define BGE_FLAG_EADDR 0x00000008
2963 #define BGE_FLAG_MII_SERDES 0x00000010
2964 #define BGE_FLAG_CPMU_PRESENT 0x00000020
2965 #define BGE_FLAG_TAGGED_STATUS 0x00000040
2966 #define BGE_FLAG_APE 0x00000080
2967 #define BGE_FLAG_MSI 0x00000100
2968 #define BGE_FLAG_PCIX 0x00000200
2969 #define BGE_FLAG_PCIE 0x00000400
2970 #define BGE_FLAG_TSO 0x00000800
2971 #define BGE_FLAG_TSO3 0x00001000
2972 #define BGE_FLAG_JUMBO_FRAME 0x00002000
2973 #define BGE_FLAG_5700_FAMILY 0x00010000
2974 #define BGE_FLAG_5705_PLUS 0x00020000
2975 #define BGE_FLAG_5714_FAMILY 0x00040000
2976 #define BGE_FLAG_575X_PLUS 0x00080000
2977 #define BGE_FLAG_5755_PLUS 0x00100000
2978 #define BGE_FLAG_5788 0x00200000
2979 #define BGE_FLAG_5717_PLUS 0x00400000
2980 #define BGE_FLAG_57765_PLUS 0x00800000
2981 #define BGE_FLAG_40BIT_BUG 0x01000000
2982 #define BGE_FLAG_4G_BNDRY_BUG 0x02000000
2983 #define BGE_FLAG_RX_ALIGNBUG 0x04000000
2984 #define BGE_FLAG_SHORT_DMA_BUG 0x08000000
2985 #define BGE_FLAG_4K_RDMA_BUG 0x10000000
2986 #define BGE_FLAG_MBOX_REORDER 0x20000000
2987 #define BGE_FLAG_RDMA_BUG 0x40000000
2988 uint32_t bge_mfw_flags; /* Management F/W flags */
2989 #define BGE_MFW_ON_RXCPU 0x00000001
2990 #define BGE_MFW_ON_APE 0x00000002
2991 #define BGE_MFW_TYPE_NCSI 0x00000004
2992 #define BGE_MFW_TYPE_DASH 0x00000008
2993 int bge_phy_ape_lock;
2994 int bge_func_addr;
2995 int bge_phy_addr;
2996 uint32_t bge_phy_flags;
2997 #define BGE_PHY_NO_WIRESPEED 0x00000001
2998 #define BGE_PHY_ADC_BUG 0x00000002
2999 #define BGE_PHY_5704_A0_BUG 0x00000004
3000 #define BGE_PHY_JITTER_BUG 0x00000008
3001 #define BGE_PHY_BER_BUG 0x00000010
3002 #define BGE_PHY_ADJUST_TRIM 0x00000020
3003 #define BGE_PHY_CRC_BUG 0x00000040
3004 #define BGE_PHY_NO_3LED 0x00000080
3005 uint32_t bge_chipid;
3006 uint32_t bge_asicrev;
3007 uint32_t bge_chiprev;
3008 uint8_t bge_asf_mode;
3009 uint8_t bge_asf_count;
3010 uint16_t bge_mps;
3011 struct bge_ring_data bge_ldata; /* rings */
3012 struct bge_chain_data bge_cdata; /* mbufs */
3013 uint16_t bge_tx_saved_considx;
3014 uint16_t bge_rx_saved_considx;
3015 uint16_t bge_ev_saved_considx;
3016 uint16_t bge_return_ring_cnt;
3017 uint16_t bge_std; /* current std ring head */
3018 uint16_t bge_jumbo; /* current jumo ring head */
3019 uint32_t bge_stat_ticks;
3020 uint32_t bge_rx_coal_ticks;
3021 uint32_t bge_tx_coal_ticks;
3022 uint32_t bge_tx_prodidx;
3023 uint32_t bge_rx_max_coal_bds;
3024 uint32_t bge_tx_max_coal_bds;
3025 uint32_t bge_mi_mode;
3026 int bge_if_flags;
3027 int bge_txcnt;
3028 int bge_link; /* link state */
3029 int bge_link_evt; /* pending link event */
3030 int bge_timer;
3031 int bge_forced_collapse;
3032 int bge_forced_udpcsum;
3033 int bge_msi;
3034 int bge_csum_features;
3035 struct callout bge_stat_ch;
3036 uint32_t bge_rx_discards;
3037 uint32_t bge_rx_inerrs;
3038 uint32_t bge_rx_nobds;
3039 uint32_t bge_tx_discards;
3040 uint32_t bge_tx_collisions;
3041 #ifdef DEVICE_POLLING
3042 int rxcycles;
3043 #endif /* DEVICE_POLLING */
3044 struct bge_mac_stats bge_mac_stats;
3045 struct task bge_intr_task;
3046 struct taskqueue *bge_tq;
3047 };
3048
3049 #define BGE_LOCK_INIT(_sc, _name) \
3050 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
3051 #define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx)
3052 #define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED)
3053 #define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx)
3054 #define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)
Cache object: f6421ac840328c725480c4abc80f0c7e
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