1 /*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 199011 2009-11-07 01:01:33Z yongari $
34 */
35
36 /*
37 * BCM570x memory map. The internal memory layout varies somewhat
38 * depending on whether or not we have external SSRAM attached.
39 * The BCM5700 can have up to 16MB of external memory. The BCM5701
40 * is apparently not designed to use external SSRAM. The mappings
41 * up to the first 4 send rings are the same for both internal and
42 * external memory configurations. Note that mini RX ring space is
43 * only available with external SSRAM configurations, which means
44 * the mini RX ring is not supported on the BCM5701.
45 *
46 * The NIC's memory can be accessed by the host in one of 3 ways:
47 *
48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
49 * registers in PCI config space can be used to read any 32-bit
50 * address within the NIC's memory.
51 *
52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
53 * space can be used in conjunction with the memory window in the
54 * device register space at offset 0x8000 to read any 32K chunk
55 * of NIC memory.
56 *
57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
58 * set, the device I/O mapping consumes 32MB of host address space,
59 * allowing all of the registers and internal NIC memory to be
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
61 * Flat mode consumes so much host address space that it is not
62 * recommended.
63 */
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
72 #define BGE_STATUS_BLOCK 0x00000B00
73 #define BGE_STATUS_BLOCK_END 0x00000B4F
74 #define BGE_SOFTWARE_GENCOMM 0x00000B50
75 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54
76 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58
77 #define BGE_SOFTWARE_GENCOMM_FW 0x00000B78
78 #define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C
79 #define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80
80 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
81 #define BGE_UNMAPPED 0x00001000
82 #define BGE_UNMAPPED_END 0x00001FFF
83 #define BGE_DMA_DESCRIPTORS 0x00002000
84 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF
85 #define BGE_SEND_RING_1_TO_4 0x00004000
86 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF
87
88 /* Firmware interface */
89 #define BGE_FW_DRV_ALIVE 0x00000001
90 #define BGE_FW_PAUSE 0x00000002
91
92 /* Mappings for internal memory configuration */
93 #define BGE_STD_RX_RINGS 0x00006000
94 #define BGE_STD_RX_RINGS_END 0x00006FFF
95 #define BGE_JUMBO_RX_RINGS 0x00007000
96 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF
97 #define BGE_BUFFPOOL_1 0x00008000
98 #define BGE_BUFFPOOL_1_END 0x0000FFFF
99 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */
100 #define BGE_BUFFPOOL_2_END 0x00017FFF
101 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */
102 #define BGE_BUFFPOOL_3_END 0x0001FFFF
103
104 /* Mappings for external SSRAM configurations */
105 #define BGE_SEND_RING_5_TO_6 0x00006000
106 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF
107 #define BGE_SEND_RING_7_TO_8 0x00007000
108 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF
109 #define BGE_SEND_RING_9_TO_16 0x00008000
110 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF
111 #define BGE_EXT_STD_RX_RINGS 0x0000C000
112 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF
113 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000
114 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF
115 #define BGE_MINI_RX_RINGS 0x0000E000
116 #define BGE_MINI_RX_RINGS_END 0x0000FFFF
117 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */
118 #define BGE_AVAIL_REGION1_END 0x00017FFF
119 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */
120 #define BGE_AVAIL_REGION2_END 0x0001FFFF
121 #define BGE_EXT_SSRAM 0x00020000
122 #define BGE_EXT_SSRAM_END 0x000FFFFF
123
124
125 /*
126 * BCM570x register offsets. These are memory mapped registers
127 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
128 * Each register must be accessed using 32 bit operations.
129 *
130 * All registers are accessed through a 32K shared memory block.
131 * The first group of registers are actually copies of the PCI
132 * configuration space registers.
133 */
134
135 /*
136 * PCI registers defined in the PCI 2.2 spec.
137 */
138 #define BGE_PCI_VID 0x00
139 #define BGE_PCI_DID 0x02
140 #define BGE_PCI_CMD 0x04
141 #define BGE_PCI_STS 0x06
142 #define BGE_PCI_REV 0x08
143 #define BGE_PCI_CLASS 0x09
144 #define BGE_PCI_CACHESZ 0x0C
145 #define BGE_PCI_LATTIMER 0x0D
146 #define BGE_PCI_HDRTYPE 0x0E
147 #define BGE_PCI_BIST 0x0F
148 #define BGE_PCI_BAR0 0x10
149 #define BGE_PCI_BAR1 0x14
150 #define BGE_PCI_SUBSYS 0x2C
151 #define BGE_PCI_SUBVID 0x2E
152 #define BGE_PCI_ROMBASE 0x30
153 #define BGE_PCI_CAPPTR 0x34
154 #define BGE_PCI_INTLINE 0x3C
155 #define BGE_PCI_INTPIN 0x3D
156 #define BGE_PCI_MINGNT 0x3E
157 #define BGE_PCI_MAXLAT 0x3F
158 #define BGE_PCI_PCIXCAP 0x40
159 #define BGE_PCI_NEXTPTR_PM 0x41
160 #define BGE_PCI_PCIX_CMD 0x42
161 #define BGE_PCI_PCIX_STS 0x44
162 #define BGE_PCI_PWRMGMT_CAPID 0x48
163 #define BGE_PCI_NEXTPTR_VPD 0x49
164 #define BGE_PCI_PWRMGMT_CAPS 0x4A
165 #define BGE_PCI_PWRMGMT_CMD 0x4C
166 #define BGE_PCI_PWRMGMT_STS 0x4D
167 #define BGE_PCI_PWRMGMT_DATA 0x4F
168 #define BGE_PCI_VPD_CAPID 0x50
169 #define BGE_PCI_NEXTPTR_MSI 0x51
170 #define BGE_PCI_VPD_ADDR 0x52
171 #define BGE_PCI_VPD_DATA 0x54
172 #define BGE_PCI_MSI_CAPID 0x58
173 #define BGE_PCI_NEXTPTR_NONE 0x59
174 #define BGE_PCI_MSI_CTL 0x5A
175 #define BGE_PCI_MSI_ADDR_HI 0x5C
176 #define BGE_PCI_MSI_ADDR_LO 0x60
177 #define BGE_PCI_MSI_DATA 0x64
178
179 /*
180 * PCI Express definitions
181 * According to
182 * PCI Express base specification, REV. 1.0a
183 */
184
185 /* PCI Express device control, 16bits */
186 #define BGE_PCIE_DEVCTL 0x08
187 #define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000
188 #define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000
189 #define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000
190 #define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000
191 #define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000
192 #define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000
193 #define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000
194
195 /* PCI MSI. ??? */
196 #define BGE_PCIE_CAPID_REG 0xD0
197 #define BGE_PCIE_CAPID 0x10
198
199 /*
200 * PCI registers specific to the BCM570x family.
201 */
202 #define BGE_PCI_MISC_CTL 0x68
203 #define BGE_PCI_DMA_RW_CTL 0x6C
204 #define BGE_PCI_PCISTATE 0x70
205 #define BGE_PCI_CLKCTL 0x74
206 #define BGE_PCI_REG_BASEADDR 0x78
207 #define BGE_PCI_MEMWIN_BASEADDR 0x7C
208 #define BGE_PCI_REG_DATA 0x80
209 #define BGE_PCI_MEMWIN_DATA 0x84
210 #define BGE_PCI_MODECTL 0x88
211 #define BGE_PCI_MISC_CFG 0x8C
212 #define BGE_PCI_MISC_LOCALCTL 0x90
213 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98
214 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C
215 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0
216 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4
217 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8
218 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
219 #define BGE_PCI_ISR_MBX_HI 0xB0
220 #define BGE_PCI_ISR_MBX_LO 0xB4
221 #define BGE_PCI_PRODID_ASICREV 0xBC
222
223 /* PCI Misc. Host control register */
224 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
225 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
226 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004
227 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008
228 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010
229 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020
230 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
231 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
232 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
233 #define BGE_PCIMISCCTL_ASICREV_SHIFT 16
234
235 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP)
236 #if BYTE_ORDER == LITTLE_ENDIAN
237 #define BGE_DMA_SWAP_OPTIONS \
238 BGE_MODECTL_WORDSWAP_NONFRAME| \
239 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
240 #else
241 #define BGE_DMA_SWAP_OPTIONS \
242 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \
243 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
244 #endif
245
246 #define BGE_INIT \
247 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \
248 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
249
250 #define BGE_CHIPID_TIGON_I 0x4000
251 #define BGE_CHIPID_TIGON_II 0x6000
252 #define BGE_CHIPID_BCM5700_A0 0x7000
253 #define BGE_CHIPID_BCM5700_A1 0x7001
254 #define BGE_CHIPID_BCM5700_B0 0x7100
255 #define BGE_CHIPID_BCM5700_B1 0x7101
256 #define BGE_CHIPID_BCM5700_B2 0x7102
257 #define BGE_CHIPID_BCM5700_B3 0x7103
258 #define BGE_CHIPID_BCM5700_ALTIMA 0x7104
259 #define BGE_CHIPID_BCM5700_C0 0x7200
260 #define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */
261 #define BGE_CHIPID_BCM5701_B0 0x0100
262 #define BGE_CHIPID_BCM5701_B2 0x0102
263 #define BGE_CHIPID_BCM5701_B5 0x0105
264 #define BGE_CHIPID_BCM5703_A0 0x1000
265 #define BGE_CHIPID_BCM5703_A1 0x1001
266 #define BGE_CHIPID_BCM5703_A2 0x1002
267 #define BGE_CHIPID_BCM5703_A3 0x1003
268 #define BGE_CHIPID_BCM5703_B0 0x1100
269 #define BGE_CHIPID_BCM5704_A0 0x2000
270 #define BGE_CHIPID_BCM5704_A1 0x2001
271 #define BGE_CHIPID_BCM5704_A2 0x2002
272 #define BGE_CHIPID_BCM5704_A3 0x2003
273 #define BGE_CHIPID_BCM5704_B0 0x2100
274 #define BGE_CHIPID_BCM5705_A0 0x3000
275 #define BGE_CHIPID_BCM5705_A1 0x3001
276 #define BGE_CHIPID_BCM5705_A2 0x3002
277 #define BGE_CHIPID_BCM5705_A3 0x3003
278 #define BGE_CHIPID_BCM5750_A0 0x4000
279 #define BGE_CHIPID_BCM5750_A1 0x4001
280 #define BGE_CHIPID_BCM5750_A3 0x4000
281 #define BGE_CHIPID_BCM5750_B0 0x4100
282 #define BGE_CHIPID_BCM5750_B1 0x4101
283 #define BGE_CHIPID_BCM5750_C0 0x4200
284 #define BGE_CHIPID_BCM5750_C1 0x4201
285 #define BGE_CHIPID_BCM5750_C2 0x4202
286 #define BGE_CHIPID_BCM5714_A0 0x5000
287 #define BGE_CHIPID_BCM5752_A0 0x6000
288 #define BGE_CHIPID_BCM5752_A1 0x6001
289 #define BGE_CHIPID_BCM5752_A2 0x6002
290 #define BGE_CHIPID_BCM5714_B0 0x8000
291 #define BGE_CHIPID_BCM5714_B3 0x8003
292 #define BGE_CHIPID_BCM5715_A0 0x9000
293 #define BGE_CHIPID_BCM5715_A1 0x9001
294 #define BGE_CHIPID_BCM5715_A3 0x9003
295 #define BGE_CHIPID_BCM5755_A0 0xa000
296 #define BGE_CHIPID_BCM5755_A1 0xa001
297 #define BGE_CHIPID_BCM5755_A2 0xa002
298 #define BGE_CHIPID_BCM5722_A0 0xa200
299 #define BGE_CHIPID_BCM5754_A0 0xb000
300 #define BGE_CHIPID_BCM5754_A1 0xb001
301 #define BGE_CHIPID_BCM5754_A2 0xb002
302 #define BGE_CHIPID_BCM5761_A0 0x5761000
303 #define BGE_CHIPID_BCM5761_A1 0x5761100
304 #define BGE_CHIPID_BCM5784_A0 0x5784000
305 #define BGE_CHIPID_BCM5784_A1 0x5784100
306 #define BGE_CHIPID_BCM5787_A0 0xb000
307 #define BGE_CHIPID_BCM5787_A1 0xb001
308 #define BGE_CHIPID_BCM5787_A2 0xb002
309 #define BGE_CHIPID_BCM5906_A1 0xc001
310 #define BGE_CHIPID_BCM5906_A2 0xc002
311 #define BGE_CHIPID_BCM57780_A0 0x57780000
312 #define BGE_CHIPID_BCM57780_A1 0x57780001
313
314 /* shorthand one */
315 #define BGE_ASICREV(x) ((x) >> 12)
316 #define BGE_ASICREV_BCM5701 0x00
317 #define BGE_ASICREV_BCM5703 0x01
318 #define BGE_ASICREV_BCM5704 0x02
319 #define BGE_ASICREV_BCM5705 0x03
320 #define BGE_ASICREV_BCM5750 0x04
321 #define BGE_ASICREV_BCM5714_A0 0x05
322 #define BGE_ASICREV_BCM5752 0x06
323 #define BGE_ASICREV_BCM5700 0x07
324 #define BGE_ASICREV_BCM5780 0x08
325 #define BGE_ASICREV_BCM5714 0x09
326 #define BGE_ASICREV_BCM5755 0x0a
327 #define BGE_ASICREV_BCM5754 0x0b
328 #define BGE_ASICREV_BCM5787 0x0b
329 #define BGE_ASICREV_BCM5906 0x0c
330 /* Should consult BGE_PCI_PRODID_ASICREV for ChipID */
331 #define BGE_ASICREV_USE_PRODID_REG 0x0f
332 /* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */
333 #define BGE_ASICREV_BCM5761 0x5761
334 #define BGE_ASICREV_BCM5784 0x5784
335 #define BGE_ASICREV_BCM5785 0x5785
336 #define BGE_ASICREV_BCM57780 0x57780
337
338 /* chip revisions */
339 #define BGE_CHIPREV(x) ((x) >> 8)
340 #define BGE_CHIPREV_5700_AX 0x70
341 #define BGE_CHIPREV_5700_BX 0x71
342 #define BGE_CHIPREV_5700_CX 0x72
343 #define BGE_CHIPREV_5701_AX 0x00
344 #define BGE_CHIPREV_5703_AX 0x10
345 #define BGE_CHIPREV_5704_AX 0x20
346 #define BGE_CHIPREV_5704_BX 0x21
347 #define BGE_CHIPREV_5750_AX 0x40
348 #define BGE_CHIPREV_5750_BX 0x41
349 /* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */
350 #define BGE_CHIPREV_5761_AX 0x57611
351 #define BGE_CHIPREV_5784_AX 0x57841
352
353 /* PCI DMA Read/Write Control register */
354 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF
355 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
356 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
357 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000
358 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000
359 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000
360 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000
361 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000
362 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000
363 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
364 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
365 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
366
367 #define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16)
368 #define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19)
369 #define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24)
370 #define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28)
371
372 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
373 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
374 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
375 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300
376 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400
377 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500
378 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600
379 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700
380
381 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000
382 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800
383 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000
384 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800
385 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000
386 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800
387 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000
388 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800
389
390 /*
391 * PCI state register -- note, this register is read only
392 * unless the PCISTATE_WR bit of the PCI Misc. Host Control
393 * register is set.
394 */
395 #define BGE_PCISTATE_FORCE_RESET 0x00000001
396 #define BGE_PCISTATE_INTR_STATE 0x00000002
397 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
398 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */
399 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
400 #define BGE_PCISTATE_WANT_EXPROM 0x00000020
401 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040
402 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
403 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
404
405 /*
406 * PCI Clock Control register -- note, this register is read only
407 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
408 * register is set.
409 */
410 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F
411 #define BGE_PCICLOCKCTL_M66EN 0x00000080
412 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200
413 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400
414 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800
415 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000
416 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000
417 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000
418 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
419 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
420
421
422 #ifndef PCIM_CMD_MWIEN
423 #define PCIM_CMD_MWIEN 0x0010
424 #endif
425 #ifndef PCIM_CMD_INTxDIS
426 #define PCIM_CMD_INTxDIS 0x0400
427 #endif
428
429 /*
430 * High priority mailbox registers
431 * Each mailbox is 64-bits wide, though we only use the
432 * lower 32 bits. To write a 64-bit value, write the upper 32 bits
433 * first. The NIC will load the mailbox after the lower 32 bit word
434 * has been updated.
435 */
436 #define BGE_MBX_IRQ0_HI 0x0200
437 #define BGE_MBX_IRQ0_LO 0x0204
438 #define BGE_MBX_IRQ1_HI 0x0208
439 #define BGE_MBX_IRQ1_LO 0x020C
440 #define BGE_MBX_IRQ2_HI 0x0210
441 #define BGE_MBX_IRQ2_LO 0x0214
442 #define BGE_MBX_IRQ3_HI 0x0218
443 #define BGE_MBX_IRQ3_LO 0x021C
444 #define BGE_MBX_GEN0_HI 0x0220
445 #define BGE_MBX_GEN0_LO 0x0224
446 #define BGE_MBX_GEN1_HI 0x0228
447 #define BGE_MBX_GEN1_LO 0x022C
448 #define BGE_MBX_GEN2_HI 0x0230
449 #define BGE_MBX_GEN2_LO 0x0234
450 #define BGE_MBX_GEN3_HI 0x0228
451 #define BGE_MBX_GEN3_LO 0x022C
452 #define BGE_MBX_GEN4_HI 0x0240
453 #define BGE_MBX_GEN4_LO 0x0244
454 #define BGE_MBX_GEN5_HI 0x0248
455 #define BGE_MBX_GEN5_LO 0x024C
456 #define BGE_MBX_GEN6_HI 0x0250
457 #define BGE_MBX_GEN6_LO 0x0254
458 #define BGE_MBX_GEN7_HI 0x0258
459 #define BGE_MBX_GEN7_LO 0x025C
460 #define BGE_MBX_RELOAD_STATS_HI 0x0260
461 #define BGE_MBX_RELOAD_STATS_LO 0x0264
462 #define BGE_MBX_RX_STD_PROD_HI 0x0268
463 #define BGE_MBX_RX_STD_PROD_LO 0x026C
464 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270
465 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274
466 #define BGE_MBX_RX_MINI_PROD_HI 0x0278
467 #define BGE_MBX_RX_MINI_PROD_LO 0x027C
468 #define BGE_MBX_RX_CONS0_HI 0x0280
469 #define BGE_MBX_RX_CONS0_LO 0x0284
470 #define BGE_MBX_RX_CONS1_HI 0x0288
471 #define BGE_MBX_RX_CONS1_LO 0x028C
472 #define BGE_MBX_RX_CONS2_HI 0x0290
473 #define BGE_MBX_RX_CONS2_LO 0x0294
474 #define BGE_MBX_RX_CONS3_HI 0x0298
475 #define BGE_MBX_RX_CONS3_LO 0x029C
476 #define BGE_MBX_RX_CONS4_HI 0x02A0
477 #define BGE_MBX_RX_CONS4_LO 0x02A4
478 #define BGE_MBX_RX_CONS5_HI 0x02A8
479 #define BGE_MBX_RX_CONS5_LO 0x02AC
480 #define BGE_MBX_RX_CONS6_HI 0x02B0
481 #define BGE_MBX_RX_CONS6_LO 0x02B4
482 #define BGE_MBX_RX_CONS7_HI 0x02B8
483 #define BGE_MBX_RX_CONS7_LO 0x02BC
484 #define BGE_MBX_RX_CONS8_HI 0x02C0
485 #define BGE_MBX_RX_CONS8_LO 0x02C4
486 #define BGE_MBX_RX_CONS9_HI 0x02C8
487 #define BGE_MBX_RX_CONS9_LO 0x02CC
488 #define BGE_MBX_RX_CONS10_HI 0x02D0
489 #define BGE_MBX_RX_CONS10_LO 0x02D4
490 #define BGE_MBX_RX_CONS11_HI 0x02D8
491 #define BGE_MBX_RX_CONS11_LO 0x02DC
492 #define BGE_MBX_RX_CONS12_HI 0x02E0
493 #define BGE_MBX_RX_CONS12_LO 0x02E4
494 #define BGE_MBX_RX_CONS13_HI 0x02E8
495 #define BGE_MBX_RX_CONS13_LO 0x02EC
496 #define BGE_MBX_RX_CONS14_HI 0x02F0
497 #define BGE_MBX_RX_CONS14_LO 0x02F4
498 #define BGE_MBX_RX_CONS15_HI 0x02F8
499 #define BGE_MBX_RX_CONS15_LO 0x02FC
500 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300
501 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304
502 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308
503 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C
504 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310
505 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314
506 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318
507 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C
508 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320
509 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324
510 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328
511 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C
512 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330
513 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334
514 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338
515 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C
516 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340
517 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344
518 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348
519 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C
520 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350
521 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354
522 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358
523 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C
524 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360
525 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364
526 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368
527 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C
528 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370
529 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374
530 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378
531 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C
532 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380
533 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384
534 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388
535 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C
536 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390
537 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394
538 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398
539 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C
540 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0
541 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4
542 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8
543 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC
544 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0
545 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4
546 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8
547 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC
548 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0
549 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4
550 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8
551 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC
552 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0
553 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4
554 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8
555 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC
556 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0
557 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4
558 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8
559 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC
560 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0
561 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4
562 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
563 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
564
565 #define BGE_TX_RINGS_MAX 4
566 #define BGE_TX_RINGS_EXTSSRAM_MAX 16
567 #define BGE_RX_RINGS_MAX 16
568
569 /* Ethernet MAC control registers */
570 #define BGE_MAC_MODE 0x0400
571 #define BGE_MAC_STS 0x0404
572 #define BGE_MAC_EVT_ENB 0x0408
573 #define BGE_MAC_LED_CTL 0x040C
574 #define BGE_MAC_ADDR1_LO 0x0410
575 #define BGE_MAC_ADDR1_HI 0x0414
576 #define BGE_MAC_ADDR2_LO 0x0418
577 #define BGE_MAC_ADDR2_HI 0x041C
578 #define BGE_MAC_ADDR3_LO 0x0420
579 #define BGE_MAC_ADDR3_HI 0x0424
580 #define BGE_MAC_ADDR4_LO 0x0428
581 #define BGE_MAC_ADDR4_HI 0x042C
582 #define BGE_WOL_PATPTR 0x0430
583 #define BGE_WOL_PATCFG 0x0434
584 #define BGE_TX_RANDOM_BACKOFF 0x0438
585 #define BGE_RX_MTU 0x043C
586 #define BGE_GBIT_PCS_TEST 0x0440
587 #define BGE_TX_TBI_AUTONEG 0x0444
588 #define BGE_RX_TBI_AUTONEG 0x0448
589 #define BGE_MI_COMM 0x044C
590 #define BGE_MI_STS 0x0450
591 #define BGE_MI_MODE 0x0454
592 #define BGE_AUTOPOLL_STS 0x0458
593 #define BGE_TX_MODE 0x045C
594 #define BGE_TX_STS 0x0460
595 #define BGE_TX_LENGTHS 0x0464
596 #define BGE_RX_MODE 0x0468
597 #define BGE_RX_STS 0x046C
598 #define BGE_MAR0 0x0470
599 #define BGE_MAR1 0x0474
600 #define BGE_MAR2 0x0478
601 #define BGE_MAR3 0x047C
602 #define BGE_RX_BD_RULES_CTL0 0x0480
603 #define BGE_RX_BD_RULES_MASKVAL0 0x0484
604 #define BGE_RX_BD_RULES_CTL1 0x0488
605 #define BGE_RX_BD_RULES_MASKVAL1 0x048C
606 #define BGE_RX_BD_RULES_CTL2 0x0490
607 #define BGE_RX_BD_RULES_MASKVAL2 0x0494
608 #define BGE_RX_BD_RULES_CTL3 0x0498
609 #define BGE_RX_BD_RULES_MASKVAL3 0x049C
610 #define BGE_RX_BD_RULES_CTL4 0x04A0
611 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4
612 #define BGE_RX_BD_RULES_CTL5 0x04A8
613 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC
614 #define BGE_RX_BD_RULES_CTL6 0x04B0
615 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4
616 #define BGE_RX_BD_RULES_CTL7 0x04B8
617 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC
618 #define BGE_RX_BD_RULES_CTL8 0x04C0
619 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4
620 #define BGE_RX_BD_RULES_CTL9 0x04C8
621 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC
622 #define BGE_RX_BD_RULES_CTL10 0x04D0
623 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4
624 #define BGE_RX_BD_RULES_CTL11 0x04D8
625 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC
626 #define BGE_RX_BD_RULES_CTL12 0x04E0
627 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4
628 #define BGE_RX_BD_RULES_CTL13 0x04E8
629 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC
630 #define BGE_RX_BD_RULES_CTL14 0x04F0
631 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4
632 #define BGE_RX_BD_RULES_CTL15 0x04F8
633 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC
634 #define BGE_RX_RULES_CFG 0x0500
635 #define BGE_SERDES_CFG 0x0590
636 #define BGE_SERDES_STS 0x0594
637 #define BGE_SGDIG_CFG 0x05B0
638 #define BGE_SGDIG_STS 0x05B4
639 #define BGE_MAC_STATS 0x0800
640
641 /* Ethernet MAC Mode register */
642 #define BGE_MACMODE_RESET 0x00000001
643 #define BGE_MACMODE_HALF_DUPLEX 0x00000002
644 #define BGE_MACMODE_PORTMODE 0x0000000C
645 #define BGE_MACMODE_LOOPBACK 0x00000010
646 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080
647 #define BGE_MACMODE_TX_BURST_ENB 0x00000100
648 #define BGE_MACMODE_MAX_DEFER 0x00000200
649 #define BGE_MACMODE_LINK_POLARITY 0x00000400
650 #define BGE_MACMODE_RX_STATS_ENB 0x00000800
651 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000
652 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000
653 #define BGE_MACMODE_TX_STATS_ENB 0x00004000
654 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000
655 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000
656 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000
657 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000
658 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000
659 #define BGE_MACMODE_MIP_ENB 0x00100000
660 #define BGE_MACMODE_TXDMA_ENB 0x00200000
661 #define BGE_MACMODE_RXDMA_ENB 0x00400000
662 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
663
664 #define BGE_PORTMODE_NONE 0x00000000
665 #define BGE_PORTMODE_MII 0x00000004
666 #define BGE_PORTMODE_GMII 0x00000008
667 #define BGE_PORTMODE_TBI 0x0000000C
668
669 /* MAC Status register */
670 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001
671 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002
672 #define BGE_MACSTAT_RX_CFG 0x00000004
673 #define BGE_MACSTAT_CFG_CHANGED 0x00000008
674 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010
675 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400
676 #define BGE_MACSTAT_LINK_CHANGED 0x00001000
677 #define BGE_MACSTAT_MI_COMPLETE 0x00400000
678 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000
679 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000
680 #define BGE_MACSTAT_ODI_ERROR 0x02000000
681 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000
682 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000
683
684 /* MAC Event Enable Register */
685 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400
686 #define BGE_EVTENB_LINK_CHANGED 0x00001000
687 #define BGE_EVTENB_MI_COMPLETE 0x00400000
688 #define BGE_EVTENB_MI_INTERRUPT 0x00800000
689 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000
690 #define BGE_EVTENB_ODI_ERROR 0x02000000
691 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000
692 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000
693
694 /* LED Control Register */
695 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001
696 #define BGE_LEDCTL_1000MBPS_LED 0x00000002
697 #define BGE_LEDCTL_100MBPS_LED 0x00000004
698 #define BGE_LEDCTL_10MBPS_LED 0x00000008
699 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010
700 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020
701 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040
702 #define BGE_LEDCTL_1000MBPS_STS 0x00000080
703 #define BGE_LEDCTL_100MBPS_STS 0x00000100
704 #define BGE_LEDCTL_10MBPS_STS 0x00000200
705 #define BGE_LEDCTL_TRADLED_STS 0x00000400
706 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000
707 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000
708
709 /* TX backoff seed register */
710 #define BGE_TX_BACKOFF_SEED_MASK 0x3F
711
712 /* Autopoll status register */
713 #define BGE_AUTOPOLLSTS_ERROR 0x00000001
714
715 /* Transmit MAC mode register */
716 #define BGE_TXMODE_RESET 0x00000001
717 #define BGE_TXMODE_ENABLE 0x00000002
718 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010
719 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020
720 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040
721
722 /* Transmit MAC status register */
723 #define BGE_TXSTAT_RX_XOFFED 0x00000001
724 #define BGE_TXSTAT_SENT_XOFF 0x00000002
725 #define BGE_TXSTAT_SENT_XON 0x00000004
726 #define BGE_TXSTAT_LINK_UP 0x00000008
727 #define BGE_TXSTAT_ODI_UFLOW 0x00000010
728 #define BGE_TXSTAT_ODI_OFLOW 0x00000020
729
730 /* Transmit MAC lengths register */
731 #define BGE_TXLEN_SLOTTIME 0x000000FF
732 #define BGE_TXLEN_IPG 0x00000F00
733 #define BGE_TXLEN_CRS 0x00003000
734
735 /* Receive MAC mode register */
736 #define BGE_RXMODE_RESET 0x00000001
737 #define BGE_RXMODE_ENABLE 0x00000002
738 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004
739 #define BGE_RXMODE_RX_GIANTS 0x00000020
740 #define BGE_RXMODE_RX_RUNTS 0x00000040
741 #define BGE_RXMODE_8022_LENCHECK 0x00000080
742 #define BGE_RXMODE_RX_PROMISC 0x00000100
743 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
744 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
745
746 /* Receive MAC status register */
747 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
748 #define BGE_RXSTAT_RCVD_XOFF 0x00000002
749 #define BGE_RXSTAT_RCVD_XON 0x00000004
750
751 /* Receive Rules Control register */
752 #define BGE_RXRULECTL_OFFSET 0x000000FF
753 #define BGE_RXRULECTL_CLASS 0x00001F00
754 #define BGE_RXRULECTL_HDRTYPE 0x0000E000
755 #define BGE_RXRULECTL_COMPARE_OP 0x00030000
756 #define BGE_RXRULECTL_MAP 0x01000000
757 #define BGE_RXRULECTL_DISCARD 0x02000000
758 #define BGE_RXRULECTL_MASK 0x04000000
759 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000
760 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000
761 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000
762 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000
763
764 /* Receive Rules Mask register */
765 #define BGE_RXRULEMASK_VALUE 0x0000FFFF
766 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000
767
768 /* SERDES configuration register */
769 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */
770 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */
771 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */
772 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */
773 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */
774 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */
775 #define BGE_SERDESCFG_TXMODE 0x00001000
776 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */
777 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */
778 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */
779 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */
780 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */
781 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */
782 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */
783 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */
784 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */
785
786 /* SERDES status register */
787 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */
788 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */
789
790 /* SGDIG config (not documented) */
791 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800
792 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000
793 #define BGE_SGDIGCFG_SEND 0x40000000
794 #define BGE_SGDIGCFG_AUTO 0x80000000
795
796 /* SGDIG status (not documented) */
797 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000
798 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000
799 #define BGE_SGDIGSTS_DONE 0x00000002
800
801
802 /* MI communication register */
803 #define BGE_MICOMM_DATA 0x0000FFFF
804 #define BGE_MICOMM_REG 0x001F0000
805 #define BGE_MICOMM_PHY 0x03E00000
806 #define BGE_MICOMM_CMD 0x0C000000
807 #define BGE_MICOMM_READFAIL 0x10000000
808 #define BGE_MICOMM_BUSY 0x20000000
809
810 #define BGE_MIREG(x) ((x & 0x1F) << 16)
811 #define BGE_MIPHY(x) ((x & 0x1F) << 21)
812 #define BGE_MICMD_WRITE 0x04000000
813 #define BGE_MICMD_READ 0x08000000
814
815 /* MI status register */
816 #define BGE_MISTS_LINK 0x00000001
817 #define BGE_MISTS_10MBPS 0x00000002
818
819 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002
820 #define BGE_MIMODE_AUTOPOLL 0x00000010
821 #define BGE_MIMODE_CLKCNT 0x001F0000
822
823
824 /*
825 * Send data initiator control registers.
826 */
827 #define BGE_SDI_MODE 0x0C00
828 #define BGE_SDI_STATUS 0x0C04
829 #define BGE_SDI_STATS_CTL 0x0C08
830 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C
831 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10
832 #define BGE_LOCSTATS_COS0 0x0C80
833 #define BGE_LOCSTATS_COS1 0x0C84
834 #define BGE_LOCSTATS_COS2 0x0C88
835 #define BGE_LOCSTATS_COS3 0x0C8C
836 #define BGE_LOCSTATS_COS4 0x0C90
837 #define BGE_LOCSTATS_COS5 0x0C84
838 #define BGE_LOCSTATS_COS6 0x0C98
839 #define BGE_LOCSTATS_COS7 0x0C9C
840 #define BGE_LOCSTATS_COS8 0x0CA0
841 #define BGE_LOCSTATS_COS9 0x0CA4
842 #define BGE_LOCSTATS_COS10 0x0CA8
843 #define BGE_LOCSTATS_COS11 0x0CAC
844 #define BGE_LOCSTATS_COS12 0x0CB0
845 #define BGE_LOCSTATS_COS13 0x0CB4
846 #define BGE_LOCSTATS_COS14 0x0CB8
847 #define BGE_LOCSTATS_COS15 0x0CBC
848 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0
849 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4
850 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8
851 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC
852 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0
853 #define BGE_LOCSTATS_IRQS 0x0CD4
854 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8
855 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC
856
857 /* Send Data Initiator mode register */
858 #define BGE_SDIMODE_RESET 0x00000001
859 #define BGE_SDIMODE_ENABLE 0x00000002
860 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004
861
862 /* Send Data Initiator stats register */
863 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004
864
865 /* Send Data Initiator stats control register */
866 #define BGE_SDISTATSCTL_ENABLE 0x00000001
867 #define BGE_SDISTATSCTL_FASTER 0x00000002
868 #define BGE_SDISTATSCTL_CLEAR 0x00000004
869 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008
870 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010
871
872 /*
873 * Send Data Completion Control registers
874 */
875 #define BGE_SDC_MODE 0x1000
876 #define BGE_SDC_STATUS 0x1004
877
878 /* Send Data completion mode register */
879 #define BGE_SDCMODE_RESET 0x00000001
880 #define BGE_SDCMODE_ENABLE 0x00000002
881 #define BGE_SDCMODE_ATTN 0x00000004
882 #define BGE_SDCMODE_CDELAY 0x00000010
883
884 /* Send Data completion status register */
885 #define BGE_SDCSTAT_ATTN 0x00000004
886
887 /*
888 * Send BD Ring Selector Control registers
889 */
890 #define BGE_SRS_MODE 0x1400
891 #define BGE_SRS_STATUS 0x1404
892 #define BGE_SRS_HWDIAG 0x1408
893 #define BGE_SRS_LOC_NIC_CONS0 0x1440
894 #define BGE_SRS_LOC_NIC_CONS1 0x1444
895 #define BGE_SRS_LOC_NIC_CONS2 0x1448
896 #define BGE_SRS_LOC_NIC_CONS3 0x144C
897 #define BGE_SRS_LOC_NIC_CONS4 0x1450
898 #define BGE_SRS_LOC_NIC_CONS5 0x1454
899 #define BGE_SRS_LOC_NIC_CONS6 0x1458
900 #define BGE_SRS_LOC_NIC_CONS7 0x145C
901 #define BGE_SRS_LOC_NIC_CONS8 0x1460
902 #define BGE_SRS_LOC_NIC_CONS9 0x1464
903 #define BGE_SRS_LOC_NIC_CONS10 0x1468
904 #define BGE_SRS_LOC_NIC_CONS11 0x146C
905 #define BGE_SRS_LOC_NIC_CONS12 0x1470
906 #define BGE_SRS_LOC_NIC_CONS13 0x1474
907 #define BGE_SRS_LOC_NIC_CONS14 0x1478
908 #define BGE_SRS_LOC_NIC_CONS15 0x147C
909
910 /* Send BD Ring Selector Mode register */
911 #define BGE_SRSMODE_RESET 0x00000001
912 #define BGE_SRSMODE_ENABLE 0x00000002
913 #define BGE_SRSMODE_ATTN 0x00000004
914
915 /* Send BD Ring Selector Status register */
916 #define BGE_SRSSTAT_ERROR 0x00000004
917
918 /* Send BD Ring Selector HW Diagnostics register */
919 #define BGE_SRSHWDIAG_STATE 0x0000000F
920 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0
921 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00
922 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000
923
924 /*
925 * Send BD Initiator Selector Control registers
926 */
927 #define BGE_SBDI_MODE 0x1800
928 #define BGE_SBDI_STATUS 0x1804
929 #define BGE_SBDI_LOC_NIC_PROD0 0x1808
930 #define BGE_SBDI_LOC_NIC_PROD1 0x180C
931 #define BGE_SBDI_LOC_NIC_PROD2 0x1810
932 #define BGE_SBDI_LOC_NIC_PROD3 0x1814
933 #define BGE_SBDI_LOC_NIC_PROD4 0x1818
934 #define BGE_SBDI_LOC_NIC_PROD5 0x181C
935 #define BGE_SBDI_LOC_NIC_PROD6 0x1820
936 #define BGE_SBDI_LOC_NIC_PROD7 0x1824
937 #define BGE_SBDI_LOC_NIC_PROD8 0x1828
938 #define BGE_SBDI_LOC_NIC_PROD9 0x182C
939 #define BGE_SBDI_LOC_NIC_PROD10 0x1830
940 #define BGE_SBDI_LOC_NIC_PROD11 0x1834
941 #define BGE_SBDI_LOC_NIC_PROD12 0x1838
942 #define BGE_SBDI_LOC_NIC_PROD13 0x183C
943 #define BGE_SBDI_LOC_NIC_PROD14 0x1840
944 #define BGE_SBDI_LOC_NIC_PROD15 0x1844
945
946 /* Send BD Initiator Mode register */
947 #define BGE_SBDIMODE_RESET 0x00000001
948 #define BGE_SBDIMODE_ENABLE 0x00000002
949 #define BGE_SBDIMODE_ATTN 0x00000004
950
951 /* Send BD Initiator Status register */
952 #define BGE_SBDISTAT_ERROR 0x00000004
953
954 /*
955 * Send BD Completion Control registers
956 */
957 #define BGE_SBDC_MODE 0x1C00
958 #define BGE_SBDC_STATUS 0x1C04
959
960 /* Send BD Completion Control Mode register */
961 #define BGE_SBDCMODE_RESET 0x00000001
962 #define BGE_SBDCMODE_ENABLE 0x00000002
963 #define BGE_SBDCMODE_ATTN 0x00000004
964
965 /* Send BD Completion Control Status register */
966 #define BGE_SBDCSTAT_ATTN 0x00000004
967
968 /*
969 * Receive List Placement Control registers
970 */
971 #define BGE_RXLP_MODE 0x2000
972 #define BGE_RXLP_STATUS 0x2004
973 #define BGE_RXLP_SEL_LIST_LOCK 0x2008
974 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C
975 #define BGE_RXLP_CFG 0x2010
976 #define BGE_RXLP_STATS_CTL 0x2014
977 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018
978 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C
979 #define BGE_RXLP_HEAD0 0x2100
980 #define BGE_RXLP_TAIL0 0x2104
981 #define BGE_RXLP_COUNT0 0x2108
982 #define BGE_RXLP_HEAD1 0x2110
983 #define BGE_RXLP_TAIL1 0x2114
984 #define BGE_RXLP_COUNT1 0x2118
985 #define BGE_RXLP_HEAD2 0x2120
986 #define BGE_RXLP_TAIL2 0x2124
987 #define BGE_RXLP_COUNT2 0x2128
988 #define BGE_RXLP_HEAD3 0x2130
989 #define BGE_RXLP_TAIL3 0x2134
990 #define BGE_RXLP_COUNT3 0x2138
991 #define BGE_RXLP_HEAD4 0x2140
992 #define BGE_RXLP_TAIL4 0x2144
993 #define BGE_RXLP_COUNT4 0x2148
994 #define BGE_RXLP_HEAD5 0x2150
995 #define BGE_RXLP_TAIL5 0x2154
996 #define BGE_RXLP_COUNT5 0x2158
997 #define BGE_RXLP_HEAD6 0x2160
998 #define BGE_RXLP_TAIL6 0x2164
999 #define BGE_RXLP_COUNT6 0x2168
1000 #define BGE_RXLP_HEAD7 0x2170
1001 #define BGE_RXLP_TAIL7 0x2174
1002 #define BGE_RXLP_COUNT7 0x2178
1003 #define BGE_RXLP_HEAD8 0x2180
1004 #define BGE_RXLP_TAIL8 0x2184
1005 #define BGE_RXLP_COUNT8 0x2188
1006 #define BGE_RXLP_HEAD9 0x2190
1007 #define BGE_RXLP_TAIL9 0x2194
1008 #define BGE_RXLP_COUNT9 0x2198
1009 #define BGE_RXLP_HEAD10 0x21A0
1010 #define BGE_RXLP_TAIL10 0x21A4
1011 #define BGE_RXLP_COUNT10 0x21A8
1012 #define BGE_RXLP_HEAD11 0x21B0
1013 #define BGE_RXLP_TAIL11 0x21B4
1014 #define BGE_RXLP_COUNT11 0x21B8
1015 #define BGE_RXLP_HEAD12 0x21C0
1016 #define BGE_RXLP_TAIL12 0x21C4
1017 #define BGE_RXLP_COUNT12 0x21C8
1018 #define BGE_RXLP_HEAD13 0x21D0
1019 #define BGE_RXLP_TAIL13 0x21D4
1020 #define BGE_RXLP_COUNT13 0x21D8
1021 #define BGE_RXLP_HEAD14 0x21E0
1022 #define BGE_RXLP_TAIL14 0x21E4
1023 #define BGE_RXLP_COUNT14 0x21E8
1024 #define BGE_RXLP_HEAD15 0x21F0
1025 #define BGE_RXLP_TAIL15 0x21F4
1026 #define BGE_RXLP_COUNT15 0x21F8
1027 #define BGE_RXLP_LOCSTAT_COS0 0x2200
1028 #define BGE_RXLP_LOCSTAT_COS1 0x2204
1029 #define BGE_RXLP_LOCSTAT_COS2 0x2208
1030 #define BGE_RXLP_LOCSTAT_COS3 0x220C
1031 #define BGE_RXLP_LOCSTAT_COS4 0x2210
1032 #define BGE_RXLP_LOCSTAT_COS5 0x2214
1033 #define BGE_RXLP_LOCSTAT_COS6 0x2218
1034 #define BGE_RXLP_LOCSTAT_COS7 0x221C
1035 #define BGE_RXLP_LOCSTAT_COS8 0x2220
1036 #define BGE_RXLP_LOCSTAT_COS9 0x2224
1037 #define BGE_RXLP_LOCSTAT_COS10 0x2228
1038 #define BGE_RXLP_LOCSTAT_COS11 0x222C
1039 #define BGE_RXLP_LOCSTAT_COS12 0x2230
1040 #define BGE_RXLP_LOCSTAT_COS13 0x2234
1041 #define BGE_RXLP_LOCSTAT_COS14 0x2238
1042 #define BGE_RXLP_LOCSTAT_COS15 0x223C
1043 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240
1044 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244
1045 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248
1046 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C
1047 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250
1048 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
1049 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
1050
1051
1052 /* Receive List Placement mode register */
1053 #define BGE_RXLPMODE_RESET 0x00000001
1054 #define BGE_RXLPMODE_ENABLE 0x00000002
1055 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004
1056 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008
1057 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010
1058
1059 /* Receive List Placement Status register */
1060 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004
1061 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008
1062 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010
1063
1064 /*
1065 * Receive Data and Receive BD Initiator Control Registers
1066 */
1067 #define BGE_RDBDI_MODE 0x2400
1068 #define BGE_RDBDI_STATUS 0x2404
1069 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440
1070 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444
1071 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448
1072 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C
1073 #define BGE_RX_STD_RCB_HADDR_HI 0x2450
1074 #define BGE_RX_STD_RCB_HADDR_LO 0x2454
1075 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458
1076 #define BGE_RX_STD_RCB_NICADDR 0x245C
1077 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460
1078 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464
1079 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468
1080 #define BGE_RX_MINI_RCB_NICADDR 0x246C
1081 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470
1082 #define BGE_RDBDI_STD_RX_CONS 0x2474
1083 #define BGE_RDBDI_MINI_RX_CONS 0x2478
1084 #define BGE_RDBDI_RETURN_PROD0 0x2480
1085 #define BGE_RDBDI_RETURN_PROD1 0x2484
1086 #define BGE_RDBDI_RETURN_PROD2 0x2488
1087 #define BGE_RDBDI_RETURN_PROD3 0x248C
1088 #define BGE_RDBDI_RETURN_PROD4 0x2490
1089 #define BGE_RDBDI_RETURN_PROD5 0x2494
1090 #define BGE_RDBDI_RETURN_PROD6 0x2498
1091 #define BGE_RDBDI_RETURN_PROD7 0x249C
1092 #define BGE_RDBDI_RETURN_PROD8 0x24A0
1093 #define BGE_RDBDI_RETURN_PROD9 0x24A4
1094 #define BGE_RDBDI_RETURN_PROD10 0x24A8
1095 #define BGE_RDBDI_RETURN_PROD11 0x24AC
1096 #define BGE_RDBDI_RETURN_PROD12 0x24B0
1097 #define BGE_RDBDI_RETURN_PROD13 0x24B4
1098 #define BGE_RDBDI_RETURN_PROD14 0x24B8
1099 #define BGE_RDBDI_RETURN_PROD15 0x24BC
1100 #define BGE_RDBDI_HWDIAG 0x24C0
1101
1102
1103 /* Receive Data and Receive BD Initiator Mode register */
1104 #define BGE_RDBDIMODE_RESET 0x00000001
1105 #define BGE_RDBDIMODE_ENABLE 0x00000002
1106 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004
1107 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008
1108 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010
1109
1110 /* Receive Data and Receive BD Initiator Status register */
1111 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004
1112 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
1113 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
1114
1115
1116 /*
1117 * Receive Data Completion Control registers
1118 */
1119 #define BGE_RDC_MODE 0x2800
1120
1121 /* Receive Data Completion Mode register */
1122 #define BGE_RDCMODE_RESET 0x00000001
1123 #define BGE_RDCMODE_ENABLE 0x00000002
1124 #define BGE_RDCMODE_ATTN 0x00000004
1125
1126 /*
1127 * Receive BD Initiator Control registers
1128 */
1129 #define BGE_RBDI_MODE 0x2C00
1130 #define BGE_RBDI_STATUS 0x2C04
1131 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08
1132 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C
1133 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10
1134 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14
1135 #define BGE_RBDI_STD_REPL_THRESH 0x2C18
1136 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C
1137
1138 /* Receive BD Initiator Mode register */
1139 #define BGE_RBDIMODE_RESET 0x00000001
1140 #define BGE_RBDIMODE_ENABLE 0x00000002
1141 #define BGE_RBDIMODE_ATTN 0x00000004
1142
1143 /* Receive BD Initiator Status register */
1144 #define BGE_RBDISTAT_ATTN 0x00000004
1145
1146 /*
1147 * Receive BD Completion Control registers
1148 */
1149 #define BGE_RBDC_MODE 0x3000
1150 #define BGE_RBDC_STATUS 0x3004
1151 #define BGE_RBDC_JUMBO_BD_PROD 0x3008
1152 #define BGE_RBDC_STD_BD_PROD 0x300C
1153 #define BGE_RBDC_MINI_BD_PROD 0x3010
1154
1155 /* Receive BD completion mode register */
1156 #define BGE_RBDCMODE_RESET 0x00000001
1157 #define BGE_RBDCMODE_ENABLE 0x00000002
1158 #define BGE_RBDCMODE_ATTN 0x00000004
1159
1160 /* Receive BD completion status register */
1161 #define BGE_RBDCSTAT_ERROR 0x00000004
1162
1163 /*
1164 * Receive List Selector Control registers
1165 */
1166 #define BGE_RXLS_MODE 0x3400
1167 #define BGE_RXLS_STATUS 0x3404
1168
1169 /* Receive List Selector Mode register */
1170 #define BGE_RXLSMODE_RESET 0x00000001
1171 #define BGE_RXLSMODE_ENABLE 0x00000002
1172 #define BGE_RXLSMODE_ATTN 0x00000004
1173
1174 /* Receive List Selector Status register */
1175 #define BGE_RXLSSTAT_ERROR 0x00000004
1176
1177 /*
1178 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
1179 */
1180 #define BGE_MBCF_MODE 0x3800
1181 #define BGE_MBCF_STATUS 0x3804
1182
1183 /* Mbuf Cluster Free mode register */
1184 #define BGE_MBCFMODE_RESET 0x00000001
1185 #define BGE_MBCFMODE_ENABLE 0x00000002
1186 #define BGE_MBCFMODE_ATTN 0x00000004
1187
1188 /* Mbuf Cluster Free status register */
1189 #define BGE_MBCFSTAT_ERROR 0x00000004
1190
1191 /*
1192 * Host Coalescing Control registers
1193 */
1194 #define BGE_HCC_MODE 0x3C00
1195 #define BGE_HCC_STATUS 0x3C04
1196 #define BGE_HCC_RX_COAL_TICKS 0x3C08
1197 #define BGE_HCC_TX_COAL_TICKS 0x3C0C
1198 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10
1199 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14
1200 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */
1201 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */
1202 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */
1203 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */
1204 #define BGE_HCC_STATS_TICKS 0x3C28
1205 #define BGE_HCC_STATS_ADDR_HI 0x3C30
1206 #define BGE_HCC_STATS_ADDR_LO 0x3C34
1207 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38
1208 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C
1209 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
1210 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
1211 #define BGE_FLOW_ATTN 0x3C48
1212 #define BGE_HCC_JUMBO_BD_CONS 0x3C50
1213 #define BGE_HCC_STD_BD_CONS 0x3C54
1214 #define BGE_HCC_MINI_BD_CONS 0x3C58
1215 #define BGE_HCC_RX_RETURN_PROD0 0x3C80
1216 #define BGE_HCC_RX_RETURN_PROD1 0x3C84
1217 #define BGE_HCC_RX_RETURN_PROD2 0x3C88
1218 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C
1219 #define BGE_HCC_RX_RETURN_PROD4 0x3C90
1220 #define BGE_HCC_RX_RETURN_PROD5 0x3C94
1221 #define BGE_HCC_RX_RETURN_PROD6 0x3C98
1222 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C
1223 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0
1224 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4
1225 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8
1226 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC
1227 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0
1228 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4
1229 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8
1230 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC
1231 #define BGE_HCC_TX_BD_CONS0 0x3CC0
1232 #define BGE_HCC_TX_BD_CONS1 0x3CC4
1233 #define BGE_HCC_TX_BD_CONS2 0x3CC8
1234 #define BGE_HCC_TX_BD_CONS3 0x3CCC
1235 #define BGE_HCC_TX_BD_CONS4 0x3CD0
1236 #define BGE_HCC_TX_BD_CONS5 0x3CD4
1237 #define BGE_HCC_TX_BD_CONS6 0x3CD8
1238 #define BGE_HCC_TX_BD_CONS7 0x3CDC
1239 #define BGE_HCC_TX_BD_CONS8 0x3CE0
1240 #define BGE_HCC_TX_BD_CONS9 0x3CE4
1241 #define BGE_HCC_TX_BD_CONS10 0x3CE8
1242 #define BGE_HCC_TX_BD_CONS11 0x3CEC
1243 #define BGE_HCC_TX_BD_CONS12 0x3CF0
1244 #define BGE_HCC_TX_BD_CONS13 0x3CF4
1245 #define BGE_HCC_TX_BD_CONS14 0x3CF8
1246 #define BGE_HCC_TX_BD_CONS15 0x3CFC
1247
1248
1249 /* Host coalescing mode register */
1250 #define BGE_HCCMODE_RESET 0x00000001
1251 #define BGE_HCCMODE_ENABLE 0x00000002
1252 #define BGE_HCCMODE_ATTN 0x00000004
1253 #define BGE_HCCMODE_COAL_NOW 0x00000008
1254 #define BGE_HCCMODE_MSI_BITS 0x00000070
1255 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180
1256
1257 #define BGE_STATBLKSZ_FULL 0x00000000
1258 #define BGE_STATBLKSZ_64BYTE 0x00000080
1259 #define BGE_STATBLKSZ_32BYTE 0x00000100
1260
1261 /* Host coalescing status register */
1262 #define BGE_HCCSTAT_ERROR 0x00000004
1263
1264 /* Flow attention register */
1265 #define BGE_FLOWATTN_MB_LOWAT 0x00000040
1266 #define BGE_FLOWATTN_MEMARB 0x00000080
1267 #define BGE_FLOWATTN_HOSTCOAL 0x00008000
1268 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000
1269 #define BGE_FLOWATTN_RCB_INVAL 0x00020000
1270 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000
1271 #define BGE_FLOWATTN_RDBDI 0x00080000
1272 #define BGE_FLOWATTN_RXLS 0x00100000
1273 #define BGE_FLOWATTN_RXLP 0x00200000
1274 #define BGE_FLOWATTN_RBDC 0x00400000
1275 #define BGE_FLOWATTN_RBDI 0x00800000
1276 #define BGE_FLOWATTN_SDC 0x08000000
1277 #define BGE_FLOWATTN_SDI 0x10000000
1278 #define BGE_FLOWATTN_SRS 0x20000000
1279 #define BGE_FLOWATTN_SBDC 0x40000000
1280 #define BGE_FLOWATTN_SBDI 0x80000000
1281
1282 /*
1283 * Memory arbiter registers
1284 */
1285 #define BGE_MARB_MODE 0x4000
1286 #define BGE_MARB_STATUS 0x4004
1287 #define BGE_MARB_TRAPADDR_HI 0x4008
1288 #define BGE_MARB_TRAPADDR_LO 0x400C
1289
1290 /* Memory arbiter mode register */
1291 #define BGE_MARBMODE_RESET 0x00000001
1292 #define BGE_MARBMODE_ENABLE 0x00000002
1293 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004
1294 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008
1295 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010
1296 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020
1297 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040
1298 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080
1299 #define BGE_MARBMODE_PCI_TRAP 0x00000100
1300 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200
1301 #define BGE_MARBMODE_RXQ_TRAP 0x00000400
1302 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800
1303 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000
1304 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000
1305 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000
1306 #define BGE_MARBMODE_MBUF_TRAP 0x00008000
1307 #define BGE_MARBMODE_TXDI_TRAP 0x00010000
1308 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000
1309 #define BGE_MARBMODE_TXBD_TRAP 0x00040000
1310 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000
1311 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000
1312 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000
1313 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
1314 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000
1315 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000
1316 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000
1317
1318 /* Memory arbiter status register */
1319 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004
1320 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008
1321 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010
1322 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020
1323 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040
1324 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080
1325 #define BGE_MARBSTAT_PCI_TRAP 0x00000100
1326 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200
1327 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400
1328 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800
1329 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000
1330 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000
1331 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000
1332 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000
1333 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000
1334 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000
1335 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000
1336 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000
1337 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000
1338 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000
1339 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
1340 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000
1341 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000
1342 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000
1343
1344 /*
1345 * Buffer manager control registers
1346 */
1347 #define BGE_BMAN_MODE 0x4400
1348 #define BGE_BMAN_STATUS 0x4404
1349 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408
1350 #define BGE_BMAN_MBUFPOOL_LEN 0x440C
1351 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410
1352 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414
1353 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418
1354 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C
1355 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420
1356 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424
1357 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428
1358 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C
1359 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430
1360 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434
1361 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438
1362 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C
1363 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440
1364 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444
1365 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448
1366 #define BGE_BMAN_HWDIAG_1 0x444C
1367 #define BGE_BMAN_HWDIAG_2 0x4450
1368 #define BGE_BMAN_HWDIAG_3 0x4454
1369
1370 /* Buffer manager mode register */
1371 #define BGE_BMANMODE_RESET 0x00000001
1372 #define BGE_BMANMODE_ENABLE 0x00000002
1373 #define BGE_BMANMODE_ATTN 0x00000004
1374 #define BGE_BMANMODE_TESTMODE 0x00000008
1375 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010
1376
1377 /* Buffer manager status register */
1378 #define BGE_BMANSTAT_ERRO 0x00000004
1379 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
1380
1381
1382 /*
1383 * Read DMA Control registers
1384 */
1385 #define BGE_RDMA_MODE 0x4800
1386 #define BGE_RDMA_STATUS 0x4804
1387
1388 /* Read DMA mode register */
1389 #define BGE_RDMAMODE_RESET 0x00000001
1390 #define BGE_RDMAMODE_ENABLE 0x00000002
1391 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1392 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1393 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010
1394 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1395 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1396 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1397 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1398 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
1399 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
1400 #define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800
1401 #define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000
1402 #define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000
1403 #define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000
1404 #define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000
1405
1406 /* Read DMA status register */
1407 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1408 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1409 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010
1410 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1411 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1412 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1413 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1414 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
1415
1416 /*
1417 * Write DMA control registers
1418 */
1419 #define BGE_WDMA_MODE 0x4C00
1420 #define BGE_WDMA_STATUS 0x4C04
1421
1422 /* Write DMA mode register */
1423 #define BGE_WDMAMODE_RESET 0x00000001
1424 #define BGE_WDMAMODE_ENABLE 0x00000002
1425 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1426 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1427 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010
1428 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1429 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1430 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1431 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1432 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
1433 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
1434 #define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000
1435
1436 /* Write DMA status register */
1437 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1438 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1439 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010
1440 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1441 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1442 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1443 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1444 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
1445
1446
1447 /*
1448 * RX CPU registers
1449 */
1450 #define BGE_RXCPU_MODE 0x5000
1451 #define BGE_RXCPU_STATUS 0x5004
1452 #define BGE_RXCPU_PC 0x501C
1453
1454 /* RX CPU mode register */
1455 #define BGE_RXCPUMODE_RESET 0x00000001
1456 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002
1457 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004
1458 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1459 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010
1460 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020
1461 #define BGE_RXCPUMODE_ROMFAIL 0x00000040
1462 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080
1463 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100
1464 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1465 #define BGE_RXCPUMODE_HALTCPU 0x00000400
1466 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800
1467 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1468 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000
1469
1470 /* RX CPU status register */
1471 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001
1472 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1473 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004
1474 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008
1475 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010
1476 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020
1477 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1478 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080
1479 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100
1480 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200
1481 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000
1482 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000
1483 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1484 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1485 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1486 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1487 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000
1488
1489 /*
1490 * V? CPU registers
1491 */
1492 #define BGE_VCPU_STATUS 0x5100
1493 #define BGE_VCPU_EXT_CTRL 0x6890
1494
1495 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000
1496 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000
1497
1498 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1499 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1500
1501 /*
1502 * TX CPU registers
1503 */
1504 #define BGE_TXCPU_MODE 0x5400
1505 #define BGE_TXCPU_STATUS 0x5404
1506 #define BGE_TXCPU_PC 0x541C
1507
1508 /* TX CPU mode register */
1509 #define BGE_TXCPUMODE_RESET 0x00000001
1510 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002
1511 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004
1512 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1513 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010
1514 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020
1515 #define BGE_TXCPUMODE_ROMFAIL 0x00000040
1516 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080
1517 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100
1518 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1519 #define BGE_TXCPUMODE_HALTCPU 0x00000400
1520 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800
1521 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1522
1523 /* TX CPU status register */
1524 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001
1525 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1526 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004
1527 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008
1528 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010
1529 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020
1530 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1531 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080
1532 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100
1533 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200
1534 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000
1535 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000
1536 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1537 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1538 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1539 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1540 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
1541
1542
1543 /*
1544 * Low priority mailbox registers
1545 */
1546 #define BGE_LPMBX_IRQ0_HI 0x5800
1547 #define BGE_LPMBX_IRQ0_LO 0x5804
1548 #define BGE_LPMBX_IRQ1_HI 0x5808
1549 #define BGE_LPMBX_IRQ1_LO 0x580C
1550 #define BGE_LPMBX_IRQ2_HI 0x5810
1551 #define BGE_LPMBX_IRQ2_LO 0x5814
1552 #define BGE_LPMBX_IRQ3_HI 0x5818
1553 #define BGE_LPMBX_IRQ3_LO 0x581C
1554 #define BGE_LPMBX_GEN0_HI 0x5820
1555 #define BGE_LPMBX_GEN0_LO 0x5824
1556 #define BGE_LPMBX_GEN1_HI 0x5828
1557 #define BGE_LPMBX_GEN1_LO 0x582C
1558 #define BGE_LPMBX_GEN2_HI 0x5830
1559 #define BGE_LPMBX_GEN2_LO 0x5834
1560 #define BGE_LPMBX_GEN3_HI 0x5828
1561 #define BGE_LPMBX_GEN3_LO 0x582C
1562 #define BGE_LPMBX_GEN4_HI 0x5840
1563 #define BGE_LPMBX_GEN4_LO 0x5844
1564 #define BGE_LPMBX_GEN5_HI 0x5848
1565 #define BGE_LPMBX_GEN5_LO 0x584C
1566 #define BGE_LPMBX_GEN6_HI 0x5850
1567 #define BGE_LPMBX_GEN6_LO 0x5854
1568 #define BGE_LPMBX_GEN7_HI 0x5858
1569 #define BGE_LPMBX_GEN7_LO 0x585C
1570 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860
1571 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864
1572 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868
1573 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C
1574 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870
1575 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874
1576 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878
1577 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C
1578 #define BGE_LPMBX_RX_CONS0_HI 0x5880
1579 #define BGE_LPMBX_RX_CONS0_LO 0x5884
1580 #define BGE_LPMBX_RX_CONS1_HI 0x5888
1581 #define BGE_LPMBX_RX_CONS1_LO 0x588C
1582 #define BGE_LPMBX_RX_CONS2_HI 0x5890
1583 #define BGE_LPMBX_RX_CONS2_LO 0x5894
1584 #define BGE_LPMBX_RX_CONS3_HI 0x5898
1585 #define BGE_LPMBX_RX_CONS3_LO 0x589C
1586 #define BGE_LPMBX_RX_CONS4_HI 0x58A0
1587 #define BGE_LPMBX_RX_CONS4_LO 0x58A4
1588 #define BGE_LPMBX_RX_CONS5_HI 0x58A8
1589 #define BGE_LPMBX_RX_CONS5_LO 0x58AC
1590 #define BGE_LPMBX_RX_CONS6_HI 0x58B0
1591 #define BGE_LPMBX_RX_CONS6_LO 0x58B4
1592 #define BGE_LPMBX_RX_CONS7_HI 0x58B8
1593 #define BGE_LPMBX_RX_CONS7_LO 0x58BC
1594 #define BGE_LPMBX_RX_CONS8_HI 0x58C0
1595 #define BGE_LPMBX_RX_CONS8_LO 0x58C4
1596 #define BGE_LPMBX_RX_CONS9_HI 0x58C8
1597 #define BGE_LPMBX_RX_CONS9_LO 0x58CC
1598 #define BGE_LPMBX_RX_CONS10_HI 0x58D0
1599 #define BGE_LPMBX_RX_CONS10_LO 0x58D4
1600 #define BGE_LPMBX_RX_CONS11_HI 0x58D8
1601 #define BGE_LPMBX_RX_CONS11_LO 0x58DC
1602 #define BGE_LPMBX_RX_CONS12_HI 0x58E0
1603 #define BGE_LPMBX_RX_CONS12_LO 0x58E4
1604 #define BGE_LPMBX_RX_CONS13_HI 0x58E8
1605 #define BGE_LPMBX_RX_CONS13_LO 0x58EC
1606 #define BGE_LPMBX_RX_CONS14_HI 0x58F0
1607 #define BGE_LPMBX_RX_CONS14_LO 0x58F4
1608 #define BGE_LPMBX_RX_CONS15_HI 0x58F8
1609 #define BGE_LPMBX_RX_CONS15_LO 0x58FC
1610 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900
1611 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904
1612 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908
1613 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C
1614 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910
1615 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914
1616 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918
1617 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C
1618 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920
1619 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924
1620 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928
1621 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C
1622 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930
1623 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934
1624 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938
1625 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C
1626 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940
1627 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944
1628 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948
1629 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C
1630 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950
1631 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954
1632 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958
1633 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C
1634 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960
1635 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964
1636 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968
1637 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C
1638 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970
1639 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974
1640 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978
1641 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C
1642 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980
1643 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984
1644 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988
1645 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C
1646 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990
1647 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994
1648 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998
1649 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C
1650 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0
1651 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4
1652 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8
1653 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC
1654 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0
1655 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4
1656 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8
1657 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC
1658 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0
1659 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4
1660 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8
1661 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC
1662 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0
1663 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4
1664 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8
1665 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC
1666 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0
1667 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4
1668 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8
1669 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC
1670 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0
1671 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4
1672 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8
1673 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC
1674
1675 /*
1676 * Flow throw Queue reset register
1677 */
1678 #define BGE_FTQ_RESET 0x5C00
1679
1680 #define BGE_FTQRESET_DMAREAD 0x00000002
1681 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004
1682 #define BGE_FTQRESET_DMADONE 0x00000010
1683 #define BGE_FTQRESET_SBDC 0x00000020
1684 #define BGE_FTQRESET_SDI 0x00000040
1685 #define BGE_FTQRESET_WDMA 0x00000080
1686 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100
1687 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200
1688 #define BGE_FTQRESET_SDC 0x00000400
1689 #define BGE_FTQRESET_HCC 0x00000800
1690 #define BGE_FTQRESET_TXFIFO 0x00001000
1691 #define BGE_FTQRESET_MBC 0x00002000
1692 #define BGE_FTQRESET_RBDC 0x00004000
1693 #define BGE_FTQRESET_RXLP 0x00008000
1694 #define BGE_FTQRESET_RDBDI 0x00010000
1695 #define BGE_FTQRESET_RDC 0x00020000
1696 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000
1697
1698 /*
1699 * Message Signaled Interrupt registers
1700 */
1701 #define BGE_MSI_MODE 0x6000
1702 #define BGE_MSI_STATUS 0x6004
1703 #define BGE_MSI_FIFOACCESS 0x6008
1704
1705 /* MSI mode register */
1706 #define BGE_MSIMODE_RESET 0x00000001
1707 #define BGE_MSIMODE_ENABLE 0x00000002
1708 #define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020
1709 #define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080
1710
1711 /* MSI status register */
1712 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
1713 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1714 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010
1715 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
1716 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
1717
1718
1719 /*
1720 * DMA Completion registers
1721 */
1722 #define BGE_DMAC_MODE 0x6400
1723
1724 /* DMA Completion mode register */
1725 #define BGE_DMACMODE_RESET 0x00000001
1726 #define BGE_DMACMODE_ENABLE 0x00000002
1727
1728
1729 /*
1730 * General control registers.
1731 */
1732 #define BGE_MODE_CTL 0x6800
1733 #define BGE_MISC_CFG 0x6804
1734 #define BGE_MISC_LOCAL_CTL 0x6808
1735 #define BGE_CPU_EVENT 0x6810
1736 #define BGE_EE_ADDR 0x6838
1737 #define BGE_EE_DATA 0x683C
1738 #define BGE_EE_CTL 0x6840
1739 #define BGE_MDI_CTL 0x6844
1740 #define BGE_EE_DELAY 0x6848
1741 #define BGE_FASTBOOT_PC 0x6894
1742
1743 /*
1744 * NVRAM Control registers
1745 */
1746 #define BGE_NVRAM_CMD 0x7000
1747 #define BGE_NVRAM_STAT 0x7004
1748 #define BGE_NVRAM_WRDATA 0x7008
1749 #define BGE_NVRAM_ADDR 0x700c
1750 #define BGE_NVRAM_RDDATA 0x7010
1751 #define BGE_NVRAM_CFG1 0x7014
1752 #define BGE_NVRAM_CFG2 0x7018
1753 #define BGE_NVRAM_CFG3 0x701c
1754 #define BGE_NVRAM_SWARB 0x7020
1755 #define BGE_NVRAM_ACCESS 0x7024
1756 #define BGE_NVRAM_WRITE1 0x7028
1757
1758 #define BGE_NVRAMCMD_RESET 0x00000001
1759 #define BGE_NVRAMCMD_DONE 0x00000008
1760 #define BGE_NVRAMCMD_START 0x00000010
1761 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */
1762 #define BGE_NVRAMCMD_ERASE 0x00000040
1763 #define BGE_NVRAMCMD_FIRST 0x00000080
1764 #define BGE_NVRAMCMD_LAST 0x00000100
1765
1766 #define BGE_NVRAM_READCMD \
1767 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1768 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE)
1769 #define BGE_NVRAM_WRITECMD \
1770 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1771 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR)
1772
1773 #define BGE_NVRAMSWARB_SET0 0x00000001
1774 #define BGE_NVRAMSWARB_SET1 0x00000002
1775 #define BGE_NVRAMSWARB_SET2 0x00000003
1776 #define BGE_NVRAMSWARB_SET3 0x00000004
1777 #define BGE_NVRAMSWARB_CLR0 0x00000010
1778 #define BGE_NVRAMSWARB_CLR1 0x00000020
1779 #define BGE_NVRAMSWARB_CLR2 0x00000040
1780 #define BGE_NVRAMSWARB_CLR3 0x00000080
1781 #define BGE_NVRAMSWARB_GNT0 0x00000100
1782 #define BGE_NVRAMSWARB_GNT1 0x00000200
1783 #define BGE_NVRAMSWARB_GNT2 0x00000400
1784 #define BGE_NVRAMSWARB_GNT3 0x00000800
1785 #define BGE_NVRAMSWARB_REQ0 0x00001000
1786 #define BGE_NVRAMSWARB_REQ1 0x00002000
1787 #define BGE_NVRAMSWARB_REQ2 0x00004000
1788 #define BGE_NVRAMSWARB_REQ3 0x00008000
1789
1790 #define BGE_NVRAMACC_ENABLE 0x00000001
1791 #define BGE_NVRAMACC_WRENABLE 0x00000002
1792
1793 /* Mode control register */
1794 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
1795 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002
1796 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004
1797 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010
1798 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020
1799 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200
1800 #define BGE_MODECTL_NO_RX_CRC 0x00000400
1801 #define BGE_MODECTL_RX_BADFRAMES 0x00000800
1802 #define BGE_MODECTL_NO_TX_INTR 0x00002000
1803 #define BGE_MODECTL_NO_RX_INTR 0x00004000
1804 #define BGE_MODECTL_FORCE_PCI32 0x00008000
1805 #define BGE_MODECTL_STACKUP 0x00010000
1806 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000
1807 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000
1808 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000
1809 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000
1810 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000
1811 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000
1812 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000
1813 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000
1814 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000
1815 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000
1816
1817 /* Misc. config register */
1818 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001
1819 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE
1820 #define BGE_MISCCFG_BOARD_ID 0x0001E000
1821 #define BGE_MISCCFG_BOARD_ID_5788 0x00010000
1822 #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000
1823 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000
1824
1825 #define BGE_32BITTIME_66MHZ (0x41 << 1)
1826
1827 /* Misc. Local Control */
1828 #define BGE_MLC_INTR_STATE 0x00000001
1829 #define BGE_MLC_INTR_CLR 0x00000002
1830 #define BGE_MLC_INTR_SET 0x00000004
1831 #define BGE_MLC_INTR_ONATTN 0x00000008
1832 #define BGE_MLC_MISCIO_IN0 0x00000100
1833 #define BGE_MLC_MISCIO_IN1 0x00000200
1834 #define BGE_MLC_MISCIO_IN2 0x00000400
1835 #define BGE_MLC_MISCIO_OUTEN0 0x00000800
1836 #define BGE_MLC_MISCIO_OUTEN1 0x00001000
1837 #define BGE_MLC_MISCIO_OUTEN2 0x00002000
1838 #define BGE_MLC_MISCIO_OUT0 0x00004000
1839 #define BGE_MLC_MISCIO_OUT1 0x00008000
1840 #define BGE_MLC_MISCIO_OUT2 0x00010000
1841 #define BGE_MLC_EXTRAM_ENB 0x00020000
1842 #define BGE_MLC_SRAM_SIZE 0x001C0000
1843 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */
1844 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */
1845 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000
1846 #define BGE_MLC_AUTO_EEPROM 0x01000000
1847
1848 #define BGE_SSRAMSIZE_256KB 0x00000000
1849 #define BGE_SSRAMSIZE_512KB 0x00040000
1850 #define BGE_SSRAMSIZE_1MB 0x00080000
1851 #define BGE_SSRAMSIZE_2MB 0x000C0000
1852 #define BGE_SSRAMSIZE_4MB 0x00100000
1853 #define BGE_SSRAMSIZE_8MB 0x00140000
1854 #define BGE_SSRAMSIZE_16M 0x00180000
1855
1856 /* EEPROM address register */
1857 #define BGE_EEADDR_ADDRESS 0x0000FFFC
1858 #define BGE_EEADDR_HALFCLK 0x01FF0000
1859 #define BGE_EEADDR_START 0x02000000
1860 #define BGE_EEADDR_DEVID 0x1C000000
1861 #define BGE_EEADDR_RESET 0x20000000
1862 #define BGE_EEADDR_DONE 0x40000000
1863 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */
1864
1865 #define BGE_EEDEVID(x) ((x & 7) << 26)
1866 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16)
1867 #define BGE_HALFCLK_384SCL 0x60
1868 #define BGE_EE_READCMD \
1869 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1870 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
1871 #define BGE_EE_WRCMD \
1872 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1873 BGE_EEADDR_START|BGE_EEADDR_DONE)
1874
1875 /* EEPROM Control register */
1876 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001
1877 #define BGE_EECTL_CLKOUT 0x00000002
1878 #define BGE_EECTL_CLKIN 0x00000004
1879 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008
1880 #define BGE_EECTL_DATAOUT 0x00000010
1881 #define BGE_EECTL_DATAIN 0x00000020
1882
1883 /* MDI (MII/GMII) access register */
1884 #define BGE_MDI_DATA 0x00000001
1885 #define BGE_MDI_DIR 0x00000002
1886 #define BGE_MDI_SEL 0x00000004
1887 #define BGE_MDI_CLK 0x00000008
1888
1889 #define BGE_MEMWIN_START 0x00008000
1890 #define BGE_MEMWIN_END 0x0000FFFF
1891
1892
1893 #define BGE_MEMWIN_READ(sc, x, val) \
1894 do { \
1895 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1896 (0xFFFF0000 & x), 4); \
1897 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
1898 } while(0)
1899
1900 #define BGE_MEMWIN_WRITE(sc, x, val) \
1901 do { \
1902 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1903 (0xFFFF0000 & x), 4); \
1904 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
1905 } while(0)
1906
1907 /*
1908 * This magic number is written to the firmware mailbox at 0xb50
1909 * before a software reset is issued. After the internal firmware
1910 * has completed its initialization it will write the opposite of
1911 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the
1912 * driver to synchronize with the firmware.
1913 */
1914 #define BGE_MAGIC_NUMBER 0x4B657654
1915
1916 typedef struct {
1917 uint32_t bge_addr_hi;
1918 uint32_t bge_addr_lo;
1919 } bge_hostaddr;
1920
1921 #define BGE_HOSTADDR(x, y) \
1922 do { \
1923 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \
1924 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \
1925 } while(0)
1926
1927 #define BGE_ADDR_LO(y) \
1928 ((uint64_t) (y) & 0xFFFFFFFF)
1929 #define BGE_ADDR_HI(y) \
1930 ((uint64_t) (y) >> 32)
1931
1932 /* Ring control block structure */
1933 struct bge_rcb {
1934 bge_hostaddr bge_hostaddr;
1935 uint32_t bge_maxlen_flags;
1936 uint32_t bge_nicaddr;
1937 };
1938
1939 #define RCB_WRITE_4(sc, rcb, offset, val) \
1940 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val)
1941 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags))
1942
1943 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001
1944 #define BGE_RCB_FLAG_RING_DISABLED 0x0002
1945
1946 struct bge_tx_bd {
1947 bge_hostaddr bge_addr;
1948 #if BYTE_ORDER == LITTLE_ENDIAN
1949 uint16_t bge_flags;
1950 uint16_t bge_len;
1951 uint16_t bge_vlan_tag;
1952 uint16_t bge_rsvd;
1953 #else
1954 uint16_t bge_len;
1955 uint16_t bge_flags;
1956 uint16_t bge_rsvd;
1957 uint16_t bge_vlan_tag;
1958 #endif
1959 };
1960
1961 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001
1962 #define BGE_TXBDFLAG_IP_CSUM 0x0002
1963 #define BGE_TXBDFLAG_END 0x0004
1964 #define BGE_TXBDFLAG_IP_FRAG 0x0008
1965 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010
1966 #define BGE_TXBDFLAG_VLAN_TAG 0x0040
1967 #define BGE_TXBDFLAG_COAL_NOW 0x0080
1968 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100
1969 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200
1970 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000
1971 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000
1972 #define BGE_TXBDFLAG_NO_CRC 0x8000
1973
1974 #define BGE_NIC_TXRING_ADDR(ringno, size) \
1975 BGE_SEND_RING_1_TO_4 + \
1976 ((ringno * sizeof(struct bge_tx_bd) * size) / 4)
1977
1978 struct bge_rx_bd {
1979 bge_hostaddr bge_addr;
1980 #if BYTE_ORDER == LITTLE_ENDIAN
1981 uint16_t bge_len;
1982 uint16_t bge_idx;
1983 uint16_t bge_flags;
1984 uint16_t bge_type;
1985 uint16_t bge_tcp_udp_csum;
1986 uint16_t bge_ip_csum;
1987 uint16_t bge_vlan_tag;
1988 uint16_t bge_error_flag;
1989 #else
1990 uint16_t bge_idx;
1991 uint16_t bge_len;
1992 uint16_t bge_type;
1993 uint16_t bge_flags;
1994 uint16_t bge_ip_csum;
1995 uint16_t bge_tcp_udp_csum;
1996 uint16_t bge_error_flag;
1997 uint16_t bge_vlan_tag;
1998 #endif
1999 uint32_t bge_rsvd;
2000 uint32_t bge_opaque;
2001 };
2002
2003 struct bge_extrx_bd {
2004 bge_hostaddr bge_addr1;
2005 bge_hostaddr bge_addr2;
2006 bge_hostaddr bge_addr3;
2007 #if BYTE_ORDER == LITTLE_ENDIAN
2008 uint16_t bge_len2;
2009 uint16_t bge_len1;
2010 uint16_t bge_rsvd1;
2011 uint16_t bge_len3;
2012 #else
2013 uint16_t bge_len1;
2014 uint16_t bge_len2;
2015 uint16_t bge_len3;
2016 uint16_t bge_rsvd1;
2017 #endif
2018 bge_hostaddr bge_addr0;
2019 #if BYTE_ORDER == LITTLE_ENDIAN
2020 uint16_t bge_len0;
2021 uint16_t bge_idx;
2022 uint16_t bge_flags;
2023 uint16_t bge_type;
2024 uint16_t bge_tcp_udp_csum;
2025 uint16_t bge_ip_csum;
2026 uint16_t bge_vlan_tag;
2027 uint16_t bge_error_flag;
2028 #else
2029 uint16_t bge_idx;
2030 uint16_t bge_len0;
2031 uint16_t bge_type;
2032 uint16_t bge_flags;
2033 uint16_t bge_ip_csum;
2034 uint16_t bge_tcp_udp_csum;
2035 uint16_t bge_error_flag;
2036 uint16_t bge_vlan_tag;
2037 #endif
2038 uint32_t bge_rsvd0;
2039 uint32_t bge_opaque;
2040 };
2041
2042 #define BGE_RXBDFLAG_END 0x0004
2043 #define BGE_RXBDFLAG_JUMBO_RING 0x0020
2044 #define BGE_RXBDFLAG_VLAN_TAG 0x0040
2045 #define BGE_RXBDFLAG_ERROR 0x0400
2046 #define BGE_RXBDFLAG_MINI_RING 0x0800
2047 #define BGE_RXBDFLAG_IP_CSUM 0x1000
2048 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
2049 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
2050
2051 #define BGE_RXERRFLAG_BAD_CRC 0x0001
2052 #define BGE_RXERRFLAG_COLL_DETECT 0x0002
2053 #define BGE_RXERRFLAG_LINK_LOST 0x0004
2054 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008
2055 #define BGE_RXERRFLAG_MAC_ABORT 0x0010
2056 #define BGE_RXERRFLAG_RUNT 0x0020
2057 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
2058 #define BGE_RXERRFLAG_GIANT 0x0080
2059
2060 struct bge_sts_idx {
2061 #if BYTE_ORDER == LITTLE_ENDIAN
2062 uint16_t bge_rx_prod_idx;
2063 uint16_t bge_tx_cons_idx;
2064 #else
2065 uint16_t bge_tx_cons_idx;
2066 uint16_t bge_rx_prod_idx;
2067 #endif
2068 };
2069
2070 struct bge_status_block {
2071 uint32_t bge_status;
2072 uint32_t bge_rsvd0;
2073 #if BYTE_ORDER == LITTLE_ENDIAN
2074 uint16_t bge_rx_jumbo_cons_idx;
2075 uint16_t bge_rx_std_cons_idx;
2076 uint16_t bge_rx_mini_cons_idx;
2077 uint16_t bge_rsvd1;
2078 #else
2079 uint16_t bge_rx_std_cons_idx;
2080 uint16_t bge_rx_jumbo_cons_idx;
2081 uint16_t bge_rsvd1;
2082 uint16_t bge_rx_mini_cons_idx;
2083 #endif
2084 struct bge_sts_idx bge_idx[16];
2085 };
2086
2087 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx
2088 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx
2089
2090 #define BGE_STATFLAG_UPDATED 0x00000001
2091 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
2092 #define BGE_STATFLAG_ERROR 0x00000004
2093
2094
2095 /*
2096 * Broadcom Vendor ID
2097 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID
2098 * even though they're now manufactured by Broadcom)
2099 */
2100 #define BCOM_VENDORID 0x14E4
2101 #define BCOM_DEVICEID_BCM5700 0x1644
2102 #define BCOM_DEVICEID_BCM5701 0x1645
2103 #define BCOM_DEVICEID_BCM5702 0x1646
2104 #define BCOM_DEVICEID_BCM5702X 0x16A6
2105 #define BCOM_DEVICEID_BCM5702_ALT 0x16C6
2106 #define BCOM_DEVICEID_BCM5703 0x1647
2107 #define BCOM_DEVICEID_BCM5703X 0x16A7
2108 #define BCOM_DEVICEID_BCM5703_ALT 0x16C7
2109 #define BCOM_DEVICEID_BCM5704C 0x1648
2110 #define BCOM_DEVICEID_BCM5704S 0x16A8
2111 #define BCOM_DEVICEID_BCM5704S_ALT 0x1649
2112 #define BCOM_DEVICEID_BCM5705 0x1653
2113 #define BCOM_DEVICEID_BCM5705K 0x1654
2114 #define BCOM_DEVICEID_BCM5705F 0x166E
2115 #define BCOM_DEVICEID_BCM5705M 0x165D
2116 #define BCOM_DEVICEID_BCM5705M_ALT 0x165E
2117 #define BCOM_DEVICEID_BCM5714C 0x1668
2118 #define BCOM_DEVICEID_BCM5714S 0x1669
2119 #define BCOM_DEVICEID_BCM5715 0x1678
2120 #define BCOM_DEVICEID_BCM5715S 0x1679
2121 #define BCOM_DEVICEID_BCM5720 0x1658
2122 #define BCOM_DEVICEID_BCM5721 0x1659
2123 #define BCOM_DEVICEID_BCM5722 0x165A
2124 #define BCOM_DEVICEID_BCM5723 0x165B
2125 #define BCOM_DEVICEID_BCM5750 0x1676
2126 #define BCOM_DEVICEID_BCM5750M 0x167C
2127 #define BCOM_DEVICEID_BCM5751 0x1677
2128 #define BCOM_DEVICEID_BCM5751F 0x167E
2129 #define BCOM_DEVICEID_BCM5751M 0x167D
2130 #define BCOM_DEVICEID_BCM5752 0x1600
2131 #define BCOM_DEVICEID_BCM5752M 0x1601
2132 #define BCOM_DEVICEID_BCM5753 0x16F7
2133 #define BCOM_DEVICEID_BCM5753F 0x16FE
2134 #define BCOM_DEVICEID_BCM5753M 0x16FD
2135 #define BCOM_DEVICEID_BCM5754 0x167A
2136 #define BCOM_DEVICEID_BCM5754M 0x1672
2137 #define BCOM_DEVICEID_BCM5755 0x167B
2138 #define BCOM_DEVICEID_BCM5755M 0x1673
2139 #define BCOM_DEVICEID_BCM5761 0x1681
2140 #define BCOM_DEVICEID_BCM5761E 0x1680
2141 #define BCOM_DEVICEID_BCM5761S 0x1688
2142 #define BCOM_DEVICEID_BCM5761SE 0x1689
2143 #define BCOM_DEVICEID_BCM5764 0x1684
2144 #define BCOM_DEVICEID_BCM5780 0x166A
2145 #define BCOM_DEVICEID_BCM5780S 0x166B
2146 #define BCOM_DEVICEID_BCM5781 0x16DD
2147 #define BCOM_DEVICEID_BCM5782 0x1696
2148 #define BCOM_DEVICEID_BCM5784 0x1698
2149 #define BCOM_DEVICEID_BCM5785F 0x16a0
2150 #define BCOM_DEVICEID_BCM5785G 0x1699
2151 #define BCOM_DEVICEID_BCM5786 0x169A
2152 #define BCOM_DEVICEID_BCM5787 0x169B
2153 #define BCOM_DEVICEID_BCM5787M 0x1693
2154 #define BCOM_DEVICEID_BCM5787F 0x167f
2155 #define BCOM_DEVICEID_BCM5788 0x169C
2156 #define BCOM_DEVICEID_BCM5789 0x169D
2157 #define BCOM_DEVICEID_BCM5901 0x170D
2158 #define BCOM_DEVICEID_BCM5901A2 0x170E
2159 #define BCOM_DEVICEID_BCM5903M 0x16FF
2160 #define BCOM_DEVICEID_BCM5906 0x1712
2161 #define BCOM_DEVICEID_BCM5906M 0x1713
2162 #define BCOM_DEVICEID_BCM57760 0x1690
2163 #define BCOM_DEVICEID_BCM57780 0x1692
2164 #define BCOM_DEVICEID_BCM57788 0x1691
2165 #define BCOM_DEVICEID_BCM57790 0x1694
2166
2167 /*
2168 * Alteon AceNIC PCI vendor/device ID.
2169 */
2170 #define ALTEON_VENDORID 0x12AE
2171 #define ALTEON_DEVICEID_ACENIC 0x0001
2172 #define ALTEON_DEVICEID_ACENIC_COPPER 0x0002
2173 #define ALTEON_DEVICEID_BCM5700 0x0003
2174 #define ALTEON_DEVICEID_BCM5701 0x0004
2175
2176 /*
2177 * 3Com 3c996 PCI vendor/device ID.
2178 */
2179 #define TC_VENDORID 0x10B7
2180 #define TC_DEVICEID_3C996 0x0003
2181
2182 /*
2183 * SysKonnect PCI vendor ID
2184 */
2185 #define SK_VENDORID 0x1148
2186 #define SK_DEVICEID_ALTIMA 0x4400
2187 #define SK_SUBSYSID_9D21 0x4421
2188 #define SK_SUBSYSID_9D41 0x4441
2189
2190 /*
2191 * Altima PCI vendor/device ID.
2192 */
2193 #define ALTIMA_VENDORID 0x173b
2194 #define ALTIMA_DEVICE_AC1000 0x03e8
2195 #define ALTIMA_DEVICE_AC1002 0x03e9
2196 #define ALTIMA_DEVICE_AC9100 0x03ea
2197
2198 /*
2199 * Dell PCI vendor ID
2200 */
2201
2202 #define DELL_VENDORID 0x1028
2203
2204 /*
2205 * Apple PCI vendor ID.
2206 */
2207 #define APPLE_VENDORID 0x106b
2208 #define APPLE_DEVICE_BCM5701 0x1645
2209
2210 /*
2211 * Sun PCI vendor ID
2212 */
2213 #define SUN_VENDORID 0x108e
2214
2215 /*
2216 * Fujitsu vendor/device IDs
2217 */
2218 #define FJTSU_VENDORID 0x10cf
2219 #define FJTSU_DEVICEID_PW008GE5 0x11a1
2220 #define FJTSU_DEVICEID_PW008GE4 0x11a2
2221 #define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */
2222
2223 /*
2224 * Offset of MAC address inside EEPROM.
2225 */
2226 #define BGE_EE_MAC_OFFSET 0x7C
2227 #define BGE_EE_MAC_OFFSET_5906 0x10
2228 #define BGE_EE_HWCFG_OFFSET 0xC8
2229
2230 #define BGE_HWCFG_VOLTAGE 0x00000003
2231 #define BGE_HWCFG_PHYLED_MODE 0x0000000C
2232 #define BGE_HWCFG_MEDIA 0x00000030
2233 #define BGE_HWCFG_ASF 0x00000080
2234
2235 #define BGE_VOLTAGE_1POINT3 0x00000000
2236 #define BGE_VOLTAGE_1POINT8 0x00000001
2237
2238 #define BGE_PHYLEDMODE_UNSPEC 0x00000000
2239 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004
2240 #define BGE_PHYLEDMODE_SINGLELED 0x00000008
2241
2242 #define BGE_MEDIA_UNSPEC 0x00000000
2243 #define BGE_MEDIA_COPPER 0x00000010
2244 #define BGE_MEDIA_FIBER 0x00000020
2245
2246 #define BGE_TICKS_PER_SEC 1000000
2247
2248 /*
2249 * Ring size constants.
2250 */
2251 #define BGE_EVENT_RING_CNT 256
2252 #define BGE_CMD_RING_CNT 64
2253 #define BGE_STD_RX_RING_CNT 512
2254 #define BGE_JUMBO_RX_RING_CNT 256
2255 #define BGE_MINI_RX_RING_CNT 1024
2256 #define BGE_RETURN_RING_CNT 1024
2257
2258 /* 5705 has smaller return ring size */
2259
2260 #define BGE_RETURN_RING_CNT_5705 512
2261
2262 /*
2263 * Possible TX ring sizes.
2264 */
2265 #define BGE_TX_RING_CNT_128 128
2266 #define BGE_TX_RING_BASE_128 0x3800
2267
2268 #define BGE_TX_RING_CNT_256 256
2269 #define BGE_TX_RING_BASE_256 0x3000
2270
2271 #define BGE_TX_RING_CNT_512 512
2272 #define BGE_TX_RING_BASE_512 0x2000
2273
2274 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512
2275 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512
2276
2277 /*
2278 * Tigon III statistics counters.
2279 */
2280 /* Statistics maintained MAC Receive block. */
2281 struct bge_rx_mac_stats {
2282 bge_hostaddr ifHCInOctets;
2283 bge_hostaddr Reserved1;
2284 bge_hostaddr etherStatsFragments;
2285 bge_hostaddr ifHCInUcastPkts;
2286 bge_hostaddr ifHCInMulticastPkts;
2287 bge_hostaddr ifHCInBroadcastPkts;
2288 bge_hostaddr dot3StatsFCSErrors;
2289 bge_hostaddr dot3StatsAlignmentErrors;
2290 bge_hostaddr xonPauseFramesReceived;
2291 bge_hostaddr xoffPauseFramesReceived;
2292 bge_hostaddr macControlFramesReceived;
2293 bge_hostaddr xoffStateEntered;
2294 bge_hostaddr dot3StatsFramesTooLong;
2295 bge_hostaddr etherStatsJabbers;
2296 bge_hostaddr etherStatsUndersizePkts;
2297 bge_hostaddr inRangeLengthError;
2298 bge_hostaddr outRangeLengthError;
2299 bge_hostaddr etherStatsPkts64Octets;
2300 bge_hostaddr etherStatsPkts65Octetsto127Octets;
2301 bge_hostaddr etherStatsPkts128Octetsto255Octets;
2302 bge_hostaddr etherStatsPkts256Octetsto511Octets;
2303 bge_hostaddr etherStatsPkts512Octetsto1023Octets;
2304 bge_hostaddr etherStatsPkts1024Octetsto1522Octets;
2305 bge_hostaddr etherStatsPkts1523Octetsto2047Octets;
2306 bge_hostaddr etherStatsPkts2048Octetsto4095Octets;
2307 bge_hostaddr etherStatsPkts4096Octetsto8191Octets;
2308 bge_hostaddr etherStatsPkts8192Octetsto9022Octets;
2309 };
2310
2311
2312 /* Statistics maintained MAC Transmit block. */
2313 struct bge_tx_mac_stats {
2314 bge_hostaddr ifHCOutOctets;
2315 bge_hostaddr Reserved2;
2316 bge_hostaddr etherStatsCollisions;
2317 bge_hostaddr outXonSent;
2318 bge_hostaddr outXoffSent;
2319 bge_hostaddr flowControlDone;
2320 bge_hostaddr dot3StatsInternalMacTransmitErrors;
2321 bge_hostaddr dot3StatsSingleCollisionFrames;
2322 bge_hostaddr dot3StatsMultipleCollisionFrames;
2323 bge_hostaddr dot3StatsDeferredTransmissions;
2324 bge_hostaddr Reserved3;
2325 bge_hostaddr dot3StatsExcessiveCollisions;
2326 bge_hostaddr dot3StatsLateCollisions;
2327 bge_hostaddr dot3Collided2Times;
2328 bge_hostaddr dot3Collided3Times;
2329 bge_hostaddr dot3Collided4Times;
2330 bge_hostaddr dot3Collided5Times;
2331 bge_hostaddr dot3Collided6Times;
2332 bge_hostaddr dot3Collided7Times;
2333 bge_hostaddr dot3Collided8Times;
2334 bge_hostaddr dot3Collided9Times;
2335 bge_hostaddr dot3Collided10Times;
2336 bge_hostaddr dot3Collided11Times;
2337 bge_hostaddr dot3Collided12Times;
2338 bge_hostaddr dot3Collided13Times;
2339 bge_hostaddr dot3Collided14Times;
2340 bge_hostaddr dot3Collided15Times;
2341 bge_hostaddr ifHCOutUcastPkts;
2342 bge_hostaddr ifHCOutMulticastPkts;
2343 bge_hostaddr ifHCOutBroadcastPkts;
2344 bge_hostaddr dot3StatsCarrierSenseErrors;
2345 bge_hostaddr ifOutDiscards;
2346 bge_hostaddr ifOutErrors;
2347 };
2348
2349 /* Stats counters access through registers */
2350 struct bge_mac_stats_regs {
2351 uint32_t ifHCOutOctets;
2352 uint32_t Reserved0;
2353 uint32_t etherStatsCollisions;
2354 uint32_t outXonSent;
2355 uint32_t outXoffSent;
2356 uint32_t Reserved1;
2357 uint32_t dot3StatsInternalMacTransmitErrors;
2358 uint32_t dot3StatsSingleCollisionFrames;
2359 uint32_t dot3StatsMultipleCollisionFrames;
2360 uint32_t dot3StatsDeferredTransmissions;
2361 uint32_t Reserved2;
2362 uint32_t dot3StatsExcessiveCollisions;
2363 uint32_t dot3StatsLateCollisions;
2364 uint32_t Reserved3[14];
2365 uint32_t ifHCOutUcastPkts;
2366 uint32_t ifHCOutMulticastPkts;
2367 uint32_t ifHCOutBroadcastPkts;
2368 uint32_t Reserved4[2];
2369 uint32_t ifHCInOctets;
2370 uint32_t Reserved5;
2371 uint32_t etherStatsFragments;
2372 uint32_t ifHCInUcastPkts;
2373 uint32_t ifHCInMulticastPkts;
2374 uint32_t ifHCInBroadcastPkts;
2375 uint32_t dot3StatsFCSErrors;
2376 uint32_t dot3StatsAlignmentErrors;
2377 uint32_t xonPauseFramesReceived;
2378 uint32_t xoffPauseFramesReceived;
2379 uint32_t macControlFramesReceived;
2380 uint32_t xoffStateEntered;
2381 uint32_t dot3StatsFramesTooLong;
2382 uint32_t etherStatsJabbers;
2383 uint32_t etherStatsUndersizePkts;
2384 };
2385
2386 struct bge_stats {
2387 uint8_t Reserved0[256];
2388
2389 /* Statistics maintained by Receive MAC. */
2390 struct bge_rx_mac_stats rxstats;
2391
2392 bge_hostaddr Unused1[37];
2393
2394 /* Statistics maintained by Transmit MAC. */
2395 struct bge_tx_mac_stats txstats;
2396
2397 bge_hostaddr Unused2[31];
2398
2399 /* Statistics maintained by Receive List Placement. */
2400 bge_hostaddr COSIfHCInPkts[16];
2401 bge_hostaddr COSFramesDroppedDueToFilters;
2402 bge_hostaddr nicDmaWriteQueueFull;
2403 bge_hostaddr nicDmaWriteHighPriQueueFull;
2404 bge_hostaddr nicNoMoreRxBDs;
2405 bge_hostaddr ifInDiscards;
2406 bge_hostaddr ifInErrors;
2407 bge_hostaddr nicRecvThresholdHit;
2408
2409 bge_hostaddr Unused3[9];
2410
2411 /* Statistics maintained by Send Data Initiator. */
2412 bge_hostaddr COSIfHCOutPkts[16];
2413 bge_hostaddr nicDmaReadQueueFull;
2414 bge_hostaddr nicDmaReadHighPriQueueFull;
2415 bge_hostaddr nicSendDataCompQueueFull;
2416
2417 /* Statistics maintained by Host Coalescing. */
2418 bge_hostaddr nicRingSetSendProdIndex;
2419 bge_hostaddr nicRingStatusUpdate;
2420 bge_hostaddr nicInterrupts;
2421 bge_hostaddr nicAvoidedInterrupts;
2422 bge_hostaddr nicSendThresholdHit;
2423
2424 uint8_t Reserved4[320];
2425 };
2426
2427 /*
2428 * Tigon general information block. This resides in host memory
2429 * and contains the status counters, ring control blocks and
2430 * producer pointers.
2431 */
2432
2433 struct bge_gib {
2434 struct bge_stats bge_stats;
2435 struct bge_rcb bge_tx_rcb[16];
2436 struct bge_rcb bge_std_rx_rcb;
2437 struct bge_rcb bge_jumbo_rx_rcb;
2438 struct bge_rcb bge_mini_rx_rcb;
2439 struct bge_rcb bge_return_rcb;
2440 };
2441
2442 #define BGE_FRAMELEN 1518
2443 #define BGE_MAX_FRAMELEN 1536
2444 #define BGE_JUMBO_FRAMELEN 9018
2445 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2446 #define BGE_MIN_FRAMELEN 60
2447
2448 /*
2449 * Other utility macros.
2450 */
2451 #define BGE_INC(x, y) (x) = (x + 1) % y
2452
2453 /*
2454 * Register access macros. The Tigon always uses memory mapped register
2455 * accesses and all registers must be accessed with 32 bit operations.
2456 */
2457
2458 #define CSR_WRITE_4(sc, reg, val) \
2459 bus_write_4(sc->bge_res, reg, val)
2460
2461 #define CSR_READ_4(sc, reg) \
2462 bus_read_4(sc->bge_res, reg)
2463
2464 #define BGE_SETBIT(sc, reg, x) \
2465 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
2466 #define BGE_CLRBIT(sc, reg, x) \
2467 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
2468
2469 #define PCI_SETBIT(dev, reg, x, s) \
2470 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
2471 #define PCI_CLRBIT(dev, reg, x, s) \
2472 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
2473
2474 /*
2475 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
2476 * values are tuneable. They control the actual amount of buffers
2477 * allocated for the standard, mini and jumbo receive rings.
2478 */
2479
2480 #define BGE_SSLOTS 256
2481 #define BGE_MSLOTS 256
2482 #define BGE_JSLOTS 384
2483
2484 #define BGE_NSEG_JUMBO 4
2485 #define BGE_NSEG_NEW 32
2486
2487 /*
2488 * Ring structures. Most of these reside in host memory and we tell
2489 * the NIC where they are via the ring control blocks. The exceptions
2490 * are the tx and command rings, which live in NIC memory and which
2491 * we access via the shared memory window.
2492 */
2493
2494 struct bge_ring_data {
2495 struct bge_rx_bd *bge_rx_std_ring;
2496 bus_addr_t bge_rx_std_ring_paddr;
2497 struct bge_extrx_bd *bge_rx_jumbo_ring;
2498 bus_addr_t bge_rx_jumbo_ring_paddr;
2499 struct bge_rx_bd *bge_rx_return_ring;
2500 bus_addr_t bge_rx_return_ring_paddr;
2501 struct bge_tx_bd *bge_tx_ring;
2502 bus_addr_t bge_tx_ring_paddr;
2503 struct bge_status_block *bge_status_block;
2504 bus_addr_t bge_status_block_paddr;
2505 struct bge_stats *bge_stats;
2506 bus_addr_t bge_stats_paddr;
2507 struct bge_gib bge_info;
2508 };
2509
2510 #define BGE_STD_RX_RING_SZ \
2511 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
2512 #define BGE_JUMBO_RX_RING_SZ \
2513 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT)
2514 #define BGE_TX_RING_SZ \
2515 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
2516 #define BGE_RX_RTN_RING_SZ(x) \
2517 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
2518
2519 #define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block)
2520
2521 #define BGE_STATS_SZ sizeof (struct bge_stats)
2522
2523 /*
2524 * Mbuf pointers. We need these to keep track of the virtual addresses
2525 * of our mbuf chains since we can only convert from physical to virtual,
2526 * not the other way around.
2527 */
2528 struct bge_chain_data {
2529 bus_dma_tag_t bge_parent_tag;
2530 bus_dma_tag_t bge_rx_std_ring_tag;
2531 bus_dma_tag_t bge_rx_jumbo_ring_tag;
2532 bus_dma_tag_t bge_rx_return_ring_tag;
2533 bus_dma_tag_t bge_tx_ring_tag;
2534 bus_dma_tag_t bge_status_tag;
2535 bus_dma_tag_t bge_stats_tag;
2536 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */
2537 bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */
2538 bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */
2539 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT];
2540 bus_dmamap_t bge_rx_std_sparemap;
2541 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
2542 bus_dmamap_t bge_rx_jumbo_sparemap;
2543 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT];
2544 bus_dmamap_t bge_rx_std_ring_map;
2545 bus_dmamap_t bge_rx_jumbo_ring_map;
2546 bus_dmamap_t bge_tx_ring_map;
2547 bus_dmamap_t bge_rx_return_ring_map;
2548 bus_dmamap_t bge_status_map;
2549 bus_dmamap_t bge_stats_map;
2550 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT];
2551 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT];
2552 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
2553 };
2554
2555 struct bge_dmamap_arg {
2556 struct bge_softc *sc;
2557 bus_addr_t bge_busaddr;
2558 uint16_t bge_flags;
2559 int bge_idx;
2560 int bge_maxsegs;
2561 struct bge_tx_bd *bge_ring;
2562 };
2563
2564 #define BGE_HWREV_TIGON 0x01
2565 #define BGE_HWREV_TIGON_II 0x02
2566 #define BGE_TIMEOUT 100000
2567 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
2568
2569 struct bge_bcom_hack {
2570 int reg;
2571 int val;
2572 };
2573
2574 #define ASF_ENABLE 1
2575 #define ASF_NEW_HANDSHAKE 2
2576 #define ASF_STACKUP 4
2577
2578 struct bge_softc {
2579 struct ifnet *bge_ifp; /* interface info */
2580 device_t bge_dev;
2581 struct mtx bge_mtx;
2582 device_t bge_miibus;
2583 void *bge_intrhand;
2584 struct resource *bge_irq;
2585 struct resource *bge_res;
2586 struct ifmedia bge_ifmedia; /* TBI media info */
2587 uint32_t bge_flags;
2588 #define BGE_FLAG_TBI 0x00000001
2589 #define BGE_FLAG_JUMBO 0x00000002
2590 #define BGE_FLAG_WIRESPEED 0x00000004
2591 #define BGE_FLAG_EADDR 0x00000008
2592 #define BGE_FLAG_MSI 0x00000100
2593 #define BGE_FLAG_PCIX 0x00000200
2594 #define BGE_FLAG_PCIE 0x00000400
2595 #define BGE_FLAG_5700_FAMILY 0x00001000
2596 #define BGE_FLAG_5705_PLUS 0x00002000
2597 #define BGE_FLAG_5714_FAMILY 0x00004000
2598 #define BGE_FLAG_575X_PLUS 0x00008000
2599 #define BGE_FLAG_5755_PLUS 0x00010000
2600 #define BGE_FLAG_RX_ALIGNBUG 0x00100000
2601 #define BGE_FLAG_NO_3LED 0x00200000
2602 #define BGE_FLAG_ADC_BUG 0x00400000
2603 #define BGE_FLAG_5704_A0_BUG 0x00800000
2604 #define BGE_FLAG_JITTER_BUG 0x01000000
2605 #define BGE_FLAG_BER_BUG 0x02000000
2606 #define BGE_FLAG_ADJUST_TRIM 0x04000000
2607 #define BGE_FLAG_CRC_BUG 0x08000000
2608 #define BGE_FLAG_5788 0x20000000
2609 uint32_t bge_chipid;
2610 uint32_t bge_asicrev;
2611 uint32_t bge_chiprev;
2612 uint8_t bge_asf_mode;
2613 uint8_t bge_asf_count;
2614 struct bge_ring_data bge_ldata; /* rings */
2615 struct bge_chain_data bge_cdata; /* mbufs */
2616 uint16_t bge_tx_saved_considx;
2617 uint16_t bge_rx_saved_considx;
2618 uint16_t bge_ev_saved_considx;
2619 uint16_t bge_return_ring_cnt;
2620 uint16_t bge_std; /* current std ring head */
2621 uint16_t bge_jumbo; /* current jumo ring head */
2622 uint32_t bge_stat_ticks;
2623 uint32_t bge_rx_coal_ticks;
2624 uint32_t bge_tx_coal_ticks;
2625 uint32_t bge_tx_prodidx;
2626 uint32_t bge_rx_max_coal_bds;
2627 uint32_t bge_tx_max_coal_bds;
2628 uint32_t bge_tx_buf_ratio;
2629 int bge_if_flags;
2630 int bge_txcnt;
2631 int bge_link; /* link state */
2632 int bge_link_evt; /* pending link event */
2633 int bge_timer;
2634 struct callout bge_stat_ch;
2635 uint32_t bge_rx_discards;
2636 uint32_t bge_tx_discards;
2637 uint32_t bge_tx_collisions;
2638 #ifdef DEVICE_POLLING
2639 int rxcycles;
2640 #endif /* DEVICE_POLLING */
2641 };
2642
2643 #define BGE_LOCK_INIT(_sc, _name) \
2644 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
2645 #define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx)
2646 #define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED)
2647 #define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx)
2648 #define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)
Cache object: f6421ac840328c725480c4abc80f0c7e
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