1 /*-
2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 #include <sys/param.h>
34
35 #include <dev/bhnd/bhnd_ids.h>
36 #include <dev/bhnd/bhndreg.h>
37 #include <dev/bhnd/bhnd.h>
38
39 #include "bhndb_hwdata.h"
40
41 /*
42 * Resource priority specifications shared by all bhndb(4) bridge
43 * implementations.
44 */
45
46 /*
47 * Define a bhndb_port_priority table.
48 */
49 #define BHNDB_PORTS(...) \
50 .ports = _BHNDB_PORT_ARRAY(__VA_ARGS__), \
51 .num_ports = nitems(_BHNDB_PORT_ARRAY(__VA_ARGS__))
52
53 #define _BHNDB_PORT_ARRAY(...) (const struct bhndb_port_priority[]) { \
54 __VA_ARGS__ \
55 }
56
57 /*
58 * Define a core priority record for all cores matching @p devclass
59 */
60 #define BHNDB_CLASS_PRIO(_devclass, _priority, ...) { \
61 .match = { \
62 BHND_MATCH_CORE_CLASS(BHND_DEVCLASS_ ## _devclass), \
63 }, \
64 .priority = (BHNDB_PRIORITY_ ## _priority), \
65 BHNDB_PORTS(__VA_ARGS__) \
66 }
67
68 /*
69 * Define a default core priority record
70 */
71 #define BHNDB_DEFAULT_PRIO(...) { \
72 .match = { \
73 BHND_MATCH_ANY , \
74 }, \
75 .priority = (BHNDB_PRIORITY_DEFAULT), \
76 BHNDB_PORTS(__VA_ARGS__) \
77 }
78
79 /* Define a port priority record for the type/port/region triplet, optionally
80 * specifying port allocation flags as the final argument */
81 #define BHNDB_PORT_PRIO(_type, _port, _region, _priority, ...) \
82 _BHNDB_PORT_PRIO(_type, _port, _region, _priority, ## __VA_ARGS__, 0)
83
84 #define _BHNDB_PORT_PRIO(_type, _port, _region, _priority, _flags, ...) \
85 { \
86 .type = (BHND_PORT_ ## _type), \
87 .port = _port, \
88 .region = _region, \
89 .priority = (BHNDB_PRIORITY_ ## _priority), \
90 .alloc_flags = (_flags) \
91 }
92
93 /* Define a port priority record for the default (_type, 0, 0) type/port/region
94 * triplet. */
95 #define BHNDB_PORT0_PRIO(_type, _priority, ...) \
96 BHNDB_PORT_PRIO(_type, 0, 0, _priority, ## __VA_ARGS__, 0)
97
98 /**
99 * Generic resource priority configuration usable with all currently supported
100 * bcma(4)-based PCI devices.
101 */
102 const struct bhndb_hw_priority bhndb_bcma_priority_table[] = {
103 /*
104 * Ignorable device classes.
105 *
106 * Runtime access to these cores is not required, and no register
107 * windows should be reserved for these device types.
108 */
109 BHNDB_CLASS_PRIO(SOC_ROUTER, NONE),
110 BHNDB_CLASS_PRIO(SOC_BRIDGE, NONE),
111 BHNDB_CLASS_PRIO(EROM, NONE),
112 BHNDB_CLASS_PRIO(OTHER, NONE),
113
114 /*
115 * Low priority device classes.
116 *
117 * These devices do not sit in a performance-critical path and can be
118 * treated as a low allocation priority.
119 */
120 BHNDB_CLASS_PRIO(CC, LOW,
121 /* Device Block */
122 BHNDB_PORT0_PRIO(DEVICE, LOW),
123
124 /* CC agent registers are not accessed via the bridge. */
125 BHNDB_PORT0_PRIO(AGENT, NONE)
126 ),
127
128 BHNDB_CLASS_PRIO(PMU, LOW,
129 /* Device Block */
130 BHNDB_PORT0_PRIO(DEVICE, LOW),
131
132 /* PMU agent registers are not accessed via the bridge. */
133 BHNDB_PORT0_PRIO(AGENT, NONE)
134 ),
135
136 /*
137 * Default Core Behavior
138 *
139 * All other cores are assumed to require efficient runtime access to
140 * the default device port, and if supported by the bus, an agent port.
141 */
142 BHNDB_DEFAULT_PRIO(
143 /* Device Block */
144 BHNDB_PORT0_PRIO(DEVICE, HIGH),
145
146 /* Agent Block */
147 BHNDB_PORT0_PRIO(AGENT, DEFAULT)
148 ),
149
150 BHNDB_HW_PRIORITY_TABLE_END
151 };
152
153 /**
154 * Generic resource priority configuration usable with all currently supported
155 * siba(4)-based PCI devices.
156 */
157 const struct bhndb_hw_priority bhndb_siba_priority_table[] = {
158 /*
159 * Ignorable device classes.
160 *
161 * Runtime access to these cores is not required, and no register
162 * windows should be reserved for these device types.
163 */
164 BHNDB_CLASS_PRIO(SOC_ROUTER, NONE),
165 BHNDB_CLASS_PRIO(SOC_BRIDGE, NONE),
166 BHNDB_CLASS_PRIO(EROM, NONE),
167 BHNDB_CLASS_PRIO(OTHER, NONE),
168
169 /*
170 * Low priority device classes.
171 *
172 * These devices do not sit in a performance-critical path and can be
173 * treated as a low allocation priority.
174 *
175 * Agent ports are marked as 'NONE' on siba(4) devices, as they
176 * will be fully mappable via register windows shared with the
177 * device0.0 port.
178 *
179 * To support early PCI_V0 devices, we enable FULFILL_ON_OVERCOMMIT for
180 * ChipCommon.
181 */
182 BHNDB_CLASS_PRIO(CC, LOW,
183 /* Device Block */
184 BHNDB_PORT_PRIO(DEVICE, 0, 0, LOW,
185 BHNDB_ALLOC_FULFILL_ON_OVERCOMMIT)
186 ),
187
188 BHNDB_CLASS_PRIO(PMU, LOW,
189 /* Device Block */
190 BHNDB_PORT_PRIO(DEVICE, 0, 0, LOW)
191 ),
192
193 /*
194 * Default Core Behavior
195 *
196 * All other cores are assumed to require efficient runtime access to
197 * the device port.
198 */
199 BHNDB_DEFAULT_PRIO(
200 /* Device Block */
201 BHNDB_PORT_PRIO(DEVICE, 0, 0, HIGH)
202 ),
203
204 BHNDB_HW_PRIORITY_TABLE_END
205 };
Cache object: 663bc482ea5942e90910eedb4a685195
|