chipc.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer,
   12  *    without modification.
   13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
   14  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
   15  *    redistribution must be conditioned upon including a substantially
   16  *    similar Disclaimer requirement for further binary redistribution.
   17  *
   18  * NO WARRANTY
   19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   21  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
   22  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
   23  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
   24  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
   27  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   29  * THE POSSIBILITY OF SUCH DAMAGES.
   30  * 
   31  * $FreeBSD$
   32  */
   33 
   34 #ifndef _BHND_CORES_CHIPC_CHIPC_H_
   35 #define _BHND_CORES_CHIPC_CHIPC_H_
   36 
   37 #include <dev/bhnd/bhnd.h>
   38 #include <dev/bhnd/nvram/bhnd_nvram.h>
   39 
   40 #include "bhnd_chipc_if.h"
   41 
   42 /**
   43  * Supported ChipCommon flash types.
   44  */
   45 typedef enum {
   46         CHIPC_FLASH_NONE        = 0,    /**< No flash, or a type unrecognized
   47                                              by the ChipCommon driver */
   48         CHIPC_PFLASH_CFI        = 1,    /**< CFI-compatible parallel flash */
   49         CHIPC_SFLASH_ST         = 2,    /**< ST serial flash */
   50         CHIPC_SFLASH_AT         = 3,    /**< Atmel serial flash */
   51         CHIPC_QSFLASH_ST        = 4,    /**< ST quad-SPI flash */ 
   52         CHIPC_QSFLASH_AT        = 5,    /**< Atmel quad-SPI flash */
   53         CHIPC_NFLASH            = 6,    /**< NAND flash */
   54         CHIPC_NFLASH_4706       = 7     /**< BCM4706 NAND flash */
   55 } chipc_flash;
   56 
   57 /**
   58  * ChipCommon capability flags;
   59  */
   60 struct chipc_caps {
   61         uint8_t         num_uarts;      /**< Number of attached UARTS (1-3) */
   62         bool            mipseb;         /**< MIPS is big-endian */
   63         uint8_t         uart_clock;     /**< UART clock source (see CHIPC_CAP_UCLKSEL_*) */
   64         uint8_t         uart_gpio;      /**< UARTs own GPIO pins 12-15 */
   65 
   66         uint8_t         extbus_type;    /**< ExtBus type (CHIPC_CAP_EXTBUS_*) */
   67 
   68         chipc_flash     flash_type;     /**< flash type */
   69         uint8_t         cfi_width;      /**< CFI bus width, 0 if unknown or CFI
   70                                              not present */
   71 
   72         bhnd_nvram_src  nvram_src;      /**< identified NVRAM source */
   73         bus_size_t      sprom_offset;   /**< Offset to SPROM data within
   74                                              SPROM/OTP, 0 if unknown or not
   75                                              present */
   76         uint8_t         otp_size;       /**< OTP (row?) size, 0 if not present */
   77 
   78         uint8_t         pll_type;       /**< PLL type */
   79         bool            pwr_ctrl;       /**< Power/clock control available */
   80         bool            jtag_master;    /**< JTAG Master present */
   81         bool            boot_rom;       /**< Internal boot ROM is active */
   82         uint8_t         backplane_64;   /**< Backplane supports 64-bit addressing.
   83                                              Note that this does not gaurantee
   84                                              the CPU itself supports 64-bit
   85                                              addressing. */
   86         bool            pmu;            /**< PMU is present. */
   87         bool            eci;            /**< ECI (enhanced coexistence inteface) is present. */
   88         bool            seci;           /**< SECI (serial ECI) is present */
   89         bool            sprom;          /**< SPROM is present */
   90         bool            gsio;           /**< GSIO (SPI/I2C) present */
   91         bool            aob;            /**< AOB (always on bus) present.
   92                                              If set, PMU and GCI registers are
   93                                              not accessible via ChipCommon,
   94                                              and are instead accessible via
   95                                              dedicated cores on the bhnd bus */
   96 };
   97 
   98 #endif /* _BHND_CORES_CHIPC_CHIPC_H_ */

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FreeBSD/Linux Kernel Cross Reference sys/dev/bhnd/cores/chipc/chipc.h

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sys/dev/bhnd/cores/chipc/chipc.h