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sys/dev/bnxt/bnxt.h
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1 /*- 2 * Broadcom NetXtreme-C/E network driver. 3 * 4 * Copyright (c) 2016 Broadcom, All Rights Reserved. 5 * The term Broadcom refers to Broadcom Limited and/or its subsidiaries 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #ifndef _BNXT_H 33 #define _BNXT_H 34 35 #include <sys/param.h> 36 #include <sys/socket.h> 37 #include <sys/sysctl.h> 38 #include <sys/taskqueue.h> 39 #include <sys/bitstring.h> 40 41 #include <machine/bus.h> 42 43 #include <net/ethernet.h> 44 #include <net/if.h> 45 #include <net/if_var.h> 46 #include <net/iflib.h> 47 48 #include "hsi_struct_def.h" 49 50 /* PCI IDs */ 51 #define BROADCOM_VENDOR_ID 0x14E4 52 53 #define BCM57301 0x16c8 54 #define BCM57302 0x16c9 55 #define BCM57304 0x16ca 56 #define BCM57311 0x16ce 57 #define BCM57312 0x16cf 58 #define BCM57314 0x16df 59 #define BCM57402 0x16d0 60 #define BCM57402_NPAR 0x16d4 61 #define BCM57404 0x16d1 62 #define BCM57404_NPAR 0x16e7 63 #define BCM57406 0x16d2 64 #define BCM57406_NPAR 0x16e8 65 #define BCM57407 0x16d5 66 #define BCM57407_NPAR 0x16ea 67 #define BCM57407_SFP 0x16e9 68 #define BCM57412 0x16d6 69 #define BCM57412_NPAR1 0x16de 70 #define BCM57412_NPAR2 0x16eb 71 #define BCM57414 0x16d7 72 #define BCM57414_NPAR1 0x16ec 73 #define BCM57414_NPAR2 0x16ed 74 #define BCM57416 0x16d8 75 #define BCM57416_NPAR1 0x16ee 76 #define BCM57416_NPAR2 0x16ef 77 #define BCM57416_SFP 0x16e3 78 #define BCM57417 0x16d9 79 #define BCM57417_NPAR1 0x16c0 80 #define BCM57417_NPAR2 0x16cc 81 #define BCM57417_SFP 0x16e2 82 #define BCM57454 0x1614 83 #define BCM58700 0x16cd 84 #define BCM57508 0x1750 85 #define BCM57504 0x1751 86 #define BCM57502 0x1752 87 #define NETXTREME_C_VF1 0x16cb 88 #define NETXTREME_C_VF2 0x16e1 89 #define NETXTREME_C_VF3 0x16e5 90 #define NETXTREME_E_VF1 0x16c1 91 #define NETXTREME_E_VF2 0x16d3 92 #define NETXTREME_E_VF3 0x16dc 93 94 /* Maximum numbers of RX and TX descriptors. iflib requires this to be a power 95 * of two. The hardware has no particular limitation. */ 96 #define BNXT_MAX_RXD ((INT32_MAX >> 1) + 1) 97 #define BNXT_MAX_TXD ((INT32_MAX >> 1) + 1) 98 99 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 100 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 101 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 102 103 #define BNXT_MAX_MTU 9000 104 105 #define BNXT_RSS_HASH_TYPE_TCPV4 0 106 #define BNXT_RSS_HASH_TYPE_UDPV4 1 107 #define BNXT_RSS_HASH_TYPE_IPV4 2 108 #define BNXT_RSS_HASH_TYPE_TCPV6 3 109 #define BNXT_RSS_HASH_TYPE_UDPV6 4 110 #define BNXT_RSS_HASH_TYPE_IPV6 5 111 #define BNXT_GET_RSS_PROFILE_ID(rss_hash_type) ((rss_hash_type >> 1) & 0x1F) 112 113 #define BNXT_NO_MORE_WOL_FILTERS 0xFFFF 114 #define bnxt_wol_supported(softc) (!((softc)->flags & BNXT_FLAG_VF) && \ 115 ((softc)->flags & BNXT_FLAG_WOL_CAP )) 116 117 /* 64-bit doorbell */ 118 #define DBR_INDEX_MASK 0x0000000000ffffffULL 119 #define DBR_PI_LO_MASK 0xff000000UL 120 #define DBR_PI_LO_SFT 24 121 #define DBR_XID_MASK 0x000fffff00000000ULL 122 #define DBR_XID_SFT 32 123 #define DBR_PI_HI_MASK 0xf0000000000000ULL 124 #define DBR_PI_HI_SFT 52 125 #define DBR_PATH_L2 (0x1ULL << 56) 126 #define DBR_VALID (0x1ULL << 58) 127 #define DBR_TYPE_SQ (0x0ULL << 60) 128 #define DBR_TYPE_RQ (0x1ULL << 60) 129 #define DBR_TYPE_SRQ (0x2ULL << 60) 130 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60) 131 #define DBR_TYPE_CQ (0x4ULL << 60) 132 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60) 133 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60) 134 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60) 135 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60) 136 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60) 137 #define DBR_TYPE_NQ (0xaULL << 60) 138 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 139 #define DBR_TYPE_PUSH_START (0xcULL << 60) 140 #define DBR_TYPE_PUSH_END (0xdULL << 60) 141 #define DBR_TYPE_NULL (0xfULL << 60) 142 143 #define BNXT_MAX_NUM_QUEUES 32 144 145 /* Completion related defines */ 146 #define CMP_VALID(cmp, v_bit) \ 147 ((!!(((struct cmpl_base *)(cmp))->info3_v & htole32(CMPL_BASE_V))) == !!(v_bit) ) 148 149 /* Chip class phase 5 */ 150 #define BNXT_CHIP_P5(sc) ((softc->flags & BNXT_FLAG_CHIP_P5)) 151 152 #define DB_PF_OFFSET_P5 0x10000 153 #define NQ_VALID(cmp, v_bit) \ 154 ((!!(((nq_cn_t *)(cmp))->v & htole32(NQ_CN_V))) == !!(v_bit) ) 155 156 #ifndef DIV_ROUND_UP 157 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 158 #endif 159 #ifndef roundup 160 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 161 #endif 162 163 #define NEXT_CP_CONS_V(ring, cons, v_bit) do { \ 164 if (__predict_false(++(cons) == (ring)->ring_size)) \ 165 ((cons) = 0, (v_bit) = !v_bit); \ 166 } while (0) 167 168 #define RING_NEXT(ring, idx) (__predict_false(idx + 1 == (ring)->ring_size) ? \ 169 0 : idx + 1) 170 171 #define CMPL_PREFETCH_NEXT(cpr, idx) \ 172 __builtin_prefetch(&((struct cmpl_base *)(cpr)->ring.vaddr)[((idx) +\ 173 (CACHE_LINE_SIZE / sizeof(struct cmpl_base))) & \ 174 ((cpr)->ring.ring_size - 1)]) 175 176 /* Lock macros */ 177 #define BNXT_HWRM_LOCK_INIT(_softc, _name) \ 178 mtx_init(&(_softc)->hwrm_lock, _name, "BNXT HWRM Lock", MTX_DEF) 179 #define BNXT_HWRM_LOCK(_softc) mtx_lock(&(_softc)->hwrm_lock) 180 #define BNXT_HWRM_UNLOCK(_softc) mtx_unlock(&(_softc)->hwrm_lock) 181 #define BNXT_HWRM_LOCK_DESTROY(_softc) mtx_destroy(&(_softc)->hwrm_lock) 182 #define BNXT_HWRM_LOCK_ASSERT(_softc) mtx_assert(&(_softc)->hwrm_lock, \ 183 MA_OWNED) 184 #define BNXT_IS_FLOW_CTRL_CHANGED(link_info) \ 185 ((link_info->last_flow_ctrl.tx != link_info->flow_ctrl.tx) || \ 186 (link_info->last_flow_ctrl.rx != link_info->flow_ctrl.rx) || \ 187 (link_info->last_flow_ctrl.autoneg != link_info->flow_ctrl.autoneg)) 188 189 /* Chip info */ 190 #define BNXT_TSO_SIZE UINT16_MAX 191 192 #define min_t(type, x, y) ({ \ 193 type __min1 = (x); \ 194 type __min2 = (y); \ 195 __min1 < __min2 ? __min1 : __min2; }) 196 197 #define max_t(type, x, y) ({ \ 198 type __max1 = (x); \ 199 type __max2 = (y); \ 200 __max1 > __max2 ? __max1 : __max2; }) 201 202 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 203 204 #define BNXT_IFMEDIA_ADD(supported, fw_speed, ifm_speed) do { \ 205 if ((supported) & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_ ## fw_speed) \ 206 ifmedia_add(softc->media, IFM_ETHER | (ifm_speed), 0, NULL); \ 207 } while(0) 208 209 #define BNXT_MIN_FRAME_SIZE 52 /* Frames must be padded to this size for some A0 chips */ 210 211 extern char bnxt_driver_version[]; 212 typedef void (*bnxt_doorbell_tx)(void *, uint16_t idx); 213 typedef void (*bnxt_doorbell_rx)(void *, uint16_t idx); 214 typedef void (*bnxt_doorbell_rx_cq)(void *, bool); 215 typedef void (*bnxt_doorbell_tx_cq)(void *, bool); 216 typedef void (*bnxt_doorbell_nq)(void *, bool); 217 218 typedef struct bnxt_doorbell_ops { 219 bnxt_doorbell_tx bnxt_db_tx; 220 bnxt_doorbell_rx bnxt_db_rx; 221 bnxt_doorbell_rx_cq bnxt_db_rx_cq; 222 bnxt_doorbell_tx_cq bnxt_db_tx_cq; 223 bnxt_doorbell_nq bnxt_db_nq; 224 } bnxt_dooorbell_ops_t; 225 /* NVRAM access */ 226 enum bnxt_nvm_directory_type { 227 BNX_DIR_TYPE_UNUSED = 0, 228 BNX_DIR_TYPE_PKG_LOG = 1, 229 BNX_DIR_TYPE_UPDATE = 2, 230 BNX_DIR_TYPE_CHIMP_PATCH = 3, 231 BNX_DIR_TYPE_BOOTCODE = 4, 232 BNX_DIR_TYPE_VPD = 5, 233 BNX_DIR_TYPE_EXP_ROM_MBA = 6, 234 BNX_DIR_TYPE_AVS = 7, 235 BNX_DIR_TYPE_PCIE = 8, 236 BNX_DIR_TYPE_PORT_MACRO = 9, 237 BNX_DIR_TYPE_APE_FW = 10, 238 BNX_DIR_TYPE_APE_PATCH = 11, 239 BNX_DIR_TYPE_KONG_FW = 12, 240 BNX_DIR_TYPE_KONG_PATCH = 13, 241 BNX_DIR_TYPE_BONO_FW = 14, 242 BNX_DIR_TYPE_BONO_PATCH = 15, 243 BNX_DIR_TYPE_TANG_FW = 16, 244 BNX_DIR_TYPE_TANG_PATCH = 17, 245 BNX_DIR_TYPE_BOOTCODE_2 = 18, 246 BNX_DIR_TYPE_CCM = 19, 247 BNX_DIR_TYPE_PCI_CFG = 20, 248 BNX_DIR_TYPE_TSCF_UCODE = 21, 249 BNX_DIR_TYPE_ISCSI_BOOT = 22, 250 BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24, 251 BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25, 252 BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26, 253 BNX_DIR_TYPE_EXT_PHY = 27, 254 BNX_DIR_TYPE_SHARED_CFG = 40, 255 BNX_DIR_TYPE_PORT_CFG = 41, 256 BNX_DIR_TYPE_FUNC_CFG = 42, 257 BNX_DIR_TYPE_MGMT_CFG = 48, 258 BNX_DIR_TYPE_MGMT_DATA = 49, 259 BNX_DIR_TYPE_MGMT_WEB_DATA = 50, 260 BNX_DIR_TYPE_MGMT_WEB_META = 51, 261 BNX_DIR_TYPE_MGMT_EVENT_LOG = 52, 262 BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53 263 }; 264 265 enum bnxnvm_pkglog_field_index { 266 BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0, 267 BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1, 268 BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2, 269 BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3, 270 BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4, 271 BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5, 272 BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6 273 }; 274 275 #define BNX_DIR_ORDINAL_FIRST 0 276 #define BNX_DIR_EXT_NONE 0 277 278 struct bnxt_bar_info { 279 struct resource *res; 280 bus_space_tag_t tag; 281 bus_space_handle_t handle; 282 bus_size_t size; 283 int rid; 284 }; 285 286 struct bnxt_flow_ctrl { 287 bool rx; 288 bool tx; 289 bool autoneg; 290 }; 291 292 struct bnxt_link_info { 293 uint8_t media_type; 294 uint8_t transceiver; 295 uint8_t phy_addr; 296 uint8_t phy_link_status; 297 uint8_t wire_speed; 298 uint8_t loop_back; 299 uint8_t link_up; 300 uint8_t last_link_up; 301 uint8_t duplex; 302 uint8_t last_duplex; 303 struct bnxt_flow_ctrl flow_ctrl; 304 struct bnxt_flow_ctrl last_flow_ctrl; 305 uint8_t duplex_setting; 306 uint8_t auto_mode; 307 #define PHY_VER_LEN 3 308 uint8_t phy_ver[PHY_VER_LEN]; 309 uint8_t phy_type; 310 uint16_t link_speed; 311 uint16_t support_speeds; 312 uint16_t auto_link_speeds; 313 uint16_t auto_link_speed; 314 uint16_t force_link_speed; 315 uint32_t preemphasis; 316 317 /* copy of requested setting */ 318 uint8_t autoneg; 319 #define BNXT_AUTONEG_SPEED 1 320 #define BNXT_AUTONEG_FLOW_CTRL 2 321 uint8_t req_duplex; 322 uint16_t req_link_speed; 323 }; 324 325 enum bnxt_cp_type { 326 BNXT_DEFAULT, 327 BNXT_TX, 328 BNXT_RX, 329 BNXT_SHARED 330 }; 331 332 struct bnxt_cos_queue { 333 uint8_t id; 334 uint8_t profile; 335 }; 336 337 struct bnxt_func_info { 338 uint32_t fw_fid; 339 uint8_t mac_addr[ETHER_ADDR_LEN]; 340 uint16_t max_rsscos_ctxs; 341 uint16_t max_cp_rings; 342 uint16_t max_tx_rings; 343 uint16_t max_rx_rings; 344 uint16_t max_hw_ring_grps; 345 uint16_t max_irqs; 346 uint16_t max_l2_ctxs; 347 uint16_t max_vnics; 348 uint16_t max_stat_ctxs; 349 }; 350 351 struct bnxt_pf_info { 352 #define BNXT_FIRST_PF_FID 1 353 #define BNXT_FIRST_VF_FID 128 354 uint8_t port_id; 355 uint32_t first_vf_id; 356 uint16_t active_vfs; 357 uint16_t max_vfs; 358 uint32_t max_encap_records; 359 uint32_t max_decap_records; 360 uint32_t max_tx_em_flows; 361 uint32_t max_tx_wm_flows; 362 uint32_t max_rx_em_flows; 363 uint32_t max_rx_wm_flows; 364 unsigned long *vf_event_bmap; 365 uint16_t hwrm_cmd_req_pages; 366 void *hwrm_cmd_req_addr[4]; 367 bus_addr_t hwrm_cmd_req_dma_addr[4]; 368 }; 369 370 struct bnxt_vf_info { 371 uint16_t fw_fid; 372 uint8_t mac_addr[ETHER_ADDR_LEN]; 373 uint16_t max_rsscos_ctxs; 374 uint16_t max_cp_rings; 375 uint16_t max_tx_rings; 376 uint16_t max_rx_rings; 377 uint16_t max_hw_ring_grps; 378 uint16_t max_l2_ctxs; 379 uint16_t max_irqs; 380 uint16_t max_vnics; 381 uint16_t max_stat_ctxs; 382 uint32_t vlan; 383 #define BNXT_VF_QOS 0x1 384 #define BNXT_VF_SPOOFCHK 0x2 385 #define BNXT_VF_LINK_FORCED 0x4 386 #define BNXT_VF_LINK_UP 0x8 387 uint32_t flags; 388 uint32_t func_flags; /* func cfg flags */ 389 uint32_t min_tx_rate; 390 uint32_t max_tx_rate; 391 void *hwrm_cmd_req_addr; 392 bus_addr_t hwrm_cmd_req_dma_addr; 393 }; 394 395 #define BNXT_PF(softc) (!((softc)->flags & BNXT_FLAG_VF)) 396 #define BNXT_VF(softc) ((softc)->flags & BNXT_FLAG_VF) 397 398 struct bnxt_vlan_tag { 399 SLIST_ENTRY(bnxt_vlan_tag) next; 400 uint64_t filter_id; 401 uint16_t tag; 402 }; 403 404 struct bnxt_vnic_info { 405 uint16_t id; 406 uint16_t def_ring_grp; 407 uint16_t cos_rule; 408 uint16_t lb_rule; 409 uint16_t mru; 410 411 uint32_t rx_mask; 412 struct iflib_dma_info mc_list; 413 int mc_list_count; 414 #define BNXT_MAX_MC_ADDRS 16 415 416 uint32_t flags; 417 #define BNXT_VNIC_FLAG_DEFAULT 0x01 418 #define BNXT_VNIC_FLAG_BD_STALL 0x02 419 #define BNXT_VNIC_FLAG_VLAN_STRIP 0x04 420 421 uint64_t filter_id; 422 423 uint16_t rss_id; 424 uint32_t rss_hash_type; 425 uint8_t rss_hash_key[HW_HASH_KEY_SIZE]; 426 struct iflib_dma_info rss_hash_key_tbl; 427 struct iflib_dma_info rss_grp_tbl; 428 SLIST_HEAD(vlan_head, bnxt_vlan_tag) vlan_tags; 429 struct iflib_dma_info vlan_tag_list; 430 }; 431 432 struct bnxt_grp_info { 433 uint16_t stats_ctx; 434 uint16_t grp_id; 435 uint16_t rx_ring_id; 436 uint16_t cp_ring_id; 437 uint16_t ag_ring_id; 438 }; 439 440 struct bnxt_ring { 441 uint64_t paddr; 442 vm_offset_t doorbell; 443 caddr_t vaddr; 444 struct bnxt_softc *softc; 445 uint32_t ring_size; /* Must be a power of two */ 446 uint16_t id; /* Logical ID */ 447 uint16_t phys_id; 448 uint16_t idx; 449 struct bnxt_full_tpa_start *tpa_start; 450 }; 451 452 struct bnxt_cp_ring { 453 struct bnxt_ring ring; 454 struct if_irq irq; 455 uint32_t cons; 456 bool v_bit; /* Value of valid bit */ 457 struct ctx_hw_stats *stats; 458 uint32_t stats_ctx_id; 459 uint32_t last_idx; /* Used by RX rings only 460 * set to the last read pidx 461 */ 462 uint64_t int_count; 463 }; 464 465 struct bnxt_full_tpa_start { 466 struct rx_tpa_start_cmpl low; 467 struct rx_tpa_start_cmpl_hi high; 468 }; 469 470 /* All the version information for the part */ 471 #define BNXT_VERSTR_SIZE (3*3+2+1) /* ie: "255.255.255\0" */ 472 #define BNXT_NAME_SIZE 17 473 #define FW_VER_STR_LEN 32 474 #define BC_HWRM_STR_LEN 21 475 struct bnxt_ver_info { 476 uint8_t hwrm_if_major; 477 uint8_t hwrm_if_minor; 478 uint8_t hwrm_if_update; 479 char hwrm_if_ver[BNXT_VERSTR_SIZE]; 480 char driver_hwrm_if_ver[BNXT_VERSTR_SIZE]; 481 char hwrm_fw_ver[BNXT_VERSTR_SIZE]; 482 char mgmt_fw_ver[BNXT_VERSTR_SIZE]; 483 char netctrl_fw_ver[BNXT_VERSTR_SIZE]; 484 char roce_fw_ver[BNXT_VERSTR_SIZE]; 485 char fw_ver_str[FW_VER_STR_LEN]; 486 char phy_ver[BNXT_VERSTR_SIZE]; 487 char pkg_ver[64]; 488 489 char hwrm_fw_name[BNXT_NAME_SIZE]; 490 char mgmt_fw_name[BNXT_NAME_SIZE]; 491 char netctrl_fw_name[BNXT_NAME_SIZE]; 492 char roce_fw_name[BNXT_NAME_SIZE]; 493 char phy_vendor[BNXT_NAME_SIZE]; 494 char phy_partnumber[BNXT_NAME_SIZE]; 495 496 uint16_t chip_num; 497 uint8_t chip_rev; 498 uint8_t chip_metal; 499 uint8_t chip_bond_id; 500 uint8_t chip_type; 501 502 uint8_t hwrm_min_major; 503 uint8_t hwrm_min_minor; 504 uint8_t hwrm_min_update; 505 506 struct sysctl_ctx_list ver_ctx; 507 struct sysctl_oid *ver_oid; 508 }; 509 510 struct bnxt_nvram_info { 511 uint16_t mfg_id; 512 uint16_t device_id; 513 uint32_t sector_size; 514 uint32_t size; 515 uint32_t reserved_size; 516 uint32_t available_size; 517 518 struct sysctl_ctx_list nvm_ctx; 519 struct sysctl_oid *nvm_oid; 520 }; 521 522 struct bnxt_func_qcfg { 523 uint16_t alloc_completion_rings; 524 uint16_t alloc_tx_rings; 525 uint16_t alloc_rx_rings; 526 uint16_t alloc_vnics; 527 }; 528 529 struct bnxt_hw_lro { 530 uint16_t enable; 531 uint16_t is_mode_gro; 532 uint16_t max_agg_segs; 533 uint16_t max_aggs; 534 uint32_t min_agg_len; 535 }; 536 537 /* The hardware supports certain page sizes. Use the supported page sizes 538 * to allocate the rings. 539 */ 540 #if (PAGE_SHIFT < 12) 541 #define BNXT_PAGE_SHIFT 12 542 #elif (PAGE_SHIFT <= 13) 543 #define BNXT_PAGE_SHIFT PAGE_SHIFT 544 #elif (PAGE_SHIFT < 16) 545 #define BNXT_PAGE_SHIFT 13 546 #else 547 #define BNXT_PAGE_SHIFT 16 548 #endif 549 550 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) 551 552 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 553 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES) 554 struct bnxt_ring_mem_info { 555 int nr_pages; 556 int page_size; 557 uint16_t flags; 558 #define BNXT_RMEM_VALID_PTE_FLAG 1 559 #define BNXT_RMEM_RING_PTE_FLAG 2 560 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4 561 uint16_t depth; 562 uint8_t init_val; 563 struct iflib_dma_info *pg_arr; 564 struct iflib_dma_info pg_tbl; 565 int vmem_size; 566 void **vmem; 567 }; 568 569 struct bnxt_ctx_pg_info { 570 uint32_t entries; 571 uint32_t nr_pages; 572 struct iflib_dma_info ctx_arr[MAX_CTX_PAGES]; 573 struct bnxt_ring_mem_info ring_mem; 574 struct bnxt_ctx_pg_info **ctx_pg_tbl; 575 }; 576 577 struct bnxt_ctx_mem_info { 578 uint32_t qp_max_entries; 579 uint16_t qp_min_qp1_entries; 580 uint16_t qp_max_l2_entries; 581 uint16_t qp_entry_size; 582 uint16_t srq_max_l2_entries; 583 uint32_t srq_max_entries; 584 uint16_t srq_entry_size; 585 uint16_t cq_max_l2_entries; 586 uint32_t cq_max_entries; 587 uint16_t cq_entry_size; 588 uint16_t vnic_max_vnic_entries; 589 uint16_t vnic_max_ring_table_entries; 590 uint16_t vnic_entry_size; 591 uint32_t stat_max_entries; 592 uint16_t stat_entry_size; 593 uint16_t tqm_entry_size; 594 uint32_t tqm_min_entries_per_ring; 595 uint32_t tqm_max_entries_per_ring; 596 uint32_t mrav_max_entries; 597 uint16_t mrav_entry_size; 598 uint16_t tim_entry_size; 599 uint32_t tim_max_entries; 600 uint8_t tqm_entries_multiple; 601 uint8_t ctx_kind_initializer; 602 603 uint32_t flags; 604 #define BNXT_CTX_FLAG_INITED 0x01 605 606 struct bnxt_ctx_pg_info qp_mem; 607 struct bnxt_ctx_pg_info srq_mem; 608 struct bnxt_ctx_pg_info cq_mem; 609 struct bnxt_ctx_pg_info vnic_mem; 610 struct bnxt_ctx_pg_info stat_mem; 611 struct bnxt_ctx_pg_info mrav_mem; 612 struct bnxt_ctx_pg_info tim_mem; 613 struct bnxt_ctx_pg_info *tqm_mem[9]; 614 }; 615 616 struct bnxt_hw_resc { 617 uint16_t min_rsscos_ctxs; 618 uint16_t max_rsscos_ctxs; 619 uint16_t min_cp_rings; 620 uint16_t max_cp_rings; 621 uint16_t resv_cp_rings; 622 uint16_t min_tx_rings; 623 uint16_t max_tx_rings; 624 uint16_t resv_tx_rings; 625 uint16_t max_tx_sch_inputs; 626 uint16_t min_rx_rings; 627 uint16_t max_rx_rings; 628 uint16_t resv_rx_rings; 629 uint16_t min_hw_ring_grps; 630 uint16_t max_hw_ring_grps; 631 uint16_t resv_hw_ring_grps; 632 uint16_t min_l2_ctxs; 633 uint16_t max_l2_ctxs; 634 uint16_t min_vnics; 635 uint16_t max_vnics; 636 uint16_t resv_vnics; 637 uint16_t min_stat_ctxs; 638 uint16_t max_stat_ctxs; 639 uint16_t resv_stat_ctxs; 640 uint16_t max_nqs; 641 uint16_t max_irqs; 642 uint16_t resv_irqs; 643 }; 644 645 #define BNXT_LLQ(q_profile) \ 646 ((q_profile) == HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE) 647 #define BNXT_CNPQ(q_profile) \ 648 ((q_profile) == HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP) 649 650 #define BNXT_HWRM_MAX_REQ_LEN (softc->hwrm_max_req_len) 651 652 struct bnxt_softc_list { 653 SLIST_ENTRY(bnxt_softc_list) next; 654 struct bnxt_softc *softc; 655 }; 656 657 struct bnxt_softc { 658 device_t dev; 659 if_ctx_t ctx; 660 if_softc_ctx_t scctx; 661 if_shared_ctx_t sctx; 662 uint32_t domain; 663 uint32_t bus; 664 uint32_t slot; 665 uint32_t function; 666 uint32_t dev_fn; 667 struct ifmedia *media; 668 struct bnxt_ctx_mem_info *ctx_mem; 669 struct bnxt_hw_resc hw_resc; 670 struct bnxt_softc_list list; 671 672 struct bnxt_bar_info hwrm_bar; 673 struct bnxt_bar_info doorbell_bar; 674 struct bnxt_link_info link_info; 675 #define BNXT_FLAG_VF 0x0001 676 #define BNXT_FLAG_NPAR 0x0002 677 #define BNXT_FLAG_WOL_CAP 0x0004 678 #define BNXT_FLAG_SHORT_CMD 0x0008 679 #define BNXT_FLAG_FW_CAP_NEW_RM 0x0010 680 #define BNXT_FLAG_CHIP_P5 0x0020 681 #define BNXT_FLAG_TPA 0x0040 682 uint32_t flags; 683 #define BNXT_STATE_LINK_CHANGE (0) 684 #define BNXT_STATE_MAX (BNXT_STATE_LINK_CHANGE + 1) 685 bitstr_t *state_bv; 686 uint32_t total_msix; 687 688 struct bnxt_func_info func; 689 struct bnxt_func_qcfg fn_qcfg; 690 struct bnxt_pf_info pf; 691 struct bnxt_vf_info vf; 692 693 uint16_t hwrm_cmd_seq; 694 uint32_t hwrm_cmd_timeo; /* milliseconds */ 695 struct iflib_dma_info hwrm_cmd_resp; 696 struct iflib_dma_info hwrm_short_cmd_req_addr; 697 /* Interrupt info for HWRM */ 698 struct if_irq irq; 699 struct mtx hwrm_lock; 700 uint16_t hwrm_max_req_len; 701 uint16_t hwrm_max_ext_req_len; 702 uint32_t hwrm_spec_code; 703 704 #define BNXT_MAX_COS_QUEUE 8 705 uint8_t max_tc; 706 uint8_t max_lltc; /* lossless TCs */ 707 struct bnxt_cos_queue q_info[BNXT_MAX_COS_QUEUE]; 708 uint8_t tc_to_qidx[BNXT_MAX_COS_QUEUE]; 709 uint8_t q_ids[BNXT_MAX_COS_QUEUE]; 710 uint8_t max_q; 711 712 uint64_t admin_ticks; 713 struct iflib_dma_info hw_rx_port_stats; 714 struct iflib_dma_info hw_tx_port_stats; 715 struct rx_port_stats *rx_port_stats; 716 struct tx_port_stats *tx_port_stats; 717 718 int num_cp_rings; 719 720 struct bnxt_cp_ring *nq_rings; 721 722 struct bnxt_ring *tx_rings; 723 struct bnxt_cp_ring *tx_cp_rings; 724 struct iflib_dma_info tx_stats[BNXT_MAX_NUM_QUEUES]; 725 int ntxqsets; 726 727 struct bnxt_vnic_info vnic_info; 728 struct bnxt_ring *ag_rings; 729 struct bnxt_ring *rx_rings; 730 struct bnxt_cp_ring *rx_cp_rings; 731 struct bnxt_grp_info *grp_info; 732 struct iflib_dma_info rx_stats[BNXT_MAX_NUM_QUEUES]; 733 int nrxqsets; 734 uint16_t rx_buf_size; 735 736 struct bnxt_cp_ring def_cp_ring; 737 struct bnxt_cp_ring def_nq_ring; 738 struct iflib_dma_info def_cp_ring_mem; 739 struct iflib_dma_info def_nq_ring_mem; 740 struct grouptask def_cp_task; 741 struct bnxt_doorbell_ops db_ops; 742 743 struct sysctl_ctx_list hw_stats; 744 struct sysctl_oid *hw_stats_oid; 745 struct sysctl_ctx_list hw_lro_ctx; 746 struct sysctl_oid *hw_lro_oid; 747 struct sysctl_ctx_list flow_ctrl_ctx; 748 struct sysctl_oid *flow_ctrl_oid; 749 750 struct bnxt_ver_info *ver_info; 751 struct bnxt_nvram_info *nvm_info; 752 bool wol; 753 bool is_dev_init; 754 struct bnxt_hw_lro hw_lro; 755 uint8_t wol_filter_id; 756 uint16_t rx_coal_usecs; 757 uint16_t rx_coal_usecs_irq; 758 uint16_t rx_coal_frames; 759 uint16_t rx_coal_frames_irq; 760 uint16_t tx_coal_usecs; 761 uint16_t tx_coal_usecs_irq; 762 uint16_t tx_coal_frames; 763 uint16_t tx_coal_frames_irq; 764 765 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2) 766 #define BNXT_DEF_STATS_COAL_TICKS 1000000 767 #define BNXT_MIN_STATS_COAL_TICKS 250000 768 #define BNXT_MAX_STATS_COAL_TICKS 1000000 769 770 }; 771 772 struct bnxt_filter_info { 773 STAILQ_ENTRY(bnxt_filter_info) next; 774 uint64_t fw_l2_filter_id; 775 #define INVALID_MAC_INDEX ((uint16_t)-1) 776 uint16_t mac_index; 777 778 /* Filter Characteristics */ 779 uint32_t flags; 780 uint32_t enables; 781 uint8_t l2_addr[ETHER_ADDR_LEN]; 782 uint8_t l2_addr_mask[ETHER_ADDR_LEN]; 783 uint16_t l2_ovlan; 784 uint16_t l2_ovlan_mask; 785 uint16_t l2_ivlan; 786 uint16_t l2_ivlan_mask; 787 uint8_t t_l2_addr[ETHER_ADDR_LEN]; 788 uint8_t t_l2_addr_mask[ETHER_ADDR_LEN]; 789 uint16_t t_l2_ovlan; 790 uint16_t t_l2_ovlan_mask; 791 uint16_t t_l2_ivlan; 792 uint16_t t_l2_ivlan_mask; 793 uint8_t tunnel_type; 794 uint16_t mirror_vnic_id; 795 uint32_t vni; 796 uint8_t pri_hint; 797 uint64_t l2_filter_id_hint; 798 }; 799 800 /* Function declarations */ 801 void bnxt_report_link(struct bnxt_softc *softc); 802 bool bnxt_check_hwrm_version(struct bnxt_softc *softc); 803 struct bnxt_softc *bnxt_find_dev(uint32_t domain, uint32_t bus, uint32_t dev_fn, char *name); 804 805 #endif /* _BNXT_H */
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