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sys/dev/bnxt/bnxt.h
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1 /*- 2 * Broadcom NetXtreme-C/E network driver. 3 * 4 * Copyright (c) 2016 Broadcom, All Rights Reserved. 5 * The term Broadcom refers to Broadcom Limited and/or its subsidiaries 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD: releng/12.0/sys/dev/bnxt/bnxt.h 327000 2017-12-19 21:07:30Z shurd $"); 31 32 #ifndef _BNXT_H 33 #define _BNXT_H 34 35 #include <sys/param.h> 36 #include <sys/socket.h> 37 #include <sys/sysctl.h> 38 #include <sys/taskqueue.h> 39 40 #include <machine/bus.h> 41 42 #include <net/ethernet.h> 43 #include <net/if.h> 44 #include <net/if_var.h> 45 #include <net/iflib.h> 46 47 #include "hsi_struct_def.h" 48 49 /* PCI IDs */ 50 #define BROADCOM_VENDOR_ID 0x14E4 51 52 #define BCM57301 0x16c8 53 #define BCM57302 0x16c9 54 #define BCM57304 0x16ca 55 #define BCM57311 0x16ce 56 #define BCM57312 0x16cf 57 #define BCM57314 0x16df 58 #define BCM57402 0x16d0 59 #define BCM57402_NPAR 0x16d4 60 #define BCM57404 0x16d1 61 #define BCM57404_NPAR 0x16e7 62 #define BCM57406 0x16d2 63 #define BCM57406_NPAR 0x16e8 64 #define BCM57407 0x16d5 65 #define BCM57407_NPAR 0x16ea 66 #define BCM57407_SFP 0x16e9 67 #define BCM57412 0x16d6 68 #define BCM57412_NPAR1 0x16de 69 #define BCM57412_NPAR2 0x16eb 70 #define BCM57414 0x16d7 71 #define BCM57414_NPAR1 0x16ec 72 #define BCM57414_NPAR2 0x16ed 73 #define BCM57416 0x16d8 74 #define BCM57416_NPAR1 0x16ee 75 #define BCM57416_NPAR2 0x16ef 76 #define BCM57416_SFP 0x16e3 77 #define BCM57417 0x16d9 78 #define BCM57417_NPAR1 0x16c0 79 #define BCM57417_NPAR2 0x16cc 80 #define BCM57417_SFP 0x16e2 81 #define BCM57454 0x1614 82 #define BCM58700 0x16cd 83 #define NETXTREME_C_VF1 0x16cb 84 #define NETXTREME_C_VF2 0x16e1 85 #define NETXTREME_C_VF3 0x16e5 86 #define NETXTREME_E_VF1 0x16c1 87 #define NETXTREME_E_VF2 0x16d3 88 #define NETXTREME_E_VF3 0x16dc 89 90 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 91 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 92 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 93 94 #define BNXT_MAX_MTU 9000 95 96 #define BNXT_RSS_HASH_TYPE_TCPV4 0 97 #define BNXT_RSS_HASH_TYPE_UDPV4 1 98 #define BNXT_RSS_HASH_TYPE_IPV4 2 99 #define BNXT_RSS_HASH_TYPE_TCPV6 3 100 #define BNXT_RSS_HASH_TYPE_UDPV6 4 101 #define BNXT_RSS_HASH_TYPE_IPV6 5 102 #define BNXT_GET_RSS_PROFILE_ID(rss_hash_type) ((rss_hash_type >> 1) & 0x1F) 103 104 #define BNXT_NO_MORE_WOL_FILTERS 0xFFFF 105 #define bnxt_wol_supported(softc) (!((softc)->flags & BNXT_FLAG_VF) && \ 106 ((softc)->flags & BNXT_FLAG_WOL_CAP )) 107 108 /* Completion related defines */ 109 #define CMP_VALID(cmp, v_bit) \ 110 ((!!(((struct cmpl_base *)(cmp))->info3_v & htole32(CMPL_BASE_V))) == !!(v_bit) ) 111 112 #define NEXT_CP_CONS_V(ring, cons, v_bit) do { \ 113 if (__predict_false(++(cons) == (ring)->ring_size)) \ 114 ((cons) = 0, (v_bit) = !v_bit); \ 115 } while (0) 116 117 #define RING_NEXT(ring, idx) (__predict_false(idx + 1 == (ring)->ring_size) ? \ 118 0 : idx + 1) 119 120 #define CMPL_PREFETCH_NEXT(cpr, idx) \ 121 __builtin_prefetch(&((struct cmpl_base *)(cpr)->ring.vaddr)[((idx) +\ 122 (CACHE_LINE_SIZE / sizeof(struct cmpl_base))) & \ 123 ((cpr)->ring.ring_size - 1)]) 124 125 /* 126 * If we update the index, a write barrier is needed after the write to ensure 127 * the completion ring has space before the RX/TX ring does. Since we can't 128 * make the RX and AG doorbells covered by the same barrier without remapping 129 * MSI-X vectors, we create the barrier over the enture doorbell bar. 130 * TODO: Remap the MSI-X vectors to allow a barrier to only cover the doorbells 131 * for a single ring group. 132 * 133 * A barrier of just the size of the write is used to ensure the ordering 134 * remains correct and no writes are lost. 135 */ 136 #define BNXT_CP_DISABLE_DB(ring) do { \ 137 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 138 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ 139 BUS_SPACE_BARRIER_WRITE); \ 140 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 141 (ring)->softc->doorbell_bar.handle, 0, \ 142 (ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \ 143 bus_space_write_4((ring)->softc->doorbell_bar.tag, \ 144 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, \ 145 htole32(CMPL_DOORBELL_KEY_CMPL | CMPL_DOORBELL_MASK)); \ 146 } while (0) 147 148 #define BNXT_CP_ENABLE_DB(ring) do { \ 149 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 150 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ 151 BUS_SPACE_BARRIER_WRITE); \ 152 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 153 (ring)->softc->doorbell_bar.handle, 0, \ 154 (ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \ 155 bus_space_write_4((ring)->softc->doorbell_bar.tag, \ 156 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, \ 157 htole32(CMPL_DOORBELL_KEY_CMPL)); \ 158 } while (0) 159 160 #define BNXT_CP_IDX_ENABLE_DB(ring, cons) do { \ 161 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 162 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ 163 BUS_SPACE_BARRIER_WRITE); \ 164 bus_space_write_4((ring)->softc->doorbell_bar.tag, \ 165 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, \ 166 htole32(CMPL_DOORBELL_KEY_CMPL | CMPL_DOORBELL_IDX_VALID | \ 167 (cons))); \ 168 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 169 (ring)->softc->doorbell_bar.handle, 0, \ 170 (ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \ 171 } while (0) 172 173 #define BNXT_CP_IDX_DISABLE_DB(ring, cons) do { \ 174 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 175 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ 176 BUS_SPACE_BARRIER_WRITE); \ 177 bus_space_write_4((ring)->softc->doorbell_bar.tag, \ 178 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, \ 179 htole32(CMPL_DOORBELL_KEY_CMPL | CMPL_DOORBELL_IDX_VALID | \ 180 CMPL_DOORBELL_MASK | (cons))); \ 181 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 182 (ring)->softc->doorbell_bar.handle, 0, \ 183 (ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \ 184 } while (0) 185 186 #define BNXT_TX_DB(ring, idx) do { \ 187 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 188 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ 189 BUS_SPACE_BARRIER_WRITE); \ 190 bus_space_write_4( \ 191 (ring)->softc->doorbell_bar.tag, \ 192 (ring)->softc->doorbell_bar.handle, \ 193 (ring)->doorbell, htole32(TX_DOORBELL_KEY_TX | (idx))); \ 194 } while (0) 195 196 #define BNXT_RX_DB(ring, idx) do { \ 197 bus_space_barrier((ring)->softc->doorbell_bar.tag, \ 198 (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ 199 BUS_SPACE_BARRIER_WRITE); \ 200 bus_space_write_4( \ 201 (ring)->softc->doorbell_bar.tag, \ 202 (ring)->softc->doorbell_bar.handle, \ 203 (ring)->doorbell, htole32(RX_DOORBELL_KEY_RX | (idx))); \ 204 } while (0) 205 206 /* Lock macros */ 207 #define BNXT_HWRM_LOCK_INIT(_softc, _name) \ 208 mtx_init(&(_softc)->hwrm_lock, _name, "BNXT HWRM Lock", MTX_DEF) 209 #define BNXT_HWRM_LOCK(_softc) mtx_lock(&(_softc)->hwrm_lock) 210 #define BNXT_HWRM_UNLOCK(_softc) mtx_unlock(&(_softc)->hwrm_lock) 211 #define BNXT_HWRM_LOCK_DESTROY(_softc) mtx_destroy(&(_softc)->hwrm_lock) 212 #define BNXT_HWRM_LOCK_ASSERT(_softc) mtx_assert(&(_softc)->hwrm_lock, \ 213 MA_OWNED) 214 #define BNXT_IS_FLOW_CTRL_CHANGED(link_info) \ 215 ((link_info->last_flow_ctrl.tx != link_info->flow_ctrl.tx) || \ 216 (link_info->last_flow_ctrl.rx != link_info->flow_ctrl.rx) || \ 217 (link_info->last_flow_ctrl.autoneg != link_info->flow_ctrl.autoneg)) 218 219 /* Chip info */ 220 #define BNXT_TSO_SIZE UINT16_MAX 221 222 #define min_t(type, x, y) ({ \ 223 type __min1 = (x); \ 224 type __min2 = (y); \ 225 __min1 < __min2 ? __min1 : __min2; }) 226 227 #define max_t(type, x, y) ({ \ 228 type __max1 = (x); \ 229 type __max2 = (y); \ 230 __max1 > __max2 ? __max1 : __max2; }) 231 232 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 233 234 #define BNXT_IFMEDIA_ADD(supported, fw_speed, ifm_speed) do { \ 235 if ((supported) & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_ ## fw_speed) \ 236 ifmedia_add(softc->media, IFM_ETHER | (ifm_speed), 0, NULL); \ 237 } while(0) 238 239 #define BNXT_MIN_FRAME_SIZE 52 /* Frames must be padded to this size for some A0 chips */ 240 241 /* NVRAM access */ 242 enum bnxt_nvm_directory_type { 243 BNX_DIR_TYPE_UNUSED = 0, 244 BNX_DIR_TYPE_PKG_LOG = 1, 245 BNX_DIR_TYPE_UPDATE = 2, 246 BNX_DIR_TYPE_CHIMP_PATCH = 3, 247 BNX_DIR_TYPE_BOOTCODE = 4, 248 BNX_DIR_TYPE_VPD = 5, 249 BNX_DIR_TYPE_EXP_ROM_MBA = 6, 250 BNX_DIR_TYPE_AVS = 7, 251 BNX_DIR_TYPE_PCIE = 8, 252 BNX_DIR_TYPE_PORT_MACRO = 9, 253 BNX_DIR_TYPE_APE_FW = 10, 254 BNX_DIR_TYPE_APE_PATCH = 11, 255 BNX_DIR_TYPE_KONG_FW = 12, 256 BNX_DIR_TYPE_KONG_PATCH = 13, 257 BNX_DIR_TYPE_BONO_FW = 14, 258 BNX_DIR_TYPE_BONO_PATCH = 15, 259 BNX_DIR_TYPE_TANG_FW = 16, 260 BNX_DIR_TYPE_TANG_PATCH = 17, 261 BNX_DIR_TYPE_BOOTCODE_2 = 18, 262 BNX_DIR_TYPE_CCM = 19, 263 BNX_DIR_TYPE_PCI_CFG = 20, 264 BNX_DIR_TYPE_TSCF_UCODE = 21, 265 BNX_DIR_TYPE_ISCSI_BOOT = 22, 266 BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24, 267 BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25, 268 BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26, 269 BNX_DIR_TYPE_EXT_PHY = 27, 270 BNX_DIR_TYPE_SHARED_CFG = 40, 271 BNX_DIR_TYPE_PORT_CFG = 41, 272 BNX_DIR_TYPE_FUNC_CFG = 42, 273 BNX_DIR_TYPE_MGMT_CFG = 48, 274 BNX_DIR_TYPE_MGMT_DATA = 49, 275 BNX_DIR_TYPE_MGMT_WEB_DATA = 50, 276 BNX_DIR_TYPE_MGMT_WEB_META = 51, 277 BNX_DIR_TYPE_MGMT_EVENT_LOG = 52, 278 BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53 279 }; 280 281 enum bnxnvm_pkglog_field_index { 282 BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0, 283 BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1, 284 BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2, 285 BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3, 286 BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4, 287 BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5, 288 BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6 289 }; 290 291 #define BNX_DIR_ORDINAL_FIRST 0 292 #define BNX_DIR_EXT_NONE 0 293 294 struct bnxt_bar_info { 295 struct resource *res; 296 bus_space_tag_t tag; 297 bus_space_handle_t handle; 298 bus_size_t size; 299 int rid; 300 }; 301 302 struct bnxt_flow_ctrl { 303 bool rx; 304 bool tx; 305 bool autoneg; 306 }; 307 308 struct bnxt_link_info { 309 uint8_t media_type; 310 uint8_t transceiver; 311 uint8_t phy_addr; 312 uint8_t phy_link_status; 313 uint8_t wire_speed; 314 uint8_t loop_back; 315 uint8_t link_up; 316 uint8_t last_link_up; 317 uint8_t duplex; 318 uint8_t last_duplex; 319 struct bnxt_flow_ctrl flow_ctrl; 320 struct bnxt_flow_ctrl last_flow_ctrl; 321 uint8_t duplex_setting; 322 uint8_t auto_mode; 323 #define PHY_VER_LEN 3 324 uint8_t phy_ver[PHY_VER_LEN]; 325 uint8_t phy_type; 326 uint16_t link_speed; 327 uint16_t support_speeds; 328 uint16_t auto_link_speeds; 329 uint16_t auto_link_speed; 330 uint16_t force_link_speed; 331 uint32_t preemphasis; 332 333 /* copy of requested setting */ 334 uint8_t autoneg; 335 #define BNXT_AUTONEG_SPEED 1 336 #define BNXT_AUTONEG_FLOW_CTRL 2 337 uint8_t req_duplex; 338 uint16_t req_link_speed; 339 }; 340 341 enum bnxt_cp_type { 342 BNXT_DEFAULT, 343 BNXT_TX, 344 BNXT_RX, 345 BNXT_SHARED 346 }; 347 348 struct bnxt_cos_queue { 349 uint8_t id; 350 uint8_t profile; 351 }; 352 353 struct bnxt_func_info { 354 uint32_t fw_fid; 355 uint8_t mac_addr[ETHER_ADDR_LEN]; 356 uint16_t max_rsscos_ctxs; 357 uint16_t max_cp_rings; 358 uint16_t max_tx_rings; 359 uint16_t max_rx_rings; 360 uint16_t max_hw_ring_grps; 361 uint16_t max_irqs; 362 uint16_t max_l2_ctxs; 363 uint16_t max_vnics; 364 uint16_t max_stat_ctxs; 365 }; 366 367 struct bnxt_pf_info { 368 #define BNXT_FIRST_PF_FID 1 369 #define BNXT_FIRST_VF_FID 128 370 uint8_t port_id; 371 uint32_t first_vf_id; 372 uint16_t active_vfs; 373 uint16_t max_vfs; 374 uint32_t max_encap_records; 375 uint32_t max_decap_records; 376 uint32_t max_tx_em_flows; 377 uint32_t max_tx_wm_flows; 378 uint32_t max_rx_em_flows; 379 uint32_t max_rx_wm_flows; 380 unsigned long *vf_event_bmap; 381 uint16_t hwrm_cmd_req_pages; 382 void *hwrm_cmd_req_addr[4]; 383 bus_addr_t hwrm_cmd_req_dma_addr[4]; 384 }; 385 386 struct bnxt_vf_info { 387 uint16_t fw_fid; 388 uint8_t mac_addr[ETHER_ADDR_LEN]; 389 uint16_t max_rsscos_ctxs; 390 uint16_t max_cp_rings; 391 uint16_t max_tx_rings; 392 uint16_t max_rx_rings; 393 uint16_t max_hw_ring_grps; 394 uint16_t max_l2_ctxs; 395 uint16_t max_irqs; 396 uint16_t max_vnics; 397 uint16_t max_stat_ctxs; 398 uint32_t vlan; 399 #define BNXT_VF_QOS 0x1 400 #define BNXT_VF_SPOOFCHK 0x2 401 #define BNXT_VF_LINK_FORCED 0x4 402 #define BNXT_VF_LINK_UP 0x8 403 uint32_t flags; 404 uint32_t func_flags; /* func cfg flags */ 405 uint32_t min_tx_rate; 406 uint32_t max_tx_rate; 407 void *hwrm_cmd_req_addr; 408 bus_addr_t hwrm_cmd_req_dma_addr; 409 }; 410 411 412 #define BNXT_PF(softc) (!((softc)->flags & BNXT_FLAG_VF)) 413 #define BNXT_VF(softc) ((softc)->flags & BNXT_FLAG_VF) 414 415 struct bnxt_vlan_tag { 416 SLIST_ENTRY(bnxt_vlan_tag) next; 417 uint16_t tpid; 418 uint16_t tag; 419 }; 420 421 struct bnxt_vnic_info { 422 uint16_t id; 423 uint16_t def_ring_grp; 424 uint16_t cos_rule; 425 uint16_t lb_rule; 426 uint16_t mru; 427 428 uint32_t rx_mask; 429 bool vlan_only; 430 struct iflib_dma_info mc_list; 431 int mc_list_count; 432 #define BNXT_MAX_MC_ADDRS 16 433 434 uint32_t flags; 435 #define BNXT_VNIC_FLAG_DEFAULT 0x01 436 #define BNXT_VNIC_FLAG_BD_STALL 0x02 437 #define BNXT_VNIC_FLAG_VLAN_STRIP 0x04 438 439 uint64_t filter_id; 440 uint32_t flow_id; 441 442 uint16_t rss_id; 443 uint32_t rss_hash_type; 444 uint8_t rss_hash_key[HW_HASH_KEY_SIZE]; 445 struct iflib_dma_info rss_hash_key_tbl; 446 struct iflib_dma_info rss_grp_tbl; 447 SLIST_HEAD(vlan_head, bnxt_vlan_tag) vlan_tags; 448 struct iflib_dma_info vlan_tag_list; 449 }; 450 451 struct bnxt_grp_info { 452 uint16_t stats_ctx; 453 uint16_t grp_id; 454 uint16_t rx_ring_id; 455 uint16_t cp_ring_id; 456 uint16_t ag_ring_id; 457 }; 458 459 struct bnxt_ring { 460 uint64_t paddr; 461 vm_offset_t doorbell; 462 caddr_t vaddr; 463 struct bnxt_softc *softc; 464 uint32_t ring_size; /* Must be a power of two */ 465 uint16_t id; /* Logical ID */ 466 uint16_t phys_id; 467 struct bnxt_full_tpa_start *tpa_start; 468 }; 469 470 struct bnxt_cp_ring { 471 struct bnxt_ring ring; 472 struct if_irq irq; 473 uint32_t cons; 474 bool v_bit; /* Value of valid bit */ 475 struct ctx_hw_stats *stats; 476 uint32_t stats_ctx_id; 477 uint32_t last_idx; /* Used by RX rings only 478 * set to the last read pidx 479 */ 480 }; 481 482 struct bnxt_full_tpa_start { 483 struct rx_tpa_start_cmpl low; 484 struct rx_tpa_start_cmpl_hi high; 485 }; 486 487 /* All the version information for the part */ 488 #define BNXT_VERSTR_SIZE (3*3+2+1) /* ie: "255.255.255\0" */ 489 #define BNXT_NAME_SIZE 17 490 struct bnxt_ver_info { 491 uint8_t hwrm_if_major; 492 uint8_t hwrm_if_minor; 493 uint8_t hwrm_if_update; 494 char hwrm_if_ver[BNXT_VERSTR_SIZE]; 495 char driver_hwrm_if_ver[BNXT_VERSTR_SIZE]; 496 char hwrm_fw_ver[BNXT_VERSTR_SIZE]; 497 char mgmt_fw_ver[BNXT_VERSTR_SIZE]; 498 char netctrl_fw_ver[BNXT_VERSTR_SIZE]; 499 char roce_fw_ver[BNXT_VERSTR_SIZE]; 500 char phy_ver[BNXT_VERSTR_SIZE]; 501 char pkg_ver[64]; 502 503 char hwrm_fw_name[BNXT_NAME_SIZE]; 504 char mgmt_fw_name[BNXT_NAME_SIZE]; 505 char netctrl_fw_name[BNXT_NAME_SIZE]; 506 char roce_fw_name[BNXT_NAME_SIZE]; 507 char phy_vendor[BNXT_NAME_SIZE]; 508 char phy_partnumber[BNXT_NAME_SIZE]; 509 510 uint16_t chip_num; 511 uint8_t chip_rev; 512 uint8_t chip_metal; 513 uint8_t chip_bond_id; 514 uint8_t chip_type; 515 516 uint8_t hwrm_min_major; 517 uint8_t hwrm_min_minor; 518 uint8_t hwrm_min_update; 519 520 struct sysctl_ctx_list ver_ctx; 521 struct sysctl_oid *ver_oid; 522 }; 523 524 struct bnxt_nvram_info { 525 uint16_t mfg_id; 526 uint16_t device_id; 527 uint32_t sector_size; 528 uint32_t size; 529 uint32_t reserved_size; 530 uint32_t available_size; 531 532 struct sysctl_ctx_list nvm_ctx; 533 struct sysctl_oid *nvm_oid; 534 }; 535 536 struct bnxt_func_qcfg { 537 uint16_t alloc_completion_rings; 538 uint16_t alloc_tx_rings; 539 uint16_t alloc_rx_rings; 540 uint16_t alloc_vnics; 541 }; 542 543 struct bnxt_hw_lro { 544 uint16_t enable; 545 uint16_t is_mode_gro; 546 uint16_t max_agg_segs; 547 uint16_t max_aggs; 548 uint32_t min_agg_len; 549 }; 550 551 struct bnxt_softc { 552 device_t dev; 553 if_ctx_t ctx; 554 if_softc_ctx_t scctx; 555 if_shared_ctx_t sctx; 556 struct ifmedia *media; 557 558 struct bnxt_bar_info hwrm_bar; 559 struct bnxt_bar_info doorbell_bar; 560 struct bnxt_link_info link_info; 561 #define BNXT_FLAG_VF 0x0001 562 #define BNXT_FLAG_NPAR 0x0002 563 #define BNXT_FLAG_WOL_CAP 0x0004 564 #define BNXT_FLAG_SHORT_CMD 0x0008 565 uint32_t flags; 566 uint32_t total_msix; 567 568 struct bnxt_func_info func; 569 struct bnxt_func_qcfg fn_qcfg; 570 struct bnxt_pf_info pf; 571 struct bnxt_vf_info vf; 572 573 uint16_t hwrm_cmd_seq; 574 uint32_t hwrm_cmd_timeo; /* milliseconds */ 575 struct iflib_dma_info hwrm_cmd_resp; 576 struct iflib_dma_info hwrm_short_cmd_req_addr; 577 /* Interrupt info for HWRM */ 578 struct if_irq irq; 579 struct mtx hwrm_lock; 580 uint16_t hwrm_max_req_len; 581 582 #define BNXT_MAX_QUEUE 8 583 uint8_t max_tc; 584 struct bnxt_cos_queue q_info[BNXT_MAX_QUEUE]; 585 586 uint64_t admin_ticks; 587 struct iflib_dma_info hw_rx_port_stats; 588 struct iflib_dma_info hw_tx_port_stats; 589 struct rx_port_stats *rx_port_stats; 590 struct tx_port_stats *tx_port_stats; 591 592 int num_cp_rings; 593 594 struct bnxt_ring *tx_rings; 595 struct bnxt_cp_ring *tx_cp_rings; 596 struct iflib_dma_info tx_stats; 597 int ntxqsets; 598 599 struct bnxt_vnic_info vnic_info; 600 struct bnxt_ring *ag_rings; 601 struct bnxt_ring *rx_rings; 602 struct bnxt_cp_ring *rx_cp_rings; 603 struct bnxt_grp_info *grp_info; 604 struct iflib_dma_info rx_stats; 605 int nrxqsets; 606 607 struct bnxt_cp_ring def_cp_ring; 608 struct iflib_dma_info def_cp_ring_mem; 609 struct grouptask def_cp_task; 610 611 struct sysctl_ctx_list hw_stats; 612 struct sysctl_oid *hw_stats_oid; 613 struct sysctl_ctx_list hw_lro_ctx; 614 struct sysctl_oid *hw_lro_oid; 615 struct sysctl_ctx_list flow_ctrl_ctx; 616 struct sysctl_oid *flow_ctrl_oid; 617 618 struct bnxt_ver_info *ver_info; 619 struct bnxt_nvram_info *nvm_info; 620 bool wol; 621 struct bnxt_hw_lro hw_lro; 622 uint8_t wol_filter_id; 623 uint16_t rx_coal_usecs; 624 uint16_t rx_coal_usecs_irq; 625 uint16_t rx_coal_frames; 626 uint16_t rx_coal_frames_irq; 627 uint16_t tx_coal_usecs; 628 uint16_t tx_coal_usecs_irq; 629 uint16_t tx_coal_frames; 630 uint16_t tx_coal_frames_irq; 631 632 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2) 633 #define BNXT_DEF_STATS_COAL_TICKS 1000000 634 #define BNXT_MIN_STATS_COAL_TICKS 250000 635 #define BNXT_MAX_STATS_COAL_TICKS 1000000 636 637 }; 638 639 struct bnxt_filter_info { 640 STAILQ_ENTRY(bnxt_filter_info) next; 641 uint64_t fw_l2_filter_id; 642 #define INVALID_MAC_INDEX ((uint16_t)-1) 643 uint16_t mac_index; 644 645 /* Filter Characteristics */ 646 uint32_t flags; 647 uint32_t enables; 648 uint8_t l2_addr[ETHER_ADDR_LEN]; 649 uint8_t l2_addr_mask[ETHER_ADDR_LEN]; 650 uint16_t l2_ovlan; 651 uint16_t l2_ovlan_mask; 652 uint16_t l2_ivlan; 653 uint16_t l2_ivlan_mask; 654 uint8_t t_l2_addr[ETHER_ADDR_LEN]; 655 uint8_t t_l2_addr_mask[ETHER_ADDR_LEN]; 656 uint16_t t_l2_ovlan; 657 uint16_t t_l2_ovlan_mask; 658 uint16_t t_l2_ivlan; 659 uint16_t t_l2_ivlan_mask; 660 uint8_t tunnel_type; 661 uint16_t mirror_vnic_id; 662 uint32_t vni; 663 uint8_t pri_hint; 664 uint64_t l2_filter_id_hint; 665 }; 666 667 /* Function declarations */ 668 void bnxt_report_link(struct bnxt_softc *softc); 669 bool bnxt_check_hwrm_version(struct bnxt_softc *softc); 670 671 #endif /* _BNXT_H */
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