Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/buslogic/btreg.h
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1 /*- 2 * Generic register and struct definitions for the BusLogic 3 * MultiMaster SCSI host adapters. Product specific probe and 4 * attach routines can be found in: 5 * sys/dev/buslogic/bt_isa.c BT-54X, BT-445 cards 6 * sys/dev/buslogic/bt_mca.c BT-64X, SDC3211B, SDC3211F 7 * sys/dev/buslogic/bt_pci.c BT-946, BT-948, BT-956, BT-958 cards 8 * 9 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 10 * 11 * Copyright (c) 1998, 1999 Justin T. Gibbs. 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions, and the following disclaimer, 19 * without modification, immediately at the beginning of the file. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: releng/12.0/sys/dev/buslogic/btreg.h 326255 2017-11-27 14:52:40Z pfg $ 36 */ 37 38 #ifndef _BTREG_H_ 39 #define _BTREG_H_ 40 41 #include <sys/queue.h> 42 43 #define BT_MAXTRANSFER_SIZE 0xffffffff /* limited by 32bit counter */ 44 #define BT_NSEG 32 /* The number of dma segments supported. 45 * BT_NSEG can be maxed out at 8192 entries, 46 * but the kernel will never need to transfer 47 * such a large request. To reduce the 48 * driver's memory consumption, we reduce the 49 * max to 32. 16 would work if all transfers 50 * are paged alined since the kernel will only 51 * generate at most a 64k transfer, but to 52 * handle non-page aligned transfers, you need 53 * 17, so we round to the next power of two 54 * to make allocating SG space easy and 55 * efficient. 56 */ 57 58 #define ALL_TARGETS (~0) 59 60 /* 61 * Control Register pp. 1-8, 1-9 (Write Only) 62 */ 63 #define CONTROL_REG 0x00 64 #define HARD_RESET 0x80 /* Hard Reset - return to POST state */ 65 #define SOFT_RESET 0x40 /* Soft Reset - Clears Adapter state */ 66 #define RESET_INTR 0x20 /* Reset/Ack Interrupt */ 67 #define RESET_SBUS 0x10 /* Drive SCSI bus reset signal */ 68 69 /* 70 * Status Register pp. 1-9, 1-10 (Read Only) 71 */ 72 #define STATUS_REG 0x00 73 #define DIAG_ACTIVE 0x80 /* Performing Internal Diags */ 74 #define DIAG_FAIL 0x40 /* Internal Diags failed */ 75 #define INIT_REQUIRED 0x20 /* MBOXes need initialization */ 76 #define HA_READY 0x10 /* HA ready for new commands */ 77 #define CMD_REG_BUSY 0x08 /* HA busy with last cmd byte */ 78 #define DATAIN_REG_READY 0x04 /* Data-in Byte available */ 79 #define STATUS_REG_RSVD 0x02 80 #define CMD_INVALID 0x01 /* Invalid Command detected */ 81 82 /* 83 * Command/Parameter Register pp. 1-10, 1-11 (Write Only) 84 */ 85 #define COMMAND_REG 0x01 86 87 /* 88 * Data in Register p. 1-11 (Read Only) 89 */ 90 #define DATAIN_REG 0x01 91 92 /* 93 * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only) 94 */ 95 #define INTSTAT_REG 0x02 96 #define INTR_PENDING 0x80 /* There is a pending INTR */ 97 #define INTSTAT_REG_RSVD 0x70 98 #define SCSI_BUS_RESET 0x08 /* Bus Reset detected */ 99 #define CMD_COMPLETE 0x04 100 #define OMB_READY 0x02 /* Outgoin Mailbox Ready */ 101 #define IMB_LOADED 0x01 /* Incoming Mailbox loaded */ 102 103 /* 104 * Definitions for the "undocumented" geometry register 105 */ 106 typedef enum { 107 GEOM_NODISK, 108 GEOM_64x32, 109 GEOM_128x32, 110 GEOM_255x32 111 } disk_geom_t; 112 113 #define GEOMETRY_REG 0x03 114 #define DISK0_GEOMETRY 0x03 115 #define DISK1_GEOMETRY 0x0c 116 #define EXTENDED_TRANSLATION 0x80 117 #define GEOMETRY_DISK0(g_reg) (greg & DISK0_GEOMETRY) 118 #define GEOMETRY_DISK1(g_reg) ((greg & DISK1_GEOMETRY) >> 2) 119 120 #define BT_NREGS (4) 121 /* 122 * Opcodes for Adapter commands. 123 * pp 1-18 -> 1-20 124 */ 125 typedef enum { 126 BOP_TEST_CMDC_INTR = 0x00, 127 BOP_INITIALIZE_24BMBOX = 0x01, 128 BOP_START_MBOX = 0x02, 129 BOP_EXECUTE_BIOS_CMD = 0x03, 130 BOP_INQUIRE_BOARD_ID = 0x04, 131 BOP_ENABLE_OMBR_INT = 0x05, 132 BOP_SET_SEL_TIMOUT = 0x06, 133 BOP_SET_TIME_ON_BUS = 0x07, 134 BOP_SET_TIME_OFF_BUS = 0x08, 135 BOP_SET_BUS_TRANS_RATE = 0x09, 136 BOP_INQUIRE_INST_LDEVS = 0x0A, 137 BOP_INQUIRE_CONFIG = 0x0B, 138 BOP_ENABLE_TARGET_MODE = 0x0C, 139 BOP_INQUIRE_SETUP_INFO = 0x0D, 140 BOP_WRITE_LRAM = 0x1A, 141 BOP_READ_LRAM = 0x1B, 142 BOP_WRITE_CHIP_FIFO = 0x1C, 143 BOP_READ_CHIP_FIFO = 0x1C, 144 BOP_ECHO_DATA_BYTE = 0x1F, 145 BOP_ADAPTER_DIAGNOSTICS = 0x20, 146 BOP_SET_ADAPTER_OPTIONS = 0x21, 147 BOP_INQUIRE_INST_HDEVS = 0x23, 148 BOP_INQUIRE_TARG_DEVS = 0x24, 149 BOP_DISABLE_HAC_INTR = 0x25, 150 BOP_INITIALIZE_32BMBOX = 0x81, 151 BOP_EXECUTE_SCSI_CMD = 0x83, 152 BOP_INQUIRE_FW_VER_3DIG = 0x84, 153 BOP_INQUIRE_FW_VER_4DIG = 0x85, 154 BOP_INQUIRE_PCI_INFO = 0x86, 155 BOP_INQUIRE_MODEL = 0x8B, 156 BOP_TARG_SYNC_INFO = 0x8C, 157 BOP_INQUIRE_ESETUP_INFO = 0x8D, 158 BOP_ENABLE_STRICT_RR = 0x8F, 159 BOP_STORE_LRAM = 0x90, 160 BOP_FETCH_LRAM = 0x91, 161 BOP_SAVE_TO_EEPROM = 0x92, 162 BOP_UPLOAD_AUTO_SCSI = 0x94, 163 BOP_MODIFY_IO_ADDR = 0x95, 164 BOP_SET_CCB_FORMAT = 0x96, 165 BOP_FLASH_ROM_DOWNLOAD = 0x97, 166 BOP_FLASH_WRITE_ENABLE = 0x98, 167 BOP_WRITE_INQ_BUFFER = 0x9A, 168 BOP_READ_INQ_BUFFER = 0x9B, 169 BOP_FLASH_UP_DOWNLOAD = 0xA7, 170 BOP_READ_SCAM_DATA = 0xA8, 171 BOP_WRITE_SCAM_DATA = 0xA9 172 } bt_op_t; 173 174 /************** Definitions of Multi-byte commands and responses ************/ 175 176 typedef struct { 177 u_int8_t num_mboxes; 178 u_int8_t base_addr[3]; 179 } init_24b_mbox_params_t; 180 181 typedef struct { 182 u_int8_t board_type; 183 #define BOARD_TYPE_NON_MCA 0x41 184 #define BOARD_TYPE_MCA 0x42 185 u_int8_t cust_features; 186 #define FEATURES_STANDARD 0x41 187 u_int8_t firmware_rev_major; 188 u_int8_t firmware_rev_minor; 189 } board_id_data_t; 190 191 typedef struct { 192 u_int8_t enable; 193 } enable_ombr_intr_params_t; 194 195 typedef struct { 196 u_int8_t enable; 197 u_int8_t reserved; 198 u_int8_t timeout[2]; /* timeout in milliseconds */ 199 } set_selto_parmas_t; 200 201 typedef struct { 202 u_int8_t time; /* time in milliseconds (2-15) */ 203 } set_timeon_bus_params_t; 204 205 typedef struct { 206 u_int8_t time; /* time in milliseconds (2-15) */ 207 } set_timeoff_bus_params_t; 208 209 typedef struct { 210 u_int8_t rate; 211 } set_bus_trasfer_rate_params_t; 212 213 typedef struct { 214 u_int8_t targets[8]; 215 } installed_ldevs_data_t; 216 217 typedef struct { 218 u_int8_t dma_chan; 219 #define DMA_CHAN_5 0x20 220 #define DMA_CHAN_6 0x40 221 #define DMA_CHAN_7 0x80 222 u_int8_t irq; 223 #define IRQ_9 0x01 224 #define IRQ_10 0x02 225 #define IRQ_11 0x04 226 #define IRQ_12 0x08 227 #define IRQ_14 0x20 228 #define IRQ_15 0x40 229 u_int8_t scsi_id; 230 } config_data_t; 231 232 typedef struct { 233 u_int8_t enable; 234 } target_mode_params_t; 235 236 typedef struct { 237 u_int8_t offset : 4, 238 period : 3, 239 sync : 1; 240 } targ_syncinfo_t; 241 242 typedef struct { 243 u_int8_t initiate_sync : 1, 244 parity_enable : 1, 245 : 6; 246 247 u_int8_t bus_transfer_rate; 248 u_int8_t time_on_bus; 249 u_int8_t time_off_bus; 250 u_int8_t num_mboxes; 251 u_int8_t mbox_base_addr[3]; 252 targ_syncinfo_t low_syncinfo[8]; /* For fast and ultra, use 8C */ 253 u_int8_t low_discinfo; 254 u_int8_t customer_sig; 255 u_int8_t letter_d; 256 u_int8_t ha_type; 257 u_int8_t low_wide_allowed; 258 u_int8_t low_wide_active; 259 targ_syncinfo_t high_syncinfo[8]; 260 u_int8_t high_discinfo; 261 u_int8_t high_wide_allowed; 262 u_int8_t high_wide_active; 263 } setup_data_t; 264 265 typedef struct { 266 u_int8_t phys_addr[3]; 267 } write_adapter_lram_params_t; 268 269 typedef struct { 270 u_int8_t phys_addr[3]; 271 } read_adapter_lram_params_t; 272 273 typedef struct { 274 u_int8_t phys_addr[3]; 275 } write_chip_fifo_params_t; 276 277 typedef struct { 278 u_int8_t phys_addr[3]; 279 } read_chip_fifo_params_t; 280 281 typedef struct { 282 u_int8_t length; /* Excludes this member */ 283 u_int8_t low_disc_disable; 284 u_int8_t low_busy_retry_disable; 285 u_int8_t high_disc_disable; 286 u_int8_t high_busy_retry_disable; 287 } set_adapter_options_params_t; 288 289 typedef struct { 290 u_int8_t targets[8]; 291 } installed_hdevs_data_t; 292 293 typedef struct { 294 u_int8_t low_devs; 295 u_int8_t high_devs; 296 } target_devs_data_t; 297 298 typedef struct { 299 u_int8_t enable; 300 } enable_hac_interrupt_params_t; 301 302 typedef struct { 303 u_int8_t num_boxes; 304 u_int8_t base_addr[4]; 305 } init_32b_mbox_params_t; 306 307 typedef u_int8_t fw_ver_3dig_data_t; 308 309 typedef u_int8_t fw_ver_4dig_data_t; 310 311 typedef struct { 312 u_int8_t offset; 313 u_int8_t response_len; 314 } fetch_lram_params_t; 315 316 #define AUTO_SCSI_BYTE_OFFSET 64 317 typedef struct { 318 u_int8_t factory_sig[2]; 319 u_int8_t auto_scsi_data_size; /* 2 -> 64 bytes */ 320 u_int8_t model_num[6]; 321 u_int8_t adapter_ioport; 322 u_int8_t floppy_enabled :1, 323 floppy_secondary :1, 324 level_trigger :1, 325 :2, 326 system_ram_area :3; 327 u_int8_t dma_channel :7, 328 dma_autoconf :1; 329 u_int8_t irq_channel :7, 330 irq_autoconf :1; 331 u_int8_t dma_trans_rate; 332 u_int8_t scsi_id; 333 u_int8_t low_termination :1, 334 scsi_parity :1, 335 high_termination :1, 336 req_ack_filter :1, 337 fast_sync :1, 338 bus_reset :1, 339 :1, 340 active_negation :1; 341 u_int8_t bus_on_delay; 342 u_int8_t bus_off_delay; 343 u_int8_t bios_enabled :1, 344 int19h_redirect :1, 345 extended_trans :1, 346 removable_drives :1, 347 :1, 348 morethan2disks :1, 349 interrupt_mode :1, 350 floptical_support:1; 351 u_int8_t low_device_enabled; 352 u_int8_t high_device_enabled; 353 u_int8_t low_wide_permitted; 354 u_int8_t high_wide_permitted; 355 u_int8_t low_fast_permitted; 356 u_int8_t high_fast_permitted; 357 u_int8_t low_sync_permitted; 358 u_int8_t high_sync_permitted; 359 u_int8_t low_disc_permitted; 360 u_int8_t high_disc_permitted; 361 u_int8_t low_send_start_unit; 362 u_int8_t high_send_start_unit; 363 u_int8_t low_ignore_in_bios_scan; 364 u_int8_t high_ignore_in_bios_scan; 365 u_int8_t pci_int_pin :2, 366 host_ioport :2, 367 round_robin :1, 368 vesa_bus_over_33 :1, 369 vesa_burst_write :1, 370 vesa_burst_read :1; 371 u_int8_t low_ultra_permitted; 372 u_int8_t high_ultra_permitted; 373 u_int8_t reserved[5]; 374 u_int8_t auto_scsi_max_lun; 375 u_int8_t :1, 376 scam_dominant :1, 377 scam_enabled :1, 378 scam_level2 :1, 379 :4; 380 u_int8_t int13_extensions :1, 381 :1, 382 cdrom_boot :1, 383 :2, 384 multi_boot :1, 385 :2; 386 u_int8_t boot_target_id :4, 387 boot_channel :4; 388 u_int8_t force_dev_scan :1, 389 :7; 390 u_int8_t low_tagged_lun_independance; 391 u_int8_t high_tagged_lun_independance; 392 u_int8_t low_renegotiate_after_cc; 393 u_int8_t high_renegotiate_after_cc; 394 u_int8_t reserverd2[10]; 395 u_int8_t manufacturing_diagnotic[2]; 396 u_int8_t checksum[2]; 397 } auto_scsi_data_t; 398 399 struct bt_isa_port { 400 u_int16_t addr; 401 u_int8_t probed; 402 u_int8_t bio; 403 }; 404 405 extern struct bt_isa_port bt_isa_ports[]; 406 407 #define BT_NUM_ISAPORTS 6 408 409 typedef enum { 410 BIO_330 = 0, 411 BIO_334 = 1, 412 BIO_230 = 2, 413 BIO_234 = 3, 414 BIO_130 = 4, 415 BIO_134 = 5, 416 BIO_DISABLED = 6, 417 BIO_DISABLED2 = 7 418 } isa_compat_io_t; 419 420 typedef struct { 421 u_int8_t io_port; 422 u_int8_t irq_num; 423 u_int8_t low_byte_term :1, 424 high_byte_term :1, 425 :2, 426 jp1_status :1, 427 jp2_status :1, 428 jp3_status :1, 429 :1; 430 u_int8_t reserved; 431 } pci_info_data_t; 432 433 typedef struct { 434 u_int8_t ascii_model[5]; /* Fifth byte is always 0 */ 435 } ha_model_data_t; 436 437 typedef struct { 438 u_int8_t sync_rate[16]; /* Sync in 10ns units */ 439 } target_sync_info_data_t; 440 441 typedef struct { 442 u_int8_t bus_type; 443 u_int8_t bios_addr; 444 u_int16_t max_sg; 445 u_int8_t num_mboxes; 446 u_int8_t mbox_base[4]; 447 u_int8_t :2, 448 sync_neg10MB :1, 449 floppy_disable :1, 450 floppy_secondary_port :1, 451 burst_mode_enabled :1, 452 level_trigger_ints :1, 453 :1; 454 u_int8_t fw_ver_bytes_2_to_4[3]; 455 u_int8_t wide_bus :1, 456 diff_bus :1, 457 scam_capable :1, 458 ultra_scsi :1, 459 auto_term :1, 460 :3; 461 } esetup_info_data_t; 462 463 typedef struct { 464 u_int32_t len; 465 u_int32_t addr; 466 } bt_sg_t; 467 468 /********************** Mail Box definitions *******************************/ 469 470 typedef enum { 471 BMBO_FREE = 0x0, /* MBO intry is free */ 472 BMBO_START = 0x1, /* MBO activate entry */ 473 BMBO_ABORT = 0x2 /* MBO abort entry */ 474 } bt_mbo_action_code_t; 475 476 typedef struct bt_mbox_out { 477 u_int32_t ccb_addr; 478 u_int8_t reserved[3]; 479 u_int8_t action_code; 480 } bt_mbox_out_t; 481 482 typedef enum { 483 BMBI_FREE = 0x0, /* MBI entry is free */ 484 BMBI_OK = 0x1, /* completed without error */ 485 BMBI_ABORT = 0x2, /* aborted ccb */ 486 BMBI_NOT_FOUND = 0x3, /* Tried to abort invalid CCB */ 487 BMBI_ERROR = 0x4 /* Completed with error */ 488 } bt_mbi_comp_code_t; 489 490 typedef struct bt_mbox_in { 491 u_int32_t ccb_addr; 492 u_int8_t btstat; 493 u_int8_t sdstat; 494 u_int8_t reserved; 495 u_int8_t comp_code; 496 } bt_mbox_in_t; 497 498 /***************** Compiled Probe Information *******************************/ 499 struct bt_probe_info { 500 int drq; 501 int irq; 502 }; 503 504 /****************** Hardware CCB definition *********************************/ 505 typedef enum { 506 INITIATOR_CCB = 0x00, 507 INITIATOR_SG_CCB = 0x02, 508 INITIATOR_CCB_WRESID = 0x03, 509 INITIATOR_SG_CCB_WRESID = 0x04, 510 INITIATOR_BUS_DEV_RESET = 0x81 511 } bt_ccb_opcode_t; 512 513 typedef enum { 514 BTSTAT_NOERROR = 0x00, 515 BTSTAT_LINKED_CMD_COMPLETE = 0x0A, 516 BTSTAT_LINKED_CMD_FLAG_COMPLETE = 0x0B, 517 BTSTAT_DATAUNDERUN_ERROR = 0x0C, 518 BTSTAT_SELTIMEOUT = 0x11, 519 BTSTAT_DATARUN_ERROR = 0x12, 520 BTSTAT_UNEXPECTED_BUSFREE = 0x13, 521 BTSTAT_INVALID_PHASE = 0x14, 522 BTSTAT_INVALID_ACTION_CODE = 0x15, 523 BTSTAT_INVALID_OPCODE = 0x16, 524 BTSTAT_LINKED_CCB_LUN_MISMATCH = 0x17, 525 BTSTAT_INVALID_CCB_OR_SG_PARAM = 0x1A, 526 BTSTAT_AUTOSENSE_FAILED = 0x1B, 527 BTSTAT_TAGGED_MSG_REJECTED = 0x1C, 528 BTSTAT_UNSUPPORTED_MSG_RECEIVED = 0x1D, 529 BTSTAT_HARDWARE_FAILURE = 0x20, 530 BTSTAT_TARGET_IGNORED_ATN = 0x21, 531 BTSTAT_HA_SCSI_BUS_RESET = 0x22, 532 BTSTAT_OTHER_SCSI_BUS_RESET = 0x23, 533 BTSTAT_INVALID_RECONNECT = 0x24, 534 BTSTAT_HA_BDR = 0x25, 535 BTSTAT_ABORT_QUEUE_GENERATED = 0x26, 536 BTSTAT_HA_SOFTWARE_ERROR = 0x27, 537 BTSTAT_HA_WATCHDOG_ERROR = 0x28, 538 BTSTAT_SCSI_PERROR_DETECTED = 0x30 539 } btstat_t; 540 541 struct bt_hccb { 542 u_int8_t opcode; 543 u_int8_t :3, 544 datain :1, 545 dataout :1, 546 wide_tag_enable :1, /* Wide Lun CCB format */ 547 wide_tag_type :2; /* Wide Lun CCB format */ 548 u_int8_t cmd_len; 549 u_int8_t sense_len; 550 int32_t data_len; /* residuals can be negative */ 551 u_int32_t data_addr; 552 u_int8_t reserved[2]; 553 u_int8_t btstat; 554 u_int8_t sdstat; 555 u_int8_t target_id; 556 u_int8_t target_lun :5, 557 tag_enable :1, 558 tag_type :2; 559 u_int8_t scsi_cdb[12]; 560 u_int8_t reserved2[6]; 561 u_int32_t sense_addr; 562 }; 563 564 typedef enum { 565 BCCB_FREE = 0x0, 566 BCCB_ACTIVE = 0x1, 567 BCCB_DEVICE_RESET = 0x2, 568 BCCB_RELEASE_SIMQ = 0x4 569 } bccb_flags_t; 570 571 struct bt_ccb { 572 struct bt_hccb hccb; 573 SLIST_ENTRY(bt_ccb) links; 574 u_int32_t flags; 575 union ccb *ccb; 576 bus_dmamap_t dmamap; 577 struct callout timer; 578 bt_sg_t *sg_list; 579 u_int32_t sg_list_phys; 580 }; 581 582 struct sg_map_node { 583 bus_dmamap_t sg_dmamap; 584 bus_addr_t sg_physaddr; 585 bt_sg_t* sg_vaddr; 586 SLIST_ENTRY(sg_map_node) links; 587 }; 588 589 struct bt_softc { 590 device_t dev; 591 struct resource *port; 592 struct resource *irq; 593 struct resource *drq; 594 void *ih; 595 struct mtx lock; 596 struct cam_sim *sim; 597 struct cam_path *path; 598 bt_mbox_out_t *cur_outbox; 599 bt_mbox_in_t *cur_inbox; 600 bt_mbox_out_t *last_outbox; 601 bt_mbox_in_t *last_inbox; 602 struct bt_ccb *bt_ccb_array; 603 SLIST_HEAD(,bt_ccb) free_bt_ccbs; 604 LIST_HEAD(,ccb_hdr) pending_ccbs; 605 u_int active_ccbs; 606 u_int32_t bt_ccb_physbase; 607 bt_mbox_in_t *in_boxes; 608 bt_mbox_out_t *out_boxes; 609 struct scsi_sense_data *sense_buffers; 610 u_int32_t sense_buffers_physbase; 611 struct bt_ccb *recovery_bccb; 612 u_int num_boxes; 613 bus_dma_tag_t parent_dmat; /* 614 * All dmat's derive from 615 * the dmat defined by our 616 * bus. 617 */ 618 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 619 bus_dma_tag_t mailbox_dmat; /* dmat for our mailboxes */ 620 bus_dmamap_t mailbox_dmamap; 621 bus_dma_tag_t ccb_dmat; /* dmat for our ccb array */ 622 bus_dmamap_t ccb_dmamap; 623 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 624 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 625 bus_dmamap_t sense_dmamap; 626 SLIST_HEAD(, sg_map_node) sg_maps; 627 bus_addr_t mailbox_physbase; 628 bus_addr_t mailbox_addrlimit; 629 u_int num_ccbs; /* Number of CCBs malloc'd */ 630 u_int max_ccbs; /* Maximum allocatable CCBs */ 631 u_int max_sg; 632 u_int scsi_id; 633 u_int32_t extended_trans :1, 634 wide_bus :1, 635 diff_bus :1, 636 ultra_scsi :1, 637 extended_lun :1, 638 strict_rr :1, 639 tag_capable :1, 640 wide_lun_ccb :1, 641 resource_shortage :1, 642 level_trigger_ints:1, 643 :22; 644 u_int16_t tags_permitted; 645 u_int16_t disc_permitted; 646 u_int16_t sync_permitted; 647 u_int16_t fast_permitted; 648 u_int16_t ultra_permitted; 649 u_int16_t wide_permitted; 650 u_int8_t init_level; 651 volatile u_int8_t command_cmp; 652 volatile u_int8_t latched_status; 653 u_int32_t bios_addr; 654 char firmware_ver[6]; 655 char model[5]; 656 }; 657 658 #define BT_TEMP_UNIT 0xFF /* Unit for probes */ 659 void bt_init_softc(device_t dev, 660 struct resource *port, 661 struct resource *irq, 662 struct resource *drq); 663 void bt_free_softc(device_t dev); 664 int bt_port_probe(device_t dev, 665 struct bt_probe_info *info); 666 int bt_probe(device_t dev); 667 int bt_fetch_adapter_info(device_t dev); 668 int bt_init(device_t dev); 669 int bt_attach(device_t dev); 670 void bt_intr(void *arg); 671 int bt_check_probed_iop(u_int ioport); 672 void bt_mark_probed_bio(isa_compat_io_t port); 673 void bt_mark_probed_iop(u_int ioport); 674 void bt_find_probe_range(int ioport, 675 int *port_index, 676 int *max_port_index); 677 678 int bt_iop_from_bio(isa_compat_io_t bio_index); 679 680 #define DEFAULT_CMD_TIMEOUT 100000 /* 10 sec */ 681 int bt_cmd(struct bt_softc *bt, bt_op_t opcode, 682 u_int8_t *params, u_int param_len, 683 u_int8_t *reply_data, u_int reply_len, 684 u_int cmd_timeout); 685 686 #define bt_name(bt) device_get_nameunit(bt->dev) 687 688 #define bt_inb(bt, reg) \ 689 bus_read_1((bt)->port, reg) 690 691 #define bt_outb(bt, reg, value) \ 692 bus_write_1((bt)->port, reg, value) 693 694 #endif /* _BT_H_ */
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