1 /*
2 * Generic register and struct definitions for the BusLogic
3 * MultiMaster SCSI host adapters. Product specific probe and
4 * attach routines can be found in:
5 * i386/isa/bt_isa.c BT-54X, BT-445 cards
6 * i386/eisa/bt_eisa.c BT-74x, BT-75x cards
7 * pci/bt_pci.c BT-946, BT-948, BT-956, BT-958 cards
8 *
9 * Copyright (c) 1998, 1999 Justin T. Gibbs.
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions, and the following disclaimer,
17 * without modification, immediately at the beginning of the file.
18 * 2. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD$
34 */
35
36 #ifndef _BTREG_H_
37 #define _BTREG_H_
38
39 #include "bt.h"
40
41 #include <sys/queue.h>
42
43 #define BT_MAXTRANSFER_SIZE 0xffffffff /* limited by 32bit counter */
44 #define BT_NSEG 32 /* The number of dma segments supported.
45 * BT_NSEG can be maxed out at 8192 entries,
46 * but the kernel will never need to transfer
47 * such a large request. To reduce the
48 * driver's memory consumption, we reduce the
49 * max to 32. 16 would work if all transfers
50 * are paged alined since the kernel will only
51 * generate at most a 64k transfer, but to
52 * handle non-page aligned transfers, you need
53 * 17, so we round to the next power of two
54 * to make allocating SG space easy and
55 * efficient.
56 */
57
58 #define ALL_TARGETS (~0)
59
60 /*
61 * Control Register pp. 1-8, 1-9 (Write Only)
62 */
63 #define CONTROL_REG 0x00
64 #define HARD_RESET 0x80 /* Hard Reset - return to POST state */
65 #define SOFT_RESET 0x40 /* Soft Reset - Clears Adapter state */
66 #define RESET_INTR 0x20 /* Reset/Ack Interrupt */
67 #define RESET_SBUS 0x10 /* Drive SCSI bus reset signal */
68
69 /*
70 * Status Register pp. 1-9, 1-10 (Read Only)
71 */
72 #define STATUS_REG 0x00
73 #define DIAG_ACTIVE 0x80 /* Performing Internal Diags */
74 #define DIAG_FAIL 0x40 /* Internal Diags failed */
75 #define INIT_REQUIRED 0x20 /* MBOXes need initialization */
76 #define HA_READY 0x10 /* HA ready for new commands */
77 #define CMD_REG_BUSY 0x08 /* HA busy with last cmd byte */
78 #define DATAIN_REG_READY 0x04 /* Data-in Byte available */
79 #define STATUS_REG_RSVD 0x02
80 #define CMD_INVALID 0x01 /* Invalid Command detected */
81
82 /*
83 * Command/Parameter Register pp. 1-10, 1-11 (Write Only)
84 */
85 #define COMMAND_REG 0x01
86
87 /*
88 * Data in Register p. 1-11 (Read Only)
89 */
90 #define DATAIN_REG 0x01
91
92 /*
93 * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only)
94 */
95 #define INTSTAT_REG 0x02
96 #define INTR_PENDING 0x80 /* There is a pending INTR */
97 #define INTSTAT_REG_RSVD 0x70
98 #define SCSI_BUS_RESET 0x08 /* Bus Reset detected */
99 #define CMD_COMPLETE 0x04
100 #define OMB_READY 0x02 /* Outgoin Mailbox Ready */
101 #define IMB_LOADED 0x01 /* Incoming Mailbox loaded */
102
103 /*
104 * Definitions for the "undocumented" geometry register
105 */
106 typedef enum {
107 GEOM_NODISK,
108 GEOM_64x32,
109 GEOM_128x32,
110 GEOM_255x32
111 } disk_geom_t;
112
113 #define GEOMETRY_REG 0x03
114 #define DISK0_GEOMETRY 0x03
115 #define DISK1_GEOMETRY 0x0c
116 #define EXTENDED_TRANSLATION 0x10
117 #define GEOMETRY_DISK0(g_reg) (greg & DISK0_GEOMETRY)
118 #define GEOMETRY_DISK1(g_reg) ((greg & DISK1_GEOMETRY) >> 2)
119
120 #define BT_NREGS (4)
121 /*
122 * Opcodes for Adapter commands.
123 * pp 1-18 -> 1-20
124 */
125 typedef enum {
126 BOP_TEST_CMDC_INTR = 0x00,
127 BOP_INITIALIZE_24BMBOX = 0x01,
128 BOP_START_MBOX = 0x02,
129 BOP_EXECUTE_BIOS_CMD = 0x03,
130 BOP_INQUIRE_BOARD_ID = 0x04,
131 BOP_ENABLE_OMBR_INT = 0x05,
132 BOP_SET_SEL_TIMOUT = 0x06,
133 BOP_SET_TIME_ON_BUS = 0x07,
134 BOP_SET_TIME_OFF_BUS = 0x08,
135 BOP_SET_BUS_TRANS_RATE = 0x09,
136 BOP_INQUIRE_INST_LDEVS = 0x0A,
137 BOP_INQUIRE_CONFIG = 0x0B,
138 BOP_ENABLE_TARGET_MODE = 0x0C,
139 BOP_INQUIRE_SETUP_INFO = 0x0D,
140 BOP_WRITE_LRAM = 0x1A,
141 BOP_READ_LRAM = 0x1B,
142 BOP_WRITE_CHIP_FIFO = 0x1C,
143 BOP_READ_CHIP_FIFO = 0x1C,
144 BOP_ECHO_DATA_BYTE = 0x1F,
145 BOP_ADAPTER_DIAGNOSTICS = 0x20,
146 BOP_SET_ADAPTER_OPTIONS = 0x21,
147 BOP_INQUIRE_INST_HDEVS = 0x23,
148 BOP_INQUIRE_TARG_DEVS = 0x24,
149 BOP_DISABLE_HAC_INTR = 0x25,
150 BOP_INITIALIZE_32BMBOX = 0x81,
151 BOP_EXECUTE_SCSI_CMD = 0x83,
152 BOP_INQUIRE_FW_VER_3DIG = 0x84,
153 BOP_INQUIRE_FW_VER_4DIG = 0x85,
154 BOP_INQUIRE_PCI_INFO = 0x86,
155 BOP_INQUIRE_MODEL = 0x8B,
156 BOP_TARG_SYNC_INFO = 0x8C,
157 BOP_INQUIRE_ESETUP_INFO = 0x8D,
158 BOP_ENABLE_STRICT_RR = 0x8F,
159 BOP_STORE_LRAM = 0x90,
160 BOP_FETCH_LRAM = 0x91,
161 BOP_SAVE_TO_EEPROM = 0x92,
162 BOP_UPLOAD_AUTO_SCSI = 0x94,
163 BOP_MODIFY_IO_ADDR = 0x95,
164 BOP_SET_CCB_FORMAT = 0x96,
165 BOP_FLASH_ROM_DOWNLOAD = 0x97,
166 BOP_FLASH_WRITE_ENABLE = 0x98,
167 BOP_WRITE_INQ_BUFFER = 0x9A,
168 BOP_READ_INQ_BUFFER = 0x9B,
169 BOP_FLASH_UP_DOWNLOAD = 0xA7,
170 BOP_READ_SCAM_DATA = 0xA8,
171 BOP_WRITE_SCAM_DATA = 0xA9
172 } bt_op_t;
173
174 /************** Definitions of Multi-byte commands and responses ************/
175
176 typedef struct {
177 u_int8_t num_mboxes;
178 u_int8_t base_addr[3];
179 } init_24b_mbox_params_t;
180
181 typedef struct {
182 u_int8_t board_type;
183 #define BOARD_TYPE_NON_MCA 0x41
184 #define BOARD_TYPE_MCA 0x42
185 u_int8_t cust_features;
186 #define FEATURES_STANDARD 0x41
187 u_int8_t firmware_rev_major;
188 u_int8_t firmware_rev_minor;
189 } board_id_data_t;
190
191 typedef struct {
192 u_int8_t enable;
193 } enable_ombr_intr_params_t;
194
195 typedef struct {
196 u_int8_t enable;
197 u_int8_t reserved;
198 u_int8_t timeout[2]; /* timeout in milliseconds */
199 } set_selto_parmas_t;
200
201 typedef struct {
202 u_int8_t time; /* time in milliseconds (2-15) */
203 } set_timeon_bus_params_t;
204
205 typedef struct {
206 u_int8_t time; /* time in milliseconds (2-15) */
207 } set_timeoff_bus_params_t;
208
209 typedef struct {
210 u_int8_t rate;
211 } set_bus_trasfer_rate_params_t;
212
213 typedef struct {
214 u_int8_t targets[8];
215 } installed_ldevs_data_t;
216
217 typedef struct {
218 u_int8_t dma_chan;
219 #define DMA_CHAN_5 0x20
220 #define DMA_CHAN_6 0x40
221 #define DMA_CHAN_7 0x80
222 u_int8_t irq;
223 #define IRQ_9 0x01
224 #define IRQ_10 0x02
225 #define IRQ_11 0x04
226 #define IRQ_12 0x08
227 #define IRQ_14 0x20
228 #define IRQ_15 0x40
229 u_int8_t scsi_id;
230 } config_data_t;
231
232 typedef struct {
233 u_int8_t enable;
234 } target_mode_params_t;
235
236 typedef struct {
237 u_int8_t offset : 4,
238 period : 3,
239 sync : 1;
240 } targ_syncinfo_t;
241
242 typedef enum {
243 HAB_ISA = 'A',
244 HAB_MCA = 'B',
245 HAB_EISA = 'C',
246 HAB_NUBUS = 'D',
247 HAB_VESA = 'E',
248 HAB_PCI = 'F'
249 } ha_type_t;
250
251 typedef struct {
252 u_int8_t initiate_sync : 1,
253 parity_enable : 1,
254 : 6;
255
256 u_int8_t bus_transfer_rate;
257 u_int8_t time_on_bus;
258 u_int8_t time_off_bus;
259 u_int8_t num_mboxes;
260 u_int8_t mbox_base_addr[3];
261 targ_syncinfo_t low_syncinfo[8]; /* For fast and ultra, use 8C */
262 u_int8_t low_discinfo;
263 u_int8_t customer_sig;
264 u_int8_t letter_d;
265 u_int8_t ha_type;
266 u_int8_t low_wide_allowed;
267 u_int8_t low_wide_active;
268 targ_syncinfo_t high_syncinfo[8];
269 u_int8_t high_discinfo;
270 u_int8_t high_wide_allowed;
271 u_int8_t high_wide_active;
272 } setup_data_t;
273
274 typedef struct {
275 u_int8_t phys_addr[3];
276 } write_adapter_lram_params_t;
277
278 typedef struct {
279 u_int8_t phys_addr[3];
280 } read_adapter_lram_params_t;
281
282 typedef struct {
283 u_int8_t phys_addr[3];
284 } write_chip_fifo_params_t;
285
286 typedef struct {
287 u_int8_t phys_addr[3];
288 } read_chip_fifo_params_t;
289
290 typedef struct {
291 u_int8_t length; /* Excludes this member */
292 u_int8_t low_disc_disable;
293 u_int8_t low_busy_retry_disable;
294 u_int8_t high_disc_disable;
295 u_int8_t high_busy_retry_disable;
296 } set_adapter_options_params_t;
297
298 typedef struct {
299 u_int8_t targets[8];
300 } installed_hdevs_data_t;
301
302 typedef struct {
303 u_int8_t low_devs;
304 u_int8_t high_devs;
305 } target_devs_data_t;
306
307 typedef struct {
308 u_int8_t enable;
309 } enable_hac_interrupt_params_t;
310
311 typedef struct {
312 u_int8_t num_boxes;
313 u_int8_t base_addr[4];
314 } init_32b_mbox_params_t;
315
316 typedef u_int8_t fw_ver_3dig_data_t;
317
318 typedef u_int8_t fw_ver_4dig_data_t;
319
320 typedef struct {
321 u_int8_t offset;
322 u_int8_t response_len;
323 } fetch_lram_params_t;
324
325 #define AUTO_SCSI_BYTE_OFFSET 64
326 typedef struct {
327 u_int8_t factory_sig[2];
328 u_int8_t auto_scsi_data_size; /* 2 -> 64 bytes */
329 u_int8_t model_num[6];
330 u_int8_t adapter_ioport;
331 u_int8_t floppy_enabled :1,
332 floppy_secondary :1,
333 level_trigger :1,
334 :2,
335 system_ram_area :3;
336 u_int8_t dma_channel :7,
337 dma_autoconf :1;
338 u_int8_t irq_channel :7,
339 irq_autoconf :1;
340 u_int8_t dma_trans_rate;
341 u_int8_t scsi_id;
342 u_int8_t low_termination :1,
343 scsi_parity :1,
344 high_termination :1,
345 req_ack_filter :1,
346 fast_sync :1,
347 bus_reset :1,
348 :1,
349 active_negation :1;
350 u_int8_t bus_on_delay;
351 u_int8_t bus_off_delay;
352 u_int8_t bios_enabled :1,
353 int19h_redirect :1,
354 extended_trans :1,
355 removable_drives :1,
356 :1,
357 morethan2disks :1,
358 interrupt_mode :1,
359 floptical_support:1;
360 u_int8_t low_device_enabled;
361 u_int8_t high_device_enabled;
362 u_int8_t low_wide_permitted;
363 u_int8_t high_wide_permitted;
364 u_int8_t low_fast_permitted;
365 u_int8_t high_fast_permitted;
366 u_int8_t low_sync_permitted;
367 u_int8_t high_sync_permitted;
368 u_int8_t low_disc_permitted;
369 u_int8_t high_disc_permitted;
370 u_int8_t low_send_start_unit;
371 u_int8_t high_send_start_unit;
372 u_int8_t low_ignore_in_bios_scan;
373 u_int8_t high_ignore_in_bios_scan;
374 u_int8_t pci_int_pin :2,
375 host_ioport :2,
376 round_robin :1,
377 vesa_bus_over_33 :1,
378 vesa_burst_write :1,
379 vesa_burst_read :1;
380 u_int8_t low_ultra_permitted;
381 u_int8_t high_ultra_permitted;
382 u_int8_t reserved[5];
383 u_int8_t auto_scsi_max_lun;
384 u_int8_t :1,
385 scam_dominant :1,
386 scam_enabled :1,
387 scam_level2 :1,
388 :4;
389 u_int8_t int13_extensions :1,
390 :1,
391 cdrom_boot :1,
392 :2,
393 multi_boot :1,
394 :2;
395 u_int8_t boot_target_id :4,
396 boot_channel :4;
397 u_int8_t force_dev_scan :1,
398 :7;
399 u_int8_t low_tagged_lun_independance;
400 u_int8_t high_tagged_lun_independance;
401 u_int8_t low_renegotiate_after_cc;
402 u_int8_t high_renegotiate_after_cc;
403 u_int8_t reserverd2[10];
404 u_int8_t manufacturing_diagnotic[2];
405 u_int8_t checksum[2];
406 } auto_scsi_data_t;
407
408 struct bt_isa_port {
409 u_int16_t addr;
410 u_int8_t probed;
411 u_int8_t bio;
412 };
413
414 extern struct bt_isa_port bt_isa_ports[];
415
416 #define BT_NUM_ISAPORTS 6
417
418 typedef enum {
419 BIO_330 = 0,
420 BIO_334 = 1,
421 BIO_230 = 2,
422 BIO_234 = 3,
423 BIO_130 = 4,
424 BIO_134 = 5,
425 BIO_DISABLED = 6,
426 BIO_DISABLED2 = 7
427 } isa_compat_io_t;
428
429 typedef struct {
430 u_int8_t io_port;
431 u_int8_t irq_num;
432 u_int8_t low_byte_term :1,
433 high_byte_term :1,
434 :2,
435 jp1_status :1,
436 jp2_status :1,
437 jp3_status :1,
438 :1;
439 u_int8_t reserved;
440 } pci_info_data_t;
441
442 typedef struct {
443 u_int8_t ascii_model[5]; /* Fifth byte is always 0 */
444 } ha_model_data_t;
445
446 typedef struct {
447 u_int8_t sync_rate[16]; /* Sync in 10ns units */
448 } target_sync_info_data_t;
449
450 typedef struct {
451 u_int8_t bus_type;
452 u_int8_t bios_addr;
453 u_int16_t max_sg;
454 u_int8_t num_mboxes;
455 u_int8_t mbox_base[4];
456 u_int8_t :2,
457 sync_neg10MB :1,
458 floppy_disable :1,
459 floppy_secondary_port :1,
460 burst_mode_enabled :1,
461 level_trigger_ints :1,
462 :1;
463 u_int8_t fw_ver_bytes_2_to_4[3];
464 u_int8_t wide_bus :1,
465 diff_bus :1,
466 scam_capable :1,
467 ultra_scsi :1,
468 auto_term :1,
469 :3;
470 } esetup_info_data_t;
471
472 typedef struct {
473 u_int32_t len;
474 u_int32_t addr;
475 } bt_sg_t;
476
477 /********************** Mail Box definitions *******************************/
478
479 typedef enum {
480 BMBO_FREE = 0x0, /* MBO intry is free */
481 BMBO_START = 0x1, /* MBO activate entry */
482 BMBO_ABORT = 0x2 /* MBO abort entry */
483 } bt_mbo_action_code_t;
484
485 typedef struct bt_mbox_out {
486 u_int32_t ccb_addr;
487 u_int8_t reserved[3];
488 u_int8_t action_code;
489 } bt_mbox_out_t;
490
491 typedef enum {
492 BMBI_FREE = 0x0, /* MBI entry is free */
493 BMBI_OK = 0x1, /* completed without error */
494 BMBI_ABORT = 0x2, /* aborted ccb */
495 BMBI_NOT_FOUND = 0x3, /* Tried to abort invalid CCB */
496 BMBI_ERROR = 0x4 /* Completed with error */
497 } bt_mbi_comp_code_t;
498
499 typedef struct bt_mbox_in {
500 u_int32_t ccb_addr;
501 u_int8_t btstat;
502 u_int8_t sdstat;
503 u_int8_t reserved;
504 u_int8_t comp_code;
505 } bt_mbox_in_t;
506
507 /***************** Compiled Probe Information *******************************/
508 struct bt_probe_info {
509 int drq;
510 int irq;
511 };
512
513 /****************** Hardware CCB definition *********************************/
514 typedef enum {
515 INITIATOR_CCB = 0x00,
516 INITIATOR_SG_CCB = 0x02,
517 INITIATOR_CCB_WRESID = 0x03,
518 INITIATOR_SG_CCB_WRESID = 0x04,
519 INITIATOR_BUS_DEV_RESET = 0x81
520 } bt_ccb_opcode_t;
521
522 typedef enum {
523 BTSTAT_NOERROR = 0x00,
524 BTSTAT_LINKED_CMD_COMPLETE = 0x0A,
525 BTSTAT_LINKED_CMD_FLAG_COMPLETE = 0x0B,
526 BTSTAT_DATAUNDERUN_ERROR = 0x0C,
527 BTSTAT_SELTIMEOUT = 0x11,
528 BTSTAT_DATARUN_ERROR = 0x12,
529 BTSTAT_UNEXPECTED_BUSFREE = 0x13,
530 BTSTAT_INVALID_PHASE = 0x14,
531 BTSTAT_INVALID_ACTION_CODE = 0x15,
532 BTSTAT_INVALID_OPCODE = 0x16,
533 BTSTAT_LINKED_CCB_LUN_MISMATCH = 0x17,
534 BTSTAT_INVALID_CCB_OR_SG_PARAM = 0x1A,
535 BTSTAT_AUTOSENSE_FAILED = 0x1B,
536 BTSTAT_TAGGED_MSG_REJECTED = 0x1C,
537 BTSTAT_UNSUPPORTED_MSG_RECEIVED = 0x1D,
538 BTSTAT_HARDWARE_FAILURE = 0x20,
539 BTSTAT_TARGET_IGNORED_ATN = 0x21,
540 BTSTAT_HA_SCSI_BUS_RESET = 0x22,
541 BTSTAT_OTHER_SCSI_BUS_RESET = 0x23,
542 BTSTAT_INVALID_RECONNECT = 0x24,
543 BTSTAT_HA_BDR = 0x25,
544 BTSTAT_ABORT_QUEUE_GENERATED = 0x26,
545 BTSTAT_HA_SOFTWARE_ERROR = 0x27,
546 BTSTAT_HA_WATCHDOG_ERROR = 0x28,
547 BTSTAT_SCSI_PERROR_DETECTED = 0x30
548 } btstat_t;
549
550 struct bt_hccb {
551 u_int8_t opcode;
552 u_int8_t :3,
553 datain :1,
554 dataout :1,
555 wide_tag_enable :1, /* Wide Lun CCB format */
556 wide_tag_type :2; /* Wide Lun CCB format */
557 u_int8_t cmd_len;
558 u_int8_t sense_len;
559 int32_t data_len; /* residuals can be negative */
560 u_int32_t data_addr;
561 u_int8_t reserved[2];
562 u_int8_t btstat;
563 u_int8_t sdstat;
564 u_int8_t target_id;
565 u_int8_t target_lun :5,
566 tag_enable :1,
567 tag_type :2;
568 u_int8_t scsi_cdb[12];
569 u_int8_t reserved2[6];
570 u_int32_t sense_addr;
571 };
572
573 typedef enum {
574 BCCB_FREE = 0x0,
575 BCCB_ACTIVE = 0x1,
576 BCCB_DEVICE_RESET = 0x2,
577 BCCB_RELEASE_SIMQ = 0x4
578 } bccb_flags_t;
579
580 struct bt_ccb {
581 struct bt_hccb hccb;
582 SLIST_ENTRY(bt_ccb) links;
583 u_int32_t flags;
584 union ccb *ccb;
585 bus_dmamap_t dmamap;
586 bt_sg_t *sg_list;
587 u_int32_t sg_list_phys;
588 };
589
590 struct sg_map_node {
591 bus_dmamap_t sg_dmamap;
592 bus_addr_t sg_physaddr;
593 bt_sg_t* sg_vaddr;
594 SLIST_ENTRY(sg_map_node) links;
595 };
596
597 struct bt_softc {
598 bus_space_tag_t tag;
599 bus_space_handle_t bsh;
600 struct cam_sim *sim;
601 struct cam_path *path;
602 bt_mbox_out_t *cur_outbox;
603 bt_mbox_in_t *cur_inbox;
604 bt_mbox_out_t *last_outbox;
605 bt_mbox_in_t *last_inbox;
606 struct bt_ccb *bt_ccb_array;
607 SLIST_HEAD(,bt_ccb) free_bt_ccbs;
608 LIST_HEAD(,ccb_hdr) pending_ccbs;
609 u_int active_ccbs;
610 u_int32_t bt_ccb_physbase;
611 bt_mbox_in_t *in_boxes;
612 bt_mbox_out_t *out_boxes;
613 struct scsi_sense_data *sense_buffers;
614 u_int32_t sense_buffers_physbase;
615 struct bt_ccb *recovery_bccb;
616 u_int num_boxes;
617 bus_dma_tag_t parent_dmat; /*
618 * All dmat's derive from
619 * the dmat defined by our
620 * bus.
621 */
622 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
623 bus_dma_tag_t mailbox_dmat; /* dmat for our mailboxes */
624 bus_dmamap_t mailbox_dmamap;
625 bus_dma_tag_t ccb_dmat; /* dmat for our ccb array */
626 bus_dmamap_t ccb_dmamap;
627 bus_dma_tag_t sg_dmat; /* dmat for our sg maps */
628 bus_dma_tag_t sense_dmat; /* dmat for our sg maps */
629 bus_dmamap_t sense_dmamap;
630 SLIST_HEAD(, sg_map_node) sg_maps;
631 bus_addr_t mailbox_physbase;
632 u_int num_ccbs; /* Number of CCBs malloc'd */
633 u_int max_ccbs; /* Maximum allocatable CCBs */
634 u_int max_sg;
635 u_int unit;
636 u_int scsi_id;
637 u_int32_t extended_trans :1,
638 wide_bus :1,
639 diff_bus :1,
640 ultra_scsi :1,
641 extended_lun :1,
642 strict_rr :1,
643 tag_capable :1,
644 wide_lun_ccb :1,
645 resource_shortage :1,
646 level_trigger_ints:1,
647 :22;
648 u_int16_t tags_permitted;
649 u_int16_t disc_permitted;
650 u_int16_t sync_permitted;
651 u_int16_t fast_permitted;
652 u_int16_t ultra_permitted;
653 u_int16_t wide_permitted;
654 u_int8_t init_level;
655 volatile u_int8_t command_cmp;
656 volatile u_int8_t latched_status;
657 u_int32_t bios_addr;
658 char firmware_ver[6];
659 char model[5];
660 };
661
662 extern struct bt_softc *bt_softcs[]; /* XXX Config should handle this */
663 extern u_long bt_unit;
664
665 #define BT_TEMP_UNIT 0xFF /* Unit for probes */
666 struct bt_softc* bt_alloc(int unit, bus_space_tag_t tag,
667 bus_space_handle_t bsh);
668 void bt_free(struct bt_softc *bt);
669 int bt_port_probe(struct bt_softc *bt,
670 struct bt_probe_info *info);
671 int bt_probe(struct bt_softc *bt);
672 int bt_fetch_adapter_info(struct bt_softc *bt);
673 int bt_init(struct bt_softc *bt);
674 int bt_attach(struct bt_softc *bt);
675 void bt_intr(void *arg);
676 char * bt_name(struct bt_softc *bt);
677 int bt_check_probed_iop(u_int ioport);
678 void bt_mark_probed_bio(isa_compat_io_t port);
679 void bt_mark_probed_iop(u_int ioport);
680 void bt_find_probe_range(int ioport,
681 int *port_index,
682 int *max_port_index);
683
684 int bt_iop_from_bio(isa_compat_io_t bio_index);
685
686 #define DEFAULT_CMD_TIMEOUT 100000 /* 10 sec */
687 int bt_cmd(struct bt_softc *bt, bt_op_t opcode,
688 u_int8_t *params, u_int param_len,
689 u_int8_t *reply_data, u_int reply_len,
690 u_int cmd_timeout);
691
692 #define bt_inb(bt, port) \
693 bus_space_read_1((bt)->tag, (bt)->bsh, port)
694
695 #define bt_outb(bt, port, value) \
696 bus_space_write_1((bt)->tag, (bt)->bsh, port, value)
697
698 #endif /* _BT_H_ */
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