The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/buslogic/btreg.h

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    1 /*-
    2  * Generic register and struct definitions for the BusLogic
    3  * MultiMaster SCSI host adapters.  Product specific probe and
    4  * attach routines can be found in:
    5  * sys/dev/buslogic/bt_isa.c    BT-54X, BT-445 cards
    6  * sys/dev/buslogic/bt_mca.c    BT-64X, SDC3211B, SDC3211F
    7  * sys/dev/buslogic/bt_eisa.c   BT-74X, BT-75x cards, SDC3222F
    8  * sys/dev/buslogic/bt_pci.c    BT-946, BT-948, BT-956, BT-958 cards
    9  *
   10  * Copyright (c) 1998, 1999 Justin T. Gibbs.
   11  * All rights reserved.
   12  *
   13  * Redistribution and use in source and binary forms, with or without
   14  * modification, are permitted provided that the following conditions
   15  * are met:
   16  * 1. Redistributions of source code must retain the above copyright
   17  *    notice, this list of conditions, and the following disclaimer,
   18  *    without modification, immediately at the beginning of the file.
   19  * 2. The name of the author may not be used to endorse or promote products
   20  *    derived from this software without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
   26  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   32  * SUCH DAMAGE.
   33  *
   34  * $FreeBSD$
   35  */
   36 
   37 #ifndef _BTREG_H_
   38 #define _BTREG_H_
   39 
   40 #include <sys/queue.h>
   41 
   42 #define BT_MAXTRANSFER_SIZE      0xffffffff     /* limited by 32bit counter */
   43 #define BT_NSEG         32      /* The number of dma segments supported.
   44                                  * BT_NSEG can be maxed out at 8192 entries,
   45                                  * but the kernel will never need to transfer
   46                                  * such a large request.  To reduce the
   47                                  * driver's memory consumption, we reduce the
   48                                  * max to 32.  16 would work if all transfers
   49                                  * are paged alined since the kernel will only
   50                                  * generate at most a 64k transfer, but to
   51                                  * handle non-page aligned transfers, you need
   52                                  * 17, so we round to the next power of two
   53                                  * to make allocating SG space easy and
   54                                  * efficient.
   55                                  */
   56 
   57 #define ALL_TARGETS (~0)
   58 
   59 /*
   60  * Control Register pp. 1-8, 1-9 (Write Only)
   61  */
   62 #define CONTROL_REG             0x00
   63 #define         HARD_RESET      0x80    /* Hard Reset - return to POST state */
   64 #define         SOFT_RESET      0x40    /* Soft Reset - Clears Adapter state */
   65 #define         RESET_INTR      0x20    /* Reset/Ack Interrupt */
   66 #define         RESET_SBUS      0x10    /* Drive SCSI bus reset signal */
   67 
   68 /*
   69  * Status Register pp. 1-9, 1-10 (Read Only)
   70  */
   71 #define STATUS_REG                      0x00
   72 #define         DIAG_ACTIVE             0x80    /* Performing Internal Diags */
   73 #define         DIAG_FAIL               0x40    /* Internal Diags failed */
   74 #define         INIT_REQUIRED           0x20    /* MBOXes need initialization */
   75 #define         HA_READY                0x10    /* HA ready for new commands */
   76 #define         CMD_REG_BUSY            0x08    /* HA busy with last cmd byte */
   77 #define         DATAIN_REG_READY        0x04    /* Data-in Byte available */
   78 #define         STATUS_REG_RSVD         0x02
   79 #define         CMD_INVALID             0x01    /* Invalid Command detected */
   80 
   81 /*
   82  * Command/Parameter Register pp. 1-10, 1-11 (Write Only)
   83  */
   84 #define COMMAND_REG                     0x01
   85 
   86 /*
   87  * Data in Register p. 1-11 (Read Only)
   88  */
   89 #define DATAIN_REG                      0x01
   90 
   91 /*
   92  * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only)
   93  */
   94 #define INTSTAT_REG                     0x02
   95 #define         INTR_PENDING            0x80    /* There is a pending INTR */
   96 #define         INTSTAT_REG_RSVD        0x70
   97 #define         SCSI_BUS_RESET          0x08    /* Bus Reset detected */
   98 #define         CMD_COMPLETE            0x04
   99 #define         OMB_READY               0x02    /* Outgoin Mailbox Ready */
  100 #define         IMB_LOADED              0x01    /* Incoming Mailbox loaded */
  101 
  102 /*
  103  * Definitions for the "undocumented" geometry register
  104  */
  105 typedef enum {
  106         GEOM_NODISK,
  107         GEOM_64x32,
  108         GEOM_128x32,
  109         GEOM_255x32
  110 } disk_geom_t;
  111 
  112 #define GEOMETRY_REG                    0x03
  113 #define         DISK0_GEOMETRY          0x03
  114 #define         DISK1_GEOMETRY          0x0c
  115 #define         EXTENDED_TRANSLATION    0x80
  116 #define         GEOMETRY_DISK0(g_reg) (greg & DISK0_GEOMETRY)
  117 #define         GEOMETRY_DISK1(g_reg) ((greg & DISK1_GEOMETRY) >> 2)
  118 
  119 #define BT_NREGS        (4)
  120 /*
  121  * Opcodes for Adapter commands.
  122  * pp 1-18 -> 1-20
  123  */
  124 typedef enum {
  125         BOP_TEST_CMDC_INTR      = 0x00,
  126         BOP_INITIALIZE_24BMBOX  = 0x01,
  127         BOP_START_MBOX          = 0x02,
  128         BOP_EXECUTE_BIOS_CMD    = 0x03,
  129         BOP_INQUIRE_BOARD_ID    = 0x04,
  130         BOP_ENABLE_OMBR_INT     = 0x05,
  131         BOP_SET_SEL_TIMOUT      = 0x06,
  132         BOP_SET_TIME_ON_BUS     = 0x07,
  133         BOP_SET_TIME_OFF_BUS    = 0x08,
  134         BOP_SET_BUS_TRANS_RATE  = 0x09,
  135         BOP_INQUIRE_INST_LDEVS  = 0x0A,
  136         BOP_INQUIRE_CONFIG      = 0x0B,
  137         BOP_ENABLE_TARGET_MODE  = 0x0C,
  138         BOP_INQUIRE_SETUP_INFO  = 0x0D,
  139         BOP_WRITE_LRAM          = 0x1A,
  140         BOP_READ_LRAM           = 0x1B,
  141         BOP_WRITE_CHIP_FIFO     = 0x1C,
  142         BOP_READ_CHIP_FIFO      = 0x1C,
  143         BOP_ECHO_DATA_BYTE      = 0x1F,
  144         BOP_ADAPTER_DIAGNOSTICS = 0x20,
  145         BOP_SET_ADAPTER_OPTIONS = 0x21,
  146         BOP_INQUIRE_INST_HDEVS  = 0x23,
  147         BOP_INQUIRE_TARG_DEVS   = 0x24,
  148         BOP_DISABLE_HAC_INTR    = 0x25,
  149         BOP_INITIALIZE_32BMBOX  = 0x81,
  150         BOP_EXECUTE_SCSI_CMD    = 0x83,
  151         BOP_INQUIRE_FW_VER_3DIG = 0x84,
  152         BOP_INQUIRE_FW_VER_4DIG = 0x85,
  153         BOP_INQUIRE_PCI_INFO    = 0x86,
  154         BOP_INQUIRE_MODEL       = 0x8B,
  155         BOP_TARG_SYNC_INFO      = 0x8C,
  156         BOP_INQUIRE_ESETUP_INFO = 0x8D,
  157         BOP_ENABLE_STRICT_RR    = 0x8F,
  158         BOP_STORE_LRAM          = 0x90,
  159         BOP_FETCH_LRAM          = 0x91,
  160         BOP_SAVE_TO_EEPROM      = 0x92,
  161         BOP_UPLOAD_AUTO_SCSI    = 0x94,
  162         BOP_MODIFY_IO_ADDR      = 0x95,
  163         BOP_SET_CCB_FORMAT      = 0x96,
  164         BOP_FLASH_ROM_DOWNLOAD  = 0x97,
  165         BOP_FLASH_WRITE_ENABLE  = 0x98,
  166         BOP_WRITE_INQ_BUFFER    = 0x9A,
  167         BOP_READ_INQ_BUFFER     = 0x9B,
  168         BOP_FLASH_UP_DOWNLOAD   = 0xA7,
  169         BOP_READ_SCAM_DATA      = 0xA8,
  170         BOP_WRITE_SCAM_DATA     = 0xA9
  171 } bt_op_t;
  172 
  173 /************** Definitions of Multi-byte commands and responses ************/
  174 
  175 typedef struct {
  176         u_int8_t num_mboxes;
  177         u_int8_t base_addr[3];
  178 } init_24b_mbox_params_t;
  179 
  180 typedef struct {
  181         u_int8_t board_type;
  182 #define         BOARD_TYPE_NON_MCA      0x41
  183 #define         BOARD_TYPE_MCA          0x42
  184         u_int8_t cust_features;
  185 #define         FEATURES_STANDARD       0x41
  186         u_int8_t firmware_rev_major;
  187         u_int8_t firmware_rev_minor;
  188 } board_id_data_t;
  189 
  190 typedef struct {
  191         u_int8_t enable;
  192 } enable_ombr_intr_params_t;
  193 
  194 typedef struct {
  195         u_int8_t enable;
  196         u_int8_t reserved;
  197         u_int8_t timeout[2];    /* timeout in milliseconds */
  198 } set_selto_parmas_t;
  199 
  200 typedef struct {
  201         u_int8_t time;          /* time in milliseconds (2-15) */
  202 } set_timeon_bus_params_t;
  203 
  204 typedef struct {
  205         u_int8_t time;          /* time in milliseconds (2-15) */
  206 } set_timeoff_bus_params_t;
  207 
  208 typedef struct {
  209         u_int8_t rate;
  210 } set_bus_trasfer_rate_params_t;
  211 
  212 typedef struct {
  213         u_int8_t targets[8];
  214 } installed_ldevs_data_t;
  215 
  216 typedef struct {
  217         u_int8_t dma_chan;
  218 #define         DMA_CHAN_5      0x20
  219 #define         DMA_CHAN_6      0x40
  220 #define         DMA_CHAN_7      0x80
  221         u_int8_t irq;
  222 #define         IRQ_9           0x01
  223 #define         IRQ_10          0x02
  224 #define         IRQ_11          0x04
  225 #define         IRQ_12          0x08
  226 #define         IRQ_14          0x20
  227 #define         IRQ_15          0x40
  228         u_int8_t scsi_id;
  229 } config_data_t;
  230 
  231 typedef struct {
  232         u_int8_t enable;
  233 } target_mode_params_t;
  234 
  235 typedef struct {
  236         u_int8_t offset : 4,
  237                  period : 3,
  238                  sync   : 1;
  239 } targ_syncinfo_t;
  240 
  241 typedef enum {
  242         HAB_ISA         = 'A',
  243         HAB_MCA         = 'B',
  244         HAB_EISA        = 'C',
  245         HAB_NUBUS       = 'D',
  246         HAB_VESA        = 'E',
  247         HAB_PCI         = 'F'
  248 } ha_type_t;
  249 
  250 typedef struct {
  251         u_int8_t        initiate_sync   : 1,
  252                         parity_enable   : 1,
  253                                         : 6;
  254 
  255         u_int8_t        bus_transfer_rate;
  256         u_int8_t        time_on_bus;
  257         u_int8_t        time_off_bus;
  258         u_int8_t        num_mboxes;
  259         u_int8_t        mbox_base_addr[3];
  260         targ_syncinfo_t low_syncinfo[8];        /* For fast and ultra, use 8C */
  261         u_int8_t        low_discinfo;
  262         u_int8_t        customer_sig;
  263         u_int8_t        letter_d;
  264         u_int8_t        ha_type;
  265         u_int8_t        low_wide_allowed;
  266         u_int8_t        low_wide_active;
  267         targ_syncinfo_t high_syncinfo[8];
  268         u_int8_t        high_discinfo;
  269         u_int8_t        high_wide_allowed;
  270         u_int8_t        high_wide_active;
  271 } setup_data_t;
  272 
  273 typedef struct {
  274         u_int8_t phys_addr[3];
  275 } write_adapter_lram_params_t;
  276 
  277 typedef struct {
  278         u_int8_t phys_addr[3];
  279 } read_adapter_lram_params_t;
  280 
  281 typedef struct {
  282         u_int8_t phys_addr[3];
  283 } write_chip_fifo_params_t;
  284 
  285 typedef struct {
  286         u_int8_t phys_addr[3];
  287 } read_chip_fifo_params_t;
  288 
  289 typedef struct {
  290         u_int8_t length;                /* Excludes this member */
  291         u_int8_t low_disc_disable;
  292         u_int8_t low_busy_retry_disable;
  293         u_int8_t high_disc_disable;
  294         u_int8_t high_busy_retry_disable;
  295 } set_adapter_options_params_t;
  296 
  297 typedef struct {
  298         u_int8_t targets[8];
  299 } installed_hdevs_data_t;
  300 
  301 typedef struct {
  302         u_int8_t low_devs;
  303         u_int8_t high_devs;
  304 } target_devs_data_t;
  305 
  306 typedef struct {
  307         u_int8_t enable;
  308 } enable_hac_interrupt_params_t;
  309 
  310 typedef struct {
  311         u_int8_t num_boxes;
  312         u_int8_t base_addr[4];
  313 } init_32b_mbox_params_t;
  314 
  315 typedef u_int8_t fw_ver_3dig_data_t;
  316 
  317 typedef u_int8_t fw_ver_4dig_data_t;
  318 
  319 typedef struct  {
  320         u_int8_t offset;
  321         u_int8_t response_len;
  322 } fetch_lram_params_t;
  323 
  324 #define AUTO_SCSI_BYTE_OFFSET   64
  325 typedef struct {
  326         u_int8_t        factory_sig[2];
  327         u_int8_t        auto_scsi_data_size;    /* 2 -> 64 bytes */
  328         u_int8_t        model_num[6];
  329         u_int8_t        adapter_ioport;
  330         u_int8_t        floppy_enabled   :1,
  331                         floppy_secondary :1,
  332                         level_trigger    :1,
  333                                          :2,
  334                         system_ram_area  :3;
  335         u_int8_t        dma_channel      :7,
  336                         dma_autoconf     :1;
  337         u_int8_t        irq_channel      :7,
  338                         irq_autoconf     :1;
  339         u_int8_t        dma_trans_rate;
  340         u_int8_t        scsi_id;
  341         u_int8_t        low_termination  :1,
  342                         scsi_parity      :1,
  343                         high_termination :1,
  344                         req_ack_filter   :1,
  345                         fast_sync        :1,
  346                         bus_reset        :1,
  347                                          :1,
  348                         active_negation  :1;
  349         u_int8_t        bus_on_delay;
  350         u_int8_t        bus_off_delay;
  351         u_int8_t        bios_enabled     :1,
  352                         int19h_redirect  :1,
  353                         extended_trans   :1,
  354                         removable_drives :1,
  355                                          :1,
  356                         morethan2disks   :1,
  357                         interrupt_mode   :1,
  358                         floptical_support:1;
  359         u_int8_t        low_device_enabled;
  360         u_int8_t        high_device_enabled;
  361         u_int8_t        low_wide_permitted;
  362         u_int8_t        high_wide_permitted;
  363         u_int8_t        low_fast_permitted;
  364         u_int8_t        high_fast_permitted;
  365         u_int8_t        low_sync_permitted;
  366         u_int8_t        high_sync_permitted;
  367         u_int8_t        low_disc_permitted;
  368         u_int8_t        high_disc_permitted;
  369         u_int8_t        low_send_start_unit;
  370         u_int8_t        high_send_start_unit;
  371         u_int8_t        low_ignore_in_bios_scan;
  372         u_int8_t        high_ignore_in_bios_scan;
  373         u_int8_t        pci_int_pin      :2,
  374                         host_ioport      :2,
  375                         round_robin      :1,
  376                         vesa_bus_over_33 :1,
  377                         vesa_burst_write :1,
  378                         vesa_burst_read  :1;
  379         u_int8_t        low_ultra_permitted;
  380         u_int8_t        high_ultra_permitted;
  381         u_int8_t        reserved[5];
  382         u_int8_t        auto_scsi_max_lun;
  383         u_int8_t                         :1,
  384                         scam_dominant    :1,
  385                         scam_enabled     :1,
  386                         scam_level2      :1,
  387                                          :4;
  388         u_int8_t        int13_extensions :1,
  389                                          :1,
  390                         cdrom_boot       :1,
  391                                          :2,
  392                         multi_boot       :1,
  393                                          :2;
  394         u_int8_t        boot_target_id   :4,
  395                         boot_channel     :4;
  396         u_int8_t        force_dev_scan   :1,
  397                                          :7;
  398         u_int8_t        low_tagged_lun_independance;
  399         u_int8_t        high_tagged_lun_independance;
  400         u_int8_t        low_renegotiate_after_cc;
  401         u_int8_t        high_renegotiate_after_cc;
  402         u_int8_t        reserverd2[10];
  403         u_int8_t        manufacturing_diagnotic[2];
  404         u_int8_t        checksum[2];
  405 } auto_scsi_data_t;
  406 
  407 struct bt_isa_port {
  408         u_int16_t addr;
  409         u_int8_t  probed;
  410         u_int8_t  bio;
  411 };
  412 
  413 extern struct bt_isa_port bt_isa_ports[];
  414 
  415 #define BT_NUM_ISAPORTS 6
  416 
  417 typedef enum {
  418         BIO_330         = 0,
  419         BIO_334         = 1,
  420         BIO_230         = 2,
  421         BIO_234         = 3,
  422         BIO_130         = 4,
  423         BIO_134         = 5,
  424         BIO_DISABLED    = 6,
  425         BIO_DISABLED2   = 7
  426 } isa_compat_io_t;
  427 
  428 typedef struct {
  429         u_int8_t io_port;
  430         u_int8_t irq_num;
  431         u_int8_t low_byte_term  :1,
  432                  high_byte_term :1,
  433                                 :2,
  434                  jp1_status     :1,
  435                  jp2_status     :1,
  436                  jp3_status     :1,
  437                                 :1;
  438         u_int8_t reserved;
  439 } pci_info_data_t;
  440 
  441 typedef struct {
  442         u_int8_t ascii_model[5];        /* Fifth byte is always 0 */
  443 } ha_model_data_t;
  444 
  445 typedef struct {
  446         u_int8_t sync_rate[16];         /* Sync in 10ns units */
  447 } target_sync_info_data_t;
  448 
  449 typedef struct {
  450         u_int8_t  bus_type;
  451         u_int8_t  bios_addr;
  452         u_int16_t max_sg;
  453         u_int8_t  num_mboxes;
  454         u_int8_t  mbox_base[4];
  455         u_int8_t                        :2,
  456                   sync_neg10MB          :1,
  457                   floppy_disable        :1,
  458                   floppy_secondary_port :1,
  459                   burst_mode_enabled    :1,
  460                   level_trigger_ints    :1,
  461                                         :1;
  462         u_int8_t  fw_ver_bytes_2_to_4[3];
  463         u_int8_t  wide_bus              :1,
  464                   diff_bus              :1,
  465                   scam_capable          :1,
  466                   ultra_scsi            :1,
  467                   auto_term             :1,
  468                                         :3;
  469 } esetup_info_data_t;
  470 
  471 typedef struct {
  472         u_int32_t len;
  473         u_int32_t addr;
  474 } bt_sg_t;
  475 
  476 /********************** Mail Box definitions *******************************/
  477 
  478 typedef enum {
  479         BMBO_FREE               = 0x0,  /* MBO intry is free */
  480         BMBO_START              = 0x1,  /* MBO activate entry */
  481         BMBO_ABORT              = 0x2   /* MBO abort entry */
  482 } bt_mbo_action_code_t; 
  483 
  484 typedef struct bt_mbox_out {     
  485         u_int32_t ccb_addr;
  486         u_int8_t  reserved[3];
  487         u_int8_t  action_code;
  488 } bt_mbox_out_t;
  489 
  490 typedef enum {
  491         BMBI_FREE               = 0x0,  /* MBI entry is free */ 
  492         BMBI_OK                 = 0x1,  /* completed without error */
  493         BMBI_ABORT              = 0x2,  /* aborted ccb */
  494         BMBI_NOT_FOUND          = 0x3,  /* Tried to abort invalid CCB */
  495         BMBI_ERROR              = 0x4   /* Completed with error */
  496 } bt_mbi_comp_code_t; 
  497 
  498 typedef struct bt_mbox_in {      
  499         u_int32_t ccb_addr;    
  500         u_int8_t  btstat;
  501         u_int8_t  sdstat;
  502         u_int8_t  reserved;
  503         u_int8_t  comp_code;
  504 } bt_mbox_in_t;
  505 
  506 /***************** Compiled Probe Information *******************************/
  507 struct bt_probe_info {
  508         int     drq;
  509         int     irq;
  510 };
  511 
  512 /****************** Hardware CCB definition *********************************/
  513 typedef enum {
  514         INITIATOR_CCB           = 0x00,
  515         INITIATOR_SG_CCB        = 0x02,
  516         INITIATOR_CCB_WRESID    = 0x03,
  517         INITIATOR_SG_CCB_WRESID = 0x04,
  518         INITIATOR_BUS_DEV_RESET = 0x81
  519 } bt_ccb_opcode_t;
  520 
  521 typedef enum {
  522         BTSTAT_NOERROR                  = 0x00,
  523         BTSTAT_LINKED_CMD_COMPLETE      = 0x0A,
  524         BTSTAT_LINKED_CMD_FLAG_COMPLETE = 0x0B,
  525         BTSTAT_DATAUNDERUN_ERROR        = 0x0C,
  526         BTSTAT_SELTIMEOUT               = 0x11,
  527         BTSTAT_DATARUN_ERROR            = 0x12,
  528         BTSTAT_UNEXPECTED_BUSFREE       = 0x13,
  529         BTSTAT_INVALID_PHASE            = 0x14,
  530         BTSTAT_INVALID_ACTION_CODE      = 0x15,
  531         BTSTAT_INVALID_OPCODE           = 0x16,
  532         BTSTAT_LINKED_CCB_LUN_MISMATCH  = 0x17,
  533         BTSTAT_INVALID_CCB_OR_SG_PARAM  = 0x1A,
  534         BTSTAT_AUTOSENSE_FAILED         = 0x1B,
  535         BTSTAT_TAGGED_MSG_REJECTED      = 0x1C,
  536         BTSTAT_UNSUPPORTED_MSG_RECEIVED = 0x1D,
  537         BTSTAT_HARDWARE_FAILURE         = 0x20,
  538         BTSTAT_TARGET_IGNORED_ATN       = 0x21,
  539         BTSTAT_HA_SCSI_BUS_RESET        = 0x22,
  540         BTSTAT_OTHER_SCSI_BUS_RESET     = 0x23,
  541         BTSTAT_INVALID_RECONNECT        = 0x24,
  542         BTSTAT_HA_BDR                   = 0x25,
  543         BTSTAT_ABORT_QUEUE_GENERATED    = 0x26,
  544         BTSTAT_HA_SOFTWARE_ERROR        = 0x27,
  545         BTSTAT_HA_WATCHDOG_ERROR        = 0x28,
  546         BTSTAT_SCSI_PERROR_DETECTED     = 0x30
  547 } btstat_t;
  548 
  549 struct bt_hccb {
  550         u_int8_t  opcode;
  551         u_int8_t                        :3,
  552                   datain                :1,
  553                   dataout               :1,
  554                   wide_tag_enable       :1,     /* Wide Lun CCB format */
  555                   wide_tag_type         :2;     /* Wide Lun CCB format */
  556         u_int8_t  cmd_len;
  557         u_int8_t  sense_len;
  558         int32_t   data_len;                     /* residuals can be negative */
  559         u_int32_t data_addr;
  560         u_int8_t  reserved[2];
  561         u_int8_t  btstat;
  562         u_int8_t  sdstat;
  563         u_int8_t  target_id;
  564         u_int8_t  target_lun    :5,
  565                   tag_enable    :1,
  566                   tag_type      :2;
  567         u_int8_t  scsi_cdb[12];
  568         u_int8_t  reserved2[6];
  569         u_int32_t sense_addr;
  570 };
  571 
  572 typedef enum {
  573         BCCB_FREE               = 0x0,
  574         BCCB_ACTIVE             = 0x1,
  575         BCCB_DEVICE_RESET       = 0x2,
  576         BCCB_RELEASE_SIMQ       = 0x4
  577 } bccb_flags_t;
  578 
  579 struct bt_ccb {
  580         struct  bt_hccb          hccb;
  581         SLIST_ENTRY(bt_ccb)      links;
  582         u_int32_t                flags;
  583         union ccb               *ccb;
  584         bus_dmamap_t             dmamap;
  585         bt_sg_t                 *sg_list;
  586         u_int32_t                sg_list_phys;
  587 };
  588 
  589 struct sg_map_node {
  590         bus_dmamap_t             sg_dmamap;
  591         bus_addr_t               sg_physaddr;
  592         bt_sg_t*                 sg_vaddr;
  593         SLIST_ENTRY(sg_map_node) links;
  594 };
  595         
  596 struct bt_softc {
  597         struct device           *dev;
  598         struct resource         *port;
  599         struct resource         *irq;
  600         struct resource         *drq;
  601         void                    *ih;
  602         bus_space_tag_t          tag;
  603         bus_space_handle_t       bsh;
  604         struct  cam_sim         *sim;
  605         struct  cam_path        *path;
  606         bt_mbox_out_t           *cur_outbox;
  607         bt_mbox_in_t            *cur_inbox;
  608         bt_mbox_out_t           *last_outbox;
  609         bt_mbox_in_t            *last_inbox;
  610         struct  bt_ccb          *bt_ccb_array;
  611         SLIST_HEAD(,bt_ccb)      free_bt_ccbs;
  612         LIST_HEAD(,ccb_hdr)      pending_ccbs;
  613         u_int                    active_ccbs;
  614         u_int32_t                bt_ccb_physbase;
  615         bt_mbox_in_t            *in_boxes;
  616         bt_mbox_out_t           *out_boxes;
  617         struct scsi_sense_data  *sense_buffers;
  618         u_int32_t                sense_buffers_physbase;
  619         struct  bt_ccb          *recovery_bccb;
  620         u_int                    num_boxes;
  621         bus_dma_tag_t            parent_dmat;   /*
  622                                                  * All dmat's derive from
  623                                                  * the dmat defined by our
  624                                                  * bus.
  625                                                  */
  626         bus_dma_tag_t            buffer_dmat;   /* dmat for buffer I/O */
  627         bus_dma_tag_t            mailbox_dmat;  /* dmat for our mailboxes */
  628         bus_dmamap_t             mailbox_dmamap;
  629         bus_dma_tag_t            ccb_dmat;      /* dmat for our ccb array */
  630         bus_dmamap_t             ccb_dmamap;
  631         bus_dma_tag_t            sg_dmat;       /* dmat for our sg segments */
  632         bus_dma_tag_t            sense_dmat;    /* dmat for our sense buffers */
  633         bus_dmamap_t             sense_dmamap;
  634         SLIST_HEAD(, sg_map_node) sg_maps;
  635         bus_addr_t               mailbox_physbase;
  636         bus_addr_t               mailbox_addrlimit;
  637         u_int                    num_ccbs;      /* Number of CCBs malloc'd */
  638         u_int                    max_ccbs;      /* Maximum allocatable CCBs */
  639         u_int                    max_sg;
  640         u_int                    unit;
  641         u_int                    scsi_id;
  642         u_int32_t                extended_trans    :1,
  643                                  wide_bus          :1,
  644                                  diff_bus          :1,
  645                                  ultra_scsi        :1,
  646                                  extended_lun      :1,
  647                                  strict_rr         :1,
  648                                  tag_capable       :1,
  649                                  wide_lun_ccb      :1,
  650                                  resource_shortage :1,
  651                                  level_trigger_ints:1,
  652                                                    :22;
  653         u_int16_t                tags_permitted;
  654         u_int16_t                disc_permitted;
  655         u_int16_t                sync_permitted;
  656         u_int16_t                fast_permitted;
  657         u_int16_t                ultra_permitted;
  658         u_int16_t                wide_permitted;
  659         u_int8_t                 init_level;
  660         volatile u_int8_t        command_cmp;
  661         volatile u_int8_t        latched_status;
  662         u_int32_t                bios_addr;
  663         char                     firmware_ver[6];
  664         char                     model[5];
  665 };
  666 
  667 extern u_long bt_unit;
  668 
  669 #define BT_TEMP_UNIT 0xFF               /* Unit for probes */
  670 void                    bt_init_softc(device_t dev,
  671                                       struct resource *port,
  672                                       struct resource *irq,
  673                                       struct resource *drq);
  674 void                    bt_free_softc(device_t dev);
  675 int                     bt_port_probe(device_t dev,
  676                                       struct bt_probe_info *info);
  677 int                     bt_probe(device_t dev);
  678 int                     bt_fetch_adapter_info(device_t dev);
  679 int                     bt_init(device_t dev); 
  680 int                     bt_attach(device_t dev);
  681 void                    bt_intr(void *arg);
  682 int                     bt_check_probed_iop(u_int ioport);
  683 void                    bt_mark_probed_bio(isa_compat_io_t port);
  684 void                    bt_mark_probed_iop(u_int ioport);
  685 void                    bt_find_probe_range(int ioport,
  686                                             int *port_index,
  687                                             int *max_port_index);
  688 
  689 int                     bt_iop_from_bio(isa_compat_io_t bio_index);
  690 
  691 #define DEFAULT_CMD_TIMEOUT 100000      /* 10 sec */
  692 int                     bt_cmd(struct bt_softc *bt, bt_op_t opcode,
  693                                u_int8_t *params, u_int param_len,
  694                                u_int8_t *reply_data, u_int reply_len,
  695                                u_int cmd_timeout);
  696 
  697 #define bt_name(bt)     device_get_nameunit(bt->dev)
  698 
  699 #define bt_inb(bt, port)                                \
  700         bus_space_read_1((bt)->tag, (bt)->bsh, port)
  701 
  702 #define bt_outb(bt, port, value)                        \
  703         bus_space_write_1((bt)->tag, (bt)->bsh, port, value)
  704 
  705 #endif  /* _BT_H_ */

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