FreeBSD/Linux Kernel Cross Reference
sys/dev/bwi/if_bwi.c
1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Sepherosa Ziehau <sepherosa@gmail.com>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in
17 * the documentation and/or other materials provided with the
18 * distribution.
19 * 3. Neither the name of The DragonFly Project nor the names of its
20 * contributors may be used to endorse or promote products derived
21 * from this software without specific, prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $
37 */
38
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
41
42 #include "opt_inet.h"
43 #include "opt_bwi.h"
44 #include "opt_wlan.h"
45
46 #include <sys/param.h>
47 #include <sys/endian.h>
48 #include <sys/kernel.h>
49 #include <sys/bus.h>
50 #include <sys/malloc.h>
51 #include <sys/proc.h>
52 #include <sys/rman.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
55 #include <sys/sysctl.h>
56 #include <sys/systm.h>
57 #include <sys/taskqueue.h>
58
59 #include <net/if.h>
60 #include <net/if_var.h>
61 #include <net/if_dl.h>
62 #include <net/if_media.h>
63 #include <net/if_types.h>
64 #include <net/if_arp.h>
65 #include <net/ethernet.h>
66 #include <net/if_llc.h>
67
68 #include <net80211/ieee80211_var.h>
69 #include <net80211/ieee80211_radiotap.h>
70 #include <net80211/ieee80211_regdomain.h>
71 #include <net80211/ieee80211_phy.h>
72 #include <net80211/ieee80211_ratectl.h>
73
74 #include <net/bpf.h>
75
76 #ifdef INET
77 #include <netinet/in.h>
78 #include <netinet/if_ether.h>
79 #endif
80
81 #include <machine/bus.h>
82
83 #include <dev/pci/pcivar.h>
84 #include <dev/pci/pcireg.h>
85
86 #include <dev/bwi/bitops.h>
87 #include <dev/bwi/if_bwireg.h>
88 #include <dev/bwi/if_bwivar.h>
89 #include <dev/bwi/bwimac.h>
90 #include <dev/bwi/bwirf.h>
91
92 struct bwi_clock_freq {
93 u_int clkfreq_min;
94 u_int clkfreq_max;
95 };
96
97 struct bwi_myaddr_bssid {
98 uint8_t myaddr[IEEE80211_ADDR_LEN];
99 uint8_t bssid[IEEE80211_ADDR_LEN];
100 } __packed;
101
102 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *,
103 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
104 const uint8_t [IEEE80211_ADDR_LEN],
105 const uint8_t [IEEE80211_ADDR_LEN]);
106 static void bwi_vap_delete(struct ieee80211vap *);
107 static void bwi_init(struct bwi_softc *);
108 static void bwi_parent(struct ieee80211com *);
109 static int bwi_transmit(struct ieee80211com *, struct mbuf *);
110 static void bwi_start_locked(struct bwi_softc *);
111 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *,
112 const struct ieee80211_bpf_params *);
113 static void bwi_watchdog(void *);
114 static void bwi_scan_start(struct ieee80211com *);
115 static void bwi_getradiocaps(struct ieee80211com *, int, int *,
116 struct ieee80211_channel[]);
117 static void bwi_set_channel(struct ieee80211com *);
118 static void bwi_scan_end(struct ieee80211com *);
119 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int);
120 static void bwi_updateslot(struct ieee80211com *);
121
122 static void bwi_calibrate(void *);
123
124 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
125 static int bwi_calc_noise(struct bwi_softc *);
126 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype);
127 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
128 struct bwi_rxbuf_hdr *, const void *, int, int, int);
129
130 static void bwi_restart(void *, int);
131 static void bwi_init_statechg(struct bwi_softc *, int);
132 static void bwi_stop(struct bwi_softc *, int);
133 static void bwi_stop_locked(struct bwi_softc *, int);
134 static int bwi_newbuf(struct bwi_softc *, int, int);
135 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
136 struct ieee80211_node *);
137 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *,
138 struct ieee80211_node *,
139 const struct ieee80211_bpf_params *);
140
141 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
142 bus_addr_t, int, int);
143 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
144
145 static int bwi_init_tx_ring32(struct bwi_softc *, int);
146 static int bwi_init_rx_ring32(struct bwi_softc *);
147 static int bwi_init_txstats32(struct bwi_softc *);
148 static void bwi_free_tx_ring32(struct bwi_softc *, int);
149 static void bwi_free_rx_ring32(struct bwi_softc *);
150 static void bwi_free_txstats32(struct bwi_softc *);
151 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
152 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
153 int, bus_addr_t, int);
154 static int bwi_rxeof32(struct bwi_softc *);
155 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
156 static void bwi_txeof_status32(struct bwi_softc *);
157
158 static int bwi_init_tx_ring64(struct bwi_softc *, int);
159 static int bwi_init_rx_ring64(struct bwi_softc *);
160 static int bwi_init_txstats64(struct bwi_softc *);
161 static void bwi_free_tx_ring64(struct bwi_softc *, int);
162 static void bwi_free_rx_ring64(struct bwi_softc *);
163 static void bwi_free_txstats64(struct bwi_softc *);
164 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
165 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
166 int, bus_addr_t, int);
167 static int bwi_rxeof64(struct bwi_softc *);
168 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
169 static void bwi_txeof_status64(struct bwi_softc *);
170
171 static int bwi_rxeof(struct bwi_softc *, int);
172 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
173 static void bwi_txeof(struct bwi_softc *);
174 static void bwi_txeof_status(struct bwi_softc *, int);
175 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
176 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
177
178 static int bwi_dma_alloc(struct bwi_softc *);
179 static void bwi_dma_free(struct bwi_softc *);
180 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
181 struct bwi_ring_data *, bus_size_t,
182 uint32_t);
183 static int bwi_dma_mbuf_create(struct bwi_softc *);
184 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
185 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
186 static void bwi_dma_txstats_free(struct bwi_softc *);
187 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
188 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
189 bus_size_t, int);
190
191 static void bwi_power_on(struct bwi_softc *, int);
192 static int bwi_power_off(struct bwi_softc *, int);
193 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
194 static int bwi_set_clock_delay(struct bwi_softc *);
195 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
196 static int bwi_get_pwron_delay(struct bwi_softc *sc);
197 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
198 const uint8_t *);
199 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
200
201 static void bwi_get_card_flags(struct bwi_softc *);
202 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
203
204 static int bwi_bus_attach(struct bwi_softc *);
205 static int bwi_bbp_attach(struct bwi_softc *);
206 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
207 static void bwi_bbp_power_off(struct bwi_softc *);
208
209 static const char *bwi_regwin_name(const struct bwi_regwin *);
210 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
211 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
212 static int bwi_regwin_select(struct bwi_softc *, int);
213
214 static void bwi_led_attach(struct bwi_softc *);
215 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
216 static void bwi_led_event(struct bwi_softc *, int);
217 static void bwi_led_blink_start(struct bwi_softc *, int, int);
218 static void bwi_led_blink_next(void *);
219 static void bwi_led_blink_end(void *);
220
221 static const struct {
222 uint16_t did_min;
223 uint16_t did_max;
224 uint16_t bbp_id;
225 } bwi_bbpid_map[] = {
226 { 0x4301, 0x4301, 0x4301 },
227 { 0x4305, 0x4307, 0x4307 },
228 { 0x4402, 0x4403, 0x4402 },
229 { 0x4610, 0x4615, 0x4610 },
230 { 0x4710, 0x4715, 0x4710 },
231 { 0x4720, 0x4725, 0x4309 }
232 };
233
234 static const struct {
235 uint16_t bbp_id;
236 int nregwin;
237 } bwi_regwin_count[] = {
238 { 0x4301, 5 },
239 { 0x4306, 6 },
240 { 0x4307, 5 },
241 { 0x4310, 8 },
242 { 0x4401, 3 },
243 { 0x4402, 3 },
244 { 0x4610, 9 },
245 { 0x4704, 9 },
246 { 0x4710, 9 },
247 { 0x5365, 7 }
248 };
249
250 #define CLKSRC(src) \
251 [BWI_CLKSRC_ ## src] = { \
252 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
253 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
254 }
255
256 static const struct {
257 u_int freq_min;
258 u_int freq_max;
259 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
260 CLKSRC(LP_OSC),
261 CLKSRC(CS_OSC),
262 CLKSRC(PCI)
263 };
264
265 #undef CLKSRC
266
267 #define VENDOR_LED_ACT(vendor) \
268 { \
269 .vid = PCI_VENDOR_##vendor, \
270 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
271 }
272
273 static const struct {
274 #define PCI_VENDOR_COMPAQ 0x0e11
275 #define PCI_VENDOR_LINKSYS 0x1737
276 uint16_t vid;
277 uint8_t led_act[BWI_LED_MAX];
278 } bwi_vendor_led_act[] = {
279 VENDOR_LED_ACT(COMPAQ),
280 VENDOR_LED_ACT(LINKSYS)
281 #undef PCI_VENDOR_LINKSYS
282 #undef PCI_VENDOR_COMPAQ
283 };
284
285 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
286 { BWI_VENDOR_LED_ACT_DEFAULT };
287
288 #undef VENDOR_LED_ACT
289
290 static const struct {
291 int on_dur;
292 int off_dur;
293 } bwi_led_duration[109] = {
294 [0] = { 400, 100 },
295 [2] = { 150, 75 },
296 [4] = { 90, 45 },
297 [11] = { 66, 34 },
298 [12] = { 53, 26 },
299 [18] = { 42, 21 },
300 [22] = { 35, 17 },
301 [24] = { 32, 16 },
302 [36] = { 21, 10 },
303 [48] = { 16, 8 },
304 [72] = { 11, 5 },
305 [96] = { 9, 4 },
306 [108] = { 7, 3 }
307 };
308
309 #ifdef BWI_DEBUG
310 #ifdef BWI_DEBUG_VERBOSE
311 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
312 #else
313 static uint32_t bwi_debug;
314 #endif
315 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
316 #endif /* BWI_DEBUG */
317
318 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
319
320 uint16_t
321 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
322 {
323 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
324 }
325
326 static __inline void
327 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
328 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
329 int tx)
330 {
331 struct bwi_desc32 *desc = &desc_array[desc_idx];
332 uint32_t ctrl, addr, addr_hi, addr_lo;
333
334 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
335 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
336
337 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
338 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
339
340 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
341 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
342 if (desc_idx == ndesc - 1)
343 ctrl |= BWI_DESC32_C_EOR;
344 if (tx) {
345 /* XXX */
346 ctrl |= BWI_DESC32_C_FRAME_START |
347 BWI_DESC32_C_FRAME_END |
348 BWI_DESC32_C_INTR;
349 }
350
351 desc->addr = htole32(addr);
352 desc->ctrl = htole32(ctrl);
353 }
354
355 int
356 bwi_attach(struct bwi_softc *sc)
357 {
358 struct ieee80211com *ic = &sc->sc_ic;
359 device_t dev = sc->sc_dev;
360 struct bwi_mac *mac;
361 struct bwi_phy *phy;
362 int i, error;
363
364 BWI_LOCK_INIT(sc);
365
366 /*
367 * Initialize taskq and various tasks
368 */
369 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO,
370 taskqueue_thread_enqueue, &sc->sc_tq);
371 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
372 device_get_nameunit(dev));
373 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc);
374 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0);
375 mbufq_init(&sc->sc_snd, ifqmaxlen);
376
377 /*
378 * Initialize sysctl variables
379 */
380 sc->sc_fw_version = BWI_FW_VERSION3;
381 sc->sc_led_idle = (2350 * hz) / 1000;
382 sc->sc_led_ticks = ticks - sc->sc_led_idle;
383 sc->sc_led_blink = 1;
384 sc->sc_txpwr_calib = 1;
385 #ifdef BWI_DEBUG
386 sc->sc_debug = bwi_debug;
387 #endif
388 bwi_power_on(sc, 1);
389
390 error = bwi_bbp_attach(sc);
391 if (error)
392 goto fail;
393
394 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
395 if (error)
396 goto fail;
397
398 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
399 error = bwi_set_clock_delay(sc);
400 if (error)
401 goto fail;
402
403 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
404 if (error)
405 goto fail;
406
407 error = bwi_get_pwron_delay(sc);
408 if (error)
409 goto fail;
410 }
411
412 error = bwi_bus_attach(sc);
413 if (error)
414 goto fail;
415
416 bwi_get_card_flags(sc);
417
418 bwi_led_attach(sc);
419
420 for (i = 0; i < sc->sc_nmac; ++i) {
421 struct bwi_regwin *old;
422
423 mac = &sc->sc_mac[i];
424 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
425 if (error)
426 goto fail;
427
428 error = bwi_mac_lateattach(mac);
429 if (error)
430 goto fail;
431
432 error = bwi_regwin_switch(sc, old, NULL);
433 if (error)
434 goto fail;
435 }
436
437 /*
438 * XXX First MAC is known to exist
439 * TODO2
440 */
441 mac = &sc->sc_mac[0];
442 phy = &mac->mac_phy;
443
444 bwi_bbp_power_off(sc);
445
446 error = bwi_dma_alloc(sc);
447 if (error)
448 goto fail;
449
450 error = bwi_mac_fw_alloc(mac);
451 if (error)
452 goto fail;
453
454 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0);
455
456 /*
457 * Setup ratesets, phytype, channels and get MAC address
458 */
459 if (phy->phy_mode == IEEE80211_MODE_11B ||
460 phy->phy_mode == IEEE80211_MODE_11G) {
461 if (phy->phy_mode == IEEE80211_MODE_11B) {
462 ic->ic_phytype = IEEE80211_T_DS;
463 } else {
464 ic->ic_phytype = IEEE80211_T_OFDM;
465 }
466
467 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr);
468 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) {
469 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr);
470 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) {
471 device_printf(dev,
472 "invalid MAC address: %6D\n",
473 ic->ic_macaddr, ":");
474 }
475 }
476 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
477 /* TODO:11A */
478 error = ENXIO;
479 goto fail;
480 } else {
481 panic("unknown phymode %d\n", phy->phy_mode);
482 }
483
484 /* Get locale */
485 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
486 BWI_SPROM_CARD_INFO_LOCALE);
487 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
488 /* XXX use locale */
489
490 ic->ic_softc = sc;
491
492 bwi_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
493 ic->ic_channels);
494
495 ic->ic_name = device_get_nameunit(dev);
496 ic->ic_caps = IEEE80211_C_STA |
497 IEEE80211_C_SHSLOT |
498 IEEE80211_C_SHPREAMBLE |
499 IEEE80211_C_WPA |
500 IEEE80211_C_BGSCAN |
501 IEEE80211_C_MONITOR;
502 ic->ic_opmode = IEEE80211_M_STA;
503 ieee80211_ifattach(ic);
504
505 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
506
507 /* override default methods */
508 ic->ic_vap_create = bwi_vap_create;
509 ic->ic_vap_delete = bwi_vap_delete;
510 ic->ic_raw_xmit = bwi_raw_xmit;
511 ic->ic_updateslot = bwi_updateslot;
512 ic->ic_scan_start = bwi_scan_start;
513 ic->ic_scan_end = bwi_scan_end;
514 ic->ic_getradiocaps = bwi_getradiocaps;
515 ic->ic_set_channel = bwi_set_channel;
516 ic->ic_transmit = bwi_transmit;
517 ic->ic_parent = bwi_parent;
518
519 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan);
520
521 ieee80211_radiotap_attach(ic,
522 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
523 BWI_TX_RADIOTAP_PRESENT,
524 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
525 BWI_RX_RADIOTAP_PRESENT);
526
527 /*
528 * Add sysctl nodes
529 */
530 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
531 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
532 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
533 "Firmware version");
534 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
535 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
536 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
537 "# ticks before LED enters idle state");
538 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
539 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
540 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
541 "Allow LED to blink");
542 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
543 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
544 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
545 "Enable software TX power calibration");
546 #ifdef BWI_DEBUG
547 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
548 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
549 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
550 #endif
551 if (bootverbose)
552 ieee80211_announce(ic);
553
554 return (0);
555 fail:
556 BWI_LOCK_DESTROY(sc);
557 return (error);
558 }
559
560 int
561 bwi_detach(struct bwi_softc *sc)
562 {
563 struct ieee80211com *ic = &sc->sc_ic;
564 int i;
565
566 bwi_stop(sc, 1);
567 callout_drain(&sc->sc_led_blink_ch);
568 callout_drain(&sc->sc_calib_ch);
569 callout_drain(&sc->sc_watchdog_timer);
570 ieee80211_ifdetach(ic);
571
572 for (i = 0; i < sc->sc_nmac; ++i)
573 bwi_mac_detach(&sc->sc_mac[i]);
574 bwi_dma_free(sc);
575 taskqueue_free(sc->sc_tq);
576 mbufq_drain(&sc->sc_snd);
577
578 BWI_LOCK_DESTROY(sc);
579
580 return (0);
581 }
582
583 static struct ieee80211vap *
584 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
585 enum ieee80211_opmode opmode, int flags,
586 const uint8_t bssid[IEEE80211_ADDR_LEN],
587 const uint8_t mac[IEEE80211_ADDR_LEN])
588 {
589 struct bwi_vap *bvp;
590 struct ieee80211vap *vap;
591
592 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
593 return NULL;
594 bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO);
595 vap = &bvp->bv_vap;
596 /* enable s/w bmiss handling for sta mode */
597 ieee80211_vap_setup(ic, vap, name, unit, opmode,
598 flags | IEEE80211_CLONE_NOBEACONS, bssid);
599
600 /* override default methods */
601 bvp->bv_newstate = vap->iv_newstate;
602 vap->iv_newstate = bwi_newstate;
603 #if 0
604 vap->iv_update_beacon = bwi_beacon_update;
605 #endif
606 ieee80211_ratectl_init(vap);
607
608 /* complete setup */
609 ieee80211_vap_attach(vap, ieee80211_media_change,
610 ieee80211_media_status, mac);
611 ic->ic_opmode = opmode;
612 return vap;
613 }
614
615 static void
616 bwi_vap_delete(struct ieee80211vap *vap)
617 {
618 struct bwi_vap *bvp = BWI_VAP(vap);
619
620 ieee80211_ratectl_deinit(vap);
621 ieee80211_vap_detach(vap);
622 free(bvp, M_80211_VAP);
623 }
624
625 void
626 bwi_suspend(struct bwi_softc *sc)
627 {
628 bwi_stop(sc, 1);
629 }
630
631 void
632 bwi_resume(struct bwi_softc *sc)
633 {
634
635 if (sc->sc_ic.ic_nrunning > 0)
636 bwi_init(sc);
637 }
638
639 int
640 bwi_shutdown(struct bwi_softc *sc)
641 {
642 bwi_stop(sc, 1);
643 return 0;
644 }
645
646 static void
647 bwi_power_on(struct bwi_softc *sc, int with_pll)
648 {
649 uint32_t gpio_in, gpio_out, gpio_en;
650 uint16_t status;
651
652 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
653 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
654 goto back;
655
656 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
657 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
658
659 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
660 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
661 if (with_pll) {
662 /* Turn off PLL first */
663 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
664 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
665 }
666
667 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
668 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
669 DELAY(1000);
670
671 if (with_pll) {
672 /* Turn on PLL */
673 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
674 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
675 DELAY(5000);
676 }
677
678 back:
679 /* Clear "Signaled Target Abort" */
680 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
681 status &= ~PCIM_STATUS_STABORT;
682 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
683 }
684
685 static int
686 bwi_power_off(struct bwi_softc *sc, int with_pll)
687 {
688 uint32_t gpio_out, gpio_en;
689
690 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
691 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
692 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
693
694 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
695 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
696 if (with_pll) {
697 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
698 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
699 }
700
701 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
702 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
703 return 0;
704 }
705
706 int
707 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
708 struct bwi_regwin **old_rw)
709 {
710 int error;
711
712 if (old_rw != NULL)
713 *old_rw = NULL;
714
715 if (!BWI_REGWIN_EXIST(rw))
716 return EINVAL;
717
718 if (sc->sc_cur_regwin != rw) {
719 error = bwi_regwin_select(sc, rw->rw_id);
720 if (error) {
721 device_printf(sc->sc_dev, "can't select regwin %d\n",
722 rw->rw_id);
723 return error;
724 }
725 }
726
727 if (old_rw != NULL)
728 *old_rw = sc->sc_cur_regwin;
729 sc->sc_cur_regwin = rw;
730 return 0;
731 }
732
733 static int
734 bwi_regwin_select(struct bwi_softc *sc, int id)
735 {
736 uint32_t win = BWI_PCIM_REGWIN(id);
737 int i;
738
739 #define RETRY_MAX 50
740 for (i = 0; i < RETRY_MAX; ++i) {
741 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
742 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
743 return 0;
744 DELAY(10);
745 }
746 #undef RETRY_MAX
747
748 return ENXIO;
749 }
750
751 static void
752 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
753 {
754 uint32_t val;
755
756 val = CSR_READ_4(sc, BWI_ID_HI);
757 *type = BWI_ID_HI_REGWIN_TYPE(val);
758 *rev = BWI_ID_HI_REGWIN_REV(val);
759
760 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
761 "vendor 0x%04x\n", *type, *rev,
762 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
763 }
764
765 static int
766 bwi_bbp_attach(struct bwi_softc *sc)
767 {
768 uint16_t bbp_id, rw_type;
769 uint8_t rw_rev;
770 uint32_t info;
771 int error, nregwin, i;
772
773 /*
774 * Get 0th regwin information
775 * NOTE: 0th regwin should exist
776 */
777 error = bwi_regwin_select(sc, 0);
778 if (error) {
779 device_printf(sc->sc_dev, "can't select regwin 0\n");
780 return error;
781 }
782 bwi_regwin_info(sc, &rw_type, &rw_rev);
783
784 /*
785 * Find out BBP id
786 */
787 bbp_id = 0;
788 info = 0;
789 if (rw_type == BWI_REGWIN_T_COM) {
790 info = CSR_READ_4(sc, BWI_INFO);
791 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
792
793 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
794
795 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
796 } else {
797 for (i = 0; i < nitems(bwi_bbpid_map); ++i) {
798 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min &&
799 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) {
800 bbp_id = bwi_bbpid_map[i].bbp_id;
801 break;
802 }
803 }
804 if (bbp_id == 0) {
805 device_printf(sc->sc_dev, "no BBP id for device id "
806 "0x%04x\n", sc->sc_pci_did);
807 return ENXIO;
808 }
809
810 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) |
811 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
812 }
813
814 /*
815 * Find out number of regwins
816 */
817 nregwin = 0;
818 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
819 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
820 } else {
821 for (i = 0; i < nitems(bwi_regwin_count); ++i) {
822 if (bwi_regwin_count[i].bbp_id == bbp_id) {
823 nregwin = bwi_regwin_count[i].nregwin;
824 break;
825 }
826 }
827 if (nregwin == 0) {
828 device_printf(sc->sc_dev, "no number of win for "
829 "BBP id 0x%04x\n", bbp_id);
830 return ENXIO;
831 }
832 }
833
834 /* Record BBP id/rev for later using */
835 sc->sc_bbp_id = bbp_id;
836 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
837 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
838 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
839 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
840
841 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
842 nregwin, sc->sc_cap);
843
844 /*
845 * Create rest of the regwins
846 */
847
848 /* Don't re-create common regwin, if it is already created */
849 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
850
851 for (; i < nregwin; ++i) {
852 /*
853 * Get regwin information
854 */
855 error = bwi_regwin_select(sc, i);
856 if (error) {
857 device_printf(sc->sc_dev,
858 "can't select regwin %d\n", i);
859 return error;
860 }
861 bwi_regwin_info(sc, &rw_type, &rw_rev);
862
863 /*
864 * Try attach:
865 * 1) Bus (PCI/PCIE) regwin
866 * 2) MAC regwin
867 * Ignore rest types of regwin
868 */
869 if (rw_type == BWI_REGWIN_T_BUSPCI ||
870 rw_type == BWI_REGWIN_T_BUSPCIE) {
871 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
872 device_printf(sc->sc_dev,
873 "bus regwin already exists\n");
874 } else {
875 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
876 rw_type, rw_rev);
877 }
878 } else if (rw_type == BWI_REGWIN_T_MAC) {
879 /* XXX ignore return value */
880 bwi_mac_attach(sc, i, rw_rev);
881 }
882 }
883
884 /* At least one MAC shold exist */
885 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
886 device_printf(sc->sc_dev, "no MAC was found\n");
887 return ENXIO;
888 }
889 KASSERT(sc->sc_nmac > 0, ("no mac's"));
890
891 /* Bus regwin must exist */
892 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
893 device_printf(sc->sc_dev, "no bus regwin was found\n");
894 return ENXIO;
895 }
896
897 /* Start with first MAC */
898 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
899 if (error)
900 return error;
901
902 return 0;
903 }
904
905 int
906 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
907 {
908 struct bwi_regwin *old, *bus;
909 uint32_t val;
910 int error;
911
912 bus = &sc->sc_bus_regwin;
913 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin"));
914
915 /*
916 * Tell bus to generate requested interrupts
917 */
918 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
919 /*
920 * NOTE: Read BWI_FLAGS from MAC regwin
921 */
922 val = CSR_READ_4(sc, BWI_FLAGS);
923
924 error = bwi_regwin_switch(sc, bus, &old);
925 if (error)
926 return error;
927
928 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
929 } else {
930 uint32_t mac_mask;
931
932 mac_mask = 1 << mac->mac_id;
933
934 error = bwi_regwin_switch(sc, bus, &old);
935 if (error)
936 return error;
937
938 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
939 val |= mac_mask << 8;
940 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
941 }
942
943 if (sc->sc_flags & BWI_F_BUS_INITED)
944 goto back;
945
946 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
947 /*
948 * Enable prefetch and burst
949 */
950 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
951 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
952
953 if (bus->rw_rev < 5) {
954 struct bwi_regwin *com = &sc->sc_com_regwin;
955
956 /*
957 * Configure timeouts for bus operation
958 */
959
960 /*
961 * Set service timeout and request timeout
962 */
963 CSR_SETBITS_4(sc, BWI_CONF_LO,
964 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
965 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
966
967 /*
968 * If there is common regwin, we switch to that regwin
969 * and switch back to bus regwin once we have done.
970 */
971 if (BWI_REGWIN_EXIST(com)) {
972 error = bwi_regwin_switch(sc, com, NULL);
973 if (error)
974 return error;
975 }
976
977 /* Let bus know what we have changed */
978 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
979 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
980 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
981 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
982
983 if (BWI_REGWIN_EXIST(com)) {
984 error = bwi_regwin_switch(sc, bus, NULL);
985 if (error)
986 return error;
987 }
988 } else if (bus->rw_rev >= 11) {
989 /*
990 * Enable memory read multiple
991 */
992 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
993 }
994 } else {
995 /* TODO:PCIE */
996 }
997
998 sc->sc_flags |= BWI_F_BUS_INITED;
999 back:
1000 return bwi_regwin_switch(sc, old, NULL);
1001 }
1002
1003 static void
1004 bwi_get_card_flags(struct bwi_softc *sc)
1005 {
1006 #define PCI_VENDOR_APPLE 0x106b
1007 #define PCI_VENDOR_DELL 0x1028
1008 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1009 if (sc->sc_card_flags == 0xffff)
1010 sc->sc_card_flags = 0;
1011
1012 if (sc->sc_pci_subvid == PCI_VENDOR_DELL &&
1013 sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1014 sc->sc_pci_revid == 0x74)
1015 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST;
1016
1017 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1018 sc->sc_pci_subdid == 0x4e && /* XXX */
1019 sc->sc_pci_revid > 0x40)
1020 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1021
1022 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1023 #undef PCI_VENDOR_DELL
1024 #undef PCI_VENDOR_APPLE
1025 }
1026
1027 static void
1028 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1029 {
1030 int i;
1031
1032 for (i = 0; i < 3; ++i) {
1033 *((uint16_t *)eaddr + i) =
1034 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1035 }
1036 }
1037
1038 static void
1039 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1040 {
1041 struct bwi_regwin *com;
1042 uint32_t val;
1043 u_int div;
1044 int src;
1045
1046 bzero(freq, sizeof(*freq));
1047 com = &sc->sc_com_regwin;
1048
1049 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist"));
1050 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin"));
1051 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode"));
1052
1053 /*
1054 * Calculate clock frequency
1055 */
1056 src = -1;
1057 div = 0;
1058 if (com->rw_rev < 6) {
1059 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1060 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1061 src = BWI_CLKSRC_PCI;
1062 div = 64;
1063 } else {
1064 src = BWI_CLKSRC_CS_OSC;
1065 div = 32;
1066 }
1067 } else if (com->rw_rev < 10) {
1068 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1069
1070 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1071 if (src == BWI_CLKSRC_LP_OSC) {
1072 div = 1;
1073 } else {
1074 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1075
1076 /* Unknown source */
1077 if (src >= BWI_CLKSRC_MAX)
1078 src = BWI_CLKSRC_CS_OSC;
1079 }
1080 } else {
1081 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1082
1083 src = BWI_CLKSRC_CS_OSC;
1084 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1085 }
1086
1087 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src));
1088 KASSERT(div != 0, ("div zero"));
1089
1090 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1091 src == BWI_CLKSRC_PCI ? "PCI" :
1092 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1093
1094 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1095 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1096
1097 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1098 freq->clkfreq_min, freq->clkfreq_max);
1099 }
1100
1101 static int
1102 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1103 {
1104 struct bwi_regwin *old, *com;
1105 uint32_t clk_ctrl, clk_src;
1106 int error, pwr_off = 0;
1107
1108 com = &sc->sc_com_regwin;
1109 if (!BWI_REGWIN_EXIST(com))
1110 return 0;
1111
1112 if (com->rw_rev >= 10 || com->rw_rev < 6)
1113 return 0;
1114
1115 /*
1116 * For common regwin whose rev is [6, 10), the chip
1117 * must be capable to change clock mode.
1118 */
1119 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1120 return 0;
1121
1122 error = bwi_regwin_switch(sc, com, &old);
1123 if (error)
1124 return error;
1125
1126 if (clk_mode == BWI_CLOCK_MODE_FAST)
1127 bwi_power_on(sc, 0); /* Don't turn on PLL */
1128
1129 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1130 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1131
1132 switch (clk_mode) {
1133 case BWI_CLOCK_MODE_FAST:
1134 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1135 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1136 break;
1137 case BWI_CLOCK_MODE_SLOW:
1138 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1139 break;
1140 case BWI_CLOCK_MODE_DYN:
1141 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1142 BWI_CLOCK_CTRL_IGNPLL |
1143 BWI_CLOCK_CTRL_NODYN);
1144 if (clk_src != BWI_CLKSRC_CS_OSC) {
1145 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1146 pwr_off = 1;
1147 }
1148 break;
1149 }
1150 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1151
1152 if (pwr_off)
1153 bwi_power_off(sc, 0); /* Leave PLL as it is */
1154
1155 return bwi_regwin_switch(sc, old, NULL);
1156 }
1157
1158 static int
1159 bwi_set_clock_delay(struct bwi_softc *sc)
1160 {
1161 struct bwi_regwin *old, *com;
1162 int error;
1163
1164 com = &sc->sc_com_regwin;
1165 if (!BWI_REGWIN_EXIST(com))
1166 return 0;
1167
1168 error = bwi_regwin_switch(sc, com, &old);
1169 if (error)
1170 return error;
1171
1172 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1173 if (sc->sc_bbp_rev == 0)
1174 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1175 else if (sc->sc_bbp_rev == 1)
1176 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1177 }
1178
1179 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1180 if (com->rw_rev >= 10) {
1181 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1182 } else {
1183 struct bwi_clock_freq freq;
1184
1185 bwi_get_clock_freq(sc, &freq);
1186 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1187 howmany(freq.clkfreq_max * 150, 1000000));
1188 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1189 howmany(freq.clkfreq_max * 15, 1000000));
1190 }
1191 }
1192
1193 return bwi_regwin_switch(sc, old, NULL);
1194 }
1195
1196 static void
1197 bwi_init(struct bwi_softc *sc)
1198 {
1199 struct ieee80211com *ic = &sc->sc_ic;
1200
1201 BWI_LOCK(sc);
1202 bwi_init_statechg(sc, 1);
1203 BWI_UNLOCK(sc);
1204
1205 if (sc->sc_flags & BWI_F_RUNNING)
1206 ieee80211_start_all(ic); /* start all vap's */
1207 }
1208
1209 static void
1210 bwi_init_statechg(struct bwi_softc *sc, int statechg)
1211 {
1212 struct bwi_mac *mac;
1213 int error;
1214
1215 BWI_ASSERT_LOCKED(sc);
1216
1217 bwi_stop_locked(sc, statechg);
1218
1219 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1220
1221 /* TODO: 2 MAC */
1222
1223 mac = &sc->sc_mac[0];
1224 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1225 if (error) {
1226 device_printf(sc->sc_dev, "%s: error %d on regwin switch\n",
1227 __func__, error);
1228 goto bad;
1229 }
1230 error = bwi_mac_init(mac);
1231 if (error) {
1232 device_printf(sc->sc_dev, "%s: error %d on MAC init\n",
1233 __func__, error);
1234 goto bad;
1235 }
1236
1237 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1238
1239 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1240 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr);
1241
1242 bwi_mac_reset_hwkeys(mac);
1243
1244 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1245 int i;
1246
1247 #define NRETRY 1000
1248 /*
1249 * Drain any possible pending TX status
1250 */
1251 for (i = 0; i < NRETRY; ++i) {
1252 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1253 BWI_TXSTATUS0_VALID) == 0)
1254 break;
1255 CSR_READ_4(sc, BWI_TXSTATUS1);
1256 }
1257 if (i == NRETRY)
1258 device_printf(sc->sc_dev,
1259 "%s: can't drain TX status\n", __func__);
1260 #undef NRETRY
1261 }
1262
1263 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1264 bwi_mac_updateslot(mac, 1);
1265
1266 /* Start MAC */
1267 error = bwi_mac_start(mac);
1268 if (error) {
1269 device_printf(sc->sc_dev, "%s: error %d starting MAC\n",
1270 __func__, error);
1271 goto bad;
1272 }
1273
1274 /* Clear stop flag before enabling interrupt */
1275 sc->sc_flags &= ~BWI_F_STOP;
1276 sc->sc_flags |= BWI_F_RUNNING;
1277 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1278
1279 /* Enable intrs */
1280 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1281 return;
1282 bad:
1283 bwi_stop_locked(sc, 1);
1284 }
1285
1286 static void
1287 bwi_parent(struct ieee80211com *ic)
1288 {
1289 struct bwi_softc *sc = ic->ic_softc;
1290 int startall = 0;
1291
1292 BWI_LOCK(sc);
1293 if (ic->ic_nrunning > 0) {
1294 struct bwi_mac *mac;
1295 int promisc = -1;
1296
1297 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1298 ("current regwin type %d",
1299 sc->sc_cur_regwin->rw_type));
1300 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1301
1302 if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) {
1303 promisc = 1;
1304 sc->sc_flags |= BWI_F_PROMISC;
1305 } else if (ic->ic_promisc == 0 &&
1306 (sc->sc_flags & BWI_F_PROMISC) != 0) {
1307 promisc = 0;
1308 sc->sc_flags &= ~BWI_F_PROMISC;
1309 }
1310
1311 if (promisc >= 0)
1312 bwi_mac_set_promisc(mac, promisc);
1313 }
1314 if (ic->ic_nrunning > 0) {
1315 if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1316 bwi_init_statechg(sc, 1);
1317 startall = 1;
1318 }
1319 } else if (sc->sc_flags & BWI_F_RUNNING)
1320 bwi_stop_locked(sc, 1);
1321 BWI_UNLOCK(sc);
1322 if (startall)
1323 ieee80211_start_all(ic);
1324 }
1325
1326 static int
1327 bwi_transmit(struct ieee80211com *ic, struct mbuf *m)
1328 {
1329 struct bwi_softc *sc = ic->ic_softc;
1330 int error;
1331
1332 BWI_LOCK(sc);
1333 if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1334 BWI_UNLOCK(sc);
1335 return (ENXIO);
1336 }
1337 error = mbufq_enqueue(&sc->sc_snd, m);
1338 if (error) {
1339 BWI_UNLOCK(sc);
1340 return (error);
1341 }
1342 bwi_start_locked(sc);
1343 BWI_UNLOCK(sc);
1344 return (0);
1345 }
1346
1347 static void
1348 bwi_start_locked(struct bwi_softc *sc)
1349 {
1350 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1351 struct ieee80211_frame *wh;
1352 struct ieee80211_node *ni;
1353 struct mbuf *m;
1354 int trans, idx;
1355
1356 BWI_ASSERT_LOCKED(sc);
1357
1358 trans = 0;
1359 idx = tbd->tbd_idx;
1360
1361 while (tbd->tbd_buf[idx].tb_mbuf == NULL &&
1362 tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC &&
1363 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1364 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1365 wh = mtod(m, struct ieee80211_frame *);
1366 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 &&
1367 ieee80211_crypto_encap(ni, m) == NULL) {
1368 if_inc_counter(ni->ni_vap->iv_ifp,
1369 IFCOUNTER_OERRORS, 1);
1370 ieee80211_free_node(ni);
1371 m_freem(m);
1372 continue;
1373 }
1374 if (bwi_encap(sc, idx, m, ni) != 0) {
1375 /* 'm' is freed in bwi_encap() if we reach here */
1376 if (ni != NULL) {
1377 if_inc_counter(ni->ni_vap->iv_ifp,
1378 IFCOUNTER_OERRORS, 1);
1379 ieee80211_free_node(ni);
1380 } else
1381 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1382 continue;
1383 }
1384 trans = 1;
1385 tbd->tbd_used++;
1386 idx = (idx + 1) % BWI_TX_NDESC;
1387 }
1388
1389 tbd->tbd_idx = idx;
1390 if (trans)
1391 sc->sc_tx_timer = 5;
1392 }
1393
1394 static int
1395 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1396 const struct ieee80211_bpf_params *params)
1397 {
1398 struct ieee80211com *ic = ni->ni_ic;
1399 struct bwi_softc *sc = ic->ic_softc;
1400 /* XXX wme? */
1401 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1402 int idx, error;
1403
1404 if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1405 m_freem(m);
1406 return ENETDOWN;
1407 }
1408
1409 BWI_LOCK(sc);
1410 idx = tbd->tbd_idx;
1411 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx));
1412 if (params == NULL) {
1413 /*
1414 * Legacy path; interpret frame contents to decide
1415 * precisely how to send the frame.
1416 */
1417 error = bwi_encap(sc, idx, m, ni);
1418 } else {
1419 /*
1420 * Caller supplied explicit parameters to use in
1421 * sending the frame.
1422 */
1423 error = bwi_encap_raw(sc, idx, m, ni, params);
1424 }
1425 if (error == 0) {
1426 tbd->tbd_used++;
1427 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC;
1428 sc->sc_tx_timer = 5;
1429 }
1430 BWI_UNLOCK(sc);
1431 return error;
1432 }
1433
1434 static void
1435 bwi_watchdog(void *arg)
1436 {
1437 struct bwi_softc *sc;
1438
1439 sc = arg;
1440 BWI_ASSERT_LOCKED(sc);
1441 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) {
1442 device_printf(sc->sc_dev, "watchdog timeout\n");
1443 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1444 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1445 }
1446 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1447 }
1448
1449 static void
1450 bwi_stop(struct bwi_softc *sc, int statechg)
1451 {
1452 BWI_LOCK(sc);
1453 bwi_stop_locked(sc, statechg);
1454 BWI_UNLOCK(sc);
1455 }
1456
1457 static void
1458 bwi_stop_locked(struct bwi_softc *sc, int statechg)
1459 {
1460 struct bwi_mac *mac;
1461 int i, error, pwr_off = 0;
1462
1463 BWI_ASSERT_LOCKED(sc);
1464
1465 callout_stop(&sc->sc_calib_ch);
1466 callout_stop(&sc->sc_led_blink_ch);
1467 sc->sc_led_blinking = 0;
1468 sc->sc_flags |= BWI_F_STOP;
1469
1470 if (sc->sc_flags & BWI_F_RUNNING) {
1471 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1472 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1473 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1474
1475 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1476 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1477 bwi_mac_stop(mac);
1478 }
1479
1480 for (i = 0; i < sc->sc_nmac; ++i) {
1481 struct bwi_regwin *old_rw;
1482
1483 mac = &sc->sc_mac[i];
1484 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1485 continue;
1486
1487 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1488 if (error)
1489 continue;
1490
1491 bwi_mac_shutdown(mac);
1492 pwr_off = 1;
1493
1494 bwi_regwin_switch(sc, old_rw, NULL);
1495 }
1496
1497 if (pwr_off)
1498 bwi_bbp_power_off(sc);
1499
1500 sc->sc_tx_timer = 0;
1501 callout_stop(&sc->sc_watchdog_timer);
1502 sc->sc_flags &= ~BWI_F_RUNNING;
1503 }
1504
1505 void
1506 bwi_intr(void *xsc)
1507 {
1508 struct epoch_tracker et;
1509 struct bwi_softc *sc = xsc;
1510 struct bwi_mac *mac;
1511 uint32_t intr_status;
1512 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1513 int i, txrx_error, tx = 0, rx_data = -1;
1514
1515 BWI_LOCK(sc);
1516
1517 if ((sc->sc_flags & BWI_F_RUNNING) == 0 ||
1518 (sc->sc_flags & BWI_F_STOP)) {
1519 BWI_UNLOCK(sc);
1520 return;
1521 }
1522 /*
1523 * Get interrupt status
1524 */
1525 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1526 if (intr_status == 0xffffffff) { /* Not for us */
1527 BWI_UNLOCK(sc);
1528 return;
1529 }
1530
1531 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1532
1533 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1534 if (intr_status == 0) { /* Nothing is interesting */
1535 BWI_UNLOCK(sc);
1536 return;
1537 }
1538
1539 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1540 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1541 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1542
1543 txrx_error = 0;
1544 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1545 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1546 uint32_t mask;
1547
1548 if (BWI_TXRX_IS_RX(i))
1549 mask = BWI_TXRX_RX_INTRS;
1550 else
1551 mask = BWI_TXRX_TX_INTRS;
1552
1553 txrx_intr_status[i] =
1554 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1555
1556 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1557 i, txrx_intr_status[i]);
1558
1559 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1560 device_printf(sc->sc_dev,
1561 "%s: intr fatal TX/RX (%d) error 0x%08x\n",
1562 __func__, i, txrx_intr_status[i]);
1563 txrx_error = 1;
1564 }
1565 }
1566 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1567
1568 /*
1569 * Acknowledge interrupt
1570 */
1571 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1572
1573 for (i = 0; i < BWI_TXRX_NRING; ++i)
1574 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1575
1576 /* Disable all interrupts */
1577 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1578
1579 /*
1580 * http://bcm-specs.sipsolutions.net/Interrupts
1581 * Says for this bit (0x800):
1582 * "Fatal Error
1583 *
1584 * We got this one while testing things when by accident the
1585 * template ram wasn't set to big endian when it should have
1586 * been after writing the initial values. It keeps on being
1587 * triggered, the only way to stop it seems to shut down the
1588 * chip."
1589 *
1590 * Suggesting that we should never get it and if we do we're not
1591 * feeding TX packets into the MAC correctly if we do... Apparently,
1592 * it is valid only on mac version 5 and higher, but I couldn't
1593 * find a reference for that... Since I see them from time to time
1594 * on my card, this suggests an error in the tx path still...
1595 */
1596 if (intr_status & BWI_INTR_PHY_TXERR) {
1597 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1598 device_printf(sc->sc_dev, "%s: intr PHY TX error\n",
1599 __func__);
1600 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1601 BWI_UNLOCK(sc);
1602 return;
1603 }
1604 }
1605
1606 if (txrx_error) {
1607 /* TODO: reset device */
1608 }
1609
1610 if (intr_status & BWI_INTR_TBTT)
1611 bwi_mac_config_ps(mac);
1612
1613 if (intr_status & BWI_INTR_EO_ATIM)
1614 device_printf(sc->sc_dev, "EO_ATIM\n");
1615
1616 if (intr_status & BWI_INTR_PMQ) {
1617 for (;;) {
1618 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1619 break;
1620 }
1621 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1622 }
1623
1624 if (intr_status & BWI_INTR_NOISE)
1625 device_printf(sc->sc_dev, "intr noise\n");
1626
1627 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) {
1628 NET_EPOCH_ENTER(et);
1629 rx_data = sc->sc_rxeof(sc);
1630 NET_EPOCH_EXIT(et);
1631 if (sc->sc_flags & BWI_F_STOP) {
1632 BWI_UNLOCK(sc);
1633 return;
1634 }
1635 }
1636
1637 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1638 sc->sc_txeof_status(sc);
1639 tx = 1;
1640 }
1641
1642 if (intr_status & BWI_INTR_TX_DONE) {
1643 bwi_txeof(sc);
1644 tx = 1;
1645 }
1646
1647 /* Re-enable interrupts */
1648 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1649
1650 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1651 int evt = BWI_LED_EVENT_NONE;
1652
1653 if (tx && rx_data > 0) {
1654 if (sc->sc_rx_rate > sc->sc_tx_rate)
1655 evt = BWI_LED_EVENT_RX;
1656 else
1657 evt = BWI_LED_EVENT_TX;
1658 } else if (tx) {
1659 evt = BWI_LED_EVENT_TX;
1660 } else if (rx_data > 0) {
1661 evt = BWI_LED_EVENT_RX;
1662 } else if (rx_data == 0) {
1663 evt = BWI_LED_EVENT_POLL;
1664 }
1665
1666 if (evt != BWI_LED_EVENT_NONE)
1667 bwi_led_event(sc, evt);
1668 }
1669
1670 BWI_UNLOCK(sc);
1671 }
1672
1673 static void
1674 bwi_scan_start(struct ieee80211com *ic)
1675 {
1676 struct bwi_softc *sc = ic->ic_softc;
1677
1678 BWI_LOCK(sc);
1679 /* Enable MAC beacon promiscuity */
1680 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1681 BWI_UNLOCK(sc);
1682 }
1683
1684 static void
1685 bwi_getradiocaps(struct ieee80211com *ic,
1686 int maxchans, int *nchans, struct ieee80211_channel chans[])
1687 {
1688 struct bwi_softc *sc = ic->ic_softc;
1689 struct bwi_mac *mac;
1690 struct bwi_phy *phy;
1691 uint8_t bands[IEEE80211_MODE_BYTES];
1692
1693 /*
1694 * XXX First MAC is known to exist
1695 * TODO2
1696 */
1697 mac = &sc->sc_mac[0];
1698 phy = &mac->mac_phy;
1699
1700 memset(bands, 0, sizeof(bands));
1701 switch (phy->phy_mode) {
1702 case IEEE80211_MODE_11G:
1703 setbit(bands, IEEE80211_MODE_11G);
1704 /* FALLTHROUGH */
1705 case IEEE80211_MODE_11B:
1706 setbit(bands, IEEE80211_MODE_11B);
1707 break;
1708 case IEEE80211_MODE_11A:
1709 /* TODO:11A */
1710 setbit(bands, IEEE80211_MODE_11A);
1711 device_printf(sc->sc_dev, "no 11a support\n");
1712 return;
1713 default:
1714 panic("unknown phymode %d\n", phy->phy_mode);
1715 }
1716
1717 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
1718 }
1719
1720 static void
1721 bwi_set_channel(struct ieee80211com *ic)
1722 {
1723 struct bwi_softc *sc = ic->ic_softc;
1724 struct ieee80211_channel *c = ic->ic_curchan;
1725 struct bwi_mac *mac;
1726
1727 BWI_LOCK(sc);
1728 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1729 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1730 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1731 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0);
1732
1733 sc->sc_rates = ieee80211_get_ratetable(c);
1734 BWI_UNLOCK(sc);
1735 }
1736
1737 static void
1738 bwi_scan_end(struct ieee80211com *ic)
1739 {
1740 struct bwi_softc *sc = ic->ic_softc;
1741
1742 BWI_LOCK(sc);
1743 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1744 BWI_UNLOCK(sc);
1745 }
1746
1747 static int
1748 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1749 {
1750 struct bwi_vap *bvp = BWI_VAP(vap);
1751 struct ieee80211com *ic= vap->iv_ic;
1752 struct bwi_softc *sc = ic->ic_softc;
1753 enum ieee80211_state ostate = vap->iv_state;
1754 struct bwi_mac *mac;
1755 int error;
1756
1757 BWI_LOCK(sc);
1758
1759 callout_stop(&sc->sc_calib_ch);
1760
1761 if (nstate == IEEE80211_S_INIT)
1762 sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1763
1764 bwi_led_newstate(sc, nstate);
1765
1766 error = bvp->bv_newstate(vap, nstate, arg);
1767 if (error != 0)
1768 goto back;
1769
1770 /*
1771 * Clear the BSSID when we stop a STA
1772 */
1773 if (vap->iv_opmode == IEEE80211_M_STA) {
1774 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) {
1775 /*
1776 * Clear out the BSSID. If we reassociate to
1777 * the same AP, this will reinialize things
1778 * correctly...
1779 */
1780 if (ic->ic_opmode == IEEE80211_M_STA &&
1781 !(sc->sc_flags & BWI_F_STOP))
1782 bwi_set_bssid(sc, bwi_zero_addr);
1783 }
1784 }
1785
1786 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
1787 /* Nothing to do */
1788 } else if (nstate == IEEE80211_S_RUN) {
1789 bwi_set_bssid(sc, vap->iv_bss->ni_bssid);
1790
1791 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1792 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1793 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1794
1795 /* Initial TX power calibration */
1796 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1797 #ifdef notyet
1798 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1799 #else
1800 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1801 #endif
1802
1803 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
1804 }
1805 back:
1806 BWI_UNLOCK(sc);
1807
1808 return error;
1809 }
1810
1811 static int
1812 bwi_dma_alloc(struct bwi_softc *sc)
1813 {
1814 int error, i, has_txstats;
1815 bus_addr_t lowaddr = 0;
1816 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1817 uint32_t txrx_ctrl_step = 0;
1818
1819 has_txstats = 0;
1820 for (i = 0; i < sc->sc_nmac; ++i) {
1821 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1822 has_txstats = 1;
1823 break;
1824 }
1825 }
1826
1827 switch (sc->sc_bus_space) {
1828 case BWI_BUS_SPACE_30BIT:
1829 case BWI_BUS_SPACE_32BIT:
1830 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1831 lowaddr = BWI_BUS_SPACE_MAXADDR;
1832 else
1833 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1834 desc_sz = sizeof(struct bwi_desc32);
1835 txrx_ctrl_step = 0x20;
1836
1837 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1838 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1839 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1840 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1841 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1842 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1843 sc->sc_rxeof = bwi_rxeof32;
1844 sc->sc_start_tx = bwi_start_tx32;
1845 if (has_txstats) {
1846 sc->sc_init_txstats = bwi_init_txstats32;
1847 sc->sc_free_txstats = bwi_free_txstats32;
1848 sc->sc_txeof_status = bwi_txeof_status32;
1849 }
1850 break;
1851
1852 case BWI_BUS_SPACE_64BIT:
1853 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
1854 desc_sz = sizeof(struct bwi_desc64);
1855 txrx_ctrl_step = 0x40;
1856
1857 sc->sc_init_tx_ring = bwi_init_tx_ring64;
1858 sc->sc_free_tx_ring = bwi_free_tx_ring64;
1859 sc->sc_init_rx_ring = bwi_init_rx_ring64;
1860 sc->sc_free_rx_ring = bwi_free_rx_ring64;
1861 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1862 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1863 sc->sc_rxeof = bwi_rxeof64;
1864 sc->sc_start_tx = bwi_start_tx64;
1865 if (has_txstats) {
1866 sc->sc_init_txstats = bwi_init_txstats64;
1867 sc->sc_free_txstats = bwi_free_txstats64;
1868 sc->sc_txeof_status = bwi_txeof_status64;
1869 }
1870 break;
1871 }
1872
1873 KASSERT(lowaddr != 0, ("lowaddr zero"));
1874 KASSERT(desc_sz != 0, ("desc_sz zero"));
1875 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero"));
1876
1877 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
1878 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
1879
1880 /*
1881 * Create top level DMA tag
1882 */
1883 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
1884 BWI_ALIGN, 0, /* alignment, bounds */
1885 lowaddr, /* lowaddr */
1886 BUS_SPACE_MAXADDR, /* highaddr */
1887 NULL, NULL, /* filter, filterarg */
1888 BUS_SPACE_MAXSIZE, /* maxsize */
1889 BUS_SPACE_UNRESTRICTED, /* nsegments */
1890 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1891 0, /* flags */
1892 NULL, NULL, /* lockfunc, lockarg */
1893 &sc->sc_parent_dtag);
1894 if (error) {
1895 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
1896 return error;
1897 }
1898
1899 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
1900
1901 /*
1902 * Create TX ring DMA stuffs
1903 */
1904 error = bus_dma_tag_create(sc->sc_parent_dtag,
1905 BWI_RING_ALIGN, 0,
1906 BUS_SPACE_MAXADDR,
1907 BUS_SPACE_MAXADDR,
1908 NULL, NULL,
1909 tx_ring_sz,
1910 1,
1911 tx_ring_sz,
1912 0,
1913 NULL, NULL,
1914 &sc->sc_txring_dtag);
1915 if (error) {
1916 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
1917 return error;
1918 }
1919
1920 for (i = 0; i < BWI_TX_NRING; ++i) {
1921 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
1922 &sc->sc_tx_rdata[i], tx_ring_sz,
1923 TXRX_CTRL(i));
1924 if (error) {
1925 device_printf(sc->sc_dev, "%dth TX ring "
1926 "DMA alloc failed\n", i);
1927 return error;
1928 }
1929 }
1930
1931 /*
1932 * Create RX ring DMA stuffs
1933 */
1934 error = bus_dma_tag_create(sc->sc_parent_dtag,
1935 BWI_RING_ALIGN, 0,
1936 BUS_SPACE_MAXADDR,
1937 BUS_SPACE_MAXADDR,
1938 NULL, NULL,
1939 rx_ring_sz,
1940 1,
1941 rx_ring_sz,
1942 0,
1943 NULL, NULL,
1944 &sc->sc_rxring_dtag);
1945 if (error) {
1946 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
1947 return error;
1948 }
1949
1950 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
1951 rx_ring_sz, TXRX_CTRL(0));
1952 if (error) {
1953 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
1954 return error;
1955 }
1956
1957 if (has_txstats) {
1958 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
1959 if (error) {
1960 device_printf(sc->sc_dev,
1961 "TX stats DMA alloc failed\n");
1962 return error;
1963 }
1964 }
1965
1966 #undef TXRX_CTRL
1967
1968 return bwi_dma_mbuf_create(sc);
1969 }
1970
1971 static void
1972 bwi_dma_free(struct bwi_softc *sc)
1973 {
1974 if (sc->sc_txring_dtag != NULL) {
1975 int i;
1976
1977 for (i = 0; i < BWI_TX_NRING; ++i) {
1978 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
1979
1980 if (rd->rdata_desc != NULL) {
1981 bus_dmamap_unload(sc->sc_txring_dtag,
1982 rd->rdata_dmap);
1983 bus_dmamem_free(sc->sc_txring_dtag,
1984 rd->rdata_desc,
1985 rd->rdata_dmap);
1986 }
1987 }
1988 bus_dma_tag_destroy(sc->sc_txring_dtag);
1989 }
1990
1991 if (sc->sc_rxring_dtag != NULL) {
1992 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
1993
1994 if (rd->rdata_desc != NULL) {
1995 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
1996 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
1997 rd->rdata_dmap);
1998 }
1999 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2000 }
2001
2002 bwi_dma_txstats_free(sc);
2003 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2004
2005 if (sc->sc_parent_dtag != NULL)
2006 bus_dma_tag_destroy(sc->sc_parent_dtag);
2007 }
2008
2009 static int
2010 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2011 struct bwi_ring_data *rd, bus_size_t size,
2012 uint32_t txrx_ctrl)
2013 {
2014 int error;
2015
2016 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2017 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2018 &rd->rdata_dmap);
2019 if (error) {
2020 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2021 return error;
2022 }
2023
2024 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2025 bwi_dma_ring_addr, &rd->rdata_paddr,
2026 BUS_DMA_NOWAIT);
2027 if (error) {
2028 device_printf(sc->sc_dev, "can't load DMA mem\n");
2029 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2030 rd->rdata_desc = NULL;
2031 return error;
2032 }
2033
2034 rd->rdata_txrx_ctrl = txrx_ctrl;
2035 return 0;
2036 }
2037
2038 static int
2039 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2040 bus_size_t desc_sz)
2041 {
2042 struct bwi_txstats_data *st;
2043 bus_size_t dma_size;
2044 int error;
2045
2046 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO);
2047 if (st == NULL) {
2048 device_printf(sc->sc_dev, "can't allocate txstats data\n");
2049 return ENOMEM;
2050 }
2051 sc->sc_txstats = st;
2052
2053 /*
2054 * Create TX stats descriptor DMA stuffs
2055 */
2056 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2057
2058 error = bus_dma_tag_create(sc->sc_parent_dtag,
2059 BWI_RING_ALIGN,
2060 0,
2061 BUS_SPACE_MAXADDR,
2062 BUS_SPACE_MAXADDR,
2063 NULL, NULL,
2064 dma_size,
2065 1,
2066 dma_size,
2067 0,
2068 NULL, NULL,
2069 &st->stats_ring_dtag);
2070 if (error) {
2071 device_printf(sc->sc_dev, "can't create txstats ring "
2072 "DMA tag\n");
2073 return error;
2074 }
2075
2076 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2077 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2078 &st->stats_ring_dmap);
2079 if (error) {
2080 device_printf(sc->sc_dev, "can't allocate txstats ring "
2081 "DMA mem\n");
2082 bus_dma_tag_destroy(st->stats_ring_dtag);
2083 st->stats_ring_dtag = NULL;
2084 return error;
2085 }
2086
2087 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2088 st->stats_ring, dma_size,
2089 bwi_dma_ring_addr, &st->stats_ring_paddr,
2090 BUS_DMA_NOWAIT);
2091 if (error) {
2092 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2093 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2094 st->stats_ring_dmap);
2095 bus_dma_tag_destroy(st->stats_ring_dtag);
2096 st->stats_ring_dtag = NULL;
2097 return error;
2098 }
2099
2100 /*
2101 * Create TX stats DMA stuffs
2102 */
2103 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2104 BWI_ALIGN);
2105
2106 error = bus_dma_tag_create(sc->sc_parent_dtag,
2107 BWI_ALIGN,
2108 0,
2109 BUS_SPACE_MAXADDR,
2110 BUS_SPACE_MAXADDR,
2111 NULL, NULL,
2112 dma_size,
2113 1,
2114 dma_size,
2115 0,
2116 NULL, NULL,
2117 &st->stats_dtag);
2118 if (error) {
2119 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2120 return error;
2121 }
2122
2123 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2124 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2125 &st->stats_dmap);
2126 if (error) {
2127 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2128 bus_dma_tag_destroy(st->stats_dtag);
2129 st->stats_dtag = NULL;
2130 return error;
2131 }
2132
2133 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2134 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2135 BUS_DMA_NOWAIT);
2136 if (error) {
2137 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2138 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2139 bus_dma_tag_destroy(st->stats_dtag);
2140 st->stats_dtag = NULL;
2141 return error;
2142 }
2143
2144 st->stats_ctrl_base = ctrl_base;
2145 return 0;
2146 }
2147
2148 static void
2149 bwi_dma_txstats_free(struct bwi_softc *sc)
2150 {
2151 struct bwi_txstats_data *st;
2152
2153 if (sc->sc_txstats == NULL)
2154 return;
2155 st = sc->sc_txstats;
2156
2157 if (st->stats_ring_dtag != NULL) {
2158 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2159 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2160 st->stats_ring_dmap);
2161 bus_dma_tag_destroy(st->stats_ring_dtag);
2162 }
2163
2164 if (st->stats_dtag != NULL) {
2165 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2166 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2167 bus_dma_tag_destroy(st->stats_dtag);
2168 }
2169
2170 free(st, M_DEVBUF);
2171 }
2172
2173 static void
2174 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2175 {
2176 KASSERT(nseg == 1, ("too many segments\n"));
2177 *((bus_addr_t *)arg) = seg->ds_addr;
2178 }
2179
2180 static int
2181 bwi_dma_mbuf_create(struct bwi_softc *sc)
2182 {
2183 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2184 int i, j, k, ntx, error;
2185
2186 /*
2187 * Create TX/RX mbuf DMA tag
2188 */
2189 error = bus_dma_tag_create(sc->sc_parent_dtag,
2190 1,
2191 0,
2192 BUS_SPACE_MAXADDR,
2193 BUS_SPACE_MAXADDR,
2194 NULL, NULL,
2195 MCLBYTES,
2196 1,
2197 MCLBYTES,
2198 BUS_DMA_ALLOCNOW,
2199 NULL, NULL,
2200 &sc->sc_buf_dtag);
2201 if (error) {
2202 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2203 return error;
2204 }
2205
2206 ntx = 0;
2207
2208 /*
2209 * Create TX mbuf DMA map
2210 */
2211 for (i = 0; i < BWI_TX_NRING; ++i) {
2212 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2213
2214 for (j = 0; j < BWI_TX_NDESC; ++j) {
2215 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2216 &tbd->tbd_buf[j].tb_dmap);
2217 if (error) {
2218 device_printf(sc->sc_dev, "can't create "
2219 "%dth tbd, %dth DMA map\n", i, j);
2220
2221 ntx = i;
2222 for (k = 0; k < j; ++k) {
2223 bus_dmamap_destroy(sc->sc_buf_dtag,
2224 tbd->tbd_buf[k].tb_dmap);
2225 }
2226 goto fail;
2227 }
2228 }
2229 }
2230 ntx = BWI_TX_NRING;
2231
2232 /*
2233 * Create RX mbuf DMA map and a spare DMA map
2234 */
2235 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2236 &rbd->rbd_tmp_dmap);
2237 if (error) {
2238 device_printf(sc->sc_dev,
2239 "can't create spare RX buf DMA map\n");
2240 goto fail;
2241 }
2242
2243 for (j = 0; j < BWI_RX_NDESC; ++j) {
2244 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2245 &rbd->rbd_buf[j].rb_dmap);
2246 if (error) {
2247 device_printf(sc->sc_dev, "can't create %dth "
2248 "RX buf DMA map\n", j);
2249
2250 for (k = 0; k < j; ++k) {
2251 bus_dmamap_destroy(sc->sc_buf_dtag,
2252 rbd->rbd_buf[j].rb_dmap);
2253 }
2254 bus_dmamap_destroy(sc->sc_buf_dtag,
2255 rbd->rbd_tmp_dmap);
2256 goto fail;
2257 }
2258 }
2259
2260 return 0;
2261 fail:
2262 bwi_dma_mbuf_destroy(sc, ntx, 0);
2263 return error;
2264 }
2265
2266 static void
2267 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2268 {
2269 int i, j;
2270
2271 if (sc->sc_buf_dtag == NULL)
2272 return;
2273
2274 for (i = 0; i < ntx; ++i) {
2275 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2276
2277 for (j = 0; j < BWI_TX_NDESC; ++j) {
2278 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2279
2280 if (tb->tb_mbuf != NULL) {
2281 bus_dmamap_unload(sc->sc_buf_dtag,
2282 tb->tb_dmap);
2283 m_freem(tb->tb_mbuf);
2284 }
2285 if (tb->tb_ni != NULL)
2286 ieee80211_free_node(tb->tb_ni);
2287 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2288 }
2289 }
2290
2291 if (nrx) {
2292 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2293
2294 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2295 for (j = 0; j < BWI_RX_NDESC; ++j) {
2296 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2297
2298 if (rb->rb_mbuf != NULL) {
2299 bus_dmamap_unload(sc->sc_buf_dtag,
2300 rb->rb_dmap);
2301 m_freem(rb->rb_mbuf);
2302 }
2303 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2304 }
2305 }
2306
2307 bus_dma_tag_destroy(sc->sc_buf_dtag);
2308 sc->sc_buf_dtag = NULL;
2309 }
2310
2311 static void
2312 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2313 {
2314 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2315 }
2316
2317 static void
2318 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2319 {
2320 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2321 }
2322
2323 static int
2324 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2325 {
2326 struct bwi_ring_data *rd;
2327 struct bwi_txbuf_data *tbd;
2328 uint32_t val, addr_hi, addr_lo;
2329
2330 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2331 rd = &sc->sc_tx_rdata[ring_idx];
2332 tbd = &sc->sc_tx_bdata[ring_idx];
2333
2334 tbd->tbd_idx = 0;
2335 tbd->tbd_used = 0;
2336
2337 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2338 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2339 BUS_DMASYNC_PREWRITE);
2340
2341 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2342 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2343
2344 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2345 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2346 BWI_TXRX32_RINGINFO_FUNC_MASK);
2347 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2348
2349 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2350 BWI_TXRX32_CTRL_ENABLE;
2351 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2352
2353 return 0;
2354 }
2355
2356 static void
2357 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2358 bus_addr_t paddr, int hdr_size, int ndesc)
2359 {
2360 uint32_t val, addr_hi, addr_lo;
2361
2362 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2363 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2364
2365 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2366 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2367 BWI_TXRX32_RINGINFO_FUNC_MASK);
2368 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2369
2370 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2371 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2372 BWI_TXRX32_CTRL_ENABLE;
2373 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2374
2375 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2376 (ndesc - 1) * sizeof(struct bwi_desc32));
2377 }
2378
2379 static int
2380 bwi_init_rx_ring32(struct bwi_softc *sc)
2381 {
2382 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2383 int i, error;
2384
2385 sc->sc_rx_bdata.rbd_idx = 0;
2386
2387 for (i = 0; i < BWI_RX_NDESC; ++i) {
2388 error = bwi_newbuf(sc, i, 1);
2389 if (error) {
2390 device_printf(sc->sc_dev,
2391 "can't allocate %dth RX buffer\n", i);
2392 return error;
2393 }
2394 }
2395 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2396 BUS_DMASYNC_PREWRITE);
2397
2398 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2399 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2400 return 0;
2401 }
2402
2403 static int
2404 bwi_init_txstats32(struct bwi_softc *sc)
2405 {
2406 struct bwi_txstats_data *st = sc->sc_txstats;
2407 bus_addr_t stats_paddr;
2408 int i;
2409
2410 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2411 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2412
2413 st->stats_idx = 0;
2414
2415 stats_paddr = st->stats_paddr;
2416 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2417 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2418 stats_paddr, sizeof(struct bwi_txstats), 0);
2419 stats_paddr += sizeof(struct bwi_txstats);
2420 }
2421 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2422 BUS_DMASYNC_PREWRITE);
2423
2424 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2425 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2426 return 0;
2427 }
2428
2429 static void
2430 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2431 int buf_len)
2432 {
2433 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2434
2435 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2436 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2437 paddr, buf_len, 0);
2438 }
2439
2440 static void
2441 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2442 int buf_idx, bus_addr_t paddr, int buf_len)
2443 {
2444 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
2445 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2446 paddr, buf_len, 1);
2447 }
2448
2449 static int
2450 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2451 {
2452 /* TODO:64 */
2453 return EOPNOTSUPP;
2454 }
2455
2456 static int
2457 bwi_init_rx_ring64(struct bwi_softc *sc)
2458 {
2459 /* TODO:64 */
2460 return EOPNOTSUPP;
2461 }
2462
2463 static int
2464 bwi_init_txstats64(struct bwi_softc *sc)
2465 {
2466 /* TODO:64 */
2467 return EOPNOTSUPP;
2468 }
2469
2470 static void
2471 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2472 int buf_len)
2473 {
2474 /* TODO:64 */
2475 }
2476
2477 static void
2478 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2479 int buf_idx, bus_addr_t paddr, int buf_len)
2480 {
2481 /* TODO:64 */
2482 }
2483
2484 static void
2485 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2486 bus_size_t mapsz __unused, int error)
2487 {
2488 if (!error) {
2489 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2490 *((bus_addr_t *)arg) = seg->ds_addr;
2491 }
2492 }
2493
2494 static int
2495 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2496 {
2497 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2498 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2499 struct bwi_rxbuf_hdr *hdr;
2500 bus_dmamap_t map;
2501 bus_addr_t paddr;
2502 struct mbuf *m;
2503 int error;
2504
2505 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2506
2507 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2508 if (m == NULL) {
2509 error = ENOBUFS;
2510
2511 /*
2512 * If the NIC is up and running, we need to:
2513 * - Clear RX buffer's header.
2514 * - Restore RX descriptor settings.
2515 */
2516 if (init)
2517 return error;
2518 else
2519 goto back;
2520 }
2521 m->m_len = m->m_pkthdr.len = MCLBYTES;
2522
2523 /*
2524 * Try to load RX buf into temporary DMA map
2525 */
2526 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2527 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
2528 if (error) {
2529 m_freem(m);
2530
2531 /*
2532 * See the comment above
2533 */
2534 if (init)
2535 return error;
2536 else
2537 goto back;
2538 }
2539
2540 if (!init)
2541 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2542 rxbuf->rb_mbuf = m;
2543 rxbuf->rb_paddr = paddr;
2544
2545 /*
2546 * Swap RX buf's DMA map with the loaded temporary one
2547 */
2548 map = rxbuf->rb_dmap;
2549 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2550 rbd->rbd_tmp_dmap = map;
2551
2552 back:
2553 /*
2554 * Clear RX buf header
2555 */
2556 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2557 bzero(hdr, sizeof(*hdr));
2558 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2559
2560 /*
2561 * Setup RX buf descriptor
2562 */
2563 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2564 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2565 return error;
2566 }
2567
2568 static void
2569 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2570 const uint8_t *addr)
2571 {
2572 int i;
2573
2574 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2575 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2576
2577 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2578 uint16_t addr_val;
2579
2580 addr_val = (uint16_t)addr[i * 2] |
2581 (((uint16_t)addr[(i * 2) + 1]) << 8);
2582 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2583 }
2584 }
2585
2586 static int
2587 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2588 {
2589 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2590 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2591 struct ieee80211com *ic = &sc->sc_ic;
2592 int idx, rx_data = 0;
2593
2594 idx = rbd->rbd_idx;
2595 while (idx != end_idx) {
2596 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2597 struct bwi_rxbuf_hdr *hdr;
2598 struct ieee80211_frame_min *wh;
2599 struct ieee80211_node *ni;
2600 struct mbuf *m;
2601 uint32_t plcp;
2602 uint16_t flags2;
2603 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate;
2604
2605 m = rb->rb_mbuf;
2606 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2607 BUS_DMASYNC_POSTREAD);
2608
2609 if (bwi_newbuf(sc, idx, 0)) {
2610 counter_u64_add(ic->ic_ierrors, 1);
2611 goto next;
2612 }
2613
2614 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2615 flags2 = le16toh(hdr->rxh_flags2);
2616
2617 hdr_extra = 0;
2618 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2619 hdr_extra = 2;
2620 wh_ofs = hdr_extra + 6; /* XXX magic number */
2621
2622 buflen = le16toh(hdr->rxh_buflen);
2623 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2624 device_printf(sc->sc_dev,
2625 "%s: zero length data, hdr_extra %d\n",
2626 __func__, hdr_extra);
2627 counter_u64_add(ic->ic_ierrors, 1);
2628 m_freem(m);
2629 goto next;
2630 }
2631
2632 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp));
2633 rssi = bwi_calc_rssi(sc, hdr);
2634 noise = bwi_calc_noise(sc);
2635
2636 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2637 m_adj(m, sizeof(*hdr) + wh_ofs);
2638
2639 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2640 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM);
2641 else
2642 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK);
2643
2644 /* RX radio tap */
2645 if (ieee80211_radiotap_active(ic))
2646 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise);
2647
2648 m_adj(m, -IEEE80211_CRC_LEN);
2649
2650 BWI_UNLOCK(sc);
2651
2652 wh = mtod(m, struct ieee80211_frame_min *);
2653 ni = ieee80211_find_rxnode(ic, wh);
2654 if (ni != NULL) {
2655 type = ieee80211_input(ni, m, rssi - noise, noise);
2656 ieee80211_free_node(ni);
2657 } else
2658 type = ieee80211_input_all(ic, m, rssi - noise, noise);
2659 if (type == IEEE80211_FC0_TYPE_DATA) {
2660 rx_data = 1;
2661 sc->sc_rx_rate = rate;
2662 }
2663
2664 BWI_LOCK(sc);
2665 next:
2666 idx = (idx + 1) % BWI_RX_NDESC;
2667
2668 if (sc->sc_flags & BWI_F_STOP) {
2669 /*
2670 * Take the fast lane, don't do
2671 * any damage to softc
2672 */
2673 return -1;
2674 }
2675 }
2676
2677 rbd->rbd_idx = idx;
2678 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2679 BUS_DMASYNC_PREWRITE);
2680
2681 return rx_data;
2682 }
2683
2684 static int
2685 bwi_rxeof32(struct bwi_softc *sc)
2686 {
2687 uint32_t val, rx_ctrl;
2688 int end_idx, rx_data;
2689
2690 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2691
2692 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2693 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2694 sizeof(struct bwi_desc32);
2695
2696 rx_data = bwi_rxeof(sc, end_idx);
2697 if (rx_data >= 0) {
2698 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2699 end_idx * sizeof(struct bwi_desc32));
2700 }
2701 return rx_data;
2702 }
2703
2704 static int
2705 bwi_rxeof64(struct bwi_softc *sc)
2706 {
2707 /* TODO:64 */
2708 return 0;
2709 }
2710
2711 static void
2712 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2713 {
2714 int i;
2715
2716 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2717
2718 #define NRETRY 10
2719
2720 for (i = 0; i < NRETRY; ++i) {
2721 uint32_t status;
2722
2723 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2724 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2725 BWI_RX32_STATUS_STATE_DISABLED)
2726 break;
2727
2728 DELAY(1000);
2729 }
2730 if (i == NRETRY)
2731 device_printf(sc->sc_dev, "reset rx ring timedout\n");
2732
2733 #undef NRETRY
2734
2735 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2736 }
2737
2738 static void
2739 bwi_free_txstats32(struct bwi_softc *sc)
2740 {
2741 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2742 }
2743
2744 static void
2745 bwi_free_rx_ring32(struct bwi_softc *sc)
2746 {
2747 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2748 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2749 int i;
2750
2751 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2752
2753 for (i = 0; i < BWI_RX_NDESC; ++i) {
2754 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2755
2756 if (rb->rb_mbuf != NULL) {
2757 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2758 m_freem(rb->rb_mbuf);
2759 rb->rb_mbuf = NULL;
2760 }
2761 }
2762 }
2763
2764 static void
2765 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2766 {
2767 struct bwi_ring_data *rd;
2768 struct bwi_txbuf_data *tbd;
2769 uint32_t state, val;
2770 int i;
2771
2772 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2773 rd = &sc->sc_tx_rdata[ring_idx];
2774 tbd = &sc->sc_tx_bdata[ring_idx];
2775
2776 #define NRETRY 10
2777
2778 for (i = 0; i < NRETRY; ++i) {
2779 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2780 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2781 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2782 state == BWI_TX32_STATUS_STATE_IDLE ||
2783 state == BWI_TX32_STATUS_STATE_STOPPED)
2784 break;
2785
2786 DELAY(1000);
2787 }
2788 if (i == NRETRY) {
2789 device_printf(sc->sc_dev,
2790 "%s: wait for TX ring(%d) stable timed out\n",
2791 __func__, ring_idx);
2792 }
2793
2794 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2795 for (i = 0; i < NRETRY; ++i) {
2796 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2797 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2798 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2799 break;
2800
2801 DELAY(1000);
2802 }
2803 if (i == NRETRY)
2804 device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n",
2805 __func__, ring_idx);
2806
2807 #undef NRETRY
2808
2809 DELAY(1000);
2810
2811 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2812
2813 for (i = 0; i < BWI_TX_NDESC; ++i) {
2814 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2815
2816 if (tb->tb_mbuf != NULL) {
2817 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2818 m_freem(tb->tb_mbuf);
2819 tb->tb_mbuf = NULL;
2820 }
2821 if (tb->tb_ni != NULL) {
2822 ieee80211_free_node(tb->tb_ni);
2823 tb->tb_ni = NULL;
2824 }
2825 }
2826 }
2827
2828 static void
2829 bwi_free_txstats64(struct bwi_softc *sc)
2830 {
2831 /* TODO:64 */
2832 }
2833
2834 static void
2835 bwi_free_rx_ring64(struct bwi_softc *sc)
2836 {
2837 /* TODO:64 */
2838 }
2839
2840 static void
2841 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2842 {
2843 /* TODO:64 */
2844 }
2845
2846 /* XXX does not belong here */
2847 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
2848 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
2849
2850 static __inline void
2851 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
2852 {
2853 uint32_t plcp;
2854
2855 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM),
2856 IEEE80211_OFDM_PLCP_RATE_MASK) |
2857 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
2858 *plcp0 = htole32(plcp);
2859 }
2860
2861 static __inline void
2862 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
2863 uint8_t rate)
2864 {
2865 int len, service, pkt_bitlen;
2866
2867 pkt_bitlen = pkt_len * NBBY;
2868 len = howmany(pkt_bitlen * 2, rate);
2869
2870 service = IEEE80211_PLCP_SERVICE_LOCKED;
2871 if (rate == (11 * 2)) {
2872 int pkt_bitlen1;
2873
2874 /*
2875 * PLCP service field needs to be adjusted,
2876 * if TX rate is 11Mbytes/s
2877 */
2878 pkt_bitlen1 = len * 11;
2879 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
2880 service |= IEEE80211_PLCP_SERVICE_LENEXT7;
2881 }
2882
2883 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK);
2884 plcp->i_service = service;
2885 plcp->i_length = htole16(len);
2886 /* NOTE: do NOT touch i_crc */
2887 }
2888
2889 static __inline void
2890 bwi_plcp_header(const struct ieee80211_rate_table *rt,
2891 void *plcp, int pkt_len, uint8_t rate)
2892 {
2893 enum ieee80211_phytype modtype;
2894
2895 /*
2896 * Assume caller has zeroed 'plcp'
2897 */
2898 modtype = ieee80211_rate2phytype(rt, rate);
2899 if (modtype == IEEE80211_T_OFDM)
2900 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
2901 else if (modtype == IEEE80211_T_DS)
2902 bwi_ds_plcp_header(plcp, pkt_len, rate);
2903 else
2904 panic("unsupport modulation type %u\n", modtype);
2905 }
2906
2907 static int
2908 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2909 struct ieee80211_node *ni)
2910 {
2911 struct ieee80211vap *vap = ni->ni_vap;
2912 struct ieee80211com *ic = &sc->sc_ic;
2913 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2914 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2915 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2916 struct bwi_mac *mac;
2917 struct bwi_txbuf_hdr *hdr;
2918 struct ieee80211_frame *wh;
2919 const struct ieee80211_txparam *tp = ni->ni_txparms;
2920 uint8_t rate, rate_fb;
2921 uint32_t mac_ctrl;
2922 uint16_t phy_ctrl;
2923 bus_addr_t paddr;
2924 int type, ismcast, pkt_len, error, rix;
2925 #if 0
2926 const uint8_t *p;
2927 int i;
2928 #endif
2929
2930 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
2931 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
2932 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2933
2934 wh = mtod(m, struct ieee80211_frame *);
2935 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2936 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
2937
2938 /* Get 802.11 frame len before prepending TX header */
2939 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2940
2941 /*
2942 * Find TX rate
2943 */
2944 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) {
2945 rate = rate_fb = tp->mgmtrate;
2946 } else if (ismcast) {
2947 rate = rate_fb = tp->mcastrate;
2948 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
2949 rate = rate_fb = tp->ucastrate;
2950 } else {
2951 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len);
2952 rate = ni->ni_txrate;
2953
2954 if (rix > 0) {
2955 rate_fb = ni->ni_rates.rs_rates[rix-1] &
2956 IEEE80211_RATE_VAL;
2957 } else {
2958 rate_fb = rate;
2959 }
2960 }
2961 tb->tb_rate[0] = rate;
2962 tb->tb_rate[1] = rate_fb;
2963 sc->sc_tx_rate = rate;
2964
2965 /*
2966 * TX radio tap
2967 */
2968 if (ieee80211_radiotap_active_vap(vap)) {
2969 sc->sc_tx_th.wt_flags = 0;
2970 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
2971 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2972 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS &&
2973 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
2974 rate != (1 * 2)) {
2975 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2976 }
2977 sc->sc_tx_th.wt_rate = rate;
2978
2979 ieee80211_radiotap_tx(vap, m);
2980 }
2981
2982 /*
2983 * Setup the embedded TX header
2984 */
2985 M_PREPEND(m, sizeof(*hdr), M_NOWAIT);
2986 if (m == NULL) {
2987 device_printf(sc->sc_dev, "%s: prepend TX header failed\n",
2988 __func__);
2989 return ENOBUFS;
2990 }
2991 hdr = mtod(m, struct bwi_txbuf_hdr *);
2992
2993 bzero(hdr, sizeof(*hdr));
2994
2995 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
2996 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
2997
2998 if (!ismcast) {
2999 uint16_t dur;
3000
3001 dur = ieee80211_ack_duration(sc->sc_rates, rate,
3002 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
3003
3004 hdr->txh_fb_duration = htole16(dur);
3005 }
3006
3007 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3008 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3009
3010 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3011 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3012
3013 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3014 BWI_TXH_PHY_C_ANTMODE_MASK);
3015 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM)
3016 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3017 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3018 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3019
3020 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3021 if (!ismcast)
3022 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3023 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM)
3024 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3025
3026 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3027 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3028
3029 /* Catch any further usage */
3030 hdr = NULL;
3031 wh = NULL;
3032
3033 /* DMA load */
3034 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3035 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3036 if (error && error != EFBIG) {
3037 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n",
3038 __func__, error);
3039 goto back;
3040 }
3041
3042 if (error) { /* error == EFBIG */
3043 struct mbuf *m_new;
3044
3045 m_new = m_defrag(m, M_NOWAIT);
3046 if (m_new == NULL) {
3047 device_printf(sc->sc_dev,
3048 "%s: can't defrag TX buffer\n", __func__);
3049 error = ENOBUFS;
3050 goto back;
3051 } else {
3052 m = m_new;
3053 }
3054
3055 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3056 bwi_dma_buf_addr, &paddr,
3057 BUS_DMA_NOWAIT);
3058 if (error) {
3059 device_printf(sc->sc_dev,
3060 "%s: can't load TX buffer (2) %d\n",
3061 __func__, error);
3062 goto back;
3063 }
3064 }
3065 error = 0;
3066
3067 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3068
3069 tb->tb_mbuf = m;
3070 tb->tb_ni = ni;
3071
3072 #if 0
3073 p = mtod(m, const uint8_t *);
3074 for (i = 0; i < m->m_pkthdr.len; ++i) {
3075 if (i != 0 && i % 8 == 0)
3076 printf("\n");
3077 printf("%02x ", p[i]);
3078 }
3079 printf("\n");
3080 #endif
3081 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3082 idx, pkt_len, m->m_pkthdr.len);
3083
3084 /* Setup TX descriptor */
3085 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3086 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3087 BUS_DMASYNC_PREWRITE);
3088
3089 /* Kick start */
3090 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3091
3092 back:
3093 if (error)
3094 m_freem(m);
3095 return error;
3096 }
3097
3098 static int
3099 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m,
3100 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
3101 {
3102 struct ieee80211vap *vap = ni->ni_vap;
3103 struct ieee80211com *ic = ni->ni_ic;
3104 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
3105 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
3106 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3107 struct bwi_mac *mac;
3108 struct bwi_txbuf_hdr *hdr;
3109 struct ieee80211_frame *wh;
3110 uint8_t rate, rate_fb;
3111 uint32_t mac_ctrl;
3112 uint16_t phy_ctrl;
3113 bus_addr_t paddr;
3114 int ismcast, pkt_len, error;
3115
3116 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3117 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3118 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3119
3120 wh = mtod(m, struct ieee80211_frame *);
3121 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3122
3123 /* Get 802.11 frame len before prepending TX header */
3124 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3125
3126 /*
3127 * Find TX rate
3128 */
3129 rate = params->ibp_rate0;
3130 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
3131 /* XXX fall back to mcast/mgmt rate? */
3132 m_freem(m);
3133 return EINVAL;
3134 }
3135 if (params->ibp_try1 != 0) {
3136 rate_fb = params->ibp_rate1;
3137 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) {
3138 /* XXX fall back to rate0? */
3139 m_freem(m);
3140 return EINVAL;
3141 }
3142 } else
3143 rate_fb = rate;
3144 tb->tb_rate[0] = rate;
3145 tb->tb_rate[1] = rate_fb;
3146 sc->sc_tx_rate = rate;
3147
3148 /*
3149 * TX radio tap
3150 */
3151 if (ieee80211_radiotap_active_vap(vap)) {
3152 sc->sc_tx_th.wt_flags = 0;
3153 /* XXX IEEE80211_BPF_CRYPTO */
3154 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
3155 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3156 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3157 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3158 sc->sc_tx_th.wt_rate = rate;
3159
3160 ieee80211_radiotap_tx(vap, m);
3161 }
3162
3163 /*
3164 * Setup the embedded TX header
3165 */
3166 M_PREPEND(m, sizeof(*hdr), M_NOWAIT);
3167 if (m == NULL) {
3168 device_printf(sc->sc_dev, "%s: prepend TX header failed\n",
3169 __func__);
3170 return ENOBUFS;
3171 }
3172 hdr = mtod(m, struct bwi_txbuf_hdr *);
3173
3174 bzero(hdr, sizeof(*hdr));
3175
3176 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3177 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3178
3179 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3180 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
3181 uint16_t dur;
3182
3183 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0);
3184
3185 hdr->txh_fb_duration = htole16(dur);
3186 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3187 }
3188
3189 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3190 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3191
3192 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3193 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3194
3195 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3196 BWI_TXH_PHY_C_ANTMODE_MASK);
3197 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) {
3198 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3199 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3200 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3201 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3202
3203 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3204 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3205
3206 /* Catch any further usage */
3207 hdr = NULL;
3208 wh = NULL;
3209
3210 /* DMA load */
3211 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3212 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3213 if (error != 0) {
3214 struct mbuf *m_new;
3215
3216 if (error != EFBIG) {
3217 device_printf(sc->sc_dev,
3218 "%s: can't load TX buffer (1) %d\n",
3219 __func__, error);
3220 goto back;
3221 }
3222 m_new = m_defrag(m, M_NOWAIT);
3223 if (m_new == NULL) {
3224 device_printf(sc->sc_dev,
3225 "%s: can't defrag TX buffer\n", __func__);
3226 error = ENOBUFS;
3227 goto back;
3228 }
3229 m = m_new;
3230 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3231 bwi_dma_buf_addr, &paddr,
3232 BUS_DMA_NOWAIT);
3233 if (error) {
3234 device_printf(sc->sc_dev,
3235 "%s: can't load TX buffer (2) %d\n",
3236 __func__, error);
3237 goto back;
3238 }
3239 }
3240
3241 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3242
3243 tb->tb_mbuf = m;
3244 tb->tb_ni = ni;
3245
3246 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3247 idx, pkt_len, m->m_pkthdr.len);
3248
3249 /* Setup TX descriptor */
3250 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3251 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3252 BUS_DMASYNC_PREWRITE);
3253
3254 /* Kick start */
3255 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3256 back:
3257 if (error)
3258 m_freem(m);
3259 return error;
3260 }
3261
3262 static void
3263 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3264 {
3265 idx = (idx + 1) % BWI_TX_NDESC;
3266 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3267 idx * sizeof(struct bwi_desc32));
3268 }
3269
3270 static void
3271 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3272 {
3273 /* TODO:64 */
3274 }
3275
3276 static void
3277 bwi_txeof_status32(struct bwi_softc *sc)
3278 {
3279 uint32_t val, ctrl_base;
3280 int end_idx;
3281
3282 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3283
3284 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3285 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3286 sizeof(struct bwi_desc32);
3287
3288 bwi_txeof_status(sc, end_idx);
3289
3290 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3291 end_idx * sizeof(struct bwi_desc32));
3292
3293 bwi_start_locked(sc);
3294 }
3295
3296 static void
3297 bwi_txeof_status64(struct bwi_softc *sc)
3298 {
3299 /* TODO:64 */
3300 }
3301
3302 static void
3303 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3304 {
3305 struct bwi_txbuf_data *tbd;
3306 struct bwi_txbuf *tb;
3307 int ring_idx, buf_idx;
3308 struct ieee80211_node *ni;
3309
3310 if (tx_id == 0) {
3311 device_printf(sc->sc_dev, "%s: zero tx id\n", __func__);
3312 return;
3313 }
3314
3315 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3316 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3317
3318 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx));
3319 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
3320
3321 tbd = &sc->sc_tx_bdata[ring_idx];
3322 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used));
3323 tbd->tbd_used--;
3324
3325 tb = &tbd->tbd_buf[buf_idx];
3326 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3327 "acked %d, data_txcnt %d, ni %p\n",
3328 buf_idx, acked, data_txcnt, tb->tb_ni);
3329
3330 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3331
3332 if ((ni = tb->tb_ni) != NULL) {
3333 const struct bwi_txbuf_hdr *hdr =
3334 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *);
3335 struct ieee80211_ratectl_tx_status txs;
3336
3337 /* NB: update rate control only for unicast frames */
3338 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) {
3339 /*
3340 * Feed back 'acked and data_txcnt'. Note that the
3341 * generic AMRR code only understands one tx rate
3342 * and the estimator doesn't handle real retry counts
3343 * well so to avoid over-aggressive downshifting we
3344 * treat any number of retries as "1".
3345 */
3346 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY;
3347 txs.long_retries = acked;
3348 if (data_txcnt > 1)
3349 txs.status = IEEE80211_RATECTL_TX_SUCCESS;
3350 else {
3351 txs.status =
3352 IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED;
3353 }
3354 ieee80211_ratectl_tx_complete(ni, &txs);
3355 }
3356 ieee80211_tx_complete(ni, tb->tb_mbuf, !acked);
3357 tb->tb_ni = NULL;
3358 } else
3359 m_freem(tb->tb_mbuf);
3360 tb->tb_mbuf = NULL;
3361
3362 if (tbd->tbd_used == 0)
3363 sc->sc_tx_timer = 0;
3364 }
3365
3366 static void
3367 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3368 {
3369 struct bwi_txstats_data *st = sc->sc_txstats;
3370 int idx;
3371
3372 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3373
3374 idx = st->stats_idx;
3375 while (idx != end_idx) {
3376 const struct bwi_txstats *stats = &st->stats[idx];
3377
3378 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3379 int data_txcnt;
3380
3381 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3382 BWI_TXS_TXCNT_DATA);
3383 _bwi_txeof(sc, le16toh(stats->txs_id),
3384 stats->txs_flags & BWI_TXS_F_ACKED,
3385 data_txcnt);
3386 }
3387 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3388 }
3389 st->stats_idx = idx;
3390 }
3391
3392 static void
3393 bwi_txeof(struct bwi_softc *sc)
3394 {
3395
3396 for (;;) {
3397 uint32_t tx_status0, tx_status1 __unused;
3398 uint16_t tx_id;
3399 int data_txcnt;
3400
3401 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3402 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3403 break;
3404 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3405
3406 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3407 data_txcnt = __SHIFTOUT(tx_status0,
3408 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3409
3410 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3411 continue;
3412
3413 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED,
3414 data_txcnt);
3415 }
3416
3417 bwi_start_locked(sc);
3418 }
3419
3420 static int
3421 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3422 {
3423 bwi_power_on(sc, 1);
3424 return bwi_set_clock_mode(sc, clk_mode);
3425 }
3426
3427 static void
3428 bwi_bbp_power_off(struct bwi_softc *sc)
3429 {
3430 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3431 bwi_power_off(sc, 1);
3432 }
3433
3434 static int
3435 bwi_get_pwron_delay(struct bwi_softc *sc)
3436 {
3437 struct bwi_regwin *com, *old;
3438 struct bwi_clock_freq freq;
3439 uint32_t val;
3440 int error;
3441
3442 com = &sc->sc_com_regwin;
3443 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin"));
3444
3445 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3446 return 0;
3447
3448 error = bwi_regwin_switch(sc, com, &old);
3449 if (error)
3450 return error;
3451
3452 bwi_get_clock_freq(sc, &freq);
3453
3454 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3455 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3456 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3457
3458 return bwi_regwin_switch(sc, old, NULL);
3459 }
3460
3461 static int
3462 bwi_bus_attach(struct bwi_softc *sc)
3463 {
3464 struct bwi_regwin *bus, *old;
3465 int error;
3466
3467 bus = &sc->sc_bus_regwin;
3468
3469 error = bwi_regwin_switch(sc, bus, &old);
3470 if (error)
3471 return error;
3472
3473 if (!bwi_regwin_is_enabled(sc, bus))
3474 bwi_regwin_enable(sc, bus, 0);
3475
3476 /* Disable interripts */
3477 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3478
3479 return bwi_regwin_switch(sc, old, NULL);
3480 }
3481
3482 static const char *
3483 bwi_regwin_name(const struct bwi_regwin *rw)
3484 {
3485 switch (rw->rw_type) {
3486 case BWI_REGWIN_T_COM:
3487 return "COM";
3488 case BWI_REGWIN_T_BUSPCI:
3489 return "PCI";
3490 case BWI_REGWIN_T_MAC:
3491 return "MAC";
3492 case BWI_REGWIN_T_BUSPCIE:
3493 return "PCIE";
3494 }
3495 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3496 return NULL;
3497 }
3498
3499 static uint32_t
3500 bwi_regwin_disable_bits(struct bwi_softc *sc)
3501 {
3502 uint32_t busrev;
3503
3504 /* XXX cache this */
3505 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3506 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3507 "bus rev %u\n", busrev);
3508
3509 if (busrev == BWI_BUSREV_0)
3510 return BWI_STATE_LO_DISABLE1;
3511 else if (busrev == BWI_BUSREV_1)
3512 return BWI_STATE_LO_DISABLE2;
3513 else
3514 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3515 }
3516
3517 int
3518 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3519 {
3520 uint32_t val, disable_bits;
3521
3522 disable_bits = bwi_regwin_disable_bits(sc);
3523 val = CSR_READ_4(sc, BWI_STATE_LO);
3524
3525 if ((val & (BWI_STATE_LO_CLOCK |
3526 BWI_STATE_LO_RESET |
3527 disable_bits)) == BWI_STATE_LO_CLOCK) {
3528 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3529 bwi_regwin_name(rw));
3530 return 1;
3531 } else {
3532 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3533 bwi_regwin_name(rw));
3534 return 0;
3535 }
3536 }
3537
3538 void
3539 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3540 {
3541 uint32_t state_lo, disable_bits;
3542 int i;
3543
3544 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3545
3546 /*
3547 * If current regwin is in 'reset' state, it was already disabled.
3548 */
3549 if (state_lo & BWI_STATE_LO_RESET) {
3550 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3551 "%s was already disabled\n", bwi_regwin_name(rw));
3552 return;
3553 }
3554
3555 disable_bits = bwi_regwin_disable_bits(sc);
3556
3557 /*
3558 * Disable normal clock
3559 */
3560 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3561 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3562
3563 /*
3564 * Wait until normal clock is disabled
3565 */
3566 #define NRETRY 1000
3567 for (i = 0; i < NRETRY; ++i) {
3568 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3569 if (state_lo & disable_bits)
3570 break;
3571 DELAY(10);
3572 }
3573 if (i == NRETRY) {
3574 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3575 bwi_regwin_name(rw));
3576 }
3577
3578 for (i = 0; i < NRETRY; ++i) {
3579 uint32_t state_hi;
3580
3581 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3582 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3583 break;
3584 DELAY(10);
3585 }
3586 if (i == NRETRY) {
3587 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3588 bwi_regwin_name(rw));
3589 }
3590 #undef NRETRY
3591
3592 /*
3593 * Reset and disable regwin with gated clock
3594 */
3595 state_lo = BWI_STATE_LO_RESET | disable_bits |
3596 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3597 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3598 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3599
3600 /* Flush pending bus write */
3601 CSR_READ_4(sc, BWI_STATE_LO);
3602 DELAY(1);
3603
3604 /* Reset and disable regwin */
3605 state_lo = BWI_STATE_LO_RESET | disable_bits |
3606 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3607 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3608
3609 /* Flush pending bus write */
3610 CSR_READ_4(sc, BWI_STATE_LO);
3611 DELAY(1);
3612 }
3613
3614 void
3615 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3616 {
3617 uint32_t state_lo, state_hi, imstate;
3618
3619 bwi_regwin_disable(sc, rw, flags);
3620
3621 /* Reset regwin with gated clock */
3622 state_lo = BWI_STATE_LO_RESET |
3623 BWI_STATE_LO_CLOCK |
3624 BWI_STATE_LO_GATED_CLOCK |
3625 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3626 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3627
3628 /* Flush pending bus write */
3629 CSR_READ_4(sc, BWI_STATE_LO);
3630 DELAY(1);
3631
3632 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3633 if (state_hi & BWI_STATE_HI_SERROR)
3634 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3635
3636 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3637 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3638 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3639 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3640 }
3641
3642 /* Enable regwin with gated clock */
3643 state_lo = BWI_STATE_LO_CLOCK |
3644 BWI_STATE_LO_GATED_CLOCK |
3645 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3646 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3647
3648 /* Flush pending bus write */
3649 CSR_READ_4(sc, BWI_STATE_LO);
3650 DELAY(1);
3651
3652 /* Enable regwin with normal clock */
3653 state_lo = BWI_STATE_LO_CLOCK |
3654 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3655 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3656
3657 /* Flush pending bus write */
3658 CSR_READ_4(sc, BWI_STATE_LO);
3659 DELAY(1);
3660 }
3661
3662 static void
3663 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3664 {
3665 struct bwi_mac *mac;
3666 struct bwi_myaddr_bssid buf;
3667 const uint8_t *p;
3668 uint32_t val;
3669 int n, i;
3670
3671 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3672 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3673 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3674
3675 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3676
3677 bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr));
3678 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3679
3680 n = sizeof(buf) / sizeof(val);
3681 p = (const uint8_t *)&buf;
3682 for (i = 0; i < n; ++i) {
3683 int j;
3684
3685 val = 0;
3686 for (j = 0; j < sizeof(val); ++j)
3687 val |= ((uint32_t)(*p++)) << (j * 8);
3688
3689 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3690 }
3691 }
3692
3693 static void
3694 bwi_updateslot(struct ieee80211com *ic)
3695 {
3696 struct bwi_softc *sc = ic->ic_softc;
3697 struct bwi_mac *mac;
3698
3699 BWI_LOCK(sc);
3700 if (sc->sc_flags & BWI_F_RUNNING) {
3701 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3702
3703 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3704 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3705 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3706
3707 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3708 }
3709 BWI_UNLOCK(sc);
3710 }
3711
3712 static void
3713 bwi_calibrate(void *xsc)
3714 {
3715 struct bwi_softc *sc = xsc;
3716 struct bwi_mac *mac;
3717
3718 BWI_ASSERT_LOCKED(sc);
3719
3720 KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR,
3721 ("opmode %d", sc->sc_ic.ic_opmode));
3722
3723 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3724 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3725 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3726
3727 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3728 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3729
3730 /* XXX 15 seconds */
3731 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3732 }
3733
3734 static int
3735 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3736 {
3737 struct bwi_mac *mac;
3738
3739 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3740 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3741 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3742
3743 return bwi_rf_calc_rssi(mac, hdr);
3744 }
3745
3746 static int
3747 bwi_calc_noise(struct bwi_softc *sc)
3748 {
3749 struct bwi_mac *mac;
3750
3751 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3752 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3753 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3754
3755 return bwi_rf_calc_noise(mac);
3756 }
3757
3758 static __inline uint8_t
3759 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type)
3760 {
3761 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK;
3762 return (ieee80211_plcp2rate(plcp, type));
3763 }
3764
3765 static void
3766 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3767 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise)
3768 {
3769 const struct ieee80211_frame_min *wh;
3770
3771 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3772 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3773 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3774
3775 wh = mtod(m, const struct ieee80211_frame_min *);
3776 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
3777 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3778
3779 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian conversion */
3780 sc->sc_rx_th.wr_rate = rate;
3781 sc->sc_rx_th.wr_antsignal = rssi;
3782 sc->sc_rx_th.wr_antnoise = noise;
3783 }
3784
3785 static void
3786 bwi_led_attach(struct bwi_softc *sc)
3787 {
3788 const uint8_t *led_act = NULL;
3789 uint16_t gpio, val[BWI_LED_MAX];
3790 int i;
3791
3792 for (i = 0; i < nitems(bwi_vendor_led_act); ++i) {
3793 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3794 led_act = bwi_vendor_led_act[i].led_act;
3795 break;
3796 }
3797 }
3798 if (led_act == NULL)
3799 led_act = bwi_default_led_act;
3800
3801 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3802 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3803 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3804
3805 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3806 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3807 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3808
3809 for (i = 0; i < BWI_LED_MAX; ++i) {
3810 struct bwi_led *led = &sc->sc_leds[i];
3811
3812 if (val[i] == 0xff) {
3813 led->l_act = led_act[i];
3814 } else {
3815 if (val[i] & BWI_LED_ACT_LOW)
3816 led->l_flags |= BWI_LED_F_ACTLOW;
3817 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3818 }
3819 led->l_mask = (1 << i);
3820
3821 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3822 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3823 led->l_act == BWI_LED_ACT_BLINK) {
3824 led->l_flags |= BWI_LED_F_BLINK;
3825 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3826 led->l_flags |= BWI_LED_F_POLLABLE;
3827 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3828 led->l_flags |= BWI_LED_F_SLOW;
3829
3830 if (sc->sc_blink_led == NULL) {
3831 sc->sc_blink_led = led;
3832 if (led->l_flags & BWI_LED_F_SLOW)
3833 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3834 }
3835 }
3836
3837 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3838 "%dth led, act %d, lowact %d\n", i,
3839 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3840 }
3841 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0);
3842 }
3843
3844 static __inline uint16_t
3845 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3846 {
3847 if (led->l_flags & BWI_LED_F_ACTLOW)
3848 on = !on;
3849 if (on)
3850 val |= led->l_mask;
3851 else
3852 val &= ~led->l_mask;
3853 return val;
3854 }
3855
3856 static void
3857 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3858 {
3859 struct ieee80211com *ic = &sc->sc_ic;
3860 uint16_t val;
3861 int i;
3862
3863 if (nstate == IEEE80211_S_INIT) {
3864 callout_stop(&sc->sc_led_blink_ch);
3865 sc->sc_led_blinking = 0;
3866 }
3867
3868 if ((sc->sc_flags & BWI_F_RUNNING) == 0)
3869 return;
3870
3871 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3872 for (i = 0; i < BWI_LED_MAX; ++i) {
3873 struct bwi_led *led = &sc->sc_leds[i];
3874 int on;
3875
3876 if (led->l_act == BWI_LED_ACT_UNKN ||
3877 led->l_act == BWI_LED_ACT_NULL)
3878 continue;
3879
3880 if ((led->l_flags & BWI_LED_F_BLINK) &&
3881 nstate != IEEE80211_S_INIT)
3882 continue;
3883
3884 switch (led->l_act) {
3885 case BWI_LED_ACT_ON: /* Always on */
3886 on = 1;
3887 break;
3888 case BWI_LED_ACT_OFF: /* Always off */
3889 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3890 on = 0;
3891 break;
3892 default:
3893 on = 1;
3894 switch (nstate) {
3895 case IEEE80211_S_INIT:
3896 on = 0;
3897 break;
3898 case IEEE80211_S_RUN:
3899 if (led->l_act == BWI_LED_ACT_11G &&
3900 ic->ic_curmode != IEEE80211_MODE_11G)
3901 on = 0;
3902 break;
3903 default:
3904 if (led->l_act == BWI_LED_ACT_ASSOC)
3905 on = 0;
3906 break;
3907 }
3908 break;
3909 }
3910
3911 val = bwi_led_onoff(led, val, on);
3912 }
3913 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3914 }
3915 static void
3916 bwi_led_event(struct bwi_softc *sc, int event)
3917 {
3918 struct bwi_led *led = sc->sc_blink_led;
3919 int rate;
3920
3921 if (event == BWI_LED_EVENT_POLL) {
3922 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3923 return;
3924 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3925 return;
3926 }
3927
3928 sc->sc_led_ticks = ticks;
3929 if (sc->sc_led_blinking)
3930 return;
3931
3932 switch (event) {
3933 case BWI_LED_EVENT_RX:
3934 rate = sc->sc_rx_rate;
3935 break;
3936 case BWI_LED_EVENT_TX:
3937 rate = sc->sc_tx_rate;
3938 break;
3939 case BWI_LED_EVENT_POLL:
3940 rate = 0;
3941 break;
3942 default:
3943 panic("unknown LED event %d\n", event);
3944 break;
3945 }
3946 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3947 bwi_led_duration[rate].off_dur);
3948 }
3949
3950 static void
3951 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
3952 {
3953 struct bwi_led *led = sc->sc_blink_led;
3954 uint16_t val;
3955
3956 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3957 val = bwi_led_onoff(led, val, 1);
3958 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3959
3960 if (led->l_flags & BWI_LED_F_SLOW) {
3961 BWI_LED_SLOWDOWN(on_dur);
3962 BWI_LED_SLOWDOWN(off_dur);
3963 }
3964
3965 sc->sc_led_blinking = 1;
3966 sc->sc_led_blink_offdur = off_dur;
3967
3968 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
3969 }
3970
3971 static void
3972 bwi_led_blink_next(void *xsc)
3973 {
3974 struct bwi_softc *sc = xsc;
3975 uint16_t val;
3976
3977 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3978 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
3979 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3980
3981 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
3982 bwi_led_blink_end, sc);
3983 }
3984
3985 static void
3986 bwi_led_blink_end(void *xsc)
3987 {
3988 struct bwi_softc *sc = xsc;
3989 sc->sc_led_blinking = 0;
3990 }
3991
3992 static void
3993 bwi_restart(void *xsc, int pending)
3994 {
3995 struct bwi_softc *sc = xsc;
3996
3997 device_printf(sc->sc_dev, "%s begin, help!\n", __func__);
3998 BWI_LOCK(sc);
3999 bwi_init_statechg(sc, 0);
4000 #if 0
4001 bwi_start_locked(sc);
4002 #endif
4003 BWI_UNLOCK(sc);
4004 }
Cache object: b32d835eb089b51c369dcf4fe61fec3d
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