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sys/dev/bwi/if_bwi.c
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1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include "opt_inet.h" 43 #include "opt_bwi.h" 44 #include "opt_wlan.h" 45 46 #include <sys/param.h> 47 #include <sys/endian.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/malloc.h> 51 #include <sys/proc.h> 52 #include <sys/rman.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 #include <sys/sysctl.h> 56 #include <sys/systm.h> 57 #include <sys/taskqueue.h> 58 59 #include <net/if.h> 60 #include <net/if_var.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 #include <net/if_types.h> 64 #include <net/if_arp.h> 65 #include <net/ethernet.h> 66 #include <net/if_llc.h> 67 68 #include <net80211/ieee80211_var.h> 69 #include <net80211/ieee80211_radiotap.h> 70 #include <net80211/ieee80211_regdomain.h> 71 #include <net80211/ieee80211_phy.h> 72 #include <net80211/ieee80211_ratectl.h> 73 74 #include <net/bpf.h> 75 76 #ifdef INET 77 #include <netinet/in.h> 78 #include <netinet/if_ether.h> 79 #endif 80 81 #include <machine/bus.h> 82 83 #include <dev/pci/pcivar.h> 84 #include <dev/pci/pcireg.h> 85 86 #include <dev/bwi/bitops.h> 87 #include <dev/bwi/if_bwireg.h> 88 #include <dev/bwi/if_bwivar.h> 89 #include <dev/bwi/bwimac.h> 90 #include <dev/bwi/bwirf.h> 91 92 struct bwi_clock_freq { 93 u_int clkfreq_min; 94 u_int clkfreq_max; 95 }; 96 97 struct bwi_myaddr_bssid { 98 uint8_t myaddr[IEEE80211_ADDR_LEN]; 99 uint8_t bssid[IEEE80211_ADDR_LEN]; 100 } __packed; 101 102 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 103 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 104 const uint8_t [IEEE80211_ADDR_LEN], 105 const uint8_t [IEEE80211_ADDR_LEN]); 106 static void bwi_vap_delete(struct ieee80211vap *); 107 static void bwi_init(struct bwi_softc *); 108 static void bwi_parent(struct ieee80211com *); 109 static int bwi_transmit(struct ieee80211com *, struct mbuf *); 110 static void bwi_start_locked(struct bwi_softc *); 111 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 112 const struct ieee80211_bpf_params *); 113 static void bwi_watchdog(void *); 114 static void bwi_scan_start(struct ieee80211com *); 115 static void bwi_getradiocaps(struct ieee80211com *, int, int *, 116 struct ieee80211_channel[]); 117 static void bwi_set_channel(struct ieee80211com *); 118 static void bwi_scan_end(struct ieee80211com *); 119 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 120 static void bwi_updateslot(struct ieee80211com *); 121 122 static void bwi_calibrate(void *); 123 124 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 125 static int bwi_calc_noise(struct bwi_softc *); 126 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype); 127 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 128 struct bwi_rxbuf_hdr *, const void *, int, int, int); 129 130 static void bwi_restart(void *, int); 131 static void bwi_init_statechg(struct bwi_softc *, int); 132 static void bwi_stop(struct bwi_softc *, int); 133 static void bwi_stop_locked(struct bwi_softc *, int); 134 static int bwi_newbuf(struct bwi_softc *, int, int); 135 static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 136 struct ieee80211_node *); 137 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 138 struct ieee80211_node *, 139 const struct ieee80211_bpf_params *); 140 141 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 142 bus_addr_t, int, int); 143 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 144 145 static int bwi_init_tx_ring32(struct bwi_softc *, int); 146 static int bwi_init_rx_ring32(struct bwi_softc *); 147 static int bwi_init_txstats32(struct bwi_softc *); 148 static void bwi_free_tx_ring32(struct bwi_softc *, int); 149 static void bwi_free_rx_ring32(struct bwi_softc *); 150 static void bwi_free_txstats32(struct bwi_softc *); 151 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 152 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 153 int, bus_addr_t, int); 154 static int bwi_rxeof32(struct bwi_softc *); 155 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 156 static void bwi_txeof_status32(struct bwi_softc *); 157 158 static int bwi_init_tx_ring64(struct bwi_softc *, int); 159 static int bwi_init_rx_ring64(struct bwi_softc *); 160 static int bwi_init_txstats64(struct bwi_softc *); 161 static void bwi_free_tx_ring64(struct bwi_softc *, int); 162 static void bwi_free_rx_ring64(struct bwi_softc *); 163 static void bwi_free_txstats64(struct bwi_softc *); 164 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 165 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 166 int, bus_addr_t, int); 167 static int bwi_rxeof64(struct bwi_softc *); 168 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 169 static void bwi_txeof_status64(struct bwi_softc *); 170 171 static int bwi_rxeof(struct bwi_softc *, int); 172 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 173 static void bwi_txeof(struct bwi_softc *); 174 static void bwi_txeof_status(struct bwi_softc *, int); 175 static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 176 static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 177 178 static int bwi_dma_alloc(struct bwi_softc *); 179 static void bwi_dma_free(struct bwi_softc *); 180 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 181 struct bwi_ring_data *, bus_size_t, 182 uint32_t); 183 static int bwi_dma_mbuf_create(struct bwi_softc *); 184 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 185 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 186 static void bwi_dma_txstats_free(struct bwi_softc *); 187 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 188 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 189 bus_size_t, int); 190 191 static void bwi_power_on(struct bwi_softc *, int); 192 static int bwi_power_off(struct bwi_softc *, int); 193 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 194 static int bwi_set_clock_delay(struct bwi_softc *); 195 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 196 static int bwi_get_pwron_delay(struct bwi_softc *sc); 197 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 198 const uint8_t *); 199 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 200 201 static void bwi_get_card_flags(struct bwi_softc *); 202 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 203 204 static int bwi_bus_attach(struct bwi_softc *); 205 static int bwi_bbp_attach(struct bwi_softc *); 206 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 207 static void bwi_bbp_power_off(struct bwi_softc *); 208 209 static const char *bwi_regwin_name(const struct bwi_regwin *); 210 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 211 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 212 static int bwi_regwin_select(struct bwi_softc *, int); 213 214 static void bwi_led_attach(struct bwi_softc *); 215 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 216 static void bwi_led_event(struct bwi_softc *, int); 217 static void bwi_led_blink_start(struct bwi_softc *, int, int); 218 static void bwi_led_blink_next(void *); 219 static void bwi_led_blink_end(void *); 220 221 static const struct { 222 uint16_t did_min; 223 uint16_t did_max; 224 uint16_t bbp_id; 225 } bwi_bbpid_map[] = { 226 { 0x4301, 0x4301, 0x4301 }, 227 { 0x4305, 0x4307, 0x4307 }, 228 { 0x4402, 0x4403, 0x4402 }, 229 { 0x4610, 0x4615, 0x4610 }, 230 { 0x4710, 0x4715, 0x4710 }, 231 { 0x4720, 0x4725, 0x4309 } 232 }; 233 234 static const struct { 235 uint16_t bbp_id; 236 int nregwin; 237 } bwi_regwin_count[] = { 238 { 0x4301, 5 }, 239 { 0x4306, 6 }, 240 { 0x4307, 5 }, 241 { 0x4310, 8 }, 242 { 0x4401, 3 }, 243 { 0x4402, 3 }, 244 { 0x4610, 9 }, 245 { 0x4704, 9 }, 246 { 0x4710, 9 }, 247 { 0x5365, 7 } 248 }; 249 250 #define CLKSRC(src) \ 251 [BWI_CLKSRC_ ## src] = { \ 252 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 253 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 254 } 255 256 static const struct { 257 u_int freq_min; 258 u_int freq_max; 259 } bwi_clkfreq[BWI_CLKSRC_MAX] = { 260 CLKSRC(LP_OSC), 261 CLKSRC(CS_OSC), 262 CLKSRC(PCI) 263 }; 264 265 #undef CLKSRC 266 267 #define VENDOR_LED_ACT(vendor) \ 268 { \ 269 .vid = PCI_VENDOR_##vendor, \ 270 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 271 } 272 273 static const struct { 274 #define PCI_VENDOR_COMPAQ 0x0e11 275 #define PCI_VENDOR_LINKSYS 0x1737 276 uint16_t vid; 277 uint8_t led_act[BWI_LED_MAX]; 278 } bwi_vendor_led_act[] = { 279 VENDOR_LED_ACT(COMPAQ), 280 VENDOR_LED_ACT(LINKSYS) 281 #undef PCI_VENDOR_LINKSYS 282 #undef PCI_VENDOR_COMPAQ 283 }; 284 285 static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 286 { BWI_VENDOR_LED_ACT_DEFAULT }; 287 288 #undef VENDOR_LED_ACT 289 290 static const struct { 291 int on_dur; 292 int off_dur; 293 } bwi_led_duration[109] = { 294 [0] = { 400, 100 }, 295 [2] = { 150, 75 }, 296 [4] = { 90, 45 }, 297 [11] = { 66, 34 }, 298 [12] = { 53, 26 }, 299 [18] = { 42, 21 }, 300 [22] = { 35, 17 }, 301 [24] = { 32, 16 }, 302 [36] = { 21, 10 }, 303 [48] = { 16, 8 }, 304 [72] = { 11, 5 }, 305 [96] = { 9, 4 }, 306 [108] = { 7, 3 } 307 }; 308 309 #ifdef BWI_DEBUG 310 #ifdef BWI_DEBUG_VERBOSE 311 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 312 #else 313 static uint32_t bwi_debug; 314 #endif 315 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 316 #endif /* BWI_DEBUG */ 317 318 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 319 320 uint16_t 321 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 322 { 323 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 324 } 325 326 static __inline void 327 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 328 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 329 int tx) 330 { 331 struct bwi_desc32 *desc = &desc_array[desc_idx]; 332 uint32_t ctrl, addr, addr_hi, addr_lo; 333 334 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 335 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 336 337 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 338 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 339 340 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 341 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 342 if (desc_idx == ndesc - 1) 343 ctrl |= BWI_DESC32_C_EOR; 344 if (tx) { 345 /* XXX */ 346 ctrl |= BWI_DESC32_C_FRAME_START | 347 BWI_DESC32_C_FRAME_END | 348 BWI_DESC32_C_INTR; 349 } 350 351 desc->addr = htole32(addr); 352 desc->ctrl = htole32(ctrl); 353 } 354 355 int 356 bwi_attach(struct bwi_softc *sc) 357 { 358 struct ieee80211com *ic = &sc->sc_ic; 359 device_t dev = sc->sc_dev; 360 struct bwi_mac *mac; 361 struct bwi_phy *phy; 362 int i, error; 363 364 BWI_LOCK_INIT(sc); 365 366 /* 367 * Initialize taskq and various tasks 368 */ 369 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 370 taskqueue_thread_enqueue, &sc->sc_tq); 371 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 372 device_get_nameunit(dev)); 373 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 374 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 375 mbufq_init(&sc->sc_snd, ifqmaxlen); 376 377 /* 378 * Initialize sysctl variables 379 */ 380 sc->sc_fw_version = BWI_FW_VERSION3; 381 sc->sc_led_idle = (2350 * hz) / 1000; 382 sc->sc_led_ticks = ticks - sc->sc_led_idle; 383 sc->sc_led_blink = 1; 384 sc->sc_txpwr_calib = 1; 385 #ifdef BWI_DEBUG 386 sc->sc_debug = bwi_debug; 387 #endif 388 bwi_power_on(sc, 1); 389 390 error = bwi_bbp_attach(sc); 391 if (error) 392 goto fail; 393 394 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 395 if (error) 396 goto fail; 397 398 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 399 error = bwi_set_clock_delay(sc); 400 if (error) 401 goto fail; 402 403 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 404 if (error) 405 goto fail; 406 407 error = bwi_get_pwron_delay(sc); 408 if (error) 409 goto fail; 410 } 411 412 error = bwi_bus_attach(sc); 413 if (error) 414 goto fail; 415 416 bwi_get_card_flags(sc); 417 418 bwi_led_attach(sc); 419 420 for (i = 0; i < sc->sc_nmac; ++i) { 421 struct bwi_regwin *old; 422 423 mac = &sc->sc_mac[i]; 424 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 425 if (error) 426 goto fail; 427 428 error = bwi_mac_lateattach(mac); 429 if (error) 430 goto fail; 431 432 error = bwi_regwin_switch(sc, old, NULL); 433 if (error) 434 goto fail; 435 } 436 437 /* 438 * XXX First MAC is known to exist 439 * TODO2 440 */ 441 mac = &sc->sc_mac[0]; 442 phy = &mac->mac_phy; 443 444 bwi_bbp_power_off(sc); 445 446 error = bwi_dma_alloc(sc); 447 if (error) 448 goto fail; 449 450 error = bwi_mac_fw_alloc(mac); 451 if (error) 452 goto fail; 453 454 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 455 456 /* 457 * Setup ratesets, phytype, channels and get MAC address 458 */ 459 if (phy->phy_mode == IEEE80211_MODE_11B || 460 phy->phy_mode == IEEE80211_MODE_11G) { 461 if (phy->phy_mode == IEEE80211_MODE_11B) { 462 ic->ic_phytype = IEEE80211_T_DS; 463 } else { 464 ic->ic_phytype = IEEE80211_T_OFDM; 465 } 466 467 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr); 468 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 469 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr); 470 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 471 device_printf(dev, 472 "invalid MAC address: %6D\n", 473 ic->ic_macaddr, ":"); 474 } 475 } 476 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 477 /* TODO:11A */ 478 error = ENXIO; 479 goto fail; 480 } else { 481 panic("unknown phymode %d\n", phy->phy_mode); 482 } 483 484 /* Get locale */ 485 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 486 BWI_SPROM_CARD_INFO_LOCALE); 487 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 488 /* XXX use locale */ 489 490 ic->ic_softc = sc; 491 492 bwi_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 493 ic->ic_channels); 494 495 ic->ic_name = device_get_nameunit(dev); 496 ic->ic_caps = IEEE80211_C_STA | 497 IEEE80211_C_SHSLOT | 498 IEEE80211_C_SHPREAMBLE | 499 IEEE80211_C_WPA | 500 IEEE80211_C_BGSCAN | 501 IEEE80211_C_MONITOR; 502 ic->ic_opmode = IEEE80211_M_STA; 503 ieee80211_ifattach(ic); 504 505 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 506 507 /* override default methods */ 508 ic->ic_vap_create = bwi_vap_create; 509 ic->ic_vap_delete = bwi_vap_delete; 510 ic->ic_raw_xmit = bwi_raw_xmit; 511 ic->ic_updateslot = bwi_updateslot; 512 ic->ic_scan_start = bwi_scan_start; 513 ic->ic_scan_end = bwi_scan_end; 514 ic->ic_getradiocaps = bwi_getradiocaps; 515 ic->ic_set_channel = bwi_set_channel; 516 ic->ic_transmit = bwi_transmit; 517 ic->ic_parent = bwi_parent; 518 519 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 520 521 ieee80211_radiotap_attach(ic, 522 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 523 BWI_TX_RADIOTAP_PRESENT, 524 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 525 BWI_RX_RADIOTAP_PRESENT); 526 527 /* 528 * Add sysctl nodes 529 */ 530 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 531 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 532 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 533 "Firmware version"); 534 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 535 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 536 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 537 "# ticks before LED enters idle state"); 538 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 539 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 540 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 541 "Allow LED to blink"); 542 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 543 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 544 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 545 "Enable software TX power calibration"); 546 #ifdef BWI_DEBUG 547 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 548 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 549 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 550 #endif 551 if (bootverbose) 552 ieee80211_announce(ic); 553 554 return (0); 555 fail: 556 BWI_LOCK_DESTROY(sc); 557 return (error); 558 } 559 560 int 561 bwi_detach(struct bwi_softc *sc) 562 { 563 struct ieee80211com *ic = &sc->sc_ic; 564 int i; 565 566 bwi_stop(sc, 1); 567 callout_drain(&sc->sc_led_blink_ch); 568 callout_drain(&sc->sc_calib_ch); 569 callout_drain(&sc->sc_watchdog_timer); 570 ieee80211_ifdetach(ic); 571 572 for (i = 0; i < sc->sc_nmac; ++i) 573 bwi_mac_detach(&sc->sc_mac[i]); 574 bwi_dma_free(sc); 575 taskqueue_free(sc->sc_tq); 576 mbufq_drain(&sc->sc_snd); 577 578 BWI_LOCK_DESTROY(sc); 579 580 return (0); 581 } 582 583 static struct ieee80211vap * 584 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 585 enum ieee80211_opmode opmode, int flags, 586 const uint8_t bssid[IEEE80211_ADDR_LEN], 587 const uint8_t mac[IEEE80211_ADDR_LEN]) 588 { 589 struct bwi_vap *bvp; 590 struct ieee80211vap *vap; 591 592 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 593 return NULL; 594 bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO); 595 vap = &bvp->bv_vap; 596 /* enable s/w bmiss handling for sta mode */ 597 ieee80211_vap_setup(ic, vap, name, unit, opmode, 598 flags | IEEE80211_CLONE_NOBEACONS, bssid); 599 600 /* override default methods */ 601 bvp->bv_newstate = vap->iv_newstate; 602 vap->iv_newstate = bwi_newstate; 603 #if 0 604 vap->iv_update_beacon = bwi_beacon_update; 605 #endif 606 ieee80211_ratectl_init(vap); 607 608 /* complete setup */ 609 ieee80211_vap_attach(vap, ieee80211_media_change, 610 ieee80211_media_status, mac); 611 ic->ic_opmode = opmode; 612 return vap; 613 } 614 615 static void 616 bwi_vap_delete(struct ieee80211vap *vap) 617 { 618 struct bwi_vap *bvp = BWI_VAP(vap); 619 620 ieee80211_ratectl_deinit(vap); 621 ieee80211_vap_detach(vap); 622 free(bvp, M_80211_VAP); 623 } 624 625 void 626 bwi_suspend(struct bwi_softc *sc) 627 { 628 bwi_stop(sc, 1); 629 } 630 631 void 632 bwi_resume(struct bwi_softc *sc) 633 { 634 635 if (sc->sc_ic.ic_nrunning > 0) 636 bwi_init(sc); 637 } 638 639 int 640 bwi_shutdown(struct bwi_softc *sc) 641 { 642 bwi_stop(sc, 1); 643 return 0; 644 } 645 646 static void 647 bwi_power_on(struct bwi_softc *sc, int with_pll) 648 { 649 uint32_t gpio_in, gpio_out, gpio_en; 650 uint16_t status; 651 652 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 653 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 654 goto back; 655 656 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 657 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 658 659 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 660 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 661 if (with_pll) { 662 /* Turn off PLL first */ 663 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 664 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 665 } 666 667 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 668 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 669 DELAY(1000); 670 671 if (with_pll) { 672 /* Turn on PLL */ 673 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 674 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 675 DELAY(5000); 676 } 677 678 back: 679 /* Clear "Signaled Target Abort" */ 680 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 681 status &= ~PCIM_STATUS_STABORT; 682 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 683 } 684 685 static int 686 bwi_power_off(struct bwi_softc *sc, int with_pll) 687 { 688 uint32_t gpio_out, gpio_en; 689 690 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 691 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 692 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 693 694 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 695 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 696 if (with_pll) { 697 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 698 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 699 } 700 701 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 702 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 703 return 0; 704 } 705 706 int 707 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 708 struct bwi_regwin **old_rw) 709 { 710 int error; 711 712 if (old_rw != NULL) 713 *old_rw = NULL; 714 715 if (!BWI_REGWIN_EXIST(rw)) 716 return EINVAL; 717 718 if (sc->sc_cur_regwin != rw) { 719 error = bwi_regwin_select(sc, rw->rw_id); 720 if (error) { 721 device_printf(sc->sc_dev, "can't select regwin %d\n", 722 rw->rw_id); 723 return error; 724 } 725 } 726 727 if (old_rw != NULL) 728 *old_rw = sc->sc_cur_regwin; 729 sc->sc_cur_regwin = rw; 730 return 0; 731 } 732 733 static int 734 bwi_regwin_select(struct bwi_softc *sc, int id) 735 { 736 uint32_t win = BWI_PCIM_REGWIN(id); 737 int i; 738 739 #define RETRY_MAX 50 740 for (i = 0; i < RETRY_MAX; ++i) { 741 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 742 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 743 return 0; 744 DELAY(10); 745 } 746 #undef RETRY_MAX 747 748 return ENXIO; 749 } 750 751 static void 752 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 753 { 754 uint32_t val; 755 756 val = CSR_READ_4(sc, BWI_ID_HI); 757 *type = BWI_ID_HI_REGWIN_TYPE(val); 758 *rev = BWI_ID_HI_REGWIN_REV(val); 759 760 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 761 "vendor 0x%04x\n", *type, *rev, 762 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 763 } 764 765 static int 766 bwi_bbp_attach(struct bwi_softc *sc) 767 { 768 uint16_t bbp_id, rw_type; 769 uint8_t rw_rev; 770 uint32_t info; 771 int error, nregwin, i; 772 773 /* 774 * Get 0th regwin information 775 * NOTE: 0th regwin should exist 776 */ 777 error = bwi_regwin_select(sc, 0); 778 if (error) { 779 device_printf(sc->sc_dev, "can't select regwin 0\n"); 780 return error; 781 } 782 bwi_regwin_info(sc, &rw_type, &rw_rev); 783 784 /* 785 * Find out BBP id 786 */ 787 bbp_id = 0; 788 info = 0; 789 if (rw_type == BWI_REGWIN_T_COM) { 790 info = CSR_READ_4(sc, BWI_INFO); 791 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 792 793 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 794 795 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 796 } else { 797 for (i = 0; i < nitems(bwi_bbpid_map); ++i) { 798 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 799 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 800 bbp_id = bwi_bbpid_map[i].bbp_id; 801 break; 802 } 803 } 804 if (bbp_id == 0) { 805 device_printf(sc->sc_dev, "no BBP id for device id " 806 "0x%04x\n", sc->sc_pci_did); 807 return ENXIO; 808 } 809 810 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 811 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 812 } 813 814 /* 815 * Find out number of regwins 816 */ 817 nregwin = 0; 818 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 819 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 820 } else { 821 for (i = 0; i < nitems(bwi_regwin_count); ++i) { 822 if (bwi_regwin_count[i].bbp_id == bbp_id) { 823 nregwin = bwi_regwin_count[i].nregwin; 824 break; 825 } 826 } 827 if (nregwin == 0) { 828 device_printf(sc->sc_dev, "no number of win for " 829 "BBP id 0x%04x\n", bbp_id); 830 return ENXIO; 831 } 832 } 833 834 /* Record BBP id/rev for later using */ 835 sc->sc_bbp_id = bbp_id; 836 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 837 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 838 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 839 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 840 841 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 842 nregwin, sc->sc_cap); 843 844 /* 845 * Create rest of the regwins 846 */ 847 848 /* Don't re-create common regwin, if it is already created */ 849 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 850 851 for (; i < nregwin; ++i) { 852 /* 853 * Get regwin information 854 */ 855 error = bwi_regwin_select(sc, i); 856 if (error) { 857 device_printf(sc->sc_dev, 858 "can't select regwin %d\n", i); 859 return error; 860 } 861 bwi_regwin_info(sc, &rw_type, &rw_rev); 862 863 /* 864 * Try attach: 865 * 1) Bus (PCI/PCIE) regwin 866 * 2) MAC regwin 867 * Ignore rest types of regwin 868 */ 869 if (rw_type == BWI_REGWIN_T_BUSPCI || 870 rw_type == BWI_REGWIN_T_BUSPCIE) { 871 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 872 device_printf(sc->sc_dev, 873 "bus regwin already exists\n"); 874 } else { 875 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 876 rw_type, rw_rev); 877 } 878 } else if (rw_type == BWI_REGWIN_T_MAC) { 879 /* XXX ignore return value */ 880 bwi_mac_attach(sc, i, rw_rev); 881 } 882 } 883 884 /* At least one MAC shold exist */ 885 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 886 device_printf(sc->sc_dev, "no MAC was found\n"); 887 return ENXIO; 888 } 889 KASSERT(sc->sc_nmac > 0, ("no mac's")); 890 891 /* Bus regwin must exist */ 892 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 893 device_printf(sc->sc_dev, "no bus regwin was found\n"); 894 return ENXIO; 895 } 896 897 /* Start with first MAC */ 898 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 899 if (error) 900 return error; 901 902 return 0; 903 } 904 905 int 906 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 907 { 908 struct bwi_regwin *old, *bus; 909 uint32_t val; 910 int error; 911 912 bus = &sc->sc_bus_regwin; 913 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 914 915 /* 916 * Tell bus to generate requested interrupts 917 */ 918 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 919 /* 920 * NOTE: Read BWI_FLAGS from MAC regwin 921 */ 922 val = CSR_READ_4(sc, BWI_FLAGS); 923 924 error = bwi_regwin_switch(sc, bus, &old); 925 if (error) 926 return error; 927 928 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 929 } else { 930 uint32_t mac_mask; 931 932 mac_mask = 1 << mac->mac_id; 933 934 error = bwi_regwin_switch(sc, bus, &old); 935 if (error) 936 return error; 937 938 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 939 val |= mac_mask << 8; 940 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 941 } 942 943 if (sc->sc_flags & BWI_F_BUS_INITED) 944 goto back; 945 946 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 947 /* 948 * Enable prefetch and burst 949 */ 950 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 951 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 952 953 if (bus->rw_rev < 5) { 954 struct bwi_regwin *com = &sc->sc_com_regwin; 955 956 /* 957 * Configure timeouts for bus operation 958 */ 959 960 /* 961 * Set service timeout and request timeout 962 */ 963 CSR_SETBITS_4(sc, BWI_CONF_LO, 964 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 965 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 966 967 /* 968 * If there is common regwin, we switch to that regwin 969 * and switch back to bus regwin once we have done. 970 */ 971 if (BWI_REGWIN_EXIST(com)) { 972 error = bwi_regwin_switch(sc, com, NULL); 973 if (error) 974 return error; 975 } 976 977 /* Let bus know what we have changed */ 978 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 979 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 980 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 981 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 982 983 if (BWI_REGWIN_EXIST(com)) { 984 error = bwi_regwin_switch(sc, bus, NULL); 985 if (error) 986 return error; 987 } 988 } else if (bus->rw_rev >= 11) { 989 /* 990 * Enable memory read multiple 991 */ 992 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 993 } 994 } else { 995 /* TODO:PCIE */ 996 } 997 998 sc->sc_flags |= BWI_F_BUS_INITED; 999 back: 1000 return bwi_regwin_switch(sc, old, NULL); 1001 } 1002 1003 static void 1004 bwi_get_card_flags(struct bwi_softc *sc) 1005 { 1006 #define PCI_VENDOR_APPLE 0x106b 1007 #define PCI_VENDOR_DELL 0x1028 1008 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1009 if (sc->sc_card_flags == 0xffff) 1010 sc->sc_card_flags = 0; 1011 1012 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1013 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1014 sc->sc_pci_revid == 0x74) 1015 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1016 1017 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1018 sc->sc_pci_subdid == 0x4e && /* XXX */ 1019 sc->sc_pci_revid > 0x40) 1020 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1021 1022 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1023 #undef PCI_VENDOR_DELL 1024 #undef PCI_VENDOR_APPLE 1025 } 1026 1027 static void 1028 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1029 { 1030 int i; 1031 1032 for (i = 0; i < 3; ++i) { 1033 *((uint16_t *)eaddr + i) = 1034 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1035 } 1036 } 1037 1038 static void 1039 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1040 { 1041 struct bwi_regwin *com; 1042 uint32_t val; 1043 u_int div; 1044 int src; 1045 1046 bzero(freq, sizeof(*freq)); 1047 com = &sc->sc_com_regwin; 1048 1049 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1050 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1051 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1052 1053 /* 1054 * Calculate clock frequency 1055 */ 1056 src = -1; 1057 div = 0; 1058 if (com->rw_rev < 6) { 1059 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1060 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1061 src = BWI_CLKSRC_PCI; 1062 div = 64; 1063 } else { 1064 src = BWI_CLKSRC_CS_OSC; 1065 div = 32; 1066 } 1067 } else if (com->rw_rev < 10) { 1068 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1069 1070 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1071 if (src == BWI_CLKSRC_LP_OSC) { 1072 div = 1; 1073 } else { 1074 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1075 1076 /* Unknown source */ 1077 if (src >= BWI_CLKSRC_MAX) 1078 src = BWI_CLKSRC_CS_OSC; 1079 } 1080 } else { 1081 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1082 1083 src = BWI_CLKSRC_CS_OSC; 1084 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1085 } 1086 1087 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1088 KASSERT(div != 0, ("div zero")); 1089 1090 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1091 src == BWI_CLKSRC_PCI ? "PCI" : 1092 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1093 1094 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1095 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1096 1097 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1098 freq->clkfreq_min, freq->clkfreq_max); 1099 } 1100 1101 static int 1102 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1103 { 1104 struct bwi_regwin *old, *com; 1105 uint32_t clk_ctrl, clk_src; 1106 int error, pwr_off = 0; 1107 1108 com = &sc->sc_com_regwin; 1109 if (!BWI_REGWIN_EXIST(com)) 1110 return 0; 1111 1112 if (com->rw_rev >= 10 || com->rw_rev < 6) 1113 return 0; 1114 1115 /* 1116 * For common regwin whose rev is [6, 10), the chip 1117 * must be capable to change clock mode. 1118 */ 1119 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1120 return 0; 1121 1122 error = bwi_regwin_switch(sc, com, &old); 1123 if (error) 1124 return error; 1125 1126 if (clk_mode == BWI_CLOCK_MODE_FAST) 1127 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1128 1129 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1130 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1131 1132 switch (clk_mode) { 1133 case BWI_CLOCK_MODE_FAST: 1134 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1135 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1136 break; 1137 case BWI_CLOCK_MODE_SLOW: 1138 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1139 break; 1140 case BWI_CLOCK_MODE_DYN: 1141 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1142 BWI_CLOCK_CTRL_IGNPLL | 1143 BWI_CLOCK_CTRL_NODYN); 1144 if (clk_src != BWI_CLKSRC_CS_OSC) { 1145 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1146 pwr_off = 1; 1147 } 1148 break; 1149 } 1150 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1151 1152 if (pwr_off) 1153 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1154 1155 return bwi_regwin_switch(sc, old, NULL); 1156 } 1157 1158 static int 1159 bwi_set_clock_delay(struct bwi_softc *sc) 1160 { 1161 struct bwi_regwin *old, *com; 1162 int error; 1163 1164 com = &sc->sc_com_regwin; 1165 if (!BWI_REGWIN_EXIST(com)) 1166 return 0; 1167 1168 error = bwi_regwin_switch(sc, com, &old); 1169 if (error) 1170 return error; 1171 1172 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1173 if (sc->sc_bbp_rev == 0) 1174 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1175 else if (sc->sc_bbp_rev == 1) 1176 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1177 } 1178 1179 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1180 if (com->rw_rev >= 10) { 1181 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1182 } else { 1183 struct bwi_clock_freq freq; 1184 1185 bwi_get_clock_freq(sc, &freq); 1186 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1187 howmany(freq.clkfreq_max * 150, 1000000)); 1188 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1189 howmany(freq.clkfreq_max * 15, 1000000)); 1190 } 1191 } 1192 1193 return bwi_regwin_switch(sc, old, NULL); 1194 } 1195 1196 static void 1197 bwi_init(struct bwi_softc *sc) 1198 { 1199 struct ieee80211com *ic = &sc->sc_ic; 1200 1201 BWI_LOCK(sc); 1202 bwi_init_statechg(sc, 1); 1203 BWI_UNLOCK(sc); 1204 1205 if (sc->sc_flags & BWI_F_RUNNING) 1206 ieee80211_start_all(ic); /* start all vap's */ 1207 } 1208 1209 static void 1210 bwi_init_statechg(struct bwi_softc *sc, int statechg) 1211 { 1212 struct bwi_mac *mac; 1213 int error; 1214 1215 BWI_ASSERT_LOCKED(sc); 1216 1217 bwi_stop_locked(sc, statechg); 1218 1219 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1220 1221 /* TODO: 2 MAC */ 1222 1223 mac = &sc->sc_mac[0]; 1224 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1225 if (error) { 1226 device_printf(sc->sc_dev, "%s: error %d on regwin switch\n", 1227 __func__, error); 1228 goto bad; 1229 } 1230 error = bwi_mac_init(mac); 1231 if (error) { 1232 device_printf(sc->sc_dev, "%s: error %d on MAC init\n", 1233 __func__, error); 1234 goto bad; 1235 } 1236 1237 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1238 1239 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1240 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr); 1241 1242 bwi_mac_reset_hwkeys(mac); 1243 1244 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1245 int i; 1246 1247 #define NRETRY 1000 1248 /* 1249 * Drain any possible pending TX status 1250 */ 1251 for (i = 0; i < NRETRY; ++i) { 1252 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1253 BWI_TXSTATUS0_VALID) == 0) 1254 break; 1255 CSR_READ_4(sc, BWI_TXSTATUS1); 1256 } 1257 if (i == NRETRY) 1258 device_printf(sc->sc_dev, 1259 "%s: can't drain TX status\n", __func__); 1260 #undef NRETRY 1261 } 1262 1263 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1264 bwi_mac_updateslot(mac, 1); 1265 1266 /* Start MAC */ 1267 error = bwi_mac_start(mac); 1268 if (error) { 1269 device_printf(sc->sc_dev, "%s: error %d starting MAC\n", 1270 __func__, error); 1271 goto bad; 1272 } 1273 1274 /* Clear stop flag before enabling interrupt */ 1275 sc->sc_flags &= ~BWI_F_STOP; 1276 sc->sc_flags |= BWI_F_RUNNING; 1277 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1278 1279 /* Enable intrs */ 1280 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1281 return; 1282 bad: 1283 bwi_stop_locked(sc, 1); 1284 } 1285 1286 static void 1287 bwi_parent(struct ieee80211com *ic) 1288 { 1289 struct bwi_softc *sc = ic->ic_softc; 1290 int startall = 0; 1291 1292 BWI_LOCK(sc); 1293 if (ic->ic_nrunning > 0) { 1294 struct bwi_mac *mac; 1295 int promisc = -1; 1296 1297 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1298 ("current regwin type %d", 1299 sc->sc_cur_regwin->rw_type)); 1300 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1301 1302 if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) { 1303 promisc = 1; 1304 sc->sc_flags |= BWI_F_PROMISC; 1305 } else if (ic->ic_promisc == 0 && 1306 (sc->sc_flags & BWI_F_PROMISC) != 0) { 1307 promisc = 0; 1308 sc->sc_flags &= ~BWI_F_PROMISC; 1309 } 1310 1311 if (promisc >= 0) 1312 bwi_mac_set_promisc(mac, promisc); 1313 } 1314 if (ic->ic_nrunning > 0) { 1315 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1316 bwi_init_statechg(sc, 1); 1317 startall = 1; 1318 } 1319 } else if (sc->sc_flags & BWI_F_RUNNING) 1320 bwi_stop_locked(sc, 1); 1321 BWI_UNLOCK(sc); 1322 if (startall) 1323 ieee80211_start_all(ic); 1324 } 1325 1326 static int 1327 bwi_transmit(struct ieee80211com *ic, struct mbuf *m) 1328 { 1329 struct bwi_softc *sc = ic->ic_softc; 1330 int error; 1331 1332 BWI_LOCK(sc); 1333 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1334 BWI_UNLOCK(sc); 1335 return (ENXIO); 1336 } 1337 error = mbufq_enqueue(&sc->sc_snd, m); 1338 if (error) { 1339 BWI_UNLOCK(sc); 1340 return (error); 1341 } 1342 bwi_start_locked(sc); 1343 BWI_UNLOCK(sc); 1344 return (0); 1345 } 1346 1347 static void 1348 bwi_start_locked(struct bwi_softc *sc) 1349 { 1350 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1351 struct ieee80211_frame *wh; 1352 struct ieee80211_node *ni; 1353 struct mbuf *m; 1354 int trans, idx; 1355 1356 BWI_ASSERT_LOCKED(sc); 1357 1358 trans = 0; 1359 idx = tbd->tbd_idx; 1360 1361 while (tbd->tbd_buf[idx].tb_mbuf == NULL && 1362 tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC && 1363 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1364 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1365 wh = mtod(m, struct ieee80211_frame *); 1366 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 && 1367 ieee80211_crypto_encap(ni, m) == NULL) { 1368 if_inc_counter(ni->ni_vap->iv_ifp, 1369 IFCOUNTER_OERRORS, 1); 1370 ieee80211_free_node(ni); 1371 m_freem(m); 1372 continue; 1373 } 1374 if (bwi_encap(sc, idx, m, ni) != 0) { 1375 /* 'm' is freed in bwi_encap() if we reach here */ 1376 if (ni != NULL) { 1377 if_inc_counter(ni->ni_vap->iv_ifp, 1378 IFCOUNTER_OERRORS, 1); 1379 ieee80211_free_node(ni); 1380 } else 1381 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1382 continue; 1383 } 1384 trans = 1; 1385 tbd->tbd_used++; 1386 idx = (idx + 1) % BWI_TX_NDESC; 1387 } 1388 1389 tbd->tbd_idx = idx; 1390 if (trans) 1391 sc->sc_tx_timer = 5; 1392 } 1393 1394 static int 1395 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1396 const struct ieee80211_bpf_params *params) 1397 { 1398 struct ieee80211com *ic = ni->ni_ic; 1399 struct bwi_softc *sc = ic->ic_softc; 1400 /* XXX wme? */ 1401 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1402 int idx, error; 1403 1404 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1405 m_freem(m); 1406 return ENETDOWN; 1407 } 1408 1409 BWI_LOCK(sc); 1410 idx = tbd->tbd_idx; 1411 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1412 if (params == NULL) { 1413 /* 1414 * Legacy path; interpret frame contents to decide 1415 * precisely how to send the frame. 1416 */ 1417 error = bwi_encap(sc, idx, m, ni); 1418 } else { 1419 /* 1420 * Caller supplied explicit parameters to use in 1421 * sending the frame. 1422 */ 1423 error = bwi_encap_raw(sc, idx, m, ni, params); 1424 } 1425 if (error == 0) { 1426 tbd->tbd_used++; 1427 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1428 sc->sc_tx_timer = 5; 1429 } 1430 BWI_UNLOCK(sc); 1431 return error; 1432 } 1433 1434 static void 1435 bwi_watchdog(void *arg) 1436 { 1437 struct bwi_softc *sc; 1438 1439 sc = arg; 1440 BWI_ASSERT_LOCKED(sc); 1441 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1442 device_printf(sc->sc_dev, "watchdog timeout\n"); 1443 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1444 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1445 } 1446 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1447 } 1448 1449 static void 1450 bwi_stop(struct bwi_softc *sc, int statechg) 1451 { 1452 BWI_LOCK(sc); 1453 bwi_stop_locked(sc, statechg); 1454 BWI_UNLOCK(sc); 1455 } 1456 1457 static void 1458 bwi_stop_locked(struct bwi_softc *sc, int statechg) 1459 { 1460 struct bwi_mac *mac; 1461 int i, error, pwr_off = 0; 1462 1463 BWI_ASSERT_LOCKED(sc); 1464 1465 callout_stop(&sc->sc_calib_ch); 1466 callout_stop(&sc->sc_led_blink_ch); 1467 sc->sc_led_blinking = 0; 1468 sc->sc_flags |= BWI_F_STOP; 1469 1470 if (sc->sc_flags & BWI_F_RUNNING) { 1471 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1472 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1473 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1474 1475 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1476 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1477 bwi_mac_stop(mac); 1478 } 1479 1480 for (i = 0; i < sc->sc_nmac; ++i) { 1481 struct bwi_regwin *old_rw; 1482 1483 mac = &sc->sc_mac[i]; 1484 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1485 continue; 1486 1487 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1488 if (error) 1489 continue; 1490 1491 bwi_mac_shutdown(mac); 1492 pwr_off = 1; 1493 1494 bwi_regwin_switch(sc, old_rw, NULL); 1495 } 1496 1497 if (pwr_off) 1498 bwi_bbp_power_off(sc); 1499 1500 sc->sc_tx_timer = 0; 1501 callout_stop(&sc->sc_watchdog_timer); 1502 sc->sc_flags &= ~BWI_F_RUNNING; 1503 } 1504 1505 void 1506 bwi_intr(void *xsc) 1507 { 1508 struct bwi_softc *sc = xsc; 1509 struct bwi_mac *mac; 1510 uint32_t intr_status; 1511 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1512 int i, txrx_error, tx = 0, rx_data = -1; 1513 1514 BWI_LOCK(sc); 1515 1516 if ((sc->sc_flags & BWI_F_RUNNING) == 0 || 1517 (sc->sc_flags & BWI_F_STOP)) { 1518 BWI_UNLOCK(sc); 1519 return; 1520 } 1521 /* 1522 * Get interrupt status 1523 */ 1524 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1525 if (intr_status == 0xffffffff) { /* Not for us */ 1526 BWI_UNLOCK(sc); 1527 return; 1528 } 1529 1530 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1531 1532 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1533 if (intr_status == 0) { /* Nothing is interesting */ 1534 BWI_UNLOCK(sc); 1535 return; 1536 } 1537 1538 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1539 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1540 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1541 1542 txrx_error = 0; 1543 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1544 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1545 uint32_t mask; 1546 1547 if (BWI_TXRX_IS_RX(i)) 1548 mask = BWI_TXRX_RX_INTRS; 1549 else 1550 mask = BWI_TXRX_TX_INTRS; 1551 1552 txrx_intr_status[i] = 1553 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1554 1555 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1556 i, txrx_intr_status[i]); 1557 1558 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1559 device_printf(sc->sc_dev, 1560 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1561 __func__, i, txrx_intr_status[i]); 1562 txrx_error = 1; 1563 } 1564 } 1565 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1566 1567 /* 1568 * Acknowledge interrupt 1569 */ 1570 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1571 1572 for (i = 0; i < BWI_TXRX_NRING; ++i) 1573 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1574 1575 /* Disable all interrupts */ 1576 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1577 1578 /* 1579 * http://bcm-specs.sipsolutions.net/Interrupts 1580 * Says for this bit (0x800): 1581 * "Fatal Error 1582 * 1583 * We got this one while testing things when by accident the 1584 * template ram wasn't set to big endian when it should have 1585 * been after writing the initial values. It keeps on being 1586 * triggered, the only way to stop it seems to shut down the 1587 * chip." 1588 * 1589 * Suggesting that we should never get it and if we do we're not 1590 * feeding TX packets into the MAC correctly if we do... Apparently, 1591 * it is valid only on mac version 5 and higher, but I couldn't 1592 * find a reference for that... Since I see them from time to time 1593 * on my card, this suggests an error in the tx path still... 1594 */ 1595 if (intr_status & BWI_INTR_PHY_TXERR) { 1596 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1597 device_printf(sc->sc_dev, "%s: intr PHY TX error\n", 1598 __func__); 1599 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1600 BWI_UNLOCK(sc); 1601 return; 1602 } 1603 } 1604 1605 if (txrx_error) { 1606 /* TODO: reset device */ 1607 } 1608 1609 if (intr_status & BWI_INTR_TBTT) 1610 bwi_mac_config_ps(mac); 1611 1612 if (intr_status & BWI_INTR_EO_ATIM) 1613 device_printf(sc->sc_dev, "EO_ATIM\n"); 1614 1615 if (intr_status & BWI_INTR_PMQ) { 1616 for (;;) { 1617 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1618 break; 1619 } 1620 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1621 } 1622 1623 if (intr_status & BWI_INTR_NOISE) 1624 device_printf(sc->sc_dev, "intr noise\n"); 1625 1626 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1627 rx_data = sc->sc_rxeof(sc); 1628 if (sc->sc_flags & BWI_F_STOP) { 1629 BWI_UNLOCK(sc); 1630 return; 1631 } 1632 } 1633 1634 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1635 sc->sc_txeof_status(sc); 1636 tx = 1; 1637 } 1638 1639 if (intr_status & BWI_INTR_TX_DONE) { 1640 bwi_txeof(sc); 1641 tx = 1; 1642 } 1643 1644 /* Re-enable interrupts */ 1645 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1646 1647 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1648 int evt = BWI_LED_EVENT_NONE; 1649 1650 if (tx && rx_data > 0) { 1651 if (sc->sc_rx_rate > sc->sc_tx_rate) 1652 evt = BWI_LED_EVENT_RX; 1653 else 1654 evt = BWI_LED_EVENT_TX; 1655 } else if (tx) { 1656 evt = BWI_LED_EVENT_TX; 1657 } else if (rx_data > 0) { 1658 evt = BWI_LED_EVENT_RX; 1659 } else if (rx_data == 0) { 1660 evt = BWI_LED_EVENT_POLL; 1661 } 1662 1663 if (evt != BWI_LED_EVENT_NONE) 1664 bwi_led_event(sc, evt); 1665 } 1666 1667 BWI_UNLOCK(sc); 1668 } 1669 1670 static void 1671 bwi_scan_start(struct ieee80211com *ic) 1672 { 1673 struct bwi_softc *sc = ic->ic_softc; 1674 1675 BWI_LOCK(sc); 1676 /* Enable MAC beacon promiscuity */ 1677 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1678 BWI_UNLOCK(sc); 1679 } 1680 1681 static void 1682 bwi_getradiocaps(struct ieee80211com *ic, 1683 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1684 { 1685 struct bwi_softc *sc = ic->ic_softc; 1686 struct bwi_mac *mac; 1687 struct bwi_phy *phy; 1688 uint8_t bands[IEEE80211_MODE_BYTES]; 1689 1690 /* 1691 * XXX First MAC is known to exist 1692 * TODO2 1693 */ 1694 mac = &sc->sc_mac[0]; 1695 phy = &mac->mac_phy; 1696 1697 memset(bands, 0, sizeof(bands)); 1698 switch (phy->phy_mode) { 1699 case IEEE80211_MODE_11G: 1700 setbit(bands, IEEE80211_MODE_11G); 1701 /* FALLTHROUGH */ 1702 case IEEE80211_MODE_11B: 1703 setbit(bands, IEEE80211_MODE_11B); 1704 break; 1705 case IEEE80211_MODE_11A: 1706 /* TODO:11A */ 1707 setbit(bands, IEEE80211_MODE_11A); 1708 device_printf(sc->sc_dev, "no 11a support\n"); 1709 return; 1710 default: 1711 panic("unknown phymode %d\n", phy->phy_mode); 1712 } 1713 1714 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 1715 } 1716 1717 static void 1718 bwi_set_channel(struct ieee80211com *ic) 1719 { 1720 struct bwi_softc *sc = ic->ic_softc; 1721 struct ieee80211_channel *c = ic->ic_curchan; 1722 struct bwi_mac *mac; 1723 1724 BWI_LOCK(sc); 1725 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1726 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1727 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1728 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1729 1730 sc->sc_rates = ieee80211_get_ratetable(c); 1731 BWI_UNLOCK(sc); 1732 } 1733 1734 static void 1735 bwi_scan_end(struct ieee80211com *ic) 1736 { 1737 struct bwi_softc *sc = ic->ic_softc; 1738 1739 BWI_LOCK(sc); 1740 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1741 BWI_UNLOCK(sc); 1742 } 1743 1744 static int 1745 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1746 { 1747 struct bwi_vap *bvp = BWI_VAP(vap); 1748 struct ieee80211com *ic= vap->iv_ic; 1749 struct bwi_softc *sc = ic->ic_softc; 1750 enum ieee80211_state ostate = vap->iv_state; 1751 struct bwi_mac *mac; 1752 int error; 1753 1754 BWI_LOCK(sc); 1755 1756 callout_stop(&sc->sc_calib_ch); 1757 1758 if (nstate == IEEE80211_S_INIT) 1759 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1760 1761 bwi_led_newstate(sc, nstate); 1762 1763 error = bvp->bv_newstate(vap, nstate, arg); 1764 if (error != 0) 1765 goto back; 1766 1767 /* 1768 * Clear the BSSID when we stop a STA 1769 */ 1770 if (vap->iv_opmode == IEEE80211_M_STA) { 1771 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1772 /* 1773 * Clear out the BSSID. If we reassociate to 1774 * the same AP, this will reinialize things 1775 * correctly... 1776 */ 1777 if (ic->ic_opmode == IEEE80211_M_STA && 1778 !(sc->sc_flags & BWI_F_STOP)) 1779 bwi_set_bssid(sc, bwi_zero_addr); 1780 } 1781 } 1782 1783 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1784 /* Nothing to do */ 1785 } else if (nstate == IEEE80211_S_RUN) { 1786 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1787 1788 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1789 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1790 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1791 1792 /* Initial TX power calibration */ 1793 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1794 #ifdef notyet 1795 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1796 #else 1797 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1798 #endif 1799 1800 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1801 } 1802 back: 1803 BWI_UNLOCK(sc); 1804 1805 return error; 1806 } 1807 1808 static int 1809 bwi_dma_alloc(struct bwi_softc *sc) 1810 { 1811 int error, i, has_txstats; 1812 bus_addr_t lowaddr = 0; 1813 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1814 uint32_t txrx_ctrl_step = 0; 1815 1816 has_txstats = 0; 1817 for (i = 0; i < sc->sc_nmac; ++i) { 1818 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1819 has_txstats = 1; 1820 break; 1821 } 1822 } 1823 1824 switch (sc->sc_bus_space) { 1825 case BWI_BUS_SPACE_30BIT: 1826 case BWI_BUS_SPACE_32BIT: 1827 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1828 lowaddr = BWI_BUS_SPACE_MAXADDR; 1829 else 1830 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1831 desc_sz = sizeof(struct bwi_desc32); 1832 txrx_ctrl_step = 0x20; 1833 1834 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1835 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1836 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1837 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1838 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1839 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1840 sc->sc_rxeof = bwi_rxeof32; 1841 sc->sc_start_tx = bwi_start_tx32; 1842 if (has_txstats) { 1843 sc->sc_init_txstats = bwi_init_txstats32; 1844 sc->sc_free_txstats = bwi_free_txstats32; 1845 sc->sc_txeof_status = bwi_txeof_status32; 1846 } 1847 break; 1848 1849 case BWI_BUS_SPACE_64BIT: 1850 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1851 desc_sz = sizeof(struct bwi_desc64); 1852 txrx_ctrl_step = 0x40; 1853 1854 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1855 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1856 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1857 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1858 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1859 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1860 sc->sc_rxeof = bwi_rxeof64; 1861 sc->sc_start_tx = bwi_start_tx64; 1862 if (has_txstats) { 1863 sc->sc_init_txstats = bwi_init_txstats64; 1864 sc->sc_free_txstats = bwi_free_txstats64; 1865 sc->sc_txeof_status = bwi_txeof_status64; 1866 } 1867 break; 1868 } 1869 1870 KASSERT(lowaddr != 0, ("lowaddr zero")); 1871 KASSERT(desc_sz != 0, ("desc_sz zero")); 1872 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1873 1874 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1875 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1876 1877 /* 1878 * Create top level DMA tag 1879 */ 1880 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1881 BWI_ALIGN, 0, /* alignment, bounds */ 1882 lowaddr, /* lowaddr */ 1883 BUS_SPACE_MAXADDR, /* highaddr */ 1884 NULL, NULL, /* filter, filterarg */ 1885 BUS_SPACE_MAXSIZE, /* maxsize */ 1886 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1887 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1888 0, /* flags */ 1889 NULL, NULL, /* lockfunc, lockarg */ 1890 &sc->sc_parent_dtag); 1891 if (error) { 1892 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1893 return error; 1894 } 1895 1896 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1897 1898 /* 1899 * Create TX ring DMA stuffs 1900 */ 1901 error = bus_dma_tag_create(sc->sc_parent_dtag, 1902 BWI_RING_ALIGN, 0, 1903 BUS_SPACE_MAXADDR, 1904 BUS_SPACE_MAXADDR, 1905 NULL, NULL, 1906 tx_ring_sz, 1907 1, 1908 tx_ring_sz, 1909 0, 1910 NULL, NULL, 1911 &sc->sc_txring_dtag); 1912 if (error) { 1913 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1914 return error; 1915 } 1916 1917 for (i = 0; i < BWI_TX_NRING; ++i) { 1918 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1919 &sc->sc_tx_rdata[i], tx_ring_sz, 1920 TXRX_CTRL(i)); 1921 if (error) { 1922 device_printf(sc->sc_dev, "%dth TX ring " 1923 "DMA alloc failed\n", i); 1924 return error; 1925 } 1926 } 1927 1928 /* 1929 * Create RX ring DMA stuffs 1930 */ 1931 error = bus_dma_tag_create(sc->sc_parent_dtag, 1932 BWI_RING_ALIGN, 0, 1933 BUS_SPACE_MAXADDR, 1934 BUS_SPACE_MAXADDR, 1935 NULL, NULL, 1936 rx_ring_sz, 1937 1, 1938 rx_ring_sz, 1939 0, 1940 NULL, NULL, 1941 &sc->sc_rxring_dtag); 1942 if (error) { 1943 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1944 return error; 1945 } 1946 1947 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1948 rx_ring_sz, TXRX_CTRL(0)); 1949 if (error) { 1950 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1951 return error; 1952 } 1953 1954 if (has_txstats) { 1955 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1956 if (error) { 1957 device_printf(sc->sc_dev, 1958 "TX stats DMA alloc failed\n"); 1959 return error; 1960 } 1961 } 1962 1963 #undef TXRX_CTRL 1964 1965 return bwi_dma_mbuf_create(sc); 1966 } 1967 1968 static void 1969 bwi_dma_free(struct bwi_softc *sc) 1970 { 1971 if (sc->sc_txring_dtag != NULL) { 1972 int i; 1973 1974 for (i = 0; i < BWI_TX_NRING; ++i) { 1975 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 1976 1977 if (rd->rdata_desc != NULL) { 1978 bus_dmamap_unload(sc->sc_txring_dtag, 1979 rd->rdata_dmap); 1980 bus_dmamem_free(sc->sc_txring_dtag, 1981 rd->rdata_desc, 1982 rd->rdata_dmap); 1983 } 1984 } 1985 bus_dma_tag_destroy(sc->sc_txring_dtag); 1986 } 1987 1988 if (sc->sc_rxring_dtag != NULL) { 1989 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 1990 1991 if (rd->rdata_desc != NULL) { 1992 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 1993 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 1994 rd->rdata_dmap); 1995 } 1996 bus_dma_tag_destroy(sc->sc_rxring_dtag); 1997 } 1998 1999 bwi_dma_txstats_free(sc); 2000 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 2001 2002 if (sc->sc_parent_dtag != NULL) 2003 bus_dma_tag_destroy(sc->sc_parent_dtag); 2004 } 2005 2006 static int 2007 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2008 struct bwi_ring_data *rd, bus_size_t size, 2009 uint32_t txrx_ctrl) 2010 { 2011 int error; 2012 2013 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2014 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2015 &rd->rdata_dmap); 2016 if (error) { 2017 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2018 return error; 2019 } 2020 2021 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2022 bwi_dma_ring_addr, &rd->rdata_paddr, 2023 BUS_DMA_NOWAIT); 2024 if (error) { 2025 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2026 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2027 rd->rdata_desc = NULL; 2028 return error; 2029 } 2030 2031 rd->rdata_txrx_ctrl = txrx_ctrl; 2032 return 0; 2033 } 2034 2035 static int 2036 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2037 bus_size_t desc_sz) 2038 { 2039 struct bwi_txstats_data *st; 2040 bus_size_t dma_size; 2041 int error; 2042 2043 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2044 if (st == NULL) { 2045 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2046 return ENOMEM; 2047 } 2048 sc->sc_txstats = st; 2049 2050 /* 2051 * Create TX stats descriptor DMA stuffs 2052 */ 2053 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2054 2055 error = bus_dma_tag_create(sc->sc_parent_dtag, 2056 BWI_RING_ALIGN, 2057 0, 2058 BUS_SPACE_MAXADDR, 2059 BUS_SPACE_MAXADDR, 2060 NULL, NULL, 2061 dma_size, 2062 1, 2063 dma_size, 2064 0, 2065 NULL, NULL, 2066 &st->stats_ring_dtag); 2067 if (error) { 2068 device_printf(sc->sc_dev, "can't create txstats ring " 2069 "DMA tag\n"); 2070 return error; 2071 } 2072 2073 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2074 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2075 &st->stats_ring_dmap); 2076 if (error) { 2077 device_printf(sc->sc_dev, "can't allocate txstats ring " 2078 "DMA mem\n"); 2079 bus_dma_tag_destroy(st->stats_ring_dtag); 2080 st->stats_ring_dtag = NULL; 2081 return error; 2082 } 2083 2084 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2085 st->stats_ring, dma_size, 2086 bwi_dma_ring_addr, &st->stats_ring_paddr, 2087 BUS_DMA_NOWAIT); 2088 if (error) { 2089 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2090 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2091 st->stats_ring_dmap); 2092 bus_dma_tag_destroy(st->stats_ring_dtag); 2093 st->stats_ring_dtag = NULL; 2094 return error; 2095 } 2096 2097 /* 2098 * Create TX stats DMA stuffs 2099 */ 2100 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2101 BWI_ALIGN); 2102 2103 error = bus_dma_tag_create(sc->sc_parent_dtag, 2104 BWI_ALIGN, 2105 0, 2106 BUS_SPACE_MAXADDR, 2107 BUS_SPACE_MAXADDR, 2108 NULL, NULL, 2109 dma_size, 2110 1, 2111 dma_size, 2112 0, 2113 NULL, NULL, 2114 &st->stats_dtag); 2115 if (error) { 2116 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2117 return error; 2118 } 2119 2120 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2121 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2122 &st->stats_dmap); 2123 if (error) { 2124 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2125 bus_dma_tag_destroy(st->stats_dtag); 2126 st->stats_dtag = NULL; 2127 return error; 2128 } 2129 2130 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2131 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2132 BUS_DMA_NOWAIT); 2133 if (error) { 2134 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2135 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2136 bus_dma_tag_destroy(st->stats_dtag); 2137 st->stats_dtag = NULL; 2138 return error; 2139 } 2140 2141 st->stats_ctrl_base = ctrl_base; 2142 return 0; 2143 } 2144 2145 static void 2146 bwi_dma_txstats_free(struct bwi_softc *sc) 2147 { 2148 struct bwi_txstats_data *st; 2149 2150 if (sc->sc_txstats == NULL) 2151 return; 2152 st = sc->sc_txstats; 2153 2154 if (st->stats_ring_dtag != NULL) { 2155 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2156 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2157 st->stats_ring_dmap); 2158 bus_dma_tag_destroy(st->stats_ring_dtag); 2159 } 2160 2161 if (st->stats_dtag != NULL) { 2162 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2163 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2164 bus_dma_tag_destroy(st->stats_dtag); 2165 } 2166 2167 free(st, M_DEVBUF); 2168 } 2169 2170 static void 2171 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2172 { 2173 KASSERT(nseg == 1, ("too many segments\n")); 2174 *((bus_addr_t *)arg) = seg->ds_addr; 2175 } 2176 2177 static int 2178 bwi_dma_mbuf_create(struct bwi_softc *sc) 2179 { 2180 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2181 int i, j, k, ntx, error; 2182 2183 /* 2184 * Create TX/RX mbuf DMA tag 2185 */ 2186 error = bus_dma_tag_create(sc->sc_parent_dtag, 2187 1, 2188 0, 2189 BUS_SPACE_MAXADDR, 2190 BUS_SPACE_MAXADDR, 2191 NULL, NULL, 2192 MCLBYTES, 2193 1, 2194 MCLBYTES, 2195 BUS_DMA_ALLOCNOW, 2196 NULL, NULL, 2197 &sc->sc_buf_dtag); 2198 if (error) { 2199 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2200 return error; 2201 } 2202 2203 ntx = 0; 2204 2205 /* 2206 * Create TX mbuf DMA map 2207 */ 2208 for (i = 0; i < BWI_TX_NRING; ++i) { 2209 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2210 2211 for (j = 0; j < BWI_TX_NDESC; ++j) { 2212 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2213 &tbd->tbd_buf[j].tb_dmap); 2214 if (error) { 2215 device_printf(sc->sc_dev, "can't create " 2216 "%dth tbd, %dth DMA map\n", i, j); 2217 2218 ntx = i; 2219 for (k = 0; k < j; ++k) { 2220 bus_dmamap_destroy(sc->sc_buf_dtag, 2221 tbd->tbd_buf[k].tb_dmap); 2222 } 2223 goto fail; 2224 } 2225 } 2226 } 2227 ntx = BWI_TX_NRING; 2228 2229 /* 2230 * Create RX mbuf DMA map and a spare DMA map 2231 */ 2232 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2233 &rbd->rbd_tmp_dmap); 2234 if (error) { 2235 device_printf(sc->sc_dev, 2236 "can't create spare RX buf DMA map\n"); 2237 goto fail; 2238 } 2239 2240 for (j = 0; j < BWI_RX_NDESC; ++j) { 2241 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2242 &rbd->rbd_buf[j].rb_dmap); 2243 if (error) { 2244 device_printf(sc->sc_dev, "can't create %dth " 2245 "RX buf DMA map\n", j); 2246 2247 for (k = 0; k < j; ++k) { 2248 bus_dmamap_destroy(sc->sc_buf_dtag, 2249 rbd->rbd_buf[j].rb_dmap); 2250 } 2251 bus_dmamap_destroy(sc->sc_buf_dtag, 2252 rbd->rbd_tmp_dmap); 2253 goto fail; 2254 } 2255 } 2256 2257 return 0; 2258 fail: 2259 bwi_dma_mbuf_destroy(sc, ntx, 0); 2260 return error; 2261 } 2262 2263 static void 2264 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2265 { 2266 int i, j; 2267 2268 if (sc->sc_buf_dtag == NULL) 2269 return; 2270 2271 for (i = 0; i < ntx; ++i) { 2272 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2273 2274 for (j = 0; j < BWI_TX_NDESC; ++j) { 2275 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2276 2277 if (tb->tb_mbuf != NULL) { 2278 bus_dmamap_unload(sc->sc_buf_dtag, 2279 tb->tb_dmap); 2280 m_freem(tb->tb_mbuf); 2281 } 2282 if (tb->tb_ni != NULL) 2283 ieee80211_free_node(tb->tb_ni); 2284 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2285 } 2286 } 2287 2288 if (nrx) { 2289 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2290 2291 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2292 for (j = 0; j < BWI_RX_NDESC; ++j) { 2293 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2294 2295 if (rb->rb_mbuf != NULL) { 2296 bus_dmamap_unload(sc->sc_buf_dtag, 2297 rb->rb_dmap); 2298 m_freem(rb->rb_mbuf); 2299 } 2300 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2301 } 2302 } 2303 2304 bus_dma_tag_destroy(sc->sc_buf_dtag); 2305 sc->sc_buf_dtag = NULL; 2306 } 2307 2308 static void 2309 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2310 { 2311 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2312 } 2313 2314 static void 2315 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2316 { 2317 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2318 } 2319 2320 static int 2321 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2322 { 2323 struct bwi_ring_data *rd; 2324 struct bwi_txbuf_data *tbd; 2325 uint32_t val, addr_hi, addr_lo; 2326 2327 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2328 rd = &sc->sc_tx_rdata[ring_idx]; 2329 tbd = &sc->sc_tx_bdata[ring_idx]; 2330 2331 tbd->tbd_idx = 0; 2332 tbd->tbd_used = 0; 2333 2334 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2335 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2336 BUS_DMASYNC_PREWRITE); 2337 2338 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2339 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2340 2341 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2342 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2343 BWI_TXRX32_RINGINFO_FUNC_MASK); 2344 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2345 2346 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2347 BWI_TXRX32_CTRL_ENABLE; 2348 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2349 2350 return 0; 2351 } 2352 2353 static void 2354 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2355 bus_addr_t paddr, int hdr_size, int ndesc) 2356 { 2357 uint32_t val, addr_hi, addr_lo; 2358 2359 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2360 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2361 2362 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2363 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2364 BWI_TXRX32_RINGINFO_FUNC_MASK); 2365 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2366 2367 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2368 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2369 BWI_TXRX32_CTRL_ENABLE; 2370 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2371 2372 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2373 (ndesc - 1) * sizeof(struct bwi_desc32)); 2374 } 2375 2376 static int 2377 bwi_init_rx_ring32(struct bwi_softc *sc) 2378 { 2379 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2380 int i, error; 2381 2382 sc->sc_rx_bdata.rbd_idx = 0; 2383 2384 for (i = 0; i < BWI_RX_NDESC; ++i) { 2385 error = bwi_newbuf(sc, i, 1); 2386 if (error) { 2387 device_printf(sc->sc_dev, 2388 "can't allocate %dth RX buffer\n", i); 2389 return error; 2390 } 2391 } 2392 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2393 BUS_DMASYNC_PREWRITE); 2394 2395 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2396 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2397 return 0; 2398 } 2399 2400 static int 2401 bwi_init_txstats32(struct bwi_softc *sc) 2402 { 2403 struct bwi_txstats_data *st = sc->sc_txstats; 2404 bus_addr_t stats_paddr; 2405 int i; 2406 2407 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2408 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2409 2410 st->stats_idx = 0; 2411 2412 stats_paddr = st->stats_paddr; 2413 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2414 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2415 stats_paddr, sizeof(struct bwi_txstats), 0); 2416 stats_paddr += sizeof(struct bwi_txstats); 2417 } 2418 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2419 BUS_DMASYNC_PREWRITE); 2420 2421 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2422 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2423 return 0; 2424 } 2425 2426 static void 2427 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2428 int buf_len) 2429 { 2430 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2431 2432 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2433 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2434 paddr, buf_len, 0); 2435 } 2436 2437 static void 2438 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2439 int buf_idx, bus_addr_t paddr, int buf_len) 2440 { 2441 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2442 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2443 paddr, buf_len, 1); 2444 } 2445 2446 static int 2447 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2448 { 2449 /* TODO:64 */ 2450 return EOPNOTSUPP; 2451 } 2452 2453 static int 2454 bwi_init_rx_ring64(struct bwi_softc *sc) 2455 { 2456 /* TODO:64 */ 2457 return EOPNOTSUPP; 2458 } 2459 2460 static int 2461 bwi_init_txstats64(struct bwi_softc *sc) 2462 { 2463 /* TODO:64 */ 2464 return EOPNOTSUPP; 2465 } 2466 2467 static void 2468 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2469 int buf_len) 2470 { 2471 /* TODO:64 */ 2472 } 2473 2474 static void 2475 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2476 int buf_idx, bus_addr_t paddr, int buf_len) 2477 { 2478 /* TODO:64 */ 2479 } 2480 2481 static void 2482 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2483 bus_size_t mapsz __unused, int error) 2484 { 2485 if (!error) { 2486 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2487 *((bus_addr_t *)arg) = seg->ds_addr; 2488 } 2489 } 2490 2491 static int 2492 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2493 { 2494 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2495 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2496 struct bwi_rxbuf_hdr *hdr; 2497 bus_dmamap_t map; 2498 bus_addr_t paddr; 2499 struct mbuf *m; 2500 int error; 2501 2502 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2503 2504 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2505 if (m == NULL) { 2506 error = ENOBUFS; 2507 2508 /* 2509 * If the NIC is up and running, we need to: 2510 * - Clear RX buffer's header. 2511 * - Restore RX descriptor settings. 2512 */ 2513 if (init) 2514 return error; 2515 else 2516 goto back; 2517 } 2518 m->m_len = m->m_pkthdr.len = MCLBYTES; 2519 2520 /* 2521 * Try to load RX buf into temporary DMA map 2522 */ 2523 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2524 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2525 if (error) { 2526 m_freem(m); 2527 2528 /* 2529 * See the comment above 2530 */ 2531 if (init) 2532 return error; 2533 else 2534 goto back; 2535 } 2536 2537 if (!init) 2538 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2539 rxbuf->rb_mbuf = m; 2540 rxbuf->rb_paddr = paddr; 2541 2542 /* 2543 * Swap RX buf's DMA map with the loaded temporary one 2544 */ 2545 map = rxbuf->rb_dmap; 2546 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2547 rbd->rbd_tmp_dmap = map; 2548 2549 back: 2550 /* 2551 * Clear RX buf header 2552 */ 2553 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2554 bzero(hdr, sizeof(*hdr)); 2555 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2556 2557 /* 2558 * Setup RX buf descriptor 2559 */ 2560 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2561 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2562 return error; 2563 } 2564 2565 static void 2566 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2567 const uint8_t *addr) 2568 { 2569 int i; 2570 2571 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2572 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2573 2574 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2575 uint16_t addr_val; 2576 2577 addr_val = (uint16_t)addr[i * 2] | 2578 (((uint16_t)addr[(i * 2) + 1]) << 8); 2579 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2580 } 2581 } 2582 2583 static int 2584 bwi_rxeof(struct bwi_softc *sc, int end_idx) 2585 { 2586 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2587 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2588 struct ieee80211com *ic = &sc->sc_ic; 2589 int idx, rx_data = 0; 2590 2591 idx = rbd->rbd_idx; 2592 while (idx != end_idx) { 2593 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2594 struct bwi_rxbuf_hdr *hdr; 2595 struct ieee80211_frame_min *wh; 2596 struct ieee80211_node *ni; 2597 struct mbuf *m; 2598 uint32_t plcp; 2599 uint16_t flags2; 2600 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2601 2602 m = rb->rb_mbuf; 2603 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2604 BUS_DMASYNC_POSTREAD); 2605 2606 if (bwi_newbuf(sc, idx, 0)) { 2607 counter_u64_add(ic->ic_ierrors, 1); 2608 goto next; 2609 } 2610 2611 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2612 flags2 = le16toh(hdr->rxh_flags2); 2613 2614 hdr_extra = 0; 2615 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2616 hdr_extra = 2; 2617 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2618 2619 buflen = le16toh(hdr->rxh_buflen); 2620 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2621 device_printf(sc->sc_dev, 2622 "%s: zero length data, hdr_extra %d\n", 2623 __func__, hdr_extra); 2624 counter_u64_add(ic->ic_ierrors, 1); 2625 m_freem(m); 2626 goto next; 2627 } 2628 2629 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp)); 2630 rssi = bwi_calc_rssi(sc, hdr); 2631 noise = bwi_calc_noise(sc); 2632 2633 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2634 m_adj(m, sizeof(*hdr) + wh_ofs); 2635 2636 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2637 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM); 2638 else 2639 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK); 2640 2641 /* RX radio tap */ 2642 if (ieee80211_radiotap_active(ic)) 2643 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise); 2644 2645 m_adj(m, -IEEE80211_CRC_LEN); 2646 2647 BWI_UNLOCK(sc); 2648 2649 wh = mtod(m, struct ieee80211_frame_min *); 2650 ni = ieee80211_find_rxnode(ic, wh); 2651 if (ni != NULL) { 2652 type = ieee80211_input(ni, m, rssi - noise, noise); 2653 ieee80211_free_node(ni); 2654 } else 2655 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2656 if (type == IEEE80211_FC0_TYPE_DATA) { 2657 rx_data = 1; 2658 sc->sc_rx_rate = rate; 2659 } 2660 2661 BWI_LOCK(sc); 2662 next: 2663 idx = (idx + 1) % BWI_RX_NDESC; 2664 2665 if (sc->sc_flags & BWI_F_STOP) { 2666 /* 2667 * Take the fast lane, don't do 2668 * any damage to softc 2669 */ 2670 return -1; 2671 } 2672 } 2673 2674 rbd->rbd_idx = idx; 2675 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2676 BUS_DMASYNC_PREWRITE); 2677 2678 return rx_data; 2679 } 2680 2681 static int 2682 bwi_rxeof32(struct bwi_softc *sc) 2683 { 2684 uint32_t val, rx_ctrl; 2685 int end_idx, rx_data; 2686 2687 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2688 2689 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2690 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2691 sizeof(struct bwi_desc32); 2692 2693 rx_data = bwi_rxeof(sc, end_idx); 2694 if (rx_data >= 0) { 2695 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2696 end_idx * sizeof(struct bwi_desc32)); 2697 } 2698 return rx_data; 2699 } 2700 2701 static int 2702 bwi_rxeof64(struct bwi_softc *sc) 2703 { 2704 /* TODO:64 */ 2705 return 0; 2706 } 2707 2708 static void 2709 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2710 { 2711 int i; 2712 2713 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2714 2715 #define NRETRY 10 2716 2717 for (i = 0; i < NRETRY; ++i) { 2718 uint32_t status; 2719 2720 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2721 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2722 BWI_RX32_STATUS_STATE_DISABLED) 2723 break; 2724 2725 DELAY(1000); 2726 } 2727 if (i == NRETRY) 2728 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2729 2730 #undef NRETRY 2731 2732 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2733 } 2734 2735 static void 2736 bwi_free_txstats32(struct bwi_softc *sc) 2737 { 2738 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2739 } 2740 2741 static void 2742 bwi_free_rx_ring32(struct bwi_softc *sc) 2743 { 2744 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2745 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2746 int i; 2747 2748 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2749 2750 for (i = 0; i < BWI_RX_NDESC; ++i) { 2751 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2752 2753 if (rb->rb_mbuf != NULL) { 2754 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2755 m_freem(rb->rb_mbuf); 2756 rb->rb_mbuf = NULL; 2757 } 2758 } 2759 } 2760 2761 static void 2762 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2763 { 2764 struct bwi_ring_data *rd; 2765 struct bwi_txbuf_data *tbd; 2766 uint32_t state, val; 2767 int i; 2768 2769 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2770 rd = &sc->sc_tx_rdata[ring_idx]; 2771 tbd = &sc->sc_tx_bdata[ring_idx]; 2772 2773 #define NRETRY 10 2774 2775 for (i = 0; i < NRETRY; ++i) { 2776 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2777 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2778 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2779 state == BWI_TX32_STATUS_STATE_IDLE || 2780 state == BWI_TX32_STATUS_STATE_STOPPED) 2781 break; 2782 2783 DELAY(1000); 2784 } 2785 if (i == NRETRY) { 2786 device_printf(sc->sc_dev, 2787 "%s: wait for TX ring(%d) stable timed out\n", 2788 __func__, ring_idx); 2789 } 2790 2791 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2792 for (i = 0; i < NRETRY; ++i) { 2793 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2794 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2795 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2796 break; 2797 2798 DELAY(1000); 2799 } 2800 if (i == NRETRY) 2801 device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n", 2802 __func__, ring_idx); 2803 2804 #undef NRETRY 2805 2806 DELAY(1000); 2807 2808 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2809 2810 for (i = 0; i < BWI_TX_NDESC; ++i) { 2811 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2812 2813 if (tb->tb_mbuf != NULL) { 2814 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2815 m_freem(tb->tb_mbuf); 2816 tb->tb_mbuf = NULL; 2817 } 2818 if (tb->tb_ni != NULL) { 2819 ieee80211_free_node(tb->tb_ni); 2820 tb->tb_ni = NULL; 2821 } 2822 } 2823 } 2824 2825 static void 2826 bwi_free_txstats64(struct bwi_softc *sc) 2827 { 2828 /* TODO:64 */ 2829 } 2830 2831 static void 2832 bwi_free_rx_ring64(struct bwi_softc *sc) 2833 { 2834 /* TODO:64 */ 2835 } 2836 2837 static void 2838 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2839 { 2840 /* TODO:64 */ 2841 } 2842 2843 /* XXX does not belong here */ 2844 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2845 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2846 2847 static __inline void 2848 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2849 { 2850 uint32_t plcp; 2851 2852 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2853 IEEE80211_OFDM_PLCP_RATE_MASK) | 2854 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2855 *plcp0 = htole32(plcp); 2856 } 2857 2858 static __inline void 2859 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2860 uint8_t rate) 2861 { 2862 int len, service, pkt_bitlen; 2863 2864 pkt_bitlen = pkt_len * NBBY; 2865 len = howmany(pkt_bitlen * 2, rate); 2866 2867 service = IEEE80211_PLCP_SERVICE_LOCKED; 2868 if (rate == (11 * 2)) { 2869 int pkt_bitlen1; 2870 2871 /* 2872 * PLCP service field needs to be adjusted, 2873 * if TX rate is 11Mbytes/s 2874 */ 2875 pkt_bitlen1 = len * 11; 2876 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2877 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2878 } 2879 2880 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2881 plcp->i_service = service; 2882 plcp->i_length = htole16(len); 2883 /* NOTE: do NOT touch i_crc */ 2884 } 2885 2886 static __inline void 2887 bwi_plcp_header(const struct ieee80211_rate_table *rt, 2888 void *plcp, int pkt_len, uint8_t rate) 2889 { 2890 enum ieee80211_phytype modtype; 2891 2892 /* 2893 * Assume caller has zeroed 'plcp' 2894 */ 2895 modtype = ieee80211_rate2phytype(rt, rate); 2896 if (modtype == IEEE80211_T_OFDM) 2897 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2898 else if (modtype == IEEE80211_T_DS) 2899 bwi_ds_plcp_header(plcp, pkt_len, rate); 2900 else 2901 panic("unsupport modulation type %u\n", modtype); 2902 } 2903 2904 static int 2905 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2906 struct ieee80211_node *ni) 2907 { 2908 struct ieee80211vap *vap = ni->ni_vap; 2909 struct ieee80211com *ic = &sc->sc_ic; 2910 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2911 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2912 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2913 struct bwi_mac *mac; 2914 struct bwi_txbuf_hdr *hdr; 2915 struct ieee80211_frame *wh; 2916 const struct ieee80211_txparam *tp = ni->ni_txparms; 2917 uint8_t rate, rate_fb; 2918 uint32_t mac_ctrl; 2919 uint16_t phy_ctrl; 2920 bus_addr_t paddr; 2921 int type, ismcast, pkt_len, error, rix; 2922 #if 0 2923 const uint8_t *p; 2924 int i; 2925 #endif 2926 2927 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2928 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2929 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2930 2931 wh = mtod(m, struct ieee80211_frame *); 2932 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2933 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2934 2935 /* Get 802.11 frame len before prepending TX header */ 2936 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2937 2938 /* 2939 * Find TX rate 2940 */ 2941 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2942 rate = rate_fb = tp->mgmtrate; 2943 } else if (ismcast) { 2944 rate = rate_fb = tp->mcastrate; 2945 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2946 rate = rate_fb = tp->ucastrate; 2947 } else { 2948 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len); 2949 rate = ni->ni_txrate; 2950 2951 if (rix > 0) { 2952 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2953 IEEE80211_RATE_VAL; 2954 } else { 2955 rate_fb = rate; 2956 } 2957 } 2958 tb->tb_rate[0] = rate; 2959 tb->tb_rate[1] = rate_fb; 2960 sc->sc_tx_rate = rate; 2961 2962 /* 2963 * TX radio tap 2964 */ 2965 if (ieee80211_radiotap_active_vap(vap)) { 2966 sc->sc_tx_th.wt_flags = 0; 2967 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 2968 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2969 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 2970 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2971 rate != (1 * 2)) { 2972 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2973 } 2974 sc->sc_tx_th.wt_rate = rate; 2975 2976 ieee80211_radiotap_tx(vap, m); 2977 } 2978 2979 /* 2980 * Setup the embedded TX header 2981 */ 2982 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 2983 if (m == NULL) { 2984 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 2985 __func__); 2986 return ENOBUFS; 2987 } 2988 hdr = mtod(m, struct bwi_txbuf_hdr *); 2989 2990 bzero(hdr, sizeof(*hdr)); 2991 2992 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 2993 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 2994 2995 if (!ismcast) { 2996 uint16_t dur; 2997 2998 dur = ieee80211_ack_duration(sc->sc_rates, rate, 2999 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 3000 3001 hdr->txh_fb_duration = htole16(dur); 3002 } 3003 3004 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3005 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3006 3007 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3008 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3009 3010 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3011 BWI_TXH_PHY_C_ANTMODE_MASK); 3012 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3013 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3014 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3015 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3016 3017 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3018 if (!ismcast) 3019 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3020 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3021 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3022 3023 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3024 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3025 3026 /* Catch any further usage */ 3027 hdr = NULL; 3028 wh = NULL; 3029 3030 /* DMA load */ 3031 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3032 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3033 if (error && error != EFBIG) { 3034 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 3035 __func__, error); 3036 goto back; 3037 } 3038 3039 if (error) { /* error == EFBIG */ 3040 struct mbuf *m_new; 3041 3042 m_new = m_defrag(m, M_NOWAIT); 3043 if (m_new == NULL) { 3044 device_printf(sc->sc_dev, 3045 "%s: can't defrag TX buffer\n", __func__); 3046 error = ENOBUFS; 3047 goto back; 3048 } else { 3049 m = m_new; 3050 } 3051 3052 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3053 bwi_dma_buf_addr, &paddr, 3054 BUS_DMA_NOWAIT); 3055 if (error) { 3056 device_printf(sc->sc_dev, 3057 "%s: can't load TX buffer (2) %d\n", 3058 __func__, error); 3059 goto back; 3060 } 3061 } 3062 error = 0; 3063 3064 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3065 3066 tb->tb_mbuf = m; 3067 tb->tb_ni = ni; 3068 3069 #if 0 3070 p = mtod(m, const uint8_t *); 3071 for (i = 0; i < m->m_pkthdr.len; ++i) { 3072 if (i != 0 && i % 8 == 0) 3073 printf("\n"); 3074 printf("%02x ", p[i]); 3075 } 3076 printf("\n"); 3077 #endif 3078 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3079 idx, pkt_len, m->m_pkthdr.len); 3080 3081 /* Setup TX descriptor */ 3082 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3083 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3084 BUS_DMASYNC_PREWRITE); 3085 3086 /* Kick start */ 3087 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3088 3089 back: 3090 if (error) 3091 m_freem(m); 3092 return error; 3093 } 3094 3095 static int 3096 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3097 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3098 { 3099 struct ieee80211vap *vap = ni->ni_vap; 3100 struct ieee80211com *ic = ni->ni_ic; 3101 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3102 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3103 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3104 struct bwi_mac *mac; 3105 struct bwi_txbuf_hdr *hdr; 3106 struct ieee80211_frame *wh; 3107 uint8_t rate, rate_fb; 3108 uint32_t mac_ctrl; 3109 uint16_t phy_ctrl; 3110 bus_addr_t paddr; 3111 int ismcast, pkt_len, error; 3112 3113 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3114 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3115 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3116 3117 wh = mtod(m, struct ieee80211_frame *); 3118 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3119 3120 /* Get 802.11 frame len before prepending TX header */ 3121 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3122 3123 /* 3124 * Find TX rate 3125 */ 3126 rate = params->ibp_rate0; 3127 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3128 /* XXX fall back to mcast/mgmt rate? */ 3129 m_freem(m); 3130 return EINVAL; 3131 } 3132 if (params->ibp_try1 != 0) { 3133 rate_fb = params->ibp_rate1; 3134 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3135 /* XXX fall back to rate0? */ 3136 m_freem(m); 3137 return EINVAL; 3138 } 3139 } else 3140 rate_fb = rate; 3141 tb->tb_rate[0] = rate; 3142 tb->tb_rate[1] = rate_fb; 3143 sc->sc_tx_rate = rate; 3144 3145 /* 3146 * TX radio tap 3147 */ 3148 if (ieee80211_radiotap_active_vap(vap)) { 3149 sc->sc_tx_th.wt_flags = 0; 3150 /* XXX IEEE80211_BPF_CRYPTO */ 3151 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3152 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3153 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3154 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3155 sc->sc_tx_th.wt_rate = rate; 3156 3157 ieee80211_radiotap_tx(vap, m); 3158 } 3159 3160 /* 3161 * Setup the embedded TX header 3162 */ 3163 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3164 if (m == NULL) { 3165 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 3166 __func__); 3167 return ENOBUFS; 3168 } 3169 hdr = mtod(m, struct bwi_txbuf_hdr *); 3170 3171 bzero(hdr, sizeof(*hdr)); 3172 3173 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3174 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3175 3176 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3177 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3178 uint16_t dur; 3179 3180 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3181 3182 hdr->txh_fb_duration = htole16(dur); 3183 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3184 } 3185 3186 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3187 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3188 3189 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3190 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3191 3192 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3193 BWI_TXH_PHY_C_ANTMODE_MASK); 3194 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3195 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3196 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3197 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3198 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3199 3200 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3201 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3202 3203 /* Catch any further usage */ 3204 hdr = NULL; 3205 wh = NULL; 3206 3207 /* DMA load */ 3208 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3209 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3210 if (error != 0) { 3211 struct mbuf *m_new; 3212 3213 if (error != EFBIG) { 3214 device_printf(sc->sc_dev, 3215 "%s: can't load TX buffer (1) %d\n", 3216 __func__, error); 3217 goto back; 3218 } 3219 m_new = m_defrag(m, M_NOWAIT); 3220 if (m_new == NULL) { 3221 device_printf(sc->sc_dev, 3222 "%s: can't defrag TX buffer\n", __func__); 3223 error = ENOBUFS; 3224 goto back; 3225 } 3226 m = m_new; 3227 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3228 bwi_dma_buf_addr, &paddr, 3229 BUS_DMA_NOWAIT); 3230 if (error) { 3231 device_printf(sc->sc_dev, 3232 "%s: can't load TX buffer (2) %d\n", 3233 __func__, error); 3234 goto back; 3235 } 3236 } 3237 3238 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3239 3240 tb->tb_mbuf = m; 3241 tb->tb_ni = ni; 3242 3243 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3244 idx, pkt_len, m->m_pkthdr.len); 3245 3246 /* Setup TX descriptor */ 3247 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3248 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3249 BUS_DMASYNC_PREWRITE); 3250 3251 /* Kick start */ 3252 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3253 back: 3254 if (error) 3255 m_freem(m); 3256 return error; 3257 } 3258 3259 static void 3260 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3261 { 3262 idx = (idx + 1) % BWI_TX_NDESC; 3263 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3264 idx * sizeof(struct bwi_desc32)); 3265 } 3266 3267 static void 3268 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3269 { 3270 /* TODO:64 */ 3271 } 3272 3273 static void 3274 bwi_txeof_status32(struct bwi_softc *sc) 3275 { 3276 uint32_t val, ctrl_base; 3277 int end_idx; 3278 3279 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3280 3281 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3282 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3283 sizeof(struct bwi_desc32); 3284 3285 bwi_txeof_status(sc, end_idx); 3286 3287 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3288 end_idx * sizeof(struct bwi_desc32)); 3289 3290 bwi_start_locked(sc); 3291 } 3292 3293 static void 3294 bwi_txeof_status64(struct bwi_softc *sc) 3295 { 3296 /* TODO:64 */ 3297 } 3298 3299 static void 3300 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3301 { 3302 struct bwi_txbuf_data *tbd; 3303 struct bwi_txbuf *tb; 3304 int ring_idx, buf_idx; 3305 struct ieee80211_node *ni; 3306 3307 if (tx_id == 0) { 3308 device_printf(sc->sc_dev, "%s: zero tx id\n", __func__); 3309 return; 3310 } 3311 3312 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3313 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3314 3315 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3316 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3317 3318 tbd = &sc->sc_tx_bdata[ring_idx]; 3319 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3320 tbd->tbd_used--; 3321 3322 tb = &tbd->tbd_buf[buf_idx]; 3323 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3324 "acked %d, data_txcnt %d, ni %p\n", 3325 buf_idx, acked, data_txcnt, tb->tb_ni); 3326 3327 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3328 3329 if ((ni = tb->tb_ni) != NULL) { 3330 const struct bwi_txbuf_hdr *hdr = 3331 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3332 struct ieee80211_ratectl_tx_status txs; 3333 3334 /* NB: update rate control only for unicast frames */ 3335 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3336 /* 3337 * Feed back 'acked and data_txcnt'. Note that the 3338 * generic AMRR code only understands one tx rate 3339 * and the estimator doesn't handle real retry counts 3340 * well so to avoid over-aggressive downshifting we 3341 * treat any number of retries as "1". 3342 */ 3343 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 3344 txs.long_retries = acked; 3345 if (data_txcnt > 1) 3346 txs.status = IEEE80211_RATECTL_TX_SUCCESS; 3347 else { 3348 txs.status = 3349 IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3350 } 3351 ieee80211_ratectl_tx_complete(ni, &txs); 3352 } 3353 ieee80211_tx_complete(ni, tb->tb_mbuf, !acked); 3354 tb->tb_ni = NULL; 3355 } else 3356 m_freem(tb->tb_mbuf); 3357 tb->tb_mbuf = NULL; 3358 3359 if (tbd->tbd_used == 0) 3360 sc->sc_tx_timer = 0; 3361 } 3362 3363 static void 3364 bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3365 { 3366 struct bwi_txstats_data *st = sc->sc_txstats; 3367 int idx; 3368 3369 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3370 3371 idx = st->stats_idx; 3372 while (idx != end_idx) { 3373 const struct bwi_txstats *stats = &st->stats[idx]; 3374 3375 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3376 int data_txcnt; 3377 3378 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3379 BWI_TXS_TXCNT_DATA); 3380 _bwi_txeof(sc, le16toh(stats->txs_id), 3381 stats->txs_flags & BWI_TXS_F_ACKED, 3382 data_txcnt); 3383 } 3384 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3385 } 3386 st->stats_idx = idx; 3387 } 3388 3389 static void 3390 bwi_txeof(struct bwi_softc *sc) 3391 { 3392 3393 for (;;) { 3394 uint32_t tx_status0, tx_status1; 3395 uint16_t tx_id; 3396 int data_txcnt; 3397 3398 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3399 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3400 break; 3401 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3402 3403 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3404 data_txcnt = __SHIFTOUT(tx_status0, 3405 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3406 3407 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3408 continue; 3409 3410 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3411 data_txcnt); 3412 } 3413 3414 bwi_start_locked(sc); 3415 } 3416 3417 static int 3418 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3419 { 3420 bwi_power_on(sc, 1); 3421 return bwi_set_clock_mode(sc, clk_mode); 3422 } 3423 3424 static void 3425 bwi_bbp_power_off(struct bwi_softc *sc) 3426 { 3427 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3428 bwi_power_off(sc, 1); 3429 } 3430 3431 static int 3432 bwi_get_pwron_delay(struct bwi_softc *sc) 3433 { 3434 struct bwi_regwin *com, *old; 3435 struct bwi_clock_freq freq; 3436 uint32_t val; 3437 int error; 3438 3439 com = &sc->sc_com_regwin; 3440 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3441 3442 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3443 return 0; 3444 3445 error = bwi_regwin_switch(sc, com, &old); 3446 if (error) 3447 return error; 3448 3449 bwi_get_clock_freq(sc, &freq); 3450 3451 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3452 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3453 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3454 3455 return bwi_regwin_switch(sc, old, NULL); 3456 } 3457 3458 static int 3459 bwi_bus_attach(struct bwi_softc *sc) 3460 { 3461 struct bwi_regwin *bus, *old; 3462 int error; 3463 3464 bus = &sc->sc_bus_regwin; 3465 3466 error = bwi_regwin_switch(sc, bus, &old); 3467 if (error) 3468 return error; 3469 3470 if (!bwi_regwin_is_enabled(sc, bus)) 3471 bwi_regwin_enable(sc, bus, 0); 3472 3473 /* Disable interripts */ 3474 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3475 3476 return bwi_regwin_switch(sc, old, NULL); 3477 } 3478 3479 static const char * 3480 bwi_regwin_name(const struct bwi_regwin *rw) 3481 { 3482 switch (rw->rw_type) { 3483 case BWI_REGWIN_T_COM: 3484 return "COM"; 3485 case BWI_REGWIN_T_BUSPCI: 3486 return "PCI"; 3487 case BWI_REGWIN_T_MAC: 3488 return "MAC"; 3489 case BWI_REGWIN_T_BUSPCIE: 3490 return "PCIE"; 3491 } 3492 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3493 return NULL; 3494 } 3495 3496 static uint32_t 3497 bwi_regwin_disable_bits(struct bwi_softc *sc) 3498 { 3499 uint32_t busrev; 3500 3501 /* XXX cache this */ 3502 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3503 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3504 "bus rev %u\n", busrev); 3505 3506 if (busrev == BWI_BUSREV_0) 3507 return BWI_STATE_LO_DISABLE1; 3508 else if (busrev == BWI_BUSREV_1) 3509 return BWI_STATE_LO_DISABLE2; 3510 else 3511 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3512 } 3513 3514 int 3515 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3516 { 3517 uint32_t val, disable_bits; 3518 3519 disable_bits = bwi_regwin_disable_bits(sc); 3520 val = CSR_READ_4(sc, BWI_STATE_LO); 3521 3522 if ((val & (BWI_STATE_LO_CLOCK | 3523 BWI_STATE_LO_RESET | 3524 disable_bits)) == BWI_STATE_LO_CLOCK) { 3525 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3526 bwi_regwin_name(rw)); 3527 return 1; 3528 } else { 3529 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3530 bwi_regwin_name(rw)); 3531 return 0; 3532 } 3533 } 3534 3535 void 3536 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3537 { 3538 uint32_t state_lo, disable_bits; 3539 int i; 3540 3541 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3542 3543 /* 3544 * If current regwin is in 'reset' state, it was already disabled. 3545 */ 3546 if (state_lo & BWI_STATE_LO_RESET) { 3547 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3548 "%s was already disabled\n", bwi_regwin_name(rw)); 3549 return; 3550 } 3551 3552 disable_bits = bwi_regwin_disable_bits(sc); 3553 3554 /* 3555 * Disable normal clock 3556 */ 3557 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3558 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3559 3560 /* 3561 * Wait until normal clock is disabled 3562 */ 3563 #define NRETRY 1000 3564 for (i = 0; i < NRETRY; ++i) { 3565 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3566 if (state_lo & disable_bits) 3567 break; 3568 DELAY(10); 3569 } 3570 if (i == NRETRY) { 3571 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3572 bwi_regwin_name(rw)); 3573 } 3574 3575 for (i = 0; i < NRETRY; ++i) { 3576 uint32_t state_hi; 3577 3578 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3579 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3580 break; 3581 DELAY(10); 3582 } 3583 if (i == NRETRY) { 3584 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3585 bwi_regwin_name(rw)); 3586 } 3587 #undef NRETRY 3588 3589 /* 3590 * Reset and disable regwin with gated clock 3591 */ 3592 state_lo = BWI_STATE_LO_RESET | disable_bits | 3593 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3594 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3595 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3596 3597 /* Flush pending bus write */ 3598 CSR_READ_4(sc, BWI_STATE_LO); 3599 DELAY(1); 3600 3601 /* Reset and disable regwin */ 3602 state_lo = BWI_STATE_LO_RESET | disable_bits | 3603 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3604 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3605 3606 /* Flush pending bus write */ 3607 CSR_READ_4(sc, BWI_STATE_LO); 3608 DELAY(1); 3609 } 3610 3611 void 3612 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3613 { 3614 uint32_t state_lo, state_hi, imstate; 3615 3616 bwi_regwin_disable(sc, rw, flags); 3617 3618 /* Reset regwin with gated clock */ 3619 state_lo = BWI_STATE_LO_RESET | 3620 BWI_STATE_LO_CLOCK | 3621 BWI_STATE_LO_GATED_CLOCK | 3622 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3623 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3624 3625 /* Flush pending bus write */ 3626 CSR_READ_4(sc, BWI_STATE_LO); 3627 DELAY(1); 3628 3629 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3630 if (state_hi & BWI_STATE_HI_SERROR) 3631 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3632 3633 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3634 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3635 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3636 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3637 } 3638 3639 /* Enable regwin with gated clock */ 3640 state_lo = BWI_STATE_LO_CLOCK | 3641 BWI_STATE_LO_GATED_CLOCK | 3642 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3643 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3644 3645 /* Flush pending bus write */ 3646 CSR_READ_4(sc, BWI_STATE_LO); 3647 DELAY(1); 3648 3649 /* Enable regwin with normal clock */ 3650 state_lo = BWI_STATE_LO_CLOCK | 3651 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3652 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3653 3654 /* Flush pending bus write */ 3655 CSR_READ_4(sc, BWI_STATE_LO); 3656 DELAY(1); 3657 } 3658 3659 static void 3660 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3661 { 3662 struct bwi_mac *mac; 3663 struct bwi_myaddr_bssid buf; 3664 const uint8_t *p; 3665 uint32_t val; 3666 int n, i; 3667 3668 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3669 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3670 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3671 3672 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3673 3674 bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr)); 3675 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3676 3677 n = sizeof(buf) / sizeof(val); 3678 p = (const uint8_t *)&buf; 3679 for (i = 0; i < n; ++i) { 3680 int j; 3681 3682 val = 0; 3683 for (j = 0; j < sizeof(val); ++j) 3684 val |= ((uint32_t)(*p++)) << (j * 8); 3685 3686 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3687 } 3688 } 3689 3690 static void 3691 bwi_updateslot(struct ieee80211com *ic) 3692 { 3693 struct bwi_softc *sc = ic->ic_softc; 3694 struct bwi_mac *mac; 3695 3696 BWI_LOCK(sc); 3697 if (sc->sc_flags & BWI_F_RUNNING) { 3698 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3699 3700 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3701 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3702 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3703 3704 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3705 } 3706 BWI_UNLOCK(sc); 3707 } 3708 3709 static void 3710 bwi_calibrate(void *xsc) 3711 { 3712 struct bwi_softc *sc = xsc; 3713 struct bwi_mac *mac; 3714 3715 BWI_ASSERT_LOCKED(sc); 3716 3717 KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR, 3718 ("opmode %d", sc->sc_ic.ic_opmode)); 3719 3720 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3721 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3722 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3723 3724 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3725 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3726 3727 /* XXX 15 seconds */ 3728 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3729 } 3730 3731 static int 3732 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3733 { 3734 struct bwi_mac *mac; 3735 3736 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3737 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3738 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3739 3740 return bwi_rf_calc_rssi(mac, hdr); 3741 } 3742 3743 static int 3744 bwi_calc_noise(struct bwi_softc *sc) 3745 { 3746 struct bwi_mac *mac; 3747 3748 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3749 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3750 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3751 3752 return bwi_rf_calc_noise(mac); 3753 } 3754 3755 static __inline uint8_t 3756 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type) 3757 { 3758 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK; 3759 return (ieee80211_plcp2rate(plcp, type)); 3760 } 3761 3762 static void 3763 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3764 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3765 { 3766 const struct ieee80211_frame_min *wh; 3767 3768 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3769 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3770 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3771 3772 wh = mtod(m, const struct ieee80211_frame_min *); 3773 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3774 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3775 3776 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian conversion */ 3777 sc->sc_rx_th.wr_rate = rate; 3778 sc->sc_rx_th.wr_antsignal = rssi; 3779 sc->sc_rx_th.wr_antnoise = noise; 3780 } 3781 3782 static void 3783 bwi_led_attach(struct bwi_softc *sc) 3784 { 3785 const uint8_t *led_act = NULL; 3786 uint16_t gpio, val[BWI_LED_MAX]; 3787 int i; 3788 3789 for (i = 0; i < nitems(bwi_vendor_led_act); ++i) { 3790 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3791 led_act = bwi_vendor_led_act[i].led_act; 3792 break; 3793 } 3794 } 3795 if (led_act == NULL) 3796 led_act = bwi_default_led_act; 3797 3798 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3799 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3800 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3801 3802 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3803 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3804 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3805 3806 for (i = 0; i < BWI_LED_MAX; ++i) { 3807 struct bwi_led *led = &sc->sc_leds[i]; 3808 3809 if (val[i] == 0xff) { 3810 led->l_act = led_act[i]; 3811 } else { 3812 if (val[i] & BWI_LED_ACT_LOW) 3813 led->l_flags |= BWI_LED_F_ACTLOW; 3814 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3815 } 3816 led->l_mask = (1 << i); 3817 3818 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3819 led->l_act == BWI_LED_ACT_BLINK_POLL || 3820 led->l_act == BWI_LED_ACT_BLINK) { 3821 led->l_flags |= BWI_LED_F_BLINK; 3822 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3823 led->l_flags |= BWI_LED_F_POLLABLE; 3824 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3825 led->l_flags |= BWI_LED_F_SLOW; 3826 3827 if (sc->sc_blink_led == NULL) { 3828 sc->sc_blink_led = led; 3829 if (led->l_flags & BWI_LED_F_SLOW) 3830 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3831 } 3832 } 3833 3834 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3835 "%dth led, act %d, lowact %d\n", i, 3836 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3837 } 3838 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3839 } 3840 3841 static __inline uint16_t 3842 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3843 { 3844 if (led->l_flags & BWI_LED_F_ACTLOW) 3845 on = !on; 3846 if (on) 3847 val |= led->l_mask; 3848 else 3849 val &= ~led->l_mask; 3850 return val; 3851 } 3852 3853 static void 3854 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3855 { 3856 struct ieee80211com *ic = &sc->sc_ic; 3857 uint16_t val; 3858 int i; 3859 3860 if (nstate == IEEE80211_S_INIT) { 3861 callout_stop(&sc->sc_led_blink_ch); 3862 sc->sc_led_blinking = 0; 3863 } 3864 3865 if ((sc->sc_flags & BWI_F_RUNNING) == 0) 3866 return; 3867 3868 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3869 for (i = 0; i < BWI_LED_MAX; ++i) { 3870 struct bwi_led *led = &sc->sc_leds[i]; 3871 int on; 3872 3873 if (led->l_act == BWI_LED_ACT_UNKN || 3874 led->l_act == BWI_LED_ACT_NULL) 3875 continue; 3876 3877 if ((led->l_flags & BWI_LED_F_BLINK) && 3878 nstate != IEEE80211_S_INIT) 3879 continue; 3880 3881 switch (led->l_act) { 3882 case BWI_LED_ACT_ON: /* Always on */ 3883 on = 1; 3884 break; 3885 case BWI_LED_ACT_OFF: /* Always off */ 3886 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3887 on = 0; 3888 break; 3889 default: 3890 on = 1; 3891 switch (nstate) { 3892 case IEEE80211_S_INIT: 3893 on = 0; 3894 break; 3895 case IEEE80211_S_RUN: 3896 if (led->l_act == BWI_LED_ACT_11G && 3897 ic->ic_curmode != IEEE80211_MODE_11G) 3898 on = 0; 3899 break; 3900 default: 3901 if (led->l_act == BWI_LED_ACT_ASSOC) 3902 on = 0; 3903 break; 3904 } 3905 break; 3906 } 3907 3908 val = bwi_led_onoff(led, val, on); 3909 } 3910 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3911 } 3912 static void 3913 bwi_led_event(struct bwi_softc *sc, int event) 3914 { 3915 struct bwi_led *led = sc->sc_blink_led; 3916 int rate; 3917 3918 if (event == BWI_LED_EVENT_POLL) { 3919 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3920 return; 3921 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3922 return; 3923 } 3924 3925 sc->sc_led_ticks = ticks; 3926 if (sc->sc_led_blinking) 3927 return; 3928 3929 switch (event) { 3930 case BWI_LED_EVENT_RX: 3931 rate = sc->sc_rx_rate; 3932 break; 3933 case BWI_LED_EVENT_TX: 3934 rate = sc->sc_tx_rate; 3935 break; 3936 case BWI_LED_EVENT_POLL: 3937 rate = 0; 3938 break; 3939 default: 3940 panic("unknown LED event %d\n", event); 3941 break; 3942 } 3943 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 3944 bwi_led_duration[rate].off_dur); 3945 } 3946 3947 static void 3948 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 3949 { 3950 struct bwi_led *led = sc->sc_blink_led; 3951 uint16_t val; 3952 3953 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3954 val = bwi_led_onoff(led, val, 1); 3955 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3956 3957 if (led->l_flags & BWI_LED_F_SLOW) { 3958 BWI_LED_SLOWDOWN(on_dur); 3959 BWI_LED_SLOWDOWN(off_dur); 3960 } 3961 3962 sc->sc_led_blinking = 1; 3963 sc->sc_led_blink_offdur = off_dur; 3964 3965 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 3966 } 3967 3968 static void 3969 bwi_led_blink_next(void *xsc) 3970 { 3971 struct bwi_softc *sc = xsc; 3972 uint16_t val; 3973 3974 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3975 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 3976 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3977 3978 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 3979 bwi_led_blink_end, sc); 3980 } 3981 3982 static void 3983 bwi_led_blink_end(void *xsc) 3984 { 3985 struct bwi_softc *sc = xsc; 3986 sc->sc_led_blinking = 0; 3987 } 3988 3989 static void 3990 bwi_restart(void *xsc, int pending) 3991 { 3992 struct bwi_softc *sc = xsc; 3993 3994 device_printf(sc->sc_dev, "%s begin, help!\n", __func__); 3995 BWI_LOCK(sc); 3996 bwi_init_statechg(sc, 0); 3997 #if 0 3998 bwi_start_locked(sc); 3999 #endif 4000 BWI_UNLOCK(sc); 4001 }
Cache object: 785de62bd3cc4eeea7baefa28ed2ff90
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