FreeBSD/Linux Kernel Cross Reference
sys/dev/bwi/if_bwi.c
1 /*
2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $
35 */
36
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD: releng/8.0/sys/dev/bwi/if_bwi.c 193310 2009-06-02 16:48:10Z imp $");
39
40 #include "opt_inet.h"
41 #include "opt_bwi.h"
42
43 #include <sys/param.h>
44 #include <sys/endian.h>
45 #include <sys/kernel.h>
46 #include <sys/bus.h>
47 #include <sys/malloc.h>
48 #include <sys/proc.h>
49 #include <sys/rman.h>
50 #include <sys/socket.h>
51 #include <sys/sockio.h>
52 #include <sys/sysctl.h>
53 #include <sys/systm.h>
54 #include <sys/taskqueue.h>
55
56 #include <net/if.h>
57 #include <net/if_dl.h>
58 #include <net/if_media.h>
59 #include <net/if_types.h>
60 #include <net/if_arp.h>
61 #include <net/ethernet.h>
62 #include <net/if_llc.h>
63
64 #include <net80211/ieee80211_var.h>
65 #include <net80211/ieee80211_radiotap.h>
66 #include <net80211/ieee80211_regdomain.h>
67 #include <net80211/ieee80211_amrr.h>
68 #include <net80211/ieee80211_phy.h>
69
70 #include <net/bpf.h>
71
72 #ifdef INET
73 #include <netinet/in.h>
74 #include <netinet/if_ether.h>
75 #endif
76
77 #include <machine/bus.h>
78
79 #include <dev/pci/pcivar.h>
80 #include <dev/pci/pcireg.h>
81
82 #include <dev/bwi/bitops.h>
83 #include <dev/bwi/if_bwireg.h>
84 #include <dev/bwi/if_bwivar.h>
85 #include <dev/bwi/bwimac.h>
86 #include <dev/bwi/bwirf.h>
87
88 struct bwi_clock_freq {
89 u_int clkfreq_min;
90 u_int clkfreq_max;
91 };
92
93 struct bwi_myaddr_bssid {
94 uint8_t myaddr[IEEE80211_ADDR_LEN];
95 uint8_t bssid[IEEE80211_ADDR_LEN];
96 } __packed;
97
98 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *,
99 const char [IFNAMSIZ], int, int, int,
100 const uint8_t [IEEE80211_ADDR_LEN],
101 const uint8_t [IEEE80211_ADDR_LEN]);
102 static void bwi_vap_delete(struct ieee80211vap *);
103 static void bwi_init(void *);
104 static int bwi_ioctl(struct ifnet *, u_long, caddr_t);
105 static void bwi_start(struct ifnet *);
106 static void bwi_start_locked(struct ifnet *);
107 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *,
108 const struct ieee80211_bpf_params *);
109 static void bwi_watchdog(struct ifnet *);
110 static void bwi_scan_start(struct ieee80211com *);
111 static void bwi_set_channel(struct ieee80211com *);
112 static void bwi_scan_end(struct ieee80211com *);
113 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int);
114 static void bwi_updateslot(struct ifnet *);
115 static struct ieee80211_node *bwi_node_alloc(struct ieee80211vap *,
116 const uint8_t [IEEE80211_ADDR_LEN]);
117 static void bwi_newassoc(struct ieee80211_node *, int);
118 static int bwi_media_change(struct ifnet *);
119
120 static void bwi_calibrate(void *);
121
122 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
123 static int bwi_calc_noise(struct bwi_softc *);
124 static __inline uint8_t bwi_ofdm_plcp2rate(const uint32_t *);
125 static __inline uint8_t bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *);
126 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
127 struct bwi_rxbuf_hdr *, const void *, int, int, int);
128
129 static void bwi_restart(void *, int);
130 static void bwi_init_statechg(struct bwi_softc *, int);
131 static void bwi_stop(struct bwi_softc *, int);
132 static void bwi_stop_locked(struct bwi_softc *, int);
133 static int bwi_newbuf(struct bwi_softc *, int, int);
134 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
135 struct ieee80211_node *);
136 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *,
137 struct ieee80211_node *,
138 const struct ieee80211_bpf_params *);
139
140 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
141 bus_addr_t, int, int);
142 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
143
144 static int bwi_init_tx_ring32(struct bwi_softc *, int);
145 static int bwi_init_rx_ring32(struct bwi_softc *);
146 static int bwi_init_txstats32(struct bwi_softc *);
147 static void bwi_free_tx_ring32(struct bwi_softc *, int);
148 static void bwi_free_rx_ring32(struct bwi_softc *);
149 static void bwi_free_txstats32(struct bwi_softc *);
150 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
151 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
152 int, bus_addr_t, int);
153 static int bwi_rxeof32(struct bwi_softc *);
154 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
155 static void bwi_txeof_status32(struct bwi_softc *);
156
157 static int bwi_init_tx_ring64(struct bwi_softc *, int);
158 static int bwi_init_rx_ring64(struct bwi_softc *);
159 static int bwi_init_txstats64(struct bwi_softc *);
160 static void bwi_free_tx_ring64(struct bwi_softc *, int);
161 static void bwi_free_rx_ring64(struct bwi_softc *);
162 static void bwi_free_txstats64(struct bwi_softc *);
163 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
164 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
165 int, bus_addr_t, int);
166 static int bwi_rxeof64(struct bwi_softc *);
167 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
168 static void bwi_txeof_status64(struct bwi_softc *);
169
170 static int bwi_rxeof(struct bwi_softc *, int);
171 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
172 static void bwi_txeof(struct bwi_softc *);
173 static void bwi_txeof_status(struct bwi_softc *, int);
174 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
175 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
176
177 static int bwi_dma_alloc(struct bwi_softc *);
178 static void bwi_dma_free(struct bwi_softc *);
179 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
180 struct bwi_ring_data *, bus_size_t,
181 uint32_t);
182 static int bwi_dma_mbuf_create(struct bwi_softc *);
183 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
184 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
185 static void bwi_dma_txstats_free(struct bwi_softc *);
186 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
187 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
188 bus_size_t, int);
189
190 static void bwi_power_on(struct bwi_softc *, int);
191 static int bwi_power_off(struct bwi_softc *, int);
192 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
193 static int bwi_set_clock_delay(struct bwi_softc *);
194 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
195 static int bwi_get_pwron_delay(struct bwi_softc *sc);
196 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
197 const uint8_t *);
198 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
199
200 static void bwi_get_card_flags(struct bwi_softc *);
201 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
202
203 static int bwi_bus_attach(struct bwi_softc *);
204 static int bwi_bbp_attach(struct bwi_softc *);
205 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
206 static void bwi_bbp_power_off(struct bwi_softc *);
207
208 static const char *bwi_regwin_name(const struct bwi_regwin *);
209 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
210 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
211 static int bwi_regwin_select(struct bwi_softc *, int);
212
213 static void bwi_led_attach(struct bwi_softc *);
214 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
215 static void bwi_led_event(struct bwi_softc *, int);
216 static void bwi_led_blink_start(struct bwi_softc *, int, int);
217 static void bwi_led_blink_next(void *);
218 static void bwi_led_blink_end(void *);
219
220 static const struct {
221 uint16_t did_min;
222 uint16_t did_max;
223 uint16_t bbp_id;
224 } bwi_bbpid_map[] = {
225 { 0x4301, 0x4301, 0x4301 },
226 { 0x4305, 0x4307, 0x4307 },
227 { 0x4403, 0x4403, 0x4402 },
228 { 0x4610, 0x4615, 0x4610 },
229 { 0x4710, 0x4715, 0x4710 },
230 { 0x4720, 0x4725, 0x4309 }
231 };
232
233 static const struct {
234 uint16_t bbp_id;
235 int nregwin;
236 } bwi_regwin_count[] = {
237 { 0x4301, 5 },
238 { 0x4306, 6 },
239 { 0x4307, 5 },
240 { 0x4310, 8 },
241 { 0x4401, 3 },
242 { 0x4402, 3 },
243 { 0x4610, 9 },
244 { 0x4704, 9 },
245 { 0x4710, 9 },
246 { 0x5365, 7 }
247 };
248
249 #define CLKSRC(src) \
250 [BWI_CLKSRC_ ## src] = { \
251 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
252 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
253 }
254
255 static const struct {
256 u_int freq_min;
257 u_int freq_max;
258 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
259 CLKSRC(LP_OSC),
260 CLKSRC(CS_OSC),
261 CLKSRC(PCI)
262 };
263
264 #undef CLKSRC
265
266 #define VENDOR_LED_ACT(vendor) \
267 { \
268 .vid = PCI_VENDOR_##vendor, \
269 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
270 }
271
272 static const struct {
273 #define PCI_VENDOR_COMPAQ 0x0e11
274 #define PCI_VENDOR_LINKSYS 0x1737
275 uint16_t vid;
276 uint8_t led_act[BWI_LED_MAX];
277 } bwi_vendor_led_act[] = {
278 VENDOR_LED_ACT(COMPAQ),
279 VENDOR_LED_ACT(LINKSYS)
280 #undef PCI_VENDOR_LINKSYS
281 #undef PCI_VENDOR_COMPAQ
282 };
283
284 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
285 { BWI_VENDOR_LED_ACT_DEFAULT };
286
287 #undef VENDOR_LED_ACT
288
289 static const struct {
290 int on_dur;
291 int off_dur;
292 } bwi_led_duration[109] = {
293 [0] = { 400, 100 },
294 [2] = { 150, 75 },
295 [4] = { 90, 45 },
296 [11] = { 66, 34 },
297 [12] = { 53, 26 },
298 [18] = { 42, 21 },
299 [22] = { 35, 17 },
300 [24] = { 32, 16 },
301 [36] = { 21, 10 },
302 [48] = { 16, 8 },
303 [72] = { 11, 5 },
304 [96] = { 9, 4 },
305 [108] = { 7, 3 }
306 };
307
308 #ifdef BWI_DEBUG
309 #ifdef BWI_DEBUG_VERBOSE
310 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
311 #else
312 static uint32_t bwi_debug;
313 #endif
314 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
315 #endif /* BWI_DEBUG */
316
317 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
318
319 uint16_t
320 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
321 {
322 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
323 }
324
325 static __inline void
326 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
327 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
328 int tx)
329 {
330 struct bwi_desc32 *desc = &desc_array[desc_idx];
331 uint32_t ctrl, addr, addr_hi, addr_lo;
332
333 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
334 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
335
336 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
337 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
338
339 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
340 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
341 if (desc_idx == ndesc - 1)
342 ctrl |= BWI_DESC32_C_EOR;
343 if (tx) {
344 /* XXX */
345 ctrl |= BWI_DESC32_C_FRAME_START |
346 BWI_DESC32_C_FRAME_END |
347 BWI_DESC32_C_INTR;
348 }
349
350 desc->addr = htole32(addr);
351 desc->ctrl = htole32(ctrl);
352 }
353
354 int
355 bwi_attach(struct bwi_softc *sc)
356 {
357 struct ieee80211com *ic;
358 device_t dev = sc->sc_dev;
359 struct ifnet *ifp;
360 struct bwi_mac *mac;
361 struct bwi_phy *phy;
362 int i, error;
363 uint8_t bands;
364 uint8_t macaddr[IEEE80211_ADDR_LEN];
365
366 BWI_LOCK_INIT(sc);
367
368 /*
369 * Initialize taskq and various tasks
370 */
371 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO,
372 taskqueue_thread_enqueue, &sc->sc_tq);
373 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
374 device_get_nameunit(dev));
375 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc);
376
377 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0);
378
379 /*
380 * Initialize sysctl variables
381 */
382 sc->sc_fw_version = BWI_FW_VERSION3;
383 sc->sc_led_idle = (2350 * hz) / 1000;
384 sc->sc_led_blink = 1;
385 sc->sc_txpwr_calib = 1;
386 #ifdef BWI_DEBUG
387 sc->sc_debug = bwi_debug;
388 #endif
389 bwi_power_on(sc, 1);
390
391 error = bwi_bbp_attach(sc);
392 if (error)
393 goto fail;
394
395 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
396 if (error)
397 goto fail;
398
399 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
400 error = bwi_set_clock_delay(sc);
401 if (error)
402 goto fail;
403
404 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
405 if (error)
406 goto fail;
407
408 error = bwi_get_pwron_delay(sc);
409 if (error)
410 goto fail;
411 }
412
413 error = bwi_bus_attach(sc);
414 if (error)
415 goto fail;
416
417 bwi_get_card_flags(sc);
418
419 bwi_led_attach(sc);
420
421 for (i = 0; i < sc->sc_nmac; ++i) {
422 struct bwi_regwin *old;
423
424 mac = &sc->sc_mac[i];
425 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
426 if (error)
427 goto fail;
428
429 error = bwi_mac_lateattach(mac);
430 if (error)
431 goto fail;
432
433 error = bwi_regwin_switch(sc, old, NULL);
434 if (error)
435 goto fail;
436 }
437
438 /*
439 * XXX First MAC is known to exist
440 * TODO2
441 */
442 mac = &sc->sc_mac[0];
443 phy = &mac->mac_phy;
444
445 bwi_bbp_power_off(sc);
446
447 error = bwi_dma_alloc(sc);
448 if (error)
449 goto fail;
450
451 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
452 if (ifp == NULL) {
453 device_printf(dev, "can not if_alloc()\n");
454 error = ENOSPC;
455 goto fail;
456 }
457 ic = ifp->if_l2com;
458
459 /* set these up early for if_printf use */
460 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
461
462 ifp->if_softc = sc;
463 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
464 ifp->if_init = bwi_init;
465 ifp->if_ioctl = bwi_ioctl;
466 ifp->if_start = bwi_start;
467 ifp->if_watchdog = bwi_watchdog;
468 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
469 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
470 IFQ_SET_READY(&ifp->if_snd);
471
472 /*
473 * Setup ratesets, phytype, channels and get MAC address
474 */
475 bands = 0;
476 if (phy->phy_mode == IEEE80211_MODE_11B ||
477 phy->phy_mode == IEEE80211_MODE_11G) {
478 setbit(&bands, IEEE80211_MODE_11B);
479 if (phy->phy_mode == IEEE80211_MODE_11B) {
480 ic->ic_phytype = IEEE80211_T_DS;
481 } else {
482 ic->ic_phytype = IEEE80211_T_OFDM;
483 setbit(&bands, IEEE80211_MODE_11G);
484 }
485
486 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, macaddr);
487 if (IEEE80211_IS_MULTICAST(macaddr)) {
488 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, macaddr);
489 if (IEEE80211_IS_MULTICAST(macaddr)) {
490 device_printf(dev,
491 "invalid MAC address: %6D\n",
492 macaddr, ":");
493 }
494 }
495 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
496 /* TODO:11A */
497 setbit(&bands, IEEE80211_MODE_11A);
498 error = ENXIO;
499 goto fail;
500 } else {
501 panic("unknown phymode %d\n", phy->phy_mode);
502 }
503
504 /* Get locale */
505 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
506 BWI_SPROM_CARD_INFO_LOCALE);
507 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
508 /* XXX use locale */
509 ieee80211_init_channels(ic, NULL, &bands);
510
511 ic->ic_ifp = ifp;
512 ic->ic_caps = IEEE80211_C_STA |
513 IEEE80211_C_SHSLOT |
514 IEEE80211_C_SHPREAMBLE |
515 IEEE80211_C_WPA |
516 IEEE80211_C_BGSCAN |
517 IEEE80211_C_MONITOR;
518 ic->ic_opmode = IEEE80211_M_STA;
519 ieee80211_ifattach(ic, macaddr);
520
521 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
522
523 /* override default methods */
524 ic->ic_vap_create = bwi_vap_create;
525 ic->ic_vap_delete = bwi_vap_delete;
526 ic->ic_raw_xmit = bwi_raw_xmit;
527 ic->ic_updateslot = bwi_updateslot;
528 ic->ic_node_alloc = bwi_node_alloc;
529 ic->ic_scan_start = bwi_scan_start;
530 ic->ic_scan_end = bwi_scan_end;
531 ic->ic_set_channel = bwi_set_channel;
532
533 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan);
534
535 ieee80211_radiotap_attach(ic,
536 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
537 BWI_TX_RADIOTAP_PRESENT,
538 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
539 BWI_RX_RADIOTAP_PRESENT);
540
541 /*
542 * Add sysctl nodes
543 */
544 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
545 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
546 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
547 "Firmware version");
548 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
549 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
550 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
551 "# ticks before LED enters idle state");
552 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
553 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
554 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
555 "Allow LED to blink");
556 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
557 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
558 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
559 "Enable software TX power calibration");
560 #ifdef BWI_DEBUG
561 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
562 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
563 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
564 #endif
565 if (bootverbose)
566 ieee80211_announce(ic);
567
568 return (0);
569 fail:
570 BWI_LOCK_DESTROY(sc);
571 return (error);
572 }
573
574 int
575 bwi_detach(struct bwi_softc *sc)
576 {
577 struct ifnet *ifp = sc->sc_ifp;
578 struct ieee80211com *ic = ifp->if_l2com;
579 int i;
580
581 bwi_stop(sc, 1);
582 callout_drain(&sc->sc_led_blink_ch);
583 callout_drain(&sc->sc_calib_ch);
584 ieee80211_ifdetach(ic);
585
586 for (i = 0; i < sc->sc_nmac; ++i)
587 bwi_mac_detach(&sc->sc_mac[i]);
588 bwi_dma_free(sc);
589 if_free(ifp);
590 taskqueue_free(sc->sc_tq);
591
592 BWI_LOCK_DESTROY(sc);
593
594 return (0);
595 }
596
597 static struct ieee80211vap *
598 bwi_vap_create(struct ieee80211com *ic,
599 const char name[IFNAMSIZ], int unit, int opmode, int flags,
600 const uint8_t bssid[IEEE80211_ADDR_LEN],
601 const uint8_t mac[IEEE80211_ADDR_LEN])
602 {
603 struct bwi_vap *bvp;
604 struct ieee80211vap *vap;
605
606 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
607 return NULL;
608 bvp = (struct bwi_vap *) malloc(sizeof(struct bwi_vap),
609 M_80211_VAP, M_WAITOK | M_ZERO);
610 if (bvp == NULL)
611 return NULL;
612 vap = &bvp->bv_vap;
613 /* enable s/w bmiss handling for sta mode */
614 ieee80211_vap_setup(ic, vap, name, unit, opmode,
615 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac);
616
617 /* override default methods */
618 bvp->bv_newstate = vap->iv_newstate;
619 vap->iv_newstate = bwi_newstate;
620 #if 0
621 vap->iv_update_beacon = bwi_beacon_update;
622 #endif
623 ieee80211_amrr_init(&bvp->bv_amrr, vap,
624 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD,
625 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD,
626 500 /*ms*/);
627
628 /* complete setup */
629 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status);
630 ic->ic_opmode = opmode;
631 return vap;
632 }
633
634 static void
635 bwi_vap_delete(struct ieee80211vap *vap)
636 {
637 struct bwi_vap *bvp = BWI_VAP(vap);
638
639 ieee80211_amrr_cleanup(&bvp->bv_amrr);
640 ieee80211_vap_detach(vap);
641 free(bvp, M_80211_VAP);
642 }
643
644 void
645 bwi_suspend(struct bwi_softc *sc)
646 {
647 bwi_stop(sc, 1);
648 }
649
650 void
651 bwi_resume(struct bwi_softc *sc)
652 {
653 struct ifnet *ifp = sc->sc_ifp;
654
655 if (ifp->if_flags & IFF_UP)
656 bwi_init(sc);
657 }
658
659 int
660 bwi_shutdown(struct bwi_softc *sc)
661 {
662 bwi_stop(sc, 1);
663 return 0;
664 }
665
666 static void
667 bwi_power_on(struct bwi_softc *sc, int with_pll)
668 {
669 uint32_t gpio_in, gpio_out, gpio_en;
670 uint16_t status;
671
672 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
673 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
674 goto back;
675
676 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
677 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
678
679 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
680 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
681 if (with_pll) {
682 /* Turn off PLL first */
683 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
684 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
685 }
686
687 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
688 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
689 DELAY(1000);
690
691 if (with_pll) {
692 /* Turn on PLL */
693 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
694 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
695 DELAY(5000);
696 }
697
698 back:
699 /* Clear "Signaled Target Abort" */
700 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
701 status &= ~PCIM_STATUS_STABORT;
702 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
703 }
704
705 static int
706 bwi_power_off(struct bwi_softc *sc, int with_pll)
707 {
708 uint32_t gpio_out, gpio_en;
709
710 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
711 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
712 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
713
714 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
715 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
716 if (with_pll) {
717 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
718 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
719 }
720
721 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
722 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
723 return 0;
724 }
725
726 int
727 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
728 struct bwi_regwin **old_rw)
729 {
730 int error;
731
732 if (old_rw != NULL)
733 *old_rw = NULL;
734
735 if (!BWI_REGWIN_EXIST(rw))
736 return EINVAL;
737
738 if (sc->sc_cur_regwin != rw) {
739 error = bwi_regwin_select(sc, rw->rw_id);
740 if (error) {
741 device_printf(sc->sc_dev, "can't select regwin %d\n",
742 rw->rw_id);
743 return error;
744 }
745 }
746
747 if (old_rw != NULL)
748 *old_rw = sc->sc_cur_regwin;
749 sc->sc_cur_regwin = rw;
750 return 0;
751 }
752
753 static int
754 bwi_regwin_select(struct bwi_softc *sc, int id)
755 {
756 uint32_t win = BWI_PCIM_REGWIN(id);
757 int i;
758
759 #define RETRY_MAX 50
760 for (i = 0; i < RETRY_MAX; ++i) {
761 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
762 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
763 return 0;
764 DELAY(10);
765 }
766 #undef RETRY_MAX
767
768 return ENXIO;
769 }
770
771 static void
772 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
773 {
774 uint32_t val;
775
776 val = CSR_READ_4(sc, BWI_ID_HI);
777 *type = BWI_ID_HI_REGWIN_TYPE(val);
778 *rev = BWI_ID_HI_REGWIN_REV(val);
779
780 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
781 "vendor 0x%04x\n", *type, *rev,
782 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
783 }
784
785 static int
786 bwi_bbp_attach(struct bwi_softc *sc)
787 {
788 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
789 uint16_t bbp_id, rw_type;
790 uint8_t rw_rev;
791 uint32_t info;
792 int error, nregwin, i;
793
794 /*
795 * Get 0th regwin information
796 * NOTE: 0th regwin should exist
797 */
798 error = bwi_regwin_select(sc, 0);
799 if (error) {
800 device_printf(sc->sc_dev, "can't select regwin 0\n");
801 return error;
802 }
803 bwi_regwin_info(sc, &rw_type, &rw_rev);
804
805 /*
806 * Find out BBP id
807 */
808 bbp_id = 0;
809 info = 0;
810 if (rw_type == BWI_REGWIN_T_COM) {
811 info = CSR_READ_4(sc, BWI_INFO);
812 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
813
814 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
815
816 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
817 } else {
818 for (i = 0; i < N(bwi_bbpid_map); ++i) {
819 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min &&
820 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) {
821 bbp_id = bwi_bbpid_map[i].bbp_id;
822 break;
823 }
824 }
825 if (bbp_id == 0) {
826 device_printf(sc->sc_dev, "no BBP id for device id "
827 "0x%04x\n", sc->sc_pci_did);
828 return ENXIO;
829 }
830
831 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) |
832 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
833 }
834
835 /*
836 * Find out number of regwins
837 */
838 nregwin = 0;
839 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
840 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
841 } else {
842 for (i = 0; i < N(bwi_regwin_count); ++i) {
843 if (bwi_regwin_count[i].bbp_id == bbp_id) {
844 nregwin = bwi_regwin_count[i].nregwin;
845 break;
846 }
847 }
848 if (nregwin == 0) {
849 device_printf(sc->sc_dev, "no number of win for "
850 "BBP id 0x%04x\n", bbp_id);
851 return ENXIO;
852 }
853 }
854
855 /* Record BBP id/rev for later using */
856 sc->sc_bbp_id = bbp_id;
857 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
858 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
859 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
860 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
861
862 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
863 nregwin, sc->sc_cap);
864
865 /*
866 * Create rest of the regwins
867 */
868
869 /* Don't re-create common regwin, if it is already created */
870 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
871
872 for (; i < nregwin; ++i) {
873 /*
874 * Get regwin information
875 */
876 error = bwi_regwin_select(sc, i);
877 if (error) {
878 device_printf(sc->sc_dev,
879 "can't select regwin %d\n", i);
880 return error;
881 }
882 bwi_regwin_info(sc, &rw_type, &rw_rev);
883
884 /*
885 * Try attach:
886 * 1) Bus (PCI/PCIE) regwin
887 * 2) MAC regwin
888 * Ignore rest types of regwin
889 */
890 if (rw_type == BWI_REGWIN_T_BUSPCI ||
891 rw_type == BWI_REGWIN_T_BUSPCIE) {
892 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
893 device_printf(sc->sc_dev,
894 "bus regwin already exists\n");
895 } else {
896 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
897 rw_type, rw_rev);
898 }
899 } else if (rw_type == BWI_REGWIN_T_MAC) {
900 /* XXX ignore return value */
901 bwi_mac_attach(sc, i, rw_rev);
902 }
903 }
904
905 /* At least one MAC shold exist */
906 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
907 device_printf(sc->sc_dev, "no MAC was found\n");
908 return ENXIO;
909 }
910 KASSERT(sc->sc_nmac > 0, ("no mac's"));
911
912 /* Bus regwin must exist */
913 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
914 device_printf(sc->sc_dev, "no bus regwin was found\n");
915 return ENXIO;
916 }
917
918 /* Start with first MAC */
919 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
920 if (error)
921 return error;
922
923 return 0;
924 #undef N
925 }
926
927 int
928 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
929 {
930 struct bwi_regwin *old, *bus;
931 uint32_t val;
932 int error;
933
934 bus = &sc->sc_bus_regwin;
935 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin"));
936
937 /*
938 * Tell bus to generate requested interrupts
939 */
940 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
941 /*
942 * NOTE: Read BWI_FLAGS from MAC regwin
943 */
944 val = CSR_READ_4(sc, BWI_FLAGS);
945
946 error = bwi_regwin_switch(sc, bus, &old);
947 if (error)
948 return error;
949
950 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
951 } else {
952 uint32_t mac_mask;
953
954 mac_mask = 1 << mac->mac_id;
955
956 error = bwi_regwin_switch(sc, bus, &old);
957 if (error)
958 return error;
959
960 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
961 val |= mac_mask << 8;
962 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
963 }
964
965 if (sc->sc_flags & BWI_F_BUS_INITED)
966 goto back;
967
968 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
969 /*
970 * Enable prefetch and burst
971 */
972 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
973 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
974
975 if (bus->rw_rev < 5) {
976 struct bwi_regwin *com = &sc->sc_com_regwin;
977
978 /*
979 * Configure timeouts for bus operation
980 */
981
982 /*
983 * Set service timeout and request timeout
984 */
985 CSR_SETBITS_4(sc, BWI_CONF_LO,
986 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
987 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
988
989 /*
990 * If there is common regwin, we switch to that regwin
991 * and switch back to bus regwin once we have done.
992 */
993 if (BWI_REGWIN_EXIST(com)) {
994 error = bwi_regwin_switch(sc, com, NULL);
995 if (error)
996 return error;
997 }
998
999 /* Let bus know what we have changed */
1000 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
1001 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
1002 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
1003 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1004
1005 if (BWI_REGWIN_EXIST(com)) {
1006 error = bwi_regwin_switch(sc, bus, NULL);
1007 if (error)
1008 return error;
1009 }
1010 } else if (bus->rw_rev >= 11) {
1011 /*
1012 * Enable memory read multiple
1013 */
1014 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
1015 }
1016 } else {
1017 /* TODO:PCIE */
1018 }
1019
1020 sc->sc_flags |= BWI_F_BUS_INITED;
1021 back:
1022 return bwi_regwin_switch(sc, old, NULL);
1023 }
1024
1025 static void
1026 bwi_get_card_flags(struct bwi_softc *sc)
1027 {
1028 #define PCI_VENDOR_APPLE 0x106b
1029 #define PCI_VENDOR_DELL 0x1028
1030 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1031 if (sc->sc_card_flags == 0xffff)
1032 sc->sc_card_flags = 0;
1033
1034 if (sc->sc_pci_subvid == PCI_VENDOR_DELL &&
1035 sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1036 sc->sc_pci_revid == 0x74)
1037 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST;
1038
1039 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1040 sc->sc_pci_subdid == 0x4e && /* XXX */
1041 sc->sc_pci_revid > 0x40)
1042 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1043
1044 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1045 #undef PCI_VENDOR_DELL
1046 #undef PCI_VENDOR_APPLE
1047 }
1048
1049 static void
1050 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1051 {
1052 int i;
1053
1054 for (i = 0; i < 3; ++i) {
1055 *((uint16_t *)eaddr + i) =
1056 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1057 }
1058 }
1059
1060 static void
1061 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1062 {
1063 struct bwi_regwin *com;
1064 uint32_t val;
1065 u_int div;
1066 int src;
1067
1068 bzero(freq, sizeof(*freq));
1069 com = &sc->sc_com_regwin;
1070
1071 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist"));
1072 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin"));
1073 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode"));
1074
1075 /*
1076 * Calculate clock frequency
1077 */
1078 src = -1;
1079 div = 0;
1080 if (com->rw_rev < 6) {
1081 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1082 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1083 src = BWI_CLKSRC_PCI;
1084 div = 64;
1085 } else {
1086 src = BWI_CLKSRC_CS_OSC;
1087 div = 32;
1088 }
1089 } else if (com->rw_rev < 10) {
1090 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1091
1092 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1093 if (src == BWI_CLKSRC_LP_OSC) {
1094 div = 1;
1095 } else {
1096 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1097
1098 /* Unknown source */
1099 if (src >= BWI_CLKSRC_MAX)
1100 src = BWI_CLKSRC_CS_OSC;
1101 }
1102 } else {
1103 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1104
1105 src = BWI_CLKSRC_CS_OSC;
1106 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1107 }
1108
1109 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src));
1110 KASSERT(div != 0, ("div zero"));
1111
1112 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1113 src == BWI_CLKSRC_PCI ? "PCI" :
1114 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1115
1116 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1117 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1118
1119 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1120 freq->clkfreq_min, freq->clkfreq_max);
1121 }
1122
1123 static int
1124 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1125 {
1126 struct bwi_regwin *old, *com;
1127 uint32_t clk_ctrl, clk_src;
1128 int error, pwr_off = 0;
1129
1130 com = &sc->sc_com_regwin;
1131 if (!BWI_REGWIN_EXIST(com))
1132 return 0;
1133
1134 if (com->rw_rev >= 10 || com->rw_rev < 6)
1135 return 0;
1136
1137 /*
1138 * For common regwin whose rev is [6, 10), the chip
1139 * must be capable to change clock mode.
1140 */
1141 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1142 return 0;
1143
1144 error = bwi_regwin_switch(sc, com, &old);
1145 if (error)
1146 return error;
1147
1148 if (clk_mode == BWI_CLOCK_MODE_FAST)
1149 bwi_power_on(sc, 0); /* Don't turn on PLL */
1150
1151 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1152 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1153
1154 switch (clk_mode) {
1155 case BWI_CLOCK_MODE_FAST:
1156 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1157 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1158 break;
1159 case BWI_CLOCK_MODE_SLOW:
1160 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1161 break;
1162 case BWI_CLOCK_MODE_DYN:
1163 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1164 BWI_CLOCK_CTRL_IGNPLL |
1165 BWI_CLOCK_CTRL_NODYN);
1166 if (clk_src != BWI_CLKSRC_CS_OSC) {
1167 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1168 pwr_off = 1;
1169 }
1170 break;
1171 }
1172 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1173
1174 if (pwr_off)
1175 bwi_power_off(sc, 0); /* Leave PLL as it is */
1176
1177 return bwi_regwin_switch(sc, old, NULL);
1178 }
1179
1180 static int
1181 bwi_set_clock_delay(struct bwi_softc *sc)
1182 {
1183 struct bwi_regwin *old, *com;
1184 int error;
1185
1186 com = &sc->sc_com_regwin;
1187 if (!BWI_REGWIN_EXIST(com))
1188 return 0;
1189
1190 error = bwi_regwin_switch(sc, com, &old);
1191 if (error)
1192 return error;
1193
1194 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1195 if (sc->sc_bbp_rev == 0)
1196 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1197 else if (sc->sc_bbp_rev == 1)
1198 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1199 }
1200
1201 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1202 if (com->rw_rev >= 10) {
1203 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1204 } else {
1205 struct bwi_clock_freq freq;
1206
1207 bwi_get_clock_freq(sc, &freq);
1208 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1209 howmany(freq.clkfreq_max * 150, 1000000));
1210 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1211 howmany(freq.clkfreq_max * 15, 1000000));
1212 }
1213 }
1214
1215 return bwi_regwin_switch(sc, old, NULL);
1216 }
1217
1218 static void
1219 bwi_init(void *xsc)
1220 {
1221 struct bwi_softc *sc = xsc;
1222 struct ifnet *ifp = sc->sc_ifp;
1223 struct ieee80211com *ic = ifp->if_l2com;
1224
1225 BWI_LOCK(sc);
1226 bwi_init_statechg(sc, 1);
1227 BWI_UNLOCK(sc);
1228
1229 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1230 ieee80211_start_all(ic); /* start all vap's */
1231 }
1232
1233 static void
1234 bwi_init_statechg(struct bwi_softc *sc, int statechg)
1235 {
1236 struct ifnet *ifp = sc->sc_ifp;
1237 struct bwi_mac *mac;
1238 int error;
1239
1240 bwi_stop_locked(sc, statechg);
1241
1242 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1243
1244 /* TODO: 2 MAC */
1245
1246 mac = &sc->sc_mac[0];
1247 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1248 if (error) {
1249 if_printf(ifp, "%s: error %d on regwin switch\n",
1250 __func__, error);
1251 goto bad;
1252 }
1253 error = bwi_mac_init(mac);
1254 if (error) {
1255 if_printf(ifp, "%s: error %d on MAC init\n", __func__, error);
1256 goto bad;
1257 }
1258
1259 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1260
1261 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1262 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, IF_LLADDR(ifp));
1263
1264 bwi_mac_reset_hwkeys(mac);
1265
1266 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1267 int i;
1268
1269 #define NRETRY 1000
1270 /*
1271 * Drain any possible pending TX status
1272 */
1273 for (i = 0; i < NRETRY; ++i) {
1274 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1275 BWI_TXSTATUS0_VALID) == 0)
1276 break;
1277 CSR_READ_4(sc, BWI_TXSTATUS1);
1278 }
1279 if (i == NRETRY)
1280 if_printf(ifp, "%s: can't drain TX status\n", __func__);
1281 #undef NRETRY
1282 }
1283
1284 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1285 bwi_mac_updateslot(mac, 1);
1286
1287 /* Start MAC */
1288 error = bwi_mac_start(mac);
1289 if (error) {
1290 if_printf(ifp, "%s: error %d starting MAC\n", __func__, error);
1291 goto bad;
1292 }
1293
1294 /* Clear stop flag before enabling interrupt */
1295 sc->sc_flags &= ~BWI_F_STOP;
1296
1297 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1298
1299 /* Enable intrs */
1300 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1301 return;
1302 bad:
1303 bwi_stop_locked(sc, 1);
1304 }
1305
1306 static int
1307 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1308 {
1309 #define IS_RUNNING(ifp) \
1310 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
1311 struct bwi_softc *sc = ifp->if_softc;
1312 struct ieee80211com *ic = ifp->if_l2com;
1313 struct ifreq *ifr = (struct ifreq *) data;
1314 int error = 0, startall = 0;
1315
1316 switch (cmd) {
1317 case SIOCSIFFLAGS:
1318 BWI_LOCK(sc);
1319 if (IS_RUNNING(ifp)) {
1320 struct bwi_mac *mac;
1321 int promisc = -1;
1322
1323 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1324 ("current regwin type %d",
1325 sc->sc_cur_regwin->rw_type));
1326 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1327
1328 if ((ifp->if_flags & IFF_PROMISC) &&
1329 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1330 promisc = 1;
1331 sc->sc_flags |= BWI_F_PROMISC;
1332 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1333 (sc->sc_flags & BWI_F_PROMISC)) {
1334 promisc = 0;
1335 sc->sc_flags &= ~BWI_F_PROMISC;
1336 }
1337
1338 if (promisc >= 0)
1339 bwi_mac_set_promisc(mac, promisc);
1340 }
1341
1342 if (ifp->if_flags & IFF_UP) {
1343 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1344 bwi_init_statechg(sc, 1);
1345 startall = 1;
1346 }
1347 } else {
1348 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1349 bwi_stop_locked(sc, 1);
1350 }
1351 BWI_UNLOCK(sc);
1352 if (startall)
1353 ieee80211_start_all(ic);
1354 break;
1355 case SIOCGIFMEDIA:
1356 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1357 break;
1358 case SIOCGIFADDR:
1359 error = ether_ioctl(ifp, cmd, data);
1360 break;
1361 default:
1362 error = EINVAL;
1363 break;
1364 }
1365 return error;
1366 #undef IS_RUNNING
1367 }
1368
1369 static void
1370 bwi_start(struct ifnet *ifp)
1371 {
1372 struct bwi_softc *sc = ifp->if_softc;
1373
1374 BWI_LOCK(sc);
1375 bwi_start_locked(ifp);
1376 BWI_UNLOCK(sc);
1377 }
1378
1379 static void
1380 bwi_start_locked(struct ifnet *ifp)
1381 {
1382 struct bwi_softc *sc = ifp->if_softc;
1383 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1384 struct ieee80211_frame *wh;
1385 struct ieee80211_node *ni;
1386 struct ieee80211_key *k;
1387 struct mbuf *m;
1388 int trans, idx;
1389
1390 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1391 return;
1392
1393 trans = 0;
1394 idx = tbd->tbd_idx;
1395
1396 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1397 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */
1398 if (m == NULL)
1399 break;
1400
1401 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1402 wh = mtod(m, struct ieee80211_frame *);
1403 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1404 k = ieee80211_crypto_encap(ni, m);
1405 if (k == NULL) {
1406 ieee80211_free_node(ni);
1407 m_freem(m);
1408 ifp->if_oerrors++;
1409 continue;
1410 }
1411 }
1412 wh = NULL; /* Catch any invalid use */
1413
1414 if (bwi_encap(sc, idx, m, ni) != 0) {
1415 /* 'm' is freed in bwi_encap() if we reach here */
1416 if (ni != NULL)
1417 ieee80211_free_node(ni);
1418 ifp->if_oerrors++;
1419 continue;
1420 }
1421
1422 trans = 1;
1423 tbd->tbd_used++;
1424 idx = (idx + 1) % BWI_TX_NDESC;
1425
1426 ifp->if_opackets++;
1427
1428 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
1429 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1430 break;
1431 }
1432 }
1433 tbd->tbd_idx = idx;
1434
1435 if (trans)
1436 ifp->if_timer = 5;
1437 }
1438
1439 static int
1440 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1441 const struct ieee80211_bpf_params *params)
1442 {
1443 struct ieee80211com *ic = ni->ni_ic;
1444 struct ifnet *ifp = ic->ic_ifp;
1445 struct bwi_softc *sc = ifp->if_softc;
1446 /* XXX wme? */
1447 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1448 int idx, error;
1449
1450 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1451 ieee80211_free_node(ni);
1452 m_freem(m);
1453 return ENETDOWN;
1454 }
1455
1456 BWI_LOCK(sc);
1457 idx = tbd->tbd_idx;
1458 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx));
1459 if (params == NULL) {
1460 /*
1461 * Legacy path; interpret frame contents to decide
1462 * precisely how to send the frame.
1463 */
1464 error = bwi_encap(sc, idx, m, ni);
1465 } else {
1466 /*
1467 * Caller supplied explicit parameters to use in
1468 * sending the frame.
1469 */
1470 error = bwi_encap_raw(sc, idx, m, ni, params);
1471 }
1472 if (error == 0) {
1473 ifp->if_opackets++;
1474 if (++tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC)
1475 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1476 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC;
1477 ifp->if_timer = 5;
1478 } else {
1479 /* NB: m is reclaimed on encap failure */
1480 ieee80211_free_node(ni);
1481 ifp->if_oerrors++;
1482 }
1483 BWI_UNLOCK(sc);
1484 return error;
1485 }
1486
1487 static void
1488 bwi_watchdog(struct ifnet *ifp)
1489 {
1490 struct bwi_softc *sc = ifp->if_softc;
1491
1492 BWI_LOCK(sc);
1493 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1494 if_printf(ifp, "watchdog timeout\n");
1495 ifp->if_oerrors++;
1496 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1497 }
1498 BWI_UNLOCK(sc);
1499 }
1500
1501 static void
1502 bwi_stop(struct bwi_softc *sc, int statechg)
1503 {
1504 BWI_LOCK(sc);
1505 bwi_stop_locked(sc, statechg);
1506 BWI_UNLOCK(sc);
1507 }
1508
1509 static void
1510 bwi_stop_locked(struct bwi_softc *sc, int statechg)
1511 {
1512 struct ifnet *ifp = sc->sc_ifp;
1513 struct bwi_mac *mac;
1514 int i, error, pwr_off = 0;
1515
1516 BWI_ASSERT_LOCKED(sc);
1517
1518 callout_stop(&sc->sc_calib_ch);
1519 callout_stop(&sc->sc_led_blink_ch);
1520 sc->sc_led_blinking = 0;
1521 sc->sc_flags |= BWI_F_STOP;
1522
1523 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1524 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1525 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1526 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1527
1528 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1529 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1530 bwi_mac_stop(mac);
1531 }
1532
1533 for (i = 0; i < sc->sc_nmac; ++i) {
1534 struct bwi_regwin *old_rw;
1535
1536 mac = &sc->sc_mac[i];
1537 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1538 continue;
1539
1540 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1541 if (error)
1542 continue;
1543
1544 bwi_mac_shutdown(mac);
1545 pwr_off = 1;
1546
1547 bwi_regwin_switch(sc, old_rw, NULL);
1548 }
1549
1550 if (pwr_off)
1551 bwi_bbp_power_off(sc);
1552
1553 sc->sc_tx_timer = 0;
1554 ifp->if_timer = 0;
1555 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1556 }
1557
1558 void
1559 bwi_intr(void *xsc)
1560 {
1561 struct bwi_softc *sc = xsc;
1562 struct ifnet *ifp = sc->sc_ifp;
1563 struct bwi_mac *mac;
1564 uint32_t intr_status;
1565 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1566 int i, txrx_error, tx = 0, rx_data = -1;
1567
1568 BWI_LOCK(sc);
1569
1570 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
1571 (sc->sc_flags & BWI_F_STOP)) {
1572 BWI_UNLOCK(sc);
1573 return;
1574 }
1575 /*
1576 * Get interrupt status
1577 */
1578 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1579 if (intr_status == 0xffffffff) { /* Not for us */
1580 BWI_UNLOCK(sc);
1581 return;
1582 }
1583
1584 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1585
1586 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1587 if (intr_status == 0) { /* Nothing is interesting */
1588 BWI_UNLOCK(sc);
1589 return;
1590 }
1591
1592 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1593 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1594 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1595
1596 txrx_error = 0;
1597 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1598 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1599 uint32_t mask;
1600
1601 if (BWI_TXRX_IS_RX(i))
1602 mask = BWI_TXRX_RX_INTRS;
1603 else
1604 mask = BWI_TXRX_TX_INTRS;
1605
1606 txrx_intr_status[i] =
1607 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1608
1609 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1610 i, txrx_intr_status[i]);
1611
1612 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1613 if_printf(ifp,
1614 "%s: intr fatal TX/RX (%d) error 0x%08x\n",
1615 __func__, i, txrx_intr_status[i]);
1616 txrx_error = 1;
1617 }
1618 }
1619 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1620
1621 /*
1622 * Acknowledge interrupt
1623 */
1624 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1625
1626 for (i = 0; i < BWI_TXRX_NRING; ++i)
1627 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1628
1629 /* Disable all interrupts */
1630 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1631
1632 /*
1633 * http://bcm-specs.sipsolutions.net/Interrupts
1634 * Says for this bit (0x800):
1635 * "Fatal Error
1636 *
1637 * We got this one while testing things when by accident the
1638 * template ram wasn't set to big endian when it should have
1639 * been after writing the initial values. It keeps on being
1640 * triggered, the only way to stop it seems to shut down the
1641 * chip."
1642 *
1643 * Suggesting that we should never get it and if we do we're not
1644 * feeding TX packets into the MAC correctly if we do... Apparently,
1645 * it is valid only on mac version 5 and higher, but I couldn't
1646 * find a reference for that... Since I see them from time to time
1647 * on my card, this suggests an error in the tx path still...
1648 */
1649 if (intr_status & BWI_INTR_PHY_TXERR) {
1650 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1651 if_printf(ifp, "%s: intr PHY TX error\n", __func__);
1652 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1653 BWI_UNLOCK(sc);
1654 return;
1655 }
1656 }
1657
1658 if (txrx_error) {
1659 /* TODO: reset device */
1660 }
1661
1662 if (intr_status & BWI_INTR_TBTT)
1663 bwi_mac_config_ps(mac);
1664
1665 if (intr_status & BWI_INTR_EO_ATIM)
1666 if_printf(ifp, "EO_ATIM\n");
1667
1668 if (intr_status & BWI_INTR_PMQ) {
1669 for (;;) {
1670 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1671 break;
1672 }
1673 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1674 }
1675
1676 if (intr_status & BWI_INTR_NOISE)
1677 if_printf(ifp, "intr noise\n");
1678
1679 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) {
1680 rx_data = sc->sc_rxeof(sc);
1681 if (sc->sc_flags & BWI_F_STOP) {
1682 BWI_UNLOCK(sc);
1683 return;
1684 }
1685 }
1686
1687 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1688 sc->sc_txeof_status(sc);
1689 tx = 1;
1690 }
1691
1692 if (intr_status & BWI_INTR_TX_DONE) {
1693 bwi_txeof(sc);
1694 tx = 1;
1695 }
1696
1697 /* Re-enable interrupts */
1698 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1699
1700 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1701 int evt = BWI_LED_EVENT_NONE;
1702
1703 if (tx && rx_data > 0) {
1704 if (sc->sc_rx_rate > sc->sc_tx_rate)
1705 evt = BWI_LED_EVENT_RX;
1706 else
1707 evt = BWI_LED_EVENT_TX;
1708 } else if (tx) {
1709 evt = BWI_LED_EVENT_TX;
1710 } else if (rx_data > 0) {
1711 evt = BWI_LED_EVENT_RX;
1712 } else if (rx_data == 0) {
1713 evt = BWI_LED_EVENT_POLL;
1714 }
1715
1716 if (evt != BWI_LED_EVENT_NONE)
1717 bwi_led_event(sc, evt);
1718 }
1719
1720 BWI_UNLOCK(sc);
1721 }
1722
1723 static void
1724 bwi_scan_start(struct ieee80211com *ic)
1725 {
1726 struct bwi_softc *sc = ic->ic_ifp->if_softc;
1727
1728 BWI_LOCK(sc);
1729 /* Enable MAC beacon promiscuity */
1730 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1731 BWI_UNLOCK(sc);
1732 }
1733
1734 static void
1735 bwi_set_channel(struct ieee80211com *ic)
1736 {
1737 struct bwi_softc *sc = ic->ic_ifp->if_softc;
1738 struct ieee80211_channel *c = ic->ic_curchan;
1739 struct bwi_mac *mac;
1740
1741 BWI_LOCK(sc);
1742 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1743 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1744 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1745 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0);
1746
1747 sc->sc_rates = ieee80211_get_ratetable(c);
1748
1749 /*
1750 * Setup radio tap channel freq and flags
1751 */
1752 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
1753 htole16(c->ic_freq);
1754 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
1755 htole16(c->ic_flags & 0xffff);
1756
1757 BWI_UNLOCK(sc);
1758 }
1759
1760 static void
1761 bwi_scan_end(struct ieee80211com *ic)
1762 {
1763 struct bwi_softc *sc = ic->ic_ifp->if_softc;
1764
1765 BWI_LOCK(sc);
1766 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1767 BWI_UNLOCK(sc);
1768 }
1769
1770 static int
1771 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1772 {
1773 struct bwi_vap *bvp = BWI_VAP(vap);
1774 struct ieee80211com *ic= vap->iv_ic;
1775 struct ifnet *ifp = ic->ic_ifp;
1776 enum ieee80211_state ostate = vap->iv_state;
1777 struct bwi_softc *sc = ifp->if_softc;
1778 struct bwi_mac *mac;
1779 struct ieee80211_node *ni = vap->iv_bss;
1780 int error;
1781
1782 BWI_LOCK(sc);
1783
1784 callout_stop(&sc->sc_calib_ch);
1785
1786 if (nstate == IEEE80211_S_INIT)
1787 sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1788
1789 bwi_led_newstate(sc, nstate);
1790
1791 error = bvp->bv_newstate(vap, nstate, arg);
1792 if (error != 0)
1793 goto back;
1794
1795 /*
1796 * Clear the BSSID when we stop a STA
1797 */
1798 if (vap->iv_opmode == IEEE80211_M_STA) {
1799 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) {
1800 /*
1801 * Clear out the BSSID. If we reassociate to
1802 * the same AP, this will reinialize things
1803 * correctly...
1804 */
1805 if (ic->ic_opmode == IEEE80211_M_STA &&
1806 !(sc->sc_flags & BWI_F_STOP))
1807 bwi_set_bssid(sc, bwi_zero_addr);
1808 }
1809 }
1810
1811 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
1812 /* Nothing to do */
1813 } else if (nstate == IEEE80211_S_RUN) {
1814 bwi_set_bssid(sc, vap->iv_bss->ni_bssid);
1815
1816 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1817 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1818 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1819
1820 /* Initial TX power calibration */
1821 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1822 #ifdef notyet
1823 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1824 #else
1825 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1826 #endif
1827 if (vap->iv_opmode == IEEE80211_M_STA) {
1828 /* fake a join to init the tx rate */
1829 bwi_newassoc(ni, 1);
1830 }
1831
1832 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
1833 }
1834 back:
1835 BWI_UNLOCK(sc);
1836
1837 return error;
1838 }
1839
1840 /* ARGUSED */
1841 static struct ieee80211_node *
1842 bwi_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
1843 {
1844 struct bwi_node *bn;
1845
1846 bn = malloc(sizeof(struct bwi_node), M_80211_NODE, M_NOWAIT | M_ZERO);
1847 return bn != NULL ? &bn->ni : NULL;
1848 }
1849
1850 static void
1851 bwi_newassoc(struct ieee80211_node *ni, int isnew)
1852 {
1853 struct ieee80211vap *vap = ni->ni_vap;
1854
1855 ieee80211_amrr_node_init(&BWI_VAP(vap)->bv_amrr,
1856 &BWI_NODE(ni)->amn, ni);
1857 }
1858
1859 static int
1860 bwi_media_change(struct ifnet *ifp)
1861 {
1862 int error = ieee80211_media_change(ifp);
1863 /* NB: only the fixed rate can change and that doesn't need a reset */
1864 return (error == ENETRESET ? 0 : error);
1865 }
1866
1867 static int
1868 bwi_dma_alloc(struct bwi_softc *sc)
1869 {
1870 int error, i, has_txstats;
1871 bus_addr_t lowaddr = 0;
1872 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1873 uint32_t txrx_ctrl_step = 0;
1874
1875 has_txstats = 0;
1876 for (i = 0; i < sc->sc_nmac; ++i) {
1877 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1878 has_txstats = 1;
1879 break;
1880 }
1881 }
1882
1883 switch (sc->sc_bus_space) {
1884 case BWI_BUS_SPACE_30BIT:
1885 case BWI_BUS_SPACE_32BIT:
1886 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1887 lowaddr = BWI_BUS_SPACE_MAXADDR;
1888 else
1889 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1890 desc_sz = sizeof(struct bwi_desc32);
1891 txrx_ctrl_step = 0x20;
1892
1893 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1894 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1895 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1896 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1897 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1898 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1899 sc->sc_rxeof = bwi_rxeof32;
1900 sc->sc_start_tx = bwi_start_tx32;
1901 if (has_txstats) {
1902 sc->sc_init_txstats = bwi_init_txstats32;
1903 sc->sc_free_txstats = bwi_free_txstats32;
1904 sc->sc_txeof_status = bwi_txeof_status32;
1905 }
1906 break;
1907
1908 case BWI_BUS_SPACE_64BIT:
1909 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
1910 desc_sz = sizeof(struct bwi_desc64);
1911 txrx_ctrl_step = 0x40;
1912
1913 sc->sc_init_tx_ring = bwi_init_tx_ring64;
1914 sc->sc_free_tx_ring = bwi_free_tx_ring64;
1915 sc->sc_init_rx_ring = bwi_init_rx_ring64;
1916 sc->sc_free_rx_ring = bwi_free_rx_ring64;
1917 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1918 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1919 sc->sc_rxeof = bwi_rxeof64;
1920 sc->sc_start_tx = bwi_start_tx64;
1921 if (has_txstats) {
1922 sc->sc_init_txstats = bwi_init_txstats64;
1923 sc->sc_free_txstats = bwi_free_txstats64;
1924 sc->sc_txeof_status = bwi_txeof_status64;
1925 }
1926 break;
1927 }
1928
1929 KASSERT(lowaddr != 0, ("lowaddr zero"));
1930 KASSERT(desc_sz != 0, ("desc_sz zero"));
1931 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero"));
1932
1933 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
1934 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
1935
1936 /*
1937 * Create top level DMA tag
1938 */
1939 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
1940 BWI_ALIGN, 0, /* alignment, bounds */
1941 lowaddr, /* lowaddr */
1942 BUS_SPACE_MAXADDR, /* highaddr */
1943 NULL, NULL, /* filter, filterarg */
1944 MAXBSIZE, /* maxsize */
1945 BUS_SPACE_UNRESTRICTED, /* nsegments */
1946 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1947 BUS_DMA_ALLOCNOW, /* flags */
1948 NULL, NULL, /* lockfunc, lockarg */
1949 &sc->sc_parent_dtag);
1950 if (error) {
1951 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
1952 return error;
1953 }
1954
1955 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
1956
1957 /*
1958 * Create TX ring DMA stuffs
1959 */
1960 error = bus_dma_tag_create(sc->sc_parent_dtag,
1961 BWI_RING_ALIGN, 0,
1962 BUS_SPACE_MAXADDR,
1963 BUS_SPACE_MAXADDR,
1964 NULL, NULL,
1965 tx_ring_sz,
1966 1,
1967 BUS_SPACE_MAXSIZE_32BIT,
1968 BUS_DMA_ALLOCNOW,
1969 NULL, NULL,
1970 &sc->sc_txring_dtag);
1971 if (error) {
1972 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
1973 return error;
1974 }
1975
1976 for (i = 0; i < BWI_TX_NRING; ++i) {
1977 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
1978 &sc->sc_tx_rdata[i], tx_ring_sz,
1979 TXRX_CTRL(i));
1980 if (error) {
1981 device_printf(sc->sc_dev, "%dth TX ring "
1982 "DMA alloc failed\n", i);
1983 return error;
1984 }
1985 }
1986
1987 /*
1988 * Create RX ring DMA stuffs
1989 */
1990 error = bus_dma_tag_create(sc->sc_parent_dtag,
1991 BWI_RING_ALIGN, 0,
1992 BUS_SPACE_MAXADDR,
1993 BUS_SPACE_MAXADDR,
1994 NULL, NULL,
1995 rx_ring_sz,
1996 1,
1997 BUS_SPACE_MAXSIZE_32BIT,
1998 BUS_DMA_ALLOCNOW,
1999 NULL, NULL,
2000 &sc->sc_rxring_dtag);
2001 if (error) {
2002 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
2003 return error;
2004 }
2005
2006 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
2007 rx_ring_sz, TXRX_CTRL(0));
2008 if (error) {
2009 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
2010 return error;
2011 }
2012
2013 if (has_txstats) {
2014 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
2015 if (error) {
2016 device_printf(sc->sc_dev,
2017 "TX stats DMA alloc failed\n");
2018 return error;
2019 }
2020 }
2021
2022 #undef TXRX_CTRL
2023
2024 return bwi_dma_mbuf_create(sc);
2025 }
2026
2027 static void
2028 bwi_dma_free(struct bwi_softc *sc)
2029 {
2030 if (sc->sc_txring_dtag != NULL) {
2031 int i;
2032
2033 for (i = 0; i < BWI_TX_NRING; ++i) {
2034 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
2035
2036 if (rd->rdata_desc != NULL) {
2037 bus_dmamap_unload(sc->sc_txring_dtag,
2038 rd->rdata_dmap);
2039 bus_dmamem_free(sc->sc_txring_dtag,
2040 rd->rdata_desc,
2041 rd->rdata_dmap);
2042 }
2043 }
2044 bus_dma_tag_destroy(sc->sc_txring_dtag);
2045 }
2046
2047 if (sc->sc_rxring_dtag != NULL) {
2048 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2049
2050 if (rd->rdata_desc != NULL) {
2051 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2052 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2053 rd->rdata_dmap);
2054 }
2055 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2056 }
2057
2058 bwi_dma_txstats_free(sc);
2059 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2060
2061 if (sc->sc_parent_dtag != NULL)
2062 bus_dma_tag_destroy(sc->sc_parent_dtag);
2063 }
2064
2065 static int
2066 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2067 struct bwi_ring_data *rd, bus_size_t size,
2068 uint32_t txrx_ctrl)
2069 {
2070 int error;
2071
2072 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2073 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2074 &rd->rdata_dmap);
2075 if (error) {
2076 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2077 return error;
2078 }
2079
2080 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2081 bwi_dma_ring_addr, &rd->rdata_paddr,
2082 BUS_DMA_NOWAIT);
2083 if (error) {
2084 device_printf(sc->sc_dev, "can't load DMA mem\n");
2085 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2086 rd->rdata_desc = NULL;
2087 return error;
2088 }
2089
2090 rd->rdata_txrx_ctrl = txrx_ctrl;
2091 return 0;
2092 }
2093
2094 static int
2095 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2096 bus_size_t desc_sz)
2097 {
2098 struct bwi_txstats_data *st;
2099 bus_size_t dma_size;
2100 int error;
2101
2102 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO);
2103 if (st == NULL) {
2104 device_printf(sc->sc_dev, "can't allocate txstats data\n");
2105 return ENOMEM;
2106 }
2107 sc->sc_txstats = st;
2108
2109 /*
2110 * Create TX stats descriptor DMA stuffs
2111 */
2112 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2113
2114 error = bus_dma_tag_create(sc->sc_parent_dtag,
2115 BWI_RING_ALIGN,
2116 0,
2117 BUS_SPACE_MAXADDR,
2118 BUS_SPACE_MAXADDR,
2119 NULL, NULL,
2120 dma_size,
2121 1,
2122 BUS_SPACE_MAXSIZE_32BIT,
2123 BUS_DMA_ALLOCNOW,
2124 NULL, NULL,
2125 &st->stats_ring_dtag);
2126 if (error) {
2127 device_printf(sc->sc_dev, "can't create txstats ring "
2128 "DMA tag\n");
2129 return error;
2130 }
2131
2132 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2133 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2134 &st->stats_ring_dmap);
2135 if (error) {
2136 device_printf(sc->sc_dev, "can't allocate txstats ring "
2137 "DMA mem\n");
2138 bus_dma_tag_destroy(st->stats_ring_dtag);
2139 st->stats_ring_dtag = NULL;
2140 return error;
2141 }
2142
2143 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2144 st->stats_ring, dma_size,
2145 bwi_dma_ring_addr, &st->stats_ring_paddr,
2146 BUS_DMA_NOWAIT);
2147 if (error) {
2148 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2149 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2150 st->stats_ring_dmap);
2151 bus_dma_tag_destroy(st->stats_ring_dtag);
2152 st->stats_ring_dtag = NULL;
2153 return error;
2154 }
2155
2156 /*
2157 * Create TX stats DMA stuffs
2158 */
2159 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2160 BWI_ALIGN);
2161
2162 error = bus_dma_tag_create(sc->sc_parent_dtag,
2163 BWI_ALIGN,
2164 0,
2165 BUS_SPACE_MAXADDR,
2166 BUS_SPACE_MAXADDR,
2167 NULL, NULL,
2168 dma_size,
2169 1,
2170 BUS_SPACE_MAXSIZE_32BIT,
2171 BUS_DMA_ALLOCNOW,
2172 NULL, NULL,
2173 &st->stats_dtag);
2174 if (error) {
2175 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2176 return error;
2177 }
2178
2179 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2180 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2181 &st->stats_dmap);
2182 if (error) {
2183 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2184 bus_dma_tag_destroy(st->stats_dtag);
2185 st->stats_dtag = NULL;
2186 return error;
2187 }
2188
2189 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2190 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2191 BUS_DMA_NOWAIT);
2192 if (error) {
2193 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2194 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2195 bus_dma_tag_destroy(st->stats_dtag);
2196 st->stats_dtag = NULL;
2197 return error;
2198 }
2199
2200 st->stats_ctrl_base = ctrl_base;
2201 return 0;
2202 }
2203
2204 static void
2205 bwi_dma_txstats_free(struct bwi_softc *sc)
2206 {
2207 struct bwi_txstats_data *st;
2208
2209 if (sc->sc_txstats == NULL)
2210 return;
2211 st = sc->sc_txstats;
2212
2213 if (st->stats_ring_dtag != NULL) {
2214 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2215 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2216 st->stats_ring_dmap);
2217 bus_dma_tag_destroy(st->stats_ring_dtag);
2218 }
2219
2220 if (st->stats_dtag != NULL) {
2221 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2222 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2223 bus_dma_tag_destroy(st->stats_dtag);
2224 }
2225
2226 free(st, M_DEVBUF);
2227 }
2228
2229 static void
2230 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2231 {
2232 KASSERT(nseg == 1, ("too many segments\n"));
2233 *((bus_addr_t *)arg) = seg->ds_addr;
2234 }
2235
2236 static int
2237 bwi_dma_mbuf_create(struct bwi_softc *sc)
2238 {
2239 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2240 int i, j, k, ntx, error;
2241
2242 /*
2243 * Create TX/RX mbuf DMA tag
2244 */
2245 error = bus_dma_tag_create(sc->sc_parent_dtag,
2246 1,
2247 0,
2248 BUS_SPACE_MAXADDR,
2249 BUS_SPACE_MAXADDR,
2250 NULL, NULL,
2251 MCLBYTES,
2252 1,
2253 BUS_SPACE_MAXSIZE_32BIT,
2254 BUS_DMA_ALLOCNOW,
2255 NULL, NULL,
2256 &sc->sc_buf_dtag);
2257 if (error) {
2258 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2259 return error;
2260 }
2261
2262 ntx = 0;
2263
2264 /*
2265 * Create TX mbuf DMA map
2266 */
2267 for (i = 0; i < BWI_TX_NRING; ++i) {
2268 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2269
2270 for (j = 0; j < BWI_TX_NDESC; ++j) {
2271 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2272 &tbd->tbd_buf[j].tb_dmap);
2273 if (error) {
2274 device_printf(sc->sc_dev, "can't create "
2275 "%dth tbd, %dth DMA map\n", i, j);
2276
2277 ntx = i;
2278 for (k = 0; k < j; ++k) {
2279 bus_dmamap_destroy(sc->sc_buf_dtag,
2280 tbd->tbd_buf[k].tb_dmap);
2281 }
2282 goto fail;
2283 }
2284 }
2285 }
2286 ntx = BWI_TX_NRING;
2287
2288 /*
2289 * Create RX mbuf DMA map and a spare DMA map
2290 */
2291 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2292 &rbd->rbd_tmp_dmap);
2293 if (error) {
2294 device_printf(sc->sc_dev,
2295 "can't create spare RX buf DMA map\n");
2296 goto fail;
2297 }
2298
2299 for (j = 0; j < BWI_RX_NDESC; ++j) {
2300 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2301 &rbd->rbd_buf[j].rb_dmap);
2302 if (error) {
2303 device_printf(sc->sc_dev, "can't create %dth "
2304 "RX buf DMA map\n", j);
2305
2306 for (k = 0; k < j; ++k) {
2307 bus_dmamap_destroy(sc->sc_buf_dtag,
2308 rbd->rbd_buf[j].rb_dmap);
2309 }
2310 bus_dmamap_destroy(sc->sc_buf_dtag,
2311 rbd->rbd_tmp_dmap);
2312 goto fail;
2313 }
2314 }
2315
2316 return 0;
2317 fail:
2318 bwi_dma_mbuf_destroy(sc, ntx, 0);
2319 return error;
2320 }
2321
2322 static void
2323 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2324 {
2325 int i, j;
2326
2327 if (sc->sc_buf_dtag == NULL)
2328 return;
2329
2330 for (i = 0; i < ntx; ++i) {
2331 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2332
2333 for (j = 0; j < BWI_TX_NDESC; ++j) {
2334 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2335
2336 if (tb->tb_mbuf != NULL) {
2337 bus_dmamap_unload(sc->sc_buf_dtag,
2338 tb->tb_dmap);
2339 m_freem(tb->tb_mbuf);
2340 }
2341 if (tb->tb_ni != NULL)
2342 ieee80211_free_node(tb->tb_ni);
2343 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2344 }
2345 }
2346
2347 if (nrx) {
2348 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2349
2350 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2351 for (j = 0; j < BWI_RX_NDESC; ++j) {
2352 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2353
2354 if (rb->rb_mbuf != NULL) {
2355 bus_dmamap_unload(sc->sc_buf_dtag,
2356 rb->rb_dmap);
2357 m_freem(rb->rb_mbuf);
2358 }
2359 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2360 }
2361 }
2362
2363 bus_dma_tag_destroy(sc->sc_buf_dtag);
2364 sc->sc_buf_dtag = NULL;
2365 }
2366
2367 static void
2368 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2369 {
2370 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2371 }
2372
2373 static void
2374 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2375 {
2376 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2377 }
2378
2379 static int
2380 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2381 {
2382 struct bwi_ring_data *rd;
2383 struct bwi_txbuf_data *tbd;
2384 uint32_t val, addr_hi, addr_lo;
2385
2386 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2387 rd = &sc->sc_tx_rdata[ring_idx];
2388 tbd = &sc->sc_tx_bdata[ring_idx];
2389
2390 tbd->tbd_idx = 0;
2391 tbd->tbd_used = 0;
2392
2393 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2394 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2395 BUS_DMASYNC_PREWRITE);
2396
2397 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2398 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2399
2400 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2401 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2402 BWI_TXRX32_RINGINFO_FUNC_MASK);
2403 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2404
2405 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2406 BWI_TXRX32_CTRL_ENABLE;
2407 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2408
2409 return 0;
2410 }
2411
2412 static void
2413 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2414 bus_addr_t paddr, int hdr_size, int ndesc)
2415 {
2416 uint32_t val, addr_hi, addr_lo;
2417
2418 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2419 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2420
2421 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2422 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2423 BWI_TXRX32_RINGINFO_FUNC_MASK);
2424 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2425
2426 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2427 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2428 BWI_TXRX32_CTRL_ENABLE;
2429 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2430
2431 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2432 (ndesc - 1) * sizeof(struct bwi_desc32));
2433 }
2434
2435 static int
2436 bwi_init_rx_ring32(struct bwi_softc *sc)
2437 {
2438 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2439 int i, error;
2440
2441 sc->sc_rx_bdata.rbd_idx = 0;
2442
2443 for (i = 0; i < BWI_RX_NDESC; ++i) {
2444 error = bwi_newbuf(sc, i, 1);
2445 if (error) {
2446 device_printf(sc->sc_dev,
2447 "can't allocate %dth RX buffer\n", i);
2448 return error;
2449 }
2450 }
2451 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2452 BUS_DMASYNC_PREWRITE);
2453
2454 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2455 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2456 return 0;
2457 }
2458
2459 static int
2460 bwi_init_txstats32(struct bwi_softc *sc)
2461 {
2462 struct bwi_txstats_data *st = sc->sc_txstats;
2463 bus_addr_t stats_paddr;
2464 int i;
2465
2466 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2467 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2468
2469 st->stats_idx = 0;
2470
2471 stats_paddr = st->stats_paddr;
2472 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2473 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2474 stats_paddr, sizeof(struct bwi_txstats), 0);
2475 stats_paddr += sizeof(struct bwi_txstats);
2476 }
2477 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2478 BUS_DMASYNC_PREWRITE);
2479
2480 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2481 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2482 return 0;
2483 }
2484
2485 static void
2486 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2487 int buf_len)
2488 {
2489 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2490
2491 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2492 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2493 paddr, buf_len, 0);
2494 }
2495
2496 static void
2497 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2498 int buf_idx, bus_addr_t paddr, int buf_len)
2499 {
2500 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
2501 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2502 paddr, buf_len, 1);
2503 }
2504
2505 static int
2506 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2507 {
2508 /* TODO:64 */
2509 return EOPNOTSUPP;
2510 }
2511
2512 static int
2513 bwi_init_rx_ring64(struct bwi_softc *sc)
2514 {
2515 /* TODO:64 */
2516 return EOPNOTSUPP;
2517 }
2518
2519 static int
2520 bwi_init_txstats64(struct bwi_softc *sc)
2521 {
2522 /* TODO:64 */
2523 return EOPNOTSUPP;
2524 }
2525
2526 static void
2527 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2528 int buf_len)
2529 {
2530 /* TODO:64 */
2531 }
2532
2533 static void
2534 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2535 int buf_idx, bus_addr_t paddr, int buf_len)
2536 {
2537 /* TODO:64 */
2538 }
2539
2540 static void
2541 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2542 bus_size_t mapsz __unused, int error)
2543 {
2544 if (!error) {
2545 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2546 *((bus_addr_t *)arg) = seg->ds_addr;
2547 }
2548 }
2549
2550 static int
2551 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2552 {
2553 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2554 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2555 struct bwi_rxbuf_hdr *hdr;
2556 bus_dmamap_t map;
2557 bus_addr_t paddr;
2558 struct mbuf *m;
2559 int error;
2560
2561 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2562
2563 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2564 if (m == NULL) {
2565 error = ENOBUFS;
2566
2567 /*
2568 * If the NIC is up and running, we need to:
2569 * - Clear RX buffer's header.
2570 * - Restore RX descriptor settings.
2571 */
2572 if (init)
2573 return error;
2574 else
2575 goto back;
2576 }
2577 m->m_len = m->m_pkthdr.len = MCLBYTES;
2578
2579 /*
2580 * Try to load RX buf into temporary DMA map
2581 */
2582 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2583 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
2584 if (error) {
2585 m_freem(m);
2586
2587 /*
2588 * See the comment above
2589 */
2590 if (init)
2591 return error;
2592 else
2593 goto back;
2594 }
2595
2596 if (!init)
2597 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2598 rxbuf->rb_mbuf = m;
2599 rxbuf->rb_paddr = paddr;
2600
2601 /*
2602 * Swap RX buf's DMA map with the loaded temporary one
2603 */
2604 map = rxbuf->rb_dmap;
2605 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2606 rbd->rbd_tmp_dmap = map;
2607
2608 back:
2609 /*
2610 * Clear RX buf header
2611 */
2612 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2613 bzero(hdr, sizeof(*hdr));
2614 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2615
2616 /*
2617 * Setup RX buf descriptor
2618 */
2619 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2620 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2621 return error;
2622 }
2623
2624 static void
2625 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2626 const uint8_t *addr)
2627 {
2628 int i;
2629
2630 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2631 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2632
2633 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2634 uint16_t addr_val;
2635
2636 addr_val = (uint16_t)addr[i * 2] |
2637 (((uint16_t)addr[(i * 2) + 1]) << 8);
2638 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2639 }
2640 }
2641
2642 static int
2643 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2644 {
2645 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2646 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2647 struct ifnet *ifp = sc->sc_ifp;
2648 struct ieee80211com *ic = ifp->if_l2com;
2649 int idx, rx_data = 0;
2650
2651 idx = rbd->rbd_idx;
2652 while (idx != end_idx) {
2653 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2654 struct bwi_rxbuf_hdr *hdr;
2655 struct ieee80211_frame_min *wh;
2656 struct ieee80211_node *ni;
2657 struct mbuf *m;
2658 const void *plcp;
2659 uint16_t flags2;
2660 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate;
2661
2662 m = rb->rb_mbuf;
2663 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2664 BUS_DMASYNC_POSTREAD);
2665
2666 if (bwi_newbuf(sc, idx, 0)) {
2667 ifp->if_ierrors++;
2668 goto next;
2669 }
2670
2671 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2672 flags2 = le16toh(hdr->rxh_flags2);
2673
2674 hdr_extra = 0;
2675 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2676 hdr_extra = 2;
2677 wh_ofs = hdr_extra + 6; /* XXX magic number */
2678
2679 buflen = le16toh(hdr->rxh_buflen);
2680 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2681 if_printf(ifp, "%s: zero length data, hdr_extra %d\n",
2682 __func__, hdr_extra);
2683 ifp->if_ierrors++;
2684 m_freem(m);
2685 goto next;
2686 }
2687
2688 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra);
2689 rssi = bwi_calc_rssi(sc, hdr);
2690 noise = bwi_calc_noise(sc);
2691
2692 m->m_pkthdr.rcvif = ifp;
2693 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2694 m_adj(m, sizeof(*hdr) + wh_ofs);
2695
2696 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2697 rate = bwi_ofdm_plcp2rate(plcp);
2698 else
2699 rate = bwi_ds_plcp2rate(plcp);
2700
2701 /* RX radio tap */
2702 if (ieee80211_radiotap_active(ic))
2703 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi, noise);
2704
2705 m_adj(m, -IEEE80211_CRC_LEN);
2706
2707 BWI_UNLOCK(sc);
2708
2709 wh = mtod(m, struct ieee80211_frame_min *);
2710 ni = ieee80211_find_rxnode(ic, wh);
2711 if (ni != NULL) {
2712 type = ieee80211_input(ni, m, rssi - noise, noise);
2713 ieee80211_free_node(ni);
2714 } else
2715 type = ieee80211_input_all(ic, m, rssi - noise, noise);
2716 if (type == IEEE80211_FC0_TYPE_DATA) {
2717 rx_data = 1;
2718 sc->sc_rx_rate = rate;
2719 }
2720
2721 BWI_LOCK(sc);
2722 next:
2723 idx = (idx + 1) % BWI_RX_NDESC;
2724
2725 if (sc->sc_flags & BWI_F_STOP) {
2726 /*
2727 * Take the fast lane, don't do
2728 * any damage to softc
2729 */
2730 return -1;
2731 }
2732 }
2733
2734 rbd->rbd_idx = idx;
2735 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2736 BUS_DMASYNC_PREWRITE);
2737
2738 return rx_data;
2739 }
2740
2741 static int
2742 bwi_rxeof32(struct bwi_softc *sc)
2743 {
2744 uint32_t val, rx_ctrl;
2745 int end_idx, rx_data;
2746
2747 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2748
2749 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2750 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2751 sizeof(struct bwi_desc32);
2752
2753 rx_data = bwi_rxeof(sc, end_idx);
2754 if (rx_data >= 0) {
2755 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2756 end_idx * sizeof(struct bwi_desc32));
2757 }
2758 return rx_data;
2759 }
2760
2761 static int
2762 bwi_rxeof64(struct bwi_softc *sc)
2763 {
2764 /* TODO:64 */
2765 return 0;
2766 }
2767
2768 static void
2769 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2770 {
2771 int i;
2772
2773 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2774
2775 #define NRETRY 10
2776
2777 for (i = 0; i < NRETRY; ++i) {
2778 uint32_t status;
2779
2780 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2781 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2782 BWI_RX32_STATUS_STATE_DISABLED)
2783 break;
2784
2785 DELAY(1000);
2786 }
2787 if (i == NRETRY)
2788 device_printf(sc->sc_dev, "reset rx ring timedout\n");
2789
2790 #undef NRETRY
2791
2792 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2793 }
2794
2795 static void
2796 bwi_free_txstats32(struct bwi_softc *sc)
2797 {
2798 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2799 }
2800
2801 static void
2802 bwi_free_rx_ring32(struct bwi_softc *sc)
2803 {
2804 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2805 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2806 int i;
2807
2808 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2809
2810 for (i = 0; i < BWI_RX_NDESC; ++i) {
2811 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2812
2813 if (rb->rb_mbuf != NULL) {
2814 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2815 m_freem(rb->rb_mbuf);
2816 rb->rb_mbuf = NULL;
2817 }
2818 }
2819 }
2820
2821 static void
2822 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2823 {
2824 struct bwi_ring_data *rd;
2825 struct bwi_txbuf_data *tbd;
2826 struct ifnet *ifp = sc->sc_ifp;
2827 uint32_t state, val;
2828 int i;
2829
2830 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2831 rd = &sc->sc_tx_rdata[ring_idx];
2832 tbd = &sc->sc_tx_bdata[ring_idx];
2833
2834 #define NRETRY 10
2835
2836 for (i = 0; i < NRETRY; ++i) {
2837 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2838 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2839 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2840 state == BWI_TX32_STATUS_STATE_IDLE ||
2841 state == BWI_TX32_STATUS_STATE_STOPPED)
2842 break;
2843
2844 DELAY(1000);
2845 }
2846 if (i == NRETRY) {
2847 if_printf(ifp, "%s: wait for TX ring(%d) stable timed out\n",
2848 __func__, ring_idx);
2849 }
2850
2851 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2852 for (i = 0; i < NRETRY; ++i) {
2853 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2854 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2855 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2856 break;
2857
2858 DELAY(1000);
2859 }
2860 if (i == NRETRY)
2861 if_printf(ifp, "%s: reset TX ring (%d) timed out\n",
2862 __func__, ring_idx);
2863
2864 #undef NRETRY
2865
2866 DELAY(1000);
2867
2868 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2869
2870 for (i = 0; i < BWI_TX_NDESC; ++i) {
2871 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2872
2873 if (tb->tb_mbuf != NULL) {
2874 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2875 m_freem(tb->tb_mbuf);
2876 tb->tb_mbuf = NULL;
2877 }
2878 if (tb->tb_ni != NULL) {
2879 ieee80211_free_node(tb->tb_ni);
2880 tb->tb_ni = NULL;
2881 }
2882 }
2883 }
2884
2885 static void
2886 bwi_free_txstats64(struct bwi_softc *sc)
2887 {
2888 /* TODO:64 */
2889 }
2890
2891 static void
2892 bwi_free_rx_ring64(struct bwi_softc *sc)
2893 {
2894 /* TODO:64 */
2895 }
2896
2897 static void
2898 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2899 {
2900 /* TODO:64 */
2901 }
2902
2903 /* XXX does not belong here */
2904 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
2905 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
2906
2907 static __inline void
2908 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
2909 {
2910 uint32_t plcp;
2911
2912 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM),
2913 IEEE80211_OFDM_PLCP_RATE_MASK) |
2914 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
2915 *plcp0 = htole32(plcp);
2916 }
2917
2918 static __inline void
2919 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
2920 uint8_t rate)
2921 {
2922 int len, service, pkt_bitlen;
2923
2924 pkt_bitlen = pkt_len * NBBY;
2925 len = howmany(pkt_bitlen * 2, rate);
2926
2927 service = IEEE80211_PLCP_SERVICE_LOCKED;
2928 if (rate == (11 * 2)) {
2929 int pkt_bitlen1;
2930
2931 /*
2932 * PLCP service field needs to be adjusted,
2933 * if TX rate is 11Mbytes/s
2934 */
2935 pkt_bitlen1 = len * 11;
2936 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
2937 service |= IEEE80211_PLCP_SERVICE_LENEXT7;
2938 }
2939
2940 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK);
2941 plcp->i_service = service;
2942 plcp->i_length = htole16(len);
2943 /* NOTE: do NOT touch i_crc */
2944 }
2945
2946 static __inline void
2947 bwi_plcp_header(const struct ieee80211_rate_table *rt,
2948 void *plcp, int pkt_len, uint8_t rate)
2949 {
2950 enum ieee80211_phytype modtype;
2951
2952 /*
2953 * Assume caller has zeroed 'plcp'
2954 */
2955 modtype = ieee80211_rate2phytype(rt, rate);
2956 if (modtype == IEEE80211_T_OFDM)
2957 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
2958 else if (modtype == IEEE80211_T_DS)
2959 bwi_ds_plcp_header(plcp, pkt_len, rate);
2960 else
2961 panic("unsupport modulation type %u\n", modtype);
2962 }
2963
2964 static int
2965 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2966 struct ieee80211_node *ni)
2967 {
2968 struct ieee80211vap *vap = ni->ni_vap;
2969 struct ifnet *ifp = sc->sc_ifp;
2970 struct ieee80211com *ic = ifp->if_l2com;
2971 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2972 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2973 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2974 struct bwi_mac *mac;
2975 struct bwi_txbuf_hdr *hdr;
2976 struct ieee80211_frame *wh;
2977 const struct ieee80211_txparam *tp;
2978 uint8_t rate, rate_fb;
2979 uint32_t mac_ctrl;
2980 uint16_t phy_ctrl;
2981 bus_addr_t paddr;
2982 int type, ismcast, pkt_len, error, rix;
2983 #if 0
2984 const uint8_t *p;
2985 int i;
2986 #endif
2987
2988 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
2989 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
2990 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2991
2992 wh = mtod(m, struct ieee80211_frame *);
2993 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2994 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
2995
2996 /* Get 802.11 frame len before prepending TX header */
2997 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2998
2999 /*
3000 * Find TX rate
3001 */
3002 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
3003 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) {
3004 rate = rate_fb = tp->mgmtrate;
3005 } else if (ismcast) {
3006 rate = rate_fb = tp->mcastrate;
3007 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
3008 rate = rate_fb = tp->ucastrate;
3009 } else {
3010 rix = ieee80211_amrr_choose(ni, &BWI_NODE(ni)->amn);
3011 rate = ni->ni_txrate;
3012
3013 if (rix > 0) {
3014 rate_fb = ni->ni_rates.rs_rates[rix-1] &
3015 IEEE80211_RATE_VAL;
3016 } else {
3017 rate_fb = rate;
3018 }
3019 }
3020 tb->tb_rate[0] = rate;
3021 tb->tb_rate[1] = rate_fb;
3022 sc->sc_tx_rate = rate;
3023
3024 /*
3025 * TX radio tap
3026 */
3027 if (ieee80211_radiotap_active_vap(vap)) {
3028 sc->sc_tx_th.wt_flags = 0;
3029 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3030 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3031 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS &&
3032 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3033 rate != (1 * 2)) {
3034 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3035 }
3036 sc->sc_tx_th.wt_rate = rate;
3037
3038 ieee80211_radiotap_tx(vap, m);
3039 }
3040
3041 /*
3042 * Setup the embedded TX header
3043 */
3044 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT);
3045 if (m == NULL) {
3046 if_printf(ifp, "%s: prepend TX header failed\n", __func__);
3047 return ENOBUFS;
3048 }
3049 hdr = mtod(m, struct bwi_txbuf_hdr *);
3050
3051 bzero(hdr, sizeof(*hdr));
3052
3053 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3054 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3055
3056 if (!ismcast) {
3057 uint16_t dur;
3058
3059 dur = ieee80211_ack_duration(sc->sc_rates, rate,
3060 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
3061
3062 hdr->txh_fb_duration = htole16(dur);
3063 }
3064
3065 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3066 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3067
3068 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3069 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3070
3071 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3072 BWI_TXH_PHY_C_ANTMODE_MASK);
3073 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM)
3074 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3075 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3076 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3077
3078 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3079 if (!ismcast)
3080 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3081 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM)
3082 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3083
3084 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3085 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3086
3087 /* Catch any further usage */
3088 hdr = NULL;
3089 wh = NULL;
3090
3091 /* DMA load */
3092 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3093 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3094 if (error && error != EFBIG) {
3095 if_printf(ifp, "%s: can't load TX buffer (1) %d\n",
3096 __func__, error);
3097 goto back;
3098 }
3099
3100 if (error) { /* error == EFBIG */
3101 struct mbuf *m_new;
3102
3103 m_new = m_defrag(m, M_DONTWAIT);
3104 if (m_new == NULL) {
3105 if_printf(ifp, "%s: can't defrag TX buffer\n",
3106 __func__);
3107 error = ENOBUFS;
3108 goto back;
3109 } else {
3110 m = m_new;
3111 }
3112
3113 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3114 bwi_dma_buf_addr, &paddr,
3115 BUS_DMA_NOWAIT);
3116 if (error) {
3117 if_printf(ifp, "%s: can't load TX buffer (2) %d\n",
3118 __func__, error);
3119 goto back;
3120 }
3121 }
3122 error = 0;
3123
3124 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3125
3126 tb->tb_mbuf = m;
3127 tb->tb_ni = ni;
3128
3129 #if 0
3130 p = mtod(m, const uint8_t *);
3131 for (i = 0; i < m->m_pkthdr.len; ++i) {
3132 if (i != 0 && i % 8 == 0)
3133 printf("\n");
3134 printf("%02x ", p[i]);
3135 }
3136 printf("\n");
3137 #endif
3138 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3139 idx, pkt_len, m->m_pkthdr.len);
3140
3141 /* Setup TX descriptor */
3142 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3143 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3144 BUS_DMASYNC_PREWRITE);
3145
3146 /* Kick start */
3147 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3148
3149 back:
3150 if (error)
3151 m_freem(m);
3152 return error;
3153 }
3154
3155 static int
3156 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m,
3157 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
3158 {
3159 struct ifnet *ifp = sc->sc_ifp;
3160 struct ieee80211vap *vap = ni->ni_vap;
3161 struct ieee80211com *ic = ni->ni_ic;
3162 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
3163 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
3164 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3165 struct bwi_mac *mac;
3166 struct bwi_txbuf_hdr *hdr;
3167 struct ieee80211_frame *wh;
3168 uint8_t rate, rate_fb;
3169 uint32_t mac_ctrl;
3170 uint16_t phy_ctrl;
3171 bus_addr_t paddr;
3172 int ismcast, pkt_len, error;
3173
3174 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3175 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3176 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3177
3178 wh = mtod(m, struct ieee80211_frame *);
3179 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3180
3181 /* Get 802.11 frame len before prepending TX header */
3182 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3183
3184 /*
3185 * Find TX rate
3186 */
3187 rate = params->ibp_rate0;
3188 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
3189 /* XXX fall back to mcast/mgmt rate? */
3190 m_freem(m);
3191 return EINVAL;
3192 }
3193 if (params->ibp_try1 != 0) {
3194 rate_fb = params->ibp_rate1;
3195 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) {
3196 /* XXX fall back to rate0? */
3197 m_freem(m);
3198 return EINVAL;
3199 }
3200 } else
3201 rate_fb = rate;
3202 tb->tb_rate[0] = rate;
3203 tb->tb_rate[1] = rate_fb;
3204 sc->sc_tx_rate = rate;
3205
3206 /*
3207 * TX radio tap
3208 */
3209 if (ieee80211_radiotap_active_vap(vap)) {
3210 sc->sc_tx_th.wt_flags = 0;
3211 /* XXX IEEE80211_BPF_CRYPTO */
3212 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3213 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3214 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3215 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3216 sc->sc_tx_th.wt_rate = rate;
3217
3218 ieee80211_radiotap_tx(vap, m);
3219 }
3220
3221 /*
3222 * Setup the embedded TX header
3223 */
3224 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT);
3225 if (m == NULL) {
3226 if_printf(ifp, "%s: prepend TX header failed\n", __func__);
3227 return ENOBUFS;
3228 }
3229 hdr = mtod(m, struct bwi_txbuf_hdr *);
3230
3231 bzero(hdr, sizeof(*hdr));
3232
3233 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3234 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3235
3236 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3237 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
3238 uint16_t dur;
3239
3240 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0);
3241
3242 hdr->txh_fb_duration = htole16(dur);
3243 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3244 }
3245
3246 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3247 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3248
3249 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3250 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3251
3252 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3253 BWI_TXH_PHY_C_ANTMODE_MASK);
3254 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) {
3255 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3256 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3257 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3258 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3259
3260 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3261 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3262
3263 /* Catch any further usage */
3264 hdr = NULL;
3265 wh = NULL;
3266
3267 /* DMA load */
3268 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3269 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3270 if (error != 0) {
3271 struct mbuf *m_new;
3272
3273 if (error != EFBIG) {
3274 if_printf(ifp, "%s: can't load TX buffer (1) %d\n",
3275 __func__, error);
3276 goto back;
3277 }
3278 m_new = m_defrag(m, M_DONTWAIT);
3279 if (m_new == NULL) {
3280 if_printf(ifp, "%s: can't defrag TX buffer\n",
3281 __func__);
3282 error = ENOBUFS;
3283 goto back;
3284 }
3285 m = m_new;
3286 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3287 bwi_dma_buf_addr, &paddr,
3288 BUS_DMA_NOWAIT);
3289 if (error) {
3290 if_printf(ifp, "%s: can't load TX buffer (2) %d\n",
3291 __func__, error);
3292 goto back;
3293 }
3294 }
3295
3296 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3297
3298 tb->tb_mbuf = m;
3299 tb->tb_ni = ni;
3300
3301 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3302 idx, pkt_len, m->m_pkthdr.len);
3303
3304 /* Setup TX descriptor */
3305 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3306 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3307 BUS_DMASYNC_PREWRITE);
3308
3309 /* Kick start */
3310 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3311 back:
3312 if (error)
3313 m_freem(m);
3314 return error;
3315 }
3316
3317 static void
3318 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3319 {
3320 idx = (idx + 1) % BWI_TX_NDESC;
3321 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3322 idx * sizeof(struct bwi_desc32));
3323 }
3324
3325 static void
3326 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3327 {
3328 /* TODO:64 */
3329 }
3330
3331 static void
3332 bwi_txeof_status32(struct bwi_softc *sc)
3333 {
3334 struct ifnet *ifp = sc->sc_ifp;
3335 uint32_t val, ctrl_base;
3336 int end_idx;
3337
3338 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3339
3340 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3341 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3342 sizeof(struct bwi_desc32);
3343
3344 bwi_txeof_status(sc, end_idx);
3345
3346 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3347 end_idx * sizeof(struct bwi_desc32));
3348
3349 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0)
3350 ifp->if_start(ifp);
3351 }
3352
3353 static void
3354 bwi_txeof_status64(struct bwi_softc *sc)
3355 {
3356 /* TODO:64 */
3357 }
3358
3359 static void
3360 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3361 {
3362 struct ifnet *ifp = sc->sc_ifp;
3363 struct bwi_txbuf_data *tbd;
3364 struct bwi_txbuf *tb;
3365 int ring_idx, buf_idx;
3366 struct ieee80211_node *ni;
3367
3368 if (tx_id == 0) {
3369 if_printf(ifp, "%s: zero tx id\n", __func__);
3370 return;
3371 }
3372
3373 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3374 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3375
3376 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx));
3377 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
3378
3379 tbd = &sc->sc_tx_bdata[ring_idx];
3380 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used));
3381 tbd->tbd_used--;
3382
3383 tb = &tbd->tbd_buf[buf_idx];
3384 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3385 "acked %d, data_txcnt %d, ni %p\n",
3386 buf_idx, acked, data_txcnt, tb->tb_ni);
3387
3388 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3389
3390 ni = tb->tb_ni;
3391 if (tb->tb_ni != NULL) {
3392 struct bwi_node *bn = (struct bwi_node *) tb->tb_ni;
3393 const struct bwi_txbuf_hdr *hdr =
3394 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *);
3395
3396 /* NB: update rate control only for unicast frames */
3397 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) {
3398 /*
3399 * Feed back 'acked and data_txcnt'. Note that the
3400 * generic AMRR code only understands one tx rate
3401 * and the estimator doesn't handle real retry counts
3402 * well so to avoid over-aggressive downshifting we
3403 * treat any number of retries as "1".
3404 */
3405 ieee80211_amrr_tx_complete(&bn->amn, acked,
3406 data_txcnt > 1);
3407 }
3408
3409 /*
3410 * Do any tx complete callback. Note this must
3411 * be done before releasing the node reference.
3412 */
3413 if (tb->tb_mbuf->m_flags & M_TXCB)
3414 ieee80211_process_callback(ni, tb->tb_mbuf, !acked);
3415
3416 ieee80211_free_node(tb->tb_ni);
3417 tb->tb_ni = NULL;
3418 }
3419 m_freem(tb->tb_mbuf);
3420 tb->tb_mbuf = NULL;
3421
3422 if (tbd->tbd_used == 0)
3423 ifp->if_timer = 0;
3424
3425 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3426 }
3427
3428 static void
3429 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3430 {
3431 struct bwi_txstats_data *st = sc->sc_txstats;
3432 int idx;
3433
3434 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3435
3436 idx = st->stats_idx;
3437 while (idx != end_idx) {
3438 const struct bwi_txstats *stats = &st->stats[idx];
3439
3440 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3441 int data_txcnt;
3442
3443 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3444 BWI_TXS_TXCNT_DATA);
3445 _bwi_txeof(sc, le16toh(stats->txs_id),
3446 stats->txs_flags & BWI_TXS_F_ACKED,
3447 data_txcnt);
3448 }
3449 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3450 }
3451 st->stats_idx = idx;
3452 }
3453
3454 static void
3455 bwi_txeof(struct bwi_softc *sc)
3456 {
3457 struct ifnet *ifp = sc->sc_ifp;
3458
3459 for (;;) {
3460 uint32_t tx_status0, tx_status1;
3461 uint16_t tx_id;
3462 int data_txcnt;
3463
3464 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3465 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3466 break;
3467 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3468
3469 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3470 data_txcnt = __SHIFTOUT(tx_status0,
3471 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3472
3473 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3474 continue;
3475
3476 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED,
3477 data_txcnt);
3478 }
3479
3480 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0)
3481 ifp->if_start(ifp);
3482 }
3483
3484 static int
3485 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3486 {
3487 bwi_power_on(sc, 1);
3488 return bwi_set_clock_mode(sc, clk_mode);
3489 }
3490
3491 static void
3492 bwi_bbp_power_off(struct bwi_softc *sc)
3493 {
3494 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3495 bwi_power_off(sc, 1);
3496 }
3497
3498 static int
3499 bwi_get_pwron_delay(struct bwi_softc *sc)
3500 {
3501 struct bwi_regwin *com, *old;
3502 struct bwi_clock_freq freq;
3503 uint32_t val;
3504 int error;
3505
3506 com = &sc->sc_com_regwin;
3507 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin"));
3508
3509 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3510 return 0;
3511
3512 error = bwi_regwin_switch(sc, com, &old);
3513 if (error)
3514 return error;
3515
3516 bwi_get_clock_freq(sc, &freq);
3517
3518 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3519 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3520 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3521
3522 return bwi_regwin_switch(sc, old, NULL);
3523 }
3524
3525 static int
3526 bwi_bus_attach(struct bwi_softc *sc)
3527 {
3528 struct bwi_regwin *bus, *old;
3529 int error;
3530
3531 bus = &sc->sc_bus_regwin;
3532
3533 error = bwi_regwin_switch(sc, bus, &old);
3534 if (error)
3535 return error;
3536
3537 if (!bwi_regwin_is_enabled(sc, bus))
3538 bwi_regwin_enable(sc, bus, 0);
3539
3540 /* Disable interripts */
3541 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3542
3543 return bwi_regwin_switch(sc, old, NULL);
3544 }
3545
3546 static const char *
3547 bwi_regwin_name(const struct bwi_regwin *rw)
3548 {
3549 switch (rw->rw_type) {
3550 case BWI_REGWIN_T_COM:
3551 return "COM";
3552 case BWI_REGWIN_T_BUSPCI:
3553 return "PCI";
3554 case BWI_REGWIN_T_MAC:
3555 return "MAC";
3556 case BWI_REGWIN_T_BUSPCIE:
3557 return "PCIE";
3558 }
3559 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3560 return NULL;
3561 }
3562
3563 static uint32_t
3564 bwi_regwin_disable_bits(struct bwi_softc *sc)
3565 {
3566 uint32_t busrev;
3567
3568 /* XXX cache this */
3569 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3570 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3571 "bus rev %u\n", busrev);
3572
3573 if (busrev == BWI_BUSREV_0)
3574 return BWI_STATE_LO_DISABLE1;
3575 else if (busrev == BWI_BUSREV_1)
3576 return BWI_STATE_LO_DISABLE2;
3577 else
3578 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3579 }
3580
3581 int
3582 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3583 {
3584 uint32_t val, disable_bits;
3585
3586 disable_bits = bwi_regwin_disable_bits(sc);
3587 val = CSR_READ_4(sc, BWI_STATE_LO);
3588
3589 if ((val & (BWI_STATE_LO_CLOCK |
3590 BWI_STATE_LO_RESET |
3591 disable_bits)) == BWI_STATE_LO_CLOCK) {
3592 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3593 bwi_regwin_name(rw));
3594 return 1;
3595 } else {
3596 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3597 bwi_regwin_name(rw));
3598 return 0;
3599 }
3600 }
3601
3602 void
3603 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3604 {
3605 uint32_t state_lo, disable_bits;
3606 int i;
3607
3608 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3609
3610 /*
3611 * If current regwin is in 'reset' state, it was already disabled.
3612 */
3613 if (state_lo & BWI_STATE_LO_RESET) {
3614 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3615 "%s was already disabled\n", bwi_regwin_name(rw));
3616 return;
3617 }
3618
3619 disable_bits = bwi_regwin_disable_bits(sc);
3620
3621 /*
3622 * Disable normal clock
3623 */
3624 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3625 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3626
3627 /*
3628 * Wait until normal clock is disabled
3629 */
3630 #define NRETRY 1000
3631 for (i = 0; i < NRETRY; ++i) {
3632 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3633 if (state_lo & disable_bits)
3634 break;
3635 DELAY(10);
3636 }
3637 if (i == NRETRY) {
3638 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3639 bwi_regwin_name(rw));
3640 }
3641
3642 for (i = 0; i < NRETRY; ++i) {
3643 uint32_t state_hi;
3644
3645 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3646 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3647 break;
3648 DELAY(10);
3649 }
3650 if (i == NRETRY) {
3651 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3652 bwi_regwin_name(rw));
3653 }
3654 #undef NRETRY
3655
3656 /*
3657 * Reset and disable regwin with gated clock
3658 */
3659 state_lo = BWI_STATE_LO_RESET | disable_bits |
3660 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3661 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3662 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3663
3664 /* Flush pending bus write */
3665 CSR_READ_4(sc, BWI_STATE_LO);
3666 DELAY(1);
3667
3668 /* Reset and disable regwin */
3669 state_lo = BWI_STATE_LO_RESET | disable_bits |
3670 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3671 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3672
3673 /* Flush pending bus write */
3674 CSR_READ_4(sc, BWI_STATE_LO);
3675 DELAY(1);
3676 }
3677
3678 void
3679 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3680 {
3681 uint32_t state_lo, state_hi, imstate;
3682
3683 bwi_regwin_disable(sc, rw, flags);
3684
3685 /* Reset regwin with gated clock */
3686 state_lo = BWI_STATE_LO_RESET |
3687 BWI_STATE_LO_CLOCK |
3688 BWI_STATE_LO_GATED_CLOCK |
3689 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3690 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3691
3692 /* Flush pending bus write */
3693 CSR_READ_4(sc, BWI_STATE_LO);
3694 DELAY(1);
3695
3696 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3697 if (state_hi & BWI_STATE_HI_SERROR)
3698 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3699
3700 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3701 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3702 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3703 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3704 }
3705
3706 /* Enable regwin with gated clock */
3707 state_lo = BWI_STATE_LO_CLOCK |
3708 BWI_STATE_LO_GATED_CLOCK |
3709 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3710 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3711
3712 /* Flush pending bus write */
3713 CSR_READ_4(sc, BWI_STATE_LO);
3714 DELAY(1);
3715
3716 /* Enable regwin with normal clock */
3717 state_lo = BWI_STATE_LO_CLOCK |
3718 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3719 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3720
3721 /* Flush pending bus write */
3722 CSR_READ_4(sc, BWI_STATE_LO);
3723 DELAY(1);
3724 }
3725
3726 static void
3727 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3728 {
3729 struct ifnet *ifp = sc->sc_ifp;
3730 struct bwi_mac *mac;
3731 struct bwi_myaddr_bssid buf;
3732 const uint8_t *p;
3733 uint32_t val;
3734 int n, i;
3735
3736 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3737 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3738 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3739
3740 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3741
3742 bcopy(IF_LLADDR(ifp), buf.myaddr, sizeof(buf.myaddr));
3743 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3744
3745 n = sizeof(buf) / sizeof(val);
3746 p = (const uint8_t *)&buf;
3747 for (i = 0; i < n; ++i) {
3748 int j;
3749
3750 val = 0;
3751 for (j = 0; j < sizeof(val); ++j)
3752 val |= ((uint32_t)(*p++)) << (j * 8);
3753
3754 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3755 }
3756 }
3757
3758 static void
3759 bwi_updateslot(struct ifnet *ifp)
3760 {
3761 struct bwi_softc *sc = ifp->if_softc;
3762 struct ieee80211com *ic = ifp->if_l2com;
3763 struct bwi_mac *mac;
3764
3765 BWI_LOCK(sc);
3766 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3767 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3768
3769 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3770 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3771 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3772
3773 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3774 }
3775 BWI_UNLOCK(sc);
3776 }
3777
3778 static void
3779 bwi_calibrate(void *xsc)
3780 {
3781 struct bwi_softc *sc = xsc;
3782 #ifdef INVARIANTS
3783 struct ifnet *ifp = sc->sc_ifp;
3784 struct ieee80211com *ic = ifp->if_l2com;
3785 #endif
3786 struct bwi_mac *mac;
3787
3788 BWI_ASSERT_LOCKED(sc);
3789
3790 KASSERT(ic->ic_opmode != IEEE80211_M_MONITOR,
3791 ("opmode %d", ic->ic_opmode));
3792
3793 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3794 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3795 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3796
3797 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3798 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3799
3800 /* XXX 15 seconds */
3801 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3802 }
3803
3804 static int
3805 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3806 {
3807 struct bwi_mac *mac;
3808
3809 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3810 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3811 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3812
3813 return bwi_rf_calc_rssi(mac, hdr);
3814 }
3815
3816 static int
3817 bwi_calc_noise(struct bwi_softc *sc)
3818 {
3819 struct bwi_mac *mac;
3820
3821 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3822 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3823 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3824
3825 return bwi_rf_calc_noise(mac);
3826 }
3827
3828 static __inline uint8_t
3829 bwi_ofdm_plcp2rate(const uint32_t *plcp0)
3830 {
3831 uint32_t plcp;
3832 uint8_t plcp_rate;
3833
3834 plcp = le32toh(*plcp0);
3835 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);
3836 return ieee80211_plcp2rate(plcp_rate, IEEE80211_T_OFDM);
3837 }
3838
3839 static __inline uint8_t
3840 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr)
3841 {
3842 return ieee80211_plcp2rate(hdr->i_signal, IEEE80211_T_DS);
3843 }
3844
3845 static void
3846 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3847 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise)
3848 {
3849 const struct ieee80211_frame_min *wh;
3850
3851 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3852 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3853 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3854
3855 wh = mtod(m, const struct ieee80211_frame_min *);
3856 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3857 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3858
3859 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */
3860 sc->sc_rx_th.wr_rate = rate;
3861 sc->sc_rx_th.wr_antsignal = rssi;
3862 sc->sc_rx_th.wr_antnoise = noise;
3863 }
3864
3865 static void
3866 bwi_led_attach(struct bwi_softc *sc)
3867 {
3868 const uint8_t *led_act = NULL;
3869 uint16_t gpio, val[BWI_LED_MAX];
3870 int i;
3871
3872 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
3873
3874 for (i = 0; i < N(bwi_vendor_led_act); ++i) {
3875 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3876 led_act = bwi_vendor_led_act[i].led_act;
3877 break;
3878 }
3879 }
3880 if (led_act == NULL)
3881 led_act = bwi_default_led_act;
3882
3883 #undef N
3884
3885 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3886 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3887 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3888
3889 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3890 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3891 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3892
3893 for (i = 0; i < BWI_LED_MAX; ++i) {
3894 struct bwi_led *led = &sc->sc_leds[i];
3895
3896 if (val[i] == 0xff) {
3897 led->l_act = led_act[i];
3898 } else {
3899 if (val[i] & BWI_LED_ACT_LOW)
3900 led->l_flags |= BWI_LED_F_ACTLOW;
3901 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3902 }
3903 led->l_mask = (1 << i);
3904
3905 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3906 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3907 led->l_act == BWI_LED_ACT_BLINK) {
3908 led->l_flags |= BWI_LED_F_BLINK;
3909 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3910 led->l_flags |= BWI_LED_F_POLLABLE;
3911 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3912 led->l_flags |= BWI_LED_F_SLOW;
3913
3914 if (sc->sc_blink_led == NULL) {
3915 sc->sc_blink_led = led;
3916 if (led->l_flags & BWI_LED_F_SLOW)
3917 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3918 }
3919 }
3920
3921 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3922 "%dth led, act %d, lowact %d\n", i,
3923 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3924 }
3925 callout_init(&sc->sc_led_blink_ch, CALLOUT_MPSAFE);
3926 }
3927
3928 static __inline uint16_t
3929 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3930 {
3931 if (led->l_flags & BWI_LED_F_ACTLOW)
3932 on = !on;
3933 if (on)
3934 val |= led->l_mask;
3935 else
3936 val &= ~led->l_mask;
3937 return val;
3938 }
3939
3940 static void
3941 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3942 {
3943 struct ifnet *ifp = sc->sc_ifp;
3944 struct ieee80211com *ic = ifp->if_l2com;
3945 uint16_t val;
3946 int i;
3947
3948 if (nstate == IEEE80211_S_INIT) {
3949 callout_stop(&sc->sc_led_blink_ch);
3950 sc->sc_led_blinking = 0;
3951 }
3952
3953 if ((ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3954 return;
3955
3956 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3957 for (i = 0; i < BWI_LED_MAX; ++i) {
3958 struct bwi_led *led = &sc->sc_leds[i];
3959 int on;
3960
3961 if (led->l_act == BWI_LED_ACT_UNKN ||
3962 led->l_act == BWI_LED_ACT_NULL)
3963 continue;
3964
3965 if ((led->l_flags & BWI_LED_F_BLINK) &&
3966 nstate != IEEE80211_S_INIT)
3967 continue;
3968
3969 switch (led->l_act) {
3970 case BWI_LED_ACT_ON: /* Always on */
3971 on = 1;
3972 break;
3973 case BWI_LED_ACT_OFF: /* Always off */
3974 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3975 on = 0;
3976 break;
3977 default:
3978 on = 1;
3979 switch (nstate) {
3980 case IEEE80211_S_INIT:
3981 on = 0;
3982 break;
3983 case IEEE80211_S_RUN:
3984 if (led->l_act == BWI_LED_ACT_11G &&
3985 ic->ic_curmode != IEEE80211_MODE_11G)
3986 on = 0;
3987 break;
3988 default:
3989 if (led->l_act == BWI_LED_ACT_ASSOC)
3990 on = 0;
3991 break;
3992 }
3993 break;
3994 }
3995
3996 val = bwi_led_onoff(led, val, on);
3997 }
3998 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3999 }
4000 static void
4001 bwi_led_event(struct bwi_softc *sc, int event)
4002 {
4003 struct bwi_led *led = sc->sc_blink_led;
4004 int rate;
4005
4006 if (event == BWI_LED_EVENT_POLL) {
4007 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
4008 return;
4009 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
4010 return;
4011 }
4012
4013 sc->sc_led_ticks = ticks;
4014 if (sc->sc_led_blinking)
4015 return;
4016
4017 switch (event) {
4018 case BWI_LED_EVENT_RX:
4019 rate = sc->sc_rx_rate;
4020 break;
4021 case BWI_LED_EVENT_TX:
4022 rate = sc->sc_tx_rate;
4023 break;
4024 case BWI_LED_EVENT_POLL:
4025 rate = 0;
4026 break;
4027 default:
4028 panic("unknown LED event %d\n", event);
4029 break;
4030 }
4031 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
4032 bwi_led_duration[rate].off_dur);
4033 }
4034
4035 static void
4036 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
4037 {
4038 struct bwi_led *led = sc->sc_blink_led;
4039 uint16_t val;
4040
4041 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
4042 val = bwi_led_onoff(led, val, 1);
4043 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
4044
4045 if (led->l_flags & BWI_LED_F_SLOW) {
4046 BWI_LED_SLOWDOWN(on_dur);
4047 BWI_LED_SLOWDOWN(off_dur);
4048 }
4049
4050 sc->sc_led_blinking = 1;
4051 sc->sc_led_blink_offdur = off_dur;
4052
4053 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
4054 }
4055
4056 static void
4057 bwi_led_blink_next(void *xsc)
4058 {
4059 struct bwi_softc *sc = xsc;
4060 uint16_t val;
4061
4062 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
4063 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
4064 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
4065
4066 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
4067 bwi_led_blink_end, sc);
4068 }
4069
4070 static void
4071 bwi_led_blink_end(void *xsc)
4072 {
4073 struct bwi_softc *sc = xsc;
4074 sc->sc_led_blinking = 0;
4075 }
4076
4077 static void
4078 bwi_restart(void *xsc, int pending)
4079 {
4080 struct bwi_softc *sc = xsc;
4081 struct ifnet *ifp = sc->sc_ifp;
4082
4083 if_printf(ifp, "%s begin, help!\n", __func__);
4084 BWI_LOCK(sc);
4085 bwi_init_statechg(xsc, 0);
4086 #if 0
4087 bwi_start_locked(ifp);
4088 #endif
4089 BWI_UNLOCK(sc);
4090 }
Cache object: 60c9d2d29b0acc426e529a5defa9d316
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