FreeBSD/Linux Kernel Cross Reference
sys/dev/bwi/if_bwi.c
1 /*
2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $
35 */
36
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD: releng/8.2/sys/dev/bwi/if_bwi.c 217887 2011-01-26 17:20:34Z bschmidt $");
39
40 #include "opt_inet.h"
41 #include "opt_bwi.h"
42
43 #include <sys/param.h>
44 #include <sys/endian.h>
45 #include <sys/kernel.h>
46 #include <sys/bus.h>
47 #include <sys/malloc.h>
48 #include <sys/proc.h>
49 #include <sys/rman.h>
50 #include <sys/socket.h>
51 #include <sys/sockio.h>
52 #include <sys/sysctl.h>
53 #include <sys/systm.h>
54 #include <sys/taskqueue.h>
55
56 #include <net/if.h>
57 #include <net/if_dl.h>
58 #include <net/if_media.h>
59 #include <net/if_types.h>
60 #include <net/if_arp.h>
61 #include <net/ethernet.h>
62 #include <net/if_llc.h>
63
64 #include <net80211/ieee80211_var.h>
65 #include <net80211/ieee80211_radiotap.h>
66 #include <net80211/ieee80211_regdomain.h>
67 #include <net80211/ieee80211_phy.h>
68 #include <net80211/ieee80211_ratectl.h>
69
70 #include <net/bpf.h>
71
72 #ifdef INET
73 #include <netinet/in.h>
74 #include <netinet/if_ether.h>
75 #endif
76
77 #include <machine/bus.h>
78
79 #include <dev/pci/pcivar.h>
80 #include <dev/pci/pcireg.h>
81
82 #include <dev/bwi/bitops.h>
83 #include <dev/bwi/if_bwireg.h>
84 #include <dev/bwi/if_bwivar.h>
85 #include <dev/bwi/bwimac.h>
86 #include <dev/bwi/bwirf.h>
87
88 struct bwi_clock_freq {
89 u_int clkfreq_min;
90 u_int clkfreq_max;
91 };
92
93 struct bwi_myaddr_bssid {
94 uint8_t myaddr[IEEE80211_ADDR_LEN];
95 uint8_t bssid[IEEE80211_ADDR_LEN];
96 } __packed;
97
98 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *,
99 const char [IFNAMSIZ], int, int, int,
100 const uint8_t [IEEE80211_ADDR_LEN],
101 const uint8_t [IEEE80211_ADDR_LEN]);
102 static void bwi_vap_delete(struct ieee80211vap *);
103 static void bwi_init(void *);
104 static int bwi_ioctl(struct ifnet *, u_long, caddr_t);
105 static void bwi_start(struct ifnet *);
106 static void bwi_start_locked(struct ifnet *);
107 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *,
108 const struct ieee80211_bpf_params *);
109 static void bwi_watchdog(struct ifnet *);
110 static void bwi_scan_start(struct ieee80211com *);
111 static void bwi_set_channel(struct ieee80211com *);
112 static void bwi_scan_end(struct ieee80211com *);
113 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int);
114 static void bwi_updateslot(struct ifnet *);
115 static int bwi_media_change(struct ifnet *);
116
117 static void bwi_calibrate(void *);
118
119 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
120 static int bwi_calc_noise(struct bwi_softc *);
121 static __inline uint8_t bwi_ofdm_plcp2rate(const uint32_t *);
122 static __inline uint8_t bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *);
123 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
124 struct bwi_rxbuf_hdr *, const void *, int, int, int);
125
126 static void bwi_restart(void *, int);
127 static void bwi_init_statechg(struct bwi_softc *, int);
128 static void bwi_stop(struct bwi_softc *, int);
129 static void bwi_stop_locked(struct bwi_softc *, int);
130 static int bwi_newbuf(struct bwi_softc *, int, int);
131 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
132 struct ieee80211_node *);
133 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *,
134 struct ieee80211_node *,
135 const struct ieee80211_bpf_params *);
136
137 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
138 bus_addr_t, int, int);
139 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
140
141 static int bwi_init_tx_ring32(struct bwi_softc *, int);
142 static int bwi_init_rx_ring32(struct bwi_softc *);
143 static int bwi_init_txstats32(struct bwi_softc *);
144 static void bwi_free_tx_ring32(struct bwi_softc *, int);
145 static void bwi_free_rx_ring32(struct bwi_softc *);
146 static void bwi_free_txstats32(struct bwi_softc *);
147 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
148 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
149 int, bus_addr_t, int);
150 static int bwi_rxeof32(struct bwi_softc *);
151 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
152 static void bwi_txeof_status32(struct bwi_softc *);
153
154 static int bwi_init_tx_ring64(struct bwi_softc *, int);
155 static int bwi_init_rx_ring64(struct bwi_softc *);
156 static int bwi_init_txstats64(struct bwi_softc *);
157 static void bwi_free_tx_ring64(struct bwi_softc *, int);
158 static void bwi_free_rx_ring64(struct bwi_softc *);
159 static void bwi_free_txstats64(struct bwi_softc *);
160 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
161 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
162 int, bus_addr_t, int);
163 static int bwi_rxeof64(struct bwi_softc *);
164 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
165 static void bwi_txeof_status64(struct bwi_softc *);
166
167 static int bwi_rxeof(struct bwi_softc *, int);
168 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
169 static void bwi_txeof(struct bwi_softc *);
170 static void bwi_txeof_status(struct bwi_softc *, int);
171 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
172 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
173
174 static int bwi_dma_alloc(struct bwi_softc *);
175 static void bwi_dma_free(struct bwi_softc *);
176 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
177 struct bwi_ring_data *, bus_size_t,
178 uint32_t);
179 static int bwi_dma_mbuf_create(struct bwi_softc *);
180 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
181 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
182 static void bwi_dma_txstats_free(struct bwi_softc *);
183 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
184 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
185 bus_size_t, int);
186
187 static void bwi_power_on(struct bwi_softc *, int);
188 static int bwi_power_off(struct bwi_softc *, int);
189 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
190 static int bwi_set_clock_delay(struct bwi_softc *);
191 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
192 static int bwi_get_pwron_delay(struct bwi_softc *sc);
193 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
194 const uint8_t *);
195 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
196
197 static void bwi_get_card_flags(struct bwi_softc *);
198 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
199
200 static int bwi_bus_attach(struct bwi_softc *);
201 static int bwi_bbp_attach(struct bwi_softc *);
202 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
203 static void bwi_bbp_power_off(struct bwi_softc *);
204
205 static const char *bwi_regwin_name(const struct bwi_regwin *);
206 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
207 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
208 static int bwi_regwin_select(struct bwi_softc *, int);
209
210 static void bwi_led_attach(struct bwi_softc *);
211 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
212 static void bwi_led_event(struct bwi_softc *, int);
213 static void bwi_led_blink_start(struct bwi_softc *, int, int);
214 static void bwi_led_blink_next(void *);
215 static void bwi_led_blink_end(void *);
216
217 static const struct {
218 uint16_t did_min;
219 uint16_t did_max;
220 uint16_t bbp_id;
221 } bwi_bbpid_map[] = {
222 { 0x4301, 0x4301, 0x4301 },
223 { 0x4305, 0x4307, 0x4307 },
224 { 0x4403, 0x4403, 0x4402 },
225 { 0x4610, 0x4615, 0x4610 },
226 { 0x4710, 0x4715, 0x4710 },
227 { 0x4720, 0x4725, 0x4309 }
228 };
229
230 static const struct {
231 uint16_t bbp_id;
232 int nregwin;
233 } bwi_regwin_count[] = {
234 { 0x4301, 5 },
235 { 0x4306, 6 },
236 { 0x4307, 5 },
237 { 0x4310, 8 },
238 { 0x4401, 3 },
239 { 0x4402, 3 },
240 { 0x4610, 9 },
241 { 0x4704, 9 },
242 { 0x4710, 9 },
243 { 0x5365, 7 }
244 };
245
246 #define CLKSRC(src) \
247 [BWI_CLKSRC_ ## src] = { \
248 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
249 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
250 }
251
252 static const struct {
253 u_int freq_min;
254 u_int freq_max;
255 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
256 CLKSRC(LP_OSC),
257 CLKSRC(CS_OSC),
258 CLKSRC(PCI)
259 };
260
261 #undef CLKSRC
262
263 #define VENDOR_LED_ACT(vendor) \
264 { \
265 .vid = PCI_VENDOR_##vendor, \
266 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
267 }
268
269 static const struct {
270 #define PCI_VENDOR_COMPAQ 0x0e11
271 #define PCI_VENDOR_LINKSYS 0x1737
272 uint16_t vid;
273 uint8_t led_act[BWI_LED_MAX];
274 } bwi_vendor_led_act[] = {
275 VENDOR_LED_ACT(COMPAQ),
276 VENDOR_LED_ACT(LINKSYS)
277 #undef PCI_VENDOR_LINKSYS
278 #undef PCI_VENDOR_COMPAQ
279 };
280
281 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
282 { BWI_VENDOR_LED_ACT_DEFAULT };
283
284 #undef VENDOR_LED_ACT
285
286 static const struct {
287 int on_dur;
288 int off_dur;
289 } bwi_led_duration[109] = {
290 [0] = { 400, 100 },
291 [2] = { 150, 75 },
292 [4] = { 90, 45 },
293 [11] = { 66, 34 },
294 [12] = { 53, 26 },
295 [18] = { 42, 21 },
296 [22] = { 35, 17 },
297 [24] = { 32, 16 },
298 [36] = { 21, 10 },
299 [48] = { 16, 8 },
300 [72] = { 11, 5 },
301 [96] = { 9, 4 },
302 [108] = { 7, 3 }
303 };
304
305 #ifdef BWI_DEBUG
306 #ifdef BWI_DEBUG_VERBOSE
307 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
308 #else
309 static uint32_t bwi_debug;
310 #endif
311 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
312 #endif /* BWI_DEBUG */
313
314 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
315
316 uint16_t
317 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
318 {
319 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
320 }
321
322 static __inline void
323 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
324 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
325 int tx)
326 {
327 struct bwi_desc32 *desc = &desc_array[desc_idx];
328 uint32_t ctrl, addr, addr_hi, addr_lo;
329
330 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
331 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
332
333 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
334 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
335
336 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
337 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
338 if (desc_idx == ndesc - 1)
339 ctrl |= BWI_DESC32_C_EOR;
340 if (tx) {
341 /* XXX */
342 ctrl |= BWI_DESC32_C_FRAME_START |
343 BWI_DESC32_C_FRAME_END |
344 BWI_DESC32_C_INTR;
345 }
346
347 desc->addr = htole32(addr);
348 desc->ctrl = htole32(ctrl);
349 }
350
351 int
352 bwi_attach(struct bwi_softc *sc)
353 {
354 struct ieee80211com *ic;
355 device_t dev = sc->sc_dev;
356 struct ifnet *ifp;
357 struct bwi_mac *mac;
358 struct bwi_phy *phy;
359 int i, error;
360 uint8_t bands;
361 uint8_t macaddr[IEEE80211_ADDR_LEN];
362
363 BWI_LOCK_INIT(sc);
364
365 /*
366 * Initialize taskq and various tasks
367 */
368 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO,
369 taskqueue_thread_enqueue, &sc->sc_tq);
370 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
371 device_get_nameunit(dev));
372 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc);
373
374 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0);
375
376 /*
377 * Initialize sysctl variables
378 */
379 sc->sc_fw_version = BWI_FW_VERSION3;
380 sc->sc_led_idle = (2350 * hz) / 1000;
381 sc->sc_led_blink = 1;
382 sc->sc_txpwr_calib = 1;
383 #ifdef BWI_DEBUG
384 sc->sc_debug = bwi_debug;
385 #endif
386 bwi_power_on(sc, 1);
387
388 error = bwi_bbp_attach(sc);
389 if (error)
390 goto fail;
391
392 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
393 if (error)
394 goto fail;
395
396 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
397 error = bwi_set_clock_delay(sc);
398 if (error)
399 goto fail;
400
401 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
402 if (error)
403 goto fail;
404
405 error = bwi_get_pwron_delay(sc);
406 if (error)
407 goto fail;
408 }
409
410 error = bwi_bus_attach(sc);
411 if (error)
412 goto fail;
413
414 bwi_get_card_flags(sc);
415
416 bwi_led_attach(sc);
417
418 for (i = 0; i < sc->sc_nmac; ++i) {
419 struct bwi_regwin *old;
420
421 mac = &sc->sc_mac[i];
422 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
423 if (error)
424 goto fail;
425
426 error = bwi_mac_lateattach(mac);
427 if (error)
428 goto fail;
429
430 error = bwi_regwin_switch(sc, old, NULL);
431 if (error)
432 goto fail;
433 }
434
435 /*
436 * XXX First MAC is known to exist
437 * TODO2
438 */
439 mac = &sc->sc_mac[0];
440 phy = &mac->mac_phy;
441
442 bwi_bbp_power_off(sc);
443
444 error = bwi_dma_alloc(sc);
445 if (error)
446 goto fail;
447
448 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
449 if (ifp == NULL) {
450 device_printf(dev, "can not if_alloc()\n");
451 error = ENOSPC;
452 goto fail;
453 }
454 ic = ifp->if_l2com;
455
456 /* set these up early for if_printf use */
457 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
458
459 ifp->if_softc = sc;
460 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
461 ifp->if_init = bwi_init;
462 ifp->if_ioctl = bwi_ioctl;
463 ifp->if_start = bwi_start;
464 ifp->if_watchdog = bwi_watchdog;
465 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
466 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
467 IFQ_SET_READY(&ifp->if_snd);
468
469 /*
470 * Setup ratesets, phytype, channels and get MAC address
471 */
472 bands = 0;
473 if (phy->phy_mode == IEEE80211_MODE_11B ||
474 phy->phy_mode == IEEE80211_MODE_11G) {
475 setbit(&bands, IEEE80211_MODE_11B);
476 if (phy->phy_mode == IEEE80211_MODE_11B) {
477 ic->ic_phytype = IEEE80211_T_DS;
478 } else {
479 ic->ic_phytype = IEEE80211_T_OFDM;
480 setbit(&bands, IEEE80211_MODE_11G);
481 }
482
483 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, macaddr);
484 if (IEEE80211_IS_MULTICAST(macaddr)) {
485 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, macaddr);
486 if (IEEE80211_IS_MULTICAST(macaddr)) {
487 device_printf(dev,
488 "invalid MAC address: %6D\n",
489 macaddr, ":");
490 }
491 }
492 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
493 /* TODO:11A */
494 setbit(&bands, IEEE80211_MODE_11A);
495 error = ENXIO;
496 goto fail;
497 } else {
498 panic("unknown phymode %d\n", phy->phy_mode);
499 }
500
501 /* Get locale */
502 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
503 BWI_SPROM_CARD_INFO_LOCALE);
504 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
505 /* XXX use locale */
506 ieee80211_init_channels(ic, NULL, &bands);
507
508 ic->ic_ifp = ifp;
509 ic->ic_caps = IEEE80211_C_STA |
510 IEEE80211_C_SHSLOT |
511 IEEE80211_C_SHPREAMBLE |
512 IEEE80211_C_WPA |
513 IEEE80211_C_BGSCAN |
514 IEEE80211_C_MONITOR;
515 ic->ic_opmode = IEEE80211_M_STA;
516 ieee80211_ifattach(ic, macaddr);
517
518 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
519
520 /* override default methods */
521 ic->ic_vap_create = bwi_vap_create;
522 ic->ic_vap_delete = bwi_vap_delete;
523 ic->ic_raw_xmit = bwi_raw_xmit;
524 ic->ic_updateslot = bwi_updateslot;
525 ic->ic_scan_start = bwi_scan_start;
526 ic->ic_scan_end = bwi_scan_end;
527 ic->ic_set_channel = bwi_set_channel;
528
529 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan);
530
531 ieee80211_radiotap_attach(ic,
532 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
533 BWI_TX_RADIOTAP_PRESENT,
534 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
535 BWI_RX_RADIOTAP_PRESENT);
536
537 /*
538 * Add sysctl nodes
539 */
540 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
541 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
542 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
543 "Firmware version");
544 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
545 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
546 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
547 "# ticks before LED enters idle state");
548 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
549 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
550 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
551 "Allow LED to blink");
552 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
553 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
554 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
555 "Enable software TX power calibration");
556 #ifdef BWI_DEBUG
557 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
558 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
559 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
560 #endif
561 if (bootverbose)
562 ieee80211_announce(ic);
563
564 return (0);
565 fail:
566 BWI_LOCK_DESTROY(sc);
567 return (error);
568 }
569
570 int
571 bwi_detach(struct bwi_softc *sc)
572 {
573 struct ifnet *ifp = sc->sc_ifp;
574 struct ieee80211com *ic = ifp->if_l2com;
575 int i;
576
577 bwi_stop(sc, 1);
578 callout_drain(&sc->sc_led_blink_ch);
579 callout_drain(&sc->sc_calib_ch);
580 ieee80211_ifdetach(ic);
581
582 for (i = 0; i < sc->sc_nmac; ++i)
583 bwi_mac_detach(&sc->sc_mac[i]);
584 bwi_dma_free(sc);
585 if_free(ifp);
586 taskqueue_free(sc->sc_tq);
587
588 BWI_LOCK_DESTROY(sc);
589
590 return (0);
591 }
592
593 static struct ieee80211vap *
594 bwi_vap_create(struct ieee80211com *ic,
595 const char name[IFNAMSIZ], int unit, int opmode, int flags,
596 const uint8_t bssid[IEEE80211_ADDR_LEN],
597 const uint8_t mac[IEEE80211_ADDR_LEN])
598 {
599 struct bwi_vap *bvp;
600 struct ieee80211vap *vap;
601
602 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
603 return NULL;
604 bvp = (struct bwi_vap *) malloc(sizeof(struct bwi_vap),
605 M_80211_VAP, M_WAITOK | M_ZERO);
606 if (bvp == NULL)
607 return NULL;
608 vap = &bvp->bv_vap;
609 /* enable s/w bmiss handling for sta mode */
610 ieee80211_vap_setup(ic, vap, name, unit, opmode,
611 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac);
612
613 /* override default methods */
614 bvp->bv_newstate = vap->iv_newstate;
615 vap->iv_newstate = bwi_newstate;
616 #if 0
617 vap->iv_update_beacon = bwi_beacon_update;
618 #endif
619 ieee80211_ratectl_init(vap);
620
621 /* complete setup */
622 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status);
623 ic->ic_opmode = opmode;
624 return vap;
625 }
626
627 static void
628 bwi_vap_delete(struct ieee80211vap *vap)
629 {
630 struct bwi_vap *bvp = BWI_VAP(vap);
631
632 ieee80211_ratectl_deinit(vap);
633 ieee80211_vap_detach(vap);
634 free(bvp, M_80211_VAP);
635 }
636
637 void
638 bwi_suspend(struct bwi_softc *sc)
639 {
640 bwi_stop(sc, 1);
641 }
642
643 void
644 bwi_resume(struct bwi_softc *sc)
645 {
646 struct ifnet *ifp = sc->sc_ifp;
647
648 if (ifp->if_flags & IFF_UP)
649 bwi_init(sc);
650 }
651
652 int
653 bwi_shutdown(struct bwi_softc *sc)
654 {
655 bwi_stop(sc, 1);
656 return 0;
657 }
658
659 static void
660 bwi_power_on(struct bwi_softc *sc, int with_pll)
661 {
662 uint32_t gpio_in, gpio_out, gpio_en;
663 uint16_t status;
664
665 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
666 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
667 goto back;
668
669 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
670 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
671
672 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
673 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
674 if (with_pll) {
675 /* Turn off PLL first */
676 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
677 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
678 }
679
680 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
681 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
682 DELAY(1000);
683
684 if (with_pll) {
685 /* Turn on PLL */
686 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
687 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
688 DELAY(5000);
689 }
690
691 back:
692 /* Clear "Signaled Target Abort" */
693 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
694 status &= ~PCIM_STATUS_STABORT;
695 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
696 }
697
698 static int
699 bwi_power_off(struct bwi_softc *sc, int with_pll)
700 {
701 uint32_t gpio_out, gpio_en;
702
703 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
704 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
705 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
706
707 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
708 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
709 if (with_pll) {
710 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
711 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
712 }
713
714 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
715 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
716 return 0;
717 }
718
719 int
720 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
721 struct bwi_regwin **old_rw)
722 {
723 int error;
724
725 if (old_rw != NULL)
726 *old_rw = NULL;
727
728 if (!BWI_REGWIN_EXIST(rw))
729 return EINVAL;
730
731 if (sc->sc_cur_regwin != rw) {
732 error = bwi_regwin_select(sc, rw->rw_id);
733 if (error) {
734 device_printf(sc->sc_dev, "can't select regwin %d\n",
735 rw->rw_id);
736 return error;
737 }
738 }
739
740 if (old_rw != NULL)
741 *old_rw = sc->sc_cur_regwin;
742 sc->sc_cur_regwin = rw;
743 return 0;
744 }
745
746 static int
747 bwi_regwin_select(struct bwi_softc *sc, int id)
748 {
749 uint32_t win = BWI_PCIM_REGWIN(id);
750 int i;
751
752 #define RETRY_MAX 50
753 for (i = 0; i < RETRY_MAX; ++i) {
754 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
755 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
756 return 0;
757 DELAY(10);
758 }
759 #undef RETRY_MAX
760
761 return ENXIO;
762 }
763
764 static void
765 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
766 {
767 uint32_t val;
768
769 val = CSR_READ_4(sc, BWI_ID_HI);
770 *type = BWI_ID_HI_REGWIN_TYPE(val);
771 *rev = BWI_ID_HI_REGWIN_REV(val);
772
773 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
774 "vendor 0x%04x\n", *type, *rev,
775 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
776 }
777
778 static int
779 bwi_bbp_attach(struct bwi_softc *sc)
780 {
781 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
782 uint16_t bbp_id, rw_type;
783 uint8_t rw_rev;
784 uint32_t info;
785 int error, nregwin, i;
786
787 /*
788 * Get 0th regwin information
789 * NOTE: 0th regwin should exist
790 */
791 error = bwi_regwin_select(sc, 0);
792 if (error) {
793 device_printf(sc->sc_dev, "can't select regwin 0\n");
794 return error;
795 }
796 bwi_regwin_info(sc, &rw_type, &rw_rev);
797
798 /*
799 * Find out BBP id
800 */
801 bbp_id = 0;
802 info = 0;
803 if (rw_type == BWI_REGWIN_T_COM) {
804 info = CSR_READ_4(sc, BWI_INFO);
805 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
806
807 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
808
809 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
810 } else {
811 for (i = 0; i < N(bwi_bbpid_map); ++i) {
812 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min &&
813 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) {
814 bbp_id = bwi_bbpid_map[i].bbp_id;
815 break;
816 }
817 }
818 if (bbp_id == 0) {
819 device_printf(sc->sc_dev, "no BBP id for device id "
820 "0x%04x\n", sc->sc_pci_did);
821 return ENXIO;
822 }
823
824 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) |
825 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
826 }
827
828 /*
829 * Find out number of regwins
830 */
831 nregwin = 0;
832 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
833 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
834 } else {
835 for (i = 0; i < N(bwi_regwin_count); ++i) {
836 if (bwi_regwin_count[i].bbp_id == bbp_id) {
837 nregwin = bwi_regwin_count[i].nregwin;
838 break;
839 }
840 }
841 if (nregwin == 0) {
842 device_printf(sc->sc_dev, "no number of win for "
843 "BBP id 0x%04x\n", bbp_id);
844 return ENXIO;
845 }
846 }
847
848 /* Record BBP id/rev for later using */
849 sc->sc_bbp_id = bbp_id;
850 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
851 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
852 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
853 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
854
855 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
856 nregwin, sc->sc_cap);
857
858 /*
859 * Create rest of the regwins
860 */
861
862 /* Don't re-create common regwin, if it is already created */
863 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
864
865 for (; i < nregwin; ++i) {
866 /*
867 * Get regwin information
868 */
869 error = bwi_regwin_select(sc, i);
870 if (error) {
871 device_printf(sc->sc_dev,
872 "can't select regwin %d\n", i);
873 return error;
874 }
875 bwi_regwin_info(sc, &rw_type, &rw_rev);
876
877 /*
878 * Try attach:
879 * 1) Bus (PCI/PCIE) regwin
880 * 2) MAC regwin
881 * Ignore rest types of regwin
882 */
883 if (rw_type == BWI_REGWIN_T_BUSPCI ||
884 rw_type == BWI_REGWIN_T_BUSPCIE) {
885 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
886 device_printf(sc->sc_dev,
887 "bus regwin already exists\n");
888 } else {
889 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
890 rw_type, rw_rev);
891 }
892 } else if (rw_type == BWI_REGWIN_T_MAC) {
893 /* XXX ignore return value */
894 bwi_mac_attach(sc, i, rw_rev);
895 }
896 }
897
898 /* At least one MAC shold exist */
899 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
900 device_printf(sc->sc_dev, "no MAC was found\n");
901 return ENXIO;
902 }
903 KASSERT(sc->sc_nmac > 0, ("no mac's"));
904
905 /* Bus regwin must exist */
906 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
907 device_printf(sc->sc_dev, "no bus regwin was found\n");
908 return ENXIO;
909 }
910
911 /* Start with first MAC */
912 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
913 if (error)
914 return error;
915
916 return 0;
917 #undef N
918 }
919
920 int
921 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
922 {
923 struct bwi_regwin *old, *bus;
924 uint32_t val;
925 int error;
926
927 bus = &sc->sc_bus_regwin;
928 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin"));
929
930 /*
931 * Tell bus to generate requested interrupts
932 */
933 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
934 /*
935 * NOTE: Read BWI_FLAGS from MAC regwin
936 */
937 val = CSR_READ_4(sc, BWI_FLAGS);
938
939 error = bwi_regwin_switch(sc, bus, &old);
940 if (error)
941 return error;
942
943 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
944 } else {
945 uint32_t mac_mask;
946
947 mac_mask = 1 << mac->mac_id;
948
949 error = bwi_regwin_switch(sc, bus, &old);
950 if (error)
951 return error;
952
953 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
954 val |= mac_mask << 8;
955 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
956 }
957
958 if (sc->sc_flags & BWI_F_BUS_INITED)
959 goto back;
960
961 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
962 /*
963 * Enable prefetch and burst
964 */
965 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
966 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
967
968 if (bus->rw_rev < 5) {
969 struct bwi_regwin *com = &sc->sc_com_regwin;
970
971 /*
972 * Configure timeouts for bus operation
973 */
974
975 /*
976 * Set service timeout and request timeout
977 */
978 CSR_SETBITS_4(sc, BWI_CONF_LO,
979 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
980 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
981
982 /*
983 * If there is common regwin, we switch to that regwin
984 * and switch back to bus regwin once we have done.
985 */
986 if (BWI_REGWIN_EXIST(com)) {
987 error = bwi_regwin_switch(sc, com, NULL);
988 if (error)
989 return error;
990 }
991
992 /* Let bus know what we have changed */
993 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
994 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
995 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
996 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
997
998 if (BWI_REGWIN_EXIST(com)) {
999 error = bwi_regwin_switch(sc, bus, NULL);
1000 if (error)
1001 return error;
1002 }
1003 } else if (bus->rw_rev >= 11) {
1004 /*
1005 * Enable memory read multiple
1006 */
1007 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
1008 }
1009 } else {
1010 /* TODO:PCIE */
1011 }
1012
1013 sc->sc_flags |= BWI_F_BUS_INITED;
1014 back:
1015 return bwi_regwin_switch(sc, old, NULL);
1016 }
1017
1018 static void
1019 bwi_get_card_flags(struct bwi_softc *sc)
1020 {
1021 #define PCI_VENDOR_APPLE 0x106b
1022 #define PCI_VENDOR_DELL 0x1028
1023 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1024 if (sc->sc_card_flags == 0xffff)
1025 sc->sc_card_flags = 0;
1026
1027 if (sc->sc_pci_subvid == PCI_VENDOR_DELL &&
1028 sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1029 sc->sc_pci_revid == 0x74)
1030 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST;
1031
1032 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1033 sc->sc_pci_subdid == 0x4e && /* XXX */
1034 sc->sc_pci_revid > 0x40)
1035 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1036
1037 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1038 #undef PCI_VENDOR_DELL
1039 #undef PCI_VENDOR_APPLE
1040 }
1041
1042 static void
1043 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1044 {
1045 int i;
1046
1047 for (i = 0; i < 3; ++i) {
1048 *((uint16_t *)eaddr + i) =
1049 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1050 }
1051 }
1052
1053 static void
1054 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1055 {
1056 struct bwi_regwin *com;
1057 uint32_t val;
1058 u_int div;
1059 int src;
1060
1061 bzero(freq, sizeof(*freq));
1062 com = &sc->sc_com_regwin;
1063
1064 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist"));
1065 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin"));
1066 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode"));
1067
1068 /*
1069 * Calculate clock frequency
1070 */
1071 src = -1;
1072 div = 0;
1073 if (com->rw_rev < 6) {
1074 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1075 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1076 src = BWI_CLKSRC_PCI;
1077 div = 64;
1078 } else {
1079 src = BWI_CLKSRC_CS_OSC;
1080 div = 32;
1081 }
1082 } else if (com->rw_rev < 10) {
1083 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1084
1085 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1086 if (src == BWI_CLKSRC_LP_OSC) {
1087 div = 1;
1088 } else {
1089 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1090
1091 /* Unknown source */
1092 if (src >= BWI_CLKSRC_MAX)
1093 src = BWI_CLKSRC_CS_OSC;
1094 }
1095 } else {
1096 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1097
1098 src = BWI_CLKSRC_CS_OSC;
1099 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1100 }
1101
1102 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src));
1103 KASSERT(div != 0, ("div zero"));
1104
1105 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1106 src == BWI_CLKSRC_PCI ? "PCI" :
1107 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1108
1109 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1110 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1111
1112 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1113 freq->clkfreq_min, freq->clkfreq_max);
1114 }
1115
1116 static int
1117 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1118 {
1119 struct bwi_regwin *old, *com;
1120 uint32_t clk_ctrl, clk_src;
1121 int error, pwr_off = 0;
1122
1123 com = &sc->sc_com_regwin;
1124 if (!BWI_REGWIN_EXIST(com))
1125 return 0;
1126
1127 if (com->rw_rev >= 10 || com->rw_rev < 6)
1128 return 0;
1129
1130 /*
1131 * For common regwin whose rev is [6, 10), the chip
1132 * must be capable to change clock mode.
1133 */
1134 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1135 return 0;
1136
1137 error = bwi_regwin_switch(sc, com, &old);
1138 if (error)
1139 return error;
1140
1141 if (clk_mode == BWI_CLOCK_MODE_FAST)
1142 bwi_power_on(sc, 0); /* Don't turn on PLL */
1143
1144 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1145 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1146
1147 switch (clk_mode) {
1148 case BWI_CLOCK_MODE_FAST:
1149 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1150 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1151 break;
1152 case BWI_CLOCK_MODE_SLOW:
1153 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1154 break;
1155 case BWI_CLOCK_MODE_DYN:
1156 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1157 BWI_CLOCK_CTRL_IGNPLL |
1158 BWI_CLOCK_CTRL_NODYN);
1159 if (clk_src != BWI_CLKSRC_CS_OSC) {
1160 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1161 pwr_off = 1;
1162 }
1163 break;
1164 }
1165 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1166
1167 if (pwr_off)
1168 bwi_power_off(sc, 0); /* Leave PLL as it is */
1169
1170 return bwi_regwin_switch(sc, old, NULL);
1171 }
1172
1173 static int
1174 bwi_set_clock_delay(struct bwi_softc *sc)
1175 {
1176 struct bwi_regwin *old, *com;
1177 int error;
1178
1179 com = &sc->sc_com_regwin;
1180 if (!BWI_REGWIN_EXIST(com))
1181 return 0;
1182
1183 error = bwi_regwin_switch(sc, com, &old);
1184 if (error)
1185 return error;
1186
1187 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1188 if (sc->sc_bbp_rev == 0)
1189 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1190 else if (sc->sc_bbp_rev == 1)
1191 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1192 }
1193
1194 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1195 if (com->rw_rev >= 10) {
1196 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1197 } else {
1198 struct bwi_clock_freq freq;
1199
1200 bwi_get_clock_freq(sc, &freq);
1201 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1202 howmany(freq.clkfreq_max * 150, 1000000));
1203 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1204 howmany(freq.clkfreq_max * 15, 1000000));
1205 }
1206 }
1207
1208 return bwi_regwin_switch(sc, old, NULL);
1209 }
1210
1211 static void
1212 bwi_init(void *xsc)
1213 {
1214 struct bwi_softc *sc = xsc;
1215 struct ifnet *ifp = sc->sc_ifp;
1216 struct ieee80211com *ic = ifp->if_l2com;
1217
1218 BWI_LOCK(sc);
1219 bwi_init_statechg(sc, 1);
1220 BWI_UNLOCK(sc);
1221
1222 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1223 ieee80211_start_all(ic); /* start all vap's */
1224 }
1225
1226 static void
1227 bwi_init_statechg(struct bwi_softc *sc, int statechg)
1228 {
1229 struct ifnet *ifp = sc->sc_ifp;
1230 struct bwi_mac *mac;
1231 int error;
1232
1233 bwi_stop_locked(sc, statechg);
1234
1235 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1236
1237 /* TODO: 2 MAC */
1238
1239 mac = &sc->sc_mac[0];
1240 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1241 if (error) {
1242 if_printf(ifp, "%s: error %d on regwin switch\n",
1243 __func__, error);
1244 goto bad;
1245 }
1246 error = bwi_mac_init(mac);
1247 if (error) {
1248 if_printf(ifp, "%s: error %d on MAC init\n", __func__, error);
1249 goto bad;
1250 }
1251
1252 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1253
1254 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1255 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, IF_LLADDR(ifp));
1256
1257 bwi_mac_reset_hwkeys(mac);
1258
1259 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1260 int i;
1261
1262 #define NRETRY 1000
1263 /*
1264 * Drain any possible pending TX status
1265 */
1266 for (i = 0; i < NRETRY; ++i) {
1267 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1268 BWI_TXSTATUS0_VALID) == 0)
1269 break;
1270 CSR_READ_4(sc, BWI_TXSTATUS1);
1271 }
1272 if (i == NRETRY)
1273 if_printf(ifp, "%s: can't drain TX status\n", __func__);
1274 #undef NRETRY
1275 }
1276
1277 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1278 bwi_mac_updateslot(mac, 1);
1279
1280 /* Start MAC */
1281 error = bwi_mac_start(mac);
1282 if (error) {
1283 if_printf(ifp, "%s: error %d starting MAC\n", __func__, error);
1284 goto bad;
1285 }
1286
1287 /* Clear stop flag before enabling interrupt */
1288 sc->sc_flags &= ~BWI_F_STOP;
1289
1290 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1291
1292 /* Enable intrs */
1293 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1294 return;
1295 bad:
1296 bwi_stop_locked(sc, 1);
1297 }
1298
1299 static int
1300 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1301 {
1302 #define IS_RUNNING(ifp) \
1303 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
1304 struct bwi_softc *sc = ifp->if_softc;
1305 struct ieee80211com *ic = ifp->if_l2com;
1306 struct ifreq *ifr = (struct ifreq *) data;
1307 int error = 0, startall = 0;
1308
1309 switch (cmd) {
1310 case SIOCSIFFLAGS:
1311 BWI_LOCK(sc);
1312 if (IS_RUNNING(ifp)) {
1313 struct bwi_mac *mac;
1314 int promisc = -1;
1315
1316 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1317 ("current regwin type %d",
1318 sc->sc_cur_regwin->rw_type));
1319 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1320
1321 if ((ifp->if_flags & IFF_PROMISC) &&
1322 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1323 promisc = 1;
1324 sc->sc_flags |= BWI_F_PROMISC;
1325 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1326 (sc->sc_flags & BWI_F_PROMISC)) {
1327 promisc = 0;
1328 sc->sc_flags &= ~BWI_F_PROMISC;
1329 }
1330
1331 if (promisc >= 0)
1332 bwi_mac_set_promisc(mac, promisc);
1333 }
1334
1335 if (ifp->if_flags & IFF_UP) {
1336 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1337 bwi_init_statechg(sc, 1);
1338 startall = 1;
1339 }
1340 } else {
1341 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1342 bwi_stop_locked(sc, 1);
1343 }
1344 BWI_UNLOCK(sc);
1345 if (startall)
1346 ieee80211_start_all(ic);
1347 break;
1348 case SIOCGIFMEDIA:
1349 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1350 break;
1351 case SIOCGIFADDR:
1352 error = ether_ioctl(ifp, cmd, data);
1353 break;
1354 default:
1355 error = EINVAL;
1356 break;
1357 }
1358 return error;
1359 #undef IS_RUNNING
1360 }
1361
1362 static void
1363 bwi_start(struct ifnet *ifp)
1364 {
1365 struct bwi_softc *sc = ifp->if_softc;
1366
1367 BWI_LOCK(sc);
1368 bwi_start_locked(ifp);
1369 BWI_UNLOCK(sc);
1370 }
1371
1372 static void
1373 bwi_start_locked(struct ifnet *ifp)
1374 {
1375 struct bwi_softc *sc = ifp->if_softc;
1376 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1377 struct ieee80211_frame *wh;
1378 struct ieee80211_node *ni;
1379 struct ieee80211_key *k;
1380 struct mbuf *m;
1381 int trans, idx;
1382
1383 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1384 return;
1385
1386 trans = 0;
1387 idx = tbd->tbd_idx;
1388
1389 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1390 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */
1391 if (m == NULL)
1392 break;
1393
1394 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1395 wh = mtod(m, struct ieee80211_frame *);
1396 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1397 k = ieee80211_crypto_encap(ni, m);
1398 if (k == NULL) {
1399 ieee80211_free_node(ni);
1400 m_freem(m);
1401 ifp->if_oerrors++;
1402 continue;
1403 }
1404 }
1405 wh = NULL; /* Catch any invalid use */
1406
1407 if (bwi_encap(sc, idx, m, ni) != 0) {
1408 /* 'm' is freed in bwi_encap() if we reach here */
1409 if (ni != NULL)
1410 ieee80211_free_node(ni);
1411 ifp->if_oerrors++;
1412 continue;
1413 }
1414
1415 trans = 1;
1416 tbd->tbd_used++;
1417 idx = (idx + 1) % BWI_TX_NDESC;
1418
1419 ifp->if_opackets++;
1420
1421 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
1422 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1423 break;
1424 }
1425 }
1426 tbd->tbd_idx = idx;
1427
1428 if (trans)
1429 ifp->if_timer = 5;
1430 }
1431
1432 static int
1433 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1434 const struct ieee80211_bpf_params *params)
1435 {
1436 struct ieee80211com *ic = ni->ni_ic;
1437 struct ifnet *ifp = ic->ic_ifp;
1438 struct bwi_softc *sc = ifp->if_softc;
1439 /* XXX wme? */
1440 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1441 int idx, error;
1442
1443 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1444 ieee80211_free_node(ni);
1445 m_freem(m);
1446 return ENETDOWN;
1447 }
1448
1449 BWI_LOCK(sc);
1450 idx = tbd->tbd_idx;
1451 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx));
1452 if (params == NULL) {
1453 /*
1454 * Legacy path; interpret frame contents to decide
1455 * precisely how to send the frame.
1456 */
1457 error = bwi_encap(sc, idx, m, ni);
1458 } else {
1459 /*
1460 * Caller supplied explicit parameters to use in
1461 * sending the frame.
1462 */
1463 error = bwi_encap_raw(sc, idx, m, ni, params);
1464 }
1465 if (error == 0) {
1466 ifp->if_opackets++;
1467 if (++tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC)
1468 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1469 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC;
1470 ifp->if_timer = 5;
1471 } else {
1472 /* NB: m is reclaimed on encap failure */
1473 ieee80211_free_node(ni);
1474 ifp->if_oerrors++;
1475 }
1476 BWI_UNLOCK(sc);
1477 return error;
1478 }
1479
1480 static void
1481 bwi_watchdog(struct ifnet *ifp)
1482 {
1483 struct bwi_softc *sc = ifp->if_softc;
1484
1485 BWI_LOCK(sc);
1486 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1487 if_printf(ifp, "watchdog timeout\n");
1488 ifp->if_oerrors++;
1489 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1490 }
1491 BWI_UNLOCK(sc);
1492 }
1493
1494 static void
1495 bwi_stop(struct bwi_softc *sc, int statechg)
1496 {
1497 BWI_LOCK(sc);
1498 bwi_stop_locked(sc, statechg);
1499 BWI_UNLOCK(sc);
1500 }
1501
1502 static void
1503 bwi_stop_locked(struct bwi_softc *sc, int statechg)
1504 {
1505 struct ifnet *ifp = sc->sc_ifp;
1506 struct bwi_mac *mac;
1507 int i, error, pwr_off = 0;
1508
1509 BWI_ASSERT_LOCKED(sc);
1510
1511 callout_stop(&sc->sc_calib_ch);
1512 callout_stop(&sc->sc_led_blink_ch);
1513 sc->sc_led_blinking = 0;
1514 sc->sc_flags |= BWI_F_STOP;
1515
1516 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1517 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1518 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1519 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1520
1521 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1522 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1523 bwi_mac_stop(mac);
1524 }
1525
1526 for (i = 0; i < sc->sc_nmac; ++i) {
1527 struct bwi_regwin *old_rw;
1528
1529 mac = &sc->sc_mac[i];
1530 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1531 continue;
1532
1533 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1534 if (error)
1535 continue;
1536
1537 bwi_mac_shutdown(mac);
1538 pwr_off = 1;
1539
1540 bwi_regwin_switch(sc, old_rw, NULL);
1541 }
1542
1543 if (pwr_off)
1544 bwi_bbp_power_off(sc);
1545
1546 sc->sc_tx_timer = 0;
1547 ifp->if_timer = 0;
1548 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1549 }
1550
1551 void
1552 bwi_intr(void *xsc)
1553 {
1554 struct bwi_softc *sc = xsc;
1555 struct ifnet *ifp = sc->sc_ifp;
1556 struct bwi_mac *mac;
1557 uint32_t intr_status;
1558 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1559 int i, txrx_error, tx = 0, rx_data = -1;
1560
1561 BWI_LOCK(sc);
1562
1563 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
1564 (sc->sc_flags & BWI_F_STOP)) {
1565 BWI_UNLOCK(sc);
1566 return;
1567 }
1568 /*
1569 * Get interrupt status
1570 */
1571 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1572 if (intr_status == 0xffffffff) { /* Not for us */
1573 BWI_UNLOCK(sc);
1574 return;
1575 }
1576
1577 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1578
1579 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1580 if (intr_status == 0) { /* Nothing is interesting */
1581 BWI_UNLOCK(sc);
1582 return;
1583 }
1584
1585 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1586 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1587 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1588
1589 txrx_error = 0;
1590 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1591 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1592 uint32_t mask;
1593
1594 if (BWI_TXRX_IS_RX(i))
1595 mask = BWI_TXRX_RX_INTRS;
1596 else
1597 mask = BWI_TXRX_TX_INTRS;
1598
1599 txrx_intr_status[i] =
1600 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1601
1602 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1603 i, txrx_intr_status[i]);
1604
1605 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1606 if_printf(ifp,
1607 "%s: intr fatal TX/RX (%d) error 0x%08x\n",
1608 __func__, i, txrx_intr_status[i]);
1609 txrx_error = 1;
1610 }
1611 }
1612 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1613
1614 /*
1615 * Acknowledge interrupt
1616 */
1617 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1618
1619 for (i = 0; i < BWI_TXRX_NRING; ++i)
1620 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1621
1622 /* Disable all interrupts */
1623 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1624
1625 /*
1626 * http://bcm-specs.sipsolutions.net/Interrupts
1627 * Says for this bit (0x800):
1628 * "Fatal Error
1629 *
1630 * We got this one while testing things when by accident the
1631 * template ram wasn't set to big endian when it should have
1632 * been after writing the initial values. It keeps on being
1633 * triggered, the only way to stop it seems to shut down the
1634 * chip."
1635 *
1636 * Suggesting that we should never get it and if we do we're not
1637 * feeding TX packets into the MAC correctly if we do... Apparently,
1638 * it is valid only on mac version 5 and higher, but I couldn't
1639 * find a reference for that... Since I see them from time to time
1640 * on my card, this suggests an error in the tx path still...
1641 */
1642 if (intr_status & BWI_INTR_PHY_TXERR) {
1643 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1644 if_printf(ifp, "%s: intr PHY TX error\n", __func__);
1645 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1646 BWI_UNLOCK(sc);
1647 return;
1648 }
1649 }
1650
1651 if (txrx_error) {
1652 /* TODO: reset device */
1653 }
1654
1655 if (intr_status & BWI_INTR_TBTT)
1656 bwi_mac_config_ps(mac);
1657
1658 if (intr_status & BWI_INTR_EO_ATIM)
1659 if_printf(ifp, "EO_ATIM\n");
1660
1661 if (intr_status & BWI_INTR_PMQ) {
1662 for (;;) {
1663 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1664 break;
1665 }
1666 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1667 }
1668
1669 if (intr_status & BWI_INTR_NOISE)
1670 if_printf(ifp, "intr noise\n");
1671
1672 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) {
1673 rx_data = sc->sc_rxeof(sc);
1674 if (sc->sc_flags & BWI_F_STOP) {
1675 BWI_UNLOCK(sc);
1676 return;
1677 }
1678 }
1679
1680 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1681 sc->sc_txeof_status(sc);
1682 tx = 1;
1683 }
1684
1685 if (intr_status & BWI_INTR_TX_DONE) {
1686 bwi_txeof(sc);
1687 tx = 1;
1688 }
1689
1690 /* Re-enable interrupts */
1691 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1692
1693 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1694 int evt = BWI_LED_EVENT_NONE;
1695
1696 if (tx && rx_data > 0) {
1697 if (sc->sc_rx_rate > sc->sc_tx_rate)
1698 evt = BWI_LED_EVENT_RX;
1699 else
1700 evt = BWI_LED_EVENT_TX;
1701 } else if (tx) {
1702 evt = BWI_LED_EVENT_TX;
1703 } else if (rx_data > 0) {
1704 evt = BWI_LED_EVENT_RX;
1705 } else if (rx_data == 0) {
1706 evt = BWI_LED_EVENT_POLL;
1707 }
1708
1709 if (evt != BWI_LED_EVENT_NONE)
1710 bwi_led_event(sc, evt);
1711 }
1712
1713 BWI_UNLOCK(sc);
1714 }
1715
1716 static void
1717 bwi_scan_start(struct ieee80211com *ic)
1718 {
1719 struct bwi_softc *sc = ic->ic_ifp->if_softc;
1720
1721 BWI_LOCK(sc);
1722 /* Enable MAC beacon promiscuity */
1723 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1724 BWI_UNLOCK(sc);
1725 }
1726
1727 static void
1728 bwi_set_channel(struct ieee80211com *ic)
1729 {
1730 struct bwi_softc *sc = ic->ic_ifp->if_softc;
1731 struct ieee80211_channel *c = ic->ic_curchan;
1732 struct bwi_mac *mac;
1733
1734 BWI_LOCK(sc);
1735 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1736 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1737 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1738 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0);
1739
1740 sc->sc_rates = ieee80211_get_ratetable(c);
1741
1742 /*
1743 * Setup radio tap channel freq and flags
1744 */
1745 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
1746 htole16(c->ic_freq);
1747 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
1748 htole16(c->ic_flags & 0xffff);
1749
1750 BWI_UNLOCK(sc);
1751 }
1752
1753 static void
1754 bwi_scan_end(struct ieee80211com *ic)
1755 {
1756 struct bwi_softc *sc = ic->ic_ifp->if_softc;
1757
1758 BWI_LOCK(sc);
1759 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1760 BWI_UNLOCK(sc);
1761 }
1762
1763 static int
1764 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1765 {
1766 struct bwi_vap *bvp = BWI_VAP(vap);
1767 struct ieee80211com *ic= vap->iv_ic;
1768 struct ifnet *ifp = ic->ic_ifp;
1769 enum ieee80211_state ostate = vap->iv_state;
1770 struct bwi_softc *sc = ifp->if_softc;
1771 struct bwi_mac *mac;
1772 int error;
1773
1774 BWI_LOCK(sc);
1775
1776 callout_stop(&sc->sc_calib_ch);
1777
1778 if (nstate == IEEE80211_S_INIT)
1779 sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1780
1781 bwi_led_newstate(sc, nstate);
1782
1783 error = bvp->bv_newstate(vap, nstate, arg);
1784 if (error != 0)
1785 goto back;
1786
1787 /*
1788 * Clear the BSSID when we stop a STA
1789 */
1790 if (vap->iv_opmode == IEEE80211_M_STA) {
1791 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) {
1792 /*
1793 * Clear out the BSSID. If we reassociate to
1794 * the same AP, this will reinialize things
1795 * correctly...
1796 */
1797 if (ic->ic_opmode == IEEE80211_M_STA &&
1798 !(sc->sc_flags & BWI_F_STOP))
1799 bwi_set_bssid(sc, bwi_zero_addr);
1800 }
1801 }
1802
1803 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
1804 /* Nothing to do */
1805 } else if (nstate == IEEE80211_S_RUN) {
1806 bwi_set_bssid(sc, vap->iv_bss->ni_bssid);
1807
1808 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1809 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1810 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1811
1812 /* Initial TX power calibration */
1813 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1814 #ifdef notyet
1815 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1816 #else
1817 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1818 #endif
1819
1820 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
1821 }
1822 back:
1823 BWI_UNLOCK(sc);
1824
1825 return error;
1826 }
1827
1828 static int
1829 bwi_media_change(struct ifnet *ifp)
1830 {
1831 int error = ieee80211_media_change(ifp);
1832 /* NB: only the fixed rate can change and that doesn't need a reset */
1833 return (error == ENETRESET ? 0 : error);
1834 }
1835
1836 static int
1837 bwi_dma_alloc(struct bwi_softc *sc)
1838 {
1839 int error, i, has_txstats;
1840 bus_addr_t lowaddr = 0;
1841 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1842 uint32_t txrx_ctrl_step = 0;
1843
1844 has_txstats = 0;
1845 for (i = 0; i < sc->sc_nmac; ++i) {
1846 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1847 has_txstats = 1;
1848 break;
1849 }
1850 }
1851
1852 switch (sc->sc_bus_space) {
1853 case BWI_BUS_SPACE_30BIT:
1854 case BWI_BUS_SPACE_32BIT:
1855 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1856 lowaddr = BWI_BUS_SPACE_MAXADDR;
1857 else
1858 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1859 desc_sz = sizeof(struct bwi_desc32);
1860 txrx_ctrl_step = 0x20;
1861
1862 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1863 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1864 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1865 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1866 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1867 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1868 sc->sc_rxeof = bwi_rxeof32;
1869 sc->sc_start_tx = bwi_start_tx32;
1870 if (has_txstats) {
1871 sc->sc_init_txstats = bwi_init_txstats32;
1872 sc->sc_free_txstats = bwi_free_txstats32;
1873 sc->sc_txeof_status = bwi_txeof_status32;
1874 }
1875 break;
1876
1877 case BWI_BUS_SPACE_64BIT:
1878 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
1879 desc_sz = sizeof(struct bwi_desc64);
1880 txrx_ctrl_step = 0x40;
1881
1882 sc->sc_init_tx_ring = bwi_init_tx_ring64;
1883 sc->sc_free_tx_ring = bwi_free_tx_ring64;
1884 sc->sc_init_rx_ring = bwi_init_rx_ring64;
1885 sc->sc_free_rx_ring = bwi_free_rx_ring64;
1886 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1887 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1888 sc->sc_rxeof = bwi_rxeof64;
1889 sc->sc_start_tx = bwi_start_tx64;
1890 if (has_txstats) {
1891 sc->sc_init_txstats = bwi_init_txstats64;
1892 sc->sc_free_txstats = bwi_free_txstats64;
1893 sc->sc_txeof_status = bwi_txeof_status64;
1894 }
1895 break;
1896 }
1897
1898 KASSERT(lowaddr != 0, ("lowaddr zero"));
1899 KASSERT(desc_sz != 0, ("desc_sz zero"));
1900 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero"));
1901
1902 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
1903 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
1904
1905 /*
1906 * Create top level DMA tag
1907 */
1908 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
1909 BWI_ALIGN, 0, /* alignment, bounds */
1910 lowaddr, /* lowaddr */
1911 BUS_SPACE_MAXADDR, /* highaddr */
1912 NULL, NULL, /* filter, filterarg */
1913 MAXBSIZE, /* maxsize */
1914 BUS_SPACE_UNRESTRICTED, /* nsegments */
1915 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1916 BUS_DMA_ALLOCNOW, /* flags */
1917 NULL, NULL, /* lockfunc, lockarg */
1918 &sc->sc_parent_dtag);
1919 if (error) {
1920 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
1921 return error;
1922 }
1923
1924 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
1925
1926 /*
1927 * Create TX ring DMA stuffs
1928 */
1929 error = bus_dma_tag_create(sc->sc_parent_dtag,
1930 BWI_RING_ALIGN, 0,
1931 BUS_SPACE_MAXADDR,
1932 BUS_SPACE_MAXADDR,
1933 NULL, NULL,
1934 tx_ring_sz,
1935 1,
1936 BUS_SPACE_MAXSIZE_32BIT,
1937 BUS_DMA_ALLOCNOW,
1938 NULL, NULL,
1939 &sc->sc_txring_dtag);
1940 if (error) {
1941 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
1942 return error;
1943 }
1944
1945 for (i = 0; i < BWI_TX_NRING; ++i) {
1946 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
1947 &sc->sc_tx_rdata[i], tx_ring_sz,
1948 TXRX_CTRL(i));
1949 if (error) {
1950 device_printf(sc->sc_dev, "%dth TX ring "
1951 "DMA alloc failed\n", i);
1952 return error;
1953 }
1954 }
1955
1956 /*
1957 * Create RX ring DMA stuffs
1958 */
1959 error = bus_dma_tag_create(sc->sc_parent_dtag,
1960 BWI_RING_ALIGN, 0,
1961 BUS_SPACE_MAXADDR,
1962 BUS_SPACE_MAXADDR,
1963 NULL, NULL,
1964 rx_ring_sz,
1965 1,
1966 BUS_SPACE_MAXSIZE_32BIT,
1967 BUS_DMA_ALLOCNOW,
1968 NULL, NULL,
1969 &sc->sc_rxring_dtag);
1970 if (error) {
1971 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
1972 return error;
1973 }
1974
1975 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
1976 rx_ring_sz, TXRX_CTRL(0));
1977 if (error) {
1978 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
1979 return error;
1980 }
1981
1982 if (has_txstats) {
1983 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
1984 if (error) {
1985 device_printf(sc->sc_dev,
1986 "TX stats DMA alloc failed\n");
1987 return error;
1988 }
1989 }
1990
1991 #undef TXRX_CTRL
1992
1993 return bwi_dma_mbuf_create(sc);
1994 }
1995
1996 static void
1997 bwi_dma_free(struct bwi_softc *sc)
1998 {
1999 if (sc->sc_txring_dtag != NULL) {
2000 int i;
2001
2002 for (i = 0; i < BWI_TX_NRING; ++i) {
2003 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
2004
2005 if (rd->rdata_desc != NULL) {
2006 bus_dmamap_unload(sc->sc_txring_dtag,
2007 rd->rdata_dmap);
2008 bus_dmamem_free(sc->sc_txring_dtag,
2009 rd->rdata_desc,
2010 rd->rdata_dmap);
2011 }
2012 }
2013 bus_dma_tag_destroy(sc->sc_txring_dtag);
2014 }
2015
2016 if (sc->sc_rxring_dtag != NULL) {
2017 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2018
2019 if (rd->rdata_desc != NULL) {
2020 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2021 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2022 rd->rdata_dmap);
2023 }
2024 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2025 }
2026
2027 bwi_dma_txstats_free(sc);
2028 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2029
2030 if (sc->sc_parent_dtag != NULL)
2031 bus_dma_tag_destroy(sc->sc_parent_dtag);
2032 }
2033
2034 static int
2035 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2036 struct bwi_ring_data *rd, bus_size_t size,
2037 uint32_t txrx_ctrl)
2038 {
2039 int error;
2040
2041 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2042 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2043 &rd->rdata_dmap);
2044 if (error) {
2045 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2046 return error;
2047 }
2048
2049 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2050 bwi_dma_ring_addr, &rd->rdata_paddr,
2051 BUS_DMA_NOWAIT);
2052 if (error) {
2053 device_printf(sc->sc_dev, "can't load DMA mem\n");
2054 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2055 rd->rdata_desc = NULL;
2056 return error;
2057 }
2058
2059 rd->rdata_txrx_ctrl = txrx_ctrl;
2060 return 0;
2061 }
2062
2063 static int
2064 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2065 bus_size_t desc_sz)
2066 {
2067 struct bwi_txstats_data *st;
2068 bus_size_t dma_size;
2069 int error;
2070
2071 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO);
2072 if (st == NULL) {
2073 device_printf(sc->sc_dev, "can't allocate txstats data\n");
2074 return ENOMEM;
2075 }
2076 sc->sc_txstats = st;
2077
2078 /*
2079 * Create TX stats descriptor DMA stuffs
2080 */
2081 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2082
2083 error = bus_dma_tag_create(sc->sc_parent_dtag,
2084 BWI_RING_ALIGN,
2085 0,
2086 BUS_SPACE_MAXADDR,
2087 BUS_SPACE_MAXADDR,
2088 NULL, NULL,
2089 dma_size,
2090 1,
2091 BUS_SPACE_MAXSIZE_32BIT,
2092 BUS_DMA_ALLOCNOW,
2093 NULL, NULL,
2094 &st->stats_ring_dtag);
2095 if (error) {
2096 device_printf(sc->sc_dev, "can't create txstats ring "
2097 "DMA tag\n");
2098 return error;
2099 }
2100
2101 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2102 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2103 &st->stats_ring_dmap);
2104 if (error) {
2105 device_printf(sc->sc_dev, "can't allocate txstats ring "
2106 "DMA mem\n");
2107 bus_dma_tag_destroy(st->stats_ring_dtag);
2108 st->stats_ring_dtag = NULL;
2109 return error;
2110 }
2111
2112 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2113 st->stats_ring, dma_size,
2114 bwi_dma_ring_addr, &st->stats_ring_paddr,
2115 BUS_DMA_NOWAIT);
2116 if (error) {
2117 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2118 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2119 st->stats_ring_dmap);
2120 bus_dma_tag_destroy(st->stats_ring_dtag);
2121 st->stats_ring_dtag = NULL;
2122 return error;
2123 }
2124
2125 /*
2126 * Create TX stats DMA stuffs
2127 */
2128 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2129 BWI_ALIGN);
2130
2131 error = bus_dma_tag_create(sc->sc_parent_dtag,
2132 BWI_ALIGN,
2133 0,
2134 BUS_SPACE_MAXADDR,
2135 BUS_SPACE_MAXADDR,
2136 NULL, NULL,
2137 dma_size,
2138 1,
2139 BUS_SPACE_MAXSIZE_32BIT,
2140 BUS_DMA_ALLOCNOW,
2141 NULL, NULL,
2142 &st->stats_dtag);
2143 if (error) {
2144 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2145 return error;
2146 }
2147
2148 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2149 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2150 &st->stats_dmap);
2151 if (error) {
2152 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2153 bus_dma_tag_destroy(st->stats_dtag);
2154 st->stats_dtag = NULL;
2155 return error;
2156 }
2157
2158 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2159 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2160 BUS_DMA_NOWAIT);
2161 if (error) {
2162 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2163 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2164 bus_dma_tag_destroy(st->stats_dtag);
2165 st->stats_dtag = NULL;
2166 return error;
2167 }
2168
2169 st->stats_ctrl_base = ctrl_base;
2170 return 0;
2171 }
2172
2173 static void
2174 bwi_dma_txstats_free(struct bwi_softc *sc)
2175 {
2176 struct bwi_txstats_data *st;
2177
2178 if (sc->sc_txstats == NULL)
2179 return;
2180 st = sc->sc_txstats;
2181
2182 if (st->stats_ring_dtag != NULL) {
2183 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2184 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2185 st->stats_ring_dmap);
2186 bus_dma_tag_destroy(st->stats_ring_dtag);
2187 }
2188
2189 if (st->stats_dtag != NULL) {
2190 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2191 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2192 bus_dma_tag_destroy(st->stats_dtag);
2193 }
2194
2195 free(st, M_DEVBUF);
2196 }
2197
2198 static void
2199 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2200 {
2201 KASSERT(nseg == 1, ("too many segments\n"));
2202 *((bus_addr_t *)arg) = seg->ds_addr;
2203 }
2204
2205 static int
2206 bwi_dma_mbuf_create(struct bwi_softc *sc)
2207 {
2208 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2209 int i, j, k, ntx, error;
2210
2211 /*
2212 * Create TX/RX mbuf DMA tag
2213 */
2214 error = bus_dma_tag_create(sc->sc_parent_dtag,
2215 1,
2216 0,
2217 BUS_SPACE_MAXADDR,
2218 BUS_SPACE_MAXADDR,
2219 NULL, NULL,
2220 MCLBYTES,
2221 1,
2222 BUS_SPACE_MAXSIZE_32BIT,
2223 BUS_DMA_ALLOCNOW,
2224 NULL, NULL,
2225 &sc->sc_buf_dtag);
2226 if (error) {
2227 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2228 return error;
2229 }
2230
2231 ntx = 0;
2232
2233 /*
2234 * Create TX mbuf DMA map
2235 */
2236 for (i = 0; i < BWI_TX_NRING; ++i) {
2237 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2238
2239 for (j = 0; j < BWI_TX_NDESC; ++j) {
2240 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2241 &tbd->tbd_buf[j].tb_dmap);
2242 if (error) {
2243 device_printf(sc->sc_dev, "can't create "
2244 "%dth tbd, %dth DMA map\n", i, j);
2245
2246 ntx = i;
2247 for (k = 0; k < j; ++k) {
2248 bus_dmamap_destroy(sc->sc_buf_dtag,
2249 tbd->tbd_buf[k].tb_dmap);
2250 }
2251 goto fail;
2252 }
2253 }
2254 }
2255 ntx = BWI_TX_NRING;
2256
2257 /*
2258 * Create RX mbuf DMA map and a spare DMA map
2259 */
2260 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2261 &rbd->rbd_tmp_dmap);
2262 if (error) {
2263 device_printf(sc->sc_dev,
2264 "can't create spare RX buf DMA map\n");
2265 goto fail;
2266 }
2267
2268 for (j = 0; j < BWI_RX_NDESC; ++j) {
2269 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2270 &rbd->rbd_buf[j].rb_dmap);
2271 if (error) {
2272 device_printf(sc->sc_dev, "can't create %dth "
2273 "RX buf DMA map\n", j);
2274
2275 for (k = 0; k < j; ++k) {
2276 bus_dmamap_destroy(sc->sc_buf_dtag,
2277 rbd->rbd_buf[j].rb_dmap);
2278 }
2279 bus_dmamap_destroy(sc->sc_buf_dtag,
2280 rbd->rbd_tmp_dmap);
2281 goto fail;
2282 }
2283 }
2284
2285 return 0;
2286 fail:
2287 bwi_dma_mbuf_destroy(sc, ntx, 0);
2288 return error;
2289 }
2290
2291 static void
2292 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2293 {
2294 int i, j;
2295
2296 if (sc->sc_buf_dtag == NULL)
2297 return;
2298
2299 for (i = 0; i < ntx; ++i) {
2300 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2301
2302 for (j = 0; j < BWI_TX_NDESC; ++j) {
2303 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2304
2305 if (tb->tb_mbuf != NULL) {
2306 bus_dmamap_unload(sc->sc_buf_dtag,
2307 tb->tb_dmap);
2308 m_freem(tb->tb_mbuf);
2309 }
2310 if (tb->tb_ni != NULL)
2311 ieee80211_free_node(tb->tb_ni);
2312 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2313 }
2314 }
2315
2316 if (nrx) {
2317 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2318
2319 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2320 for (j = 0; j < BWI_RX_NDESC; ++j) {
2321 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2322
2323 if (rb->rb_mbuf != NULL) {
2324 bus_dmamap_unload(sc->sc_buf_dtag,
2325 rb->rb_dmap);
2326 m_freem(rb->rb_mbuf);
2327 }
2328 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2329 }
2330 }
2331
2332 bus_dma_tag_destroy(sc->sc_buf_dtag);
2333 sc->sc_buf_dtag = NULL;
2334 }
2335
2336 static void
2337 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2338 {
2339 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2340 }
2341
2342 static void
2343 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2344 {
2345 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2346 }
2347
2348 static int
2349 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2350 {
2351 struct bwi_ring_data *rd;
2352 struct bwi_txbuf_data *tbd;
2353 uint32_t val, addr_hi, addr_lo;
2354
2355 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2356 rd = &sc->sc_tx_rdata[ring_idx];
2357 tbd = &sc->sc_tx_bdata[ring_idx];
2358
2359 tbd->tbd_idx = 0;
2360 tbd->tbd_used = 0;
2361
2362 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2363 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2364 BUS_DMASYNC_PREWRITE);
2365
2366 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2367 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2368
2369 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2370 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2371 BWI_TXRX32_RINGINFO_FUNC_MASK);
2372 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2373
2374 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2375 BWI_TXRX32_CTRL_ENABLE;
2376 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2377
2378 return 0;
2379 }
2380
2381 static void
2382 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2383 bus_addr_t paddr, int hdr_size, int ndesc)
2384 {
2385 uint32_t val, addr_hi, addr_lo;
2386
2387 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2388 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2389
2390 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2391 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2392 BWI_TXRX32_RINGINFO_FUNC_MASK);
2393 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2394
2395 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2396 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2397 BWI_TXRX32_CTRL_ENABLE;
2398 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2399
2400 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2401 (ndesc - 1) * sizeof(struct bwi_desc32));
2402 }
2403
2404 static int
2405 bwi_init_rx_ring32(struct bwi_softc *sc)
2406 {
2407 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2408 int i, error;
2409
2410 sc->sc_rx_bdata.rbd_idx = 0;
2411
2412 for (i = 0; i < BWI_RX_NDESC; ++i) {
2413 error = bwi_newbuf(sc, i, 1);
2414 if (error) {
2415 device_printf(sc->sc_dev,
2416 "can't allocate %dth RX buffer\n", i);
2417 return error;
2418 }
2419 }
2420 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2421 BUS_DMASYNC_PREWRITE);
2422
2423 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2424 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2425 return 0;
2426 }
2427
2428 static int
2429 bwi_init_txstats32(struct bwi_softc *sc)
2430 {
2431 struct bwi_txstats_data *st = sc->sc_txstats;
2432 bus_addr_t stats_paddr;
2433 int i;
2434
2435 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2436 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2437
2438 st->stats_idx = 0;
2439
2440 stats_paddr = st->stats_paddr;
2441 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2442 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2443 stats_paddr, sizeof(struct bwi_txstats), 0);
2444 stats_paddr += sizeof(struct bwi_txstats);
2445 }
2446 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2447 BUS_DMASYNC_PREWRITE);
2448
2449 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2450 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2451 return 0;
2452 }
2453
2454 static void
2455 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2456 int buf_len)
2457 {
2458 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2459
2460 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2461 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2462 paddr, buf_len, 0);
2463 }
2464
2465 static void
2466 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2467 int buf_idx, bus_addr_t paddr, int buf_len)
2468 {
2469 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
2470 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2471 paddr, buf_len, 1);
2472 }
2473
2474 static int
2475 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2476 {
2477 /* TODO:64 */
2478 return EOPNOTSUPP;
2479 }
2480
2481 static int
2482 bwi_init_rx_ring64(struct bwi_softc *sc)
2483 {
2484 /* TODO:64 */
2485 return EOPNOTSUPP;
2486 }
2487
2488 static int
2489 bwi_init_txstats64(struct bwi_softc *sc)
2490 {
2491 /* TODO:64 */
2492 return EOPNOTSUPP;
2493 }
2494
2495 static void
2496 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2497 int buf_len)
2498 {
2499 /* TODO:64 */
2500 }
2501
2502 static void
2503 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2504 int buf_idx, bus_addr_t paddr, int buf_len)
2505 {
2506 /* TODO:64 */
2507 }
2508
2509 static void
2510 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2511 bus_size_t mapsz __unused, int error)
2512 {
2513 if (!error) {
2514 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2515 *((bus_addr_t *)arg) = seg->ds_addr;
2516 }
2517 }
2518
2519 static int
2520 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2521 {
2522 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2523 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2524 struct bwi_rxbuf_hdr *hdr;
2525 bus_dmamap_t map;
2526 bus_addr_t paddr;
2527 struct mbuf *m;
2528 int error;
2529
2530 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2531
2532 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2533 if (m == NULL) {
2534 error = ENOBUFS;
2535
2536 /*
2537 * If the NIC is up and running, we need to:
2538 * - Clear RX buffer's header.
2539 * - Restore RX descriptor settings.
2540 */
2541 if (init)
2542 return error;
2543 else
2544 goto back;
2545 }
2546 m->m_len = m->m_pkthdr.len = MCLBYTES;
2547
2548 /*
2549 * Try to load RX buf into temporary DMA map
2550 */
2551 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2552 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
2553 if (error) {
2554 m_freem(m);
2555
2556 /*
2557 * See the comment above
2558 */
2559 if (init)
2560 return error;
2561 else
2562 goto back;
2563 }
2564
2565 if (!init)
2566 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2567 rxbuf->rb_mbuf = m;
2568 rxbuf->rb_paddr = paddr;
2569
2570 /*
2571 * Swap RX buf's DMA map with the loaded temporary one
2572 */
2573 map = rxbuf->rb_dmap;
2574 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2575 rbd->rbd_tmp_dmap = map;
2576
2577 back:
2578 /*
2579 * Clear RX buf header
2580 */
2581 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2582 bzero(hdr, sizeof(*hdr));
2583 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2584
2585 /*
2586 * Setup RX buf descriptor
2587 */
2588 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2589 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2590 return error;
2591 }
2592
2593 static void
2594 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2595 const uint8_t *addr)
2596 {
2597 int i;
2598
2599 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2600 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2601
2602 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2603 uint16_t addr_val;
2604
2605 addr_val = (uint16_t)addr[i * 2] |
2606 (((uint16_t)addr[(i * 2) + 1]) << 8);
2607 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2608 }
2609 }
2610
2611 static int
2612 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2613 {
2614 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2615 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2616 struct ifnet *ifp = sc->sc_ifp;
2617 struct ieee80211com *ic = ifp->if_l2com;
2618 int idx, rx_data = 0;
2619
2620 idx = rbd->rbd_idx;
2621 while (idx != end_idx) {
2622 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2623 struct bwi_rxbuf_hdr *hdr;
2624 struct ieee80211_frame_min *wh;
2625 struct ieee80211_node *ni;
2626 struct mbuf *m;
2627 const void *plcp;
2628 uint16_t flags2;
2629 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate;
2630
2631 m = rb->rb_mbuf;
2632 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2633 BUS_DMASYNC_POSTREAD);
2634
2635 if (bwi_newbuf(sc, idx, 0)) {
2636 ifp->if_ierrors++;
2637 goto next;
2638 }
2639
2640 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2641 flags2 = le16toh(hdr->rxh_flags2);
2642
2643 hdr_extra = 0;
2644 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2645 hdr_extra = 2;
2646 wh_ofs = hdr_extra + 6; /* XXX magic number */
2647
2648 buflen = le16toh(hdr->rxh_buflen);
2649 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2650 if_printf(ifp, "%s: zero length data, hdr_extra %d\n",
2651 __func__, hdr_extra);
2652 ifp->if_ierrors++;
2653 m_freem(m);
2654 goto next;
2655 }
2656
2657 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra);
2658 rssi = bwi_calc_rssi(sc, hdr);
2659 noise = bwi_calc_noise(sc);
2660
2661 m->m_pkthdr.rcvif = ifp;
2662 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2663 m_adj(m, sizeof(*hdr) + wh_ofs);
2664
2665 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2666 rate = bwi_ofdm_plcp2rate(plcp);
2667 else
2668 rate = bwi_ds_plcp2rate(plcp);
2669
2670 /* RX radio tap */
2671 if (ieee80211_radiotap_active(ic))
2672 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi, noise);
2673
2674 m_adj(m, -IEEE80211_CRC_LEN);
2675
2676 BWI_UNLOCK(sc);
2677
2678 wh = mtod(m, struct ieee80211_frame_min *);
2679 ni = ieee80211_find_rxnode(ic, wh);
2680 if (ni != NULL) {
2681 type = ieee80211_input(ni, m, rssi - noise, noise);
2682 ieee80211_free_node(ni);
2683 } else
2684 type = ieee80211_input_all(ic, m, rssi - noise, noise);
2685 if (type == IEEE80211_FC0_TYPE_DATA) {
2686 rx_data = 1;
2687 sc->sc_rx_rate = rate;
2688 }
2689
2690 BWI_LOCK(sc);
2691 next:
2692 idx = (idx + 1) % BWI_RX_NDESC;
2693
2694 if (sc->sc_flags & BWI_F_STOP) {
2695 /*
2696 * Take the fast lane, don't do
2697 * any damage to softc
2698 */
2699 return -1;
2700 }
2701 }
2702
2703 rbd->rbd_idx = idx;
2704 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2705 BUS_DMASYNC_PREWRITE);
2706
2707 return rx_data;
2708 }
2709
2710 static int
2711 bwi_rxeof32(struct bwi_softc *sc)
2712 {
2713 uint32_t val, rx_ctrl;
2714 int end_idx, rx_data;
2715
2716 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2717
2718 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2719 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2720 sizeof(struct bwi_desc32);
2721
2722 rx_data = bwi_rxeof(sc, end_idx);
2723 if (rx_data >= 0) {
2724 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2725 end_idx * sizeof(struct bwi_desc32));
2726 }
2727 return rx_data;
2728 }
2729
2730 static int
2731 bwi_rxeof64(struct bwi_softc *sc)
2732 {
2733 /* TODO:64 */
2734 return 0;
2735 }
2736
2737 static void
2738 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2739 {
2740 int i;
2741
2742 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2743
2744 #define NRETRY 10
2745
2746 for (i = 0; i < NRETRY; ++i) {
2747 uint32_t status;
2748
2749 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2750 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2751 BWI_RX32_STATUS_STATE_DISABLED)
2752 break;
2753
2754 DELAY(1000);
2755 }
2756 if (i == NRETRY)
2757 device_printf(sc->sc_dev, "reset rx ring timedout\n");
2758
2759 #undef NRETRY
2760
2761 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2762 }
2763
2764 static void
2765 bwi_free_txstats32(struct bwi_softc *sc)
2766 {
2767 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2768 }
2769
2770 static void
2771 bwi_free_rx_ring32(struct bwi_softc *sc)
2772 {
2773 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2774 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2775 int i;
2776
2777 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2778
2779 for (i = 0; i < BWI_RX_NDESC; ++i) {
2780 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2781
2782 if (rb->rb_mbuf != NULL) {
2783 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2784 m_freem(rb->rb_mbuf);
2785 rb->rb_mbuf = NULL;
2786 }
2787 }
2788 }
2789
2790 static void
2791 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2792 {
2793 struct bwi_ring_data *rd;
2794 struct bwi_txbuf_data *tbd;
2795 struct ifnet *ifp = sc->sc_ifp;
2796 uint32_t state, val;
2797 int i;
2798
2799 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2800 rd = &sc->sc_tx_rdata[ring_idx];
2801 tbd = &sc->sc_tx_bdata[ring_idx];
2802
2803 #define NRETRY 10
2804
2805 for (i = 0; i < NRETRY; ++i) {
2806 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2807 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2808 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2809 state == BWI_TX32_STATUS_STATE_IDLE ||
2810 state == BWI_TX32_STATUS_STATE_STOPPED)
2811 break;
2812
2813 DELAY(1000);
2814 }
2815 if (i == NRETRY) {
2816 if_printf(ifp, "%s: wait for TX ring(%d) stable timed out\n",
2817 __func__, ring_idx);
2818 }
2819
2820 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2821 for (i = 0; i < NRETRY; ++i) {
2822 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2823 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2824 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2825 break;
2826
2827 DELAY(1000);
2828 }
2829 if (i == NRETRY)
2830 if_printf(ifp, "%s: reset TX ring (%d) timed out\n",
2831 __func__, ring_idx);
2832
2833 #undef NRETRY
2834
2835 DELAY(1000);
2836
2837 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2838
2839 for (i = 0; i < BWI_TX_NDESC; ++i) {
2840 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2841
2842 if (tb->tb_mbuf != NULL) {
2843 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2844 m_freem(tb->tb_mbuf);
2845 tb->tb_mbuf = NULL;
2846 }
2847 if (tb->tb_ni != NULL) {
2848 ieee80211_free_node(tb->tb_ni);
2849 tb->tb_ni = NULL;
2850 }
2851 }
2852 }
2853
2854 static void
2855 bwi_free_txstats64(struct bwi_softc *sc)
2856 {
2857 /* TODO:64 */
2858 }
2859
2860 static void
2861 bwi_free_rx_ring64(struct bwi_softc *sc)
2862 {
2863 /* TODO:64 */
2864 }
2865
2866 static void
2867 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2868 {
2869 /* TODO:64 */
2870 }
2871
2872 /* XXX does not belong here */
2873 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
2874 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
2875
2876 static __inline void
2877 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
2878 {
2879 uint32_t plcp;
2880
2881 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM),
2882 IEEE80211_OFDM_PLCP_RATE_MASK) |
2883 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
2884 *plcp0 = htole32(plcp);
2885 }
2886
2887 static __inline void
2888 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
2889 uint8_t rate)
2890 {
2891 int len, service, pkt_bitlen;
2892
2893 pkt_bitlen = pkt_len * NBBY;
2894 len = howmany(pkt_bitlen * 2, rate);
2895
2896 service = IEEE80211_PLCP_SERVICE_LOCKED;
2897 if (rate == (11 * 2)) {
2898 int pkt_bitlen1;
2899
2900 /*
2901 * PLCP service field needs to be adjusted,
2902 * if TX rate is 11Mbytes/s
2903 */
2904 pkt_bitlen1 = len * 11;
2905 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
2906 service |= IEEE80211_PLCP_SERVICE_LENEXT7;
2907 }
2908
2909 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK);
2910 plcp->i_service = service;
2911 plcp->i_length = htole16(len);
2912 /* NOTE: do NOT touch i_crc */
2913 }
2914
2915 static __inline void
2916 bwi_plcp_header(const struct ieee80211_rate_table *rt,
2917 void *plcp, int pkt_len, uint8_t rate)
2918 {
2919 enum ieee80211_phytype modtype;
2920
2921 /*
2922 * Assume caller has zeroed 'plcp'
2923 */
2924 modtype = ieee80211_rate2phytype(rt, rate);
2925 if (modtype == IEEE80211_T_OFDM)
2926 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
2927 else if (modtype == IEEE80211_T_DS)
2928 bwi_ds_plcp_header(plcp, pkt_len, rate);
2929 else
2930 panic("unsupport modulation type %u\n", modtype);
2931 }
2932
2933 static int
2934 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2935 struct ieee80211_node *ni)
2936 {
2937 struct ieee80211vap *vap = ni->ni_vap;
2938 struct ifnet *ifp = sc->sc_ifp;
2939 struct ieee80211com *ic = ifp->if_l2com;
2940 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2941 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2942 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2943 struct bwi_mac *mac;
2944 struct bwi_txbuf_hdr *hdr;
2945 struct ieee80211_frame *wh;
2946 const struct ieee80211_txparam *tp;
2947 uint8_t rate, rate_fb;
2948 uint32_t mac_ctrl;
2949 uint16_t phy_ctrl;
2950 bus_addr_t paddr;
2951 int type, ismcast, pkt_len, error, rix;
2952 #if 0
2953 const uint8_t *p;
2954 int i;
2955 #endif
2956
2957 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
2958 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
2959 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2960
2961 wh = mtod(m, struct ieee80211_frame *);
2962 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2963 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
2964
2965 /* Get 802.11 frame len before prepending TX header */
2966 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2967
2968 /*
2969 * Find TX rate
2970 */
2971 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
2972 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) {
2973 rate = rate_fb = tp->mgmtrate;
2974 } else if (ismcast) {
2975 rate = rate_fb = tp->mcastrate;
2976 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
2977 rate = rate_fb = tp->ucastrate;
2978 } else {
2979 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len);
2980 rate = ni->ni_txrate;
2981
2982 if (rix > 0) {
2983 rate_fb = ni->ni_rates.rs_rates[rix-1] &
2984 IEEE80211_RATE_VAL;
2985 } else {
2986 rate_fb = rate;
2987 }
2988 }
2989 tb->tb_rate[0] = rate;
2990 tb->tb_rate[1] = rate_fb;
2991 sc->sc_tx_rate = rate;
2992
2993 /*
2994 * TX radio tap
2995 */
2996 if (ieee80211_radiotap_active_vap(vap)) {
2997 sc->sc_tx_th.wt_flags = 0;
2998 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
2999 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3000 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS &&
3001 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3002 rate != (1 * 2)) {
3003 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3004 }
3005 sc->sc_tx_th.wt_rate = rate;
3006
3007 ieee80211_radiotap_tx(vap, m);
3008 }
3009
3010 /*
3011 * Setup the embedded TX header
3012 */
3013 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT);
3014 if (m == NULL) {
3015 if_printf(ifp, "%s: prepend TX header failed\n", __func__);
3016 return ENOBUFS;
3017 }
3018 hdr = mtod(m, struct bwi_txbuf_hdr *);
3019
3020 bzero(hdr, sizeof(*hdr));
3021
3022 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3023 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3024
3025 if (!ismcast) {
3026 uint16_t dur;
3027
3028 dur = ieee80211_ack_duration(sc->sc_rates, rate,
3029 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
3030
3031 hdr->txh_fb_duration = htole16(dur);
3032 }
3033
3034 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3035 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3036
3037 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3038 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3039
3040 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3041 BWI_TXH_PHY_C_ANTMODE_MASK);
3042 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM)
3043 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3044 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3045 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3046
3047 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3048 if (!ismcast)
3049 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3050 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM)
3051 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3052
3053 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3054 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3055
3056 /* Catch any further usage */
3057 hdr = NULL;
3058 wh = NULL;
3059
3060 /* DMA load */
3061 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3062 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3063 if (error && error != EFBIG) {
3064 if_printf(ifp, "%s: can't load TX buffer (1) %d\n",
3065 __func__, error);
3066 goto back;
3067 }
3068
3069 if (error) { /* error == EFBIG */
3070 struct mbuf *m_new;
3071
3072 m_new = m_defrag(m, M_DONTWAIT);
3073 if (m_new == NULL) {
3074 if_printf(ifp, "%s: can't defrag TX buffer\n",
3075 __func__);
3076 error = ENOBUFS;
3077 goto back;
3078 } else {
3079 m = m_new;
3080 }
3081
3082 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3083 bwi_dma_buf_addr, &paddr,
3084 BUS_DMA_NOWAIT);
3085 if (error) {
3086 if_printf(ifp, "%s: can't load TX buffer (2) %d\n",
3087 __func__, error);
3088 goto back;
3089 }
3090 }
3091 error = 0;
3092
3093 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3094
3095 tb->tb_mbuf = m;
3096 tb->tb_ni = ni;
3097
3098 #if 0
3099 p = mtod(m, const uint8_t *);
3100 for (i = 0; i < m->m_pkthdr.len; ++i) {
3101 if (i != 0 && i % 8 == 0)
3102 printf("\n");
3103 printf("%02x ", p[i]);
3104 }
3105 printf("\n");
3106 #endif
3107 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3108 idx, pkt_len, m->m_pkthdr.len);
3109
3110 /* Setup TX descriptor */
3111 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3112 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3113 BUS_DMASYNC_PREWRITE);
3114
3115 /* Kick start */
3116 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3117
3118 back:
3119 if (error)
3120 m_freem(m);
3121 return error;
3122 }
3123
3124 static int
3125 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m,
3126 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
3127 {
3128 struct ifnet *ifp = sc->sc_ifp;
3129 struct ieee80211vap *vap = ni->ni_vap;
3130 struct ieee80211com *ic = ni->ni_ic;
3131 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
3132 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
3133 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3134 struct bwi_mac *mac;
3135 struct bwi_txbuf_hdr *hdr;
3136 struct ieee80211_frame *wh;
3137 uint8_t rate, rate_fb;
3138 uint32_t mac_ctrl;
3139 uint16_t phy_ctrl;
3140 bus_addr_t paddr;
3141 int ismcast, pkt_len, error;
3142
3143 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3144 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3145 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3146
3147 wh = mtod(m, struct ieee80211_frame *);
3148 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3149
3150 /* Get 802.11 frame len before prepending TX header */
3151 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3152
3153 /*
3154 * Find TX rate
3155 */
3156 rate = params->ibp_rate0;
3157 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
3158 /* XXX fall back to mcast/mgmt rate? */
3159 m_freem(m);
3160 return EINVAL;
3161 }
3162 if (params->ibp_try1 != 0) {
3163 rate_fb = params->ibp_rate1;
3164 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) {
3165 /* XXX fall back to rate0? */
3166 m_freem(m);
3167 return EINVAL;
3168 }
3169 } else
3170 rate_fb = rate;
3171 tb->tb_rate[0] = rate;
3172 tb->tb_rate[1] = rate_fb;
3173 sc->sc_tx_rate = rate;
3174
3175 /*
3176 * TX radio tap
3177 */
3178 if (ieee80211_radiotap_active_vap(vap)) {
3179 sc->sc_tx_th.wt_flags = 0;
3180 /* XXX IEEE80211_BPF_CRYPTO */
3181 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3182 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3183 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3184 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3185 sc->sc_tx_th.wt_rate = rate;
3186
3187 ieee80211_radiotap_tx(vap, m);
3188 }
3189
3190 /*
3191 * Setup the embedded TX header
3192 */
3193 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT);
3194 if (m == NULL) {
3195 if_printf(ifp, "%s: prepend TX header failed\n", __func__);
3196 return ENOBUFS;
3197 }
3198 hdr = mtod(m, struct bwi_txbuf_hdr *);
3199
3200 bzero(hdr, sizeof(*hdr));
3201
3202 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3203 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3204
3205 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3206 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
3207 uint16_t dur;
3208
3209 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0);
3210
3211 hdr->txh_fb_duration = htole16(dur);
3212 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3213 }
3214
3215 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3216 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3217
3218 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3219 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3220
3221 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3222 BWI_TXH_PHY_C_ANTMODE_MASK);
3223 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) {
3224 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3225 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3226 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3227 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3228
3229 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3230 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3231
3232 /* Catch any further usage */
3233 hdr = NULL;
3234 wh = NULL;
3235
3236 /* DMA load */
3237 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3238 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3239 if (error != 0) {
3240 struct mbuf *m_new;
3241
3242 if (error != EFBIG) {
3243 if_printf(ifp, "%s: can't load TX buffer (1) %d\n",
3244 __func__, error);
3245 goto back;
3246 }
3247 m_new = m_defrag(m, M_DONTWAIT);
3248 if (m_new == NULL) {
3249 if_printf(ifp, "%s: can't defrag TX buffer\n",
3250 __func__);
3251 error = ENOBUFS;
3252 goto back;
3253 }
3254 m = m_new;
3255 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3256 bwi_dma_buf_addr, &paddr,
3257 BUS_DMA_NOWAIT);
3258 if (error) {
3259 if_printf(ifp, "%s: can't load TX buffer (2) %d\n",
3260 __func__, error);
3261 goto back;
3262 }
3263 }
3264
3265 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3266
3267 tb->tb_mbuf = m;
3268 tb->tb_ni = ni;
3269
3270 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3271 idx, pkt_len, m->m_pkthdr.len);
3272
3273 /* Setup TX descriptor */
3274 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3275 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3276 BUS_DMASYNC_PREWRITE);
3277
3278 /* Kick start */
3279 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3280 back:
3281 if (error)
3282 m_freem(m);
3283 return error;
3284 }
3285
3286 static void
3287 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3288 {
3289 idx = (idx + 1) % BWI_TX_NDESC;
3290 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3291 idx * sizeof(struct bwi_desc32));
3292 }
3293
3294 static void
3295 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3296 {
3297 /* TODO:64 */
3298 }
3299
3300 static void
3301 bwi_txeof_status32(struct bwi_softc *sc)
3302 {
3303 struct ifnet *ifp = sc->sc_ifp;
3304 uint32_t val, ctrl_base;
3305 int end_idx;
3306
3307 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3308
3309 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3310 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3311 sizeof(struct bwi_desc32);
3312
3313 bwi_txeof_status(sc, end_idx);
3314
3315 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3316 end_idx * sizeof(struct bwi_desc32));
3317
3318 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0)
3319 ifp->if_start(ifp);
3320 }
3321
3322 static void
3323 bwi_txeof_status64(struct bwi_softc *sc)
3324 {
3325 /* TODO:64 */
3326 }
3327
3328 static void
3329 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3330 {
3331 struct ifnet *ifp = sc->sc_ifp;
3332 struct bwi_txbuf_data *tbd;
3333 struct bwi_txbuf *tb;
3334 int ring_idx, buf_idx;
3335 struct ieee80211_node *ni;
3336 struct ieee80211vap *vap;
3337
3338 if (tx_id == 0) {
3339 if_printf(ifp, "%s: zero tx id\n", __func__);
3340 return;
3341 }
3342
3343 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3344 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3345
3346 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx));
3347 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
3348
3349 tbd = &sc->sc_tx_bdata[ring_idx];
3350 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used));
3351 tbd->tbd_used--;
3352
3353 tb = &tbd->tbd_buf[buf_idx];
3354 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3355 "acked %d, data_txcnt %d, ni %p\n",
3356 buf_idx, acked, data_txcnt, tb->tb_ni);
3357
3358 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3359
3360 ni = tb->tb_ni;
3361 if (tb->tb_ni != NULL) {
3362 const struct bwi_txbuf_hdr *hdr =
3363 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *);
3364 vap = ni->ni_vap;
3365
3366 /* NB: update rate control only for unicast frames */
3367 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) {
3368 /*
3369 * Feed back 'acked and data_txcnt'. Note that the
3370 * generic AMRR code only understands one tx rate
3371 * and the estimator doesn't handle real retry counts
3372 * well so to avoid over-aggressive downshifting we
3373 * treat any number of retries as "1".
3374 */
3375 ieee80211_ratectl_tx_complete(vap, ni,
3376 (data_txcnt > 1) ? IEEE80211_RATECTL_TX_SUCCESS :
3377 IEEE80211_RATECTL_TX_FAILURE, &acked, NULL);
3378 }
3379
3380 /*
3381 * Do any tx complete callback. Note this must
3382 * be done before releasing the node reference.
3383 */
3384 if (tb->tb_mbuf->m_flags & M_TXCB)
3385 ieee80211_process_callback(ni, tb->tb_mbuf, !acked);
3386
3387 ieee80211_free_node(tb->tb_ni);
3388 tb->tb_ni = NULL;
3389 }
3390 m_freem(tb->tb_mbuf);
3391 tb->tb_mbuf = NULL;
3392
3393 if (tbd->tbd_used == 0)
3394 ifp->if_timer = 0;
3395
3396 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3397 }
3398
3399 static void
3400 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3401 {
3402 struct bwi_txstats_data *st = sc->sc_txstats;
3403 int idx;
3404
3405 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3406
3407 idx = st->stats_idx;
3408 while (idx != end_idx) {
3409 const struct bwi_txstats *stats = &st->stats[idx];
3410
3411 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3412 int data_txcnt;
3413
3414 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3415 BWI_TXS_TXCNT_DATA);
3416 _bwi_txeof(sc, le16toh(stats->txs_id),
3417 stats->txs_flags & BWI_TXS_F_ACKED,
3418 data_txcnt);
3419 }
3420 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3421 }
3422 st->stats_idx = idx;
3423 }
3424
3425 static void
3426 bwi_txeof(struct bwi_softc *sc)
3427 {
3428 struct ifnet *ifp = sc->sc_ifp;
3429
3430 for (;;) {
3431 uint32_t tx_status0, tx_status1;
3432 uint16_t tx_id;
3433 int data_txcnt;
3434
3435 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3436 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3437 break;
3438 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3439
3440 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3441 data_txcnt = __SHIFTOUT(tx_status0,
3442 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3443
3444 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3445 continue;
3446
3447 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED,
3448 data_txcnt);
3449 }
3450
3451 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0)
3452 ifp->if_start(ifp);
3453 }
3454
3455 static int
3456 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3457 {
3458 bwi_power_on(sc, 1);
3459 return bwi_set_clock_mode(sc, clk_mode);
3460 }
3461
3462 static void
3463 bwi_bbp_power_off(struct bwi_softc *sc)
3464 {
3465 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3466 bwi_power_off(sc, 1);
3467 }
3468
3469 static int
3470 bwi_get_pwron_delay(struct bwi_softc *sc)
3471 {
3472 struct bwi_regwin *com, *old;
3473 struct bwi_clock_freq freq;
3474 uint32_t val;
3475 int error;
3476
3477 com = &sc->sc_com_regwin;
3478 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin"));
3479
3480 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3481 return 0;
3482
3483 error = bwi_regwin_switch(sc, com, &old);
3484 if (error)
3485 return error;
3486
3487 bwi_get_clock_freq(sc, &freq);
3488
3489 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3490 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3491 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3492
3493 return bwi_regwin_switch(sc, old, NULL);
3494 }
3495
3496 static int
3497 bwi_bus_attach(struct bwi_softc *sc)
3498 {
3499 struct bwi_regwin *bus, *old;
3500 int error;
3501
3502 bus = &sc->sc_bus_regwin;
3503
3504 error = bwi_regwin_switch(sc, bus, &old);
3505 if (error)
3506 return error;
3507
3508 if (!bwi_regwin_is_enabled(sc, bus))
3509 bwi_regwin_enable(sc, bus, 0);
3510
3511 /* Disable interripts */
3512 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3513
3514 return bwi_regwin_switch(sc, old, NULL);
3515 }
3516
3517 static const char *
3518 bwi_regwin_name(const struct bwi_regwin *rw)
3519 {
3520 switch (rw->rw_type) {
3521 case BWI_REGWIN_T_COM:
3522 return "COM";
3523 case BWI_REGWIN_T_BUSPCI:
3524 return "PCI";
3525 case BWI_REGWIN_T_MAC:
3526 return "MAC";
3527 case BWI_REGWIN_T_BUSPCIE:
3528 return "PCIE";
3529 }
3530 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3531 return NULL;
3532 }
3533
3534 static uint32_t
3535 bwi_regwin_disable_bits(struct bwi_softc *sc)
3536 {
3537 uint32_t busrev;
3538
3539 /* XXX cache this */
3540 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3541 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3542 "bus rev %u\n", busrev);
3543
3544 if (busrev == BWI_BUSREV_0)
3545 return BWI_STATE_LO_DISABLE1;
3546 else if (busrev == BWI_BUSREV_1)
3547 return BWI_STATE_LO_DISABLE2;
3548 else
3549 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3550 }
3551
3552 int
3553 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3554 {
3555 uint32_t val, disable_bits;
3556
3557 disable_bits = bwi_regwin_disable_bits(sc);
3558 val = CSR_READ_4(sc, BWI_STATE_LO);
3559
3560 if ((val & (BWI_STATE_LO_CLOCK |
3561 BWI_STATE_LO_RESET |
3562 disable_bits)) == BWI_STATE_LO_CLOCK) {
3563 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3564 bwi_regwin_name(rw));
3565 return 1;
3566 } else {
3567 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3568 bwi_regwin_name(rw));
3569 return 0;
3570 }
3571 }
3572
3573 void
3574 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3575 {
3576 uint32_t state_lo, disable_bits;
3577 int i;
3578
3579 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3580
3581 /*
3582 * If current regwin is in 'reset' state, it was already disabled.
3583 */
3584 if (state_lo & BWI_STATE_LO_RESET) {
3585 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3586 "%s was already disabled\n", bwi_regwin_name(rw));
3587 return;
3588 }
3589
3590 disable_bits = bwi_regwin_disable_bits(sc);
3591
3592 /*
3593 * Disable normal clock
3594 */
3595 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3596 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3597
3598 /*
3599 * Wait until normal clock is disabled
3600 */
3601 #define NRETRY 1000
3602 for (i = 0; i < NRETRY; ++i) {
3603 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3604 if (state_lo & disable_bits)
3605 break;
3606 DELAY(10);
3607 }
3608 if (i == NRETRY) {
3609 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3610 bwi_regwin_name(rw));
3611 }
3612
3613 for (i = 0; i < NRETRY; ++i) {
3614 uint32_t state_hi;
3615
3616 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3617 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3618 break;
3619 DELAY(10);
3620 }
3621 if (i == NRETRY) {
3622 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3623 bwi_regwin_name(rw));
3624 }
3625 #undef NRETRY
3626
3627 /*
3628 * Reset and disable regwin with gated clock
3629 */
3630 state_lo = BWI_STATE_LO_RESET | disable_bits |
3631 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3632 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3633 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3634
3635 /* Flush pending bus write */
3636 CSR_READ_4(sc, BWI_STATE_LO);
3637 DELAY(1);
3638
3639 /* Reset and disable regwin */
3640 state_lo = BWI_STATE_LO_RESET | disable_bits |
3641 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3642 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3643
3644 /* Flush pending bus write */
3645 CSR_READ_4(sc, BWI_STATE_LO);
3646 DELAY(1);
3647 }
3648
3649 void
3650 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3651 {
3652 uint32_t state_lo, state_hi, imstate;
3653
3654 bwi_regwin_disable(sc, rw, flags);
3655
3656 /* Reset regwin with gated clock */
3657 state_lo = BWI_STATE_LO_RESET |
3658 BWI_STATE_LO_CLOCK |
3659 BWI_STATE_LO_GATED_CLOCK |
3660 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3661 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3662
3663 /* Flush pending bus write */
3664 CSR_READ_4(sc, BWI_STATE_LO);
3665 DELAY(1);
3666
3667 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3668 if (state_hi & BWI_STATE_HI_SERROR)
3669 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3670
3671 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3672 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3673 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3674 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3675 }
3676
3677 /* Enable regwin with gated clock */
3678 state_lo = BWI_STATE_LO_CLOCK |
3679 BWI_STATE_LO_GATED_CLOCK |
3680 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3681 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3682
3683 /* Flush pending bus write */
3684 CSR_READ_4(sc, BWI_STATE_LO);
3685 DELAY(1);
3686
3687 /* Enable regwin with normal clock */
3688 state_lo = BWI_STATE_LO_CLOCK |
3689 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3690 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3691
3692 /* Flush pending bus write */
3693 CSR_READ_4(sc, BWI_STATE_LO);
3694 DELAY(1);
3695 }
3696
3697 static void
3698 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3699 {
3700 struct ifnet *ifp = sc->sc_ifp;
3701 struct bwi_mac *mac;
3702 struct bwi_myaddr_bssid buf;
3703 const uint8_t *p;
3704 uint32_t val;
3705 int n, i;
3706
3707 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3708 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3709 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3710
3711 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3712
3713 bcopy(IF_LLADDR(ifp), buf.myaddr, sizeof(buf.myaddr));
3714 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3715
3716 n = sizeof(buf) / sizeof(val);
3717 p = (const uint8_t *)&buf;
3718 for (i = 0; i < n; ++i) {
3719 int j;
3720
3721 val = 0;
3722 for (j = 0; j < sizeof(val); ++j)
3723 val |= ((uint32_t)(*p++)) << (j * 8);
3724
3725 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3726 }
3727 }
3728
3729 static void
3730 bwi_updateslot(struct ifnet *ifp)
3731 {
3732 struct bwi_softc *sc = ifp->if_softc;
3733 struct ieee80211com *ic = ifp->if_l2com;
3734 struct bwi_mac *mac;
3735
3736 BWI_LOCK(sc);
3737 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3738 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3739
3740 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3741 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3742 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3743
3744 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3745 }
3746 BWI_UNLOCK(sc);
3747 }
3748
3749 static void
3750 bwi_calibrate(void *xsc)
3751 {
3752 struct bwi_softc *sc = xsc;
3753 #ifdef INVARIANTS
3754 struct ifnet *ifp = sc->sc_ifp;
3755 struct ieee80211com *ic = ifp->if_l2com;
3756 #endif
3757 struct bwi_mac *mac;
3758
3759 BWI_ASSERT_LOCKED(sc);
3760
3761 KASSERT(ic->ic_opmode != IEEE80211_M_MONITOR,
3762 ("opmode %d", ic->ic_opmode));
3763
3764 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3765 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3766 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3767
3768 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3769 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3770
3771 /* XXX 15 seconds */
3772 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3773 }
3774
3775 static int
3776 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3777 {
3778 struct bwi_mac *mac;
3779
3780 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3781 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3782 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3783
3784 return bwi_rf_calc_rssi(mac, hdr);
3785 }
3786
3787 static int
3788 bwi_calc_noise(struct bwi_softc *sc)
3789 {
3790 struct bwi_mac *mac;
3791
3792 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3793 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3794 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3795
3796 return bwi_rf_calc_noise(mac);
3797 }
3798
3799 static __inline uint8_t
3800 bwi_ofdm_plcp2rate(const uint32_t *plcp0)
3801 {
3802 uint32_t plcp;
3803 uint8_t plcp_rate;
3804
3805 plcp = le32toh(*plcp0);
3806 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);
3807 return ieee80211_plcp2rate(plcp_rate, IEEE80211_T_OFDM);
3808 }
3809
3810 static __inline uint8_t
3811 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr)
3812 {
3813 return ieee80211_plcp2rate(hdr->i_signal, IEEE80211_T_DS);
3814 }
3815
3816 static void
3817 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3818 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise)
3819 {
3820 const struct ieee80211_frame_min *wh;
3821
3822 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3823 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3824 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3825
3826 wh = mtod(m, const struct ieee80211_frame_min *);
3827 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3828 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3829
3830 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */
3831 sc->sc_rx_th.wr_rate = rate;
3832 sc->sc_rx_th.wr_antsignal = rssi;
3833 sc->sc_rx_th.wr_antnoise = noise;
3834 }
3835
3836 static void
3837 bwi_led_attach(struct bwi_softc *sc)
3838 {
3839 const uint8_t *led_act = NULL;
3840 uint16_t gpio, val[BWI_LED_MAX];
3841 int i;
3842
3843 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
3844
3845 for (i = 0; i < N(bwi_vendor_led_act); ++i) {
3846 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3847 led_act = bwi_vendor_led_act[i].led_act;
3848 break;
3849 }
3850 }
3851 if (led_act == NULL)
3852 led_act = bwi_default_led_act;
3853
3854 #undef N
3855
3856 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3857 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3858 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3859
3860 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3861 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3862 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3863
3864 for (i = 0; i < BWI_LED_MAX; ++i) {
3865 struct bwi_led *led = &sc->sc_leds[i];
3866
3867 if (val[i] == 0xff) {
3868 led->l_act = led_act[i];
3869 } else {
3870 if (val[i] & BWI_LED_ACT_LOW)
3871 led->l_flags |= BWI_LED_F_ACTLOW;
3872 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3873 }
3874 led->l_mask = (1 << i);
3875
3876 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3877 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3878 led->l_act == BWI_LED_ACT_BLINK) {
3879 led->l_flags |= BWI_LED_F_BLINK;
3880 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3881 led->l_flags |= BWI_LED_F_POLLABLE;
3882 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3883 led->l_flags |= BWI_LED_F_SLOW;
3884
3885 if (sc->sc_blink_led == NULL) {
3886 sc->sc_blink_led = led;
3887 if (led->l_flags & BWI_LED_F_SLOW)
3888 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3889 }
3890 }
3891
3892 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3893 "%dth led, act %d, lowact %d\n", i,
3894 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3895 }
3896 callout_init(&sc->sc_led_blink_ch, CALLOUT_MPSAFE);
3897 }
3898
3899 static __inline uint16_t
3900 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3901 {
3902 if (led->l_flags & BWI_LED_F_ACTLOW)
3903 on = !on;
3904 if (on)
3905 val |= led->l_mask;
3906 else
3907 val &= ~led->l_mask;
3908 return val;
3909 }
3910
3911 static void
3912 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3913 {
3914 struct ifnet *ifp = sc->sc_ifp;
3915 struct ieee80211com *ic = ifp->if_l2com;
3916 uint16_t val;
3917 int i;
3918
3919 if (nstate == IEEE80211_S_INIT) {
3920 callout_stop(&sc->sc_led_blink_ch);
3921 sc->sc_led_blinking = 0;
3922 }
3923
3924 if ((ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3925 return;
3926
3927 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3928 for (i = 0; i < BWI_LED_MAX; ++i) {
3929 struct bwi_led *led = &sc->sc_leds[i];
3930 int on;
3931
3932 if (led->l_act == BWI_LED_ACT_UNKN ||
3933 led->l_act == BWI_LED_ACT_NULL)
3934 continue;
3935
3936 if ((led->l_flags & BWI_LED_F_BLINK) &&
3937 nstate != IEEE80211_S_INIT)
3938 continue;
3939
3940 switch (led->l_act) {
3941 case BWI_LED_ACT_ON: /* Always on */
3942 on = 1;
3943 break;
3944 case BWI_LED_ACT_OFF: /* Always off */
3945 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3946 on = 0;
3947 break;
3948 default:
3949 on = 1;
3950 switch (nstate) {
3951 case IEEE80211_S_INIT:
3952 on = 0;
3953 break;
3954 case IEEE80211_S_RUN:
3955 if (led->l_act == BWI_LED_ACT_11G &&
3956 ic->ic_curmode != IEEE80211_MODE_11G)
3957 on = 0;
3958 break;
3959 default:
3960 if (led->l_act == BWI_LED_ACT_ASSOC)
3961 on = 0;
3962 break;
3963 }
3964 break;
3965 }
3966
3967 val = bwi_led_onoff(led, val, on);
3968 }
3969 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3970 }
3971 static void
3972 bwi_led_event(struct bwi_softc *sc, int event)
3973 {
3974 struct bwi_led *led = sc->sc_blink_led;
3975 int rate;
3976
3977 if (event == BWI_LED_EVENT_POLL) {
3978 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3979 return;
3980 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3981 return;
3982 }
3983
3984 sc->sc_led_ticks = ticks;
3985 if (sc->sc_led_blinking)
3986 return;
3987
3988 switch (event) {
3989 case BWI_LED_EVENT_RX:
3990 rate = sc->sc_rx_rate;
3991 break;
3992 case BWI_LED_EVENT_TX:
3993 rate = sc->sc_tx_rate;
3994 break;
3995 case BWI_LED_EVENT_POLL:
3996 rate = 0;
3997 break;
3998 default:
3999 panic("unknown LED event %d\n", event);
4000 break;
4001 }
4002 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
4003 bwi_led_duration[rate].off_dur);
4004 }
4005
4006 static void
4007 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
4008 {
4009 struct bwi_led *led = sc->sc_blink_led;
4010 uint16_t val;
4011
4012 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
4013 val = bwi_led_onoff(led, val, 1);
4014 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
4015
4016 if (led->l_flags & BWI_LED_F_SLOW) {
4017 BWI_LED_SLOWDOWN(on_dur);
4018 BWI_LED_SLOWDOWN(off_dur);
4019 }
4020
4021 sc->sc_led_blinking = 1;
4022 sc->sc_led_blink_offdur = off_dur;
4023
4024 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
4025 }
4026
4027 static void
4028 bwi_led_blink_next(void *xsc)
4029 {
4030 struct bwi_softc *sc = xsc;
4031 uint16_t val;
4032
4033 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
4034 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
4035 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
4036
4037 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
4038 bwi_led_blink_end, sc);
4039 }
4040
4041 static void
4042 bwi_led_blink_end(void *xsc)
4043 {
4044 struct bwi_softc *sc = xsc;
4045 sc->sc_led_blinking = 0;
4046 }
4047
4048 static void
4049 bwi_restart(void *xsc, int pending)
4050 {
4051 struct bwi_softc *sc = xsc;
4052 struct ifnet *ifp = sc->sc_ifp;
4053
4054 if_printf(ifp, "%s begin, help!\n", __func__);
4055 BWI_LOCK(sc);
4056 bwi_init_statechg(xsc, 0);
4057 #if 0
4058 bwi_start_locked(ifp);
4059 #endif
4060 BWI_UNLOCK(sc);
4061 }
Cache object: 01afdc649d5f2a6d7a9e8ec711b39e68
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