FreeBSD/Linux Kernel Cross Reference
sys/dev/bwi/if_bwi.c
1 /*
2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $
35 */
36
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD: releng/9.0/sys/dev/bwi/if_bwi.c 217511 2011-01-17 20:15:15Z bschmidt $");
39
40 #include "opt_inet.h"
41 #include "opt_bwi.h"
42
43 #include <sys/param.h>
44 #include <sys/endian.h>
45 #include <sys/kernel.h>
46 #include <sys/bus.h>
47 #include <sys/malloc.h>
48 #include <sys/proc.h>
49 #include <sys/rman.h>
50 #include <sys/socket.h>
51 #include <sys/sockio.h>
52 #include <sys/sysctl.h>
53 #include <sys/systm.h>
54 #include <sys/taskqueue.h>
55
56 #include <net/if.h>
57 #include <net/if_dl.h>
58 #include <net/if_media.h>
59 #include <net/if_types.h>
60 #include <net/if_arp.h>
61 #include <net/ethernet.h>
62 #include <net/if_llc.h>
63
64 #include <net80211/ieee80211_var.h>
65 #include <net80211/ieee80211_radiotap.h>
66 #include <net80211/ieee80211_regdomain.h>
67 #include <net80211/ieee80211_phy.h>
68 #include <net80211/ieee80211_ratectl.h>
69
70 #include <net/bpf.h>
71
72 #ifdef INET
73 #include <netinet/in.h>
74 #include <netinet/if_ether.h>
75 #endif
76
77 #include <machine/bus.h>
78
79 #include <dev/pci/pcivar.h>
80 #include <dev/pci/pcireg.h>
81
82 #include <dev/bwi/bitops.h>
83 #include <dev/bwi/if_bwireg.h>
84 #include <dev/bwi/if_bwivar.h>
85 #include <dev/bwi/bwimac.h>
86 #include <dev/bwi/bwirf.h>
87
88 struct bwi_clock_freq {
89 u_int clkfreq_min;
90 u_int clkfreq_max;
91 };
92
93 struct bwi_myaddr_bssid {
94 uint8_t myaddr[IEEE80211_ADDR_LEN];
95 uint8_t bssid[IEEE80211_ADDR_LEN];
96 } __packed;
97
98 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *,
99 const char [IFNAMSIZ], int, int, int,
100 const uint8_t [IEEE80211_ADDR_LEN],
101 const uint8_t [IEEE80211_ADDR_LEN]);
102 static void bwi_vap_delete(struct ieee80211vap *);
103 static void bwi_init(void *);
104 static int bwi_ioctl(struct ifnet *, u_long, caddr_t);
105 static void bwi_start(struct ifnet *);
106 static void bwi_start_locked(struct ifnet *);
107 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *,
108 const struct ieee80211_bpf_params *);
109 static void bwi_watchdog(void *);
110 static void bwi_scan_start(struct ieee80211com *);
111 static void bwi_set_channel(struct ieee80211com *);
112 static void bwi_scan_end(struct ieee80211com *);
113 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int);
114 static void bwi_updateslot(struct ifnet *);
115 static int bwi_media_change(struct ifnet *);
116
117 static void bwi_calibrate(void *);
118
119 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
120 static int bwi_calc_noise(struct bwi_softc *);
121 static __inline uint8_t bwi_ofdm_plcp2rate(const uint32_t *);
122 static __inline uint8_t bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *);
123 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
124 struct bwi_rxbuf_hdr *, const void *, int, int, int);
125
126 static void bwi_restart(void *, int);
127 static void bwi_init_statechg(struct bwi_softc *, int);
128 static void bwi_stop(struct bwi_softc *, int);
129 static void bwi_stop_locked(struct bwi_softc *, int);
130 static int bwi_newbuf(struct bwi_softc *, int, int);
131 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
132 struct ieee80211_node *);
133 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *,
134 struct ieee80211_node *,
135 const struct ieee80211_bpf_params *);
136
137 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
138 bus_addr_t, int, int);
139 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
140
141 static int bwi_init_tx_ring32(struct bwi_softc *, int);
142 static int bwi_init_rx_ring32(struct bwi_softc *);
143 static int bwi_init_txstats32(struct bwi_softc *);
144 static void bwi_free_tx_ring32(struct bwi_softc *, int);
145 static void bwi_free_rx_ring32(struct bwi_softc *);
146 static void bwi_free_txstats32(struct bwi_softc *);
147 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
148 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
149 int, bus_addr_t, int);
150 static int bwi_rxeof32(struct bwi_softc *);
151 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
152 static void bwi_txeof_status32(struct bwi_softc *);
153
154 static int bwi_init_tx_ring64(struct bwi_softc *, int);
155 static int bwi_init_rx_ring64(struct bwi_softc *);
156 static int bwi_init_txstats64(struct bwi_softc *);
157 static void bwi_free_tx_ring64(struct bwi_softc *, int);
158 static void bwi_free_rx_ring64(struct bwi_softc *);
159 static void bwi_free_txstats64(struct bwi_softc *);
160 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
161 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
162 int, bus_addr_t, int);
163 static int bwi_rxeof64(struct bwi_softc *);
164 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
165 static void bwi_txeof_status64(struct bwi_softc *);
166
167 static int bwi_rxeof(struct bwi_softc *, int);
168 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
169 static void bwi_txeof(struct bwi_softc *);
170 static void bwi_txeof_status(struct bwi_softc *, int);
171 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
172 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
173
174 static int bwi_dma_alloc(struct bwi_softc *);
175 static void bwi_dma_free(struct bwi_softc *);
176 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
177 struct bwi_ring_data *, bus_size_t,
178 uint32_t);
179 static int bwi_dma_mbuf_create(struct bwi_softc *);
180 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
181 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
182 static void bwi_dma_txstats_free(struct bwi_softc *);
183 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
184 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
185 bus_size_t, int);
186
187 static void bwi_power_on(struct bwi_softc *, int);
188 static int bwi_power_off(struct bwi_softc *, int);
189 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
190 static int bwi_set_clock_delay(struct bwi_softc *);
191 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
192 static int bwi_get_pwron_delay(struct bwi_softc *sc);
193 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
194 const uint8_t *);
195 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
196
197 static void bwi_get_card_flags(struct bwi_softc *);
198 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
199
200 static int bwi_bus_attach(struct bwi_softc *);
201 static int bwi_bbp_attach(struct bwi_softc *);
202 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
203 static void bwi_bbp_power_off(struct bwi_softc *);
204
205 static const char *bwi_regwin_name(const struct bwi_regwin *);
206 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
207 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
208 static int bwi_regwin_select(struct bwi_softc *, int);
209
210 static void bwi_led_attach(struct bwi_softc *);
211 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
212 static void bwi_led_event(struct bwi_softc *, int);
213 static void bwi_led_blink_start(struct bwi_softc *, int, int);
214 static void bwi_led_blink_next(void *);
215 static void bwi_led_blink_end(void *);
216
217 static const struct {
218 uint16_t did_min;
219 uint16_t did_max;
220 uint16_t bbp_id;
221 } bwi_bbpid_map[] = {
222 { 0x4301, 0x4301, 0x4301 },
223 { 0x4305, 0x4307, 0x4307 },
224 { 0x4403, 0x4403, 0x4402 },
225 { 0x4610, 0x4615, 0x4610 },
226 { 0x4710, 0x4715, 0x4710 },
227 { 0x4720, 0x4725, 0x4309 }
228 };
229
230 static const struct {
231 uint16_t bbp_id;
232 int nregwin;
233 } bwi_regwin_count[] = {
234 { 0x4301, 5 },
235 { 0x4306, 6 },
236 { 0x4307, 5 },
237 { 0x4310, 8 },
238 { 0x4401, 3 },
239 { 0x4402, 3 },
240 { 0x4610, 9 },
241 { 0x4704, 9 },
242 { 0x4710, 9 },
243 { 0x5365, 7 }
244 };
245
246 #define CLKSRC(src) \
247 [BWI_CLKSRC_ ## src] = { \
248 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
249 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
250 }
251
252 static const struct {
253 u_int freq_min;
254 u_int freq_max;
255 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
256 CLKSRC(LP_OSC),
257 CLKSRC(CS_OSC),
258 CLKSRC(PCI)
259 };
260
261 #undef CLKSRC
262
263 #define VENDOR_LED_ACT(vendor) \
264 { \
265 .vid = PCI_VENDOR_##vendor, \
266 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
267 }
268
269 static const struct {
270 #define PCI_VENDOR_COMPAQ 0x0e11
271 #define PCI_VENDOR_LINKSYS 0x1737
272 uint16_t vid;
273 uint8_t led_act[BWI_LED_MAX];
274 } bwi_vendor_led_act[] = {
275 VENDOR_LED_ACT(COMPAQ),
276 VENDOR_LED_ACT(LINKSYS)
277 #undef PCI_VENDOR_LINKSYS
278 #undef PCI_VENDOR_COMPAQ
279 };
280
281 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
282 { BWI_VENDOR_LED_ACT_DEFAULT };
283
284 #undef VENDOR_LED_ACT
285
286 static const struct {
287 int on_dur;
288 int off_dur;
289 } bwi_led_duration[109] = {
290 [0] = { 400, 100 },
291 [2] = { 150, 75 },
292 [4] = { 90, 45 },
293 [11] = { 66, 34 },
294 [12] = { 53, 26 },
295 [18] = { 42, 21 },
296 [22] = { 35, 17 },
297 [24] = { 32, 16 },
298 [36] = { 21, 10 },
299 [48] = { 16, 8 },
300 [72] = { 11, 5 },
301 [96] = { 9, 4 },
302 [108] = { 7, 3 }
303 };
304
305 #ifdef BWI_DEBUG
306 #ifdef BWI_DEBUG_VERBOSE
307 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
308 #else
309 static uint32_t bwi_debug;
310 #endif
311 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
312 #endif /* BWI_DEBUG */
313
314 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
315
316 uint16_t
317 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
318 {
319 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
320 }
321
322 static __inline void
323 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
324 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
325 int tx)
326 {
327 struct bwi_desc32 *desc = &desc_array[desc_idx];
328 uint32_t ctrl, addr, addr_hi, addr_lo;
329
330 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
331 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
332
333 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
334 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
335
336 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
337 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
338 if (desc_idx == ndesc - 1)
339 ctrl |= BWI_DESC32_C_EOR;
340 if (tx) {
341 /* XXX */
342 ctrl |= BWI_DESC32_C_FRAME_START |
343 BWI_DESC32_C_FRAME_END |
344 BWI_DESC32_C_INTR;
345 }
346
347 desc->addr = htole32(addr);
348 desc->ctrl = htole32(ctrl);
349 }
350
351 int
352 bwi_attach(struct bwi_softc *sc)
353 {
354 struct ieee80211com *ic;
355 device_t dev = sc->sc_dev;
356 struct ifnet *ifp;
357 struct bwi_mac *mac;
358 struct bwi_phy *phy;
359 int i, error;
360 uint8_t bands;
361 uint8_t macaddr[IEEE80211_ADDR_LEN];
362
363 BWI_LOCK_INIT(sc);
364
365 /*
366 * Initialize taskq and various tasks
367 */
368 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO,
369 taskqueue_thread_enqueue, &sc->sc_tq);
370 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
371 device_get_nameunit(dev));
372 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc);
373
374 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0);
375
376 /*
377 * Initialize sysctl variables
378 */
379 sc->sc_fw_version = BWI_FW_VERSION3;
380 sc->sc_led_idle = (2350 * hz) / 1000;
381 sc->sc_led_blink = 1;
382 sc->sc_txpwr_calib = 1;
383 #ifdef BWI_DEBUG
384 sc->sc_debug = bwi_debug;
385 #endif
386 bwi_power_on(sc, 1);
387
388 error = bwi_bbp_attach(sc);
389 if (error)
390 goto fail;
391
392 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
393 if (error)
394 goto fail;
395
396 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
397 error = bwi_set_clock_delay(sc);
398 if (error)
399 goto fail;
400
401 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
402 if (error)
403 goto fail;
404
405 error = bwi_get_pwron_delay(sc);
406 if (error)
407 goto fail;
408 }
409
410 error = bwi_bus_attach(sc);
411 if (error)
412 goto fail;
413
414 bwi_get_card_flags(sc);
415
416 bwi_led_attach(sc);
417
418 for (i = 0; i < sc->sc_nmac; ++i) {
419 struct bwi_regwin *old;
420
421 mac = &sc->sc_mac[i];
422 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
423 if (error)
424 goto fail;
425
426 error = bwi_mac_lateattach(mac);
427 if (error)
428 goto fail;
429
430 error = bwi_regwin_switch(sc, old, NULL);
431 if (error)
432 goto fail;
433 }
434
435 /*
436 * XXX First MAC is known to exist
437 * TODO2
438 */
439 mac = &sc->sc_mac[0];
440 phy = &mac->mac_phy;
441
442 bwi_bbp_power_off(sc);
443
444 error = bwi_dma_alloc(sc);
445 if (error)
446 goto fail;
447
448 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
449 if (ifp == NULL) {
450 device_printf(dev, "can not if_alloc()\n");
451 error = ENOSPC;
452 goto fail;
453 }
454 ic = ifp->if_l2com;
455
456 /* set these up early for if_printf use */
457 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
458
459 ifp->if_softc = sc;
460 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
461 ifp->if_init = bwi_init;
462 ifp->if_ioctl = bwi_ioctl;
463 ifp->if_start = bwi_start;
464 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
465 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
466 IFQ_SET_READY(&ifp->if_snd);
467 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0);
468
469 /*
470 * Setup ratesets, phytype, channels and get MAC address
471 */
472 bands = 0;
473 if (phy->phy_mode == IEEE80211_MODE_11B ||
474 phy->phy_mode == IEEE80211_MODE_11G) {
475 setbit(&bands, IEEE80211_MODE_11B);
476 if (phy->phy_mode == IEEE80211_MODE_11B) {
477 ic->ic_phytype = IEEE80211_T_DS;
478 } else {
479 ic->ic_phytype = IEEE80211_T_OFDM;
480 setbit(&bands, IEEE80211_MODE_11G);
481 }
482
483 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, macaddr);
484 if (IEEE80211_IS_MULTICAST(macaddr)) {
485 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, macaddr);
486 if (IEEE80211_IS_MULTICAST(macaddr)) {
487 device_printf(dev,
488 "invalid MAC address: %6D\n",
489 macaddr, ":");
490 }
491 }
492 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
493 /* TODO:11A */
494 setbit(&bands, IEEE80211_MODE_11A);
495 error = ENXIO;
496 goto fail;
497 } else {
498 panic("unknown phymode %d\n", phy->phy_mode);
499 }
500
501 /* Get locale */
502 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
503 BWI_SPROM_CARD_INFO_LOCALE);
504 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
505 /* XXX use locale */
506 ieee80211_init_channels(ic, NULL, &bands);
507
508 ic->ic_ifp = ifp;
509 ic->ic_caps = IEEE80211_C_STA |
510 IEEE80211_C_SHSLOT |
511 IEEE80211_C_SHPREAMBLE |
512 IEEE80211_C_WPA |
513 IEEE80211_C_BGSCAN |
514 IEEE80211_C_MONITOR;
515 ic->ic_opmode = IEEE80211_M_STA;
516 ieee80211_ifattach(ic, macaddr);
517
518 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
519
520 /* override default methods */
521 ic->ic_vap_create = bwi_vap_create;
522 ic->ic_vap_delete = bwi_vap_delete;
523 ic->ic_raw_xmit = bwi_raw_xmit;
524 ic->ic_updateslot = bwi_updateslot;
525 ic->ic_scan_start = bwi_scan_start;
526 ic->ic_scan_end = bwi_scan_end;
527 ic->ic_set_channel = bwi_set_channel;
528
529 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan);
530
531 ieee80211_radiotap_attach(ic,
532 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
533 BWI_TX_RADIOTAP_PRESENT,
534 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
535 BWI_RX_RADIOTAP_PRESENT);
536
537 /*
538 * Add sysctl nodes
539 */
540 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
541 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
542 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
543 "Firmware version");
544 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
545 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
546 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
547 "# ticks before LED enters idle state");
548 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
549 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
550 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
551 "Allow LED to blink");
552 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
553 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
554 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
555 "Enable software TX power calibration");
556 #ifdef BWI_DEBUG
557 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
558 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
559 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
560 #endif
561 if (bootverbose)
562 ieee80211_announce(ic);
563
564 return (0);
565 fail:
566 BWI_LOCK_DESTROY(sc);
567 return (error);
568 }
569
570 int
571 bwi_detach(struct bwi_softc *sc)
572 {
573 struct ifnet *ifp = sc->sc_ifp;
574 struct ieee80211com *ic = ifp->if_l2com;
575 int i;
576
577 bwi_stop(sc, 1);
578 callout_drain(&sc->sc_led_blink_ch);
579 callout_drain(&sc->sc_calib_ch);
580 callout_drain(&sc->sc_watchdog_timer);
581 ieee80211_ifdetach(ic);
582
583 for (i = 0; i < sc->sc_nmac; ++i)
584 bwi_mac_detach(&sc->sc_mac[i]);
585 bwi_dma_free(sc);
586 if_free(ifp);
587 taskqueue_free(sc->sc_tq);
588
589 BWI_LOCK_DESTROY(sc);
590
591 return (0);
592 }
593
594 static struct ieee80211vap *
595 bwi_vap_create(struct ieee80211com *ic,
596 const char name[IFNAMSIZ], int unit, int opmode, int flags,
597 const uint8_t bssid[IEEE80211_ADDR_LEN],
598 const uint8_t mac[IEEE80211_ADDR_LEN])
599 {
600 struct bwi_vap *bvp;
601 struct ieee80211vap *vap;
602
603 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
604 return NULL;
605 bvp = (struct bwi_vap *) malloc(sizeof(struct bwi_vap),
606 M_80211_VAP, M_WAITOK | M_ZERO);
607 if (bvp == NULL)
608 return NULL;
609 vap = &bvp->bv_vap;
610 /* enable s/w bmiss handling for sta mode */
611 ieee80211_vap_setup(ic, vap, name, unit, opmode,
612 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac);
613
614 /* override default methods */
615 bvp->bv_newstate = vap->iv_newstate;
616 vap->iv_newstate = bwi_newstate;
617 #if 0
618 vap->iv_update_beacon = bwi_beacon_update;
619 #endif
620 ieee80211_ratectl_init(vap);
621
622 /* complete setup */
623 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status);
624 ic->ic_opmode = opmode;
625 return vap;
626 }
627
628 static void
629 bwi_vap_delete(struct ieee80211vap *vap)
630 {
631 struct bwi_vap *bvp = BWI_VAP(vap);
632
633 ieee80211_ratectl_deinit(vap);
634 ieee80211_vap_detach(vap);
635 free(bvp, M_80211_VAP);
636 }
637
638 void
639 bwi_suspend(struct bwi_softc *sc)
640 {
641 bwi_stop(sc, 1);
642 }
643
644 void
645 bwi_resume(struct bwi_softc *sc)
646 {
647 struct ifnet *ifp = sc->sc_ifp;
648
649 if (ifp->if_flags & IFF_UP)
650 bwi_init(sc);
651 }
652
653 int
654 bwi_shutdown(struct bwi_softc *sc)
655 {
656 bwi_stop(sc, 1);
657 return 0;
658 }
659
660 static void
661 bwi_power_on(struct bwi_softc *sc, int with_pll)
662 {
663 uint32_t gpio_in, gpio_out, gpio_en;
664 uint16_t status;
665
666 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
667 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
668 goto back;
669
670 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
671 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
672
673 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
674 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
675 if (with_pll) {
676 /* Turn off PLL first */
677 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
678 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
679 }
680
681 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
682 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
683 DELAY(1000);
684
685 if (with_pll) {
686 /* Turn on PLL */
687 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
688 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
689 DELAY(5000);
690 }
691
692 back:
693 /* Clear "Signaled Target Abort" */
694 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
695 status &= ~PCIM_STATUS_STABORT;
696 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
697 }
698
699 static int
700 bwi_power_off(struct bwi_softc *sc, int with_pll)
701 {
702 uint32_t gpio_out, gpio_en;
703
704 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
705 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
706 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
707
708 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
709 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
710 if (with_pll) {
711 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
712 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
713 }
714
715 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
716 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
717 return 0;
718 }
719
720 int
721 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
722 struct bwi_regwin **old_rw)
723 {
724 int error;
725
726 if (old_rw != NULL)
727 *old_rw = NULL;
728
729 if (!BWI_REGWIN_EXIST(rw))
730 return EINVAL;
731
732 if (sc->sc_cur_regwin != rw) {
733 error = bwi_regwin_select(sc, rw->rw_id);
734 if (error) {
735 device_printf(sc->sc_dev, "can't select regwin %d\n",
736 rw->rw_id);
737 return error;
738 }
739 }
740
741 if (old_rw != NULL)
742 *old_rw = sc->sc_cur_regwin;
743 sc->sc_cur_regwin = rw;
744 return 0;
745 }
746
747 static int
748 bwi_regwin_select(struct bwi_softc *sc, int id)
749 {
750 uint32_t win = BWI_PCIM_REGWIN(id);
751 int i;
752
753 #define RETRY_MAX 50
754 for (i = 0; i < RETRY_MAX; ++i) {
755 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
756 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
757 return 0;
758 DELAY(10);
759 }
760 #undef RETRY_MAX
761
762 return ENXIO;
763 }
764
765 static void
766 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
767 {
768 uint32_t val;
769
770 val = CSR_READ_4(sc, BWI_ID_HI);
771 *type = BWI_ID_HI_REGWIN_TYPE(val);
772 *rev = BWI_ID_HI_REGWIN_REV(val);
773
774 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
775 "vendor 0x%04x\n", *type, *rev,
776 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
777 }
778
779 static int
780 bwi_bbp_attach(struct bwi_softc *sc)
781 {
782 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
783 uint16_t bbp_id, rw_type;
784 uint8_t rw_rev;
785 uint32_t info;
786 int error, nregwin, i;
787
788 /*
789 * Get 0th regwin information
790 * NOTE: 0th regwin should exist
791 */
792 error = bwi_regwin_select(sc, 0);
793 if (error) {
794 device_printf(sc->sc_dev, "can't select regwin 0\n");
795 return error;
796 }
797 bwi_regwin_info(sc, &rw_type, &rw_rev);
798
799 /*
800 * Find out BBP id
801 */
802 bbp_id = 0;
803 info = 0;
804 if (rw_type == BWI_REGWIN_T_COM) {
805 info = CSR_READ_4(sc, BWI_INFO);
806 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
807
808 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
809
810 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
811 } else {
812 for (i = 0; i < N(bwi_bbpid_map); ++i) {
813 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min &&
814 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) {
815 bbp_id = bwi_bbpid_map[i].bbp_id;
816 break;
817 }
818 }
819 if (bbp_id == 0) {
820 device_printf(sc->sc_dev, "no BBP id for device id "
821 "0x%04x\n", sc->sc_pci_did);
822 return ENXIO;
823 }
824
825 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) |
826 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
827 }
828
829 /*
830 * Find out number of regwins
831 */
832 nregwin = 0;
833 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
834 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
835 } else {
836 for (i = 0; i < N(bwi_regwin_count); ++i) {
837 if (bwi_regwin_count[i].bbp_id == bbp_id) {
838 nregwin = bwi_regwin_count[i].nregwin;
839 break;
840 }
841 }
842 if (nregwin == 0) {
843 device_printf(sc->sc_dev, "no number of win for "
844 "BBP id 0x%04x\n", bbp_id);
845 return ENXIO;
846 }
847 }
848
849 /* Record BBP id/rev for later using */
850 sc->sc_bbp_id = bbp_id;
851 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
852 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
853 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
854 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
855
856 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
857 nregwin, sc->sc_cap);
858
859 /*
860 * Create rest of the regwins
861 */
862
863 /* Don't re-create common regwin, if it is already created */
864 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
865
866 for (; i < nregwin; ++i) {
867 /*
868 * Get regwin information
869 */
870 error = bwi_regwin_select(sc, i);
871 if (error) {
872 device_printf(sc->sc_dev,
873 "can't select regwin %d\n", i);
874 return error;
875 }
876 bwi_regwin_info(sc, &rw_type, &rw_rev);
877
878 /*
879 * Try attach:
880 * 1) Bus (PCI/PCIE) regwin
881 * 2) MAC regwin
882 * Ignore rest types of regwin
883 */
884 if (rw_type == BWI_REGWIN_T_BUSPCI ||
885 rw_type == BWI_REGWIN_T_BUSPCIE) {
886 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
887 device_printf(sc->sc_dev,
888 "bus regwin already exists\n");
889 } else {
890 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
891 rw_type, rw_rev);
892 }
893 } else if (rw_type == BWI_REGWIN_T_MAC) {
894 /* XXX ignore return value */
895 bwi_mac_attach(sc, i, rw_rev);
896 }
897 }
898
899 /* At least one MAC shold exist */
900 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
901 device_printf(sc->sc_dev, "no MAC was found\n");
902 return ENXIO;
903 }
904 KASSERT(sc->sc_nmac > 0, ("no mac's"));
905
906 /* Bus regwin must exist */
907 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
908 device_printf(sc->sc_dev, "no bus regwin was found\n");
909 return ENXIO;
910 }
911
912 /* Start with first MAC */
913 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
914 if (error)
915 return error;
916
917 return 0;
918 #undef N
919 }
920
921 int
922 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
923 {
924 struct bwi_regwin *old, *bus;
925 uint32_t val;
926 int error;
927
928 bus = &sc->sc_bus_regwin;
929 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin"));
930
931 /*
932 * Tell bus to generate requested interrupts
933 */
934 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
935 /*
936 * NOTE: Read BWI_FLAGS from MAC regwin
937 */
938 val = CSR_READ_4(sc, BWI_FLAGS);
939
940 error = bwi_regwin_switch(sc, bus, &old);
941 if (error)
942 return error;
943
944 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
945 } else {
946 uint32_t mac_mask;
947
948 mac_mask = 1 << mac->mac_id;
949
950 error = bwi_regwin_switch(sc, bus, &old);
951 if (error)
952 return error;
953
954 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
955 val |= mac_mask << 8;
956 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
957 }
958
959 if (sc->sc_flags & BWI_F_BUS_INITED)
960 goto back;
961
962 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
963 /*
964 * Enable prefetch and burst
965 */
966 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
967 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
968
969 if (bus->rw_rev < 5) {
970 struct bwi_regwin *com = &sc->sc_com_regwin;
971
972 /*
973 * Configure timeouts for bus operation
974 */
975
976 /*
977 * Set service timeout and request timeout
978 */
979 CSR_SETBITS_4(sc, BWI_CONF_LO,
980 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
981 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
982
983 /*
984 * If there is common regwin, we switch to that regwin
985 * and switch back to bus regwin once we have done.
986 */
987 if (BWI_REGWIN_EXIST(com)) {
988 error = bwi_regwin_switch(sc, com, NULL);
989 if (error)
990 return error;
991 }
992
993 /* Let bus know what we have changed */
994 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
995 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
996 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
997 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
998
999 if (BWI_REGWIN_EXIST(com)) {
1000 error = bwi_regwin_switch(sc, bus, NULL);
1001 if (error)
1002 return error;
1003 }
1004 } else if (bus->rw_rev >= 11) {
1005 /*
1006 * Enable memory read multiple
1007 */
1008 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
1009 }
1010 } else {
1011 /* TODO:PCIE */
1012 }
1013
1014 sc->sc_flags |= BWI_F_BUS_INITED;
1015 back:
1016 return bwi_regwin_switch(sc, old, NULL);
1017 }
1018
1019 static void
1020 bwi_get_card_flags(struct bwi_softc *sc)
1021 {
1022 #define PCI_VENDOR_APPLE 0x106b
1023 #define PCI_VENDOR_DELL 0x1028
1024 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1025 if (sc->sc_card_flags == 0xffff)
1026 sc->sc_card_flags = 0;
1027
1028 if (sc->sc_pci_subvid == PCI_VENDOR_DELL &&
1029 sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1030 sc->sc_pci_revid == 0x74)
1031 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST;
1032
1033 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1034 sc->sc_pci_subdid == 0x4e && /* XXX */
1035 sc->sc_pci_revid > 0x40)
1036 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1037
1038 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1039 #undef PCI_VENDOR_DELL
1040 #undef PCI_VENDOR_APPLE
1041 }
1042
1043 static void
1044 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1045 {
1046 int i;
1047
1048 for (i = 0; i < 3; ++i) {
1049 *((uint16_t *)eaddr + i) =
1050 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1051 }
1052 }
1053
1054 static void
1055 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1056 {
1057 struct bwi_regwin *com;
1058 uint32_t val;
1059 u_int div;
1060 int src;
1061
1062 bzero(freq, sizeof(*freq));
1063 com = &sc->sc_com_regwin;
1064
1065 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist"));
1066 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin"));
1067 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode"));
1068
1069 /*
1070 * Calculate clock frequency
1071 */
1072 src = -1;
1073 div = 0;
1074 if (com->rw_rev < 6) {
1075 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1076 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1077 src = BWI_CLKSRC_PCI;
1078 div = 64;
1079 } else {
1080 src = BWI_CLKSRC_CS_OSC;
1081 div = 32;
1082 }
1083 } else if (com->rw_rev < 10) {
1084 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1085
1086 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1087 if (src == BWI_CLKSRC_LP_OSC) {
1088 div = 1;
1089 } else {
1090 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1091
1092 /* Unknown source */
1093 if (src >= BWI_CLKSRC_MAX)
1094 src = BWI_CLKSRC_CS_OSC;
1095 }
1096 } else {
1097 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1098
1099 src = BWI_CLKSRC_CS_OSC;
1100 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1101 }
1102
1103 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src));
1104 KASSERT(div != 0, ("div zero"));
1105
1106 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1107 src == BWI_CLKSRC_PCI ? "PCI" :
1108 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1109
1110 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1111 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1112
1113 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1114 freq->clkfreq_min, freq->clkfreq_max);
1115 }
1116
1117 static int
1118 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1119 {
1120 struct bwi_regwin *old, *com;
1121 uint32_t clk_ctrl, clk_src;
1122 int error, pwr_off = 0;
1123
1124 com = &sc->sc_com_regwin;
1125 if (!BWI_REGWIN_EXIST(com))
1126 return 0;
1127
1128 if (com->rw_rev >= 10 || com->rw_rev < 6)
1129 return 0;
1130
1131 /*
1132 * For common regwin whose rev is [6, 10), the chip
1133 * must be capable to change clock mode.
1134 */
1135 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1136 return 0;
1137
1138 error = bwi_regwin_switch(sc, com, &old);
1139 if (error)
1140 return error;
1141
1142 if (clk_mode == BWI_CLOCK_MODE_FAST)
1143 bwi_power_on(sc, 0); /* Don't turn on PLL */
1144
1145 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1146 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1147
1148 switch (clk_mode) {
1149 case BWI_CLOCK_MODE_FAST:
1150 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1151 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1152 break;
1153 case BWI_CLOCK_MODE_SLOW:
1154 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1155 break;
1156 case BWI_CLOCK_MODE_DYN:
1157 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1158 BWI_CLOCK_CTRL_IGNPLL |
1159 BWI_CLOCK_CTRL_NODYN);
1160 if (clk_src != BWI_CLKSRC_CS_OSC) {
1161 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1162 pwr_off = 1;
1163 }
1164 break;
1165 }
1166 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1167
1168 if (pwr_off)
1169 bwi_power_off(sc, 0); /* Leave PLL as it is */
1170
1171 return bwi_regwin_switch(sc, old, NULL);
1172 }
1173
1174 static int
1175 bwi_set_clock_delay(struct bwi_softc *sc)
1176 {
1177 struct bwi_regwin *old, *com;
1178 int error;
1179
1180 com = &sc->sc_com_regwin;
1181 if (!BWI_REGWIN_EXIST(com))
1182 return 0;
1183
1184 error = bwi_regwin_switch(sc, com, &old);
1185 if (error)
1186 return error;
1187
1188 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1189 if (sc->sc_bbp_rev == 0)
1190 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1191 else if (sc->sc_bbp_rev == 1)
1192 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1193 }
1194
1195 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1196 if (com->rw_rev >= 10) {
1197 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1198 } else {
1199 struct bwi_clock_freq freq;
1200
1201 bwi_get_clock_freq(sc, &freq);
1202 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1203 howmany(freq.clkfreq_max * 150, 1000000));
1204 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1205 howmany(freq.clkfreq_max * 15, 1000000));
1206 }
1207 }
1208
1209 return bwi_regwin_switch(sc, old, NULL);
1210 }
1211
1212 static void
1213 bwi_init(void *xsc)
1214 {
1215 struct bwi_softc *sc = xsc;
1216 struct ifnet *ifp = sc->sc_ifp;
1217 struct ieee80211com *ic = ifp->if_l2com;
1218
1219 BWI_LOCK(sc);
1220 bwi_init_statechg(sc, 1);
1221 BWI_UNLOCK(sc);
1222
1223 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1224 ieee80211_start_all(ic); /* start all vap's */
1225 }
1226
1227 static void
1228 bwi_init_statechg(struct bwi_softc *sc, int statechg)
1229 {
1230 struct ifnet *ifp = sc->sc_ifp;
1231 struct bwi_mac *mac;
1232 int error;
1233
1234 bwi_stop_locked(sc, statechg);
1235
1236 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1237
1238 /* TODO: 2 MAC */
1239
1240 mac = &sc->sc_mac[0];
1241 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1242 if (error) {
1243 if_printf(ifp, "%s: error %d on regwin switch\n",
1244 __func__, error);
1245 goto bad;
1246 }
1247 error = bwi_mac_init(mac);
1248 if (error) {
1249 if_printf(ifp, "%s: error %d on MAC init\n", __func__, error);
1250 goto bad;
1251 }
1252
1253 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1254
1255 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1256 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, IF_LLADDR(ifp));
1257
1258 bwi_mac_reset_hwkeys(mac);
1259
1260 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1261 int i;
1262
1263 #define NRETRY 1000
1264 /*
1265 * Drain any possible pending TX status
1266 */
1267 for (i = 0; i < NRETRY; ++i) {
1268 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1269 BWI_TXSTATUS0_VALID) == 0)
1270 break;
1271 CSR_READ_4(sc, BWI_TXSTATUS1);
1272 }
1273 if (i == NRETRY)
1274 if_printf(ifp, "%s: can't drain TX status\n", __func__);
1275 #undef NRETRY
1276 }
1277
1278 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1279 bwi_mac_updateslot(mac, 1);
1280
1281 /* Start MAC */
1282 error = bwi_mac_start(mac);
1283 if (error) {
1284 if_printf(ifp, "%s: error %d starting MAC\n", __func__, error);
1285 goto bad;
1286 }
1287
1288 /* Clear stop flag before enabling interrupt */
1289 sc->sc_flags &= ~BWI_F_STOP;
1290
1291 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1292 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1293
1294 /* Enable intrs */
1295 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1296 return;
1297 bad:
1298 bwi_stop_locked(sc, 1);
1299 }
1300
1301 static int
1302 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1303 {
1304 #define IS_RUNNING(ifp) \
1305 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
1306 struct bwi_softc *sc = ifp->if_softc;
1307 struct ieee80211com *ic = ifp->if_l2com;
1308 struct ifreq *ifr = (struct ifreq *) data;
1309 int error = 0, startall = 0;
1310
1311 switch (cmd) {
1312 case SIOCSIFFLAGS:
1313 BWI_LOCK(sc);
1314 if (IS_RUNNING(ifp)) {
1315 struct bwi_mac *mac;
1316 int promisc = -1;
1317
1318 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1319 ("current regwin type %d",
1320 sc->sc_cur_regwin->rw_type));
1321 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1322
1323 if ((ifp->if_flags & IFF_PROMISC) &&
1324 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1325 promisc = 1;
1326 sc->sc_flags |= BWI_F_PROMISC;
1327 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1328 (sc->sc_flags & BWI_F_PROMISC)) {
1329 promisc = 0;
1330 sc->sc_flags &= ~BWI_F_PROMISC;
1331 }
1332
1333 if (promisc >= 0)
1334 bwi_mac_set_promisc(mac, promisc);
1335 }
1336
1337 if (ifp->if_flags & IFF_UP) {
1338 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1339 bwi_init_statechg(sc, 1);
1340 startall = 1;
1341 }
1342 } else {
1343 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1344 bwi_stop_locked(sc, 1);
1345 }
1346 BWI_UNLOCK(sc);
1347 if (startall)
1348 ieee80211_start_all(ic);
1349 break;
1350 case SIOCGIFMEDIA:
1351 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1352 break;
1353 case SIOCGIFADDR:
1354 error = ether_ioctl(ifp, cmd, data);
1355 break;
1356 default:
1357 error = EINVAL;
1358 break;
1359 }
1360 return error;
1361 #undef IS_RUNNING
1362 }
1363
1364 static void
1365 bwi_start(struct ifnet *ifp)
1366 {
1367 struct bwi_softc *sc = ifp->if_softc;
1368
1369 BWI_LOCK(sc);
1370 bwi_start_locked(ifp);
1371 BWI_UNLOCK(sc);
1372 }
1373
1374 static void
1375 bwi_start_locked(struct ifnet *ifp)
1376 {
1377 struct bwi_softc *sc = ifp->if_softc;
1378 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1379 struct ieee80211_frame *wh;
1380 struct ieee80211_node *ni;
1381 struct ieee80211_key *k;
1382 struct mbuf *m;
1383 int trans, idx;
1384
1385 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1386 return;
1387
1388 trans = 0;
1389 idx = tbd->tbd_idx;
1390
1391 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1392 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */
1393 if (m == NULL)
1394 break;
1395
1396 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1397 wh = mtod(m, struct ieee80211_frame *);
1398 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1399 k = ieee80211_crypto_encap(ni, m);
1400 if (k == NULL) {
1401 ieee80211_free_node(ni);
1402 m_freem(m);
1403 ifp->if_oerrors++;
1404 continue;
1405 }
1406 }
1407 wh = NULL; /* Catch any invalid use */
1408
1409 if (bwi_encap(sc, idx, m, ni) != 0) {
1410 /* 'm' is freed in bwi_encap() if we reach here */
1411 if (ni != NULL)
1412 ieee80211_free_node(ni);
1413 ifp->if_oerrors++;
1414 continue;
1415 }
1416
1417 trans = 1;
1418 tbd->tbd_used++;
1419 idx = (idx + 1) % BWI_TX_NDESC;
1420
1421 ifp->if_opackets++;
1422
1423 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
1424 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1425 break;
1426 }
1427 }
1428 tbd->tbd_idx = idx;
1429
1430 if (trans)
1431 sc->sc_tx_timer = 5;
1432 }
1433
1434 static int
1435 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1436 const struct ieee80211_bpf_params *params)
1437 {
1438 struct ieee80211com *ic = ni->ni_ic;
1439 struct ifnet *ifp = ic->ic_ifp;
1440 struct bwi_softc *sc = ifp->if_softc;
1441 /* XXX wme? */
1442 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1443 int idx, error;
1444
1445 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1446 ieee80211_free_node(ni);
1447 m_freem(m);
1448 return ENETDOWN;
1449 }
1450
1451 BWI_LOCK(sc);
1452 idx = tbd->tbd_idx;
1453 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx));
1454 if (params == NULL) {
1455 /*
1456 * Legacy path; interpret frame contents to decide
1457 * precisely how to send the frame.
1458 */
1459 error = bwi_encap(sc, idx, m, ni);
1460 } else {
1461 /*
1462 * Caller supplied explicit parameters to use in
1463 * sending the frame.
1464 */
1465 error = bwi_encap_raw(sc, idx, m, ni, params);
1466 }
1467 if (error == 0) {
1468 ifp->if_opackets++;
1469 if (++tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC)
1470 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1471 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC;
1472 sc->sc_tx_timer = 5;
1473 } else {
1474 /* NB: m is reclaimed on encap failure */
1475 ieee80211_free_node(ni);
1476 ifp->if_oerrors++;
1477 }
1478 BWI_UNLOCK(sc);
1479 return error;
1480 }
1481
1482 static void
1483 bwi_watchdog(void *arg)
1484 {
1485 struct bwi_softc *sc;
1486 struct ifnet *ifp;
1487
1488 sc = arg;
1489 ifp = sc->sc_ifp;
1490 BWI_ASSERT_LOCKED(sc);
1491 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) {
1492 if_printf(ifp, "watchdog timeout\n");
1493 ifp->if_oerrors++;
1494 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1495 }
1496 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1497 }
1498
1499 static void
1500 bwi_stop(struct bwi_softc *sc, int statechg)
1501 {
1502 BWI_LOCK(sc);
1503 bwi_stop_locked(sc, statechg);
1504 BWI_UNLOCK(sc);
1505 }
1506
1507 static void
1508 bwi_stop_locked(struct bwi_softc *sc, int statechg)
1509 {
1510 struct ifnet *ifp = sc->sc_ifp;
1511 struct bwi_mac *mac;
1512 int i, error, pwr_off = 0;
1513
1514 BWI_ASSERT_LOCKED(sc);
1515
1516 callout_stop(&sc->sc_calib_ch);
1517 callout_stop(&sc->sc_led_blink_ch);
1518 sc->sc_led_blinking = 0;
1519 sc->sc_flags |= BWI_F_STOP;
1520
1521 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1522 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1523 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1524 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1525
1526 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1527 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1528 bwi_mac_stop(mac);
1529 }
1530
1531 for (i = 0; i < sc->sc_nmac; ++i) {
1532 struct bwi_regwin *old_rw;
1533
1534 mac = &sc->sc_mac[i];
1535 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1536 continue;
1537
1538 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1539 if (error)
1540 continue;
1541
1542 bwi_mac_shutdown(mac);
1543 pwr_off = 1;
1544
1545 bwi_regwin_switch(sc, old_rw, NULL);
1546 }
1547
1548 if (pwr_off)
1549 bwi_bbp_power_off(sc);
1550
1551 sc->sc_tx_timer = 0;
1552 callout_stop(&sc->sc_watchdog_timer);
1553 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1554 }
1555
1556 void
1557 bwi_intr(void *xsc)
1558 {
1559 struct bwi_softc *sc = xsc;
1560 struct ifnet *ifp = sc->sc_ifp;
1561 struct bwi_mac *mac;
1562 uint32_t intr_status;
1563 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1564 int i, txrx_error, tx = 0, rx_data = -1;
1565
1566 BWI_LOCK(sc);
1567
1568 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
1569 (sc->sc_flags & BWI_F_STOP)) {
1570 BWI_UNLOCK(sc);
1571 return;
1572 }
1573 /*
1574 * Get interrupt status
1575 */
1576 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1577 if (intr_status == 0xffffffff) { /* Not for us */
1578 BWI_UNLOCK(sc);
1579 return;
1580 }
1581
1582 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1583
1584 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1585 if (intr_status == 0) { /* Nothing is interesting */
1586 BWI_UNLOCK(sc);
1587 return;
1588 }
1589
1590 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1591 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1592 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1593
1594 txrx_error = 0;
1595 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1596 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1597 uint32_t mask;
1598
1599 if (BWI_TXRX_IS_RX(i))
1600 mask = BWI_TXRX_RX_INTRS;
1601 else
1602 mask = BWI_TXRX_TX_INTRS;
1603
1604 txrx_intr_status[i] =
1605 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1606
1607 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1608 i, txrx_intr_status[i]);
1609
1610 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1611 if_printf(ifp,
1612 "%s: intr fatal TX/RX (%d) error 0x%08x\n",
1613 __func__, i, txrx_intr_status[i]);
1614 txrx_error = 1;
1615 }
1616 }
1617 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1618
1619 /*
1620 * Acknowledge interrupt
1621 */
1622 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1623
1624 for (i = 0; i < BWI_TXRX_NRING; ++i)
1625 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1626
1627 /* Disable all interrupts */
1628 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1629
1630 /*
1631 * http://bcm-specs.sipsolutions.net/Interrupts
1632 * Says for this bit (0x800):
1633 * "Fatal Error
1634 *
1635 * We got this one while testing things when by accident the
1636 * template ram wasn't set to big endian when it should have
1637 * been after writing the initial values. It keeps on being
1638 * triggered, the only way to stop it seems to shut down the
1639 * chip."
1640 *
1641 * Suggesting that we should never get it and if we do we're not
1642 * feeding TX packets into the MAC correctly if we do... Apparently,
1643 * it is valid only on mac version 5 and higher, but I couldn't
1644 * find a reference for that... Since I see them from time to time
1645 * on my card, this suggests an error in the tx path still...
1646 */
1647 if (intr_status & BWI_INTR_PHY_TXERR) {
1648 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1649 if_printf(ifp, "%s: intr PHY TX error\n", __func__);
1650 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1651 BWI_UNLOCK(sc);
1652 return;
1653 }
1654 }
1655
1656 if (txrx_error) {
1657 /* TODO: reset device */
1658 }
1659
1660 if (intr_status & BWI_INTR_TBTT)
1661 bwi_mac_config_ps(mac);
1662
1663 if (intr_status & BWI_INTR_EO_ATIM)
1664 if_printf(ifp, "EO_ATIM\n");
1665
1666 if (intr_status & BWI_INTR_PMQ) {
1667 for (;;) {
1668 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1669 break;
1670 }
1671 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1672 }
1673
1674 if (intr_status & BWI_INTR_NOISE)
1675 if_printf(ifp, "intr noise\n");
1676
1677 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) {
1678 rx_data = sc->sc_rxeof(sc);
1679 if (sc->sc_flags & BWI_F_STOP) {
1680 BWI_UNLOCK(sc);
1681 return;
1682 }
1683 }
1684
1685 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1686 sc->sc_txeof_status(sc);
1687 tx = 1;
1688 }
1689
1690 if (intr_status & BWI_INTR_TX_DONE) {
1691 bwi_txeof(sc);
1692 tx = 1;
1693 }
1694
1695 /* Re-enable interrupts */
1696 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1697
1698 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1699 int evt = BWI_LED_EVENT_NONE;
1700
1701 if (tx && rx_data > 0) {
1702 if (sc->sc_rx_rate > sc->sc_tx_rate)
1703 evt = BWI_LED_EVENT_RX;
1704 else
1705 evt = BWI_LED_EVENT_TX;
1706 } else if (tx) {
1707 evt = BWI_LED_EVENT_TX;
1708 } else if (rx_data > 0) {
1709 evt = BWI_LED_EVENT_RX;
1710 } else if (rx_data == 0) {
1711 evt = BWI_LED_EVENT_POLL;
1712 }
1713
1714 if (evt != BWI_LED_EVENT_NONE)
1715 bwi_led_event(sc, evt);
1716 }
1717
1718 BWI_UNLOCK(sc);
1719 }
1720
1721 static void
1722 bwi_scan_start(struct ieee80211com *ic)
1723 {
1724 struct bwi_softc *sc = ic->ic_ifp->if_softc;
1725
1726 BWI_LOCK(sc);
1727 /* Enable MAC beacon promiscuity */
1728 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1729 BWI_UNLOCK(sc);
1730 }
1731
1732 static void
1733 bwi_set_channel(struct ieee80211com *ic)
1734 {
1735 struct bwi_softc *sc = ic->ic_ifp->if_softc;
1736 struct ieee80211_channel *c = ic->ic_curchan;
1737 struct bwi_mac *mac;
1738
1739 BWI_LOCK(sc);
1740 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1741 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1742 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1743 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0);
1744
1745 sc->sc_rates = ieee80211_get_ratetable(c);
1746
1747 /*
1748 * Setup radio tap channel freq and flags
1749 */
1750 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
1751 htole16(c->ic_freq);
1752 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
1753 htole16(c->ic_flags & 0xffff);
1754
1755 BWI_UNLOCK(sc);
1756 }
1757
1758 static void
1759 bwi_scan_end(struct ieee80211com *ic)
1760 {
1761 struct bwi_softc *sc = ic->ic_ifp->if_softc;
1762
1763 BWI_LOCK(sc);
1764 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1765 BWI_UNLOCK(sc);
1766 }
1767
1768 static int
1769 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1770 {
1771 struct bwi_vap *bvp = BWI_VAP(vap);
1772 struct ieee80211com *ic= vap->iv_ic;
1773 struct ifnet *ifp = ic->ic_ifp;
1774 enum ieee80211_state ostate = vap->iv_state;
1775 struct bwi_softc *sc = ifp->if_softc;
1776 struct bwi_mac *mac;
1777 int error;
1778
1779 BWI_LOCK(sc);
1780
1781 callout_stop(&sc->sc_calib_ch);
1782
1783 if (nstate == IEEE80211_S_INIT)
1784 sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1785
1786 bwi_led_newstate(sc, nstate);
1787
1788 error = bvp->bv_newstate(vap, nstate, arg);
1789 if (error != 0)
1790 goto back;
1791
1792 /*
1793 * Clear the BSSID when we stop a STA
1794 */
1795 if (vap->iv_opmode == IEEE80211_M_STA) {
1796 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) {
1797 /*
1798 * Clear out the BSSID. If we reassociate to
1799 * the same AP, this will reinialize things
1800 * correctly...
1801 */
1802 if (ic->ic_opmode == IEEE80211_M_STA &&
1803 !(sc->sc_flags & BWI_F_STOP))
1804 bwi_set_bssid(sc, bwi_zero_addr);
1805 }
1806 }
1807
1808 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
1809 /* Nothing to do */
1810 } else if (nstate == IEEE80211_S_RUN) {
1811 bwi_set_bssid(sc, vap->iv_bss->ni_bssid);
1812
1813 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1814 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1815 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1816
1817 /* Initial TX power calibration */
1818 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1819 #ifdef notyet
1820 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1821 #else
1822 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1823 #endif
1824
1825 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
1826 }
1827 back:
1828 BWI_UNLOCK(sc);
1829
1830 return error;
1831 }
1832
1833 static int
1834 bwi_media_change(struct ifnet *ifp)
1835 {
1836 int error = ieee80211_media_change(ifp);
1837 /* NB: only the fixed rate can change and that doesn't need a reset */
1838 return (error == ENETRESET ? 0 : error);
1839 }
1840
1841 static int
1842 bwi_dma_alloc(struct bwi_softc *sc)
1843 {
1844 int error, i, has_txstats;
1845 bus_addr_t lowaddr = 0;
1846 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1847 uint32_t txrx_ctrl_step = 0;
1848
1849 has_txstats = 0;
1850 for (i = 0; i < sc->sc_nmac; ++i) {
1851 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1852 has_txstats = 1;
1853 break;
1854 }
1855 }
1856
1857 switch (sc->sc_bus_space) {
1858 case BWI_BUS_SPACE_30BIT:
1859 case BWI_BUS_SPACE_32BIT:
1860 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1861 lowaddr = BWI_BUS_SPACE_MAXADDR;
1862 else
1863 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1864 desc_sz = sizeof(struct bwi_desc32);
1865 txrx_ctrl_step = 0x20;
1866
1867 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1868 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1869 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1870 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1871 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1872 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1873 sc->sc_rxeof = bwi_rxeof32;
1874 sc->sc_start_tx = bwi_start_tx32;
1875 if (has_txstats) {
1876 sc->sc_init_txstats = bwi_init_txstats32;
1877 sc->sc_free_txstats = bwi_free_txstats32;
1878 sc->sc_txeof_status = bwi_txeof_status32;
1879 }
1880 break;
1881
1882 case BWI_BUS_SPACE_64BIT:
1883 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
1884 desc_sz = sizeof(struct bwi_desc64);
1885 txrx_ctrl_step = 0x40;
1886
1887 sc->sc_init_tx_ring = bwi_init_tx_ring64;
1888 sc->sc_free_tx_ring = bwi_free_tx_ring64;
1889 sc->sc_init_rx_ring = bwi_init_rx_ring64;
1890 sc->sc_free_rx_ring = bwi_free_rx_ring64;
1891 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1892 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1893 sc->sc_rxeof = bwi_rxeof64;
1894 sc->sc_start_tx = bwi_start_tx64;
1895 if (has_txstats) {
1896 sc->sc_init_txstats = bwi_init_txstats64;
1897 sc->sc_free_txstats = bwi_free_txstats64;
1898 sc->sc_txeof_status = bwi_txeof_status64;
1899 }
1900 break;
1901 }
1902
1903 KASSERT(lowaddr != 0, ("lowaddr zero"));
1904 KASSERT(desc_sz != 0, ("desc_sz zero"));
1905 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero"));
1906
1907 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
1908 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
1909
1910 /*
1911 * Create top level DMA tag
1912 */
1913 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
1914 BWI_ALIGN, 0, /* alignment, bounds */
1915 lowaddr, /* lowaddr */
1916 BUS_SPACE_MAXADDR, /* highaddr */
1917 NULL, NULL, /* filter, filterarg */
1918 MAXBSIZE, /* maxsize */
1919 BUS_SPACE_UNRESTRICTED, /* nsegments */
1920 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1921 BUS_DMA_ALLOCNOW, /* flags */
1922 NULL, NULL, /* lockfunc, lockarg */
1923 &sc->sc_parent_dtag);
1924 if (error) {
1925 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
1926 return error;
1927 }
1928
1929 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
1930
1931 /*
1932 * Create TX ring DMA stuffs
1933 */
1934 error = bus_dma_tag_create(sc->sc_parent_dtag,
1935 BWI_RING_ALIGN, 0,
1936 BUS_SPACE_MAXADDR,
1937 BUS_SPACE_MAXADDR,
1938 NULL, NULL,
1939 tx_ring_sz,
1940 1,
1941 BUS_SPACE_MAXSIZE_32BIT,
1942 BUS_DMA_ALLOCNOW,
1943 NULL, NULL,
1944 &sc->sc_txring_dtag);
1945 if (error) {
1946 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
1947 return error;
1948 }
1949
1950 for (i = 0; i < BWI_TX_NRING; ++i) {
1951 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
1952 &sc->sc_tx_rdata[i], tx_ring_sz,
1953 TXRX_CTRL(i));
1954 if (error) {
1955 device_printf(sc->sc_dev, "%dth TX ring "
1956 "DMA alloc failed\n", i);
1957 return error;
1958 }
1959 }
1960
1961 /*
1962 * Create RX ring DMA stuffs
1963 */
1964 error = bus_dma_tag_create(sc->sc_parent_dtag,
1965 BWI_RING_ALIGN, 0,
1966 BUS_SPACE_MAXADDR,
1967 BUS_SPACE_MAXADDR,
1968 NULL, NULL,
1969 rx_ring_sz,
1970 1,
1971 BUS_SPACE_MAXSIZE_32BIT,
1972 BUS_DMA_ALLOCNOW,
1973 NULL, NULL,
1974 &sc->sc_rxring_dtag);
1975 if (error) {
1976 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
1977 return error;
1978 }
1979
1980 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
1981 rx_ring_sz, TXRX_CTRL(0));
1982 if (error) {
1983 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
1984 return error;
1985 }
1986
1987 if (has_txstats) {
1988 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
1989 if (error) {
1990 device_printf(sc->sc_dev,
1991 "TX stats DMA alloc failed\n");
1992 return error;
1993 }
1994 }
1995
1996 #undef TXRX_CTRL
1997
1998 return bwi_dma_mbuf_create(sc);
1999 }
2000
2001 static void
2002 bwi_dma_free(struct bwi_softc *sc)
2003 {
2004 if (sc->sc_txring_dtag != NULL) {
2005 int i;
2006
2007 for (i = 0; i < BWI_TX_NRING; ++i) {
2008 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
2009
2010 if (rd->rdata_desc != NULL) {
2011 bus_dmamap_unload(sc->sc_txring_dtag,
2012 rd->rdata_dmap);
2013 bus_dmamem_free(sc->sc_txring_dtag,
2014 rd->rdata_desc,
2015 rd->rdata_dmap);
2016 }
2017 }
2018 bus_dma_tag_destroy(sc->sc_txring_dtag);
2019 }
2020
2021 if (sc->sc_rxring_dtag != NULL) {
2022 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2023
2024 if (rd->rdata_desc != NULL) {
2025 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2026 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2027 rd->rdata_dmap);
2028 }
2029 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2030 }
2031
2032 bwi_dma_txstats_free(sc);
2033 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2034
2035 if (sc->sc_parent_dtag != NULL)
2036 bus_dma_tag_destroy(sc->sc_parent_dtag);
2037 }
2038
2039 static int
2040 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2041 struct bwi_ring_data *rd, bus_size_t size,
2042 uint32_t txrx_ctrl)
2043 {
2044 int error;
2045
2046 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2047 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2048 &rd->rdata_dmap);
2049 if (error) {
2050 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2051 return error;
2052 }
2053
2054 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2055 bwi_dma_ring_addr, &rd->rdata_paddr,
2056 BUS_DMA_NOWAIT);
2057 if (error) {
2058 device_printf(sc->sc_dev, "can't load DMA mem\n");
2059 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2060 rd->rdata_desc = NULL;
2061 return error;
2062 }
2063
2064 rd->rdata_txrx_ctrl = txrx_ctrl;
2065 return 0;
2066 }
2067
2068 static int
2069 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2070 bus_size_t desc_sz)
2071 {
2072 struct bwi_txstats_data *st;
2073 bus_size_t dma_size;
2074 int error;
2075
2076 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO);
2077 if (st == NULL) {
2078 device_printf(sc->sc_dev, "can't allocate txstats data\n");
2079 return ENOMEM;
2080 }
2081 sc->sc_txstats = st;
2082
2083 /*
2084 * Create TX stats descriptor DMA stuffs
2085 */
2086 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2087
2088 error = bus_dma_tag_create(sc->sc_parent_dtag,
2089 BWI_RING_ALIGN,
2090 0,
2091 BUS_SPACE_MAXADDR,
2092 BUS_SPACE_MAXADDR,
2093 NULL, NULL,
2094 dma_size,
2095 1,
2096 BUS_SPACE_MAXSIZE_32BIT,
2097 BUS_DMA_ALLOCNOW,
2098 NULL, NULL,
2099 &st->stats_ring_dtag);
2100 if (error) {
2101 device_printf(sc->sc_dev, "can't create txstats ring "
2102 "DMA tag\n");
2103 return error;
2104 }
2105
2106 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2107 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2108 &st->stats_ring_dmap);
2109 if (error) {
2110 device_printf(sc->sc_dev, "can't allocate txstats ring "
2111 "DMA mem\n");
2112 bus_dma_tag_destroy(st->stats_ring_dtag);
2113 st->stats_ring_dtag = NULL;
2114 return error;
2115 }
2116
2117 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2118 st->stats_ring, dma_size,
2119 bwi_dma_ring_addr, &st->stats_ring_paddr,
2120 BUS_DMA_NOWAIT);
2121 if (error) {
2122 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2123 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2124 st->stats_ring_dmap);
2125 bus_dma_tag_destroy(st->stats_ring_dtag);
2126 st->stats_ring_dtag = NULL;
2127 return error;
2128 }
2129
2130 /*
2131 * Create TX stats DMA stuffs
2132 */
2133 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2134 BWI_ALIGN);
2135
2136 error = bus_dma_tag_create(sc->sc_parent_dtag,
2137 BWI_ALIGN,
2138 0,
2139 BUS_SPACE_MAXADDR,
2140 BUS_SPACE_MAXADDR,
2141 NULL, NULL,
2142 dma_size,
2143 1,
2144 BUS_SPACE_MAXSIZE_32BIT,
2145 BUS_DMA_ALLOCNOW,
2146 NULL, NULL,
2147 &st->stats_dtag);
2148 if (error) {
2149 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2150 return error;
2151 }
2152
2153 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2154 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2155 &st->stats_dmap);
2156 if (error) {
2157 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2158 bus_dma_tag_destroy(st->stats_dtag);
2159 st->stats_dtag = NULL;
2160 return error;
2161 }
2162
2163 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2164 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2165 BUS_DMA_NOWAIT);
2166 if (error) {
2167 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2168 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2169 bus_dma_tag_destroy(st->stats_dtag);
2170 st->stats_dtag = NULL;
2171 return error;
2172 }
2173
2174 st->stats_ctrl_base = ctrl_base;
2175 return 0;
2176 }
2177
2178 static void
2179 bwi_dma_txstats_free(struct bwi_softc *sc)
2180 {
2181 struct bwi_txstats_data *st;
2182
2183 if (sc->sc_txstats == NULL)
2184 return;
2185 st = sc->sc_txstats;
2186
2187 if (st->stats_ring_dtag != NULL) {
2188 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2189 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2190 st->stats_ring_dmap);
2191 bus_dma_tag_destroy(st->stats_ring_dtag);
2192 }
2193
2194 if (st->stats_dtag != NULL) {
2195 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2196 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2197 bus_dma_tag_destroy(st->stats_dtag);
2198 }
2199
2200 free(st, M_DEVBUF);
2201 }
2202
2203 static void
2204 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2205 {
2206 KASSERT(nseg == 1, ("too many segments\n"));
2207 *((bus_addr_t *)arg) = seg->ds_addr;
2208 }
2209
2210 static int
2211 bwi_dma_mbuf_create(struct bwi_softc *sc)
2212 {
2213 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2214 int i, j, k, ntx, error;
2215
2216 /*
2217 * Create TX/RX mbuf DMA tag
2218 */
2219 error = bus_dma_tag_create(sc->sc_parent_dtag,
2220 1,
2221 0,
2222 BUS_SPACE_MAXADDR,
2223 BUS_SPACE_MAXADDR,
2224 NULL, NULL,
2225 MCLBYTES,
2226 1,
2227 BUS_SPACE_MAXSIZE_32BIT,
2228 BUS_DMA_ALLOCNOW,
2229 NULL, NULL,
2230 &sc->sc_buf_dtag);
2231 if (error) {
2232 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2233 return error;
2234 }
2235
2236 ntx = 0;
2237
2238 /*
2239 * Create TX mbuf DMA map
2240 */
2241 for (i = 0; i < BWI_TX_NRING; ++i) {
2242 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2243
2244 for (j = 0; j < BWI_TX_NDESC; ++j) {
2245 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2246 &tbd->tbd_buf[j].tb_dmap);
2247 if (error) {
2248 device_printf(sc->sc_dev, "can't create "
2249 "%dth tbd, %dth DMA map\n", i, j);
2250
2251 ntx = i;
2252 for (k = 0; k < j; ++k) {
2253 bus_dmamap_destroy(sc->sc_buf_dtag,
2254 tbd->tbd_buf[k].tb_dmap);
2255 }
2256 goto fail;
2257 }
2258 }
2259 }
2260 ntx = BWI_TX_NRING;
2261
2262 /*
2263 * Create RX mbuf DMA map and a spare DMA map
2264 */
2265 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2266 &rbd->rbd_tmp_dmap);
2267 if (error) {
2268 device_printf(sc->sc_dev,
2269 "can't create spare RX buf DMA map\n");
2270 goto fail;
2271 }
2272
2273 for (j = 0; j < BWI_RX_NDESC; ++j) {
2274 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2275 &rbd->rbd_buf[j].rb_dmap);
2276 if (error) {
2277 device_printf(sc->sc_dev, "can't create %dth "
2278 "RX buf DMA map\n", j);
2279
2280 for (k = 0; k < j; ++k) {
2281 bus_dmamap_destroy(sc->sc_buf_dtag,
2282 rbd->rbd_buf[j].rb_dmap);
2283 }
2284 bus_dmamap_destroy(sc->sc_buf_dtag,
2285 rbd->rbd_tmp_dmap);
2286 goto fail;
2287 }
2288 }
2289
2290 return 0;
2291 fail:
2292 bwi_dma_mbuf_destroy(sc, ntx, 0);
2293 return error;
2294 }
2295
2296 static void
2297 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2298 {
2299 int i, j;
2300
2301 if (sc->sc_buf_dtag == NULL)
2302 return;
2303
2304 for (i = 0; i < ntx; ++i) {
2305 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2306
2307 for (j = 0; j < BWI_TX_NDESC; ++j) {
2308 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2309
2310 if (tb->tb_mbuf != NULL) {
2311 bus_dmamap_unload(sc->sc_buf_dtag,
2312 tb->tb_dmap);
2313 m_freem(tb->tb_mbuf);
2314 }
2315 if (tb->tb_ni != NULL)
2316 ieee80211_free_node(tb->tb_ni);
2317 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2318 }
2319 }
2320
2321 if (nrx) {
2322 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2323
2324 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2325 for (j = 0; j < BWI_RX_NDESC; ++j) {
2326 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2327
2328 if (rb->rb_mbuf != NULL) {
2329 bus_dmamap_unload(sc->sc_buf_dtag,
2330 rb->rb_dmap);
2331 m_freem(rb->rb_mbuf);
2332 }
2333 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2334 }
2335 }
2336
2337 bus_dma_tag_destroy(sc->sc_buf_dtag);
2338 sc->sc_buf_dtag = NULL;
2339 }
2340
2341 static void
2342 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2343 {
2344 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2345 }
2346
2347 static void
2348 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2349 {
2350 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2351 }
2352
2353 static int
2354 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2355 {
2356 struct bwi_ring_data *rd;
2357 struct bwi_txbuf_data *tbd;
2358 uint32_t val, addr_hi, addr_lo;
2359
2360 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2361 rd = &sc->sc_tx_rdata[ring_idx];
2362 tbd = &sc->sc_tx_bdata[ring_idx];
2363
2364 tbd->tbd_idx = 0;
2365 tbd->tbd_used = 0;
2366
2367 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2368 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2369 BUS_DMASYNC_PREWRITE);
2370
2371 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2372 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2373
2374 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2375 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2376 BWI_TXRX32_RINGINFO_FUNC_MASK);
2377 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2378
2379 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2380 BWI_TXRX32_CTRL_ENABLE;
2381 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2382
2383 return 0;
2384 }
2385
2386 static void
2387 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2388 bus_addr_t paddr, int hdr_size, int ndesc)
2389 {
2390 uint32_t val, addr_hi, addr_lo;
2391
2392 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2393 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2394
2395 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2396 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2397 BWI_TXRX32_RINGINFO_FUNC_MASK);
2398 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2399
2400 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2401 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2402 BWI_TXRX32_CTRL_ENABLE;
2403 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2404
2405 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2406 (ndesc - 1) * sizeof(struct bwi_desc32));
2407 }
2408
2409 static int
2410 bwi_init_rx_ring32(struct bwi_softc *sc)
2411 {
2412 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2413 int i, error;
2414
2415 sc->sc_rx_bdata.rbd_idx = 0;
2416
2417 for (i = 0; i < BWI_RX_NDESC; ++i) {
2418 error = bwi_newbuf(sc, i, 1);
2419 if (error) {
2420 device_printf(sc->sc_dev,
2421 "can't allocate %dth RX buffer\n", i);
2422 return error;
2423 }
2424 }
2425 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2426 BUS_DMASYNC_PREWRITE);
2427
2428 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2429 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2430 return 0;
2431 }
2432
2433 static int
2434 bwi_init_txstats32(struct bwi_softc *sc)
2435 {
2436 struct bwi_txstats_data *st = sc->sc_txstats;
2437 bus_addr_t stats_paddr;
2438 int i;
2439
2440 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2441 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2442
2443 st->stats_idx = 0;
2444
2445 stats_paddr = st->stats_paddr;
2446 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2447 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2448 stats_paddr, sizeof(struct bwi_txstats), 0);
2449 stats_paddr += sizeof(struct bwi_txstats);
2450 }
2451 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2452 BUS_DMASYNC_PREWRITE);
2453
2454 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2455 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2456 return 0;
2457 }
2458
2459 static void
2460 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2461 int buf_len)
2462 {
2463 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2464
2465 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2466 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2467 paddr, buf_len, 0);
2468 }
2469
2470 static void
2471 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2472 int buf_idx, bus_addr_t paddr, int buf_len)
2473 {
2474 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
2475 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2476 paddr, buf_len, 1);
2477 }
2478
2479 static int
2480 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2481 {
2482 /* TODO:64 */
2483 return EOPNOTSUPP;
2484 }
2485
2486 static int
2487 bwi_init_rx_ring64(struct bwi_softc *sc)
2488 {
2489 /* TODO:64 */
2490 return EOPNOTSUPP;
2491 }
2492
2493 static int
2494 bwi_init_txstats64(struct bwi_softc *sc)
2495 {
2496 /* TODO:64 */
2497 return EOPNOTSUPP;
2498 }
2499
2500 static void
2501 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2502 int buf_len)
2503 {
2504 /* TODO:64 */
2505 }
2506
2507 static void
2508 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2509 int buf_idx, bus_addr_t paddr, int buf_len)
2510 {
2511 /* TODO:64 */
2512 }
2513
2514 static void
2515 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2516 bus_size_t mapsz __unused, int error)
2517 {
2518 if (!error) {
2519 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2520 *((bus_addr_t *)arg) = seg->ds_addr;
2521 }
2522 }
2523
2524 static int
2525 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2526 {
2527 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2528 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2529 struct bwi_rxbuf_hdr *hdr;
2530 bus_dmamap_t map;
2531 bus_addr_t paddr;
2532 struct mbuf *m;
2533 int error;
2534
2535 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2536
2537 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2538 if (m == NULL) {
2539 error = ENOBUFS;
2540
2541 /*
2542 * If the NIC is up and running, we need to:
2543 * - Clear RX buffer's header.
2544 * - Restore RX descriptor settings.
2545 */
2546 if (init)
2547 return error;
2548 else
2549 goto back;
2550 }
2551 m->m_len = m->m_pkthdr.len = MCLBYTES;
2552
2553 /*
2554 * Try to load RX buf into temporary DMA map
2555 */
2556 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2557 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
2558 if (error) {
2559 m_freem(m);
2560
2561 /*
2562 * See the comment above
2563 */
2564 if (init)
2565 return error;
2566 else
2567 goto back;
2568 }
2569
2570 if (!init)
2571 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2572 rxbuf->rb_mbuf = m;
2573 rxbuf->rb_paddr = paddr;
2574
2575 /*
2576 * Swap RX buf's DMA map with the loaded temporary one
2577 */
2578 map = rxbuf->rb_dmap;
2579 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2580 rbd->rbd_tmp_dmap = map;
2581
2582 back:
2583 /*
2584 * Clear RX buf header
2585 */
2586 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2587 bzero(hdr, sizeof(*hdr));
2588 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2589
2590 /*
2591 * Setup RX buf descriptor
2592 */
2593 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2594 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2595 return error;
2596 }
2597
2598 static void
2599 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2600 const uint8_t *addr)
2601 {
2602 int i;
2603
2604 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2605 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2606
2607 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2608 uint16_t addr_val;
2609
2610 addr_val = (uint16_t)addr[i * 2] |
2611 (((uint16_t)addr[(i * 2) + 1]) << 8);
2612 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2613 }
2614 }
2615
2616 static int
2617 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2618 {
2619 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2620 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2621 struct ifnet *ifp = sc->sc_ifp;
2622 struct ieee80211com *ic = ifp->if_l2com;
2623 int idx, rx_data = 0;
2624
2625 idx = rbd->rbd_idx;
2626 while (idx != end_idx) {
2627 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2628 struct bwi_rxbuf_hdr *hdr;
2629 struct ieee80211_frame_min *wh;
2630 struct ieee80211_node *ni;
2631 struct mbuf *m;
2632 const void *plcp;
2633 uint16_t flags2;
2634 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate;
2635
2636 m = rb->rb_mbuf;
2637 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2638 BUS_DMASYNC_POSTREAD);
2639
2640 if (bwi_newbuf(sc, idx, 0)) {
2641 ifp->if_ierrors++;
2642 goto next;
2643 }
2644
2645 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2646 flags2 = le16toh(hdr->rxh_flags2);
2647
2648 hdr_extra = 0;
2649 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2650 hdr_extra = 2;
2651 wh_ofs = hdr_extra + 6; /* XXX magic number */
2652
2653 buflen = le16toh(hdr->rxh_buflen);
2654 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2655 if_printf(ifp, "%s: zero length data, hdr_extra %d\n",
2656 __func__, hdr_extra);
2657 ifp->if_ierrors++;
2658 m_freem(m);
2659 goto next;
2660 }
2661
2662 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra);
2663 rssi = bwi_calc_rssi(sc, hdr);
2664 noise = bwi_calc_noise(sc);
2665
2666 m->m_pkthdr.rcvif = ifp;
2667 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2668 m_adj(m, sizeof(*hdr) + wh_ofs);
2669
2670 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2671 rate = bwi_ofdm_plcp2rate(plcp);
2672 else
2673 rate = bwi_ds_plcp2rate(plcp);
2674
2675 /* RX radio tap */
2676 if (ieee80211_radiotap_active(ic))
2677 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi, noise);
2678
2679 m_adj(m, -IEEE80211_CRC_LEN);
2680
2681 BWI_UNLOCK(sc);
2682
2683 wh = mtod(m, struct ieee80211_frame_min *);
2684 ni = ieee80211_find_rxnode(ic, wh);
2685 if (ni != NULL) {
2686 type = ieee80211_input(ni, m, rssi - noise, noise);
2687 ieee80211_free_node(ni);
2688 } else
2689 type = ieee80211_input_all(ic, m, rssi - noise, noise);
2690 if (type == IEEE80211_FC0_TYPE_DATA) {
2691 rx_data = 1;
2692 sc->sc_rx_rate = rate;
2693 }
2694
2695 BWI_LOCK(sc);
2696 next:
2697 idx = (idx + 1) % BWI_RX_NDESC;
2698
2699 if (sc->sc_flags & BWI_F_STOP) {
2700 /*
2701 * Take the fast lane, don't do
2702 * any damage to softc
2703 */
2704 return -1;
2705 }
2706 }
2707
2708 rbd->rbd_idx = idx;
2709 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2710 BUS_DMASYNC_PREWRITE);
2711
2712 return rx_data;
2713 }
2714
2715 static int
2716 bwi_rxeof32(struct bwi_softc *sc)
2717 {
2718 uint32_t val, rx_ctrl;
2719 int end_idx, rx_data;
2720
2721 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2722
2723 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2724 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2725 sizeof(struct bwi_desc32);
2726
2727 rx_data = bwi_rxeof(sc, end_idx);
2728 if (rx_data >= 0) {
2729 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2730 end_idx * sizeof(struct bwi_desc32));
2731 }
2732 return rx_data;
2733 }
2734
2735 static int
2736 bwi_rxeof64(struct bwi_softc *sc)
2737 {
2738 /* TODO:64 */
2739 return 0;
2740 }
2741
2742 static void
2743 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2744 {
2745 int i;
2746
2747 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2748
2749 #define NRETRY 10
2750
2751 for (i = 0; i < NRETRY; ++i) {
2752 uint32_t status;
2753
2754 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2755 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2756 BWI_RX32_STATUS_STATE_DISABLED)
2757 break;
2758
2759 DELAY(1000);
2760 }
2761 if (i == NRETRY)
2762 device_printf(sc->sc_dev, "reset rx ring timedout\n");
2763
2764 #undef NRETRY
2765
2766 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2767 }
2768
2769 static void
2770 bwi_free_txstats32(struct bwi_softc *sc)
2771 {
2772 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2773 }
2774
2775 static void
2776 bwi_free_rx_ring32(struct bwi_softc *sc)
2777 {
2778 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2779 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2780 int i;
2781
2782 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2783
2784 for (i = 0; i < BWI_RX_NDESC; ++i) {
2785 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2786
2787 if (rb->rb_mbuf != NULL) {
2788 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2789 m_freem(rb->rb_mbuf);
2790 rb->rb_mbuf = NULL;
2791 }
2792 }
2793 }
2794
2795 static void
2796 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2797 {
2798 struct bwi_ring_data *rd;
2799 struct bwi_txbuf_data *tbd;
2800 struct ifnet *ifp = sc->sc_ifp;
2801 uint32_t state, val;
2802 int i;
2803
2804 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2805 rd = &sc->sc_tx_rdata[ring_idx];
2806 tbd = &sc->sc_tx_bdata[ring_idx];
2807
2808 #define NRETRY 10
2809
2810 for (i = 0; i < NRETRY; ++i) {
2811 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2812 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2813 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2814 state == BWI_TX32_STATUS_STATE_IDLE ||
2815 state == BWI_TX32_STATUS_STATE_STOPPED)
2816 break;
2817
2818 DELAY(1000);
2819 }
2820 if (i == NRETRY) {
2821 if_printf(ifp, "%s: wait for TX ring(%d) stable timed out\n",
2822 __func__, ring_idx);
2823 }
2824
2825 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2826 for (i = 0; i < NRETRY; ++i) {
2827 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2828 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2829 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2830 break;
2831
2832 DELAY(1000);
2833 }
2834 if (i == NRETRY)
2835 if_printf(ifp, "%s: reset TX ring (%d) timed out\n",
2836 __func__, ring_idx);
2837
2838 #undef NRETRY
2839
2840 DELAY(1000);
2841
2842 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2843
2844 for (i = 0; i < BWI_TX_NDESC; ++i) {
2845 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2846
2847 if (tb->tb_mbuf != NULL) {
2848 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2849 m_freem(tb->tb_mbuf);
2850 tb->tb_mbuf = NULL;
2851 }
2852 if (tb->tb_ni != NULL) {
2853 ieee80211_free_node(tb->tb_ni);
2854 tb->tb_ni = NULL;
2855 }
2856 }
2857 }
2858
2859 static void
2860 bwi_free_txstats64(struct bwi_softc *sc)
2861 {
2862 /* TODO:64 */
2863 }
2864
2865 static void
2866 bwi_free_rx_ring64(struct bwi_softc *sc)
2867 {
2868 /* TODO:64 */
2869 }
2870
2871 static void
2872 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2873 {
2874 /* TODO:64 */
2875 }
2876
2877 /* XXX does not belong here */
2878 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
2879 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
2880
2881 static __inline void
2882 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
2883 {
2884 uint32_t plcp;
2885
2886 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM),
2887 IEEE80211_OFDM_PLCP_RATE_MASK) |
2888 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
2889 *plcp0 = htole32(plcp);
2890 }
2891
2892 static __inline void
2893 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
2894 uint8_t rate)
2895 {
2896 int len, service, pkt_bitlen;
2897
2898 pkt_bitlen = pkt_len * NBBY;
2899 len = howmany(pkt_bitlen * 2, rate);
2900
2901 service = IEEE80211_PLCP_SERVICE_LOCKED;
2902 if (rate == (11 * 2)) {
2903 int pkt_bitlen1;
2904
2905 /*
2906 * PLCP service field needs to be adjusted,
2907 * if TX rate is 11Mbytes/s
2908 */
2909 pkt_bitlen1 = len * 11;
2910 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
2911 service |= IEEE80211_PLCP_SERVICE_LENEXT7;
2912 }
2913
2914 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK);
2915 plcp->i_service = service;
2916 plcp->i_length = htole16(len);
2917 /* NOTE: do NOT touch i_crc */
2918 }
2919
2920 static __inline void
2921 bwi_plcp_header(const struct ieee80211_rate_table *rt,
2922 void *plcp, int pkt_len, uint8_t rate)
2923 {
2924 enum ieee80211_phytype modtype;
2925
2926 /*
2927 * Assume caller has zeroed 'plcp'
2928 */
2929 modtype = ieee80211_rate2phytype(rt, rate);
2930 if (modtype == IEEE80211_T_OFDM)
2931 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
2932 else if (modtype == IEEE80211_T_DS)
2933 bwi_ds_plcp_header(plcp, pkt_len, rate);
2934 else
2935 panic("unsupport modulation type %u\n", modtype);
2936 }
2937
2938 static int
2939 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2940 struct ieee80211_node *ni)
2941 {
2942 struct ieee80211vap *vap = ni->ni_vap;
2943 struct ifnet *ifp = sc->sc_ifp;
2944 struct ieee80211com *ic = ifp->if_l2com;
2945 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2946 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2947 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2948 struct bwi_mac *mac;
2949 struct bwi_txbuf_hdr *hdr;
2950 struct ieee80211_frame *wh;
2951 const struct ieee80211_txparam *tp;
2952 uint8_t rate, rate_fb;
2953 uint32_t mac_ctrl;
2954 uint16_t phy_ctrl;
2955 bus_addr_t paddr;
2956 int type, ismcast, pkt_len, error, rix;
2957 #if 0
2958 const uint8_t *p;
2959 int i;
2960 #endif
2961
2962 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
2963 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
2964 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2965
2966 wh = mtod(m, struct ieee80211_frame *);
2967 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2968 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
2969
2970 /* Get 802.11 frame len before prepending TX header */
2971 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2972
2973 /*
2974 * Find TX rate
2975 */
2976 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
2977 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) {
2978 rate = rate_fb = tp->mgmtrate;
2979 } else if (ismcast) {
2980 rate = rate_fb = tp->mcastrate;
2981 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
2982 rate = rate_fb = tp->ucastrate;
2983 } else {
2984 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len);
2985 rate = ni->ni_txrate;
2986
2987 if (rix > 0) {
2988 rate_fb = ni->ni_rates.rs_rates[rix-1] &
2989 IEEE80211_RATE_VAL;
2990 } else {
2991 rate_fb = rate;
2992 }
2993 }
2994 tb->tb_rate[0] = rate;
2995 tb->tb_rate[1] = rate_fb;
2996 sc->sc_tx_rate = rate;
2997
2998 /*
2999 * TX radio tap
3000 */
3001 if (ieee80211_radiotap_active_vap(vap)) {
3002 sc->sc_tx_th.wt_flags = 0;
3003 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3004 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3005 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS &&
3006 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3007 rate != (1 * 2)) {
3008 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3009 }
3010 sc->sc_tx_th.wt_rate = rate;
3011
3012 ieee80211_radiotap_tx(vap, m);
3013 }
3014
3015 /*
3016 * Setup the embedded TX header
3017 */
3018 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT);
3019 if (m == NULL) {
3020 if_printf(ifp, "%s: prepend TX header failed\n", __func__);
3021 return ENOBUFS;
3022 }
3023 hdr = mtod(m, struct bwi_txbuf_hdr *);
3024
3025 bzero(hdr, sizeof(*hdr));
3026
3027 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3028 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3029
3030 if (!ismcast) {
3031 uint16_t dur;
3032
3033 dur = ieee80211_ack_duration(sc->sc_rates, rate,
3034 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
3035
3036 hdr->txh_fb_duration = htole16(dur);
3037 }
3038
3039 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3040 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3041
3042 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3043 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3044
3045 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3046 BWI_TXH_PHY_C_ANTMODE_MASK);
3047 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM)
3048 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3049 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3050 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3051
3052 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3053 if (!ismcast)
3054 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3055 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM)
3056 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3057
3058 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3059 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3060
3061 /* Catch any further usage */
3062 hdr = NULL;
3063 wh = NULL;
3064
3065 /* DMA load */
3066 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3067 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3068 if (error && error != EFBIG) {
3069 if_printf(ifp, "%s: can't load TX buffer (1) %d\n",
3070 __func__, error);
3071 goto back;
3072 }
3073
3074 if (error) { /* error == EFBIG */
3075 struct mbuf *m_new;
3076
3077 m_new = m_defrag(m, M_DONTWAIT);
3078 if (m_new == NULL) {
3079 if_printf(ifp, "%s: can't defrag TX buffer\n",
3080 __func__);
3081 error = ENOBUFS;
3082 goto back;
3083 } else {
3084 m = m_new;
3085 }
3086
3087 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3088 bwi_dma_buf_addr, &paddr,
3089 BUS_DMA_NOWAIT);
3090 if (error) {
3091 if_printf(ifp, "%s: can't load TX buffer (2) %d\n",
3092 __func__, error);
3093 goto back;
3094 }
3095 }
3096 error = 0;
3097
3098 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3099
3100 tb->tb_mbuf = m;
3101 tb->tb_ni = ni;
3102
3103 #if 0
3104 p = mtod(m, const uint8_t *);
3105 for (i = 0; i < m->m_pkthdr.len; ++i) {
3106 if (i != 0 && i % 8 == 0)
3107 printf("\n");
3108 printf("%02x ", p[i]);
3109 }
3110 printf("\n");
3111 #endif
3112 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3113 idx, pkt_len, m->m_pkthdr.len);
3114
3115 /* Setup TX descriptor */
3116 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3117 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3118 BUS_DMASYNC_PREWRITE);
3119
3120 /* Kick start */
3121 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3122
3123 back:
3124 if (error)
3125 m_freem(m);
3126 return error;
3127 }
3128
3129 static int
3130 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m,
3131 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
3132 {
3133 struct ifnet *ifp = sc->sc_ifp;
3134 struct ieee80211vap *vap = ni->ni_vap;
3135 struct ieee80211com *ic = ni->ni_ic;
3136 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
3137 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
3138 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3139 struct bwi_mac *mac;
3140 struct bwi_txbuf_hdr *hdr;
3141 struct ieee80211_frame *wh;
3142 uint8_t rate, rate_fb;
3143 uint32_t mac_ctrl;
3144 uint16_t phy_ctrl;
3145 bus_addr_t paddr;
3146 int ismcast, pkt_len, error;
3147
3148 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3149 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3150 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3151
3152 wh = mtod(m, struct ieee80211_frame *);
3153 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3154
3155 /* Get 802.11 frame len before prepending TX header */
3156 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3157
3158 /*
3159 * Find TX rate
3160 */
3161 rate = params->ibp_rate0;
3162 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
3163 /* XXX fall back to mcast/mgmt rate? */
3164 m_freem(m);
3165 return EINVAL;
3166 }
3167 if (params->ibp_try1 != 0) {
3168 rate_fb = params->ibp_rate1;
3169 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) {
3170 /* XXX fall back to rate0? */
3171 m_freem(m);
3172 return EINVAL;
3173 }
3174 } else
3175 rate_fb = rate;
3176 tb->tb_rate[0] = rate;
3177 tb->tb_rate[1] = rate_fb;
3178 sc->sc_tx_rate = rate;
3179
3180 /*
3181 * TX radio tap
3182 */
3183 if (ieee80211_radiotap_active_vap(vap)) {
3184 sc->sc_tx_th.wt_flags = 0;
3185 /* XXX IEEE80211_BPF_CRYPTO */
3186 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3187 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3188 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3189 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3190 sc->sc_tx_th.wt_rate = rate;
3191
3192 ieee80211_radiotap_tx(vap, m);
3193 }
3194
3195 /*
3196 * Setup the embedded TX header
3197 */
3198 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT);
3199 if (m == NULL) {
3200 if_printf(ifp, "%s: prepend TX header failed\n", __func__);
3201 return ENOBUFS;
3202 }
3203 hdr = mtod(m, struct bwi_txbuf_hdr *);
3204
3205 bzero(hdr, sizeof(*hdr));
3206
3207 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3208 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3209
3210 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3211 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
3212 uint16_t dur;
3213
3214 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0);
3215
3216 hdr->txh_fb_duration = htole16(dur);
3217 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3218 }
3219
3220 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3221 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3222
3223 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3224 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3225
3226 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3227 BWI_TXH_PHY_C_ANTMODE_MASK);
3228 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) {
3229 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3230 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3231 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3232 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3233
3234 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3235 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3236
3237 /* Catch any further usage */
3238 hdr = NULL;
3239 wh = NULL;
3240
3241 /* DMA load */
3242 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3243 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3244 if (error != 0) {
3245 struct mbuf *m_new;
3246
3247 if (error != EFBIG) {
3248 if_printf(ifp, "%s: can't load TX buffer (1) %d\n",
3249 __func__, error);
3250 goto back;
3251 }
3252 m_new = m_defrag(m, M_DONTWAIT);
3253 if (m_new == NULL) {
3254 if_printf(ifp, "%s: can't defrag TX buffer\n",
3255 __func__);
3256 error = ENOBUFS;
3257 goto back;
3258 }
3259 m = m_new;
3260 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3261 bwi_dma_buf_addr, &paddr,
3262 BUS_DMA_NOWAIT);
3263 if (error) {
3264 if_printf(ifp, "%s: can't load TX buffer (2) %d\n",
3265 __func__, error);
3266 goto back;
3267 }
3268 }
3269
3270 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3271
3272 tb->tb_mbuf = m;
3273 tb->tb_ni = ni;
3274
3275 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3276 idx, pkt_len, m->m_pkthdr.len);
3277
3278 /* Setup TX descriptor */
3279 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3280 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3281 BUS_DMASYNC_PREWRITE);
3282
3283 /* Kick start */
3284 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3285 back:
3286 if (error)
3287 m_freem(m);
3288 return error;
3289 }
3290
3291 static void
3292 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3293 {
3294 idx = (idx + 1) % BWI_TX_NDESC;
3295 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3296 idx * sizeof(struct bwi_desc32));
3297 }
3298
3299 static void
3300 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3301 {
3302 /* TODO:64 */
3303 }
3304
3305 static void
3306 bwi_txeof_status32(struct bwi_softc *sc)
3307 {
3308 struct ifnet *ifp = sc->sc_ifp;
3309 uint32_t val, ctrl_base;
3310 int end_idx;
3311
3312 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3313
3314 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3315 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3316 sizeof(struct bwi_desc32);
3317
3318 bwi_txeof_status(sc, end_idx);
3319
3320 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3321 end_idx * sizeof(struct bwi_desc32));
3322
3323 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0)
3324 ifp->if_start(ifp);
3325 }
3326
3327 static void
3328 bwi_txeof_status64(struct bwi_softc *sc)
3329 {
3330 /* TODO:64 */
3331 }
3332
3333 static void
3334 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3335 {
3336 struct ifnet *ifp = sc->sc_ifp;
3337 struct bwi_txbuf_data *tbd;
3338 struct bwi_txbuf *tb;
3339 int ring_idx, buf_idx;
3340 struct ieee80211_node *ni;
3341 struct ieee80211vap *vap;
3342
3343 if (tx_id == 0) {
3344 if_printf(ifp, "%s: zero tx id\n", __func__);
3345 return;
3346 }
3347
3348 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3349 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3350
3351 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx));
3352 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
3353
3354 tbd = &sc->sc_tx_bdata[ring_idx];
3355 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used));
3356 tbd->tbd_used--;
3357
3358 tb = &tbd->tbd_buf[buf_idx];
3359 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3360 "acked %d, data_txcnt %d, ni %p\n",
3361 buf_idx, acked, data_txcnt, tb->tb_ni);
3362
3363 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3364
3365 ni = tb->tb_ni;
3366 if (tb->tb_ni != NULL) {
3367 const struct bwi_txbuf_hdr *hdr =
3368 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *);
3369 vap = ni->ni_vap;
3370
3371 /* NB: update rate control only for unicast frames */
3372 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) {
3373 /*
3374 * Feed back 'acked and data_txcnt'. Note that the
3375 * generic AMRR code only understands one tx rate
3376 * and the estimator doesn't handle real retry counts
3377 * well so to avoid over-aggressive downshifting we
3378 * treat any number of retries as "1".
3379 */
3380 ieee80211_ratectl_tx_complete(vap, ni,
3381 (data_txcnt > 1) ? IEEE80211_RATECTL_TX_SUCCESS :
3382 IEEE80211_RATECTL_TX_FAILURE, &acked, NULL);
3383 }
3384
3385 /*
3386 * Do any tx complete callback. Note this must
3387 * be done before releasing the node reference.
3388 */
3389 if (tb->tb_mbuf->m_flags & M_TXCB)
3390 ieee80211_process_callback(ni, tb->tb_mbuf, !acked);
3391
3392 ieee80211_free_node(tb->tb_ni);
3393 tb->tb_ni = NULL;
3394 }
3395 m_freem(tb->tb_mbuf);
3396 tb->tb_mbuf = NULL;
3397
3398 if (tbd->tbd_used == 0)
3399 sc->sc_tx_timer = 0;
3400
3401 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3402 }
3403
3404 static void
3405 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3406 {
3407 struct bwi_txstats_data *st = sc->sc_txstats;
3408 int idx;
3409
3410 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3411
3412 idx = st->stats_idx;
3413 while (idx != end_idx) {
3414 const struct bwi_txstats *stats = &st->stats[idx];
3415
3416 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3417 int data_txcnt;
3418
3419 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3420 BWI_TXS_TXCNT_DATA);
3421 _bwi_txeof(sc, le16toh(stats->txs_id),
3422 stats->txs_flags & BWI_TXS_F_ACKED,
3423 data_txcnt);
3424 }
3425 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3426 }
3427 st->stats_idx = idx;
3428 }
3429
3430 static void
3431 bwi_txeof(struct bwi_softc *sc)
3432 {
3433 struct ifnet *ifp = sc->sc_ifp;
3434
3435 for (;;) {
3436 uint32_t tx_status0, tx_status1;
3437 uint16_t tx_id;
3438 int data_txcnt;
3439
3440 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3441 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3442 break;
3443 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3444
3445 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3446 data_txcnt = __SHIFTOUT(tx_status0,
3447 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3448
3449 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3450 continue;
3451
3452 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED,
3453 data_txcnt);
3454 }
3455
3456 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0)
3457 ifp->if_start(ifp);
3458 }
3459
3460 static int
3461 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3462 {
3463 bwi_power_on(sc, 1);
3464 return bwi_set_clock_mode(sc, clk_mode);
3465 }
3466
3467 static void
3468 bwi_bbp_power_off(struct bwi_softc *sc)
3469 {
3470 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3471 bwi_power_off(sc, 1);
3472 }
3473
3474 static int
3475 bwi_get_pwron_delay(struct bwi_softc *sc)
3476 {
3477 struct bwi_regwin *com, *old;
3478 struct bwi_clock_freq freq;
3479 uint32_t val;
3480 int error;
3481
3482 com = &sc->sc_com_regwin;
3483 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin"));
3484
3485 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3486 return 0;
3487
3488 error = bwi_regwin_switch(sc, com, &old);
3489 if (error)
3490 return error;
3491
3492 bwi_get_clock_freq(sc, &freq);
3493
3494 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3495 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3496 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3497
3498 return bwi_regwin_switch(sc, old, NULL);
3499 }
3500
3501 static int
3502 bwi_bus_attach(struct bwi_softc *sc)
3503 {
3504 struct bwi_regwin *bus, *old;
3505 int error;
3506
3507 bus = &sc->sc_bus_regwin;
3508
3509 error = bwi_regwin_switch(sc, bus, &old);
3510 if (error)
3511 return error;
3512
3513 if (!bwi_regwin_is_enabled(sc, bus))
3514 bwi_regwin_enable(sc, bus, 0);
3515
3516 /* Disable interripts */
3517 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3518
3519 return bwi_regwin_switch(sc, old, NULL);
3520 }
3521
3522 static const char *
3523 bwi_regwin_name(const struct bwi_regwin *rw)
3524 {
3525 switch (rw->rw_type) {
3526 case BWI_REGWIN_T_COM:
3527 return "COM";
3528 case BWI_REGWIN_T_BUSPCI:
3529 return "PCI";
3530 case BWI_REGWIN_T_MAC:
3531 return "MAC";
3532 case BWI_REGWIN_T_BUSPCIE:
3533 return "PCIE";
3534 }
3535 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3536 return NULL;
3537 }
3538
3539 static uint32_t
3540 bwi_regwin_disable_bits(struct bwi_softc *sc)
3541 {
3542 uint32_t busrev;
3543
3544 /* XXX cache this */
3545 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3546 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3547 "bus rev %u\n", busrev);
3548
3549 if (busrev == BWI_BUSREV_0)
3550 return BWI_STATE_LO_DISABLE1;
3551 else if (busrev == BWI_BUSREV_1)
3552 return BWI_STATE_LO_DISABLE2;
3553 else
3554 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3555 }
3556
3557 int
3558 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3559 {
3560 uint32_t val, disable_bits;
3561
3562 disable_bits = bwi_regwin_disable_bits(sc);
3563 val = CSR_READ_4(sc, BWI_STATE_LO);
3564
3565 if ((val & (BWI_STATE_LO_CLOCK |
3566 BWI_STATE_LO_RESET |
3567 disable_bits)) == BWI_STATE_LO_CLOCK) {
3568 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3569 bwi_regwin_name(rw));
3570 return 1;
3571 } else {
3572 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3573 bwi_regwin_name(rw));
3574 return 0;
3575 }
3576 }
3577
3578 void
3579 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3580 {
3581 uint32_t state_lo, disable_bits;
3582 int i;
3583
3584 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3585
3586 /*
3587 * If current regwin is in 'reset' state, it was already disabled.
3588 */
3589 if (state_lo & BWI_STATE_LO_RESET) {
3590 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3591 "%s was already disabled\n", bwi_regwin_name(rw));
3592 return;
3593 }
3594
3595 disable_bits = bwi_regwin_disable_bits(sc);
3596
3597 /*
3598 * Disable normal clock
3599 */
3600 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3601 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3602
3603 /*
3604 * Wait until normal clock is disabled
3605 */
3606 #define NRETRY 1000
3607 for (i = 0; i < NRETRY; ++i) {
3608 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3609 if (state_lo & disable_bits)
3610 break;
3611 DELAY(10);
3612 }
3613 if (i == NRETRY) {
3614 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3615 bwi_regwin_name(rw));
3616 }
3617
3618 for (i = 0; i < NRETRY; ++i) {
3619 uint32_t state_hi;
3620
3621 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3622 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3623 break;
3624 DELAY(10);
3625 }
3626 if (i == NRETRY) {
3627 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3628 bwi_regwin_name(rw));
3629 }
3630 #undef NRETRY
3631
3632 /*
3633 * Reset and disable regwin with gated clock
3634 */
3635 state_lo = BWI_STATE_LO_RESET | disable_bits |
3636 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3637 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3638 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3639
3640 /* Flush pending bus write */
3641 CSR_READ_4(sc, BWI_STATE_LO);
3642 DELAY(1);
3643
3644 /* Reset and disable regwin */
3645 state_lo = BWI_STATE_LO_RESET | disable_bits |
3646 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3647 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3648
3649 /* Flush pending bus write */
3650 CSR_READ_4(sc, BWI_STATE_LO);
3651 DELAY(1);
3652 }
3653
3654 void
3655 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3656 {
3657 uint32_t state_lo, state_hi, imstate;
3658
3659 bwi_regwin_disable(sc, rw, flags);
3660
3661 /* Reset regwin with gated clock */
3662 state_lo = BWI_STATE_LO_RESET |
3663 BWI_STATE_LO_CLOCK |
3664 BWI_STATE_LO_GATED_CLOCK |
3665 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3666 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3667
3668 /* Flush pending bus write */
3669 CSR_READ_4(sc, BWI_STATE_LO);
3670 DELAY(1);
3671
3672 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3673 if (state_hi & BWI_STATE_HI_SERROR)
3674 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3675
3676 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3677 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3678 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3679 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3680 }
3681
3682 /* Enable regwin with gated clock */
3683 state_lo = BWI_STATE_LO_CLOCK |
3684 BWI_STATE_LO_GATED_CLOCK |
3685 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3686 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3687
3688 /* Flush pending bus write */
3689 CSR_READ_4(sc, BWI_STATE_LO);
3690 DELAY(1);
3691
3692 /* Enable regwin with normal clock */
3693 state_lo = BWI_STATE_LO_CLOCK |
3694 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3695 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3696
3697 /* Flush pending bus write */
3698 CSR_READ_4(sc, BWI_STATE_LO);
3699 DELAY(1);
3700 }
3701
3702 static void
3703 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3704 {
3705 struct ifnet *ifp = sc->sc_ifp;
3706 struct bwi_mac *mac;
3707 struct bwi_myaddr_bssid buf;
3708 const uint8_t *p;
3709 uint32_t val;
3710 int n, i;
3711
3712 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3713 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3714 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3715
3716 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3717
3718 bcopy(IF_LLADDR(ifp), buf.myaddr, sizeof(buf.myaddr));
3719 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3720
3721 n = sizeof(buf) / sizeof(val);
3722 p = (const uint8_t *)&buf;
3723 for (i = 0; i < n; ++i) {
3724 int j;
3725
3726 val = 0;
3727 for (j = 0; j < sizeof(val); ++j)
3728 val |= ((uint32_t)(*p++)) << (j * 8);
3729
3730 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3731 }
3732 }
3733
3734 static void
3735 bwi_updateslot(struct ifnet *ifp)
3736 {
3737 struct bwi_softc *sc = ifp->if_softc;
3738 struct ieee80211com *ic = ifp->if_l2com;
3739 struct bwi_mac *mac;
3740
3741 BWI_LOCK(sc);
3742 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3743 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3744
3745 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3746 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3747 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3748
3749 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3750 }
3751 BWI_UNLOCK(sc);
3752 }
3753
3754 static void
3755 bwi_calibrate(void *xsc)
3756 {
3757 struct bwi_softc *sc = xsc;
3758 #ifdef INVARIANTS
3759 struct ifnet *ifp = sc->sc_ifp;
3760 struct ieee80211com *ic = ifp->if_l2com;
3761 #endif
3762 struct bwi_mac *mac;
3763
3764 BWI_ASSERT_LOCKED(sc);
3765
3766 KASSERT(ic->ic_opmode != IEEE80211_M_MONITOR,
3767 ("opmode %d", ic->ic_opmode));
3768
3769 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3770 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3771 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3772
3773 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3774 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3775
3776 /* XXX 15 seconds */
3777 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3778 }
3779
3780 static int
3781 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3782 {
3783 struct bwi_mac *mac;
3784
3785 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3786 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3787 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3788
3789 return bwi_rf_calc_rssi(mac, hdr);
3790 }
3791
3792 static int
3793 bwi_calc_noise(struct bwi_softc *sc)
3794 {
3795 struct bwi_mac *mac;
3796
3797 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3798 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3799 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3800
3801 return bwi_rf_calc_noise(mac);
3802 }
3803
3804 static __inline uint8_t
3805 bwi_ofdm_plcp2rate(const uint32_t *plcp0)
3806 {
3807 uint32_t plcp;
3808 uint8_t plcp_rate;
3809
3810 plcp = le32toh(*plcp0);
3811 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);
3812 return ieee80211_plcp2rate(plcp_rate, IEEE80211_T_OFDM);
3813 }
3814
3815 static __inline uint8_t
3816 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr)
3817 {
3818 return ieee80211_plcp2rate(hdr->i_signal, IEEE80211_T_DS);
3819 }
3820
3821 static void
3822 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3823 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise)
3824 {
3825 const struct ieee80211_frame_min *wh;
3826
3827 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3828 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3829 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3830
3831 wh = mtod(m, const struct ieee80211_frame_min *);
3832 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3833 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3834
3835 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */
3836 sc->sc_rx_th.wr_rate = rate;
3837 sc->sc_rx_th.wr_antsignal = rssi;
3838 sc->sc_rx_th.wr_antnoise = noise;
3839 }
3840
3841 static void
3842 bwi_led_attach(struct bwi_softc *sc)
3843 {
3844 const uint8_t *led_act = NULL;
3845 uint16_t gpio, val[BWI_LED_MAX];
3846 int i;
3847
3848 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
3849
3850 for (i = 0; i < N(bwi_vendor_led_act); ++i) {
3851 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3852 led_act = bwi_vendor_led_act[i].led_act;
3853 break;
3854 }
3855 }
3856 if (led_act == NULL)
3857 led_act = bwi_default_led_act;
3858
3859 #undef N
3860
3861 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3862 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3863 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3864
3865 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3866 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3867 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3868
3869 for (i = 0; i < BWI_LED_MAX; ++i) {
3870 struct bwi_led *led = &sc->sc_leds[i];
3871
3872 if (val[i] == 0xff) {
3873 led->l_act = led_act[i];
3874 } else {
3875 if (val[i] & BWI_LED_ACT_LOW)
3876 led->l_flags |= BWI_LED_F_ACTLOW;
3877 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3878 }
3879 led->l_mask = (1 << i);
3880
3881 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3882 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3883 led->l_act == BWI_LED_ACT_BLINK) {
3884 led->l_flags |= BWI_LED_F_BLINK;
3885 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3886 led->l_flags |= BWI_LED_F_POLLABLE;
3887 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3888 led->l_flags |= BWI_LED_F_SLOW;
3889
3890 if (sc->sc_blink_led == NULL) {
3891 sc->sc_blink_led = led;
3892 if (led->l_flags & BWI_LED_F_SLOW)
3893 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3894 }
3895 }
3896
3897 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3898 "%dth led, act %d, lowact %d\n", i,
3899 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3900 }
3901 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0);
3902 }
3903
3904 static __inline uint16_t
3905 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3906 {
3907 if (led->l_flags & BWI_LED_F_ACTLOW)
3908 on = !on;
3909 if (on)
3910 val |= led->l_mask;
3911 else
3912 val &= ~led->l_mask;
3913 return val;
3914 }
3915
3916 static void
3917 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3918 {
3919 struct ifnet *ifp = sc->sc_ifp;
3920 struct ieee80211com *ic = ifp->if_l2com;
3921 uint16_t val;
3922 int i;
3923
3924 if (nstate == IEEE80211_S_INIT) {
3925 callout_stop(&sc->sc_led_blink_ch);
3926 sc->sc_led_blinking = 0;
3927 }
3928
3929 if ((ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3930 return;
3931
3932 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3933 for (i = 0; i < BWI_LED_MAX; ++i) {
3934 struct bwi_led *led = &sc->sc_leds[i];
3935 int on;
3936
3937 if (led->l_act == BWI_LED_ACT_UNKN ||
3938 led->l_act == BWI_LED_ACT_NULL)
3939 continue;
3940
3941 if ((led->l_flags & BWI_LED_F_BLINK) &&
3942 nstate != IEEE80211_S_INIT)
3943 continue;
3944
3945 switch (led->l_act) {
3946 case BWI_LED_ACT_ON: /* Always on */
3947 on = 1;
3948 break;
3949 case BWI_LED_ACT_OFF: /* Always off */
3950 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3951 on = 0;
3952 break;
3953 default:
3954 on = 1;
3955 switch (nstate) {
3956 case IEEE80211_S_INIT:
3957 on = 0;
3958 break;
3959 case IEEE80211_S_RUN:
3960 if (led->l_act == BWI_LED_ACT_11G &&
3961 ic->ic_curmode != IEEE80211_MODE_11G)
3962 on = 0;
3963 break;
3964 default:
3965 if (led->l_act == BWI_LED_ACT_ASSOC)
3966 on = 0;
3967 break;
3968 }
3969 break;
3970 }
3971
3972 val = bwi_led_onoff(led, val, on);
3973 }
3974 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3975 }
3976 static void
3977 bwi_led_event(struct bwi_softc *sc, int event)
3978 {
3979 struct bwi_led *led = sc->sc_blink_led;
3980 int rate;
3981
3982 if (event == BWI_LED_EVENT_POLL) {
3983 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3984 return;
3985 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3986 return;
3987 }
3988
3989 sc->sc_led_ticks = ticks;
3990 if (sc->sc_led_blinking)
3991 return;
3992
3993 switch (event) {
3994 case BWI_LED_EVENT_RX:
3995 rate = sc->sc_rx_rate;
3996 break;
3997 case BWI_LED_EVENT_TX:
3998 rate = sc->sc_tx_rate;
3999 break;
4000 case BWI_LED_EVENT_POLL:
4001 rate = 0;
4002 break;
4003 default:
4004 panic("unknown LED event %d\n", event);
4005 break;
4006 }
4007 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
4008 bwi_led_duration[rate].off_dur);
4009 }
4010
4011 static void
4012 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
4013 {
4014 struct bwi_led *led = sc->sc_blink_led;
4015 uint16_t val;
4016
4017 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
4018 val = bwi_led_onoff(led, val, 1);
4019 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
4020
4021 if (led->l_flags & BWI_LED_F_SLOW) {
4022 BWI_LED_SLOWDOWN(on_dur);
4023 BWI_LED_SLOWDOWN(off_dur);
4024 }
4025
4026 sc->sc_led_blinking = 1;
4027 sc->sc_led_blink_offdur = off_dur;
4028
4029 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
4030 }
4031
4032 static void
4033 bwi_led_blink_next(void *xsc)
4034 {
4035 struct bwi_softc *sc = xsc;
4036 uint16_t val;
4037
4038 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
4039 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
4040 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
4041
4042 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
4043 bwi_led_blink_end, sc);
4044 }
4045
4046 static void
4047 bwi_led_blink_end(void *xsc)
4048 {
4049 struct bwi_softc *sc = xsc;
4050 sc->sc_led_blinking = 0;
4051 }
4052
4053 static void
4054 bwi_restart(void *xsc, int pending)
4055 {
4056 struct bwi_softc *sc = xsc;
4057 struct ifnet *ifp = sc->sc_ifp;
4058
4059 if_printf(ifp, "%s begin, help!\n", __func__);
4060 BWI_LOCK(sc);
4061 bwi_init_statechg(xsc, 0);
4062 #if 0
4063 bwi_start_locked(ifp);
4064 #endif
4065 BWI_UNLOCK(sc);
4066 }
Cache object: e279dfd4228e4a0fe003827ae8702d28
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