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sys/dev/bwi/if_bwi.c
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1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD: releng/9.2/sys/dev/bwi/if_bwi.c 248078 2013-03-09 00:39:54Z marius $"); 39 40 #include "opt_inet.h" 41 #include "opt_bwi.h" 42 43 #include <sys/param.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/malloc.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/systm.h> 54 #include <sys/taskqueue.h> 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 #include <net/if_arp.h> 61 #include <net/ethernet.h> 62 #include <net/if_llc.h> 63 64 #include <net80211/ieee80211_var.h> 65 #include <net80211/ieee80211_radiotap.h> 66 #include <net80211/ieee80211_regdomain.h> 67 #include <net80211/ieee80211_phy.h> 68 #include <net80211/ieee80211_ratectl.h> 69 70 #include <net/bpf.h> 71 72 #ifdef INET 73 #include <netinet/in.h> 74 #include <netinet/if_ether.h> 75 #endif 76 77 #include <machine/bus.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 82 #include <dev/bwi/bitops.h> 83 #include <dev/bwi/if_bwireg.h> 84 #include <dev/bwi/if_bwivar.h> 85 #include <dev/bwi/bwimac.h> 86 #include <dev/bwi/bwirf.h> 87 88 struct bwi_clock_freq { 89 u_int clkfreq_min; 90 u_int clkfreq_max; 91 }; 92 93 struct bwi_myaddr_bssid { 94 uint8_t myaddr[IEEE80211_ADDR_LEN]; 95 uint8_t bssid[IEEE80211_ADDR_LEN]; 96 } __packed; 97 98 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 99 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 100 const uint8_t [IEEE80211_ADDR_LEN], 101 const uint8_t [IEEE80211_ADDR_LEN]); 102 static void bwi_vap_delete(struct ieee80211vap *); 103 static void bwi_init(void *); 104 static int bwi_ioctl(struct ifnet *, u_long, caddr_t); 105 static void bwi_start(struct ifnet *); 106 static void bwi_start_locked(struct ifnet *); 107 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 108 const struct ieee80211_bpf_params *); 109 static void bwi_watchdog(void *); 110 static void bwi_scan_start(struct ieee80211com *); 111 static void bwi_set_channel(struct ieee80211com *); 112 static void bwi_scan_end(struct ieee80211com *); 113 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 114 static void bwi_updateslot(struct ifnet *); 115 static int bwi_media_change(struct ifnet *); 116 117 static void bwi_calibrate(void *); 118 119 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 120 static int bwi_calc_noise(struct bwi_softc *); 121 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype); 122 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 123 struct bwi_rxbuf_hdr *, const void *, int, int, int); 124 125 static void bwi_restart(void *, int); 126 static void bwi_init_statechg(struct bwi_softc *, int); 127 static void bwi_stop(struct bwi_softc *, int); 128 static void bwi_stop_locked(struct bwi_softc *, int); 129 static int bwi_newbuf(struct bwi_softc *, int, int); 130 static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 131 struct ieee80211_node *); 132 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 133 struct ieee80211_node *, 134 const struct ieee80211_bpf_params *); 135 136 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 137 bus_addr_t, int, int); 138 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 139 140 static int bwi_init_tx_ring32(struct bwi_softc *, int); 141 static int bwi_init_rx_ring32(struct bwi_softc *); 142 static int bwi_init_txstats32(struct bwi_softc *); 143 static void bwi_free_tx_ring32(struct bwi_softc *, int); 144 static void bwi_free_rx_ring32(struct bwi_softc *); 145 static void bwi_free_txstats32(struct bwi_softc *); 146 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 147 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 148 int, bus_addr_t, int); 149 static int bwi_rxeof32(struct bwi_softc *); 150 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 151 static void bwi_txeof_status32(struct bwi_softc *); 152 153 static int bwi_init_tx_ring64(struct bwi_softc *, int); 154 static int bwi_init_rx_ring64(struct bwi_softc *); 155 static int bwi_init_txstats64(struct bwi_softc *); 156 static void bwi_free_tx_ring64(struct bwi_softc *, int); 157 static void bwi_free_rx_ring64(struct bwi_softc *); 158 static void bwi_free_txstats64(struct bwi_softc *); 159 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 160 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 161 int, bus_addr_t, int); 162 static int bwi_rxeof64(struct bwi_softc *); 163 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 164 static void bwi_txeof_status64(struct bwi_softc *); 165 166 static int bwi_rxeof(struct bwi_softc *, int); 167 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 168 static void bwi_txeof(struct bwi_softc *); 169 static void bwi_txeof_status(struct bwi_softc *, int); 170 static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 171 static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 172 173 static int bwi_dma_alloc(struct bwi_softc *); 174 static void bwi_dma_free(struct bwi_softc *); 175 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 176 struct bwi_ring_data *, bus_size_t, 177 uint32_t); 178 static int bwi_dma_mbuf_create(struct bwi_softc *); 179 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 180 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 181 static void bwi_dma_txstats_free(struct bwi_softc *); 182 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 183 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 184 bus_size_t, int); 185 186 static void bwi_power_on(struct bwi_softc *, int); 187 static int bwi_power_off(struct bwi_softc *, int); 188 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 189 static int bwi_set_clock_delay(struct bwi_softc *); 190 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 191 static int bwi_get_pwron_delay(struct bwi_softc *sc); 192 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 193 const uint8_t *); 194 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 195 196 static void bwi_get_card_flags(struct bwi_softc *); 197 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 198 199 static int bwi_bus_attach(struct bwi_softc *); 200 static int bwi_bbp_attach(struct bwi_softc *); 201 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 202 static void bwi_bbp_power_off(struct bwi_softc *); 203 204 static const char *bwi_regwin_name(const struct bwi_regwin *); 205 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 206 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 207 static int bwi_regwin_select(struct bwi_softc *, int); 208 209 static void bwi_led_attach(struct bwi_softc *); 210 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 211 static void bwi_led_event(struct bwi_softc *, int); 212 static void bwi_led_blink_start(struct bwi_softc *, int, int); 213 static void bwi_led_blink_next(void *); 214 static void bwi_led_blink_end(void *); 215 216 static const struct { 217 uint16_t did_min; 218 uint16_t did_max; 219 uint16_t bbp_id; 220 } bwi_bbpid_map[] = { 221 { 0x4301, 0x4301, 0x4301 }, 222 { 0x4305, 0x4307, 0x4307 }, 223 { 0x4402, 0x4403, 0x4402 }, 224 { 0x4610, 0x4615, 0x4610 }, 225 { 0x4710, 0x4715, 0x4710 }, 226 { 0x4720, 0x4725, 0x4309 } 227 }; 228 229 static const struct { 230 uint16_t bbp_id; 231 int nregwin; 232 } bwi_regwin_count[] = { 233 { 0x4301, 5 }, 234 { 0x4306, 6 }, 235 { 0x4307, 5 }, 236 { 0x4310, 8 }, 237 { 0x4401, 3 }, 238 { 0x4402, 3 }, 239 { 0x4610, 9 }, 240 { 0x4704, 9 }, 241 { 0x4710, 9 }, 242 { 0x5365, 7 } 243 }; 244 245 #define CLKSRC(src) \ 246 [BWI_CLKSRC_ ## src] = { \ 247 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 248 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 249 } 250 251 static const struct { 252 u_int freq_min; 253 u_int freq_max; 254 } bwi_clkfreq[BWI_CLKSRC_MAX] = { 255 CLKSRC(LP_OSC), 256 CLKSRC(CS_OSC), 257 CLKSRC(PCI) 258 }; 259 260 #undef CLKSRC 261 262 #define VENDOR_LED_ACT(vendor) \ 263 { \ 264 .vid = PCI_VENDOR_##vendor, \ 265 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 266 } 267 268 static const struct { 269 #define PCI_VENDOR_COMPAQ 0x0e11 270 #define PCI_VENDOR_LINKSYS 0x1737 271 uint16_t vid; 272 uint8_t led_act[BWI_LED_MAX]; 273 } bwi_vendor_led_act[] = { 274 VENDOR_LED_ACT(COMPAQ), 275 VENDOR_LED_ACT(LINKSYS) 276 #undef PCI_VENDOR_LINKSYS 277 #undef PCI_VENDOR_COMPAQ 278 }; 279 280 static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 281 { BWI_VENDOR_LED_ACT_DEFAULT }; 282 283 #undef VENDOR_LED_ACT 284 285 static const struct { 286 int on_dur; 287 int off_dur; 288 } bwi_led_duration[109] = { 289 [0] = { 400, 100 }, 290 [2] = { 150, 75 }, 291 [4] = { 90, 45 }, 292 [11] = { 66, 34 }, 293 [12] = { 53, 26 }, 294 [18] = { 42, 21 }, 295 [22] = { 35, 17 }, 296 [24] = { 32, 16 }, 297 [36] = { 21, 10 }, 298 [48] = { 16, 8 }, 299 [72] = { 11, 5 }, 300 [96] = { 9, 4 }, 301 [108] = { 7, 3 } 302 }; 303 304 #ifdef BWI_DEBUG 305 #ifdef BWI_DEBUG_VERBOSE 306 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 307 #else 308 static uint32_t bwi_debug; 309 #endif 310 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 311 #endif /* BWI_DEBUG */ 312 313 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 314 315 uint16_t 316 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 317 { 318 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 319 } 320 321 static __inline void 322 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 323 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 324 int tx) 325 { 326 struct bwi_desc32 *desc = &desc_array[desc_idx]; 327 uint32_t ctrl, addr, addr_hi, addr_lo; 328 329 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 330 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 331 332 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 333 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 334 335 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 336 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 337 if (desc_idx == ndesc - 1) 338 ctrl |= BWI_DESC32_C_EOR; 339 if (tx) { 340 /* XXX */ 341 ctrl |= BWI_DESC32_C_FRAME_START | 342 BWI_DESC32_C_FRAME_END | 343 BWI_DESC32_C_INTR; 344 } 345 346 desc->addr = htole32(addr); 347 desc->ctrl = htole32(ctrl); 348 } 349 350 int 351 bwi_attach(struct bwi_softc *sc) 352 { 353 struct ieee80211com *ic; 354 device_t dev = sc->sc_dev; 355 struct ifnet *ifp; 356 struct bwi_mac *mac; 357 struct bwi_phy *phy; 358 int i, error; 359 uint8_t bands; 360 uint8_t macaddr[IEEE80211_ADDR_LEN]; 361 362 BWI_LOCK_INIT(sc); 363 364 /* 365 * Initialize taskq and various tasks 366 */ 367 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 368 taskqueue_thread_enqueue, &sc->sc_tq); 369 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 370 device_get_nameunit(dev)); 371 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 372 373 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 374 375 /* 376 * Initialize sysctl variables 377 */ 378 sc->sc_fw_version = BWI_FW_VERSION3; 379 sc->sc_led_idle = (2350 * hz) / 1000; 380 sc->sc_led_blink = 1; 381 sc->sc_txpwr_calib = 1; 382 #ifdef BWI_DEBUG 383 sc->sc_debug = bwi_debug; 384 #endif 385 bwi_power_on(sc, 1); 386 387 error = bwi_bbp_attach(sc); 388 if (error) 389 goto fail; 390 391 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 392 if (error) 393 goto fail; 394 395 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 396 error = bwi_set_clock_delay(sc); 397 if (error) 398 goto fail; 399 400 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 401 if (error) 402 goto fail; 403 404 error = bwi_get_pwron_delay(sc); 405 if (error) 406 goto fail; 407 } 408 409 error = bwi_bus_attach(sc); 410 if (error) 411 goto fail; 412 413 bwi_get_card_flags(sc); 414 415 bwi_led_attach(sc); 416 417 for (i = 0; i < sc->sc_nmac; ++i) { 418 struct bwi_regwin *old; 419 420 mac = &sc->sc_mac[i]; 421 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 422 if (error) 423 goto fail; 424 425 error = bwi_mac_lateattach(mac); 426 if (error) 427 goto fail; 428 429 error = bwi_regwin_switch(sc, old, NULL); 430 if (error) 431 goto fail; 432 } 433 434 /* 435 * XXX First MAC is known to exist 436 * TODO2 437 */ 438 mac = &sc->sc_mac[0]; 439 phy = &mac->mac_phy; 440 441 bwi_bbp_power_off(sc); 442 443 error = bwi_dma_alloc(sc); 444 if (error) 445 goto fail; 446 447 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 448 if (ifp == NULL) { 449 device_printf(dev, "can not if_alloc()\n"); 450 error = ENOSPC; 451 goto fail; 452 } 453 ic = ifp->if_l2com; 454 455 /* set these up early for if_printf use */ 456 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 457 458 ifp->if_softc = sc; 459 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 460 ifp->if_init = bwi_init; 461 ifp->if_ioctl = bwi_ioctl; 462 ifp->if_start = bwi_start; 463 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 464 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 465 IFQ_SET_READY(&ifp->if_snd); 466 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 467 468 /* 469 * Setup ratesets, phytype, channels and get MAC address 470 */ 471 bands = 0; 472 if (phy->phy_mode == IEEE80211_MODE_11B || 473 phy->phy_mode == IEEE80211_MODE_11G) { 474 setbit(&bands, IEEE80211_MODE_11B); 475 if (phy->phy_mode == IEEE80211_MODE_11B) { 476 ic->ic_phytype = IEEE80211_T_DS; 477 } else { 478 ic->ic_phytype = IEEE80211_T_OFDM; 479 setbit(&bands, IEEE80211_MODE_11G); 480 } 481 482 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, macaddr); 483 if (IEEE80211_IS_MULTICAST(macaddr)) { 484 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, macaddr); 485 if (IEEE80211_IS_MULTICAST(macaddr)) { 486 device_printf(dev, 487 "invalid MAC address: %6D\n", 488 macaddr, ":"); 489 } 490 } 491 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 492 /* TODO:11A */ 493 setbit(&bands, IEEE80211_MODE_11A); 494 error = ENXIO; 495 goto fail; 496 } else { 497 panic("unknown phymode %d\n", phy->phy_mode); 498 } 499 500 /* Get locale */ 501 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 502 BWI_SPROM_CARD_INFO_LOCALE); 503 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 504 /* XXX use locale */ 505 ieee80211_init_channels(ic, NULL, &bands); 506 507 ic->ic_ifp = ifp; 508 ic->ic_caps = IEEE80211_C_STA | 509 IEEE80211_C_SHSLOT | 510 IEEE80211_C_SHPREAMBLE | 511 IEEE80211_C_WPA | 512 IEEE80211_C_BGSCAN | 513 IEEE80211_C_MONITOR; 514 ic->ic_opmode = IEEE80211_M_STA; 515 ieee80211_ifattach(ic, macaddr); 516 517 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 518 519 /* override default methods */ 520 ic->ic_vap_create = bwi_vap_create; 521 ic->ic_vap_delete = bwi_vap_delete; 522 ic->ic_raw_xmit = bwi_raw_xmit; 523 ic->ic_updateslot = bwi_updateslot; 524 ic->ic_scan_start = bwi_scan_start; 525 ic->ic_scan_end = bwi_scan_end; 526 ic->ic_set_channel = bwi_set_channel; 527 528 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 529 530 ieee80211_radiotap_attach(ic, 531 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 532 BWI_TX_RADIOTAP_PRESENT, 533 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 534 BWI_RX_RADIOTAP_PRESENT); 535 536 /* 537 * Add sysctl nodes 538 */ 539 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 540 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 541 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 542 "Firmware version"); 543 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 544 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 545 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 546 "# ticks before LED enters idle state"); 547 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 548 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 549 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 550 "Allow LED to blink"); 551 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 552 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 553 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 554 "Enable software TX power calibration"); 555 #ifdef BWI_DEBUG 556 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 557 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 558 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 559 #endif 560 if (bootverbose) 561 ieee80211_announce(ic); 562 563 return (0); 564 fail: 565 BWI_LOCK_DESTROY(sc); 566 return (error); 567 } 568 569 int 570 bwi_detach(struct bwi_softc *sc) 571 { 572 struct ifnet *ifp = sc->sc_ifp; 573 struct ieee80211com *ic = ifp->if_l2com; 574 int i; 575 576 bwi_stop(sc, 1); 577 callout_drain(&sc->sc_led_blink_ch); 578 callout_drain(&sc->sc_calib_ch); 579 callout_drain(&sc->sc_watchdog_timer); 580 ieee80211_ifdetach(ic); 581 582 for (i = 0; i < sc->sc_nmac; ++i) 583 bwi_mac_detach(&sc->sc_mac[i]); 584 bwi_dma_free(sc); 585 if_free(ifp); 586 taskqueue_free(sc->sc_tq); 587 588 BWI_LOCK_DESTROY(sc); 589 590 return (0); 591 } 592 593 static struct ieee80211vap * 594 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 595 enum ieee80211_opmode opmode, int flags, 596 const uint8_t bssid[IEEE80211_ADDR_LEN], 597 const uint8_t mac[IEEE80211_ADDR_LEN]) 598 { 599 struct bwi_vap *bvp; 600 struct ieee80211vap *vap; 601 602 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 603 return NULL; 604 bvp = (struct bwi_vap *) malloc(sizeof(struct bwi_vap), 605 M_80211_VAP, M_WAITOK | M_ZERO); 606 if (bvp == NULL) 607 return NULL; 608 vap = &bvp->bv_vap; 609 /* enable s/w bmiss handling for sta mode */ 610 ieee80211_vap_setup(ic, vap, name, unit, opmode, 611 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 612 613 /* override default methods */ 614 bvp->bv_newstate = vap->iv_newstate; 615 vap->iv_newstate = bwi_newstate; 616 #if 0 617 vap->iv_update_beacon = bwi_beacon_update; 618 #endif 619 ieee80211_ratectl_init(vap); 620 621 /* complete setup */ 622 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status); 623 ic->ic_opmode = opmode; 624 return vap; 625 } 626 627 static void 628 bwi_vap_delete(struct ieee80211vap *vap) 629 { 630 struct bwi_vap *bvp = BWI_VAP(vap); 631 632 ieee80211_ratectl_deinit(vap); 633 ieee80211_vap_detach(vap); 634 free(bvp, M_80211_VAP); 635 } 636 637 void 638 bwi_suspend(struct bwi_softc *sc) 639 { 640 bwi_stop(sc, 1); 641 } 642 643 void 644 bwi_resume(struct bwi_softc *sc) 645 { 646 struct ifnet *ifp = sc->sc_ifp; 647 648 if (ifp->if_flags & IFF_UP) 649 bwi_init(sc); 650 } 651 652 int 653 bwi_shutdown(struct bwi_softc *sc) 654 { 655 bwi_stop(sc, 1); 656 return 0; 657 } 658 659 static void 660 bwi_power_on(struct bwi_softc *sc, int with_pll) 661 { 662 uint32_t gpio_in, gpio_out, gpio_en; 663 uint16_t status; 664 665 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 666 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 667 goto back; 668 669 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 670 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 671 672 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 673 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 674 if (with_pll) { 675 /* Turn off PLL first */ 676 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 677 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 678 } 679 680 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 681 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 682 DELAY(1000); 683 684 if (with_pll) { 685 /* Turn on PLL */ 686 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 687 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 688 DELAY(5000); 689 } 690 691 back: 692 /* Clear "Signaled Target Abort" */ 693 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 694 status &= ~PCIM_STATUS_STABORT; 695 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 696 } 697 698 static int 699 bwi_power_off(struct bwi_softc *sc, int with_pll) 700 { 701 uint32_t gpio_out, gpio_en; 702 703 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 704 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 705 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 706 707 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 708 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 709 if (with_pll) { 710 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 711 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 712 } 713 714 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 715 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 716 return 0; 717 } 718 719 int 720 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 721 struct bwi_regwin **old_rw) 722 { 723 int error; 724 725 if (old_rw != NULL) 726 *old_rw = NULL; 727 728 if (!BWI_REGWIN_EXIST(rw)) 729 return EINVAL; 730 731 if (sc->sc_cur_regwin != rw) { 732 error = bwi_regwin_select(sc, rw->rw_id); 733 if (error) { 734 device_printf(sc->sc_dev, "can't select regwin %d\n", 735 rw->rw_id); 736 return error; 737 } 738 } 739 740 if (old_rw != NULL) 741 *old_rw = sc->sc_cur_regwin; 742 sc->sc_cur_regwin = rw; 743 return 0; 744 } 745 746 static int 747 bwi_regwin_select(struct bwi_softc *sc, int id) 748 { 749 uint32_t win = BWI_PCIM_REGWIN(id); 750 int i; 751 752 #define RETRY_MAX 50 753 for (i = 0; i < RETRY_MAX; ++i) { 754 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 755 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 756 return 0; 757 DELAY(10); 758 } 759 #undef RETRY_MAX 760 761 return ENXIO; 762 } 763 764 static void 765 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 766 { 767 uint32_t val; 768 769 val = CSR_READ_4(sc, BWI_ID_HI); 770 *type = BWI_ID_HI_REGWIN_TYPE(val); 771 *rev = BWI_ID_HI_REGWIN_REV(val); 772 773 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 774 "vendor 0x%04x\n", *type, *rev, 775 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 776 } 777 778 static int 779 bwi_bbp_attach(struct bwi_softc *sc) 780 { 781 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 782 uint16_t bbp_id, rw_type; 783 uint8_t rw_rev; 784 uint32_t info; 785 int error, nregwin, i; 786 787 /* 788 * Get 0th regwin information 789 * NOTE: 0th regwin should exist 790 */ 791 error = bwi_regwin_select(sc, 0); 792 if (error) { 793 device_printf(sc->sc_dev, "can't select regwin 0\n"); 794 return error; 795 } 796 bwi_regwin_info(sc, &rw_type, &rw_rev); 797 798 /* 799 * Find out BBP id 800 */ 801 bbp_id = 0; 802 info = 0; 803 if (rw_type == BWI_REGWIN_T_COM) { 804 info = CSR_READ_4(sc, BWI_INFO); 805 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 806 807 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 808 809 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 810 } else { 811 for (i = 0; i < N(bwi_bbpid_map); ++i) { 812 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 813 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 814 bbp_id = bwi_bbpid_map[i].bbp_id; 815 break; 816 } 817 } 818 if (bbp_id == 0) { 819 device_printf(sc->sc_dev, "no BBP id for device id " 820 "0x%04x\n", sc->sc_pci_did); 821 return ENXIO; 822 } 823 824 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 825 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 826 } 827 828 /* 829 * Find out number of regwins 830 */ 831 nregwin = 0; 832 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 833 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 834 } else { 835 for (i = 0; i < N(bwi_regwin_count); ++i) { 836 if (bwi_regwin_count[i].bbp_id == bbp_id) { 837 nregwin = bwi_regwin_count[i].nregwin; 838 break; 839 } 840 } 841 if (nregwin == 0) { 842 device_printf(sc->sc_dev, "no number of win for " 843 "BBP id 0x%04x\n", bbp_id); 844 return ENXIO; 845 } 846 } 847 848 /* Record BBP id/rev for later using */ 849 sc->sc_bbp_id = bbp_id; 850 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 851 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 852 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 853 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 854 855 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 856 nregwin, sc->sc_cap); 857 858 /* 859 * Create rest of the regwins 860 */ 861 862 /* Don't re-create common regwin, if it is already created */ 863 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 864 865 for (; i < nregwin; ++i) { 866 /* 867 * Get regwin information 868 */ 869 error = bwi_regwin_select(sc, i); 870 if (error) { 871 device_printf(sc->sc_dev, 872 "can't select regwin %d\n", i); 873 return error; 874 } 875 bwi_regwin_info(sc, &rw_type, &rw_rev); 876 877 /* 878 * Try attach: 879 * 1) Bus (PCI/PCIE) regwin 880 * 2) MAC regwin 881 * Ignore rest types of regwin 882 */ 883 if (rw_type == BWI_REGWIN_T_BUSPCI || 884 rw_type == BWI_REGWIN_T_BUSPCIE) { 885 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 886 device_printf(sc->sc_dev, 887 "bus regwin already exists\n"); 888 } else { 889 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 890 rw_type, rw_rev); 891 } 892 } else if (rw_type == BWI_REGWIN_T_MAC) { 893 /* XXX ignore return value */ 894 bwi_mac_attach(sc, i, rw_rev); 895 } 896 } 897 898 /* At least one MAC shold exist */ 899 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 900 device_printf(sc->sc_dev, "no MAC was found\n"); 901 return ENXIO; 902 } 903 KASSERT(sc->sc_nmac > 0, ("no mac's")); 904 905 /* Bus regwin must exist */ 906 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 907 device_printf(sc->sc_dev, "no bus regwin was found\n"); 908 return ENXIO; 909 } 910 911 /* Start with first MAC */ 912 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 913 if (error) 914 return error; 915 916 return 0; 917 #undef N 918 } 919 920 int 921 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 922 { 923 struct bwi_regwin *old, *bus; 924 uint32_t val; 925 int error; 926 927 bus = &sc->sc_bus_regwin; 928 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 929 930 /* 931 * Tell bus to generate requested interrupts 932 */ 933 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 934 /* 935 * NOTE: Read BWI_FLAGS from MAC regwin 936 */ 937 val = CSR_READ_4(sc, BWI_FLAGS); 938 939 error = bwi_regwin_switch(sc, bus, &old); 940 if (error) 941 return error; 942 943 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 944 } else { 945 uint32_t mac_mask; 946 947 mac_mask = 1 << mac->mac_id; 948 949 error = bwi_regwin_switch(sc, bus, &old); 950 if (error) 951 return error; 952 953 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 954 val |= mac_mask << 8; 955 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 956 } 957 958 if (sc->sc_flags & BWI_F_BUS_INITED) 959 goto back; 960 961 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 962 /* 963 * Enable prefetch and burst 964 */ 965 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 966 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 967 968 if (bus->rw_rev < 5) { 969 struct bwi_regwin *com = &sc->sc_com_regwin; 970 971 /* 972 * Configure timeouts for bus operation 973 */ 974 975 /* 976 * Set service timeout and request timeout 977 */ 978 CSR_SETBITS_4(sc, BWI_CONF_LO, 979 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 980 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 981 982 /* 983 * If there is common regwin, we switch to that regwin 984 * and switch back to bus regwin once we have done. 985 */ 986 if (BWI_REGWIN_EXIST(com)) { 987 error = bwi_regwin_switch(sc, com, NULL); 988 if (error) 989 return error; 990 } 991 992 /* Let bus know what we have changed */ 993 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 994 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 995 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 996 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 997 998 if (BWI_REGWIN_EXIST(com)) { 999 error = bwi_regwin_switch(sc, bus, NULL); 1000 if (error) 1001 return error; 1002 } 1003 } else if (bus->rw_rev >= 11) { 1004 /* 1005 * Enable memory read multiple 1006 */ 1007 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 1008 } 1009 } else { 1010 /* TODO:PCIE */ 1011 } 1012 1013 sc->sc_flags |= BWI_F_BUS_INITED; 1014 back: 1015 return bwi_regwin_switch(sc, old, NULL); 1016 } 1017 1018 static void 1019 bwi_get_card_flags(struct bwi_softc *sc) 1020 { 1021 #define PCI_VENDOR_APPLE 0x106b 1022 #define PCI_VENDOR_DELL 0x1028 1023 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1024 if (sc->sc_card_flags == 0xffff) 1025 sc->sc_card_flags = 0; 1026 1027 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1028 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1029 sc->sc_pci_revid == 0x74) 1030 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1031 1032 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1033 sc->sc_pci_subdid == 0x4e && /* XXX */ 1034 sc->sc_pci_revid > 0x40) 1035 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1036 1037 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1038 #undef PCI_VENDOR_DELL 1039 #undef PCI_VENDOR_APPLE 1040 } 1041 1042 static void 1043 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1044 { 1045 int i; 1046 1047 for (i = 0; i < 3; ++i) { 1048 *((uint16_t *)eaddr + i) = 1049 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1050 } 1051 } 1052 1053 static void 1054 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1055 { 1056 struct bwi_regwin *com; 1057 uint32_t val; 1058 u_int div; 1059 int src; 1060 1061 bzero(freq, sizeof(*freq)); 1062 com = &sc->sc_com_regwin; 1063 1064 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1065 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1066 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1067 1068 /* 1069 * Calculate clock frequency 1070 */ 1071 src = -1; 1072 div = 0; 1073 if (com->rw_rev < 6) { 1074 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1075 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1076 src = BWI_CLKSRC_PCI; 1077 div = 64; 1078 } else { 1079 src = BWI_CLKSRC_CS_OSC; 1080 div = 32; 1081 } 1082 } else if (com->rw_rev < 10) { 1083 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1084 1085 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1086 if (src == BWI_CLKSRC_LP_OSC) { 1087 div = 1; 1088 } else { 1089 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1090 1091 /* Unknown source */ 1092 if (src >= BWI_CLKSRC_MAX) 1093 src = BWI_CLKSRC_CS_OSC; 1094 } 1095 } else { 1096 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1097 1098 src = BWI_CLKSRC_CS_OSC; 1099 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1100 } 1101 1102 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1103 KASSERT(div != 0, ("div zero")); 1104 1105 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1106 src == BWI_CLKSRC_PCI ? "PCI" : 1107 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1108 1109 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1110 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1111 1112 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1113 freq->clkfreq_min, freq->clkfreq_max); 1114 } 1115 1116 static int 1117 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1118 { 1119 struct bwi_regwin *old, *com; 1120 uint32_t clk_ctrl, clk_src; 1121 int error, pwr_off = 0; 1122 1123 com = &sc->sc_com_regwin; 1124 if (!BWI_REGWIN_EXIST(com)) 1125 return 0; 1126 1127 if (com->rw_rev >= 10 || com->rw_rev < 6) 1128 return 0; 1129 1130 /* 1131 * For common regwin whose rev is [6, 10), the chip 1132 * must be capable to change clock mode. 1133 */ 1134 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1135 return 0; 1136 1137 error = bwi_regwin_switch(sc, com, &old); 1138 if (error) 1139 return error; 1140 1141 if (clk_mode == BWI_CLOCK_MODE_FAST) 1142 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1143 1144 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1145 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1146 1147 switch (clk_mode) { 1148 case BWI_CLOCK_MODE_FAST: 1149 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1150 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1151 break; 1152 case BWI_CLOCK_MODE_SLOW: 1153 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1154 break; 1155 case BWI_CLOCK_MODE_DYN: 1156 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1157 BWI_CLOCK_CTRL_IGNPLL | 1158 BWI_CLOCK_CTRL_NODYN); 1159 if (clk_src != BWI_CLKSRC_CS_OSC) { 1160 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1161 pwr_off = 1; 1162 } 1163 break; 1164 } 1165 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1166 1167 if (pwr_off) 1168 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1169 1170 return bwi_regwin_switch(sc, old, NULL); 1171 } 1172 1173 static int 1174 bwi_set_clock_delay(struct bwi_softc *sc) 1175 { 1176 struct bwi_regwin *old, *com; 1177 int error; 1178 1179 com = &sc->sc_com_regwin; 1180 if (!BWI_REGWIN_EXIST(com)) 1181 return 0; 1182 1183 error = bwi_regwin_switch(sc, com, &old); 1184 if (error) 1185 return error; 1186 1187 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1188 if (sc->sc_bbp_rev == 0) 1189 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1190 else if (sc->sc_bbp_rev == 1) 1191 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1192 } 1193 1194 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1195 if (com->rw_rev >= 10) { 1196 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1197 } else { 1198 struct bwi_clock_freq freq; 1199 1200 bwi_get_clock_freq(sc, &freq); 1201 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1202 howmany(freq.clkfreq_max * 150, 1000000)); 1203 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1204 howmany(freq.clkfreq_max * 15, 1000000)); 1205 } 1206 } 1207 1208 return bwi_regwin_switch(sc, old, NULL); 1209 } 1210 1211 static void 1212 bwi_init(void *xsc) 1213 { 1214 struct bwi_softc *sc = xsc; 1215 struct ifnet *ifp = sc->sc_ifp; 1216 struct ieee80211com *ic = ifp->if_l2com; 1217 1218 BWI_LOCK(sc); 1219 bwi_init_statechg(sc, 1); 1220 BWI_UNLOCK(sc); 1221 1222 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1223 ieee80211_start_all(ic); /* start all vap's */ 1224 } 1225 1226 static void 1227 bwi_init_statechg(struct bwi_softc *sc, int statechg) 1228 { 1229 struct ifnet *ifp = sc->sc_ifp; 1230 struct bwi_mac *mac; 1231 int error; 1232 1233 bwi_stop_locked(sc, statechg); 1234 1235 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1236 1237 /* TODO: 2 MAC */ 1238 1239 mac = &sc->sc_mac[0]; 1240 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1241 if (error) { 1242 if_printf(ifp, "%s: error %d on regwin switch\n", 1243 __func__, error); 1244 goto bad; 1245 } 1246 error = bwi_mac_init(mac); 1247 if (error) { 1248 if_printf(ifp, "%s: error %d on MAC init\n", __func__, error); 1249 goto bad; 1250 } 1251 1252 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1253 1254 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1255 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, IF_LLADDR(ifp)); 1256 1257 bwi_mac_reset_hwkeys(mac); 1258 1259 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1260 int i; 1261 1262 #define NRETRY 1000 1263 /* 1264 * Drain any possible pending TX status 1265 */ 1266 for (i = 0; i < NRETRY; ++i) { 1267 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1268 BWI_TXSTATUS0_VALID) == 0) 1269 break; 1270 CSR_READ_4(sc, BWI_TXSTATUS1); 1271 } 1272 if (i == NRETRY) 1273 if_printf(ifp, "%s: can't drain TX status\n", __func__); 1274 #undef NRETRY 1275 } 1276 1277 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1278 bwi_mac_updateslot(mac, 1); 1279 1280 /* Start MAC */ 1281 error = bwi_mac_start(mac); 1282 if (error) { 1283 if_printf(ifp, "%s: error %d starting MAC\n", __func__, error); 1284 goto bad; 1285 } 1286 1287 /* Clear stop flag before enabling interrupt */ 1288 sc->sc_flags &= ~BWI_F_STOP; 1289 1290 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1291 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1292 1293 /* Enable intrs */ 1294 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1295 return; 1296 bad: 1297 bwi_stop_locked(sc, 1); 1298 } 1299 1300 static int 1301 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1302 { 1303 #define IS_RUNNING(ifp) \ 1304 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1305 struct bwi_softc *sc = ifp->if_softc; 1306 struct ieee80211com *ic = ifp->if_l2com; 1307 struct ifreq *ifr = (struct ifreq *) data; 1308 int error = 0, startall = 0; 1309 1310 switch (cmd) { 1311 case SIOCSIFFLAGS: 1312 BWI_LOCK(sc); 1313 if (IS_RUNNING(ifp)) { 1314 struct bwi_mac *mac; 1315 int promisc = -1; 1316 1317 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1318 ("current regwin type %d", 1319 sc->sc_cur_regwin->rw_type)); 1320 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1321 1322 if ((ifp->if_flags & IFF_PROMISC) && 1323 (sc->sc_flags & BWI_F_PROMISC) == 0) { 1324 promisc = 1; 1325 sc->sc_flags |= BWI_F_PROMISC; 1326 } else if ((ifp->if_flags & IFF_PROMISC) == 0 && 1327 (sc->sc_flags & BWI_F_PROMISC)) { 1328 promisc = 0; 1329 sc->sc_flags &= ~BWI_F_PROMISC; 1330 } 1331 1332 if (promisc >= 0) 1333 bwi_mac_set_promisc(mac, promisc); 1334 } 1335 1336 if (ifp->if_flags & IFF_UP) { 1337 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1338 bwi_init_statechg(sc, 1); 1339 startall = 1; 1340 } 1341 } else { 1342 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1343 bwi_stop_locked(sc, 1); 1344 } 1345 BWI_UNLOCK(sc); 1346 if (startall) 1347 ieee80211_start_all(ic); 1348 break; 1349 case SIOCGIFMEDIA: 1350 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1351 break; 1352 case SIOCGIFADDR: 1353 error = ether_ioctl(ifp, cmd, data); 1354 break; 1355 default: 1356 error = EINVAL; 1357 break; 1358 } 1359 return error; 1360 #undef IS_RUNNING 1361 } 1362 1363 static void 1364 bwi_start(struct ifnet *ifp) 1365 { 1366 struct bwi_softc *sc = ifp->if_softc; 1367 1368 BWI_LOCK(sc); 1369 bwi_start_locked(ifp); 1370 BWI_UNLOCK(sc); 1371 } 1372 1373 static void 1374 bwi_start_locked(struct ifnet *ifp) 1375 { 1376 struct bwi_softc *sc = ifp->if_softc; 1377 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1378 struct ieee80211_frame *wh; 1379 struct ieee80211_node *ni; 1380 struct ieee80211_key *k; 1381 struct mbuf *m; 1382 int trans, idx; 1383 1384 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1385 return; 1386 1387 trans = 0; 1388 idx = tbd->tbd_idx; 1389 1390 while (tbd->tbd_buf[idx].tb_mbuf == NULL) { 1391 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1392 if (m == NULL) 1393 break; 1394 1395 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1396 wh = mtod(m, struct ieee80211_frame *); 1397 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1398 k = ieee80211_crypto_encap(ni, m); 1399 if (k == NULL) { 1400 ieee80211_free_node(ni); 1401 m_freem(m); 1402 ifp->if_oerrors++; 1403 continue; 1404 } 1405 } 1406 wh = NULL; /* Catch any invalid use */ 1407 1408 if (bwi_encap(sc, idx, m, ni) != 0) { 1409 /* 'm' is freed in bwi_encap() if we reach here */ 1410 if (ni != NULL) 1411 ieee80211_free_node(ni); 1412 ifp->if_oerrors++; 1413 continue; 1414 } 1415 1416 trans = 1; 1417 tbd->tbd_used++; 1418 idx = (idx + 1) % BWI_TX_NDESC; 1419 1420 ifp->if_opackets++; 1421 1422 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) { 1423 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1424 break; 1425 } 1426 } 1427 tbd->tbd_idx = idx; 1428 1429 if (trans) 1430 sc->sc_tx_timer = 5; 1431 } 1432 1433 static int 1434 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1435 const struct ieee80211_bpf_params *params) 1436 { 1437 struct ieee80211com *ic = ni->ni_ic; 1438 struct ifnet *ifp = ic->ic_ifp; 1439 struct bwi_softc *sc = ifp->if_softc; 1440 /* XXX wme? */ 1441 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1442 int idx, error; 1443 1444 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1445 ieee80211_free_node(ni); 1446 m_freem(m); 1447 return ENETDOWN; 1448 } 1449 1450 BWI_LOCK(sc); 1451 idx = tbd->tbd_idx; 1452 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1453 if (params == NULL) { 1454 /* 1455 * Legacy path; interpret frame contents to decide 1456 * precisely how to send the frame. 1457 */ 1458 error = bwi_encap(sc, idx, m, ni); 1459 } else { 1460 /* 1461 * Caller supplied explicit parameters to use in 1462 * sending the frame. 1463 */ 1464 error = bwi_encap_raw(sc, idx, m, ni, params); 1465 } 1466 if (error == 0) { 1467 ifp->if_opackets++; 1468 if (++tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) 1469 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1470 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1471 sc->sc_tx_timer = 5; 1472 } else { 1473 /* NB: m is reclaimed on encap failure */ 1474 ieee80211_free_node(ni); 1475 ifp->if_oerrors++; 1476 } 1477 BWI_UNLOCK(sc); 1478 return error; 1479 } 1480 1481 static void 1482 bwi_watchdog(void *arg) 1483 { 1484 struct bwi_softc *sc; 1485 struct ifnet *ifp; 1486 1487 sc = arg; 1488 ifp = sc->sc_ifp; 1489 BWI_ASSERT_LOCKED(sc); 1490 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1491 if_printf(ifp, "watchdog timeout\n"); 1492 ifp->if_oerrors++; 1493 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1494 } 1495 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1496 } 1497 1498 static void 1499 bwi_stop(struct bwi_softc *sc, int statechg) 1500 { 1501 BWI_LOCK(sc); 1502 bwi_stop_locked(sc, statechg); 1503 BWI_UNLOCK(sc); 1504 } 1505 1506 static void 1507 bwi_stop_locked(struct bwi_softc *sc, int statechg) 1508 { 1509 struct ifnet *ifp = sc->sc_ifp; 1510 struct bwi_mac *mac; 1511 int i, error, pwr_off = 0; 1512 1513 BWI_ASSERT_LOCKED(sc); 1514 1515 callout_stop(&sc->sc_calib_ch); 1516 callout_stop(&sc->sc_led_blink_ch); 1517 sc->sc_led_blinking = 0; 1518 sc->sc_flags |= BWI_F_STOP; 1519 1520 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1521 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1522 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1523 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1524 1525 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1526 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1527 bwi_mac_stop(mac); 1528 } 1529 1530 for (i = 0; i < sc->sc_nmac; ++i) { 1531 struct bwi_regwin *old_rw; 1532 1533 mac = &sc->sc_mac[i]; 1534 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1535 continue; 1536 1537 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1538 if (error) 1539 continue; 1540 1541 bwi_mac_shutdown(mac); 1542 pwr_off = 1; 1543 1544 bwi_regwin_switch(sc, old_rw, NULL); 1545 } 1546 1547 if (pwr_off) 1548 bwi_bbp_power_off(sc); 1549 1550 sc->sc_tx_timer = 0; 1551 callout_stop(&sc->sc_watchdog_timer); 1552 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1553 } 1554 1555 void 1556 bwi_intr(void *xsc) 1557 { 1558 struct bwi_softc *sc = xsc; 1559 struct ifnet *ifp = sc->sc_ifp; 1560 struct bwi_mac *mac; 1561 uint32_t intr_status; 1562 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1563 int i, txrx_error, tx = 0, rx_data = -1; 1564 1565 BWI_LOCK(sc); 1566 1567 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1568 (sc->sc_flags & BWI_F_STOP)) { 1569 BWI_UNLOCK(sc); 1570 return; 1571 } 1572 /* 1573 * Get interrupt status 1574 */ 1575 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1576 if (intr_status == 0xffffffff) { /* Not for us */ 1577 BWI_UNLOCK(sc); 1578 return; 1579 } 1580 1581 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1582 1583 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1584 if (intr_status == 0) { /* Nothing is interesting */ 1585 BWI_UNLOCK(sc); 1586 return; 1587 } 1588 1589 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1590 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1591 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1592 1593 txrx_error = 0; 1594 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1595 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1596 uint32_t mask; 1597 1598 if (BWI_TXRX_IS_RX(i)) 1599 mask = BWI_TXRX_RX_INTRS; 1600 else 1601 mask = BWI_TXRX_TX_INTRS; 1602 1603 txrx_intr_status[i] = 1604 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1605 1606 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1607 i, txrx_intr_status[i]); 1608 1609 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1610 if_printf(ifp, 1611 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1612 __func__, i, txrx_intr_status[i]); 1613 txrx_error = 1; 1614 } 1615 } 1616 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1617 1618 /* 1619 * Acknowledge interrupt 1620 */ 1621 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1622 1623 for (i = 0; i < BWI_TXRX_NRING; ++i) 1624 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1625 1626 /* Disable all interrupts */ 1627 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1628 1629 /* 1630 * http://bcm-specs.sipsolutions.net/Interrupts 1631 * Says for this bit (0x800): 1632 * "Fatal Error 1633 * 1634 * We got this one while testing things when by accident the 1635 * template ram wasn't set to big endian when it should have 1636 * been after writing the initial values. It keeps on being 1637 * triggered, the only way to stop it seems to shut down the 1638 * chip." 1639 * 1640 * Suggesting that we should never get it and if we do we're not 1641 * feeding TX packets into the MAC correctly if we do... Apparently, 1642 * it is valid only on mac version 5 and higher, but I couldn't 1643 * find a reference for that... Since I see them from time to time 1644 * on my card, this suggests an error in the tx path still... 1645 */ 1646 if (intr_status & BWI_INTR_PHY_TXERR) { 1647 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1648 if_printf(ifp, "%s: intr PHY TX error\n", __func__); 1649 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1650 BWI_UNLOCK(sc); 1651 return; 1652 } 1653 } 1654 1655 if (txrx_error) { 1656 /* TODO: reset device */ 1657 } 1658 1659 if (intr_status & BWI_INTR_TBTT) 1660 bwi_mac_config_ps(mac); 1661 1662 if (intr_status & BWI_INTR_EO_ATIM) 1663 if_printf(ifp, "EO_ATIM\n"); 1664 1665 if (intr_status & BWI_INTR_PMQ) { 1666 for (;;) { 1667 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1668 break; 1669 } 1670 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1671 } 1672 1673 if (intr_status & BWI_INTR_NOISE) 1674 if_printf(ifp, "intr noise\n"); 1675 1676 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1677 rx_data = sc->sc_rxeof(sc); 1678 if (sc->sc_flags & BWI_F_STOP) { 1679 BWI_UNLOCK(sc); 1680 return; 1681 } 1682 } 1683 1684 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1685 sc->sc_txeof_status(sc); 1686 tx = 1; 1687 } 1688 1689 if (intr_status & BWI_INTR_TX_DONE) { 1690 bwi_txeof(sc); 1691 tx = 1; 1692 } 1693 1694 /* Re-enable interrupts */ 1695 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1696 1697 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1698 int evt = BWI_LED_EVENT_NONE; 1699 1700 if (tx && rx_data > 0) { 1701 if (sc->sc_rx_rate > sc->sc_tx_rate) 1702 evt = BWI_LED_EVENT_RX; 1703 else 1704 evt = BWI_LED_EVENT_TX; 1705 } else if (tx) { 1706 evt = BWI_LED_EVENT_TX; 1707 } else if (rx_data > 0) { 1708 evt = BWI_LED_EVENT_RX; 1709 } else if (rx_data == 0) { 1710 evt = BWI_LED_EVENT_POLL; 1711 } 1712 1713 if (evt != BWI_LED_EVENT_NONE) 1714 bwi_led_event(sc, evt); 1715 } 1716 1717 BWI_UNLOCK(sc); 1718 } 1719 1720 static void 1721 bwi_scan_start(struct ieee80211com *ic) 1722 { 1723 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1724 1725 BWI_LOCK(sc); 1726 /* Enable MAC beacon promiscuity */ 1727 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1728 BWI_UNLOCK(sc); 1729 } 1730 1731 static void 1732 bwi_set_channel(struct ieee80211com *ic) 1733 { 1734 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1735 struct ieee80211_channel *c = ic->ic_curchan; 1736 struct bwi_mac *mac; 1737 1738 BWI_LOCK(sc); 1739 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1740 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1741 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1742 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1743 1744 sc->sc_rates = ieee80211_get_ratetable(c); 1745 1746 /* 1747 * Setup radio tap channel freq and flags 1748 */ 1749 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1750 htole16(c->ic_freq); 1751 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1752 htole16(c->ic_flags & 0xffff); 1753 1754 BWI_UNLOCK(sc); 1755 } 1756 1757 static void 1758 bwi_scan_end(struct ieee80211com *ic) 1759 { 1760 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1761 1762 BWI_LOCK(sc); 1763 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1764 BWI_UNLOCK(sc); 1765 } 1766 1767 static int 1768 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1769 { 1770 struct bwi_vap *bvp = BWI_VAP(vap); 1771 struct ieee80211com *ic= vap->iv_ic; 1772 struct ifnet *ifp = ic->ic_ifp; 1773 enum ieee80211_state ostate = vap->iv_state; 1774 struct bwi_softc *sc = ifp->if_softc; 1775 struct bwi_mac *mac; 1776 int error; 1777 1778 BWI_LOCK(sc); 1779 1780 callout_stop(&sc->sc_calib_ch); 1781 1782 if (nstate == IEEE80211_S_INIT) 1783 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1784 1785 bwi_led_newstate(sc, nstate); 1786 1787 error = bvp->bv_newstate(vap, nstate, arg); 1788 if (error != 0) 1789 goto back; 1790 1791 /* 1792 * Clear the BSSID when we stop a STA 1793 */ 1794 if (vap->iv_opmode == IEEE80211_M_STA) { 1795 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1796 /* 1797 * Clear out the BSSID. If we reassociate to 1798 * the same AP, this will reinialize things 1799 * correctly... 1800 */ 1801 if (ic->ic_opmode == IEEE80211_M_STA && 1802 !(sc->sc_flags & BWI_F_STOP)) 1803 bwi_set_bssid(sc, bwi_zero_addr); 1804 } 1805 } 1806 1807 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1808 /* Nothing to do */ 1809 } else if (nstate == IEEE80211_S_RUN) { 1810 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1811 1812 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1813 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1814 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1815 1816 /* Initial TX power calibration */ 1817 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1818 #ifdef notyet 1819 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1820 #else 1821 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1822 #endif 1823 1824 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1825 } 1826 back: 1827 BWI_UNLOCK(sc); 1828 1829 return error; 1830 } 1831 1832 static int 1833 bwi_media_change(struct ifnet *ifp) 1834 { 1835 int error = ieee80211_media_change(ifp); 1836 /* NB: only the fixed rate can change and that doesn't need a reset */ 1837 return (error == ENETRESET ? 0 : error); 1838 } 1839 1840 static int 1841 bwi_dma_alloc(struct bwi_softc *sc) 1842 { 1843 int error, i, has_txstats; 1844 bus_addr_t lowaddr = 0; 1845 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1846 uint32_t txrx_ctrl_step = 0; 1847 1848 has_txstats = 0; 1849 for (i = 0; i < sc->sc_nmac; ++i) { 1850 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1851 has_txstats = 1; 1852 break; 1853 } 1854 } 1855 1856 switch (sc->sc_bus_space) { 1857 case BWI_BUS_SPACE_30BIT: 1858 case BWI_BUS_SPACE_32BIT: 1859 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1860 lowaddr = BWI_BUS_SPACE_MAXADDR; 1861 else 1862 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1863 desc_sz = sizeof(struct bwi_desc32); 1864 txrx_ctrl_step = 0x20; 1865 1866 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1867 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1868 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1869 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1870 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1871 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1872 sc->sc_rxeof = bwi_rxeof32; 1873 sc->sc_start_tx = bwi_start_tx32; 1874 if (has_txstats) { 1875 sc->sc_init_txstats = bwi_init_txstats32; 1876 sc->sc_free_txstats = bwi_free_txstats32; 1877 sc->sc_txeof_status = bwi_txeof_status32; 1878 } 1879 break; 1880 1881 case BWI_BUS_SPACE_64BIT: 1882 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1883 desc_sz = sizeof(struct bwi_desc64); 1884 txrx_ctrl_step = 0x40; 1885 1886 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1887 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1888 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1889 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1890 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1891 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1892 sc->sc_rxeof = bwi_rxeof64; 1893 sc->sc_start_tx = bwi_start_tx64; 1894 if (has_txstats) { 1895 sc->sc_init_txstats = bwi_init_txstats64; 1896 sc->sc_free_txstats = bwi_free_txstats64; 1897 sc->sc_txeof_status = bwi_txeof_status64; 1898 } 1899 break; 1900 } 1901 1902 KASSERT(lowaddr != 0, ("lowaddr zero")); 1903 KASSERT(desc_sz != 0, ("desc_sz zero")); 1904 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1905 1906 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1907 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1908 1909 /* 1910 * Create top level DMA tag 1911 */ 1912 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1913 BWI_ALIGN, 0, /* alignment, bounds */ 1914 lowaddr, /* lowaddr */ 1915 BUS_SPACE_MAXADDR, /* highaddr */ 1916 NULL, NULL, /* filter, filterarg */ 1917 MAXBSIZE, /* maxsize */ 1918 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1919 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1920 BUS_DMA_ALLOCNOW, /* flags */ 1921 NULL, NULL, /* lockfunc, lockarg */ 1922 &sc->sc_parent_dtag); 1923 if (error) { 1924 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1925 return error; 1926 } 1927 1928 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1929 1930 /* 1931 * Create TX ring DMA stuffs 1932 */ 1933 error = bus_dma_tag_create(sc->sc_parent_dtag, 1934 BWI_RING_ALIGN, 0, 1935 BUS_SPACE_MAXADDR, 1936 BUS_SPACE_MAXADDR, 1937 NULL, NULL, 1938 tx_ring_sz, 1939 1, 1940 BUS_SPACE_MAXSIZE_32BIT, 1941 BUS_DMA_ALLOCNOW, 1942 NULL, NULL, 1943 &sc->sc_txring_dtag); 1944 if (error) { 1945 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1946 return error; 1947 } 1948 1949 for (i = 0; i < BWI_TX_NRING; ++i) { 1950 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1951 &sc->sc_tx_rdata[i], tx_ring_sz, 1952 TXRX_CTRL(i)); 1953 if (error) { 1954 device_printf(sc->sc_dev, "%dth TX ring " 1955 "DMA alloc failed\n", i); 1956 return error; 1957 } 1958 } 1959 1960 /* 1961 * Create RX ring DMA stuffs 1962 */ 1963 error = bus_dma_tag_create(sc->sc_parent_dtag, 1964 BWI_RING_ALIGN, 0, 1965 BUS_SPACE_MAXADDR, 1966 BUS_SPACE_MAXADDR, 1967 NULL, NULL, 1968 rx_ring_sz, 1969 1, 1970 BUS_SPACE_MAXSIZE_32BIT, 1971 BUS_DMA_ALLOCNOW, 1972 NULL, NULL, 1973 &sc->sc_rxring_dtag); 1974 if (error) { 1975 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1976 return error; 1977 } 1978 1979 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1980 rx_ring_sz, TXRX_CTRL(0)); 1981 if (error) { 1982 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1983 return error; 1984 } 1985 1986 if (has_txstats) { 1987 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1988 if (error) { 1989 device_printf(sc->sc_dev, 1990 "TX stats DMA alloc failed\n"); 1991 return error; 1992 } 1993 } 1994 1995 #undef TXRX_CTRL 1996 1997 return bwi_dma_mbuf_create(sc); 1998 } 1999 2000 static void 2001 bwi_dma_free(struct bwi_softc *sc) 2002 { 2003 if (sc->sc_txring_dtag != NULL) { 2004 int i; 2005 2006 for (i = 0; i < BWI_TX_NRING; ++i) { 2007 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 2008 2009 if (rd->rdata_desc != NULL) { 2010 bus_dmamap_unload(sc->sc_txring_dtag, 2011 rd->rdata_dmap); 2012 bus_dmamem_free(sc->sc_txring_dtag, 2013 rd->rdata_desc, 2014 rd->rdata_dmap); 2015 } 2016 } 2017 bus_dma_tag_destroy(sc->sc_txring_dtag); 2018 } 2019 2020 if (sc->sc_rxring_dtag != NULL) { 2021 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2022 2023 if (rd->rdata_desc != NULL) { 2024 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 2025 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 2026 rd->rdata_dmap); 2027 } 2028 bus_dma_tag_destroy(sc->sc_rxring_dtag); 2029 } 2030 2031 bwi_dma_txstats_free(sc); 2032 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 2033 2034 if (sc->sc_parent_dtag != NULL) 2035 bus_dma_tag_destroy(sc->sc_parent_dtag); 2036 } 2037 2038 static int 2039 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2040 struct bwi_ring_data *rd, bus_size_t size, 2041 uint32_t txrx_ctrl) 2042 { 2043 int error; 2044 2045 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2046 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2047 &rd->rdata_dmap); 2048 if (error) { 2049 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2050 return error; 2051 } 2052 2053 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2054 bwi_dma_ring_addr, &rd->rdata_paddr, 2055 BUS_DMA_NOWAIT); 2056 if (error) { 2057 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2058 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2059 rd->rdata_desc = NULL; 2060 return error; 2061 } 2062 2063 rd->rdata_txrx_ctrl = txrx_ctrl; 2064 return 0; 2065 } 2066 2067 static int 2068 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2069 bus_size_t desc_sz) 2070 { 2071 struct bwi_txstats_data *st; 2072 bus_size_t dma_size; 2073 int error; 2074 2075 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2076 if (st == NULL) { 2077 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2078 return ENOMEM; 2079 } 2080 sc->sc_txstats = st; 2081 2082 /* 2083 * Create TX stats descriptor DMA stuffs 2084 */ 2085 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2086 2087 error = bus_dma_tag_create(sc->sc_parent_dtag, 2088 BWI_RING_ALIGN, 2089 0, 2090 BUS_SPACE_MAXADDR, 2091 BUS_SPACE_MAXADDR, 2092 NULL, NULL, 2093 dma_size, 2094 1, 2095 BUS_SPACE_MAXSIZE_32BIT, 2096 BUS_DMA_ALLOCNOW, 2097 NULL, NULL, 2098 &st->stats_ring_dtag); 2099 if (error) { 2100 device_printf(sc->sc_dev, "can't create txstats ring " 2101 "DMA tag\n"); 2102 return error; 2103 } 2104 2105 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2106 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2107 &st->stats_ring_dmap); 2108 if (error) { 2109 device_printf(sc->sc_dev, "can't allocate txstats ring " 2110 "DMA mem\n"); 2111 bus_dma_tag_destroy(st->stats_ring_dtag); 2112 st->stats_ring_dtag = NULL; 2113 return error; 2114 } 2115 2116 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2117 st->stats_ring, dma_size, 2118 bwi_dma_ring_addr, &st->stats_ring_paddr, 2119 BUS_DMA_NOWAIT); 2120 if (error) { 2121 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2122 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2123 st->stats_ring_dmap); 2124 bus_dma_tag_destroy(st->stats_ring_dtag); 2125 st->stats_ring_dtag = NULL; 2126 return error; 2127 } 2128 2129 /* 2130 * Create TX stats DMA stuffs 2131 */ 2132 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2133 BWI_ALIGN); 2134 2135 error = bus_dma_tag_create(sc->sc_parent_dtag, 2136 BWI_ALIGN, 2137 0, 2138 BUS_SPACE_MAXADDR, 2139 BUS_SPACE_MAXADDR, 2140 NULL, NULL, 2141 dma_size, 2142 1, 2143 BUS_SPACE_MAXSIZE_32BIT, 2144 BUS_DMA_ALLOCNOW, 2145 NULL, NULL, 2146 &st->stats_dtag); 2147 if (error) { 2148 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2149 return error; 2150 } 2151 2152 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2153 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2154 &st->stats_dmap); 2155 if (error) { 2156 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2157 bus_dma_tag_destroy(st->stats_dtag); 2158 st->stats_dtag = NULL; 2159 return error; 2160 } 2161 2162 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2163 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2164 BUS_DMA_NOWAIT); 2165 if (error) { 2166 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2167 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2168 bus_dma_tag_destroy(st->stats_dtag); 2169 st->stats_dtag = NULL; 2170 return error; 2171 } 2172 2173 st->stats_ctrl_base = ctrl_base; 2174 return 0; 2175 } 2176 2177 static void 2178 bwi_dma_txstats_free(struct bwi_softc *sc) 2179 { 2180 struct bwi_txstats_data *st; 2181 2182 if (sc->sc_txstats == NULL) 2183 return; 2184 st = sc->sc_txstats; 2185 2186 if (st->stats_ring_dtag != NULL) { 2187 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2188 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2189 st->stats_ring_dmap); 2190 bus_dma_tag_destroy(st->stats_ring_dtag); 2191 } 2192 2193 if (st->stats_dtag != NULL) { 2194 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2195 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2196 bus_dma_tag_destroy(st->stats_dtag); 2197 } 2198 2199 free(st, M_DEVBUF); 2200 } 2201 2202 static void 2203 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2204 { 2205 KASSERT(nseg == 1, ("too many segments\n")); 2206 *((bus_addr_t *)arg) = seg->ds_addr; 2207 } 2208 2209 static int 2210 bwi_dma_mbuf_create(struct bwi_softc *sc) 2211 { 2212 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2213 int i, j, k, ntx, error; 2214 2215 /* 2216 * Create TX/RX mbuf DMA tag 2217 */ 2218 error = bus_dma_tag_create(sc->sc_parent_dtag, 2219 1, 2220 0, 2221 BUS_SPACE_MAXADDR, 2222 BUS_SPACE_MAXADDR, 2223 NULL, NULL, 2224 MCLBYTES, 2225 1, 2226 BUS_SPACE_MAXSIZE_32BIT, 2227 BUS_DMA_ALLOCNOW, 2228 NULL, NULL, 2229 &sc->sc_buf_dtag); 2230 if (error) { 2231 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2232 return error; 2233 } 2234 2235 ntx = 0; 2236 2237 /* 2238 * Create TX mbuf DMA map 2239 */ 2240 for (i = 0; i < BWI_TX_NRING; ++i) { 2241 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2242 2243 for (j = 0; j < BWI_TX_NDESC; ++j) { 2244 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2245 &tbd->tbd_buf[j].tb_dmap); 2246 if (error) { 2247 device_printf(sc->sc_dev, "can't create " 2248 "%dth tbd, %dth DMA map\n", i, j); 2249 2250 ntx = i; 2251 for (k = 0; k < j; ++k) { 2252 bus_dmamap_destroy(sc->sc_buf_dtag, 2253 tbd->tbd_buf[k].tb_dmap); 2254 } 2255 goto fail; 2256 } 2257 } 2258 } 2259 ntx = BWI_TX_NRING; 2260 2261 /* 2262 * Create RX mbuf DMA map and a spare DMA map 2263 */ 2264 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2265 &rbd->rbd_tmp_dmap); 2266 if (error) { 2267 device_printf(sc->sc_dev, 2268 "can't create spare RX buf DMA map\n"); 2269 goto fail; 2270 } 2271 2272 for (j = 0; j < BWI_RX_NDESC; ++j) { 2273 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2274 &rbd->rbd_buf[j].rb_dmap); 2275 if (error) { 2276 device_printf(sc->sc_dev, "can't create %dth " 2277 "RX buf DMA map\n", j); 2278 2279 for (k = 0; k < j; ++k) { 2280 bus_dmamap_destroy(sc->sc_buf_dtag, 2281 rbd->rbd_buf[j].rb_dmap); 2282 } 2283 bus_dmamap_destroy(sc->sc_buf_dtag, 2284 rbd->rbd_tmp_dmap); 2285 goto fail; 2286 } 2287 } 2288 2289 return 0; 2290 fail: 2291 bwi_dma_mbuf_destroy(sc, ntx, 0); 2292 return error; 2293 } 2294 2295 static void 2296 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2297 { 2298 int i, j; 2299 2300 if (sc->sc_buf_dtag == NULL) 2301 return; 2302 2303 for (i = 0; i < ntx; ++i) { 2304 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2305 2306 for (j = 0; j < BWI_TX_NDESC; ++j) { 2307 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2308 2309 if (tb->tb_mbuf != NULL) { 2310 bus_dmamap_unload(sc->sc_buf_dtag, 2311 tb->tb_dmap); 2312 m_freem(tb->tb_mbuf); 2313 } 2314 if (tb->tb_ni != NULL) 2315 ieee80211_free_node(tb->tb_ni); 2316 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2317 } 2318 } 2319 2320 if (nrx) { 2321 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2322 2323 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2324 for (j = 0; j < BWI_RX_NDESC; ++j) { 2325 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2326 2327 if (rb->rb_mbuf != NULL) { 2328 bus_dmamap_unload(sc->sc_buf_dtag, 2329 rb->rb_dmap); 2330 m_freem(rb->rb_mbuf); 2331 } 2332 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2333 } 2334 } 2335 2336 bus_dma_tag_destroy(sc->sc_buf_dtag); 2337 sc->sc_buf_dtag = NULL; 2338 } 2339 2340 static void 2341 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2342 { 2343 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2344 } 2345 2346 static void 2347 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2348 { 2349 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2350 } 2351 2352 static int 2353 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2354 { 2355 struct bwi_ring_data *rd; 2356 struct bwi_txbuf_data *tbd; 2357 uint32_t val, addr_hi, addr_lo; 2358 2359 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2360 rd = &sc->sc_tx_rdata[ring_idx]; 2361 tbd = &sc->sc_tx_bdata[ring_idx]; 2362 2363 tbd->tbd_idx = 0; 2364 tbd->tbd_used = 0; 2365 2366 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2367 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2368 BUS_DMASYNC_PREWRITE); 2369 2370 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2371 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2372 2373 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2374 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2375 BWI_TXRX32_RINGINFO_FUNC_MASK); 2376 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2377 2378 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2379 BWI_TXRX32_CTRL_ENABLE; 2380 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2381 2382 return 0; 2383 } 2384 2385 static void 2386 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2387 bus_addr_t paddr, int hdr_size, int ndesc) 2388 { 2389 uint32_t val, addr_hi, addr_lo; 2390 2391 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2392 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2393 2394 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2395 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2396 BWI_TXRX32_RINGINFO_FUNC_MASK); 2397 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2398 2399 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2400 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2401 BWI_TXRX32_CTRL_ENABLE; 2402 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2403 2404 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2405 (ndesc - 1) * sizeof(struct bwi_desc32)); 2406 } 2407 2408 static int 2409 bwi_init_rx_ring32(struct bwi_softc *sc) 2410 { 2411 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2412 int i, error; 2413 2414 sc->sc_rx_bdata.rbd_idx = 0; 2415 2416 for (i = 0; i < BWI_RX_NDESC; ++i) { 2417 error = bwi_newbuf(sc, i, 1); 2418 if (error) { 2419 device_printf(sc->sc_dev, 2420 "can't allocate %dth RX buffer\n", i); 2421 return error; 2422 } 2423 } 2424 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2425 BUS_DMASYNC_PREWRITE); 2426 2427 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2428 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2429 return 0; 2430 } 2431 2432 static int 2433 bwi_init_txstats32(struct bwi_softc *sc) 2434 { 2435 struct bwi_txstats_data *st = sc->sc_txstats; 2436 bus_addr_t stats_paddr; 2437 int i; 2438 2439 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2440 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2441 2442 st->stats_idx = 0; 2443 2444 stats_paddr = st->stats_paddr; 2445 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2446 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2447 stats_paddr, sizeof(struct bwi_txstats), 0); 2448 stats_paddr += sizeof(struct bwi_txstats); 2449 } 2450 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2451 BUS_DMASYNC_PREWRITE); 2452 2453 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2454 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2455 return 0; 2456 } 2457 2458 static void 2459 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2460 int buf_len) 2461 { 2462 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2463 2464 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2465 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2466 paddr, buf_len, 0); 2467 } 2468 2469 static void 2470 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2471 int buf_idx, bus_addr_t paddr, int buf_len) 2472 { 2473 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2474 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2475 paddr, buf_len, 1); 2476 } 2477 2478 static int 2479 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2480 { 2481 /* TODO:64 */ 2482 return EOPNOTSUPP; 2483 } 2484 2485 static int 2486 bwi_init_rx_ring64(struct bwi_softc *sc) 2487 { 2488 /* TODO:64 */ 2489 return EOPNOTSUPP; 2490 } 2491 2492 static int 2493 bwi_init_txstats64(struct bwi_softc *sc) 2494 { 2495 /* TODO:64 */ 2496 return EOPNOTSUPP; 2497 } 2498 2499 static void 2500 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2501 int buf_len) 2502 { 2503 /* TODO:64 */ 2504 } 2505 2506 static void 2507 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2508 int buf_idx, bus_addr_t paddr, int buf_len) 2509 { 2510 /* TODO:64 */ 2511 } 2512 2513 static void 2514 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2515 bus_size_t mapsz __unused, int error) 2516 { 2517 if (!error) { 2518 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2519 *((bus_addr_t *)arg) = seg->ds_addr; 2520 } 2521 } 2522 2523 static int 2524 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2525 { 2526 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2527 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2528 struct bwi_rxbuf_hdr *hdr; 2529 bus_dmamap_t map; 2530 bus_addr_t paddr; 2531 struct mbuf *m; 2532 int error; 2533 2534 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2535 2536 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2537 if (m == NULL) { 2538 error = ENOBUFS; 2539 2540 /* 2541 * If the NIC is up and running, we need to: 2542 * - Clear RX buffer's header. 2543 * - Restore RX descriptor settings. 2544 */ 2545 if (init) 2546 return error; 2547 else 2548 goto back; 2549 } 2550 m->m_len = m->m_pkthdr.len = MCLBYTES; 2551 2552 /* 2553 * Try to load RX buf into temporary DMA map 2554 */ 2555 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2556 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2557 if (error) { 2558 m_freem(m); 2559 2560 /* 2561 * See the comment above 2562 */ 2563 if (init) 2564 return error; 2565 else 2566 goto back; 2567 } 2568 2569 if (!init) 2570 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2571 rxbuf->rb_mbuf = m; 2572 rxbuf->rb_paddr = paddr; 2573 2574 /* 2575 * Swap RX buf's DMA map with the loaded temporary one 2576 */ 2577 map = rxbuf->rb_dmap; 2578 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2579 rbd->rbd_tmp_dmap = map; 2580 2581 back: 2582 /* 2583 * Clear RX buf header 2584 */ 2585 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2586 bzero(hdr, sizeof(*hdr)); 2587 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2588 2589 /* 2590 * Setup RX buf descriptor 2591 */ 2592 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2593 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2594 return error; 2595 } 2596 2597 static void 2598 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2599 const uint8_t *addr) 2600 { 2601 int i; 2602 2603 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2604 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2605 2606 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2607 uint16_t addr_val; 2608 2609 addr_val = (uint16_t)addr[i * 2] | 2610 (((uint16_t)addr[(i * 2) + 1]) << 8); 2611 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2612 } 2613 } 2614 2615 static int 2616 bwi_rxeof(struct bwi_softc *sc, int end_idx) 2617 { 2618 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2619 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2620 struct ifnet *ifp = sc->sc_ifp; 2621 struct ieee80211com *ic = ifp->if_l2com; 2622 int idx, rx_data = 0; 2623 2624 idx = rbd->rbd_idx; 2625 while (idx != end_idx) { 2626 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2627 struct bwi_rxbuf_hdr *hdr; 2628 struct ieee80211_frame_min *wh; 2629 struct ieee80211_node *ni; 2630 struct mbuf *m; 2631 uint32_t plcp; 2632 uint16_t flags2; 2633 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2634 2635 m = rb->rb_mbuf; 2636 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2637 BUS_DMASYNC_POSTREAD); 2638 2639 if (bwi_newbuf(sc, idx, 0)) { 2640 ifp->if_ierrors++; 2641 goto next; 2642 } 2643 2644 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2645 flags2 = le16toh(hdr->rxh_flags2); 2646 2647 hdr_extra = 0; 2648 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2649 hdr_extra = 2; 2650 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2651 2652 buflen = le16toh(hdr->rxh_buflen); 2653 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2654 if_printf(ifp, "%s: zero length data, hdr_extra %d\n", 2655 __func__, hdr_extra); 2656 ifp->if_ierrors++; 2657 m_freem(m); 2658 goto next; 2659 } 2660 2661 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp)); 2662 rssi = bwi_calc_rssi(sc, hdr); 2663 noise = bwi_calc_noise(sc); 2664 2665 m->m_pkthdr.rcvif = ifp; 2666 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2667 m_adj(m, sizeof(*hdr) + wh_ofs); 2668 2669 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2670 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM); 2671 else 2672 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK); 2673 2674 /* RX radio tap */ 2675 if (ieee80211_radiotap_active(ic)) 2676 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise); 2677 2678 m_adj(m, -IEEE80211_CRC_LEN); 2679 2680 BWI_UNLOCK(sc); 2681 2682 wh = mtod(m, struct ieee80211_frame_min *); 2683 ni = ieee80211_find_rxnode(ic, wh); 2684 if (ni != NULL) { 2685 type = ieee80211_input(ni, m, rssi - noise, noise); 2686 ieee80211_free_node(ni); 2687 } else 2688 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2689 if (type == IEEE80211_FC0_TYPE_DATA) { 2690 rx_data = 1; 2691 sc->sc_rx_rate = rate; 2692 } 2693 2694 BWI_LOCK(sc); 2695 next: 2696 idx = (idx + 1) % BWI_RX_NDESC; 2697 2698 if (sc->sc_flags & BWI_F_STOP) { 2699 /* 2700 * Take the fast lane, don't do 2701 * any damage to softc 2702 */ 2703 return -1; 2704 } 2705 } 2706 2707 rbd->rbd_idx = idx; 2708 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2709 BUS_DMASYNC_PREWRITE); 2710 2711 return rx_data; 2712 } 2713 2714 static int 2715 bwi_rxeof32(struct bwi_softc *sc) 2716 { 2717 uint32_t val, rx_ctrl; 2718 int end_idx, rx_data; 2719 2720 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2721 2722 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2723 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2724 sizeof(struct bwi_desc32); 2725 2726 rx_data = bwi_rxeof(sc, end_idx); 2727 if (rx_data >= 0) { 2728 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2729 end_idx * sizeof(struct bwi_desc32)); 2730 } 2731 return rx_data; 2732 } 2733 2734 static int 2735 bwi_rxeof64(struct bwi_softc *sc) 2736 { 2737 /* TODO:64 */ 2738 return 0; 2739 } 2740 2741 static void 2742 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2743 { 2744 int i; 2745 2746 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2747 2748 #define NRETRY 10 2749 2750 for (i = 0; i < NRETRY; ++i) { 2751 uint32_t status; 2752 2753 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2754 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2755 BWI_RX32_STATUS_STATE_DISABLED) 2756 break; 2757 2758 DELAY(1000); 2759 } 2760 if (i == NRETRY) 2761 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2762 2763 #undef NRETRY 2764 2765 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2766 } 2767 2768 static void 2769 bwi_free_txstats32(struct bwi_softc *sc) 2770 { 2771 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2772 } 2773 2774 static void 2775 bwi_free_rx_ring32(struct bwi_softc *sc) 2776 { 2777 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2778 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2779 int i; 2780 2781 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2782 2783 for (i = 0; i < BWI_RX_NDESC; ++i) { 2784 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2785 2786 if (rb->rb_mbuf != NULL) { 2787 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2788 m_freem(rb->rb_mbuf); 2789 rb->rb_mbuf = NULL; 2790 } 2791 } 2792 } 2793 2794 static void 2795 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2796 { 2797 struct bwi_ring_data *rd; 2798 struct bwi_txbuf_data *tbd; 2799 struct ifnet *ifp = sc->sc_ifp; 2800 uint32_t state, val; 2801 int i; 2802 2803 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2804 rd = &sc->sc_tx_rdata[ring_idx]; 2805 tbd = &sc->sc_tx_bdata[ring_idx]; 2806 2807 #define NRETRY 10 2808 2809 for (i = 0; i < NRETRY; ++i) { 2810 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2811 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2812 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2813 state == BWI_TX32_STATUS_STATE_IDLE || 2814 state == BWI_TX32_STATUS_STATE_STOPPED) 2815 break; 2816 2817 DELAY(1000); 2818 } 2819 if (i == NRETRY) { 2820 if_printf(ifp, "%s: wait for TX ring(%d) stable timed out\n", 2821 __func__, ring_idx); 2822 } 2823 2824 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2825 for (i = 0; i < NRETRY; ++i) { 2826 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2827 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2828 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2829 break; 2830 2831 DELAY(1000); 2832 } 2833 if (i == NRETRY) 2834 if_printf(ifp, "%s: reset TX ring (%d) timed out\n", 2835 __func__, ring_idx); 2836 2837 #undef NRETRY 2838 2839 DELAY(1000); 2840 2841 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2842 2843 for (i = 0; i < BWI_TX_NDESC; ++i) { 2844 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2845 2846 if (tb->tb_mbuf != NULL) { 2847 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2848 m_freem(tb->tb_mbuf); 2849 tb->tb_mbuf = NULL; 2850 } 2851 if (tb->tb_ni != NULL) { 2852 ieee80211_free_node(tb->tb_ni); 2853 tb->tb_ni = NULL; 2854 } 2855 } 2856 } 2857 2858 static void 2859 bwi_free_txstats64(struct bwi_softc *sc) 2860 { 2861 /* TODO:64 */ 2862 } 2863 2864 static void 2865 bwi_free_rx_ring64(struct bwi_softc *sc) 2866 { 2867 /* TODO:64 */ 2868 } 2869 2870 static void 2871 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2872 { 2873 /* TODO:64 */ 2874 } 2875 2876 /* XXX does not belong here */ 2877 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2878 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2879 2880 static __inline void 2881 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2882 { 2883 uint32_t plcp; 2884 2885 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2886 IEEE80211_OFDM_PLCP_RATE_MASK) | 2887 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2888 *plcp0 = htole32(plcp); 2889 } 2890 2891 static __inline void 2892 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2893 uint8_t rate) 2894 { 2895 int len, service, pkt_bitlen; 2896 2897 pkt_bitlen = pkt_len * NBBY; 2898 len = howmany(pkt_bitlen * 2, rate); 2899 2900 service = IEEE80211_PLCP_SERVICE_LOCKED; 2901 if (rate == (11 * 2)) { 2902 int pkt_bitlen1; 2903 2904 /* 2905 * PLCP service field needs to be adjusted, 2906 * if TX rate is 11Mbytes/s 2907 */ 2908 pkt_bitlen1 = len * 11; 2909 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2910 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2911 } 2912 2913 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2914 plcp->i_service = service; 2915 plcp->i_length = htole16(len); 2916 /* NOTE: do NOT touch i_crc */ 2917 } 2918 2919 static __inline void 2920 bwi_plcp_header(const struct ieee80211_rate_table *rt, 2921 void *plcp, int pkt_len, uint8_t rate) 2922 { 2923 enum ieee80211_phytype modtype; 2924 2925 /* 2926 * Assume caller has zeroed 'plcp' 2927 */ 2928 modtype = ieee80211_rate2phytype(rt, rate); 2929 if (modtype == IEEE80211_T_OFDM) 2930 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2931 else if (modtype == IEEE80211_T_DS) 2932 bwi_ds_plcp_header(plcp, pkt_len, rate); 2933 else 2934 panic("unsupport modulation type %u\n", modtype); 2935 } 2936 2937 static int 2938 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2939 struct ieee80211_node *ni) 2940 { 2941 struct ieee80211vap *vap = ni->ni_vap; 2942 struct ifnet *ifp = sc->sc_ifp; 2943 struct ieee80211com *ic = ifp->if_l2com; 2944 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2945 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2946 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2947 struct bwi_mac *mac; 2948 struct bwi_txbuf_hdr *hdr; 2949 struct ieee80211_frame *wh; 2950 const struct ieee80211_txparam *tp; 2951 uint8_t rate, rate_fb; 2952 uint32_t mac_ctrl; 2953 uint16_t phy_ctrl; 2954 bus_addr_t paddr; 2955 int type, ismcast, pkt_len, error, rix; 2956 #if 0 2957 const uint8_t *p; 2958 int i; 2959 #endif 2960 2961 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2962 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2963 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2964 2965 wh = mtod(m, struct ieee80211_frame *); 2966 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2967 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2968 2969 /* Get 802.11 frame len before prepending TX header */ 2970 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2971 2972 /* 2973 * Find TX rate 2974 */ 2975 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 2976 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2977 rate = rate_fb = tp->mgmtrate; 2978 } else if (ismcast) { 2979 rate = rate_fb = tp->mcastrate; 2980 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2981 rate = rate_fb = tp->ucastrate; 2982 } else { 2983 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len); 2984 rate = ni->ni_txrate; 2985 2986 if (rix > 0) { 2987 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2988 IEEE80211_RATE_VAL; 2989 } else { 2990 rate_fb = rate; 2991 } 2992 } 2993 tb->tb_rate[0] = rate; 2994 tb->tb_rate[1] = rate_fb; 2995 sc->sc_tx_rate = rate; 2996 2997 /* 2998 * TX radio tap 2999 */ 3000 if (ieee80211_radiotap_active_vap(vap)) { 3001 sc->sc_tx_th.wt_flags = 0; 3002 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3003 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3004 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 3005 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3006 rate != (1 * 2)) { 3007 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3008 } 3009 sc->sc_tx_th.wt_rate = rate; 3010 3011 ieee80211_radiotap_tx(vap, m); 3012 } 3013 3014 /* 3015 * Setup the embedded TX header 3016 */ 3017 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3018 if (m == NULL) { 3019 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3020 return ENOBUFS; 3021 } 3022 hdr = mtod(m, struct bwi_txbuf_hdr *); 3023 3024 bzero(hdr, sizeof(*hdr)); 3025 3026 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3027 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3028 3029 if (!ismcast) { 3030 uint16_t dur; 3031 3032 dur = ieee80211_ack_duration(sc->sc_rates, rate, 3033 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 3034 3035 hdr->txh_fb_duration = htole16(dur); 3036 } 3037 3038 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3039 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3040 3041 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3042 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3043 3044 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3045 BWI_TXH_PHY_C_ANTMODE_MASK); 3046 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3047 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3048 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3049 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3050 3051 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3052 if (!ismcast) 3053 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3054 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3055 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3056 3057 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3058 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3059 3060 /* Catch any further usage */ 3061 hdr = NULL; 3062 wh = NULL; 3063 3064 /* DMA load */ 3065 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3066 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3067 if (error && error != EFBIG) { 3068 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3069 __func__, error); 3070 goto back; 3071 } 3072 3073 if (error) { /* error == EFBIG */ 3074 struct mbuf *m_new; 3075 3076 m_new = m_defrag(m, M_NOWAIT); 3077 if (m_new == NULL) { 3078 if_printf(ifp, "%s: can't defrag TX buffer\n", 3079 __func__); 3080 error = ENOBUFS; 3081 goto back; 3082 } else { 3083 m = m_new; 3084 } 3085 3086 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3087 bwi_dma_buf_addr, &paddr, 3088 BUS_DMA_NOWAIT); 3089 if (error) { 3090 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3091 __func__, error); 3092 goto back; 3093 } 3094 } 3095 error = 0; 3096 3097 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3098 3099 tb->tb_mbuf = m; 3100 tb->tb_ni = ni; 3101 3102 #if 0 3103 p = mtod(m, const uint8_t *); 3104 for (i = 0; i < m->m_pkthdr.len; ++i) { 3105 if (i != 0 && i % 8 == 0) 3106 printf("\n"); 3107 printf("%02x ", p[i]); 3108 } 3109 printf("\n"); 3110 #endif 3111 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3112 idx, pkt_len, m->m_pkthdr.len); 3113 3114 /* Setup TX descriptor */ 3115 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3116 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3117 BUS_DMASYNC_PREWRITE); 3118 3119 /* Kick start */ 3120 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3121 3122 back: 3123 if (error) 3124 m_freem(m); 3125 return error; 3126 } 3127 3128 static int 3129 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3130 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3131 { 3132 struct ifnet *ifp = sc->sc_ifp; 3133 struct ieee80211vap *vap = ni->ni_vap; 3134 struct ieee80211com *ic = ni->ni_ic; 3135 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3136 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3137 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3138 struct bwi_mac *mac; 3139 struct bwi_txbuf_hdr *hdr; 3140 struct ieee80211_frame *wh; 3141 uint8_t rate, rate_fb; 3142 uint32_t mac_ctrl; 3143 uint16_t phy_ctrl; 3144 bus_addr_t paddr; 3145 int ismcast, pkt_len, error; 3146 3147 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3148 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3149 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3150 3151 wh = mtod(m, struct ieee80211_frame *); 3152 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3153 3154 /* Get 802.11 frame len before prepending TX header */ 3155 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3156 3157 /* 3158 * Find TX rate 3159 */ 3160 rate = params->ibp_rate0; 3161 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3162 /* XXX fall back to mcast/mgmt rate? */ 3163 m_freem(m); 3164 return EINVAL; 3165 } 3166 if (params->ibp_try1 != 0) { 3167 rate_fb = params->ibp_rate1; 3168 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3169 /* XXX fall back to rate0? */ 3170 m_freem(m); 3171 return EINVAL; 3172 } 3173 } else 3174 rate_fb = rate; 3175 tb->tb_rate[0] = rate; 3176 tb->tb_rate[1] = rate_fb; 3177 sc->sc_tx_rate = rate; 3178 3179 /* 3180 * TX radio tap 3181 */ 3182 if (ieee80211_radiotap_active_vap(vap)) { 3183 sc->sc_tx_th.wt_flags = 0; 3184 /* XXX IEEE80211_BPF_CRYPTO */ 3185 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3186 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3187 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3188 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3189 sc->sc_tx_th.wt_rate = rate; 3190 3191 ieee80211_radiotap_tx(vap, m); 3192 } 3193 3194 /* 3195 * Setup the embedded TX header 3196 */ 3197 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3198 if (m == NULL) { 3199 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3200 return ENOBUFS; 3201 } 3202 hdr = mtod(m, struct bwi_txbuf_hdr *); 3203 3204 bzero(hdr, sizeof(*hdr)); 3205 3206 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3207 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3208 3209 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3210 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3211 uint16_t dur; 3212 3213 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3214 3215 hdr->txh_fb_duration = htole16(dur); 3216 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3217 } 3218 3219 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3220 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3221 3222 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3223 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3224 3225 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3226 BWI_TXH_PHY_C_ANTMODE_MASK); 3227 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3228 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3229 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3230 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3231 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3232 3233 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3234 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3235 3236 /* Catch any further usage */ 3237 hdr = NULL; 3238 wh = NULL; 3239 3240 /* DMA load */ 3241 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3242 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3243 if (error != 0) { 3244 struct mbuf *m_new; 3245 3246 if (error != EFBIG) { 3247 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3248 __func__, error); 3249 goto back; 3250 } 3251 m_new = m_defrag(m, M_NOWAIT); 3252 if (m_new == NULL) { 3253 if_printf(ifp, "%s: can't defrag TX buffer\n", 3254 __func__); 3255 error = ENOBUFS; 3256 goto back; 3257 } 3258 m = m_new; 3259 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3260 bwi_dma_buf_addr, &paddr, 3261 BUS_DMA_NOWAIT); 3262 if (error) { 3263 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3264 __func__, error); 3265 goto back; 3266 } 3267 } 3268 3269 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3270 3271 tb->tb_mbuf = m; 3272 tb->tb_ni = ni; 3273 3274 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3275 idx, pkt_len, m->m_pkthdr.len); 3276 3277 /* Setup TX descriptor */ 3278 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3279 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3280 BUS_DMASYNC_PREWRITE); 3281 3282 /* Kick start */ 3283 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3284 back: 3285 if (error) 3286 m_freem(m); 3287 return error; 3288 } 3289 3290 static void 3291 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3292 { 3293 idx = (idx + 1) % BWI_TX_NDESC; 3294 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3295 idx * sizeof(struct bwi_desc32)); 3296 } 3297 3298 static void 3299 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3300 { 3301 /* TODO:64 */ 3302 } 3303 3304 static void 3305 bwi_txeof_status32(struct bwi_softc *sc) 3306 { 3307 struct ifnet *ifp = sc->sc_ifp; 3308 uint32_t val, ctrl_base; 3309 int end_idx; 3310 3311 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3312 3313 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3314 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3315 sizeof(struct bwi_desc32); 3316 3317 bwi_txeof_status(sc, end_idx); 3318 3319 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3320 end_idx * sizeof(struct bwi_desc32)); 3321 3322 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3323 ifp->if_start(ifp); 3324 } 3325 3326 static void 3327 bwi_txeof_status64(struct bwi_softc *sc) 3328 { 3329 /* TODO:64 */ 3330 } 3331 3332 static void 3333 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3334 { 3335 struct ifnet *ifp = sc->sc_ifp; 3336 struct bwi_txbuf_data *tbd; 3337 struct bwi_txbuf *tb; 3338 int ring_idx, buf_idx; 3339 struct ieee80211_node *ni; 3340 struct ieee80211vap *vap; 3341 3342 if (tx_id == 0) { 3343 if_printf(ifp, "%s: zero tx id\n", __func__); 3344 return; 3345 } 3346 3347 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3348 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3349 3350 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3351 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3352 3353 tbd = &sc->sc_tx_bdata[ring_idx]; 3354 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3355 tbd->tbd_used--; 3356 3357 tb = &tbd->tbd_buf[buf_idx]; 3358 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3359 "acked %d, data_txcnt %d, ni %p\n", 3360 buf_idx, acked, data_txcnt, tb->tb_ni); 3361 3362 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3363 3364 ni = tb->tb_ni; 3365 if (tb->tb_ni != NULL) { 3366 const struct bwi_txbuf_hdr *hdr = 3367 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3368 vap = ni->ni_vap; 3369 3370 /* NB: update rate control only for unicast frames */ 3371 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3372 /* 3373 * Feed back 'acked and data_txcnt'. Note that the 3374 * generic AMRR code only understands one tx rate 3375 * and the estimator doesn't handle real retry counts 3376 * well so to avoid over-aggressive downshifting we 3377 * treat any number of retries as "1". 3378 */ 3379 ieee80211_ratectl_tx_complete(vap, ni, 3380 (data_txcnt > 1) ? IEEE80211_RATECTL_TX_SUCCESS : 3381 IEEE80211_RATECTL_TX_FAILURE, &acked, NULL); 3382 } 3383 3384 /* 3385 * Do any tx complete callback. Note this must 3386 * be done before releasing the node reference. 3387 */ 3388 if (tb->tb_mbuf->m_flags & M_TXCB) 3389 ieee80211_process_callback(ni, tb->tb_mbuf, !acked); 3390 3391 ieee80211_free_node(tb->tb_ni); 3392 tb->tb_ni = NULL; 3393 } 3394 m_freem(tb->tb_mbuf); 3395 tb->tb_mbuf = NULL; 3396 3397 if (tbd->tbd_used == 0) 3398 sc->sc_tx_timer = 0; 3399 3400 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3401 } 3402 3403 static void 3404 bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3405 { 3406 struct bwi_txstats_data *st = sc->sc_txstats; 3407 int idx; 3408 3409 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3410 3411 idx = st->stats_idx; 3412 while (idx != end_idx) { 3413 const struct bwi_txstats *stats = &st->stats[idx]; 3414 3415 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3416 int data_txcnt; 3417 3418 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3419 BWI_TXS_TXCNT_DATA); 3420 _bwi_txeof(sc, le16toh(stats->txs_id), 3421 stats->txs_flags & BWI_TXS_F_ACKED, 3422 data_txcnt); 3423 } 3424 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3425 } 3426 st->stats_idx = idx; 3427 } 3428 3429 static void 3430 bwi_txeof(struct bwi_softc *sc) 3431 { 3432 struct ifnet *ifp = sc->sc_ifp; 3433 3434 for (;;) { 3435 uint32_t tx_status0, tx_status1; 3436 uint16_t tx_id; 3437 int data_txcnt; 3438 3439 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3440 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3441 break; 3442 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3443 3444 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3445 data_txcnt = __SHIFTOUT(tx_status0, 3446 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3447 3448 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3449 continue; 3450 3451 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3452 data_txcnt); 3453 } 3454 3455 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3456 ifp->if_start(ifp); 3457 } 3458 3459 static int 3460 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3461 { 3462 bwi_power_on(sc, 1); 3463 return bwi_set_clock_mode(sc, clk_mode); 3464 } 3465 3466 static void 3467 bwi_bbp_power_off(struct bwi_softc *sc) 3468 { 3469 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3470 bwi_power_off(sc, 1); 3471 } 3472 3473 static int 3474 bwi_get_pwron_delay(struct bwi_softc *sc) 3475 { 3476 struct bwi_regwin *com, *old; 3477 struct bwi_clock_freq freq; 3478 uint32_t val; 3479 int error; 3480 3481 com = &sc->sc_com_regwin; 3482 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3483 3484 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3485 return 0; 3486 3487 error = bwi_regwin_switch(sc, com, &old); 3488 if (error) 3489 return error; 3490 3491 bwi_get_clock_freq(sc, &freq); 3492 3493 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3494 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3495 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3496 3497 return bwi_regwin_switch(sc, old, NULL); 3498 } 3499 3500 static int 3501 bwi_bus_attach(struct bwi_softc *sc) 3502 { 3503 struct bwi_regwin *bus, *old; 3504 int error; 3505 3506 bus = &sc->sc_bus_regwin; 3507 3508 error = bwi_regwin_switch(sc, bus, &old); 3509 if (error) 3510 return error; 3511 3512 if (!bwi_regwin_is_enabled(sc, bus)) 3513 bwi_regwin_enable(sc, bus, 0); 3514 3515 /* Disable interripts */ 3516 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3517 3518 return bwi_regwin_switch(sc, old, NULL); 3519 } 3520 3521 static const char * 3522 bwi_regwin_name(const struct bwi_regwin *rw) 3523 { 3524 switch (rw->rw_type) { 3525 case BWI_REGWIN_T_COM: 3526 return "COM"; 3527 case BWI_REGWIN_T_BUSPCI: 3528 return "PCI"; 3529 case BWI_REGWIN_T_MAC: 3530 return "MAC"; 3531 case BWI_REGWIN_T_BUSPCIE: 3532 return "PCIE"; 3533 } 3534 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3535 return NULL; 3536 } 3537 3538 static uint32_t 3539 bwi_regwin_disable_bits(struct bwi_softc *sc) 3540 { 3541 uint32_t busrev; 3542 3543 /* XXX cache this */ 3544 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3545 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3546 "bus rev %u\n", busrev); 3547 3548 if (busrev == BWI_BUSREV_0) 3549 return BWI_STATE_LO_DISABLE1; 3550 else if (busrev == BWI_BUSREV_1) 3551 return BWI_STATE_LO_DISABLE2; 3552 else 3553 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3554 } 3555 3556 int 3557 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3558 { 3559 uint32_t val, disable_bits; 3560 3561 disable_bits = bwi_regwin_disable_bits(sc); 3562 val = CSR_READ_4(sc, BWI_STATE_LO); 3563 3564 if ((val & (BWI_STATE_LO_CLOCK | 3565 BWI_STATE_LO_RESET | 3566 disable_bits)) == BWI_STATE_LO_CLOCK) { 3567 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3568 bwi_regwin_name(rw)); 3569 return 1; 3570 } else { 3571 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3572 bwi_regwin_name(rw)); 3573 return 0; 3574 } 3575 } 3576 3577 void 3578 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3579 { 3580 uint32_t state_lo, disable_bits; 3581 int i; 3582 3583 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3584 3585 /* 3586 * If current regwin is in 'reset' state, it was already disabled. 3587 */ 3588 if (state_lo & BWI_STATE_LO_RESET) { 3589 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3590 "%s was already disabled\n", bwi_regwin_name(rw)); 3591 return; 3592 } 3593 3594 disable_bits = bwi_regwin_disable_bits(sc); 3595 3596 /* 3597 * Disable normal clock 3598 */ 3599 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3600 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3601 3602 /* 3603 * Wait until normal clock is disabled 3604 */ 3605 #define NRETRY 1000 3606 for (i = 0; i < NRETRY; ++i) { 3607 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3608 if (state_lo & disable_bits) 3609 break; 3610 DELAY(10); 3611 } 3612 if (i == NRETRY) { 3613 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3614 bwi_regwin_name(rw)); 3615 } 3616 3617 for (i = 0; i < NRETRY; ++i) { 3618 uint32_t state_hi; 3619 3620 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3621 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3622 break; 3623 DELAY(10); 3624 } 3625 if (i == NRETRY) { 3626 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3627 bwi_regwin_name(rw)); 3628 } 3629 #undef NRETRY 3630 3631 /* 3632 * Reset and disable regwin with gated clock 3633 */ 3634 state_lo = BWI_STATE_LO_RESET | disable_bits | 3635 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3636 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3637 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3638 3639 /* Flush pending bus write */ 3640 CSR_READ_4(sc, BWI_STATE_LO); 3641 DELAY(1); 3642 3643 /* Reset and disable regwin */ 3644 state_lo = BWI_STATE_LO_RESET | disable_bits | 3645 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3646 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3647 3648 /* Flush pending bus write */ 3649 CSR_READ_4(sc, BWI_STATE_LO); 3650 DELAY(1); 3651 } 3652 3653 void 3654 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3655 { 3656 uint32_t state_lo, state_hi, imstate; 3657 3658 bwi_regwin_disable(sc, rw, flags); 3659 3660 /* Reset regwin with gated clock */ 3661 state_lo = BWI_STATE_LO_RESET | 3662 BWI_STATE_LO_CLOCK | 3663 BWI_STATE_LO_GATED_CLOCK | 3664 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3665 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3666 3667 /* Flush pending bus write */ 3668 CSR_READ_4(sc, BWI_STATE_LO); 3669 DELAY(1); 3670 3671 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3672 if (state_hi & BWI_STATE_HI_SERROR) 3673 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3674 3675 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3676 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3677 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3678 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3679 } 3680 3681 /* Enable regwin with gated clock */ 3682 state_lo = BWI_STATE_LO_CLOCK | 3683 BWI_STATE_LO_GATED_CLOCK | 3684 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3685 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3686 3687 /* Flush pending bus write */ 3688 CSR_READ_4(sc, BWI_STATE_LO); 3689 DELAY(1); 3690 3691 /* Enable regwin with normal clock */ 3692 state_lo = BWI_STATE_LO_CLOCK | 3693 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3694 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3695 3696 /* Flush pending bus write */ 3697 CSR_READ_4(sc, BWI_STATE_LO); 3698 DELAY(1); 3699 } 3700 3701 static void 3702 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3703 { 3704 struct ifnet *ifp = sc->sc_ifp; 3705 struct bwi_mac *mac; 3706 struct bwi_myaddr_bssid buf; 3707 const uint8_t *p; 3708 uint32_t val; 3709 int n, i; 3710 3711 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3712 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3713 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3714 3715 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3716 3717 bcopy(IF_LLADDR(ifp), buf.myaddr, sizeof(buf.myaddr)); 3718 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3719 3720 n = sizeof(buf) / sizeof(val); 3721 p = (const uint8_t *)&buf; 3722 for (i = 0; i < n; ++i) { 3723 int j; 3724 3725 val = 0; 3726 for (j = 0; j < sizeof(val); ++j) 3727 val |= ((uint32_t)(*p++)) << (j * 8); 3728 3729 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3730 } 3731 } 3732 3733 static void 3734 bwi_updateslot(struct ifnet *ifp) 3735 { 3736 struct bwi_softc *sc = ifp->if_softc; 3737 struct ieee80211com *ic = ifp->if_l2com; 3738 struct bwi_mac *mac; 3739 3740 BWI_LOCK(sc); 3741 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3742 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3743 3744 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3745 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3746 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3747 3748 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3749 } 3750 BWI_UNLOCK(sc); 3751 } 3752 3753 static void 3754 bwi_calibrate(void *xsc) 3755 { 3756 struct bwi_softc *sc = xsc; 3757 #ifdef INVARIANTS 3758 struct ifnet *ifp = sc->sc_ifp; 3759 struct ieee80211com *ic = ifp->if_l2com; 3760 #endif 3761 struct bwi_mac *mac; 3762 3763 BWI_ASSERT_LOCKED(sc); 3764 3765 KASSERT(ic->ic_opmode != IEEE80211_M_MONITOR, 3766 ("opmode %d", ic->ic_opmode)); 3767 3768 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3769 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3770 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3771 3772 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3773 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3774 3775 /* XXX 15 seconds */ 3776 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3777 } 3778 3779 static int 3780 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3781 { 3782 struct bwi_mac *mac; 3783 3784 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3785 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3786 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3787 3788 return bwi_rf_calc_rssi(mac, hdr); 3789 } 3790 3791 static int 3792 bwi_calc_noise(struct bwi_softc *sc) 3793 { 3794 struct bwi_mac *mac; 3795 3796 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3797 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3798 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3799 3800 return bwi_rf_calc_noise(mac); 3801 } 3802 3803 static __inline uint8_t 3804 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type) 3805 { 3806 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK; 3807 return (ieee80211_plcp2rate(plcp, type)); 3808 } 3809 3810 static void 3811 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3812 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3813 { 3814 const struct ieee80211_frame_min *wh; 3815 3816 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3817 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3818 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3819 3820 wh = mtod(m, const struct ieee80211_frame_min *); 3821 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3822 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3823 3824 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */ 3825 sc->sc_rx_th.wr_rate = rate; 3826 sc->sc_rx_th.wr_antsignal = rssi; 3827 sc->sc_rx_th.wr_antnoise = noise; 3828 } 3829 3830 static void 3831 bwi_led_attach(struct bwi_softc *sc) 3832 { 3833 const uint8_t *led_act = NULL; 3834 uint16_t gpio, val[BWI_LED_MAX]; 3835 int i; 3836 3837 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 3838 3839 for (i = 0; i < N(bwi_vendor_led_act); ++i) { 3840 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3841 led_act = bwi_vendor_led_act[i].led_act; 3842 break; 3843 } 3844 } 3845 if (led_act == NULL) 3846 led_act = bwi_default_led_act; 3847 3848 #undef N 3849 3850 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3851 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3852 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3853 3854 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3855 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3856 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3857 3858 for (i = 0; i < BWI_LED_MAX; ++i) { 3859 struct bwi_led *led = &sc->sc_leds[i]; 3860 3861 if (val[i] == 0xff) { 3862 led->l_act = led_act[i]; 3863 } else { 3864 if (val[i] & BWI_LED_ACT_LOW) 3865 led->l_flags |= BWI_LED_F_ACTLOW; 3866 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3867 } 3868 led->l_mask = (1 << i); 3869 3870 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3871 led->l_act == BWI_LED_ACT_BLINK_POLL || 3872 led->l_act == BWI_LED_ACT_BLINK) { 3873 led->l_flags |= BWI_LED_F_BLINK; 3874 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3875 led->l_flags |= BWI_LED_F_POLLABLE; 3876 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3877 led->l_flags |= BWI_LED_F_SLOW; 3878 3879 if (sc->sc_blink_led == NULL) { 3880 sc->sc_blink_led = led; 3881 if (led->l_flags & BWI_LED_F_SLOW) 3882 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3883 } 3884 } 3885 3886 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3887 "%dth led, act %d, lowact %d\n", i, 3888 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3889 } 3890 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3891 } 3892 3893 static __inline uint16_t 3894 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3895 { 3896 if (led->l_flags & BWI_LED_F_ACTLOW) 3897 on = !on; 3898 if (on) 3899 val |= led->l_mask; 3900 else 3901 val &= ~led->l_mask; 3902 return val; 3903 } 3904 3905 static void 3906 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3907 { 3908 struct ifnet *ifp = sc->sc_ifp; 3909 struct ieee80211com *ic = ifp->if_l2com; 3910 uint16_t val; 3911 int i; 3912 3913 if (nstate == IEEE80211_S_INIT) { 3914 callout_stop(&sc->sc_led_blink_ch); 3915 sc->sc_led_blinking = 0; 3916 } 3917 3918 if ((ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3919 return; 3920 3921 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3922 for (i = 0; i < BWI_LED_MAX; ++i) { 3923 struct bwi_led *led = &sc->sc_leds[i]; 3924 int on; 3925 3926 if (led->l_act == BWI_LED_ACT_UNKN || 3927 led->l_act == BWI_LED_ACT_NULL) 3928 continue; 3929 3930 if ((led->l_flags & BWI_LED_F_BLINK) && 3931 nstate != IEEE80211_S_INIT) 3932 continue; 3933 3934 switch (led->l_act) { 3935 case BWI_LED_ACT_ON: /* Always on */ 3936 on = 1; 3937 break; 3938 case BWI_LED_ACT_OFF: /* Always off */ 3939 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3940 on = 0; 3941 break; 3942 default: 3943 on = 1; 3944 switch (nstate) { 3945 case IEEE80211_S_INIT: 3946 on = 0; 3947 break; 3948 case IEEE80211_S_RUN: 3949 if (led->l_act == BWI_LED_ACT_11G && 3950 ic->ic_curmode != IEEE80211_MODE_11G) 3951 on = 0; 3952 break; 3953 default: 3954 if (led->l_act == BWI_LED_ACT_ASSOC) 3955 on = 0; 3956 break; 3957 } 3958 break; 3959 } 3960 3961 val = bwi_led_onoff(led, val, on); 3962 } 3963 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3964 } 3965 static void 3966 bwi_led_event(struct bwi_softc *sc, int event) 3967 { 3968 struct bwi_led *led = sc->sc_blink_led; 3969 int rate; 3970 3971 if (event == BWI_LED_EVENT_POLL) { 3972 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3973 return; 3974 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3975 return; 3976 } 3977 3978 sc->sc_led_ticks = ticks; 3979 if (sc->sc_led_blinking) 3980 return; 3981 3982 switch (event) { 3983 case BWI_LED_EVENT_RX: 3984 rate = sc->sc_rx_rate; 3985 break; 3986 case BWI_LED_EVENT_TX: 3987 rate = sc->sc_tx_rate; 3988 break; 3989 case BWI_LED_EVENT_POLL: 3990 rate = 0; 3991 break; 3992 default: 3993 panic("unknown LED event %d\n", event); 3994 break; 3995 } 3996 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 3997 bwi_led_duration[rate].off_dur); 3998 } 3999 4000 static void 4001 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 4002 { 4003 struct bwi_led *led = sc->sc_blink_led; 4004 uint16_t val; 4005 4006 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4007 val = bwi_led_onoff(led, val, 1); 4008 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4009 4010 if (led->l_flags & BWI_LED_F_SLOW) { 4011 BWI_LED_SLOWDOWN(on_dur); 4012 BWI_LED_SLOWDOWN(off_dur); 4013 } 4014 4015 sc->sc_led_blinking = 1; 4016 sc->sc_led_blink_offdur = off_dur; 4017 4018 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 4019 } 4020 4021 static void 4022 bwi_led_blink_next(void *xsc) 4023 { 4024 struct bwi_softc *sc = xsc; 4025 uint16_t val; 4026 4027 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4028 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 4029 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4030 4031 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 4032 bwi_led_blink_end, sc); 4033 } 4034 4035 static void 4036 bwi_led_blink_end(void *xsc) 4037 { 4038 struct bwi_softc *sc = xsc; 4039 sc->sc_led_blinking = 0; 4040 } 4041 4042 static void 4043 bwi_restart(void *xsc, int pending) 4044 { 4045 struct bwi_softc *sc = xsc; 4046 struct ifnet *ifp = sc->sc_ifp; 4047 4048 if_printf(ifp, "%s begin, help!\n", __func__); 4049 BWI_LOCK(sc); 4050 bwi_init_statechg(xsc, 0); 4051 #if 0 4052 bwi_start_locked(ifp); 4053 #endif 4054 BWI_UNLOCK(sc); 4055 }
Cache object: e3f9f4b63cd1bca542c2d9af8a18ab7e
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