The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/bxe/ecore_init_ops.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause
    3  *
    4  * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  *
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
   20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   26  * THE POSSIBILITY OF SUCH DAMAGE.
   27  */
   28 
   29 #include <sys/cdefs.h>
   30 __FBSDID("$FreeBSD$");
   31 
   32 #ifndef ECORE_INIT_OPS_H
   33 #define ECORE_INIT_OPS_H
   34 
   35 
   36 
   37 
   38 
   39 
   40 
   41 
   42 
   43 
   44 static int ecore_gunzip(struct bxe_softc *sc, const uint8_t *zbuf, int len);
   45 static void ecore_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, uint32_t val);
   46 static void ecore_write_dmae_phys_len(struct bxe_softc *sc,
   47                                       ecore_dma_addr_t phys_addr, uint32_t addr,
   48                                       uint32_t len);
   49 
   50 static void ecore_init_str_wr(struct bxe_softc *sc, uint32_t addr,
   51                               const uint32_t *data, uint32_t len)
   52 {
   53         uint32_t i;
   54 
   55         for (i = 0; i < len; i++)
   56                 REG_WR(sc, addr + i*4, data[i]);
   57 }
   58 
   59 static void ecore_init_ind_wr(struct bxe_softc *sc, uint32_t addr,
   60                               const uint32_t *data, uint32_t len)
   61 {
   62         uint32_t i;
   63 
   64         for (i = 0; i < len; i++)
   65                 ecore_reg_wr_ind(sc, addr + i*4, data[i]);
   66 }
   67 
   68 static void ecore_write_big_buf(struct bxe_softc *sc, uint32_t addr, uint32_t len,
   69                                 uint8_t wb)
   70 {
   71         if (DMAE_READY(sc))
   72                 ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
   73 
   74         /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
   75         else if (wb && CHIP_IS_E1(sc))
   76                 ecore_init_ind_wr(sc, addr, GUNZIP_BUF(sc), len);
   77 
   78         /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
   79         else
   80                 ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
   81 }
   82 
   83 static void ecore_init_fill(struct bxe_softc *sc, uint32_t addr, int fill,
   84                             uint32_t len, uint8_t wb)
   85 {
   86         uint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
   87         uint32_t buf_len32 = buf_len/4;
   88         uint32_t i;
   89 
   90         ECORE_MEMSET(GUNZIP_BUF(sc), (uint8_t)fill, buf_len);
   91 
   92         for (i = 0; i < len; i += buf_len32) {
   93                 uint32_t cur_len = min(buf_len32, len - i);
   94 
   95                 ecore_write_big_buf(sc, addr + i*4, cur_len, wb);
   96         }
   97 }
   98 
   99 static void ecore_write_big_buf_wb(struct bxe_softc *sc, uint32_t addr, uint32_t len)
  100 {
  101         if (DMAE_READY(sc))
  102                 ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
  103 
  104         /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
  105         else if (CHIP_IS_E1(sc))
  106                 ecore_init_ind_wr(sc, addr, GUNZIP_BUF(sc), len);
  107 
  108         /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
  109         else
  110                 ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
  111 }
  112 
  113 static void ecore_init_wr_64(struct bxe_softc *sc, uint32_t addr,
  114                              const uint32_t *data, uint32_t len64)
  115 {
  116         uint32_t buf_len32 = FW_BUF_SIZE/4;
  117         uint32_t len = len64*2;
  118         uint64_t data64 = 0;
  119         uint32_t i;
  120 
  121         /* 64 bit value is in a blob: first low DWORD, then high DWORD */
  122         data64 = HILO_U64((*(data + 1)), (*data));
  123 
  124         len64 = min((uint32_t)(FW_BUF_SIZE/8), len64);
  125         for (i = 0; i < len64; i++) {
  126                 uint64_t *pdata = ((uint64_t *)(GUNZIP_BUF(sc))) + i;
  127 
  128                 *pdata = data64;
  129         }
  130 
  131         for (i = 0; i < len; i += buf_len32) {
  132                 uint32_t cur_len = min(buf_len32, len - i);
  133 
  134                 ecore_write_big_buf_wb(sc, addr + i*4, cur_len);
  135         }
  136 }
  137 
  138 /*********************************************************
  139    There are different blobs for each PRAM section.
  140    In addition, each blob write operation is divided into a few operations
  141    in order to decrease the amount of phys. contiguous buffer needed.
  142    Thus, when we select a blob the address may be with some offset
  143    from the beginning of PRAM section.
  144    The same holds for the INT_TABLE sections.
  145 **********************************************************/
  146 #define IF_IS_INT_TABLE_ADDR(base, addr) \
  147                         if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
  148 
  149 #define IF_IS_PRAM_ADDR(base, addr) \
  150                         if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
  151 
  152 static const uint8_t *ecore_sel_blob(struct bxe_softc *sc, uint32_t addr,
  153                                 const uint8_t *data)
  154 {
  155         IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
  156                 data = INIT_TSEM_INT_TABLE_DATA(sc);
  157         else
  158                 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
  159                         data = INIT_CSEM_INT_TABLE_DATA(sc);
  160         else
  161                 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
  162                         data = INIT_USEM_INT_TABLE_DATA(sc);
  163         else
  164                 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
  165                         data = INIT_XSEM_INT_TABLE_DATA(sc);
  166         else
  167                 IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
  168                         data = INIT_TSEM_PRAM_DATA(sc);
  169         else
  170                 IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
  171                         data = INIT_CSEM_PRAM_DATA(sc);
  172         else
  173                 IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
  174                         data = INIT_USEM_PRAM_DATA(sc);
  175         else
  176                 IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
  177                         data = INIT_XSEM_PRAM_DATA(sc);
  178 
  179         return data;
  180 }
  181 
  182 static void ecore_init_wr_wb(struct bxe_softc *sc, uint32_t addr,
  183                              const uint32_t *data, uint32_t len)
  184 {
  185         if (DMAE_READY(sc))
  186                 VIRT_WR_DMAE_LEN(sc, data, addr, len, 0);
  187 
  188         /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
  189         else if (CHIP_IS_E1(sc))
  190                 ecore_init_ind_wr(sc, addr, data, len);
  191 
  192         /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
  193         else
  194                 ecore_init_str_wr(sc, addr, data, len);
  195 }
  196 
  197 #ifndef FW_ZIP_SUPPORT
  198 static void ecore_init_fw(struct bxe_softc *sc, uint32_t addr, uint32_t len)
  199 {
  200         const uint8_t *data = NULL;
  201 
  202         data = ecore_sel_blob(sc, addr, (const uint8_t *)data);
  203 
  204         if (DMAE_READY(sc))
  205                 VIRT_WR_DMAE_LEN(sc, data, addr, len, 1);
  206 
  207         /* in E1 BIOS initiated ZLR may interrupt widebus writes */
  208         else if (CHIP_IS_E1(sc))
  209                 ecore_init_ind_wr(sc, addr, (const uint32_t *)data, len);
  210 
  211         /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
  212         else
  213                 ecore_init_str_wr(sc, addr, (const uint32_t *)data, len);
  214 }
  215 
  216 #endif
  217 
  218 static void ecore_wr_64(struct bxe_softc *sc, uint32_t reg, uint32_t val_lo,
  219                         uint32_t val_hi)
  220 {
  221         uint32_t wb_write[2];
  222 
  223         wb_write[0] = val_lo;
  224         wb_write[1] = val_hi;
  225         REG_WR_DMAE_LEN(sc, reg, wb_write, 2);
  226 }
  227 
  228 static void ecore_init_wr_zp(struct bxe_softc *sc, uint32_t addr, uint32_t len,
  229                              uint32_t blob_off)
  230 {
  231         const uint8_t *data = NULL;
  232         int rc;
  233         uint32_t i;
  234 
  235         data = ecore_sel_blob(sc, addr, data) + blob_off*4;
  236 
  237         rc = ecore_gunzip(sc, data, len);
  238         if (rc)
  239                 return;
  240 
  241         /* gunzip_outlen is in dwords */
  242         len = GUNZIP_OUTLEN(sc);
  243         for (i = 0; i < len; i++)
  244                 ((uint32_t *)GUNZIP_BUF(sc))[i] = (uint32_t)
  245                                 ECORE_CPU_TO_LE32(((uint32_t *)GUNZIP_BUF(sc))[i]);
  246 
  247         ecore_write_big_buf_wb(sc, addr, len);
  248 }
  249 
  250 static void ecore_init_block(struct bxe_softc *sc, uint32_t block, uint32_t stage)
  251 {
  252         uint16_t op_start =
  253                 INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,
  254                                                      STAGE_START)];
  255         uint16_t op_end =
  256                 INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,
  257                                                      STAGE_END)];
  258         const union init_op *op;
  259         uint32_t op_idx, op_type, addr, len;
  260         const uint32_t *data, *data_base;
  261 
  262         /* If empty block */
  263         if (op_start == op_end)
  264                 return;
  265 
  266         data_base = INIT_DATA(sc);
  267 
  268         for (op_idx = op_start; op_idx < op_end; op_idx++) {
  269 
  270                 op = (const union init_op *)&(INIT_OPS(sc)[op_idx]);
  271                 /* Get generic data */
  272                 op_type = op->raw.op;
  273                 addr = op->raw.offset;
  274                 /* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and
  275                  * OP_WR64 (we assume that op_arr_write and op_write have the
  276                  * same structure).
  277                  */
  278                 len = op->arr_wr.data_len;
  279                 data = data_base + op->arr_wr.data_off;
  280 
  281                 switch (op_type) {
  282                 case OP_RD:
  283                         REG_RD(sc, addr);
  284                         break;
  285                 case OP_WR:
  286                         REG_WR(sc, addr, op->write.val);
  287                         break;
  288                 case OP_SW:
  289                         ecore_init_str_wr(sc, addr, data, len);
  290                         break;
  291                 case OP_WB:
  292                         ecore_init_wr_wb(sc, addr, data, len);
  293                         break;
  294 #ifndef FW_ZIP_SUPPORT
  295                 case OP_FW:
  296                         ecore_init_fw(sc, addr, len);
  297                         break;
  298 #endif
  299                 case OP_ZR:
  300                         ecore_init_fill(sc, addr, 0, op->zero.len, 0);
  301                         break;
  302                 case OP_WB_ZR:
  303                         ecore_init_fill(sc, addr, 0, op->zero.len, 1);
  304                         break;
  305                 case OP_ZP:
  306                         ecore_init_wr_zp(sc, addr, len,
  307                                          op->arr_wr.data_off);
  308                         break;
  309                 case OP_WR_64:
  310                         ecore_init_wr_64(sc, addr, data, len);
  311                         break;
  312                 case OP_IF_MODE_AND:
  313                         /* if any of the flags doesn't match, skip the
  314                          * conditional block.
  315                          */
  316                         if ((INIT_MODE_FLAGS(sc) &
  317                                 op->if_mode.mode_bit_map) !=
  318                                 op->if_mode.mode_bit_map)
  319                                 op_idx += op->if_mode.cmd_offset;
  320                         break;
  321                 case OP_IF_MODE_OR:
  322                         /* if all the flags don't match, skip the conditional
  323                          * block.
  324                          */
  325                         if ((INIT_MODE_FLAGS(sc) &
  326                                 op->if_mode.mode_bit_map) == 0)
  327                                 op_idx += op->if_mode.cmd_offset;
  328                         break;
  329                     /* the following opcodes are unused at the moment. */
  330                 case OP_IF_PHASE:
  331                 case OP_RT:
  332                 case OP_DELAY:
  333                 case OP_VERIFY:
  334                 default:
  335                         /* Should never get here! */
  336 
  337                         break;
  338                 }
  339         }
  340 }
  341 
  342 
  343 /****************************************************************************
  344 * PXP Arbiter
  345 ****************************************************************************/
  346 /*
  347  * This code configures the PCI read/write arbiter
  348  * which implements a weighted round robin
  349  * between the virtual queues in the chip.
  350  *
  351  * The values were derived for each PCI max payload and max request size.
  352  * since max payload and max request size are only known at run time,
  353  * this is done as a separate init stage.
  354  */
  355 
  356 #define NUM_WR_Q                        13
  357 #define NUM_RD_Q                        29
  358 #define MAX_RD_ORD                      3
  359 #define MAX_WR_ORD                      2
  360 
  361 /* configuration for one arbiter queue */
  362 struct arb_line {
  363         int l;
  364         int add;
  365         int ubound;
  366 };
  367 
  368 /* derived configuration for each read queue for each max request size */
  369 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
  370 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
  371         { {4, 8,  4},  {4,  8,  4},  {4,  8,  4},  {4,  8,  4}  },
  372         { {4, 3,  3},  {4,  3,  3},  {4,  3,  3},  {4,  3,  3}  },
  373         { {8, 3,  6},  {16, 3,  11}, {16, 3,  11}, {16, 3,  11} },
  374         { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
  375         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
  376         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
  377         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
  378         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
  379 /* 10 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  380         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  381         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  382         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  383         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  384         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  385         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  386         { {8, 64, 6},  {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
  387         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  388         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  389 /* 20 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  390         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  391         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  392         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  393         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  394         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  395         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  396         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  397         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
  398         { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
  399 };
  400 
  401 /* derived configuration for each write queue for each max request size */
  402 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
  403 /* 1 */ { {4, 6,  3},  {4,  6,  3},  {4,  6,  3} },
  404         { {4, 2,  3},  {4,  2,  3},  {4,  2,  3} },
  405         { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
  406         { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
  407         { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
  408         { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
  409         { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
  410         { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
  411         { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
  412 /* 10 */{ {8, 9,  6},  {16, 9,  11}, {32, 9,  21} },
  413         { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
  414         { {8, 9,  6},  {16, 9,  11}, {16, 9,  11} },
  415         { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
  416 };
  417 
  418 /* register addresses for read queues */
  419 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
  420 /* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
  421                 PXP2_REG_RQ_BW_RD_UBOUND0},
  422         {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
  423                 PXP2_REG_PSWRQ_BW_UB1},
  424         {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
  425                 PXP2_REG_PSWRQ_BW_UB2},
  426         {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
  427                 PXP2_REG_PSWRQ_BW_UB3},
  428         {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
  429                 PXP2_REG_RQ_BW_RD_UBOUND4},
  430         {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
  431                 PXP2_REG_RQ_BW_RD_UBOUND5},
  432         {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
  433                 PXP2_REG_PSWRQ_BW_UB6},
  434         {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
  435                 PXP2_REG_PSWRQ_BW_UB7},
  436         {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
  437                 PXP2_REG_PSWRQ_BW_UB8},
  438 /* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
  439                 PXP2_REG_PSWRQ_BW_UB9},
  440         {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
  441                 PXP2_REG_PSWRQ_BW_UB10},
  442         {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
  443                 PXP2_REG_PSWRQ_BW_UB11},
  444         {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
  445                 PXP2_REG_RQ_BW_RD_UBOUND12},
  446         {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
  447                 PXP2_REG_RQ_BW_RD_UBOUND13},
  448         {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
  449                 PXP2_REG_RQ_BW_RD_UBOUND14},
  450         {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
  451                 PXP2_REG_RQ_BW_RD_UBOUND15},
  452         {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
  453                 PXP2_REG_RQ_BW_RD_UBOUND16},
  454         {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
  455                 PXP2_REG_RQ_BW_RD_UBOUND17},
  456         {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
  457                 PXP2_REG_RQ_BW_RD_UBOUND18},
  458 /* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
  459                 PXP2_REG_RQ_BW_RD_UBOUND19},
  460         {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
  461                 PXP2_REG_RQ_BW_RD_UBOUND20},
  462         {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
  463                 PXP2_REG_RQ_BW_RD_UBOUND22},
  464         {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
  465                 PXP2_REG_RQ_BW_RD_UBOUND23},
  466         {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
  467                 PXP2_REG_RQ_BW_RD_UBOUND24},
  468         {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
  469                 PXP2_REG_RQ_BW_RD_UBOUND25},
  470         {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
  471                 PXP2_REG_RQ_BW_RD_UBOUND26},
  472         {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
  473                 PXP2_REG_RQ_BW_RD_UBOUND27},
  474         {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
  475                 PXP2_REG_PSWRQ_BW_UB28}
  476 };
  477 
  478 /* register addresses for write queues */
  479 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
  480 /* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
  481                 PXP2_REG_PSWRQ_BW_UB1},
  482         {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
  483                 PXP2_REG_PSWRQ_BW_UB2},
  484         {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
  485                 PXP2_REG_PSWRQ_BW_UB3},
  486         {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
  487                 PXP2_REG_PSWRQ_BW_UB6},
  488         {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
  489                 PXP2_REG_PSWRQ_BW_UB7},
  490         {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
  491                 PXP2_REG_PSWRQ_BW_UB8},
  492         {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
  493                 PXP2_REG_PSWRQ_BW_UB9},
  494         {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
  495                 PXP2_REG_PSWRQ_BW_UB10},
  496         {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
  497                 PXP2_REG_PSWRQ_BW_UB11},
  498 /* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
  499                 PXP2_REG_PSWRQ_BW_UB28},
  500         {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
  501                 PXP2_REG_RQ_BW_WR_UBOUND29},
  502         {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
  503                 PXP2_REG_RQ_BW_WR_UBOUND30}
  504 };
  505 
  506 static void ecore_init_pxp_arb(struct bxe_softc *sc, int r_order,
  507                                int w_order)
  508 {
  509         uint32_t val, i;
  510 
  511         if (r_order > MAX_RD_ORD) {
  512                 ECORE_MSG(sc, "read order of %d  order adjusted to %d\n",
  513                            r_order, MAX_RD_ORD);
  514                 r_order = MAX_RD_ORD;
  515         }
  516         if (w_order > MAX_WR_ORD) {
  517                 ECORE_MSG(sc, "write order of %d  order adjusted to %d\n",
  518                            w_order, MAX_WR_ORD);
  519                 w_order = MAX_WR_ORD;
  520         }
  521         if (CHIP_REV_IS_FPGA(sc)) {
  522                 ECORE_MSG(sc, "write order adjusted to 1 for FPGA\n");
  523                 w_order = 0;
  524         }
  525         ECORE_MSG(sc, "read order %d  write order %d\n", r_order, w_order);
  526 
  527         for (i = 0; i < NUM_RD_Q-1; i++) {
  528                 REG_WR(sc, read_arb_addr[i].l, read_arb_data[i][r_order].l);
  529                 REG_WR(sc, read_arb_addr[i].add,
  530                        read_arb_data[i][r_order].add);
  531                 REG_WR(sc, read_arb_addr[i].ubound,
  532                        read_arb_data[i][r_order].ubound);
  533         }
  534 
  535         for (i = 0; i < NUM_WR_Q-1; i++) {
  536                 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
  537                     (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
  538 
  539                         REG_WR(sc, write_arb_addr[i].l,
  540                                write_arb_data[i][w_order].l);
  541 
  542                         REG_WR(sc, write_arb_addr[i].add,
  543                                write_arb_data[i][w_order].add);
  544 
  545                         REG_WR(sc, write_arb_addr[i].ubound,
  546                                write_arb_data[i][w_order].ubound);
  547                 } else {
  548 
  549                         val = REG_RD(sc, write_arb_addr[i].l);
  550                         REG_WR(sc, write_arb_addr[i].l,
  551                                val | (write_arb_data[i][w_order].l << 10));
  552 
  553                         val = REG_RD(sc, write_arb_addr[i].add);
  554                         REG_WR(sc, write_arb_addr[i].add,
  555                                val | (write_arb_data[i][w_order].add << 10));
  556 
  557                         val = REG_RD(sc, write_arb_addr[i].ubound);
  558                         REG_WR(sc, write_arb_addr[i].ubound,
  559                                val | (write_arb_data[i][w_order].ubound << 7));
  560                 }
  561         }
  562 
  563         val =  write_arb_data[NUM_WR_Q-1][w_order].add;
  564         val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
  565         val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
  566         REG_WR(sc, PXP2_REG_PSWRQ_BW_RD, val);
  567 
  568         val =  read_arb_data[NUM_RD_Q-1][r_order].add;
  569         val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
  570         val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
  571         REG_WR(sc, PXP2_REG_PSWRQ_BW_WR, val);
  572 
  573         REG_WR(sc, PXP2_REG_RQ_WR_MBS0, w_order);
  574         REG_WR(sc, PXP2_REG_RQ_WR_MBS1, w_order);
  575         REG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order);
  576         REG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order);
  577 
  578         if ((CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) && (r_order == MAX_RD_ORD))
  579                 REG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
  580 
  581         if (CHIP_IS_E3(sc))
  582                 REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order));
  583         else if (CHIP_IS_E2(sc))
  584                 REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));
  585         else
  586                 REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
  587 
  588         if (!CHIP_IS_E1(sc)) {
  589                 /*    MPS      w_order     optimal TH      presently TH
  590                  *    128         0             0               2
  591                  *    256         1             1               3
  592                  *    >=512       2             2               3
  593                  */
  594                 /* DMAE is special */
  595                 if (!CHIP_IS_E1H(sc)) {
  596                         /* E2 can use optimal TH */
  597                         val = w_order;
  598                         REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);
  599                 } else {
  600                         val = ((w_order == 0) ? 2 : 3);
  601                         REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);
  602                 }
  603 
  604                 REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
  605                 REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
  606                 REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
  607                 REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
  608                 REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
  609                 REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
  610                 REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
  611                 REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
  612                 REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
  613                 REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
  614         }
  615 
  616         /* Validate number of tags suppoted by device */
  617 #define PCIE_REG_PCIER_TL_HDR_FC_ST             0x2980
  618         val = REG_RD(sc, PCIE_REG_PCIER_TL_HDR_FC_ST);
  619         val &= 0xFF;
  620         if (val <= 0x20)
  621                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x20);
  622 }
  623 
  624 /****************************************************************************
  625 * ILT management
  626 ****************************************************************************/
  627 /*
  628  * This codes hides the low level HW interaction for ILT management and
  629  * configuration. The API consists of a shadow ILT table which is set by the
  630  * driver and a set of routines to use it to configure the HW.
  631  *
  632  */
  633 
  634 /* ILT HW init operations */
  635 
  636 /* ILT memory management operations */
  637 #define ILT_MEMOP_ALLOC         0
  638 #define ILT_MEMOP_FREE          1
  639 
  640 /* the phys address is shifted right 12 bits and has an added
  641  * 1=valid bit added to the 53rd bit
  642  * then since this is a wide register(TM)
  643  * we split it into two 32 bit writes
  644  */
  645 #define ILT_ADDR1(x)            ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
  646 #define ILT_ADDR2(x)            ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
  647 #define ILT_RANGE(f, l)         (((l) << 10) | f)
  648 
  649 static int ecore_ilt_line_mem_op(struct bxe_softc *sc,
  650                                  struct ilt_line *line, uint32_t size, uint8_t memop)
  651 {
  652         if (memop == ILT_MEMOP_FREE) {
  653                 ECORE_ILT_FREE(line->page, line->page_mapping, line->size);
  654                 return 0;
  655         }
  656         ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size);
  657         if (!line->page)
  658                 return -1;
  659         line->size = size;
  660         return 0;
  661 }
  662 
  663 
  664 static int ecore_ilt_client_mem_op(struct bxe_softc *sc, int cli_num,
  665                                    uint8_t memop)
  666 {
  667         int i, rc;
  668         struct ecore_ilt *ilt = SC_ILT(sc);
  669         struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
  670 
  671         if (!ilt || !ilt->lines)
  672                 return -1;
  673 
  674         if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
  675                 return 0;
  676 
  677         for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
  678                 rc = ecore_ilt_line_mem_op(sc, &ilt->lines[i],
  679                                            ilt_cli->page_size, memop);
  680         }
  681         return rc;
  682 }
  683 
  684 static inline int ecore_ilt_mem_op_cnic(struct bxe_softc *sc, uint8_t memop)
  685 {
  686         int rc = 0;
  687 
  688         if (CONFIGURE_NIC_MODE(sc))
  689                 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);
  690         if (!rc)
  691                 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_TM, memop);
  692 
  693         return rc;
  694 }
  695 
  696 static int ecore_ilt_mem_op(struct bxe_softc *sc, uint8_t memop)
  697 {
  698         int rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_CDU, memop);
  699         if (!rc)
  700                 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_QM, memop);
  701         if (!rc && CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc))
  702                 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);
  703 
  704         return rc;
  705 }
  706 
  707 static void ecore_ilt_line_wr(struct bxe_softc *sc, int abs_idx,
  708                               ecore_dma_addr_t page_mapping)
  709 {
  710         uint32_t reg;
  711 
  712         if (CHIP_IS_E1(sc))
  713                 reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;
  714         else
  715                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
  716 
  717         ecore_wr_64(sc, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
  718 }
  719 
  720 static void ecore_ilt_line_init_op(struct bxe_softc *sc,
  721                                    struct ecore_ilt *ilt, int idx, uint8_t initop)
  722 {
  723         ecore_dma_addr_t        null_mapping;
  724         int abs_idx = ilt->start_line + idx;
  725 
  726 
  727         switch (initop) {
  728         case INITOP_INIT:
  729                 /* set in the init-value array */
  730         case INITOP_SET:
  731                 ecore_ilt_line_wr(sc, abs_idx, ilt->lines[idx].page_mapping);
  732                 break;
  733         case INITOP_CLEAR:
  734                 null_mapping = 0;
  735                 ecore_ilt_line_wr(sc, abs_idx, null_mapping);
  736                 break;
  737         }
  738 }
  739 
  740 static void ecore_ilt_boundry_init_op(struct bxe_softc *sc,
  741                                       struct ilt_client_info *ilt_cli,
  742                                       uint32_t ilt_start, uint8_t initop)
  743 {
  744         uint32_t start_reg = 0;
  745         uint32_t end_reg = 0;
  746 
  747         /* The boundary is either SET or INIT,
  748            CLEAR => SET and for now SET ~~ INIT */
  749 
  750         /* find the appropriate regs */
  751         if (CHIP_IS_E1(sc)) {
  752                 switch (ilt_cli->client_num) {
  753                 case ILT_CLIENT_CDU:
  754                         start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
  755                         break;
  756                 case ILT_CLIENT_QM:
  757                         start_reg = PXP2_REG_PSWRQ_QM0_L2P;
  758                         break;
  759                 case ILT_CLIENT_SRC:
  760                         start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
  761                         break;
  762                 case ILT_CLIENT_TM:
  763                         start_reg = PXP2_REG_PSWRQ_TM0_L2P;
  764                         break;
  765                 }
  766                 REG_WR(sc, start_reg + SC_FUNC(sc)*4,
  767                        ILT_RANGE((ilt_start + ilt_cli->start),
  768                                  (ilt_start + ilt_cli->end)));
  769         } else {
  770                 switch (ilt_cli->client_num) {
  771                 case ILT_CLIENT_CDU:
  772                         start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
  773                         end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
  774                         break;
  775                 case ILT_CLIENT_QM:
  776                         start_reg = PXP2_REG_RQ_QM_FIRST_ILT;
  777                         end_reg = PXP2_REG_RQ_QM_LAST_ILT;
  778                         break;
  779                 case ILT_CLIENT_SRC:
  780                         start_reg = PXP2_REG_RQ_SRC_FIRST_ILT;
  781                         end_reg = PXP2_REG_RQ_SRC_LAST_ILT;
  782                         break;
  783                 case ILT_CLIENT_TM:
  784                         start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
  785                         end_reg = PXP2_REG_RQ_TM_LAST_ILT;
  786                         break;
  787                 }
  788                 REG_WR(sc, start_reg, (ilt_start + ilt_cli->start));
  789                 REG_WR(sc, end_reg, (ilt_start + ilt_cli->end));
  790         }
  791 }
  792 
  793 static void ecore_ilt_client_init_op_ilt(struct bxe_softc *sc,
  794                                          struct ecore_ilt *ilt,
  795                                          struct ilt_client_info *ilt_cli,
  796                                          uint8_t initop)
  797 {
  798         int i;
  799 
  800         if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
  801                 return;
  802 
  803         for (i = ilt_cli->start; i <= ilt_cli->end; i++)
  804                 ecore_ilt_line_init_op(sc, ilt, i, initop);
  805 
  806         /* init/clear the ILT boundries */
  807         ecore_ilt_boundry_init_op(sc, ilt_cli, ilt->start_line, initop);
  808 }
  809 
  810 static void ecore_ilt_client_init_op(struct bxe_softc *sc,
  811                                      struct ilt_client_info *ilt_cli, uint8_t initop)
  812 {
  813         struct ecore_ilt *ilt = SC_ILT(sc);
  814 
  815         ecore_ilt_client_init_op_ilt(sc, ilt, ilt_cli, initop);
  816 }
  817 
  818 static void ecore_ilt_client_id_init_op(struct bxe_softc *sc,
  819                                         int cli_num, uint8_t initop)
  820 {
  821         struct ecore_ilt *ilt = SC_ILT(sc);
  822         struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
  823 
  824         ecore_ilt_client_init_op(sc, ilt_cli, initop);
  825 }
  826 
  827 static inline void ecore_ilt_init_op_cnic(struct bxe_softc *sc, uint8_t initop)
  828 {
  829         if (CONFIGURE_NIC_MODE(sc))
  830                 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);
  831         ecore_ilt_client_id_init_op(sc, ILT_CLIENT_TM, initop);
  832 }
  833 
  834 static void ecore_ilt_init_op(struct bxe_softc *sc, uint8_t initop)
  835 {
  836         ecore_ilt_client_id_init_op(sc, ILT_CLIENT_CDU, initop);
  837         ecore_ilt_client_id_init_op(sc, ILT_CLIENT_QM, initop);
  838         if (CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc))
  839                 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);
  840 }
  841 
  842 static void ecore_ilt_init_client_psz(struct bxe_softc *sc, int cli_num,
  843                                       uint32_t psz_reg, uint8_t initop)
  844 {
  845         struct ecore_ilt *ilt = SC_ILT(sc);
  846         struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
  847 
  848         if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
  849                 return;
  850 
  851         switch (initop) {
  852         case INITOP_INIT:
  853                 /* set in the init-value array */
  854         case INITOP_SET:
  855                 REG_WR(sc, psz_reg, ILOG2(ilt_cli->page_size >> 12));
  856                 break;
  857         case INITOP_CLEAR:
  858                 break;
  859         }
  860 }
  861 
  862 /*
  863  * called during init common stage, ilt clients should be initialized
  864  * prioir to calling this function
  865  */
  866 static void ecore_ilt_init_page_size(struct bxe_softc *sc, uint8_t initop)
  867 {
  868         ecore_ilt_init_client_psz(sc, ILT_CLIENT_CDU,
  869                                   PXP2_REG_RQ_CDU_P_SIZE, initop);
  870         ecore_ilt_init_client_psz(sc, ILT_CLIENT_QM,
  871                                   PXP2_REG_RQ_QM_P_SIZE, initop);
  872         ecore_ilt_init_client_psz(sc, ILT_CLIENT_SRC,
  873                                   PXP2_REG_RQ_SRC_P_SIZE, initop);
  874         ecore_ilt_init_client_psz(sc, ILT_CLIENT_TM,
  875                                   PXP2_REG_RQ_TM_P_SIZE, initop);
  876 }
  877 
  878 /****************************************************************************
  879 * QM initializations
  880 ****************************************************************************/
  881 #define QM_QUEUES_PER_FUNC      16 /* E1 has 32, but only 16 are used */
  882 #define QM_INIT_MIN_CID_COUNT   31
  883 #define QM_INIT(cid_cnt)        (cid_cnt > QM_INIT_MIN_CID_COUNT)
  884 
  885 /* called during init port stage */
  886 static void ecore_qm_init_cid_count(struct bxe_softc *sc, int qm_cid_count,
  887                                     uint8_t initop)
  888 {
  889         int port = SC_PORT(sc);
  890 
  891         if (QM_INIT(qm_cid_count)) {
  892                 switch (initop) {
  893                 case INITOP_INIT:
  894                         /* set in the init-value array */
  895                 case INITOP_SET:
  896                         REG_WR(sc, QM_REG_CONNNUM_0 + port*4,
  897                                qm_cid_count/16 - 1);
  898                         break;
  899                 case INITOP_CLEAR:
  900                         break;
  901                 }
  902         }
  903 }
  904 
  905 static void ecore_qm_set_ptr_table(struct bxe_softc *sc, int qm_cid_count,
  906                                    uint32_t base_reg, uint32_t reg)
  907 {
  908         int i;
  909         uint32_t wb_data[2] = {0, 0};
  910         for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) {
  911                 REG_WR(sc, base_reg + i*4,
  912                        qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
  913                 ecore_init_wr_wb(sc, reg + i*8,
  914                                  wb_data, 2);
  915         }
  916 }
  917 
  918 /* called during init common stage */
  919 static void ecore_qm_init_ptr_table(struct bxe_softc *sc, int qm_cid_count,
  920                                     uint8_t initop)
  921 {
  922         if (!QM_INIT(qm_cid_count))
  923                 return;
  924 
  925         switch (initop) {
  926         case INITOP_INIT:
  927                 /* set in the init-value array */
  928         case INITOP_SET:
  929                 ecore_qm_set_ptr_table(sc, qm_cid_count,
  930                                        QM_REG_BASEADDR, QM_REG_PTRTBL);
  931                 if (CHIP_IS_E1H(sc))
  932                         ecore_qm_set_ptr_table(sc, qm_cid_count,
  933                                                QM_REG_BASEADDR_EXT_A,
  934                                                QM_REG_PTRTBL_EXT_A);
  935                 break;
  936         case INITOP_CLEAR:
  937                 break;
  938         }
  939 }
  940 
  941 /****************************************************************************
  942 * SRC initializations
  943 ****************************************************************************/
  944 #ifdef ECORE_L5
  945 /* called during init func stage */
  946 static void ecore_src_init_t2(struct bxe_softc *sc, struct src_ent *t2,
  947                               ecore_dma_addr_t t2_mapping, int src_cid_count)
  948 {
  949         int i;
  950         int port = SC_PORT(sc);
  951 
  952         /* Initialize T2 */
  953         for (i = 0; i < src_cid_count-1; i++)
  954                 t2[i].next = (uint64_t)(t2_mapping +
  955                              (i+1)*sizeof(struct src_ent));
  956 
  957         /* tell the searcher where the T2 table is */
  958         REG_WR(sc, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
  959 
  960         ecore_wr_64(sc, SRC_REG_FIRSTFREE0 + port*16,
  961                     U64_LO(t2_mapping), U64_HI(t2_mapping));
  962 
  963         ecore_wr_64(sc, SRC_REG_LASTFREE0 + port*16,
  964                     U64_LO((uint64_t)t2_mapping +
  965                            (src_cid_count-1) * sizeof(struct src_ent)),
  966                     U64_HI((uint64_t)t2_mapping +
  967                            (src_cid_count-1) * sizeof(struct src_ent)));
  968 }
  969 #endif
  970 #endif /* ECORE_INIT_OPS_H */

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