if_ath_cardbus.c

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    1 /*      $OpenBSD: if_ath_cardbus.c,v 1.21 2023/01/04 07:06:08 jsg Exp $   */
    2 /*      $NetBSD: if_ath_cardbus.c,v 1.4 2004/08/02 19:14:28 mycroft Exp $ */
    3 
    4 /*
    5  * Copyright (c) 2003
    6  *      Ichiro FUKUHARA <ichiro@ichiro.org>.
    7  * All rights reserved.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
   19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   21  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
   22  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  */
   30 
   31 /*
   32  * CardBus bus front-end for the AR5001 Wireless LAN 802.11a/b/g CardBus.
   33  */
   34 
   35 #include <sys/param.h>
   36 #include <sys/systm.h> 
   37 #include <sys/mbuf.h>   
   38 #include <sys/malloc.h>
   39 #include <sys/kernel.h>
   40 #include <sys/socket.h>
   41 #include <sys/ioctl.h>
   42 #include <sys/errno.h>
   43 #include <sys/device.h>
   44 #include <sys/gpio.h>
   45 #include <sys/endian.h>
   46  
   47 #include <net/if.h>
   48 #include <net/if_media.h>
   49 
   50 #include <netinet/in.h> 
   51 #include <netinet/if_ether.h>
   52 
   53 #include <net80211/ieee80211_var.h>
   54 #include <net80211/ieee80211_rssadapt.h>
   55 
   56 #include <machine/bus.h>
   57 #include <machine/intr.h>
   58 
   59 #include <dev/gpio/gpiovar.h>
   60 
   61 #include <dev/pci/pcivar.h>
   62 #include <dev/pci/pcireg.h>
   63 #include <dev/pci/pcidevs.h>
   64 
   65 #include <dev/cardbus/cardbusvar.h>
   66 
   67 #include <dev/ic/athvar.h>
   68 
   69 /*
   70  * PCI configuration space registers
   71  */
   72 #define ATH_PCI_MMBA            0x10    /* memory mapped base */
   73 
   74 struct ath_cardbus_softc {
   75         struct ath_softc        sc_ath;
   76 
   77         /* CardBus-specific goo. */
   78         void    *sc_ih;                 /* interrupt handle */
   79         cardbus_devfunc_t sc_ct;        /* our CardBus devfuncs */
   80         pcitag_t sc_tag;                /* our CardBus tag */
   81 
   82         pcireg_t sc_bar_val;            /* value of the BAR */
   83 
   84         int     sc_intrline;            /* interrupt line */
   85         pci_chipset_tag_t sc_pc;
   86 };
   87 
   88 int     ath_cardbus_match(struct device *, void *, void *);
   89 void    ath_cardbus_attach(struct device *, struct device *, void *);
   90 int     ath_cardbus_detach(struct device *, int);
   91 
   92 const struct cfattach ath_cardbus_ca = {
   93         sizeof(struct ath_cardbus_softc),
   94         ath_cardbus_match,
   95         ath_cardbus_attach,
   96         ath_cardbus_detach
   97 };
   98 
   99 
  100 void    ath_cardbus_setup(struct ath_cardbus_softc *);
  101 
  102 int     ath_cardbus_enable(struct ath_softc *);
  103 void    ath_cardbus_disable(struct ath_softc *);
  104 void    ath_cardbus_power(struct ath_softc *, int);
  105 
  106 int
  107 ath_cardbus_match(struct device *parent, void *match, void *aux)
  108 {
  109         struct cardbus_attach_args *ca = aux;
  110         const char* devname;
  111 
  112         devname = ath_hal_probe(PCI_VENDOR(ca->ca_id),
  113                                 PCI_PRODUCT(ca->ca_id));
  114 
  115         if (devname)
  116                 return (1);
  117 
  118         return (0);
  119 }
  120 
  121 void
  122 ath_cardbus_attach(struct device *parent, struct device *self, void *aux)
  123 {
  124         struct ath_cardbus_softc *csc = (void *)self;
  125         struct ath_softc *sc = &csc->sc_ath;
  126         struct cardbus_attach_args *ca = aux;
  127         cardbus_devfunc_t ct = ca->ca_ct;
  128         bus_addr_t adr;
  129 
  130         sc->sc_dmat = ca->ca_dmat;
  131         csc->sc_ct = ct;
  132         csc->sc_tag = ca->ca_tag;
  133         csc->sc_pc = ca->ca_pc;
  134 
  135         /*
  136          * Power management hooks.
  137          */
  138         sc->sc_enable = ath_cardbus_enable;
  139         sc->sc_disable = ath_cardbus_disable;
  140         sc->sc_power = ath_cardbus_power;
  141 
  142         /*
  143          * Map the device.
  144          */
  145         if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
  146             &sc->sc_st, &sc->sc_sh, &adr, &sc->sc_ss) == 0) {
  147                 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
  148         }
  149 
  150         else {
  151                 printf(": unable to map device registers\n");
  152                 return;
  153         }
  154 
  155         /*
  156          * Set up the PCI configuration registers.
  157          */
  158         ath_cardbus_setup(csc);
  159 
  160         /* Remember which interrupt line. */
  161         csc->sc_intrline = ca->ca_intrline;
  162 
  163         printf(": irq %d\n", csc->sc_intrline);
  164 
  165         /*
  166          * Finish off the attach.
  167          */
  168         ath_attach(PCI_PRODUCT(ca->ca_id), sc);
  169 
  170         /*
  171          * Power down the socket.
  172          */
  173         Cardbus_function_disable(csc->sc_ct);
  174 }
  175 
  176 int
  177 ath_cardbus_detach(struct device *self, int flags)
  178 {
  179         struct ath_cardbus_softc *csc = (void *)self;
  180         struct ath_softc *sc = &csc->sc_ath;
  181         struct cardbus_devfunc *ct = csc->sc_ct;
  182         int rv;
  183 
  184 #if defined(DIAGNOSTIC)
  185         if (ct == NULL)
  186                 panic("%s: data structure lacks", sc->sc_dev.dv_xname);
  187 #endif
  188 
  189         rv = ath_detach(sc, flags);
  190         if (rv)
  191                 return (rv);
  192 
  193         /*
  194          * Unhook the interrupt handler.
  195          */
  196         if (csc->sc_ih != NULL) {
  197                 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
  198                 csc->sc_ih = NULL;
  199         }
  200 
  201         /*
  202          * Release bus space and close window.
  203          */
  204         Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA,
  205                     sc->sc_st, sc->sc_sh, sc->sc_ss);
  206 
  207         return (0);
  208 }
  209 
  210 int
  211 ath_cardbus_enable(struct ath_softc *sc)
  212 {
  213         struct ath_cardbus_softc *csc = (void *) sc;
  214         cardbus_devfunc_t ct = csc->sc_ct;
  215         cardbus_chipset_tag_t cc = ct->ct_cc;
  216         cardbus_function_tag_t cf = ct->ct_cf;
  217 
  218         /*
  219          * Power on the socket.
  220          */
  221         Cardbus_function_enable(ct);
  222 
  223         /*
  224          * Set up the PCI configuration registers.
  225          */
  226         ath_cardbus_setup(csc);
  227 
  228         /*
  229          * Map and establish the interrupt.
  230          */
  231         csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
  232             ath_intr, sc, sc->sc_dev.dv_xname);
  233         if (csc->sc_ih == NULL) {
  234                 printf(": unable to establish irq %d\n",
  235                        csc->sc_intrline);
  236                 Cardbus_function_disable(csc->sc_ct);
  237                 return (1);
  238         }
  239         return (0);
  240 }
  241 
  242 void
  243 ath_cardbus_disable(struct ath_softc *sc)
  244 {
  245         struct ath_cardbus_softc *csc = (void *) sc;
  246         cardbus_devfunc_t ct = csc->sc_ct;
  247         cardbus_chipset_tag_t cc = ct->ct_cc;
  248         cardbus_function_tag_t cf = ct->ct_cf;
  249 
  250         /* Unhook the interrupt handler. */
  251         cardbus_intr_disestablish(cc, cf, csc->sc_ih);
  252         csc->sc_ih = NULL;
  253 
  254         /* Power down the socket. */
  255         Cardbus_function_disable(ct);
  256 }
  257 
  258 void
  259 ath_cardbus_power(struct ath_softc *sc, int why)
  260 {
  261         if (why == DVACT_RESUME)
  262                 ath_enable(sc);
  263 }
  264 
  265 void
  266 ath_cardbus_setup(struct ath_cardbus_softc *csc)
  267 {
  268         cardbus_devfunc_t ct = csc->sc_ct;
  269         cardbus_chipset_tag_t cc = ct->ct_cc;
  270         pci_chipset_tag_t pc = csc->sc_pc;
  271         pcireg_t reg;
  272 
  273 #ifdef notyet
  274         (void)cardbus_setpowerstate(sc->sc_dev.dv_xname, ct, csc->sc_tag,
  275             PCI_PWR_D0);
  276 #endif
  277 
  278         /* Program the BAR. */
  279         pci_conf_write(pc, csc->sc_tag, ATH_PCI_MMBA,
  280             csc->sc_bar_val);
  281 
  282         /* Make sure the right access type is on the CardBus bridge. */
  283         (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE);
  284         (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
  285 
  286         /* Enable the appropriate bits in the PCI CSR. */
  287         reg = pci_conf_read(pc, csc->sc_tag,
  288             PCI_COMMAND_STATUS_REG);
  289         reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
  290         pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
  291             reg);
  292 
  293         /*
  294          * Make sure the latency timer is set to some reasonable
  295          * value.
  296          */
  297         reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
  298         if (PCI_LATTIMER(reg) < 0x20) {
  299                 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
  300                 reg |= (0x20 << PCI_LATTIMER_SHIFT);
  301                 pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
  302         }
  303 }

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FreeBSD/Linux Kernel Cross Reference sys/dev/cardbus/if_ath_cardbus.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/cardbus/if_ath_cardbus.c