The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/cardbus/if_fxp_cardbus.c

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    1 /*      $OpenBSD: if_fxp_cardbus.c,v 1.38 2022/04/06 18:59:28 naddy Exp $ */
    2 /*      $NetBSD: if_fxp_cardbus.c,v 1.12 2000/05/08 18:23:36 thorpej Exp $      */
    3 
    4 /*
    5  * Copyright (c) 1999 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Johan Danielsson.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   30  * POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 /*
   34  * CardBus front-end for the Intel i8255x family of Ethernet chips.
   35  */
   36 
   37 #include "bpfilter.h"
   38 
   39 #include <sys/param.h>
   40 #include <sys/systm.h>
   41 #include <sys/mbuf.h>
   42 #include <sys/socket.h>
   43 #include <sys/ioctl.h>
   44 #include <sys/errno.h>
   45 #include <sys/malloc.h>
   46 #include <sys/kernel.h>
   47 #include <sys/timeout.h>
   48 #include <sys/device.h>
   49 #include <sys/endian.h>
   50 
   51 #include <net/if.h>
   52 #include <net/if_media.h>
   53 
   54 #if NBPFILTER > 0
   55 #include <net/bpf.h>
   56 #endif
   57 
   58 #include <netinet/in.h>
   59 #include <netinet/if_ether.h>
   60 
   61 #include <machine/bus.h>
   62 #include <machine/intr.h>
   63 
   64 #include <dev/mii/miivar.h>
   65 
   66 #include <dev/ic/fxpreg.h>
   67 #include <dev/ic/fxpvar.h>
   68 
   69 #include <dev/pci/pcivar.h>
   70 #include <dev/pci/pcireg.h>
   71 #include <dev/pci/pcidevs.h>
   72 
   73 #include <dev/cardbus/cardbusvar.h>
   74 
   75 int fxp_cardbus_match(struct device *, void *, void *);
   76 void fxp_cardbus_attach(struct device *, struct device *, void *);
   77 int fxp_cardbus_detach(struct device *, int);
   78 void fxp_cardbus_setup(struct fxp_softc *);
   79 
   80 struct fxp_cardbus_softc {
   81         struct fxp_softc sc;
   82         cardbus_devfunc_t ct;
   83         pcitag_t ct_tag;
   84         pcireg_t base0_reg;
   85         pcireg_t base1_reg;
   86         bus_size_t size;
   87         pci_chipset_tag_t pc;
   88 };
   89 
   90 const struct cfattach fxp_cardbus_ca = {
   91         sizeof(struct fxp_cardbus_softc), fxp_cardbus_match, fxp_cardbus_attach,
   92             fxp_cardbus_detach
   93 };
   94 
   95 const struct pci_matchid fxp_cardbus_devices[] = {
   96         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8255X },
   97 };
   98 
   99 #ifdef CBB_DEBUG
  100 #define DPRINTF(X) printf X
  101 #else
  102 #define DPRINTF(X)
  103 #endif
  104 
  105 int
  106 fxp_cardbus_match(struct device *parent, void *match, void *aux)
  107 {
  108         return (cardbus_matchbyid((struct cardbus_attach_args *)aux,
  109             fxp_cardbus_devices, nitems(fxp_cardbus_devices)));
  110 }
  111 
  112 void
  113 fxp_cardbus_attach(struct device *parent, struct device *self, void *aux)
  114 {
  115         char intrstr[16];
  116         struct fxp_softc *sc = (struct fxp_softc *) self;
  117         struct fxp_cardbus_softc *csc = (struct fxp_cardbus_softc *) self;
  118         struct cardbus_attach_args *ca = aux;
  119         struct cardbus_softc *psc =
  120             (struct cardbus_softc *)sc->sc_dev.dv_parent;
  121         cardbus_chipset_tag_t cc = psc->sc_cc;
  122         cardbus_function_tag_t cf = psc->sc_cf;
  123         bus_space_tag_t iot, memt;
  124         bus_space_handle_t ioh, memh;
  125 
  126         bus_addr_t adr;
  127         bus_size_t size;
  128 
  129         csc->ct = ca->ca_ct;
  130         csc->pc = ca->ca_pc;
  131 
  132         /*
  133          * Map control/status registers.
  134          */
  135         if (Cardbus_mapreg_map(csc->ct, CARDBUS_BASE1_REG,
  136             PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, &adr, &size) == 0) {
  137                 csc->base1_reg = adr | 1;
  138                 sc->sc_st = iot;
  139                 sc->sc_sh = ioh;
  140                 csc->size = size;
  141         } else if (Cardbus_mapreg_map(csc->ct, CARDBUS_BASE0_REG,
  142             PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
  143             0, &memt, &memh, &adr, &size) == 0) {
  144                 csc->base0_reg = adr;
  145                 sc->sc_st = memt;
  146                 sc->sc_sh = memh;
  147                 csc->size = size;
  148         } else
  149                 panic("%s: failed to allocate mem and io space", __func__);
  150 
  151         sc->sc_dmat = ca->ca_dmat;
  152 #if 0
  153         sc->sc_enable = fxp_cardbus_enable;
  154         sc->sc_disable = fxp_cardbus_disable;
  155         sc->sc_enabled = 0;
  156 #endif
  157 
  158         Cardbus_function_enable(csc->ct);
  159 
  160         fxp_cardbus_setup(sc);
  161 
  162         /* Map and establish the interrupt. */
  163         sc->sc_ih = cardbus_intr_establish(cc, cf, psc->sc_intrline, IPL_NET,
  164             fxp_intr, sc, sc->sc_dev.dv_xname);
  165         if (NULL == sc->sc_ih) {
  166                 printf(": couldn't establish interrupt");
  167                 printf("at %d\n", ca->ca_intrline);
  168                 return;
  169         }
  170         snprintf(intrstr, sizeof(intrstr), "irq %d", ca->ca_intrline);
  171         
  172         sc->sc_revision = PCI_REVISION(ca->ca_class);
  173 
  174         fxp_attach(sc, intrstr);
  175 }
  176 
  177 void
  178 fxp_cardbus_setup(struct fxp_softc *sc)
  179 {
  180         struct fxp_cardbus_softc *csc = (struct fxp_cardbus_softc *) sc;
  181         struct cardbus_softc *psc =
  182             (struct cardbus_softc *) sc->sc_dev.dv_parent;
  183         cardbus_chipset_tag_t cc = psc->sc_cc;
  184         pci_chipset_tag_t pc = csc->pc;
  185         cardbus_function_tag_t cf = psc->sc_cf;
  186         pcireg_t command;
  187 
  188         csc->ct_tag = pci_make_tag(pc, csc->ct->ct_bus,
  189             csc->ct->ct_dev, csc->ct->ct_func);
  190 
  191         command = pci_conf_read(pc, csc->ct_tag, PCI_COMMAND_STATUS_REG);
  192         if (csc->base0_reg) {
  193                 pci_conf_write(pc, csc->ct_tag, CARDBUS_BASE0_REG, csc->base0_reg);
  194                 (cf->cardbus_ctrl) (cc, CARDBUS_MEM_ENABLE);
  195                 command |= PCI_COMMAND_MEM_ENABLE |
  196                     PCI_COMMAND_MASTER_ENABLE;
  197         } else if (csc->base1_reg) {
  198                 pci_conf_write(pc, csc->ct_tag, CARDBUS_BASE1_REG, csc->base1_reg);
  199                 (cf->cardbus_ctrl) (cc, CARDBUS_IO_ENABLE);
  200                 command |= (PCI_COMMAND_IO_ENABLE |
  201                     PCI_COMMAND_MASTER_ENABLE);
  202         }
  203 
  204         (cf->cardbus_ctrl) (cc, CARDBUS_BM_ENABLE);
  205 
  206         /* enable the card */
  207         pci_conf_write(pc, csc->ct_tag, PCI_COMMAND_STATUS_REG, command);
  208 }
  209 
  210 int
  211 fxp_cardbus_detach(struct device *self, int flags)
  212 {
  213         struct fxp_softc *sc = (struct fxp_softc *) self;
  214         struct fxp_cardbus_softc *csc = (struct fxp_cardbus_softc *) self;
  215         struct cardbus_devfunc *ct = csc->ct;
  216         int reg;
  217 
  218         cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih);
  219         fxp_detach(sc);
  220 
  221         if (csc->base0_reg)
  222                 reg = CARDBUS_BASE0_REG;
  223         else
  224                 reg = CARDBUS_BASE1_REG;
  225         Cardbus_mapreg_unmap(ct, reg, sc->sc_st, sc->sc_sh, csc->size);
  226         return (0);
  227 }

Cache object: 39999ae2ac28a7efc169450e9fa2d449


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