if_rl_cardbus.c

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    1 /*      $OpenBSD: if_rl_cardbus.c,v 1.32 2022/04/06 18:59:28 naddy Exp $ */
    2 /*      $NetBSD: if_rl_cardbus.c,v 1.3.8.3 2001/11/14 19:14:02 nathanw Exp $    */
    3 
    4 /*
    5  * Copyright (c) 2000 Masanori Kanaoka
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. The name of the author may not be used to endorse or promote products
   17  *    derived from this software without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
   28  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   29  */
   30 
   31 /*
   32  * if_rl_cardbus.c:
   33  *      Cardbus specific routines for Realtek 8139 ethernet adapter.
   34  *      Tested for 
   35  *              - elecom-Laneed LD-10/100CBA (Accton MPX5030)
   36  *              - MELCO         LPC3-TX-CB   (Realtek 8139)
   37  */
   38 
   39 #include "bpfilter.h"
   40 
   41 #include <sys/param.h>
   42 #include <sys/systm.h>
   43 #include <sys/mbuf.h>
   44 #include <sys/socket.h>
   45 #include <sys/ioctl.h>
   46 #include <sys/errno.h>
   47 #include <sys/malloc.h>
   48 #include <sys/kernel.h>
   49 #include <sys/timeout.h>
   50 #include <sys/device.h>
   51 #include <sys/endian.h>
   52 
   53 #include <net/if.h>
   54 #include <net/if_media.h>
   55 
   56 #if NBPFILTER > 0
   57 #include <net/bpf.h>
   58 #endif
   59 
   60 #include <netinet/in.h>
   61 #include <netinet/if_ether.h>
   62 
   63 #include <machine/bus.h>
   64 #include <machine/intr.h>
   65 
   66 #include <dev/mii/miivar.h>
   67 
   68 #include <dev/pci/pcivar.h>
   69 #include <dev/pci/pcireg.h>
   70 #include <dev/pci/pcidevs.h>
   71 
   72 #include <dev/cardbus/cardbusvar.h>
   73 
   74 /*
   75  * Default to using PIO access for this driver. On SMP systems,
   76  * there appear to be problems with memory mapped mode: it looks like
   77  * doing too many memory mapped access back to back in rapid succession
   78  * can hang the bus. I'm inclined to blame this on crummy design/construction
   79  * on the part of Realtek. Memory mapped mode does appear to work on
   80  * uniprocessor systems though.
   81  */
   82 #define RL_USEIOSPACE 
   83 
   84 #include <dev/ic/rtl81x9reg.h>
   85 
   86 /*
   87  * Various supported device vendors/types and their names.
   88  */
   89 const struct pci_matchid rl_cardbus_devices[] = {
   90         { PCI_VENDOR_ABOCOM, PCI_PRODUCT_ABOCOM_FE2000VX },
   91         { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_5030 },
   92         { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD },
   93         { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD },
   94         { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD },
   95         { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3603_TX },
   96         { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX },
   97         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8138 },
   98         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139 },
   99 };
  100 
  101 struct rl_cardbus_softc {
  102         struct rl_softc sc_rl;  /* real rtk softc */ 
  103 
  104         /* CardBus-specific goo. */
  105         cardbus_devfunc_t sc_ct;
  106         pci_chipset_tag_t sc_pc;
  107         pcitag_t sc_tag;
  108         int sc_csr;
  109         int sc_cben;
  110         int sc_bar_reg;
  111         pcireg_t sc_bar_val;
  112         bus_size_t sc_mapsize;
  113         int sc_intrline;
  114 };
  115 
  116 static int rl_cardbus_match(struct device *, void *, void *);
  117 static void rl_cardbus_attach(struct device *, struct device *, void *);
  118 static int rl_cardbus_detach(struct device *, int);
  119 void rl_cardbus_setup(struct rl_cardbus_softc *);
  120 
  121 const struct cfattach rl_cardbus_ca = {
  122         sizeof(struct rl_cardbus_softc), rl_cardbus_match, rl_cardbus_attach,
  123             rl_cardbus_detach
  124 };
  125 
  126 int
  127 rl_cardbus_match(struct device *parent, void *match, void *aux)
  128 {
  129         return (cardbus_matchbyid((struct cardbus_attach_args *)aux,
  130             rl_cardbus_devices, nitems(rl_cardbus_devices)));
  131 }
  132 
  133 
  134 void
  135 rl_cardbus_attach(struct device *parent, struct device *self, void *aux)
  136 {
  137         struct rl_cardbus_softc         *csc =
  138             (struct rl_cardbus_softc *)self;
  139         struct rl_softc                 *sc = &csc->sc_rl;
  140         struct cardbus_attach_args      *ca = aux;
  141         struct cardbus_softc            *psc =
  142             (struct cardbus_softc *)sc->sc_dev.dv_parent;
  143         cardbus_chipset_tag_t           cc = psc->sc_cc;
  144         cardbus_function_tag_t          cf = psc->sc_cf;                            
  145         cardbus_devfunc_t               ct = ca->ca_ct;
  146         bus_addr_t                      adr;
  147 
  148         sc->sc_dmat = ca->ca_dmat;
  149         csc->sc_ct = ct;
  150         csc->sc_tag = ca->ca_tag;
  151         csc->sc_intrline = ca->ca_intrline;
  152         csc->sc_pc = ca->ca_pc;
  153 
  154         /*
  155          * Map control/status registers.
  156          */
  157         csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
  158 #ifdef RL_USEIOSPACE
  159         if (Cardbus_mapreg_map(ct, RL_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
  160             &sc->rl_btag, &sc->rl_bhandle, &adr, &csc->sc_mapsize) == 0) {
  161                 csc->sc_cben = CARDBUS_IO_ENABLE;
  162                 csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
  163                 csc->sc_bar_reg = RL_PCI_LOIO;
  164                 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO;
  165         }
  166 #else
  167         if (Cardbus_mapreg_map(ct, RL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
  168             &sc->rl_btag, &sc->rl_bhandle, &adr, &csc->sc_mapsize) == 0) {
  169                 csc->sc_cben = CARDBUS_MEM_ENABLE;
  170                 csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
  171                 csc->sc_bar_reg = RL_PCI_LOMEM;
  172                 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
  173         }
  174 #endif
  175         else {
  176                 printf("%s: unable to map deviceregisters\n",
  177                          sc->sc_dev.dv_xname);
  178                 return;
  179         }
  180 
  181         Cardbus_function_enable(ct);
  182 
  183         rl_cardbus_setup(csc);
  184 
  185         /*
  186          * Map and establish the interrupt.
  187          */
  188         sc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
  189             rl_intr, sc, sc->sc_dev.dv_xname);
  190         if (sc->sc_ih == NULL) {
  191                 printf(": couldn't establish interrupt\n");
  192                 Cardbus_function_disable(csc->sc_ct);
  193                 return;
  194         }
  195         printf(": irq %d", csc->sc_intrline);
  196 
  197         sc->rl_type = RL_8139;
  198 
  199         rl_attach(sc);
  200 }
  201 
  202 int 
  203 rl_cardbus_detach(struct device *self, int flags)
  204 {
  205         struct rl_cardbus_softc *csc = (void *) self;
  206         struct rl_softc         *sc = &csc->sc_rl;
  207         struct cardbus_devfunc  *ct = csc->sc_ct;
  208         int                     rv;
  209 
  210 #ifdef DIAGNOSTIC
  211         if (ct == NULL)
  212                 panic("%s: data structure lacks", sc->sc_dev.dv_xname);
  213 #endif
  214         rv = rl_detach(sc);
  215         if (rv)
  216                 return (rv);
  217         /*
  218          * Unhook the interrupt handler.
  219          */
  220         if (sc->sc_ih != NULL)
  221                 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih);
  222         
  223         /*
  224          * Release bus space and close window.
  225          */
  226         if (csc->sc_bar_reg != 0)
  227                 Cardbus_mapreg_unmap(ct, csc->sc_bar_reg,
  228                         sc->rl_btag, sc->rl_bhandle, csc->sc_mapsize);
  229 
  230         return (0);
  231 }
  232 
  233 void 
  234 rl_cardbus_setup(struct rl_cardbus_softc *csc)
  235 {
  236         struct rl_softc         *sc = &csc->sc_rl;
  237         cardbus_devfunc_t       ct = csc->sc_ct;
  238         cardbus_chipset_tag_t   cc = ct->ct_cc;
  239         pci_chipset_tag_t       pc = csc->sc_pc;
  240         pcireg_t                reg, command;
  241         int                     pmreg;
  242 
  243         /*
  244          * Handle power management nonsense.
  245          */
  246         if (pci_get_capability(pc, csc->sc_tag,
  247             PCI_CAP_PWRMGMT, &pmreg, 0)) {
  248                 command = pci_conf_read(pc, csc->sc_tag, pmreg + 4);
  249                 if (command & RL_PSTATE_MASK) {
  250                         pcireg_t                iobase, membase, irq;
  251 
  252                         /* Save important PCI config data. */
  253                         iobase = pci_conf_read(pc, csc->sc_tag,
  254                             RL_PCI_LOIO);
  255                         membase = pci_conf_read(pc, csc->sc_tag,
  256                             RL_PCI_LOMEM);
  257                         irq = pci_conf_read(pc, csc->sc_tag,
  258                             PCI_PRODUCT_DELTA_8139);
  259 
  260                         /* Reset the power state. */
  261                         printf("%s: chip is in D%d power mode "
  262                             "-- setting to D0\n", sc->sc_dev.dv_xname,
  263                             command & RL_PSTATE_MASK);
  264                         command &= 0xFFFFFFFC;
  265                         pci_conf_write(pc, csc->sc_tag,
  266                             pmreg + 4, command);
  267 
  268                         /* Restore PCI config data. */
  269                         pci_conf_write(pc, csc->sc_tag,
  270                             RL_PCI_LOIO, iobase);
  271                         pci_conf_write(pc, csc->sc_tag,
  272                             RL_PCI_LOMEM, membase);
  273                         pci_conf_write(pc, csc->sc_tag,
  274                             PCI_PRODUCT_DELTA_8139, irq);
  275                 }
  276         }
  277 
  278         /* Make sure the right access type is on the CardBus bridge. */
  279         (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben);
  280         (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
  281 
  282         /* Program the BAR */
  283         pci_conf_write(pc, csc->sc_tag,
  284                 csc->sc_bar_reg, csc->sc_bar_val);
  285 
  286         /* Enable the appropriate bits in the CARDBUS CSR. */
  287         reg = pci_conf_read(pc, csc->sc_tag, 
  288             PCI_COMMAND_STATUS_REG);
  289         reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
  290         reg |= csc->sc_csr;
  291         pci_conf_write(pc, csc->sc_tag, 
  292             PCI_COMMAND_STATUS_REG, reg);
  293 
  294         /*
  295          * Make sure the latency timer is set to some reasonable
  296          * value.
  297          */
  298         reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
  299         if (PCI_LATTIMER(reg) < 0x20) {
  300                 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
  301                 reg |= (0x20 << PCI_LATTIMER_SHIFT);
  302                 pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
  303         }
  304 }
  305
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FreeBSD/Linux Kernel Cross Reference sys/dev/cardbus/if_rl_cardbus.c

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sys/dev/cardbus/if_rl_cardbus.c
