cesa.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (C) 2009-2011 Semihalf.
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  *
   28  * $FreeBSD$
   29  */
   30 
   31 #ifndef _DEV_CESA_H_
   32 #define _DEV_CESA_H_
   33 
   34 /* Maximum number of queued requests */
   35 #define CESA_REQUESTS                   256
   36 
   37 /*
   38  * CESA is able to process data only in CESA SRAM, which is quite small (2 kB).
   39  * We have to fit a packet there, which contains SA descriptor, keys, IV
   40  * and data to be processed. Every request must be converted into chain of
   41  * packets and each packet can hold about 1.75 kB of data.
   42  *
   43  * To process each packet we need at least 1 SA descriptor and at least 4 TDMA
   44  * descriptors. However there are cases when we use 2 SA and 8 TDMA descriptors
   45  * per packet. Number of used TDMA descriptors can increase beyond given values
   46  * if data in the request is fragmented in physical memory.
   47  *
   48  * The driver uses preallocated SA and TDMA descriptors pools to get best
   49  * performace. Size of these pools should match expected request size. Example:
   50  *
   51  * Expected average request size:                       1.5 kB (Ethernet MTU)
   52  * Packets per average request:                         (1.5 kB / 1.75 kB) = 1
   53  * SA decriptors per average request (worst case):      1 * 2 = 2
   54  * TDMA desctiptors per average request (worst case):   1 * 8 = 8
   55  *
   56  * More TDMA descriptors should be allocated, if data fragmentation is expected
   57  * (for example while processing mbufs larger than MCLBYTES). The driver may use
   58  * 2 additional TDMA descriptors per each discontinuity in the physical data
   59  * layout.
   60  */
   61 
   62 /* Values below are optimized for requests containing about 1.5 kB of data */
   63 #define CESA_SA_DESC_PER_REQ            2
   64 #define CESA_TDMA_DESC_PER_REQ          8
   65 
   66 #define CESA_SA_DESCRIPTORS             (CESA_SA_DESC_PER_REQ * CESA_REQUESTS)
   67 #define CESA_TDMA_DESCRIPTORS           (CESA_TDMA_DESC_PER_REQ * CESA_REQUESTS)
   68 
   69 /* Useful constants */
   70 #define CESA_HMAC_TRUNC_LEN             12
   71 #define CESA_MAX_FRAGMENTS              64
   72 #define CESA_SRAM_SIZE                  2048
   73 
   74 /*
   75  * CESA_MAX_HASH_LEN is maximum length of hash generated by CESA.
   76  * As CESA supports MD5, SHA1 and SHA-256 this equals to 32 bytes.
   77  */
   78 #define CESA_MAX_HASH_LEN               32
   79 #define CESA_MAX_KEY_LEN                32
   80 #define CESA_MAX_IV_LEN                 16
   81 #define CESA_MAX_HMAC_BLOCK_LEN         64
   82 #define CESA_MAX_MKEY_LEN               CESA_MAX_HMAC_BLOCK_LEN
   83 #define CESA_MAX_PACKET_SIZE            (CESA_SRAM_SIZE - CESA_DATA(0))
   84 #define CESA_MAX_REQUEST_SIZE           65535
   85 
   86 /* Locking macros */
   87 #define CESA_LOCK(sc, what)             mtx_lock(&(sc)->sc_ ## what ## _lock)
   88 #define CESA_UNLOCK(sc, what)           mtx_unlock(&(sc)->sc_ ## what ## _lock)
   89 #define CESA_LOCK_ASSERT(sc, what)      \
   90         mtx_assert(&(sc)->sc_ ## what ## _lock, MA_OWNED)
   91 
   92 /* Registers read/write macros */
   93 #define CESA_REG_READ(sc, reg)          \
   94         bus_read_4((sc)->sc_res[RES_CESA_REGS], (reg))
   95 #define CESA_REG_WRITE(sc, reg, val)    \
   96         bus_write_4((sc)->sc_res[RES_CESA_REGS], (reg), (val))
   97 
   98 #define CESA_TDMA_READ(sc, reg)         \
   99         bus_read_4((sc)->sc_res[RES_TDMA_REGS], (reg))
  100 #define CESA_TDMA_WRITE(sc, reg, val)   \
  101         bus_write_4((sc)->sc_res[RES_TDMA_REGS], (reg), (val))
  102 
  103 /* Generic allocator for objects */
  104 #define CESA_GENERIC_ALLOC_LOCKED(sc, obj, pool) do {           \
  105         CESA_LOCK(sc, pool);                                    \
  106                                                                 \
  107         if (STAILQ_EMPTY(&(sc)->sc_free_ ## pool))              \
  108                 obj = NULL;                                     \
  109         else {                                                  \
  110                 obj = STAILQ_FIRST(&(sc)->sc_free_ ## pool);    \
  111                 STAILQ_REMOVE_HEAD(&(sc)->sc_free_ ## pool,     \
  112                     obj ## _stq);                               \
  113         }                                                       \
  114                                                                 \
  115         CESA_UNLOCK(sc, pool);                                  \
  116 } while (0)
  117 
  118 #define CESA_GENERIC_FREE_LOCKED(sc, obj, pool) do {            \
  119         CESA_LOCK(sc, pool);                                    \
  120         STAILQ_INSERT_TAIL(&(sc)->sc_free_ ## pool, obj,        \
  121             obj ## _stq);                                       \
  122         CESA_UNLOCK(sc, pool);                                  \
  123 } while (0)
  124 
  125 /* CESA SRAM offset calculation macros */
  126 #define CESA_SA_DATA(member)                                    \
  127         (sizeof(struct cesa_sa_hdesc) + offsetof(struct cesa_sa_data, member))
  128 #define CESA_DATA(offset)                                       \
  129         (sizeof(struct cesa_sa_hdesc) + sizeof(struct cesa_sa_data) + offset)
  130 
  131 /* CESA memory and IRQ resources */
  132 enum cesa_res_type {
  133         RES_TDMA_REGS,
  134         RES_CESA_REGS,
  135         RES_CESA_IRQ,
  136         RES_CESA_NUM
  137 };
  138 
  139 struct cesa_tdma_hdesc {
  140         uint16_t        cthd_byte_count;
  141         uint16_t        cthd_flags;
  142         uint32_t        cthd_src;
  143         uint32_t        cthd_dst;
  144         uint32_t        cthd_next;
  145 };
  146 
  147 struct cesa_sa_hdesc {
  148         uint32_t        cshd_config;
  149         uint16_t        cshd_enc_src;
  150         uint16_t        cshd_enc_dst;
  151         uint32_t        cshd_enc_dlen;
  152         uint32_t        cshd_enc_key;
  153         uint16_t        cshd_enc_iv;
  154         uint16_t        cshd_enc_iv_buf;
  155         uint16_t        cshd_mac_src;
  156         uint16_t        cshd_mac_total_dlen;
  157         uint16_t        cshd_mac_dst;
  158         uint16_t        cshd_mac_dlen;
  159         uint16_t        cshd_mac_iv_in;
  160         uint16_t        cshd_mac_iv_out;
  161 };
  162 
  163 struct cesa_sa_data {
  164         uint8_t         csd_key[CESA_MAX_KEY_LEN];
  165         uint8_t         csd_iv[CESA_MAX_IV_LEN];
  166         uint8_t         csd_hiv_in[CESA_MAX_HASH_LEN];
  167         uint8_t         csd_hiv_out[CESA_MAX_HASH_LEN];
  168         uint8_t         csd_hash[CESA_MAX_HASH_LEN];
  169 };
  170 
  171 struct cesa_dma_mem {
  172         void            *cdm_vaddr;
  173         bus_addr_t      cdm_paddr;
  174         bus_dma_tag_t   cdm_tag;
  175         bus_dmamap_t    cdm_map;
  176 };
  177 
  178 struct cesa_tdma_desc {
  179         struct cesa_tdma_hdesc          *ctd_cthd;
  180         bus_addr_t                      ctd_cthd_paddr;
  181 
  182         STAILQ_ENTRY(cesa_tdma_desc)    ctd_stq;
  183 };
  184 
  185 struct cesa_sa_desc {
  186         struct cesa_sa_hdesc            *csd_cshd;
  187         bus_addr_t                      csd_cshd_paddr;
  188 
  189         STAILQ_ENTRY(cesa_sa_desc)      csd_stq;
  190 };
  191 
  192 struct cesa_session {
  193         uint32_t                        cs_config;
  194         unsigned int                    cs_ivlen;
  195         unsigned int                    cs_hlen;
  196         unsigned int                    cs_mblen;
  197         uint8_t                         cs_key[CESA_MAX_KEY_LEN];
  198         uint8_t                         cs_aes_dkey[CESA_MAX_KEY_LEN];
  199         uint8_t                         cs_hiv_in[CESA_MAX_HASH_LEN];
  200         uint8_t                         cs_hiv_out[CESA_MAX_HASH_LEN];
  201 };
  202 
  203 struct cesa_request {
  204         struct cesa_sa_data             *cr_csd;
  205         bus_addr_t                      cr_csd_paddr;
  206         struct cryptop                  *cr_crp;
  207         struct cesa_session             *cr_cs;
  208         bus_dmamap_t                    cr_dmap;
  209         int                             cr_dmap_loaded;
  210 
  211         STAILQ_HEAD(, cesa_tdma_desc)   cr_tdesc;
  212         STAILQ_HEAD(, cesa_sa_desc)     cr_sdesc;
  213 
  214         STAILQ_ENTRY(cesa_request)      cr_stq;
  215 };
  216 
  217 struct cesa_packet {
  218         STAILQ_HEAD(, cesa_tdma_desc)   cp_copyin;
  219         STAILQ_HEAD(, cesa_tdma_desc)   cp_copyout;
  220         unsigned int                    cp_size;
  221         unsigned int                    cp_offset;
  222 };
  223 
  224 struct cesa_softc {
  225         device_t                        sc_dev;
  226         int32_t                         sc_cid;
  227         uint32_t                        sc_soc_id;
  228         struct resource                 *sc_res[RES_CESA_NUM];
  229         void                            *sc_icookie;
  230         bus_dma_tag_t                   sc_data_dtag;
  231         int                             sc_error;
  232         int                             sc_tperr;
  233         uint8_t                         sc_cesa_engine_id;
  234 
  235         struct mtx                      sc_sc_lock;
  236         int                             sc_blocked;
  237 
  238         /* TDMA descriptors pool */
  239         struct mtx                      sc_tdesc_lock;
  240         struct cesa_tdma_desc           sc_tdesc[CESA_TDMA_DESCRIPTORS];
  241         struct cesa_dma_mem             sc_tdesc_cdm;
  242         STAILQ_HEAD(, cesa_tdma_desc)   sc_free_tdesc;
  243 
  244         /* SA descriptors pool */
  245         struct mtx                      sc_sdesc_lock;
  246         struct cesa_sa_desc             sc_sdesc[CESA_SA_DESCRIPTORS];
  247         struct cesa_dma_mem             sc_sdesc_cdm;
  248         STAILQ_HEAD(, cesa_sa_desc)     sc_free_sdesc;
  249 
  250         /* Requests pool */
  251         struct mtx                      sc_requests_lock;
  252         struct cesa_request             sc_requests[CESA_REQUESTS];
  253         struct cesa_dma_mem             sc_requests_cdm;
  254         STAILQ_HEAD(, cesa_request)     sc_free_requests;
  255         STAILQ_HEAD(, cesa_request)     sc_ready_requests;
  256         STAILQ_HEAD(, cesa_request)     sc_queued_requests;
  257 
  258         struct mtx                      sc_sessions_lock;
  259 
  260         /* CESA SRAM Address */
  261         bus_addr_t                      sc_sram_base_pa;
  262         void                            *sc_sram_base_va;
  263         bus_size_t                      sc_sram_size;
  264 };
  265 
  266 struct cesa_chain_info {
  267         struct cesa_softc               *cci_sc;
  268         struct cesa_request             *cci_cr;
  269         uint32_t                        cci_config;
  270         int                             cci_error;
  271 };
  272 
  273 /* CESA descriptors flags definitions */
  274 #define CESA_CTHD_OWNED                 (1 << 15)
  275 
  276 #define CESA_CSHD_MAC                   (0 << 0)
  277 #define CESA_CSHD_ENC                   (1 << 0)
  278 #define CESA_CSHD_MAC_AND_ENC           (2 << 0)
  279 #define CESA_CSHD_ENC_AND_MAC           (3 << 0)
  280 #define CESA_CSHD_OP_MASK               (3 << 0)
  281 
  282 #define CESA_CSHD_MD5                   (4 << 4)
  283 #define CESA_CSHD_SHA1                  (5 << 4)
  284 #define CESA_CSHD_SHA2_256              (1 << 4)
  285 #define CESA_CSHD_MD5_HMAC              (6 << 4)
  286 #define CESA_CSHD_SHA1_HMAC             (7 << 4)
  287 #define CESA_CSHD_SHA2_256_HMAC         (3 << 4)
  288 
  289 #define CESA_CSHD_96_BIT_HMAC           (1 << 7)
  290 
  291 #define CESA_CSHD_DES                   (1 << 8)
  292 #define CESA_CSHD_3DES                  (2 << 8)
  293 #define CESA_CSHD_AES                   (3 << 8)
  294 
  295 #define CESA_CSHD_DECRYPT               (1 << 12)
  296 #define CESA_CSHD_CBC                   (1 << 16)
  297 #define CESA_CSHD_3DES_EDE              (1 << 20)
  298 
  299 #define CESA_CSH_AES_KLEN_128           (0 << 24)
  300 #define CESA_CSH_AES_KLEN_192           (1 << 24)
  301 #define CESA_CSH_AES_KLEN_256           (2 << 24)
  302 #define CESA_CSH_AES_KLEN_MASK          (3 << 24)
  303 
  304 #define CESA_CSHD_FRAG_FIRST            (1 << 30)
  305 #define CESA_CSHD_FRAG_LAST             (2U << 30)
  306 #define CESA_CSHD_FRAG_MIDDLE           (3U << 30)
  307 
  308 /* CESA registers definitions */
  309 #define CESA_ICR                        0x0E20
  310 #define CESA_ICR_ACCTDMA                (1 << 7)
  311 #define CESA_ICR_TPERR                  (1 << 12)
  312 
  313 #define CESA_ICM                        0x0E24
  314 #define CESA_ICM_ACCTDMA                CESA_ICR_ACCTDMA
  315 #define CESA_ICM_TPERR                  CESA_ICR_TPERR
  316 
  317 /* CESA TDMA registers definitions */
  318 #define CESA_TDMA_ND                    0x0830
  319 
  320 #define CESA_TDMA_CR                    0x0840
  321 #define CESA_TDMA_CR_DBL128             (4 << 0)
  322 #define CESA_TDMA_CR_ORDEN              (1 << 4)
  323 #define CESA_TDMA_CR_SBL128             (4 << 6)
  324 #define CESA_TDMA_CR_NBS                (1 << 11)
  325 #define CESA_TDMA_CR_ENABLE             (1 << 12)
  326 #define CESA_TDMA_CR_FETCHND            (1 << 13)
  327 #define CESA_TDMA_CR_ACTIVE             (1 << 14)
  328 #define CESA_TDMA_NUM_OUTSTAND          (2 << 16)
  329 
  330 #define CESA_TDMA_ECR                   0x08C8
  331 #define CESA_TDMA_ECR_MISS              (1 << 0)
  332 #define CESA_TDMA_ECR_DOUBLE_HIT        (1 << 1)
  333 #define CESA_TDMA_ECR_BOTH_HIT          (1 << 2)
  334 #define CESA_TDMA_ECR_DATA_ERROR        (1 << 3)
  335 
  336 #define CESA_TDMA_EMR                   0x08CC
  337 #define CESA_TDMA_EMR_MISS              CESA_TDMA_ECR_MISS
  338 #define CESA_TDMA_EMR_DOUBLE_HIT        CESA_TDMA_ECR_DOUBLE_HIT
  339 #define CESA_TDMA_EMR_BOTH_HIT          CESA_TDMA_ECR_BOTH_HIT
  340 #define CESA_TDMA_EMR_DATA_ERROR        CESA_TDMA_ECR_DATA_ERROR
  341 
  342 /* CESA SA registers definitions */
  343 #define CESA_SA_CMD                     0x0E00
  344 #define CESA_SA_CMD_ACTVATE             (1 << 0)
  345 #define CESA_SA_CMD_SHA2                (1 << 31)
  346 
  347 #define CESA_SA_DPR                     0x0E04
  348 
  349 #define CESA_SA_CR                      0x0E08
  350 #define CESA_SA_CR_WAIT_FOR_TDMA        (1 << 7)
  351 #define CESA_SA_CR_ACTIVATE_TDMA        (1 << 9)
  352 #define CESA_SA_CR_MULTI_MODE           (1 << 11)
  353 
  354 #define CESA_SA_SR                      0x0E0C
  355 #define CESA_SA_SR_ACTIVE               (1 << 0)
  356 
  357 #define CESA_TDMA_SIZE                  0x1000
  358 #define CESA_CESA_SIZE                  0x1000
  359 #define CESA0_TDMA_ADDR                 0x90000
  360 #define CESA0_CESA_ADDR                 0x9D000
  361 #define CESA1_TDMA_ADDR                 0x92000
  362 #define CESA1_CESA_ADDR                 0x9F000
  363 #endif
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FreeBSD/Linux Kernel Cross Reference sys/dev/cesa/cesa.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/cesa/cesa.h
