The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/cfi/cfi_reg.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-3-Clause
    3  *
    4  * Copyright (c) 2007, Juniper Networks, Inc.
    5  * Copyright (c) 2012-2013, SRI International
    6  * All rights reserved.
    7  *
    8  * Portions of this software were developed by SRI International and the
    9  * University of Cambridge Computer Laboratory under DARPA/AFRL contract
   10  * (FA8750-10-C-0237) ("CTSRD"), as part of the DARPA CRASH research
   11  * programme.
   12  *
   13  * Redistribution and use in source and binary forms, with or without
   14  * modification, are permitted provided that the following conditions
   15  * are met:
   16  * 1. Redistributions of source code must retain the above copyright
   17  *    notice, this list of conditions and the following disclaimer.
   18  * 2. Redistributions in binary form must reproduce the above copyright
   19  *    notice, this list of conditions and the following disclaimer in the
   20  *    documentation and/or other materials provided with the distribution.
   21  * 3. Neither the name of the author nor the names of any co-contributors
   22  *    may be used to endorse or promote products derived from this software
   23  *    without specific prior written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   26  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   27  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   28  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   29  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
   30  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   31  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
   32  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   33  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   34  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   35  * SUCH DAMAGE.
   36  *
   37  * $FreeBSD: releng/12.0/sys/dev/cfi/cfi_reg.h 326022 2017-11-20 19:36:21Z pfg $
   38  */
   39 
   40 #ifndef _DEV_CFI_REG_H_
   41 #define _DEV_CFI_REG_H_
   42 
   43 struct cfi_qry {
   44         u_char          reserved[16];
   45         u_char          ident[3];       /* "QRY" */
   46         u_char          pri_vend[2];
   47         u_char          pri_vend_eqt[2];
   48         u_char          alt_vend[2];
   49         u_char          alt_vend_eqt[2];
   50         /* System Interface Information. */
   51         u_char          min_vcc;
   52         u_char          max_vcc;
   53         u_char          min_vpp;
   54         u_char          max_vpp;
   55         u_char          tto_byte_write;         /* 2**n microseconds. */
   56         u_char          tto_buf_write;          /* 2**n microseconds. */
   57         u_char          tto_block_erase;        /* 2**n milliseconds. */
   58         u_char          tto_chip_erase;         /* 2**n milliseconds. */
   59         u_char          mto_byte_write;         /* 2**n times typical t/o. */
   60         u_char          mto_buf_write;          /* 2**n times typical t/o. */
   61         u_char          mto_block_erase;        /* 2**n times typical t/o. */
   62         u_char          mto_chip_erase;         /* 2**n times typical t/o. */
   63         /* Device Geometry Definition. */
   64         u_char          size;                   /* 2**n bytes. */
   65         u_char          iface[2];
   66         u_char          max_buf_write_size[2];  /* 2**n. */
   67         u_char          nregions;               /* Number of erase regions. */
   68         u_char          region[4];              /* Single entry. */
   69         /* Additional entries follow. */
   70         /* Primary Vendor-specific Extended Query table follows. */
   71         /* Alternate Vendor-specific Extended Query table follows. */
   72 };
   73 
   74 #define CFI_QRY_CMD_ADDR        0x55
   75 #define CFI_QRY_CMD_DATA        0x98
   76 
   77 #define CFI_QRY_IDENT           offsetof(struct cfi_qry, ident)
   78 #define CFI_QRY_VEND            offsetof(struct cfi_qry, pri_vend)
   79 
   80 #define CFI_QRY_TTO_WRITE       offsetof(struct cfi_qry, tto_byte_write)
   81 #define CFI_QRY_TTO_BUFWRITE    offsetof(struct cfi_qry, tto_buf_write)
   82 #define CFI_QRY_TTO_ERASE       offsetof(struct cfi_qry, tto_block_erase)
   83 #define CFI_QRY_MTO_WRITE       offsetof(struct cfi_qry, mto_byte_write)
   84 #define CFI_QRY_MTO_BUFWRITE    offsetof(struct cfi_qry, mto_buf_write)
   85 #define CFI_QRY_MTO_ERASE       offsetof(struct cfi_qry, mto_block_erase)
   86 
   87 #define CFI_QRY_SIZE            offsetof(struct cfi_qry, size)
   88 #define CFI_QRY_IFACE           offsetof(struct cfi_qry, iface)
   89 #define CFI_QRY_MAXBUF          offsetof(struct cfi_qry, max_buf_write_size)
   90 #define CFI_QRY_NREGIONS        offsetof(struct cfi_qry, nregions)
   91 #define CFI_QRY_REGION0         offsetof(struct cfi_qry, region)
   92 #define CFI_QRY_REGION(x)       (CFI_QRY_REGION0 + (x) * 4)
   93 
   94 #define CFI_VEND_NONE           0x0000
   95 #define CFI_VEND_INTEL_ECS      0x0001
   96 #define CFI_VEND_AMD_SCS        0x0002
   97 #define CFI_VEND_INTEL_SCS      0x0003
   98 #define CFI_VEND_AMD_ECS        0x0004
   99 #define CFI_VEND_MITSUBISHI_SCS 0x0100
  100 #define CFI_VEND_MITSUBISHI_ECS 0x0101
  101 
  102 #define CFI_IFACE_X8            0x0000
  103 #define CFI_IFACE_X16           0x0001
  104 #define CFI_IFACE_X8X16         0x0002
  105 #define CFI_IFACE_X32           0x0003
  106 #define CFI_IFACE_X16X32        0x0005
  107 
  108 /* Standard Command Set (aka Basic Command Set) */
  109 #define CFI_BCS_BLOCK_ERASE     0x20
  110 #define CFI_BCS_PROGRAM         0x40
  111 #define CFI_BCS_CLEAR_STATUS    0x50
  112 #define CFI_BCS_READ_STATUS     0x70
  113 #define CFI_BCS_ERASE_SUSPEND   0xb0
  114 #define CFI_BCS_ERASE_RESUME    0xd0    /* Equals CONFIRM */
  115 #define CFI_BCS_CONFIRM         0xd0
  116 #define CFI_BCS_BUF_PROG_SETUP  0xe8
  117 #define CFI_BCS_READ_ARRAY      0xff
  118 #define CFI_BCS_READ_ARRAY2     0xf0
  119 
  120 /* Intel commands. */
  121 #define CFI_INTEL_LB            0x01    /* Lock Block */
  122 #define CFI_INTEL_LBS           0x60    /* Lock Block Setup */
  123 #define CFI_INTEL_READ_ID       0x90    /* Read Identifier */
  124 #define CFI_INTEL_PP_SETUP      0xc0    /* Protection Program Setup */
  125 #define CFI_INTEL_UB            0xd0    /* Unlock Block */
  126 
  127 /* NB: these are addresses for 16-bit accesses */
  128 #define CFI_INTEL_PLR           0x80    /* Protection Lock Register */
  129 #define CFI_INTEL_PR(n)         (0x81+(n)) /* Protection Register */
  130 
  131 /* Status register definitions */
  132 #define CFI_INTEL_STATUS_WSMS   0x0080  /* Write Machine Status */
  133 #define CFI_INTEL_STATUS_ESS    0x0040  /* Erase Suspend Status */
  134 #define CFI_INTEL_STATUS_ECLBS  0x0020  /* Erase and Clear Lock-Bit Status */
  135 #define CFI_INTEL_STATUS_PSLBS  0x0010  /* Program and Set Lock-Bit Status */
  136 #define CFI_INTEL_STATUS_VPENS  0x0008  /* Programming Voltage Status */
  137 #define CFI_INTEL_STATUS_PSS    0x0004  /* Program Suspend Status */
  138 #define CFI_INTEL_STATUS_DPS    0x0002  /* Device Protect Status */
  139 #define CFI_INTEL_STATUS_RSVD   0x0001  /* reserved */
  140 
  141 /* eXtended Status register definitions */
  142 #define CFI_INTEL_XSTATUS_WBS   0x8000  /* Write Buffer Status */
  143 #define CFI_INTEL_XSTATUS_RSVD  0x7f00  /* reserved */
  144 
  145 /* AMD commands. */
  146 #define CFI_AMD_BLOCK_ERASE     0x30
  147 #define CFI_AMD_UNLOCK_ACK      0x55
  148 #define CFI_AMD_ERASE_SECTOR    0x80
  149 #define CFI_AMD_PROGRAM         0xa0
  150 #define CFI_AMD_UNLOCK          0xaa
  151 
  152 #define AMD_ADDR_START          0xaaa
  153 #define AMD_ADDR_ACK            0x555
  154 
  155 #endif /* _DEV_CFI_REG_H_ */

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