coretemp.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   18  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   19  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
   20  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   22  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   24  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
   25  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   26  * POSSIBILITY OF SUCH DAMAGE.
   27  */
   28 
   29 /*
   30  * Device driver for Intel's On Die thermal sensor via MSR.
   31  * First introduced in Intel's Core line of processors.
   32  */
   33 
   34 #include <sys/cdefs.h>
   35 __FBSDID("$FreeBSD$");
   36 
   37 #include <sys/param.h>
   38 #include <sys/bus.h>
   39 #include <sys/conf.h>
   40 #include <sys/kernel.h>
   41 #include <sys/lock.h>
   42 #include <sys/module.h>
   43 #include <sys/mutex.h>
   44 #include <sys/proc.h>   /* for curthread */
   45 #include <sys/smp.h>
   46 #include <sys/sysctl.h>
   47 #include <sys/systm.h>
   48 
   49 #include <machine/specialreg.h>
   50 #include <machine/cpufunc.h>
   51 #include <machine/cputypes.h>
   52 #include <machine/md_var.h>
   53 
   54 #define TZ_ZEROC                        2731
   55 
   56 #define THERM_STATUS_LOG                0x02
   57 #define THERM_STATUS                    0x01
   58 #define THERM_STATUS_TEMP_SHIFT         16
   59 #define THERM_STATUS_TEMP_MASK          0x7f
   60 #define THERM_STATUS_RES_SHIFT          27
   61 #define THERM_STATUS_RES_MASK           0x0f
   62 #define THERM_STATUS_VALID_SHIFT        31
   63 #define THERM_STATUS_VALID_MASK         0x01
   64 
   65 struct coretemp_softc {
   66         device_t        sc_dev;
   67         int             sc_tjmax;
   68         unsigned int    sc_throttle_log;
   69 };
   70 
   71 /*
   72  * Device methods.
   73  */
   74 static void     coretemp_identify(driver_t *driver, device_t parent);
   75 static int      coretemp_probe(device_t dev);
   76 static int      coretemp_attach(device_t dev);
   77 static int      coretemp_detach(device_t dev);
   78 
   79 static uint64_t coretemp_get_thermal_msr(int cpu);
   80 static void     coretemp_clear_thermal_msr(int cpu);
   81 static int      coretemp_get_val_sysctl(SYSCTL_HANDLER_ARGS);
   82 static int      coretemp_throttle_log_sysctl(SYSCTL_HANDLER_ARGS);
   83 
   84 static device_method_t coretemp_methods[] = {
   85         /* Device interface */
   86         DEVMETHOD(device_identify,      coretemp_identify),
   87         DEVMETHOD(device_probe,         coretemp_probe),
   88         DEVMETHOD(device_attach,        coretemp_attach),
   89         DEVMETHOD(device_detach,        coretemp_detach),
   90 
   91         DEVMETHOD_END
   92 };
   93 
   94 static driver_t coretemp_driver = {
   95         "coretemp",
   96         coretemp_methods,
   97         sizeof(struct coretemp_softc),
   98 };
   99 
  100 enum therm_info {
  101         CORETEMP_TEMP,
  102         CORETEMP_DELTA,
  103         CORETEMP_RESOLUTION,
  104         CORETEMP_TJMAX,
  105 };
  106 
  107 DRIVER_MODULE(coretemp, cpu, coretemp_driver, NULL, NULL);
  108 
  109 static void
  110 coretemp_identify(driver_t *driver, device_t parent)
  111 {
  112         device_t child;
  113         u_int regs[4];
  114 
  115         /* Make sure we're not being doubly invoked. */
  116         if (device_find_child(parent, "coretemp", -1) != NULL)
  117                 return;
  118 
  119         /* Check that CPUID 0x06 is supported and the vendor is Intel.*/
  120         if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL)
  121                 return;
  122         /*
  123          * CPUID 0x06 returns 1 if the processor has on-die thermal
  124          * sensors. EBX[0:3] contains the number of sensors.
  125          */
  126         do_cpuid(0x06, regs);
  127         if ((regs[0] & 0x1) != 1)
  128                 return;
  129 
  130         /*
  131          * We add a child for each CPU since settings must be performed
  132          * on each CPU in the SMP case.
  133          */
  134         child = device_add_child(parent, "coretemp", device_get_unit(parent));
  135         if (child == NULL)
  136                 device_printf(parent, "add coretemp child failed\n");
  137 }
  138 
  139 static int
  140 coretemp_probe(device_t dev)
  141 {
  142         if (resource_disabled("coretemp", 0))
  143                 return (ENXIO);
  144 
  145         device_set_desc(dev, "CPU On-Die Thermal Sensors");
  146 
  147         if (!bootverbose && device_get_unit(dev) != 0)
  148                 device_quiet(dev);
  149 
  150         return (BUS_PROBE_GENERIC);
  151 }
  152 
  153 static int
  154 coretemp_attach(device_t dev)
  155 {
  156         struct coretemp_softc *sc = device_get_softc(dev);
  157         device_t pdev;
  158         uint64_t msr;
  159         int cpu_model, cpu_stepping;
  160         int ret, tjtarget;
  161         struct sysctl_oid *oid;
  162         struct sysctl_ctx_list *ctx;
  163 
  164         sc->sc_dev = dev;
  165         pdev = device_get_parent(dev);
  166         cpu_model = CPUID_TO_MODEL(cpu_id);
  167         cpu_stepping = CPUID_TO_STEPPING(cpu_id);
  168 
  169         /*
  170          * Some CPUs, namely the PIII, don't have thermal sensors, but
  171          * report them when the CPUID check is performed in
  172          * coretemp_identify(). This leads to a later GPF when the sensor
  173          * is queried via a MSR, so we stop here.
  174          */
  175         if (cpu_model < 0xe)
  176                 return (ENXIO);
  177 
  178 #if 0 /*
  179        * XXXrpaulo: I have this CPU model and when it returns from C3
  180        * coretemp continues to function properly.
  181        */
  182          
  183         /*
  184          * Check for errata AE18.
  185          * "Processor Digital Thermal Sensor (DTS) Readout stops
  186          *  updating upon returning from C3/C4 state."
  187          *
  188          * Adapted from the Linux coretemp driver.
  189          */
  190         if (cpu_model == 0xe && cpu_stepping < 0xc) {
  191                 msr = rdmsr(MSR_BIOS_SIGN);
  192                 msr = msr >> 32;
  193                 if (msr < 0x39) {
  194                         device_printf(dev, "not supported (Intel errata "
  195                             "AE18), try updating your BIOS\n");
  196                         return (ENXIO);
  197                 }
  198         }
  199 #endif
  200 
  201         /*
  202          * Use 100C as the initial value.
  203          */
  204         sc->sc_tjmax = 100;
  205 
  206         if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) {
  207                 /*
  208                  * On some Core 2 CPUs, there's an undocumented MSR that
  209                  * can tell us if Tj(max) is 100 or 85.
  210                  *
  211                  * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted
  212                  * from the Linux coretemp driver.
  213                  */
  214                 msr = rdmsr(MSR_IA32_EXT_CONFIG);
  215                 if (msr & (1 << 30))
  216                         sc->sc_tjmax = 85;
  217         } else if (cpu_model == 0x17) {
  218                 switch (cpu_stepping) {
  219                 case 0x6:       /* Mobile Core 2 Duo */
  220                         sc->sc_tjmax = 105;
  221                         break;
  222                 default:        /* Unknown stepping */
  223                         break;
  224                 }
  225         } else if (cpu_model == 0x1c) {
  226                 switch (cpu_stepping) {
  227                 case 0xa:       /* 45nm Atom D400, N400 and D500 series */
  228                         sc->sc_tjmax = 100;
  229                         break;
  230                 default:
  231                         sc->sc_tjmax = 90;
  232                         break;
  233                 }
  234         } else {
  235                 /*
  236                  * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
  237                  *
  238                  * This method is described in Intel white paper "CPU
  239                  * Monitoring With DTS/PECI". (#322683)
  240                  */
  241                 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
  242                 if (ret == 0) {
  243                         tjtarget = (msr >> 16) & 0xff;
  244 
  245                         /*
  246                          * On earlier generation of processors, the value
  247                          * obtained from IA32_TEMPERATURE_TARGET register is
  248                          * an offset that needs to be summed with a model
  249                          * specific base.  It is however not clear what
  250                          * these numbers are, with the publicly available
  251                          * documents from Intel.
  252                          *
  253                          * For now, we consider [70, 110]C range, as
  254                          * described in #322683, as "reasonable" and accept
  255                          * these values whenever the MSR is available for
  256                          * read, regardless the CPU model.
  257                          */
  258                         if (tjtarget >= 70 && tjtarget <= 110)
  259                                 sc->sc_tjmax = tjtarget;
  260                         else
  261                                 device_printf(dev, "Tj(target) value %d "
  262                                     "does not seem right.\n", tjtarget);
  263                 } else
  264                         device_printf(dev, "Can not get Tj(target) "
  265                             "from your CPU, using 100C.\n");
  266         }
  267 
  268         if (bootverbose)
  269                 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax);
  270 
  271         ctx = device_get_sysctl_ctx(dev);
  272 
  273         oid = SYSCTL_ADD_NODE(ctx,
  274             SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)), OID_AUTO,
  275             "coretemp", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
  276             "Per-CPU thermal information");
  277 
  278         /*
  279          * Add the MIBs to dev.cpu.N and dev.cpu.N.coretemp.
  280          */
  281         SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)),
  282             OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
  283             dev, CORETEMP_TEMP, coretemp_get_val_sysctl, "IK",
  284             "Current temperature");
  285         SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "delta",
  286             CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_DELTA,
  287             coretemp_get_val_sysctl, "I",
  288             "Delta between TCC activation and current temperature");
  289         SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "resolution",
  290             CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_RESOLUTION,
  291             coretemp_get_val_sysctl, "I",
  292             "Resolution of CPU thermal sensor");
  293         SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "tjmax",
  294             CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_TJMAX,
  295             coretemp_get_val_sysctl, "IK",
  296             "TCC activation temperature");
  297         SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
  298             "throttle_log", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev, 0,
  299             coretemp_throttle_log_sysctl, "I",
  300             "Set to 1 if the thermal sensor has tripped");
  301 
  302         return (0);
  303 }
  304 
  305 static int
  306 coretemp_detach(device_t dev)
  307 {
  308         return (0);
  309 }
  310 
  311 struct coretemp_args {
  312         u_int           msr;
  313         uint64_t        val;
  314 };
  315 
  316 /*
  317  * The digital temperature reading is located at bit 16
  318  * of MSR_THERM_STATUS.
  319  *
  320  * There is a bit on that MSR that indicates whether the
  321  * temperature is valid or not.
  322  *
  323  * The temperature is computed by subtracting the temperature
  324  * reading by Tj(max).
  325  */
  326 static uint64_t
  327 coretemp_get_thermal_msr(int cpu)
  328 {
  329         uint64_t res;
  330 
  331         x86_msr_op(MSR_THERM_STATUS, MSR_OP_RENDEZVOUS_ONE | MSR_OP_READ |
  332             MSR_OP_CPUID(cpu), 0, &res);
  333         return (res);
  334 }
  335 
  336 static void
  337 coretemp_clear_thermal_msr(int cpu)
  338 {
  339         x86_msr_op(MSR_THERM_STATUS, MSR_OP_RENDEZVOUS_ONE | MSR_OP_WRITE |
  340             MSR_OP_CPUID(cpu), 0, NULL);
  341 }
  342 
  343 static int
  344 coretemp_get_val_sysctl(SYSCTL_HANDLER_ARGS)
  345 {
  346         device_t dev;
  347         uint64_t msr;
  348         int val, tmp;
  349         struct coretemp_softc *sc;
  350         enum therm_info type;
  351         char stemp[16];
  352 
  353         dev = (device_t) arg1;
  354         msr = coretemp_get_thermal_msr(device_get_unit(dev));
  355         sc = device_get_softc(dev);
  356         type = arg2;
  357 
  358         if (((msr >> THERM_STATUS_VALID_SHIFT) & THERM_STATUS_VALID_MASK) != 1) {
  359                 val = -1;
  360         } else {
  361                 switch (type) {
  362                 case CORETEMP_TEMP:
  363                         tmp = (msr >> THERM_STATUS_TEMP_SHIFT) &
  364                             THERM_STATUS_TEMP_MASK;
  365                         val = (sc->sc_tjmax - tmp) * 10 + TZ_ZEROC;
  366                         break;
  367                 case CORETEMP_DELTA:
  368                         val = (msr >> THERM_STATUS_TEMP_SHIFT) &
  369                             THERM_STATUS_TEMP_MASK;
  370                         break;
  371                 case CORETEMP_RESOLUTION:
  372                         val = (msr >> THERM_STATUS_RES_SHIFT) &
  373                             THERM_STATUS_RES_MASK;
  374                         break;
  375                 case CORETEMP_TJMAX:
  376                         val = sc->sc_tjmax * 10 + TZ_ZEROC;
  377                         break;
  378                 }
  379         }
  380 
  381         if (msr & THERM_STATUS_LOG) {
  382                 coretemp_clear_thermal_msr(device_get_unit(dev));
  383                 sc->sc_throttle_log = 1;
  384 
  385                 /*
  386                  * Check for Critical Temperature Status and Critical
  387                  * Temperature Log.  It doesn't really matter if the
  388                  * current temperature is invalid because the "Critical
  389                  * Temperature Log" bit will tell us if the Critical
  390                  * Temperature has * been reached in past. It's not
  391                  * directly related to the current temperature.
  392                  *
  393                  * If we reach a critical level, allow devctl(4)
  394                  * to catch this and shutdown the system.
  395                  */
  396                 if (msr & THERM_STATUS) {
  397                         tmp = (msr >> THERM_STATUS_TEMP_SHIFT) &
  398                             THERM_STATUS_TEMP_MASK;
  399                         tmp = (sc->sc_tjmax - tmp) * 10 + TZ_ZEROC;
  400                         device_printf(dev, "critical temperature detected, "
  401                             "suggest system shutdown\n");
  402                         snprintf(stemp, sizeof(stemp), "%d", tmp);
  403                         devctl_notify("coretemp", "Thermal", stemp,
  404                             "notify=0xcc");
  405                 }
  406         }
  407 
  408         return (sysctl_handle_int(oidp, &val, 0, req));
  409 }
  410 
  411 static int
  412 coretemp_throttle_log_sysctl(SYSCTL_HANDLER_ARGS)
  413 {
  414         device_t dev;
  415         uint64_t msr;
  416         int error, val;
  417         struct coretemp_softc *sc;
  418 
  419         dev = (device_t) arg1;
  420         msr = coretemp_get_thermal_msr(device_get_unit(dev));
  421         sc = device_get_softc(dev);
  422 
  423         if (msr & THERM_STATUS_LOG) {
  424                 coretemp_clear_thermal_msr(device_get_unit(dev));
  425                 sc->sc_throttle_log = 1;
  426         }
  427 
  428         val = sc->sc_throttle_log;
  429 
  430         error = sysctl_handle_int(oidp, &val, 0, req);
  431 
  432         if (error || !req->newptr)
  433                 return (error);
  434         else if (val != 0)
  435                 return (EINVAL);
  436 
  437         coretemp_clear_thermal_msr(device_get_unit(dev));
  438         sc->sc_throttle_log = 0;
  439 
  440         return (0);
  441 }
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FreeBSD/Linux Kernel Cross Reference sys/dev/coretemp/coretemp.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/coretemp/coretemp.c
