The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/coretemp/coretemp.c

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    1 /*-
    2  * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   16  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   17  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
   18  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   19  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   20  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   22  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
   23  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   24  * POSSIBILITY OF SUCH DAMAGE.
   25  */
   26 
   27 /*
   28  * Device driver for Intel's On Die thermal sensor via MSR.
   29  * First introduced in Intel's Core line of processors.
   30  */
   31 
   32 #include <sys/cdefs.h>
   33 __FBSDID("$FreeBSD: stable/7/sys/dev/coretemp/coretemp.c 212007 2010-08-30 18:53:12Z delphij $");
   34 
   35 #include <sys/param.h>
   36 #include <sys/bus.h>
   37 #include <sys/systm.h>
   38 #include <sys/types.h>
   39 #include <sys/module.h>
   40 #include <sys/conf.h>
   41 #include <sys/kernel.h>
   42 #include <sys/sysctl.h>
   43 #include <sys/proc.h>   /* for curthread */
   44 #include <sys/sched.h>
   45 
   46 #include <machine/specialreg.h>
   47 #include <machine/cpufunc.h>
   48 #include <machine/cputypes.h>
   49 #include <machine/md_var.h>
   50 
   51 struct coretemp_softc {
   52         device_t        sc_dev;
   53         int             sc_tjmax;
   54         struct sysctl_oid *sc_oid;
   55 };
   56 
   57 /*
   58  * Device methods.
   59  */
   60 static void     coretemp_identify(driver_t *driver, device_t parent);
   61 static int      coretemp_probe(device_t dev);
   62 static int      coretemp_attach(device_t dev);
   63 static int      coretemp_detach(device_t dev);
   64 
   65 static int      coretemp_get_temp(device_t dev);
   66 static int      coretemp_get_temp_sysctl(SYSCTL_HANDLER_ARGS);
   67 
   68 static device_method_t coretemp_methods[] = {
   69         /* Device interface */
   70         DEVMETHOD(device_identify,      coretemp_identify),
   71         DEVMETHOD(device_probe,         coretemp_probe),
   72         DEVMETHOD(device_attach,        coretemp_attach),
   73         DEVMETHOD(device_detach,        coretemp_detach),
   74 
   75         {0, 0}
   76 };
   77 
   78 static driver_t coretemp_driver = {
   79         "coretemp",
   80         coretemp_methods,
   81         sizeof(struct coretemp_softc),
   82 };
   83 
   84 static devclass_t coretemp_devclass;
   85 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL);
   86 
   87 static void
   88 coretemp_identify(driver_t *driver, device_t parent)
   89 {
   90         device_t child;
   91         u_int regs[4];
   92 
   93         /* Make sure we're not being doubly invoked. */
   94         if (device_find_child(parent, "coretemp", -1) != NULL)
   95                 return;
   96 
   97         /* Check that CPUID 0x06 is supported and the vendor is Intel.*/
   98         if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL)
   99                 return;
  100         /*
  101          * CPUID 0x06 returns 1 if the processor has on-die thermal
  102          * sensors. EBX[0:3] contains the number of sensors.
  103          */
  104         do_cpuid(0x06, regs);
  105         if ((regs[0] & 0x1) != 1)
  106                 return;
  107 
  108         /*
  109          * We add a child for each CPU since settings must be performed
  110          * on each CPU in the SMP case.
  111          */
  112         child = device_add_child(parent, "coretemp", -1);
  113         if (child == NULL)
  114                 device_printf(parent, "add coretemp child failed\n");
  115 }
  116 
  117 static int
  118 coretemp_probe(device_t dev)
  119 {
  120         if (resource_disabled("coretemp", 0))
  121                 return (ENXIO);
  122 
  123         device_set_desc(dev, "CPU On-Die Thermal Sensors");
  124 
  125         return (BUS_PROBE_GENERIC);
  126 }
  127 
  128 static int
  129 coretemp_attach(device_t dev)
  130 {
  131         struct coretemp_softc *sc = device_get_softc(dev);
  132         device_t pdev;
  133         uint64_t msr;
  134         int cpu_model, cpu_stepping;
  135         int ret, tjtarget;
  136 
  137         sc->sc_dev = dev;
  138         pdev = device_get_parent(dev);
  139         cpu_model = CPUID_TO_MODEL(cpu_id);
  140         cpu_stepping = cpu_id & CPUID_STEPPING;
  141 
  142         /*
  143          * Some CPUs, namely the PIII, don't have thermal sensors, but
  144          * report them when the CPUID check is performed in
  145          * coretemp_identify(). This leads to a later GPF when the sensor
  146          * is queried via a MSR, so we stop here.
  147          */
  148         if (cpu_model < 0xe)
  149                 return (ENXIO);
  150 
  151         /*
  152          * Check for errata AE18.
  153          * "Processor Digital Thermal Sensor (DTS) Readout stops
  154          *  updating upon returning from C3/C4 state."
  155          *
  156          * Adapted from the Linux coretemp driver.
  157          */
  158         if (cpu_model == 0xe && cpu_stepping < 0xc) {
  159                 msr = rdmsr(MSR_BIOS_SIGN);
  160                 msr = msr >> 32;
  161                 if (msr < 0x39) {
  162                         device_printf(dev, "not supported (Intel errata "
  163                             "AE18), try updating your BIOS\n");
  164                         return (ENXIO);
  165                 }
  166         }
  167 
  168         /*
  169          * Use 100C as the initial value.
  170          */
  171         sc->sc_tjmax = 100;
  172 
  173         if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) {
  174                 /*
  175                  * On some Core 2 CPUs, there's an undocumented MSR that
  176                  * can tell us if Tj(max) is 100 or 85.
  177                  *
  178                  * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted
  179                  * from the Linux coretemp driver.
  180                  */
  181                 msr = rdmsr(MSR_IA32_EXT_CONFIG);
  182                 if (msr & (1 << 30))
  183                         sc->sc_tjmax = 85;
  184         } else if (cpu_model == 0x17) {
  185                 switch (cpu_stepping) {
  186                 case 0x6:       /* Mobile Core 2 Duo */
  187                         sc->sc_tjmax = 104;
  188                         break;
  189                 default:        /* Unknown stepping */
  190                         break;
  191                 }
  192         } else {
  193                 /*
  194                  * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
  195                  *
  196                  * This method is described in Intel white paper "CPU
  197                  * Monitoring With DTS/PECI". (#322683)
  198                  */
  199                 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
  200                 if (ret == 0) {
  201                         tjtarget = (msr >> 16) & 0xff;
  202                         
  203                         /*
  204                          * On earlier generation of processors, the value
  205                          * obtained from IA32_TEMPERATURE_TARGET register is
  206                          * an offset that needs to be summed with a model
  207                          * specific base.  It is however not clear what
  208                          * these numbers are, with the publicly available
  209                          * documents from Intel.
  210                          *
  211                          * For now, we consider [70, 100]C range, as
  212                          * described in #322683, as "reasonable" and accept
  213                          * these values whenever the MSR is available for
  214                          * read, regardless the CPU model.
  215                          */
  216                         if (tjtarget >= 70 && tjtarget <= 100)
  217                                 sc->sc_tjmax = tjtarget;
  218                         else
  219                                 device_printf(dev, "Tj(target) value %d "
  220                                     "does not seem right.\n", tjtarget);
  221                 } else
  222                         device_printf(dev, "Can not get Tj(target) "
  223                             "from your CPU, using 100C.\n");
  224         }
  225 
  226         if (bootverbose)
  227                 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax);
  228 
  229         /*
  230          * Add the "temperature" MIB to dev.cpu.N.
  231          */
  232         sc->sc_oid = SYSCTL_ADD_PROC(device_get_sysctl_ctx(pdev),
  233             SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)),
  234             OID_AUTO, "temperature",
  235             CTLTYPE_INT | CTLFLAG_RD,
  236             dev, 0, coretemp_get_temp_sysctl, "I",
  237             "Current temperature in degC");
  238 
  239         return (0);
  240 }
  241 
  242 static int
  243 coretemp_detach(device_t dev)
  244 {
  245         struct coretemp_softc *sc = device_get_softc(dev);
  246 
  247         sysctl_remove_oid(sc->sc_oid, 1, 0);
  248 
  249         return (0);
  250 }
  251 
  252 
  253 static int
  254 coretemp_get_temp(device_t dev)
  255 {
  256         uint64_t msr;
  257         int temp;
  258         int cpu = device_get_unit(dev);
  259         struct coretemp_softc *sc = device_get_softc(dev);
  260         char stemp[16];
  261 
  262         thread_lock(curthread);
  263         sched_bind(curthread, cpu);
  264         thread_unlock(curthread);
  265 
  266         /*
  267          * The digital temperature reading is located at bit 16
  268          * of MSR_THERM_STATUS.
  269          *
  270          * There is a bit on that MSR that indicates whether the
  271          * temperature is valid or not.
  272          *
  273          * The temperature is computed by subtracting the temperature
  274          * reading by Tj(max).
  275          */
  276         msr = rdmsr(MSR_THERM_STATUS);
  277 
  278         thread_lock(curthread);
  279         sched_unbind(curthread);
  280         thread_unlock(curthread);
  281 
  282         /*
  283          * Check for Thermal Status and Thermal Status Log.
  284          */
  285         if ((msr & 0x3) == 0x3)
  286                 device_printf(dev, "PROCHOT asserted\n");
  287 
  288         /*
  289          * Bit 31 contains "Reading valid"
  290          */
  291         if (((msr >> 31) & 0x1) == 1) {
  292                 /*
  293                  * Starting on bit 16 and ending on bit 22.
  294                  */
  295                 temp = sc->sc_tjmax - ((msr >> 16) & 0x7f);
  296         } else
  297                 temp = -1;
  298 
  299         /*
  300          * Check for Critical Temperature Status and Critical
  301          * Temperature Log.
  302          * It doesn't really matter if the current temperature is
  303          * invalid because the "Critical Temperature Log" bit will
  304          * tell us if the Critical Temperature has been reached in
  305          * past. It's not directly related to the current temperature.
  306          *
  307          * If we reach a critical level, allow devctl(4) to catch this
  308          * and shutdown the system.
  309          */
  310         if (((msr >> 4) & 0x3) == 0x3) {
  311                 device_printf(dev, "critical temperature detected, "
  312                     "suggest system shutdown\n");
  313                 snprintf(stemp, sizeof(stemp), "%d", temp);
  314                 devctl_notify("coretemp", "Thermal", stemp, "notify=0xcc");
  315         }
  316 
  317         return (temp);
  318 }
  319 
  320 static int
  321 coretemp_get_temp_sysctl(SYSCTL_HANDLER_ARGS)
  322 {
  323         device_t dev = (device_t) arg1;
  324         int temp;
  325 
  326         temp = coretemp_get_temp(dev);
  327 
  328         return (sysctl_handle_int(oidp, &temp, 0, req));
  329 }

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