The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/dev/coretemp/coretemp.c

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   16  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   17  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
   18  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   19  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   20  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   22  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
   23  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   24  * POSSIBILITY OF SUCH DAMAGE.
   25  */
   26 
   27 /*
   28  * Device driver for Intel's On Die thermal sensor via MSR.
   29  * First introduced in Intel's Core line of processors.
   30  */
   31 
   32 #include <sys/cdefs.h>
   33 __FBSDID("$FreeBSD: releng/8.2/sys/dev/coretemp/coretemp.c 211914 2010-08-28 00:48:40Z delphij $");
   34 
   35 #include <sys/param.h>
   36 #include <sys/bus.h>
   37 #include <sys/systm.h>
   38 #include <sys/types.h>
   39 #include <sys/module.h>
   40 #include <sys/conf.h>
   41 #include <sys/kernel.h>
   42 #include <sys/sysctl.h>
   43 #include <sys/proc.h>   /* for curthread */
   44 #include <sys/sched.h>
   45 
   46 #include <machine/specialreg.h>
   47 #include <machine/cpufunc.h>
   48 #include <machine/cputypes.h>
   49 #include <machine/md_var.h>
   50 
   51 #define TZ_ZEROC        2732
   52 
   53 struct coretemp_softc {
   54         device_t        sc_dev;
   55         int             sc_tjmax;
   56         struct sysctl_oid *sc_oid;
   57 };
   58 
   59 /*
   60  * Device methods.
   61  */
   62 static void     coretemp_identify(driver_t *driver, device_t parent);
   63 static int      coretemp_probe(device_t dev);
   64 static int      coretemp_attach(device_t dev);
   65 static int      coretemp_detach(device_t dev);
   66 
   67 static int      coretemp_get_temp(device_t dev);
   68 static int      coretemp_get_temp_sysctl(SYSCTL_HANDLER_ARGS);
   69 
   70 static device_method_t coretemp_methods[] = {
   71         /* Device interface */
   72         DEVMETHOD(device_identify,      coretemp_identify),
   73         DEVMETHOD(device_probe,         coretemp_probe),
   74         DEVMETHOD(device_attach,        coretemp_attach),
   75         DEVMETHOD(device_detach,        coretemp_detach),
   76 
   77         {0, 0}
   78 };
   79 
   80 static driver_t coretemp_driver = {
   81         "coretemp",
   82         coretemp_methods,
   83         sizeof(struct coretemp_softc),
   84 };
   85 
   86 static devclass_t coretemp_devclass;
   87 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL);
   88 
   89 static void
   90 coretemp_identify(driver_t *driver, device_t parent)
   91 {
   92         device_t child;
   93         u_int regs[4];
   94 
   95         /* Make sure we're not being doubly invoked. */
   96         if (device_find_child(parent, "coretemp", -1) != NULL)
   97                 return;
   98 
   99         /* Check that CPUID 0x06 is supported and the vendor is Intel.*/
  100         if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL)
  101                 return;
  102         /*
  103          * CPUID 0x06 returns 1 if the processor has on-die thermal
  104          * sensors. EBX[0:3] contains the number of sensors.
  105          */
  106         do_cpuid(0x06, regs);
  107         if ((regs[0] & 0x1) != 1)
  108                 return;
  109 
  110         /*
  111          * We add a child for each CPU since settings must be performed
  112          * on each CPU in the SMP case.
  113          */
  114         child = device_add_child(parent, "coretemp", -1);
  115         if (child == NULL)
  116                 device_printf(parent, "add coretemp child failed\n");
  117 }
  118 
  119 static int
  120 coretemp_probe(device_t dev)
  121 {
  122         if (resource_disabled("coretemp", 0))
  123                 return (ENXIO);
  124 
  125         device_set_desc(dev, "CPU On-Die Thermal Sensors");
  126 
  127         return (BUS_PROBE_GENERIC);
  128 }
  129 
  130 static int
  131 coretemp_attach(device_t dev)
  132 {
  133         struct coretemp_softc *sc = device_get_softc(dev);
  134         device_t pdev;
  135         uint64_t msr;
  136         int cpu_model, cpu_stepping;
  137         int ret, tjtarget;
  138 
  139         sc->sc_dev = dev;
  140         pdev = device_get_parent(dev);
  141         cpu_model = CPUID_TO_MODEL(cpu_id);
  142         cpu_stepping = cpu_id & CPUID_STEPPING;
  143 
  144         /*
  145          * Some CPUs, namely the PIII, don't have thermal sensors, but
  146          * report them when the CPUID check is performed in
  147          * coretemp_identify(). This leads to a later GPF when the sensor
  148          * is queried via a MSR, so we stop here.
  149          */
  150         if (cpu_model < 0xe)
  151                 return (ENXIO);
  152         
  153 #if 0 /*
  154        * XXXrpaulo: I have this CPU model and when it returns from C3
  155        * coretemp continues to function properly.
  156        */
  157          
  158         /*
  159          * Check for errata AE18.
  160          * "Processor Digital Thermal Sensor (DTS) Readout stops
  161          *  updating upon returning from C3/C4 state."
  162          *
  163          * Adapted from the Linux coretemp driver.
  164          */
  165         if (cpu_model == 0xe && cpu_stepping < 0xc) {
  166                 msr = rdmsr(MSR_BIOS_SIGN);
  167                 msr = msr >> 32;
  168                 if (msr < 0x39) {
  169                         device_printf(dev, "not supported (Intel errata "
  170                             "AE18), try updating your BIOS\n");
  171                         return (ENXIO);
  172                 }
  173         }
  174 #endif
  175 
  176         /*
  177          * Use 100C as the initial value.
  178          */
  179         sc->sc_tjmax = 100;
  180 
  181         if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) {
  182                 /*
  183                  * On some Core 2 CPUs, there's an undocumented MSR that
  184                  * can tell us if Tj(max) is 100 or 85.
  185                  *
  186                  * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted
  187                  * from the Linux coretemp driver.
  188                  */
  189                 msr = rdmsr(MSR_IA32_EXT_CONFIG);
  190                 if (msr & (1 << 30))
  191                         sc->sc_tjmax = 85;
  192         } else if (cpu_model == 0x17) {
  193                 switch (cpu_stepping) {
  194                 case 0x6:       /* Mobile Core 2 Duo */
  195                         sc->sc_tjmax = 104;
  196                         break;
  197                 default:        /* Unknown stepping */
  198                         break;
  199                 }
  200         } else {
  201                 /*
  202                  * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
  203                  *
  204                  * This method is described in Intel white paper "CPU
  205                  * Monitoring With DTS/PECI". (#322683)
  206                  */
  207                 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
  208                 if (ret == 0) {
  209                         tjtarget = (msr >> 16) & 0xff;
  210                         
  211                         /*
  212                          * On earlier generation of processors, the value
  213                          * obtained from IA32_TEMPERATURE_TARGET register is
  214                          * an offset that needs to be summed with a model
  215                          * specific base.  It is however not clear what
  216                          * these numbers are, with the publicly available
  217                          * documents from Intel.
  218                          *
  219                          * For now, we consider [70, 100]C range, as
  220                          * described in #322683, as "reasonable" and accept
  221                          * these values whenever the MSR is available for
  222                          * read, regardless the CPU model.
  223                          */
  224                         if (tjtarget >= 70 && tjtarget <= 100)
  225                                 sc->sc_tjmax = tjtarget;
  226                         else
  227                                 device_printf(dev, "Tj(target) value %d "
  228                                     "does not seem right.\n", tjtarget);
  229                 } else
  230                         device_printf(dev, "Can not get Tj(target) "
  231                             "from your CPU, using 100C.\n");
  232         }
  233 
  234         if (bootverbose)
  235                 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax);
  236 
  237         /*
  238          * Add the "temperature" MIB to dev.cpu.N.
  239          */
  240         sc->sc_oid = SYSCTL_ADD_PROC(device_get_sysctl_ctx(pdev),
  241             SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)),
  242             OID_AUTO, "temperature",
  243             CTLTYPE_INT | CTLFLAG_RD,
  244             dev, 0, coretemp_get_temp_sysctl, "IK",
  245             "Current temperature");
  246 
  247         return (0);
  248 }
  249 
  250 static int
  251 coretemp_detach(device_t dev)
  252 {
  253         struct coretemp_softc *sc = device_get_softc(dev);
  254 
  255         sysctl_remove_oid(sc->sc_oid, 1, 0);
  256 
  257         return (0);
  258 }
  259 
  260 
  261 static int
  262 coretemp_get_temp(device_t dev)
  263 {
  264         uint64_t msr;
  265         int temp;
  266         int cpu = device_get_unit(dev);
  267         struct coretemp_softc *sc = device_get_softc(dev);
  268         char stemp[16];
  269 
  270         thread_lock(curthread);
  271         sched_bind(curthread, cpu);
  272         thread_unlock(curthread);
  273 
  274         /*
  275          * The digital temperature reading is located at bit 16
  276          * of MSR_THERM_STATUS.
  277          *
  278          * There is a bit on that MSR that indicates whether the
  279          * temperature is valid or not.
  280          *
  281          * The temperature is computed by subtracting the temperature
  282          * reading by Tj(max).
  283          */
  284         msr = rdmsr(MSR_THERM_STATUS);
  285 
  286         thread_lock(curthread);
  287         sched_unbind(curthread);
  288         thread_unlock(curthread);
  289 
  290         /*
  291          * Check for Thermal Status and Thermal Status Log.
  292          */
  293         if ((msr & 0x3) == 0x3)
  294                 device_printf(dev, "PROCHOT asserted\n");
  295 
  296         /*
  297          * Bit 31 contains "Reading valid"
  298          */
  299         if (((msr >> 31) & 0x1) == 1) {
  300                 /*
  301                  * Starting on bit 16 and ending on bit 22.
  302                  */
  303                 temp = sc->sc_tjmax - ((msr >> 16) & 0x7f);
  304         } else
  305                 temp = -1;
  306 
  307         /*
  308          * Check for Critical Temperature Status and Critical
  309          * Temperature Log.
  310          * It doesn't really matter if the current temperature is
  311          * invalid because the "Critical Temperature Log" bit will
  312          * tell us if the Critical Temperature has been reached in
  313          * past. It's not directly related to the current temperature.
  314          *
  315          * If we reach a critical level, allow devctl(4) to catch this
  316          * and shutdown the system.
  317          */
  318         if (((msr >> 4) & 0x3) == 0x3) {
  319                 device_printf(dev, "critical temperature detected, "
  320                     "suggest system shutdown\n");
  321                 snprintf(stemp, sizeof(stemp), "%d", temp);
  322                 devctl_notify("coretemp", "Thermal", stemp, "notify=0xcc");
  323         }
  324 
  325         return (temp);
  326 }
  327 
  328 static int
  329 coretemp_get_temp_sysctl(SYSCTL_HANDLER_ARGS)
  330 {
  331         device_t dev = (device_t) arg1;
  332         int temp;
  333 
  334         temp = coretemp_get_temp(dev) * 10 + TZ_ZEROC;
  335 
  336         return (sysctl_handle_int(oidp, &temp, 0, req));
  337 }

Cache object: 4e876358389de8e6fab2a0c85c41fa7d


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.