The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/dev/cpufreq/ichss.c

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (c) 2004-2005 Nate Lawson (SDG)
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/8.0/sys/dev/cpufreq/ichss.c 181691 2008-08-13 16:09:40Z jhb $");
   29 
   30 #include <sys/param.h>
   31 #include <sys/bus.h>
   32 #include <sys/cpu.h>
   33 #include <sys/kernel.h>
   34 #include <sys/malloc.h>
   35 #include <sys/module.h>
   36 #include <sys/pcpu.h>
   37 #include <sys/sysctl.h>
   38 #include <sys/systm.h>
   39 
   40 #include <dev/pci/pcivar.h>
   41 #include <machine/bus.h>
   42 #include <machine/resource.h>
   43 #include <sys/rman.h>
   44 
   45 #include "cpufreq_if.h"
   46 
   47 /*
   48  * The SpeedStep ICH feature is a chipset-initiated voltage and frequency
   49  * transition available on the ICH2M, 3M, and 4M.  It is different from
   50  * the newer Pentium-M SpeedStep feature.  It offers only two levels of
   51  * frequency/voltage.  Often, the BIOS will select one of the levels via
   52  * SMM code during the power-on process (i.e., choose a lower level if the
   53  * system is off AC power.)
   54  */
   55 
   56 struct ichss_softc {
   57         device_t         dev;
   58         int              bm_rid;        /* Bus-mastering control (PM2REG). */
   59         struct resource *bm_reg;
   60         int              ctrl_rid;      /* Control/status register. */
   61         struct resource *ctrl_reg;
   62         struct cf_setting sets[2];      /* Only two settings. */
   63 };
   64 
   65 /* Supported PCI IDs. */
   66 #define PCI_VENDOR_INTEL        0x8086
   67 #define PCI_DEV_82801BA         0x244c /* ICH2M */
   68 #define PCI_DEV_82801CA         0x248c /* ICH3M */
   69 #define PCI_DEV_82801DB         0x24cc /* ICH4M */
   70 #define PCI_DEV_82815BA         0x1130 /* Unsupported/buggy part */
   71 
   72 /* PCI config registers for finding PMBASE and enabling SpeedStep. */
   73 #define ICHSS_PMBASE_OFFSET     0x40
   74 #define ICHSS_PMCFG_OFFSET      0xa0
   75 
   76 /* Values and masks. */
   77 #define ICHSS_ENABLE            (1<<3)  /* Enable SpeedStep control. */
   78 #define ICHSS_IO_REG            0x1     /* Access register via I/O space. */
   79 #define ICHSS_PMBASE_MASK       0xff80  /* PMBASE address bits. */
   80 #define ICHSS_CTRL_BIT          0x1     /* 0 is high speed, 1 is low. */
   81 #define ICHSS_BM_DISABLE        0x1
   82 
   83 /* Offsets from PMBASE for various registers. */
   84 #define ICHSS_BM_OFFSET         0x20
   85 #define ICHSS_CTRL_OFFSET       0x50
   86 
   87 #define ICH_GET_REG(reg)                                \
   88         (bus_space_read_1(rman_get_bustag((reg)),       \
   89             rman_get_bushandle((reg)), 0))
   90 #define ICH_SET_REG(reg, val)                           \
   91         (bus_space_write_1(rman_get_bustag((reg)),      \
   92             rman_get_bushandle((reg)), 0, (val)))
   93 
   94 static void     ichss_identify(driver_t *driver, device_t parent);
   95 static int      ichss_probe(device_t dev);
   96 static int      ichss_attach(device_t dev);
   97 static int      ichss_detach(device_t dev);
   98 static int      ichss_settings(device_t dev, struct cf_setting *sets,
   99                     int *count);
  100 static int      ichss_set(device_t dev, const struct cf_setting *set);
  101 static int      ichss_get(device_t dev, struct cf_setting *set);
  102 static int      ichss_type(device_t dev, int *type);
  103 
  104 static device_method_t ichss_methods[] = {
  105         /* Device interface */
  106         DEVMETHOD(device_identify,      ichss_identify),
  107         DEVMETHOD(device_probe,         ichss_probe),
  108         DEVMETHOD(device_attach,        ichss_attach),
  109         DEVMETHOD(device_detach,        ichss_detach),
  110 
  111         /* cpufreq interface */
  112         DEVMETHOD(cpufreq_drv_set,      ichss_set),
  113         DEVMETHOD(cpufreq_drv_get,      ichss_get),
  114         DEVMETHOD(cpufreq_drv_type,     ichss_type),
  115         DEVMETHOD(cpufreq_drv_settings, ichss_settings),
  116         {0, 0}
  117 };
  118 static driver_t ichss_driver = {
  119         "ichss", ichss_methods, sizeof(struct ichss_softc)
  120 };
  121 static devclass_t ichss_devclass;
  122 DRIVER_MODULE(ichss, cpu, ichss_driver, ichss_devclass, 0, 0);
  123 
  124 static device_t ich_device;
  125 
  126 #if 0
  127 #define DPRINT(x...)    printf(x)
  128 #else
  129 #define DPRINT(x...)
  130 #endif
  131 
  132 static void
  133 ichss_identify(driver_t *driver, device_t parent)
  134 {
  135         device_t child;
  136         uint32_t pmbase;
  137 
  138         if (resource_disabled("ichss", 0))
  139                 return;
  140 
  141         /*
  142          * It appears that ICH SpeedStep only requires a single CPU to
  143          * set the value (since the chipset is shared by all CPUs.)
  144          * Thus, we only add a child to cpu 0.
  145          */
  146         if (device_get_unit(parent) != 0)
  147                 return;
  148 
  149         /* Avoid duplicates. */
  150         if (device_find_child(parent, "ichss", -1))
  151                 return;
  152 
  153         /*
  154          * ICH2/3/4-M I/O Controller Hub is at bus 0, slot 1F, function 0.
  155          * E.g. see Section 6.1 "PCI Devices and Functions" and table 6.1 of
  156          * Intel(r) 82801BA I/O Controller Hub 2 (ICH2) and Intel(r) 82801BAM
  157          * I/O Controller Hub 2 Mobile (ICH2-M).
  158          *
  159          * TODO: add a quirk to disable if we see the 82815_MC along
  160          * with the 82801BA and revision < 5.
  161          */
  162         ich_device = pci_find_bsf(0, 0x1f, 0);
  163         if (ich_device == NULL ||
  164             pci_get_vendor(ich_device) != PCI_VENDOR_INTEL ||
  165             (pci_get_device(ich_device) != PCI_DEV_82801BA &&
  166             pci_get_device(ich_device) != PCI_DEV_82801CA &&
  167             pci_get_device(ich_device) != PCI_DEV_82801DB))
  168                 return;
  169 
  170         /* Find the PMBASE register from our PCI config header. */
  171         pmbase = pci_read_config(ich_device, ICHSS_PMBASE_OFFSET,
  172             sizeof(pmbase));
  173         if ((pmbase & ICHSS_IO_REG) == 0) {
  174                 printf("ichss: invalid PMBASE memory type\n");
  175                 return;
  176         }
  177         pmbase &= ICHSS_PMBASE_MASK;
  178         if (pmbase == 0) {
  179                 printf("ichss: invalid zero PMBASE address\n");
  180                 return;
  181         }
  182         DPRINT("ichss: PMBASE is %#x\n", pmbase);
  183 
  184         child = BUS_ADD_CHILD(parent, 20, "ichss", 0);
  185         if (child == NULL) {
  186                 device_printf(parent, "add SpeedStep child failed\n");
  187                 return;
  188         }
  189 
  190         /* Add the bus master arbitration and control registers. */
  191         bus_set_resource(child, SYS_RES_IOPORT, 0, pmbase + ICHSS_BM_OFFSET,
  192             1);
  193         bus_set_resource(child, SYS_RES_IOPORT, 1, pmbase + ICHSS_CTRL_OFFSET,
  194             1);
  195 }
  196 
  197 static int
  198 ichss_probe(device_t dev)
  199 {
  200         device_t est_dev, perf_dev;
  201         int error, type;
  202 
  203         /*
  204          * If the ACPI perf driver has attached and is not just offering
  205          * info, let it manage things.  Also, if Enhanced SpeedStep is
  206          * available, don't attach.
  207          */
  208         perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
  209         if (perf_dev && device_is_attached(perf_dev)) {
  210                 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
  211                 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
  212                         return (ENXIO);
  213         }
  214         est_dev = device_find_child(device_get_parent(dev), "est", -1);
  215         if (est_dev && device_is_attached(est_dev))
  216                 return (ENXIO);
  217 
  218         device_set_desc(dev, "SpeedStep ICH");
  219         return (-1000);
  220 }
  221 
  222 static int
  223 ichss_attach(device_t dev)
  224 {
  225         struct ichss_softc *sc;
  226         uint16_t ss_en;
  227 
  228         sc = device_get_softc(dev);
  229         sc->dev = dev;
  230 
  231         sc->bm_rid = 0;
  232         sc->bm_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->bm_rid,
  233             RF_ACTIVE);
  234         if (sc->bm_reg == NULL) {
  235                 device_printf(dev, "failed to alloc BM arb register\n");
  236                 return (ENXIO);
  237         }
  238         sc->ctrl_rid = 1;
  239         sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
  240             &sc->ctrl_rid, RF_ACTIVE);
  241         if (sc->ctrl_reg == NULL) {
  242                 device_printf(dev, "failed to alloc control register\n");
  243                 bus_release_resource(dev, SYS_RES_IOPORT, sc->bm_rid,
  244                     sc->bm_reg);
  245                 return (ENXIO);
  246         }
  247 
  248         /* Activate SpeedStep control if not already enabled. */
  249         ss_en = pci_read_config(ich_device, ICHSS_PMCFG_OFFSET, sizeof(ss_en));
  250         if ((ss_en & ICHSS_ENABLE) == 0) {
  251                 device_printf(dev, "enabling SpeedStep support\n");
  252                 pci_write_config(ich_device, ICHSS_PMCFG_OFFSET,
  253                     ss_en | ICHSS_ENABLE, sizeof(ss_en));
  254         }
  255 
  256         /* Setup some defaults for our exported settings. */
  257         sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN;
  258         sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN;
  259         sc->sets[0].power = CPUFREQ_VAL_UNKNOWN;
  260         sc->sets[0].lat = 1000;
  261         sc->sets[0].dev = dev;
  262         sc->sets[1] = sc->sets[0];
  263         cpufreq_register(dev);
  264 
  265         return (0);
  266 }
  267 
  268 static int
  269 ichss_detach(device_t dev)
  270 {
  271         /* TODO: teardown BM and CTRL registers. */
  272         return (ENXIO);
  273 }
  274 
  275 static int
  276 ichss_settings(device_t dev, struct cf_setting *sets, int *count)
  277 {
  278         struct ichss_softc *sc;
  279         struct cf_setting set;
  280         int first, i;
  281 
  282         if (sets == NULL || count == NULL)
  283                 return (EINVAL);
  284         if (*count < 2) {
  285                 *count = 2;
  286                 return (E2BIG);
  287         }
  288         sc = device_get_softc(dev);
  289 
  290         /*
  291          * Estimate frequencies for both levels, temporarily switching to
  292          * the other one if we haven't calibrated it yet.
  293          */
  294         ichss_get(dev, &set);
  295         for (i = 0; i < 2; i++) {
  296                 if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) {
  297                         first = (i == 0) ? 1 : 0;
  298                         ichss_set(dev, &sc->sets[i]);
  299                         ichss_set(dev, &sc->sets[first]);
  300                 }
  301         }
  302 
  303         bcopy(sc->sets, sets, sizeof(sc->sets));
  304         *count = 2;
  305 
  306         return (0);
  307 }
  308 
  309 static int
  310 ichss_set(device_t dev, const struct cf_setting *set)
  311 {
  312         struct ichss_softc *sc;
  313         uint8_t bmval, new_val, old_val, req_val;
  314         uint64_t rate;
  315         register_t regs;
  316 
  317         /* Look up appropriate bit value based on frequency. */
  318         sc = device_get_softc(dev);
  319         if (CPUFREQ_CMP(set->freq, sc->sets[0].freq))
  320                 req_val = 0;
  321         else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq))
  322                 req_val = ICHSS_CTRL_BIT;
  323         else
  324                 return (EINVAL);
  325         DPRINT("ichss: requested setting %d\n", req_val);
  326 
  327         /* Disable interrupts and get the other register contents. */
  328         regs = intr_disable();
  329         old_val = ICH_GET_REG(sc->ctrl_reg) & ~ICHSS_CTRL_BIT;
  330 
  331         /*
  332          * Disable bus master arbitration, write the new value to the control
  333          * register, and then re-enable bus master arbitration.
  334          */
  335         bmval = ICH_GET_REG(sc->bm_reg) | ICHSS_BM_DISABLE;
  336         ICH_SET_REG(sc->bm_reg, bmval);
  337         ICH_SET_REG(sc->ctrl_reg, old_val | req_val);
  338         ICH_SET_REG(sc->bm_reg, bmval & ~ICHSS_BM_DISABLE);
  339 
  340         /* Get the new value and re-enable interrupts. */
  341         new_val = ICH_GET_REG(sc->ctrl_reg);
  342         intr_restore(regs);
  343 
  344         /* Check if the desired state was indeed selected. */
  345         if (req_val != (new_val & ICHSS_CTRL_BIT)) {
  346             device_printf(sc->dev, "transition to %d failed\n", req_val);
  347             return (ENXIO);
  348         }
  349 
  350         /* Re-initialize our cycle counter if we don't know this new state. */
  351         if (sc->sets[req_val].freq == CPUFREQ_VAL_UNKNOWN) {
  352                 cpu_est_clockrate(0, &rate);
  353                 sc->sets[req_val].freq = rate / 1000000;
  354                 DPRINT("ichss: set calibrated new rate of %d\n",
  355                     sc->sets[req_val].freq);
  356         }
  357 
  358         return (0);
  359 }
  360 
  361 static int
  362 ichss_get(device_t dev, struct cf_setting *set)
  363 {
  364         struct ichss_softc *sc;
  365         uint64_t rate;
  366         uint8_t state;
  367 
  368         sc = device_get_softc(dev);
  369         state = ICH_GET_REG(sc->ctrl_reg) & ICHSS_CTRL_BIT;
  370 
  371         /* If we haven't changed settings yet, estimate the current value. */
  372         if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) {
  373                 cpu_est_clockrate(0, &rate);
  374                 sc->sets[state].freq = rate / 1000000;
  375                 DPRINT("ichss: get calibrated new rate of %d\n",
  376                     sc->sets[state].freq);
  377         }
  378         *set = sc->sets[state];
  379 
  380         return (0);
  381 }
  382 
  383 static int
  384 ichss_type(device_t dev, int *type)
  385 {
  386 
  387         if (type == NULL)
  388                 return (EINVAL);
  389 
  390         *type = CPUFREQ_TYPE_ABSOLUTE;
  391         return (0);
  392 }

Cache object: 4c7fa212b417b11ac44d105bfeef9f2f


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.