FreeBSD/Linux Kernel Cross Reference
sys/dev/ct/ct.c
1 /* $NecBSD: ct.c,v 1.13.12.5 2001/06/26 07:31:53 honda Exp $ */
2
3 #include <sys/cdefs.h>
4 __FBSDID("$FreeBSD: releng/10.4/sys/dev/ct/ct.c 242871 2012-11-10 14:58:06Z nyan $");
5 /* $NetBSD$ */
6
7 #define CT_DEBUG
8 #define CT_IO_CONTROL_FLAGS (CT_USE_CCSEQ | CT_FAST_INTR)
9
10 /*-
11 * [NetBSD for NEC PC-98 series]
12 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
13 * NetBSD/pc98 porting staff. All rights reserved.
14 *
15 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
16 * Naofumi HONDA. All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
20 * are met:
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * 3. The name of the author may not be used to endorse or promote products
27 * derived from this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
33 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 */
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/bio.h>
46 #include <sys/buf.h>
47 #include <sys/queue.h>
48 #include <sys/malloc.h>
49 #include <sys/errno.h>
50
51 #include <machine/bus.h>
52
53 #include <cam/scsi/scsi_low.h>
54
55 #include <dev/ic/wd33c93reg.h>
56 #include <dev/ct/ctvar.h>
57 #include <dev/ct/ct_machdep.h>
58
59 #define CT_NTARGETS 8
60 #define CT_NLUNS 8
61 #define CT_RESET_DEFAULT 2000
62 #define CT_DELAY_MAX (2 * 1000 * 1000)
63 #define CT_DELAY_INTERVAL (1)
64
65 /***************************************************
66 * DEBUG
67 ***************************************************/
68 #ifdef CT_DEBUG
69 int ct_debug;
70 #endif /* CT_DEBUG */
71
72 /***************************************************
73 * IO control
74 ***************************************************/
75 #define CT_USE_CCSEQ 0x0100
76 #define CT_FAST_INTR 0x0200
77
78 u_int ct_io_control = CT_IO_CONTROL_FLAGS;
79
80 /***************************************************
81 * default data
82 ***************************************************/
83 u_int8_t cthw_cmdlevel[256] = {
84 /* 0 1 2 3 4 5 6 7 8 9 A B C E D F */
85 /**/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
86 /*1*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
87 /*2*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
88 /*3*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
89 /*4*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
90 /*5*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
91 /*6*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
92 /*7*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
93 /*8*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
94 /*9*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
95 /*A*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
96 /*B*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
97 /*C*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
98 /*D*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
99 /*E*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
100 /*F*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
101 };
102
103 #if 0
104 /* default synch data table */
105 /* A 10 6.6 5.0 4.0 3.3 2.8 2.5 2.0 M/s */
106 /* X 100 150 200 250 300 350 400 500 ns */
107 static struct ct_synch_data ct_synch_data_FSCSI[] = {
108 {25, 0xa0}, {37, 0xb0}, {50, 0x20}, {62, 0xd0}, {75, 0x30},
109 {87, 0xf0}, {100, 0x40}, {125, 0x50}, {0, 0}
110 };
111
112 static struct ct_synch_data ct_synch_data_SCSI[] = {
113 {50, 0x20}, {75, 0x30}, {100, 0x40}, {125, 0x50}, {0, 0}
114 };
115 #endif
116 /***************************************************
117 * DEVICE STRUCTURE
118 ***************************************************/
119 extern struct cfdriver ct_cd;
120
121 /*****************************************************************
122 * Interface functions
123 *****************************************************************/
124 static int ct_xfer(struct ct_softc *, u_int8_t *, int, int, u_int *);
125 static void ct_io_xfer(struct ct_softc *);
126 static int ct_reselected(struct ct_softc *, u_int8_t);
127 static void ct_phase_error(struct ct_softc *, u_int8_t);
128 static int ct_start_selection(struct ct_softc *, struct slccb *);
129 static int ct_msg(struct ct_softc *, struct targ_info *, u_int);
130 static int ct_world_start(struct ct_softc *, int);
131 static __inline void cthw_phase_bypass(struct ct_softc *, u_int8_t);
132 static int cthw_chip_reset(struct ct_bus_access_handle *, int *, int, int);
133 static void cthw_bus_reset(struct ct_softc *);
134 static int ct_ccb_nexus_establish(struct ct_softc *);
135 static int ct_lun_nexus_establish(struct ct_softc *);
136 static int ct_target_nexus_establish(struct ct_softc *, int, int);
137 static void cthw_attention(struct ct_softc *);
138 static int ct_targ_init(struct ct_softc *, struct targ_info *, int);
139 static int ct_unbusy(struct ct_softc *);
140 static void ct_attention(struct ct_softc *);
141 static struct ct_synch_data *ct_make_synch_table(struct ct_softc *);
142 static int ct_catch_intr(struct ct_softc *);
143
144 struct scsi_low_funcs ct_funcs = {
145 SC_LOW_INIT_T ct_world_start,
146 SC_LOW_BUSRST_T cthw_bus_reset,
147 SC_LOW_TARG_INIT_T ct_targ_init,
148 SC_LOW_LUN_INIT_T NULL,
149
150 SC_LOW_SELECT_T ct_start_selection,
151 SC_LOW_NEXUS_T ct_lun_nexus_establish,
152 SC_LOW_NEXUS_T ct_ccb_nexus_establish,
153
154 SC_LOW_ATTEN_T cthw_attention,
155 SC_LOW_MSG_T ct_msg,
156
157 SC_LOW_TIMEOUT_T NULL,
158 SC_LOW_POLL_T ctintr,
159
160 NULL, /* SC_LOW_POWER_T cthw_power, */
161 };
162
163 /**************************************************
164 * HW functions
165 **************************************************/
166 static __inline void
167 cthw_phase_bypass(struct ct_softc *ct, u_int8_t ph)
168 {
169 struct ct_bus_access_handle *chp = &ct->sc_ch;
170
171 ct_cr_write_1(chp, wd3s_cph, ph);
172 ct_cr_write_1(chp, wd3s_cmd, WD3S_SELECT_ATN_TFR);
173 }
174
175 static void
176 cthw_bus_reset(struct ct_softc *ct)
177 {
178
179 /*
180 * wd33c93 does not have bus reset function.
181 */
182 if (ct->ct_bus_reset != NULL)
183 ((*ct->ct_bus_reset) (ct));
184 }
185
186 static int
187 cthw_chip_reset(struct ct_bus_access_handle *chp, int *chiprevp, int chipclk,
188 int hostid)
189 {
190 #define CT_SELTIMEOUT_20MHz_REGV (0x80)
191 u_int8_t aux, regv;
192 u_int seltout;
193 int wc;
194
195 /* issue abort cmd */
196 ct_cr_write_1(chp, wd3s_cmd, WD3S_ABORT);
197 DELAY(1000); /* 1ms wait */
198 (void) ct_stat_read_1(chp);
199 (void) ct_cr_read_1(chp, wd3s_stat);
200
201 /* setup chip registers */
202 regv = 0;
203 seltout = CT_SELTIMEOUT_20MHz_REGV;
204 switch (chipclk)
205 {
206 case 8:
207 case 10:
208 seltout = (seltout * chipclk) / 20;
209 regv = IDR_FS_8_10;
210 break;
211
212 case 12:
213 case 15:
214 seltout = (seltout * chipclk) / 20;
215 regv = IDR_FS_12_15;
216 break;
217
218 case 16:
219 case 20:
220 seltout = (seltout * chipclk) / 20;
221 regv = IDR_FS_16_20;
222 break;
223
224 default:
225 panic("ct: illegal chip clk rate");
226 break;
227 }
228
229 regv |= IDR_EHP | hostid | IDR_RAF | IDR_EAF;
230 ct_cr_write_1(chp, wd3s_oid, regv);
231
232 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
233 for (wc = CT_RESET_DEFAULT; wc > 0; wc --)
234 {
235 aux = ct_stat_read_1(chp);
236 if (aux != 0xff && (aux & STR_INT))
237 {
238 regv = ct_cr_read_1(chp, wd3s_stat);
239 if (regv == BSR_RESET || regv == BSR_AFM_RESET)
240 break;
241
242 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
243 }
244 DELAY(1);
245 }
246 if (wc == 0)
247 return ENXIO;
248
249 ct_cr_write_1(chp, wd3s_tout, seltout);
250 ct_cr_write_1(chp, wd3s_sid, SIDR_RESEL);
251 ct_cr_write_1(chp, wd3s_ctrl, CR_DEFAULT);
252 ct_cr_write_1(chp, wd3s_synch, 0);
253 if (chiprevp != NULL)
254 {
255 *chiprevp = CT_WD33C93;
256 if (regv == BSR_RESET)
257 goto out;
258
259 *chiprevp = CT_WD33C93_A;
260 ct_cr_write_1(chp, wd3s_qtag, 0xaa);
261 if (ct_cr_read_1(chp, wd3s_qtag) != 0xaa)
262 {
263 ct_cr_write_1(chp, wd3s_qtag, 0x0);
264 goto out;
265 }
266 ct_cr_write_1(chp, wd3s_qtag, 0x55);
267 if (ct_cr_read_1(chp, wd3s_qtag) != 0x55)
268 {
269 ct_cr_write_1(chp, wd3s_qtag, 0x0);
270 goto out;
271 }
272 ct_cr_write_1(chp, wd3s_qtag, 0x0);
273 *chiprevp = CT_WD33C93_B;
274 }
275
276 out:
277 (void) ct_stat_read_1(chp);
278 (void) ct_cr_read_1(chp, wd3s_stat);
279 return 0;
280 }
281
282 static struct ct_synch_data *
283 ct_make_synch_table(struct ct_softc *ct)
284 {
285 struct ct_synch_data *sdtp, *sdp;
286 u_int base, i, period;
287
288 sdtp = sdp = &ct->sc_default_sdt[0];
289
290 if ((ct->sc_chipclk % 5) == 0)
291 base = 1000 / (5 * 2); /* 5 MHz type */
292 else
293 base = 1000 / (4 * 2); /* 4 MHz type */
294
295 if (ct->sc_chiprev >= CT_WD33C93_B)
296 {
297 /* fast scsi */
298 for (i = 2; i < 8; i ++, sdp ++)
299 {
300 period = (base * i) / 2;
301 if (period >= 200) /* 5 MHz */
302 break;
303 sdp->cs_period = period / 4;
304 sdp->cs_syncr = (i * 0x10) | 0x80;
305 }
306 }
307
308 for (i = 2; i < 8; i ++, sdp ++)
309 {
310 period = (base * i);
311 if (period > 500) /* 2 MHz */
312 break;
313 sdp->cs_period = period / 4;
314 sdp->cs_syncr = (i * 0x10);
315 }
316
317 sdp->cs_period = 0;
318 sdp->cs_syncr = 0;
319 return sdtp;
320 }
321
322 /**************************************************
323 * Attach & Probe
324 **************************************************/
325 int
326 ctprobesubr(struct ct_bus_access_handle *chp, u_int dvcfg, int hsid,
327 u_int chipclk, int *chiprevp)
328 {
329
330 #if 0
331 if ((ct_stat_read_1(chp) & STR_BSY) != 0)
332 return 0;
333 #endif
334 if (cthw_chip_reset(chp, chiprevp, chipclk, hsid) != 0)
335 return 0;
336 return 1;
337 }
338
339 void
340 ctattachsubr(struct ct_softc *ct)
341 {
342 struct scsi_low_softc *slp = &ct->sc_sclow;
343
344 ct->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */
345 slp->sl_funcs = &ct_funcs;
346 slp->sl_flags |= HW_READ_PADDING;
347 (void) scsi_low_attach(slp, 0, CT_NTARGETS, CT_NLUNS,
348 sizeof(struct ct_targ_info), 0);
349 }
350
351 /**************************************************
352 * SCSI LOW interface functions
353 **************************************************/
354 static void
355 cthw_attention(struct ct_softc *ct)
356 {
357 struct ct_bus_access_handle *chp = &ct->sc_ch;
358
359 ct->sc_atten = 1;
360 if ((ct_stat_read_1(chp) & (STR_BSY | STR_CIP)) != 0)
361 return;
362
363 ct_cr_write_1(chp, wd3s_cmd, WD3S_ASSERT_ATN);
364 DELAY(10);
365 if ((ct_stat_read_1(chp) & STR_LCI) == 0)
366 ct->sc_atten = 0;
367 ct_unbusy(ct);
368 return;
369 }
370
371 static void
372 ct_attention(struct ct_softc *ct)
373 {
374 struct scsi_low_softc *slp = &ct->sc_sclow;
375
376 if (slp->sl_atten == 0)
377 {
378 ct_unbusy(ct);
379 scsi_low_attention(slp);
380 }
381 else if (ct->sc_atten != 0)
382 {
383 ct_unbusy(ct);
384 cthw_attention(ct);
385 }
386 }
387
388 static int
389 ct_targ_init(struct ct_softc *ct, struct targ_info *ti, int action)
390 {
391 struct ct_targ_info *cti = (void *) ti;
392
393 if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE)
394 {
395 if (ct->sc_sdp == NULL)
396 {
397 ct->sc_sdp = ct_make_synch_table(ct);
398 }
399
400 switch (ct->sc_chiprev)
401 {
402 default:
403 ti->ti_maxsynch.offset = 5;
404 break;
405
406 case CT_WD33C93_A:
407 case CT_AM33C93_A:
408 ti->ti_maxsynch.offset = 12;
409 break;
410
411 case CT_WD33C93_B:
412 case CT_WD33C93_C:
413 ti->ti_maxsynch.offset = 12;
414 break;
415 }
416
417 ti->ti_maxsynch.period = ct->sc_sdp[0].cs_period;
418 ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
419 cti->cti_syncreg = 0;
420 }
421
422 return 0;
423 }
424
425 static int
426 ct_world_start(struct ct_softc *ct, int fdone)
427 {
428 struct scsi_low_softc *slp = &ct->sc_sclow;
429 struct ct_bus_access_handle *chp = &ct->sc_ch;
430
431 if (ct->sc_sdp == NULL)
432 {
433 ct->sc_sdp = ct_make_synch_table(ct);
434 }
435
436 if (slp->sl_cfgflags & CFG_NOPARITY)
437 ct->sc_creg = CR_DEFAULT;
438 else
439 ct->sc_creg = CR_DEFAULT_HP;
440
441 if (ct->sc_dma & CT_DMA_DMASTART)
442 (*ct->ct_dma_xfer_stop) (ct);
443 if (ct->sc_dma & CT_DMA_PIOSTART)
444 (*ct->ct_pio_xfer_stop) (ct);
445 ct->sc_dma = 0;
446 ct->sc_atten = 0;
447
448 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
449 scsi_low_bus_reset(slp);
450 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
451
452 return 0;
453 }
454
455 static int
456 ct_start_selection(struct ct_softc *ct, struct slccb *cb)
457 {
458 struct scsi_low_softc *slp = &ct->sc_sclow;
459 struct ct_bus_access_handle *chp = &ct->sc_ch;
460
461 struct targ_info *ti = slp->sl_Tnexus;
462 struct lun_info *li = slp->sl_Lnexus;
463 int s, satok;
464 u_int8_t cmd;
465
466 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
467 ct->sc_atten = 0;
468 satok = 0;
469
470 if (scsi_low_is_disconnect_ok(cb) != 0)
471 {
472 if (ct->sc_chiprev >= CT_WD33C93_A)
473 satok = 1;
474 else if (cthw_cmdlevel[slp->sl_scp.scp_cmd[0]] != 0)
475 satok = 1;
476 }
477
478 if (satok != 0 &&
479 scsi_low_is_msgout_continue(ti, SCSI_LOW_MSG_IDENTIFY) == 0)
480 {
481 cmd = WD3S_SELECT_ATN_TFR;
482 ct->sc_satgo = CT_SAT_GOING;
483 }
484 else
485 {
486 cmd = WD3S_SELECT_ATN;
487 ct->sc_satgo = 0;
488 }
489
490 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) != 0)
491 return SCSI_LOW_START_FAIL;
492
493 if ((ct->sc_satgo & CT_SAT_GOING) != 0)
494 {
495 (void) scsi_low_msgout(slp, ti, SCSI_LOW_MSGOUT_INIT);
496 scsi_low_cmd(slp, ti);
497 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
498 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
499 }
500 else
501 {
502 /* anyway attention assert */
503 SCSI_LOW_ASSERT_ATN(slp);
504 }
505
506 ct_target_nexus_establish(ct, li->li_lun, slp->sl_scp.scp_direction);
507
508 s = splhigh();
509 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) == 0)
510 {
511 /* XXX:
512 * Reload a lun again here.
513 */
514 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
515 ct_cr_write_1(chp, wd3s_cmd, cmd);
516 if ((ct_stat_read_1(chp) & STR_LCI) == 0)
517 {
518 splx(s);
519 SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART);
520 return SCSI_LOW_START_OK;
521 }
522 }
523 splx(s);
524 return SCSI_LOW_START_FAIL;
525 }
526
527 static int
528 ct_msg(struct ct_softc *ct, struct targ_info *ti, u_int msg)
529 {
530 struct ct_bus_access_handle *chp = &ct->sc_ch;
531 struct ct_targ_info *cti = (void *) ti;
532 struct ct_synch_data *csp = ct->sc_sdp;
533 u_int offset, period;
534 int error;
535
536 if ((msg & SCSI_LOW_MSG_WIDE) != 0)
537 {
538 if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8)
539 {
540 ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
541 return EINVAL;
542 }
543 return 0;
544 }
545
546 if ((msg & SCSI_LOW_MSG_SYNCH) == 0)
547 return 0;
548
549 offset = ti->ti_maxsynch.offset;
550 period = ti->ti_maxsynch.period;
551 for ( ; csp->cs_period != 0; csp ++)
552 {
553 if (period == csp->cs_period)
554 break;
555 }
556
557 if (ti->ti_maxsynch.period != 0 && csp->cs_period == 0)
558 {
559 ti->ti_maxsynch.period = 0;
560 ti->ti_maxsynch.offset = 0;
561 cti->cti_syncreg = 0;
562 error = EINVAL;
563 }
564 else
565 {
566 cti->cti_syncreg = ((offset & 0x0f) | csp->cs_syncr);
567 error = 0;
568 }
569
570 if (ct->ct_synch_setup != 0)
571 (*ct->ct_synch_setup) (ct, ti);
572 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
573 return error;
574 }
575
576 /*************************************************
577 * <DATA PHASE>
578 *************************************************/
579 static int
580 ct_xfer(struct ct_softc *ct, u_int8_t *data, int len, int direction,
581 u_int *statp)
582 {
583 struct ct_bus_access_handle *chp = &ct->sc_ch;
584 int wc;
585 register u_int8_t aux;
586
587 *statp = 0;
588 if (len == 1)
589 {
590 ct_cr_write_1(chp, wd3s_cmd, WD3S_SBT | WD3S_TFR_INFO);
591 }
592 else
593 {
594 cthw_set_count(chp, len);
595 ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
596 }
597
598 aux = ct_stat_read_1(chp);
599 if ((aux & STR_LCI) != 0)
600 {
601 cthw_set_count(chp, 0);
602 return len;
603 }
604
605 for (wc = 0; wc < ct->sc_tmaxcnt; wc ++)
606 {
607 /* check data ready */
608 if ((aux & (STR_BSY | STR_DBR)) == (STR_BSY | STR_DBR))
609 {
610 if (direction == SCSI_LOW_READ)
611 {
612 *data = ct_cr_read_1(chp, wd3s_data);
613 if ((aux & STR_PE) != 0)
614 *statp |= SCSI_LOW_DATA_PE;
615 }
616 else
617 {
618 ct_cr_write_1(chp, wd3s_data, *data);
619 }
620 len --;
621 if (len <= 0)
622 break;
623 data ++;
624 }
625 else
626 {
627 DELAY(1);
628 }
629
630 /* check phase miss */
631 aux = ct_stat_read_1(chp);
632 if ((aux & STR_INT) != 0)
633 break;
634 }
635 return len;
636 }
637
638 #define CT_PADDING_BUF_SIZE 32
639
640 static void
641 ct_io_xfer(struct ct_softc *ct)
642 {
643 struct scsi_low_softc *slp = &ct->sc_sclow;
644 struct ct_bus_access_handle *chp = &ct->sc_ch;
645 struct sc_p *sp = &slp->sl_scp;
646 u_int stat;
647 int len;
648 u_int8_t pbuf[CT_PADDING_BUF_SIZE];
649
650 /* polling mode */
651 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg);
652
653 if (sp->scp_datalen <= 0)
654 {
655 slp->sl_error |= PDMAERR;
656
657 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
658 bzero(pbuf, CT_PADDING_BUF_SIZE);
659 ct_xfer(ct, pbuf, CT_PADDING_BUF_SIZE,
660 sp->scp_direction, &stat);
661 }
662 else
663 {
664 len = ct_xfer(ct, sp->scp_data, sp->scp_datalen,
665 sp->scp_direction, &stat);
666 sp->scp_data += (sp->scp_datalen - len);
667 sp->scp_datalen = len;
668 }
669 }
670
671 /**************************************************
672 * <PHASE ERROR>
673 **************************************************/
674 struct ct_err {
675 u_char *pe_msg;
676 u_int pe_err;
677 u_int pe_errmsg;
678 int pe_done;
679 };
680
681 struct ct_err ct_cmderr[] = {
682 /**/ { "illegal cmd", FATALIO, SCSI_LOW_MSG_ABORT, 1},
683 /*1*/ { "unexpected bus free", FATALIO, 0, 1},
684 /*2*/ { NULL, SELTIMEOUTIO, 0, 1},
685 /*3*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
686 /*4*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
687 /*5*/ { "unknown" , FATALIO, SCSI_LOW_MSG_ABORT, 1},
688 /*6*/ { "miss reselection (target mode)", FATALIO, SCSI_LOW_MSG_ABORT, 0},
689 /*7*/ { "wrong status byte", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
690 };
691
692 static void
693 ct_phase_error(struct ct_softc *ct, u_int8_t scsi_status)
694 {
695 struct scsi_low_softc *slp = &ct->sc_sclow;
696 struct targ_info *ti = slp->sl_Tnexus;
697 struct ct_err *pep;
698 u_int msg = 0;
699
700 if ((scsi_status & BSR_CM) == BSR_CMDERR &&
701 (scsi_status & BSR_PHVALID) == 0)
702 {
703 pep = &ct_cmderr[scsi_status & BSR_PM];
704 slp->sl_error |= pep->pe_err;
705 if ((pep->pe_err & PARITYERR) != 0)
706 {
707 if (ti->ti_phase == PH_MSGIN)
708 msg = SCSI_LOW_MSG_PARITY;
709 else
710 msg = SCSI_LOW_MSG_ERROR;
711 }
712 else
713 msg = pep->pe_errmsg;
714
715 if (msg != 0)
716 scsi_low_assert_msg(slp, slp->sl_Tnexus, msg, 1);
717
718 if (pep->pe_msg != NULL)
719 {
720 device_printf(slp->sl_dev, "phase error: %s",
721 pep->pe_msg);
722 scsi_low_print(slp, slp->sl_Tnexus);
723 }
724
725 if (pep->pe_done != 0)
726 scsi_low_disconnected(slp, ti);
727 }
728 else
729 {
730 slp->sl_error |= FATALIO;
731 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD, "phase error");
732 }
733 }
734
735 /**************************************************
736 * ### SCSI PHASE SEQUENCER ###
737 **************************************************/
738 static int
739 ct_reselected(struct ct_softc *ct, u_int8_t scsi_status)
740 {
741 struct scsi_low_softc *slp = &ct->sc_sclow;
742 struct ct_bus_access_handle *chp = &ct->sc_ch;
743 struct targ_info *ti;
744 u_int sid;
745 u_int8_t regv;
746
747 ct->sc_atten = 0;
748 ct->sc_satgo &= ~CT_SAT_GOING;
749 regv = ct_cr_read_1(chp, wd3s_sid);
750 if ((regv & SIDR_VALID) == 0)
751 return EJUSTRETURN;
752
753 sid = regv & SIDR_IDM;
754 if ((ti = scsi_low_reselected(slp, sid)) == NULL)
755 return EJUSTRETURN;
756
757 ct_target_nexus_establish(ct, 0, SCSI_LOW_READ);
758 if (scsi_status != BSR_AFM_RESEL)
759 return EJUSTRETURN;
760
761 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
762 regv = ct_cr_read_1(chp, wd3s_data);
763 if (scsi_low_msgin(slp, ti, (u_int) regv) == 0)
764 {
765 if (scsi_low_is_msgout_continue(ti, 0) != 0)
766 {
767 /* XXX: scsi_low_attetion */
768 scsi_low_attention(slp);
769 }
770 }
771
772 if (ct->sc_atten != 0)
773 {
774 ct_attention(ct);
775 }
776
777 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
778 return EJUSTRETURN;
779 }
780
781 static int
782 ct_target_nexus_establish(struct ct_softc *ct, int lun, int dir)
783 {
784 struct scsi_low_softc *slp = &ct->sc_sclow;
785 struct ct_bus_access_handle *chp = &ct->sc_ch;
786 struct targ_info *ti = slp->sl_Tnexus;
787 struct ct_targ_info *cti = (void *) ti;
788
789 if (dir == SCSI_LOW_WRITE)
790 ct_cr_write_1(chp, wd3s_did, ti->ti_id);
791 else
792 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
793 ct_cr_write_1(chp, wd3s_lun, lun);
794 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
795 ct_cr_write_1(chp, wd3s_cph, 0);
796 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
797 cthw_set_count(chp, 0);
798 return 0;
799 }
800
801 static int
802 ct_lun_nexus_establish(struct ct_softc *ct)
803 {
804 struct scsi_low_softc *slp = &ct->sc_sclow;
805 struct ct_bus_access_handle *chp = &ct->sc_ch;
806 struct lun_info *li = slp->sl_Lnexus;
807
808 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
809 return 0;
810 }
811
812 static int
813 ct_ccb_nexus_establish(struct ct_softc *ct)
814 {
815 struct scsi_low_softc *slp = &ct->sc_sclow;
816 struct ct_bus_access_handle *chp = &ct->sc_ch;
817 struct lun_info *li = slp->sl_Lnexus;
818 struct targ_info *ti = slp->sl_Tnexus;
819 struct ct_targ_info *cti = (void *) ti;
820 struct slccb *cb = slp->sl_Qnexus;
821
822 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
823
824 if ((ct->sc_satgo & CT_SAT_GOING) != 0)
825 {
826 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
827 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
828 }
829 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
830 ct_cr_write_1(chp, wd3s_did, ti->ti_id);
831 else
832 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
833 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
834 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
835 return 0;
836 }
837
838 static int
839 ct_unbusy(struct ct_softc *ct)
840 {
841 struct scsi_low_softc *slp = &ct->sc_sclow;
842 struct ct_bus_access_handle *chp = &ct->sc_ch;
843 int wc;
844 register u_int8_t regv;
845
846 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
847 {
848 regv = ct_stat_read_1(chp);
849 if ((regv & (STR_BSY | STR_CIP)) == 0)
850 return 0;
851 if (regv == (u_int8_t) -1)
852 return EIO;
853
854 DELAY(CT_DELAY_INTERVAL);
855 }
856
857 device_printf(slp->sl_dev, "unbusy timeout\n");
858 return EBUSY;
859 }
860
861 static int
862 ct_catch_intr(struct ct_softc *ct)
863 {
864 struct ct_bus_access_handle *chp = &ct->sc_ch;
865 int wc;
866 register u_int8_t regv;
867
868 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
869 {
870 regv = ct_stat_read_1(chp);
871 if ((regv & (STR_INT | STR_BSY | STR_CIP)) == STR_INT)
872 return 0;
873
874 DELAY(CT_DELAY_INTERVAL);
875 }
876 return EJUSTRETURN;
877 }
878
879 int
880 ctintr(void *arg)
881 {
882 struct ct_softc *ct = arg;
883 struct scsi_low_softc *slp = &ct->sc_sclow;
884 struct ct_bus_access_handle *chp = &ct->sc_ch;
885 struct targ_info *ti;
886 struct buf *bp;
887 u_int derror, flags;
888 int len, satgo, error;
889 u_int8_t scsi_status, regv;
890
891 again:
892 if (slp->sl_flags & HW_INACTIVE)
893 return 0;
894
895 /**************************************************
896 * Get status & bus phase
897 **************************************************/
898 if ((ct_stat_read_1(chp) & STR_INT) == 0)
899 return 0;
900
901 scsi_status = ct_cr_read_1(chp, wd3s_stat);
902 if (scsi_status == ((u_int8_t) -1))
903 return 1;
904
905 /**************************************************
906 * Check reselection, or nexus
907 **************************************************/
908 if (scsi_status == BSR_RESEL || scsi_status == BSR_AFM_RESEL)
909 {
910 if (ct_reselected(ct, scsi_status) == EJUSTRETURN)
911 return 1;
912 }
913
914 if ((ti = slp->sl_Tnexus) == NULL)
915 return 1;
916
917 /**************************************************
918 * Debug section
919 **************************************************/
920 #ifdef CT_DEBUG
921 if (ct_debug > 0)
922 {
923 scsi_low_print(slp, NULL);
924 device_printf(slp->sl_dev, "scsi_status 0x%x\n\n",
925 (u_int) scsi_status);
926 #ifdef KDB
927 if (ct_debug > 1)
928 kdb_enter(KDB_WHY_CAM, "ct");
929 #endif /* KDB */
930 }
931 #endif /* CT_DEBUG */
932
933 /**************************************************
934 * Internal scsi phase
935 **************************************************/
936 satgo = ct->sc_satgo;
937 ct->sc_satgo &= ~CT_SAT_GOING;
938
939 switch (ti->ti_phase)
940 {
941 case PH_SELSTART:
942 if ((satgo & CT_SAT_GOING) == 0)
943 {
944 if (scsi_status != BSR_SELECTED)
945 {
946 ct_phase_error(ct, scsi_status);
947 return 1;
948 }
949 scsi_low_arbit_win(slp);
950 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED);
951 return 1;
952 }
953 else
954 {
955 scsi_low_arbit_win(slp);
956 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); /* XXX */
957 }
958 break;
959
960 case PH_RESEL:
961 if ((scsi_status & BSR_PHVALID) == 0 ||
962 (scsi_status & BSR_PM) != BSR_MSGIN)
963 {
964 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD,
965 "phase miss after reselect");
966 return 1;
967 }
968 break;
969
970 default:
971 if (slp->sl_flags & HW_PDMASTART)
972 {
973 slp->sl_flags &= ~HW_PDMASTART;
974 if (ct->sc_dma & CT_DMA_DMASTART)
975 {
976 (*ct->ct_dma_xfer_stop) (ct);
977 ct->sc_dma &= ~CT_DMA_DMASTART;
978 }
979 else if (ct->sc_dma & CT_DMA_PIOSTART)
980 {
981 (*ct->ct_pio_xfer_stop) (ct);
982 ct->sc_dma &= ~CT_DMA_PIOSTART;
983 }
984 else
985 {
986 scsi_low_data_finish(slp);
987 }
988 }
989 break;
990 }
991
992 /**************************************************
993 * parse scsi phase
994 **************************************************/
995 if (scsi_status & BSR_PHVALID)
996 {
997 /**************************************************
998 * Normal SCSI phase.
999 **************************************************/
1000 if ((scsi_status & BSR_CM) == BSR_CMDABT)
1001 {
1002 ct_phase_error(ct, scsi_status);
1003 return 1;
1004 }
1005
1006 switch (scsi_status & BSR_PM)
1007 {
1008 case BSR_DATAOUT:
1009 SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1010 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0)
1011 {
1012 ct_attention(ct);
1013 }
1014 goto common_data_phase;
1015
1016 case BSR_DATAIN:
1017 SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1018 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0)
1019 {
1020 ct_attention(ct);
1021 }
1022
1023 common_data_phase:
1024 if (slp->sl_scp.scp_datalen > 0)
1025 {
1026 slp->sl_flags |= HW_PDMASTART;
1027 if ((ct->sc_xmode & CT_XMODE_PIO) != 0)
1028 {
1029 error = (*ct->ct_pio_xfer_start) (ct);
1030 if (error == 0)
1031 {
1032 ct->sc_dma |= CT_DMA_PIOSTART;
1033 return 1;
1034 }
1035 }
1036
1037 if ((ct->sc_xmode & CT_XMODE_DMA) != 0)
1038 {
1039 error = (*ct->ct_dma_xfer_start) (ct);
1040 if (error == 0)
1041 {
1042 ct->sc_dma |= CT_DMA_DMASTART;
1043 return 1;
1044 }
1045 }
1046 }
1047 else
1048 {
1049 if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
1050 {
1051 if (!(slp->sl_flags & HW_READ_PADDING))
1052 {
1053 device_printf(slp->sl_dev,
1054 "read padding required\n");
1055 return 1;
1056 }
1057 }
1058 else
1059 {
1060 if (!(slp->sl_flags & HW_WRITE_PADDING))
1061 {
1062 device_printf(slp->sl_dev,
1063 "write padding required\n");
1064 return 1;
1065 }
1066 }
1067 slp->sl_flags |= HW_PDMASTART;
1068 }
1069
1070 ct_io_xfer(ct);
1071 return 1;
1072
1073 case BSR_CMDOUT:
1074 SCSI_LOW_SETUP_PHASE(ti, PH_CMD);
1075 if (scsi_low_cmd(slp, ti) != 0)
1076 {
1077 ct_attention(ct);
1078 }
1079
1080 if (ct_xfer(ct, slp->sl_scp.scp_cmd,
1081 slp->sl_scp.scp_cmdlen,
1082 SCSI_LOW_WRITE, &derror) != 0)
1083 {
1084 device_printf(slp->sl_dev,
1085 "scsi cmd xfer short\n");
1086 }
1087 return 1;
1088
1089 case BSR_STATIN:
1090 SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
1091 if ((ct_io_control & CT_USE_CCSEQ) != 0)
1092 {
1093 if (scsi_low_is_msgout_continue(ti, 0) != 0 ||
1094 ct->sc_atten != 0)
1095 {
1096 ct_xfer(ct, ®v, 1, SCSI_LOW_READ,
1097 &derror);
1098 scsi_low_statusin(slp, ti,
1099 regv | derror);
1100 }
1101 else
1102 {
1103 ct->sc_satgo |= CT_SAT_GOING;
1104 cthw_set_count(chp, 0);
1105 cthw_phase_bypass(ct, 0x41);
1106 }
1107 }
1108 else
1109 {
1110 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror);
1111 scsi_low_statusin(slp, ti, regv | derror);
1112 }
1113 return 1;
1114
1115 case BSR_UNSPINFO0:
1116 case BSR_UNSPINFO1:
1117 device_printf(slp->sl_dev, "illegal bus phase (0x%x)\n",
1118 (u_int) scsi_status);
1119 scsi_low_print(slp, ti);
1120 return 1;
1121
1122 case BSR_MSGOUT:
1123 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT);
1124 flags = SCSI_LOW_MSGOUT_UNIFY;
1125 if (ti->ti_ophase != ti->ti_phase)
1126 flags |= SCSI_LOW_MSGOUT_INIT;
1127 len = scsi_low_msgout(slp, ti, flags);
1128
1129 if (len > 1 && slp->sl_atten == 0)
1130 {
1131 ct_attention(ct);
1132 }
1133
1134 if (ct_xfer(ct, ti->ti_msgoutstr, len,
1135 SCSI_LOW_WRITE, &derror) != 0)
1136 {
1137 device_printf(slp->sl_dev,
1138 "scsi msgout xfer short\n");
1139 }
1140 SCSI_LOW_DEASSERT_ATN(slp);
1141 ct->sc_atten = 0;
1142 return 1;
1143
1144 case BSR_MSGIN:/* msg in */
1145 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1146
1147 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror);
1148 if (scsi_low_msgin(slp, ti, regv | derror) == 0)
1149 {
1150 if (scsi_low_is_msgout_continue(ti, 0) != 0)
1151 {
1152 /* XXX: scsi_low_attetion */
1153 scsi_low_attention(slp);
1154 }
1155 }
1156
1157 if ((ct_io_control & CT_FAST_INTR) != 0)
1158 {
1159 if (ct_catch_intr(ct) == 0)
1160 goto again;
1161 }
1162 return 1;
1163 }
1164 }
1165 else
1166 {
1167 /**************************************************
1168 * Special SCSI phase
1169 **************************************************/
1170 switch (scsi_status)
1171 {
1172 case BSR_SATSDP: /* SAT with save data pointer */
1173 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1174 ct->sc_satgo |= CT_SAT_GOING;
1175 scsi_low_msgin(slp, ti, MSG_SAVESP);
1176 cthw_phase_bypass(ct, 0x41);
1177 return 1;
1178
1179 case BSR_SATFIN: /* SAT COMPLETE */
1180 /*
1181 * emulate statusin => msgin
1182 */
1183 SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
1184 scsi_low_statusin(slp, ti, ct_cr_read_1(chp, wd3s_lun));
1185
1186 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1187 scsi_low_msgin(slp, ti, MSG_COMP);
1188
1189 scsi_low_disconnected(slp, ti);
1190 return 1;
1191
1192 case BSR_ACKREQ: /* negate ACK */
1193 if (ct->sc_atten != 0)
1194 {
1195 ct_attention(ct);
1196 }
1197
1198 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
1199 if ((ct_io_control & CT_FAST_INTR) != 0)
1200 {
1201 /* XXX:
1202 * Should clear a pending interrupt and
1203 * sync with a next interrupt!
1204 */
1205 ct_catch_intr(ct);
1206 }
1207 return 1;
1208
1209 case BSR_DISC: /* disconnect */
1210 if (slp->sl_msgphase == MSGPH_NULL &&
1211 (satgo & CT_SAT_GOING) != 0)
1212 {
1213 /*
1214 * emulate disconnect msg
1215 */
1216 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1217 scsi_low_msgin(slp, ti, MSG_DISCON);
1218 }
1219 scsi_low_disconnected(slp, ti);
1220 return 1;
1221
1222 default:
1223 break;
1224 }
1225 }
1226
1227 ct_phase_error(ct, scsi_status);
1228 return 1;
1229 }
Cache object: f03414b3feafb7a4c076eea2676592ec
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