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1 /* $NecBSD: ct.c,v 1.13.12.5 2001/06/26 07:31:53 honda Exp $ */ 2 3 #include <sys/cdefs.h> 4 __FBSDID("$FreeBSD$"); 5 /* $NetBSD$ */ 6 7 #define CT_DEBUG 8 #define CT_IO_CONTROL_FLAGS (CT_USE_CCSEQ | CT_FAST_INTR) 9 10 /*- 11 * [NetBSD for NEC PC-98 series] 12 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 13 * NetBSD/pc98 porting staff. All rights reserved. 14 * 15 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 16 * Naofumi HONDA. All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. The name of the author may not be used to endorse or promote products 27 * derived from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 32 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 33 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 34 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/bio.h> 46 #include <sys/buf.h> 47 #include <sys/queue.h> 48 #include <sys/malloc.h> 49 #include <sys/errno.h> 50 #include <sys/rman.h> 51 52 #include <machine/bus.h> 53 54 #include <cam/scsi/scsi_low.h> 55 56 #include <dev/ic/wd33c93reg.h> 57 #include <dev/ct/ctvar.h> 58 #include <dev/ct/ct_machdep.h> 59 60 #define CT_NTARGETS 8 61 #define CT_NLUNS 8 62 #define CT_RESET_DEFAULT 2000 63 #define CT_DELAY_MAX (2 * 1000 * 1000) 64 #define CT_DELAY_INTERVAL (1) 65 66 /*************************************************** 67 * DEBUG 68 ***************************************************/ 69 #ifdef CT_DEBUG 70 int ct_debug; 71 #endif /* CT_DEBUG */ 72 73 /*************************************************** 74 * IO control 75 ***************************************************/ 76 #define CT_USE_CCSEQ 0x0100 77 #define CT_FAST_INTR 0x0200 78 79 u_int ct_io_control = CT_IO_CONTROL_FLAGS; 80 81 /*************************************************** 82 * default data 83 ***************************************************/ 84 u_int8_t cthw_cmdlevel[256] = { 85 /* 0 1 2 3 4 5 6 7 8 9 A B C E D F */ 86 /**/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 , 87 /*1*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 88 /*2*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 , 89 /*3*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 90 /*4*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 91 /*5*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 92 /*6*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 93 /*7*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 94 /*8*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 95 /*9*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 96 /*A*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 97 /*B*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 98 /*C*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 99 /*D*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 100 /*E*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 101 /*F*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 102 }; 103 104 #if 0 105 /* default synch data table */ 106 /* A 10 6.6 5.0 4.0 3.3 2.8 2.5 2.0 M/s */ 107 /* X 100 150 200 250 300 350 400 500 ns */ 108 static struct ct_synch_data ct_synch_data_FSCSI[] = { 109 {25, 0xa0}, {37, 0xb0}, {50, 0x20}, {62, 0xd0}, {75, 0x30}, 110 {87, 0xf0}, {100, 0x40}, {125, 0x50}, {0, 0} 111 }; 112 113 static struct ct_synch_data ct_synch_data_SCSI[] = { 114 {50, 0x20}, {75, 0x30}, {100, 0x40}, {125, 0x50}, {0, 0} 115 }; 116 #endif 117 /*************************************************** 118 * DEVICE STRUCTURE 119 ***************************************************/ 120 extern struct cfdriver ct_cd; 121 122 /***************************************************************** 123 * Interface functions 124 *****************************************************************/ 125 static int ct_xfer(struct ct_softc *, u_int8_t *, int, int, u_int *); 126 static void ct_io_xfer(struct ct_softc *); 127 static int ct_reselected(struct ct_softc *, u_int8_t); 128 static void ct_phase_error(struct ct_softc *, u_int8_t); 129 static int ct_start_selection(struct ct_softc *, struct slccb *); 130 static int ct_msg(struct ct_softc *, struct targ_info *, u_int); 131 static int ct_world_start(struct ct_softc *, int); 132 static __inline void cthw_phase_bypass(struct ct_softc *, u_int8_t); 133 static int cthw_chip_reset(struct ct_bus_access_handle *, int *, int, int); 134 static void cthw_bus_reset(struct ct_softc *); 135 static int ct_ccb_nexus_establish(struct ct_softc *); 136 static int ct_lun_nexus_establish(struct ct_softc *); 137 static int ct_target_nexus_establish(struct ct_softc *, int, int); 138 static void cthw_attention(struct ct_softc *); 139 static int ct_targ_init(struct ct_softc *, struct targ_info *, int); 140 static int ct_unbusy(struct ct_softc *); 141 static void ct_attention(struct ct_softc *); 142 static struct ct_synch_data *ct_make_synch_table(struct ct_softc *); 143 static int ct_catch_intr(struct ct_softc *); 144 static int ct_poll(void *); 145 146 struct scsi_low_funcs ct_funcs = { 147 SC_LOW_INIT_T ct_world_start, 148 SC_LOW_BUSRST_T cthw_bus_reset, 149 SC_LOW_TARG_INIT_T ct_targ_init, 150 SC_LOW_LUN_INIT_T NULL, 151 152 SC_LOW_SELECT_T ct_start_selection, 153 SC_LOW_NEXUS_T ct_lun_nexus_establish, 154 SC_LOW_NEXUS_T ct_ccb_nexus_establish, 155 156 SC_LOW_ATTEN_T cthw_attention, 157 SC_LOW_MSG_T ct_msg, 158 159 SC_LOW_TIMEOUT_T NULL, 160 SC_LOW_POLL_T ct_poll, 161 162 NULL, /* SC_LOW_POWER_T cthw_power, */ 163 }; 164 165 /************************************************** 166 * HW functions 167 **************************************************/ 168 static __inline void 169 cthw_phase_bypass(struct ct_softc *ct, u_int8_t ph) 170 { 171 struct ct_bus_access_handle *chp = &ct->sc_ch; 172 173 ct_cr_write_1(chp, wd3s_cph, ph); 174 ct_cr_write_1(chp, wd3s_cmd, WD3S_SELECT_ATN_TFR); 175 } 176 177 static void 178 cthw_bus_reset(struct ct_softc *ct) 179 { 180 181 /* 182 * wd33c93 does not have bus reset function. 183 */ 184 if (ct->ct_bus_reset != NULL) 185 ((*ct->ct_bus_reset) (ct)); 186 } 187 188 static int 189 cthw_chip_reset(struct ct_bus_access_handle *chp, int *chiprevp, int chipclk, 190 int hostid) 191 { 192 #define CT_SELTIMEOUT_20MHz_REGV (0x80) 193 u_int8_t aux, regv; 194 u_int seltout; 195 int wc; 196 197 /* issue abort cmd */ 198 ct_cr_write_1(chp, wd3s_cmd, WD3S_ABORT); 199 DELAY(1000); /* 1ms wait */ 200 (void) ct_stat_read_1(chp); 201 (void) ct_cr_read_1(chp, wd3s_stat); 202 203 /* setup chip registers */ 204 regv = 0; 205 seltout = CT_SELTIMEOUT_20MHz_REGV; 206 switch (chipclk) 207 { 208 case 8: 209 case 10: 210 seltout = (seltout * chipclk) / 20; 211 regv = IDR_FS_8_10; 212 break; 213 214 case 12: 215 case 15: 216 seltout = (seltout * chipclk) / 20; 217 regv = IDR_FS_12_15; 218 break; 219 220 case 16: 221 case 20: 222 seltout = (seltout * chipclk) / 20; 223 regv = IDR_FS_16_20; 224 break; 225 226 default: 227 panic("ct: illegal chip clk rate"); 228 break; 229 } 230 231 regv |= IDR_EHP | hostid | IDR_RAF | IDR_EAF; 232 ct_cr_write_1(chp, wd3s_oid, regv); 233 234 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET); 235 for (wc = CT_RESET_DEFAULT; wc > 0; wc --) 236 { 237 aux = ct_stat_read_1(chp); 238 if (aux != 0xff && (aux & STR_INT)) 239 { 240 regv = ct_cr_read_1(chp, wd3s_stat); 241 if (regv == BSR_RESET || regv == BSR_AFM_RESET) 242 break; 243 244 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET); 245 } 246 DELAY(1); 247 } 248 if (wc == 0) 249 return ENXIO; 250 251 ct_cr_write_1(chp, wd3s_tout, seltout); 252 ct_cr_write_1(chp, wd3s_sid, SIDR_RESEL); 253 ct_cr_write_1(chp, wd3s_ctrl, CR_DEFAULT); 254 ct_cr_write_1(chp, wd3s_synch, 0); 255 if (chiprevp != NULL) 256 { 257 *chiprevp = CT_WD33C93; 258 if (regv == BSR_RESET) 259 goto out; 260 261 *chiprevp = CT_WD33C93_A; 262 ct_cr_write_1(chp, wd3s_qtag, 0xaa); 263 if (ct_cr_read_1(chp, wd3s_qtag) != 0xaa) 264 { 265 ct_cr_write_1(chp, wd3s_qtag, 0x0); 266 goto out; 267 } 268 ct_cr_write_1(chp, wd3s_qtag, 0x55); 269 if (ct_cr_read_1(chp, wd3s_qtag) != 0x55) 270 { 271 ct_cr_write_1(chp, wd3s_qtag, 0x0); 272 goto out; 273 } 274 ct_cr_write_1(chp, wd3s_qtag, 0x0); 275 *chiprevp = CT_WD33C93_B; 276 } 277 278 out: 279 (void) ct_stat_read_1(chp); 280 (void) ct_cr_read_1(chp, wd3s_stat); 281 return 0; 282 } 283 284 static struct ct_synch_data * 285 ct_make_synch_table(struct ct_softc *ct) 286 { 287 struct ct_synch_data *sdtp, *sdp; 288 u_int base, i, period; 289 290 sdtp = sdp = &ct->sc_default_sdt[0]; 291 292 if ((ct->sc_chipclk % 5) == 0) 293 base = 1000 / (5 * 2); /* 5 MHz type */ 294 else 295 base = 1000 / (4 * 2); /* 4 MHz type */ 296 297 if (ct->sc_chiprev >= CT_WD33C93_B) 298 { 299 /* fast scsi */ 300 for (i = 2; i < 8; i ++, sdp ++) 301 { 302 period = (base * i) / 2; 303 if (period >= 200) /* 5 MHz */ 304 break; 305 sdp->cs_period = period / 4; 306 sdp->cs_syncr = (i * 0x10) | 0x80; 307 } 308 } 309 310 for (i = 2; i < 8; i ++, sdp ++) 311 { 312 period = (base * i); 313 if (period > 500) /* 2 MHz */ 314 break; 315 sdp->cs_period = period / 4; 316 sdp->cs_syncr = (i * 0x10); 317 } 318 319 sdp->cs_period = 0; 320 sdp->cs_syncr = 0; 321 return sdtp; 322 } 323 324 /************************************************** 325 * Attach & Probe 326 **************************************************/ 327 int 328 ctprobesubr(struct ct_bus_access_handle *chp, u_int dvcfg, int hsid, 329 u_int chipclk, int *chiprevp) 330 { 331 332 #if 0 333 if ((ct_stat_read_1(chp) & STR_BSY) != 0) 334 return 0; 335 #endif 336 if (cthw_chip_reset(chp, chiprevp, chipclk, hsid) != 0) 337 return 0; 338 return 1; 339 } 340 341 void 342 ctattachsubr(struct ct_softc *ct) 343 { 344 struct scsi_low_softc *slp = &ct->sc_sclow; 345 346 ct->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */ 347 slp->sl_funcs = &ct_funcs; 348 slp->sl_flags |= HW_READ_PADDING; 349 (void) scsi_low_attach(slp, 0, CT_NTARGETS, CT_NLUNS, 350 sizeof(struct ct_targ_info), 0); 351 } 352 353 /************************************************** 354 * SCSI LOW interface functions 355 **************************************************/ 356 static void 357 cthw_attention(struct ct_softc *ct) 358 { 359 struct ct_bus_access_handle *chp = &ct->sc_ch; 360 361 ct->sc_atten = 1; 362 if ((ct_stat_read_1(chp) & (STR_BSY | STR_CIP)) != 0) 363 return; 364 365 ct_cr_write_1(chp, wd3s_cmd, WD3S_ASSERT_ATN); 366 DELAY(10); 367 if ((ct_stat_read_1(chp) & STR_LCI) == 0) 368 ct->sc_atten = 0; 369 ct_unbusy(ct); 370 return; 371 } 372 373 static void 374 ct_attention(struct ct_softc *ct) 375 { 376 struct scsi_low_softc *slp = &ct->sc_sclow; 377 378 if (slp->sl_atten == 0) 379 { 380 ct_unbusy(ct); 381 scsi_low_attention(slp); 382 } 383 else if (ct->sc_atten != 0) 384 { 385 ct_unbusy(ct); 386 cthw_attention(ct); 387 } 388 } 389 390 static int 391 ct_targ_init(struct ct_softc *ct, struct targ_info *ti, int action) 392 { 393 struct ct_targ_info *cti = (void *) ti; 394 395 if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE) 396 { 397 if (ct->sc_sdp == NULL) 398 { 399 ct->sc_sdp = ct_make_synch_table(ct); 400 } 401 402 switch (ct->sc_chiprev) 403 { 404 default: 405 ti->ti_maxsynch.offset = 5; 406 break; 407 408 case CT_WD33C93_A: 409 case CT_AM33C93_A: 410 ti->ti_maxsynch.offset = 12; 411 break; 412 413 case CT_WD33C93_B: 414 case CT_WD33C93_C: 415 ti->ti_maxsynch.offset = 12; 416 break; 417 } 418 419 ti->ti_maxsynch.period = ct->sc_sdp[0].cs_period; 420 ti->ti_width = SCSI_LOW_BUS_WIDTH_8; 421 cti->cti_syncreg = 0; 422 } 423 424 return 0; 425 } 426 427 static int 428 ct_world_start(struct ct_softc *ct, int fdone) 429 { 430 struct scsi_low_softc *slp = &ct->sc_sclow; 431 struct ct_bus_access_handle *chp = &ct->sc_ch; 432 433 if (ct->sc_sdp == NULL) 434 { 435 ct->sc_sdp = ct_make_synch_table(ct); 436 } 437 438 if (slp->sl_cfgflags & CFG_NOPARITY) 439 ct->sc_creg = CR_DEFAULT; 440 else 441 ct->sc_creg = CR_DEFAULT_HP; 442 443 if (ct->sc_dma & CT_DMA_DMASTART) 444 (*ct->ct_dma_xfer_stop) (ct); 445 if (ct->sc_dma & CT_DMA_PIOSTART) 446 (*ct->ct_pio_xfer_stop) (ct); 447 ct->sc_dma = 0; 448 ct->sc_atten = 0; 449 450 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid); 451 scsi_low_bus_reset(slp); 452 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid); 453 454 return 0; 455 } 456 457 static int 458 ct_start_selection(struct ct_softc *ct, struct slccb *cb) 459 { 460 struct scsi_low_softc *slp = &ct->sc_sclow; 461 struct ct_bus_access_handle *chp = &ct->sc_ch; 462 463 struct targ_info *ti = slp->sl_Tnexus; 464 struct lun_info *li = slp->sl_Lnexus; 465 int s, satok; 466 u_int8_t cmd; 467 468 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000; 469 ct->sc_atten = 0; 470 satok = 0; 471 472 if (scsi_low_is_disconnect_ok(cb) != 0) 473 { 474 if (ct->sc_chiprev >= CT_WD33C93_A) 475 satok = 1; 476 else if (cthw_cmdlevel[slp->sl_scp.scp_cmd[0]] != 0) 477 satok = 1; 478 } 479 480 if (satok != 0 && 481 scsi_low_is_msgout_continue(ti, SCSI_LOW_MSG_IDENTIFY) == 0) 482 { 483 cmd = WD3S_SELECT_ATN_TFR; 484 ct->sc_satgo = CT_SAT_GOING; 485 } 486 else 487 { 488 cmd = WD3S_SELECT_ATN; 489 ct->sc_satgo = 0; 490 } 491 492 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) != 0) 493 return SCSI_LOW_START_FAIL; 494 495 if ((ct->sc_satgo & CT_SAT_GOING) != 0) 496 { 497 (void) scsi_low_msgout(slp, ti, SCSI_LOW_MSGOUT_INIT); 498 scsi_low_cmd(slp, ti); 499 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen); 500 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen); 501 } 502 else 503 { 504 /* anyway attention assert */ 505 SCSI_LOW_ASSERT_ATN(slp); 506 } 507 508 ct_target_nexus_establish(ct, li->li_lun, slp->sl_scp.scp_direction); 509 510 s = splhigh(); 511 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) == 0) 512 { 513 /* XXX: 514 * Reload a lun again here. 515 */ 516 ct_cr_write_1(chp, wd3s_lun, li->li_lun); 517 ct_cr_write_1(chp, wd3s_cmd, cmd); 518 if ((ct_stat_read_1(chp) & STR_LCI) == 0) 519 { 520 splx(s); 521 SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART); 522 return SCSI_LOW_START_OK; 523 } 524 } 525 splx(s); 526 return SCSI_LOW_START_FAIL; 527 } 528 529 static int 530 ct_msg(struct ct_softc *ct, struct targ_info *ti, u_int msg) 531 { 532 struct ct_bus_access_handle *chp = &ct->sc_ch; 533 struct ct_targ_info *cti = (void *) ti; 534 struct ct_synch_data *csp = ct->sc_sdp; 535 u_int offset, period; 536 int error; 537 538 if ((msg & SCSI_LOW_MSG_WIDE) != 0) 539 { 540 if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8) 541 { 542 ti->ti_width = SCSI_LOW_BUS_WIDTH_8; 543 return EINVAL; 544 } 545 return 0; 546 } 547 548 if ((msg & SCSI_LOW_MSG_SYNCH) == 0) 549 return 0; 550 551 offset = ti->ti_maxsynch.offset; 552 period = ti->ti_maxsynch.period; 553 for ( ; csp->cs_period != 0; csp ++) 554 { 555 if (period == csp->cs_period) 556 break; 557 } 558 559 if (ti->ti_maxsynch.period != 0 && csp->cs_period == 0) 560 { 561 ti->ti_maxsynch.period = 0; 562 ti->ti_maxsynch.offset = 0; 563 cti->cti_syncreg = 0; 564 error = EINVAL; 565 } 566 else 567 { 568 cti->cti_syncreg = ((offset & 0x0f) | csp->cs_syncr); 569 error = 0; 570 } 571 572 if (ct->ct_synch_setup != 0) 573 (*ct->ct_synch_setup) (ct, ti); 574 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg); 575 return error; 576 } 577 578 /************************************************* 579 * <DATA PHASE> 580 *************************************************/ 581 static int 582 ct_xfer(struct ct_softc *ct, u_int8_t *data, int len, int direction, 583 u_int *statp) 584 { 585 struct ct_bus_access_handle *chp = &ct->sc_ch; 586 int wc; 587 register u_int8_t aux; 588 589 *statp = 0; 590 if (len == 1) 591 { 592 ct_cr_write_1(chp, wd3s_cmd, WD3S_SBT | WD3S_TFR_INFO); 593 } 594 else 595 { 596 cthw_set_count(chp, len); 597 ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO); 598 } 599 600 aux = ct_stat_read_1(chp); 601 if ((aux & STR_LCI) != 0) 602 { 603 cthw_set_count(chp, 0); 604 return len; 605 } 606 607 for (wc = 0; wc < ct->sc_tmaxcnt; wc ++) 608 { 609 /* check data ready */ 610 if ((aux & (STR_BSY | STR_DBR)) == (STR_BSY | STR_DBR)) 611 { 612 if (direction == SCSI_LOW_READ) 613 { 614 *data = ct_cr_read_1(chp, wd3s_data); 615 if ((aux & STR_PE) != 0) 616 *statp |= SCSI_LOW_DATA_PE; 617 } 618 else 619 { 620 ct_cr_write_1(chp, wd3s_data, *data); 621 } 622 len --; 623 if (len <= 0) 624 break; 625 data ++; 626 } 627 else 628 { 629 DELAY(1); 630 } 631 632 /* check phase miss */ 633 aux = ct_stat_read_1(chp); 634 if ((aux & STR_INT) != 0) 635 break; 636 } 637 return len; 638 } 639 640 #define CT_PADDING_BUF_SIZE 32 641 642 static void 643 ct_io_xfer(struct ct_softc *ct) 644 { 645 struct scsi_low_softc *slp = &ct->sc_sclow; 646 struct ct_bus_access_handle *chp = &ct->sc_ch; 647 struct sc_p *sp = &slp->sl_scp; 648 u_int stat; 649 int len; 650 u_int8_t pbuf[CT_PADDING_BUF_SIZE]; 651 652 /* polling mode */ 653 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg); 654 655 if (sp->scp_datalen <= 0) 656 { 657 slp->sl_error |= PDMAERR; 658 659 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE) 660 bzero(pbuf, CT_PADDING_BUF_SIZE); 661 ct_xfer(ct, pbuf, CT_PADDING_BUF_SIZE, 662 sp->scp_direction, &stat); 663 } 664 else 665 { 666 len = ct_xfer(ct, sp->scp_data, sp->scp_datalen, 667 sp->scp_direction, &stat); 668 sp->scp_data += (sp->scp_datalen - len); 669 sp->scp_datalen = len; 670 } 671 } 672 673 /************************************************** 674 * <PHASE ERROR> 675 **************************************************/ 676 struct ct_err { 677 u_char *pe_msg; 678 u_int pe_err; 679 u_int pe_errmsg; 680 int pe_done; 681 }; 682 683 struct ct_err ct_cmderr[] = { 684 /**/ { "illegal cmd", FATALIO, SCSI_LOW_MSG_ABORT, 1}, 685 /*1*/ { "unexpected bus free", FATALIO, 0, 1}, 686 /*2*/ { NULL, SELTIMEOUTIO, 0, 1}, 687 /*3*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0}, 688 /*4*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0}, 689 /*5*/ { "unknown" , FATALIO, SCSI_LOW_MSG_ABORT, 1}, 690 /*6*/ { "miss reselection (target mode)", FATALIO, SCSI_LOW_MSG_ABORT, 0}, 691 /*7*/ { "wrong status byte", PARITYERR, SCSI_LOW_MSG_ERROR, 0}, 692 }; 693 694 static void 695 ct_phase_error(struct ct_softc *ct, u_int8_t scsi_status) 696 { 697 struct scsi_low_softc *slp = &ct->sc_sclow; 698 struct targ_info *ti = slp->sl_Tnexus; 699 struct ct_err *pep; 700 u_int msg = 0; 701 702 if ((scsi_status & BSR_CM) == BSR_CMDERR && 703 (scsi_status & BSR_PHVALID) == 0) 704 { 705 pep = &ct_cmderr[scsi_status & BSR_PM]; 706 slp->sl_error |= pep->pe_err; 707 if ((pep->pe_err & PARITYERR) != 0) 708 { 709 if (ti->ti_phase == PH_MSGIN) 710 msg = SCSI_LOW_MSG_PARITY; 711 else 712 msg = SCSI_LOW_MSG_ERROR; 713 } 714 else 715 msg = pep->pe_errmsg; 716 717 if (msg != 0) 718 scsi_low_assert_msg(slp, slp->sl_Tnexus, msg, 1); 719 720 if (pep->pe_msg != NULL) 721 { 722 device_printf(slp->sl_dev, "phase error: %s", 723 pep->pe_msg); 724 scsi_low_print(slp, slp->sl_Tnexus); 725 } 726 727 if (pep->pe_done != 0) 728 scsi_low_disconnected(slp, ti); 729 } 730 else 731 { 732 slp->sl_error |= FATALIO; 733 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD, "phase error"); 734 } 735 } 736 737 /************************************************** 738 * ### SCSI PHASE SEQUENCER ### 739 **************************************************/ 740 static int 741 ct_reselected(struct ct_softc *ct, u_int8_t scsi_status) 742 { 743 struct scsi_low_softc *slp = &ct->sc_sclow; 744 struct ct_bus_access_handle *chp = &ct->sc_ch; 745 struct targ_info *ti; 746 u_int sid; 747 u_int8_t regv; 748 749 ct->sc_atten = 0; 750 ct->sc_satgo &= ~CT_SAT_GOING; 751 regv = ct_cr_read_1(chp, wd3s_sid); 752 if ((regv & SIDR_VALID) == 0) 753 return EJUSTRETURN; 754 755 sid = regv & SIDR_IDM; 756 if ((ti = scsi_low_reselected(slp, sid)) == NULL) 757 return EJUSTRETURN; 758 759 ct_target_nexus_establish(ct, 0, SCSI_LOW_READ); 760 if (scsi_status != BSR_AFM_RESEL) 761 return EJUSTRETURN; 762 763 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN); 764 regv = ct_cr_read_1(chp, wd3s_data); 765 if (scsi_low_msgin(slp, ti, (u_int) regv) == 0) 766 { 767 if (scsi_low_is_msgout_continue(ti, 0) != 0) 768 { 769 /* XXX: scsi_low_attetion */ 770 scsi_low_attention(slp); 771 } 772 } 773 774 if (ct->sc_atten != 0) 775 { 776 ct_attention(ct); 777 } 778 779 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK); 780 return EJUSTRETURN; 781 } 782 783 static int 784 ct_target_nexus_establish(struct ct_softc *ct, int lun, int dir) 785 { 786 struct scsi_low_softc *slp = &ct->sc_sclow; 787 struct ct_bus_access_handle *chp = &ct->sc_ch; 788 struct targ_info *ti = slp->sl_Tnexus; 789 struct ct_targ_info *cti = (void *) ti; 790 791 if (dir == SCSI_LOW_WRITE) 792 ct_cr_write_1(chp, wd3s_did, ti->ti_id); 793 else 794 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD); 795 ct_cr_write_1(chp, wd3s_lun, lun); 796 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA); 797 ct_cr_write_1(chp, wd3s_cph, 0); 798 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg); 799 cthw_set_count(chp, 0); 800 return 0; 801 } 802 803 static int 804 ct_lun_nexus_establish(struct ct_softc *ct) 805 { 806 struct scsi_low_softc *slp = &ct->sc_sclow; 807 struct ct_bus_access_handle *chp = &ct->sc_ch; 808 struct lun_info *li = slp->sl_Lnexus; 809 810 ct_cr_write_1(chp, wd3s_lun, li->li_lun); 811 return 0; 812 } 813 814 static int 815 ct_ccb_nexus_establish(struct ct_softc *ct) 816 { 817 struct scsi_low_softc *slp = &ct->sc_sclow; 818 struct ct_bus_access_handle *chp = &ct->sc_ch; 819 struct lun_info *li = slp->sl_Lnexus; 820 struct targ_info *ti = slp->sl_Tnexus; 821 struct ct_targ_info *cti = (void *) ti; 822 struct slccb *cb = slp->sl_Qnexus; 823 824 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000; 825 826 if ((ct->sc_satgo & CT_SAT_GOING) != 0) 827 { 828 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen); 829 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen); 830 } 831 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE) 832 ct_cr_write_1(chp, wd3s_did, ti->ti_id); 833 else 834 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD); 835 ct_cr_write_1(chp, wd3s_lun, li->li_lun); 836 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg); 837 return 0; 838 } 839 840 static int 841 ct_unbusy(struct ct_softc *ct) 842 { 843 struct scsi_low_softc *slp = &ct->sc_sclow; 844 struct ct_bus_access_handle *chp = &ct->sc_ch; 845 int wc; 846 register u_int8_t regv; 847 848 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++) 849 { 850 regv = ct_stat_read_1(chp); 851 if ((regv & (STR_BSY | STR_CIP)) == 0) 852 return 0; 853 if (regv == (u_int8_t) -1) 854 return EIO; 855 856 DELAY(CT_DELAY_INTERVAL); 857 } 858 859 device_printf(slp->sl_dev, "unbusy timeout\n"); 860 return EBUSY; 861 } 862 863 static int 864 ct_catch_intr(struct ct_softc *ct) 865 { 866 struct ct_bus_access_handle *chp = &ct->sc_ch; 867 int wc; 868 register u_int8_t regv; 869 870 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++) 871 { 872 regv = ct_stat_read_1(chp); 873 if ((regv & (STR_INT | STR_BSY | STR_CIP)) == STR_INT) 874 return 0; 875 876 DELAY(CT_DELAY_INTERVAL); 877 } 878 return EJUSTRETURN; 879 } 880 881 void 882 ctintr(void *arg) 883 { 884 struct ct_softc *ct = arg; 885 struct scsi_low_softc *slp = &ct->sc_sclow; 886 887 SCSI_LOW_LOCK(slp); 888 ct_poll(ct); 889 SCSI_LOW_UNLOCK(slp); 890 } 891 892 static int 893 ct_poll(void *arg) 894 { 895 struct ct_softc *ct = arg; 896 struct scsi_low_softc *slp = &ct->sc_sclow; 897 struct ct_bus_access_handle *chp = &ct->sc_ch; 898 struct targ_info *ti; 899 struct buf *bp; 900 u_int derror, flags; 901 int len, satgo, error; 902 u_int8_t scsi_status, regv; 903 904 again: 905 if (slp->sl_flags & HW_INACTIVE) 906 return 0; 907 908 /************************************************** 909 * Get status & bus phase 910 **************************************************/ 911 if ((ct_stat_read_1(chp) & STR_INT) == 0) 912 return 0; 913 914 scsi_status = ct_cr_read_1(chp, wd3s_stat); 915 if (scsi_status == ((u_int8_t) -1)) 916 return 1; 917 918 /************************************************** 919 * Check reselection, or nexus 920 **************************************************/ 921 if (scsi_status == BSR_RESEL || scsi_status == BSR_AFM_RESEL) 922 { 923 if (ct_reselected(ct, scsi_status) == EJUSTRETURN) 924 return 1; 925 } 926 927 if ((ti = slp->sl_Tnexus) == NULL) 928 return 1; 929 930 /************************************************** 931 * Debug section 932 **************************************************/ 933 #ifdef CT_DEBUG 934 if (ct_debug > 0) 935 { 936 scsi_low_print(slp, NULL); 937 device_printf(slp->sl_dev, "scsi_status 0x%x\n\n", 938 (u_int) scsi_status); 939 #ifdef KDB 940 if (ct_debug > 1) 941 kdb_enter(KDB_WHY_CAM, "ct"); 942 #endif /* KDB */ 943 } 944 #endif /* CT_DEBUG */ 945 946 /************************************************** 947 * Internal scsi phase 948 **************************************************/ 949 satgo = ct->sc_satgo; 950 ct->sc_satgo &= ~CT_SAT_GOING; 951 952 switch (ti->ti_phase) 953 { 954 case PH_SELSTART: 955 if ((satgo & CT_SAT_GOING) == 0) 956 { 957 if (scsi_status != BSR_SELECTED) 958 { 959 ct_phase_error(ct, scsi_status); 960 return 1; 961 } 962 scsi_low_arbit_win(slp); 963 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED); 964 return 1; 965 } 966 else 967 { 968 scsi_low_arbit_win(slp); 969 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); /* XXX */ 970 } 971 break; 972 973 case PH_RESEL: 974 if ((scsi_status & BSR_PHVALID) == 0 || 975 (scsi_status & BSR_PM) != BSR_MSGIN) 976 { 977 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD, 978 "phase miss after reselect"); 979 return 1; 980 } 981 break; 982 983 default: 984 if (slp->sl_flags & HW_PDMASTART) 985 { 986 slp->sl_flags &= ~HW_PDMASTART; 987 if (ct->sc_dma & CT_DMA_DMASTART) 988 { 989 (*ct->ct_dma_xfer_stop) (ct); 990 ct->sc_dma &= ~CT_DMA_DMASTART; 991 } 992 else if (ct->sc_dma & CT_DMA_PIOSTART) 993 { 994 (*ct->ct_pio_xfer_stop) (ct); 995 ct->sc_dma &= ~CT_DMA_PIOSTART; 996 } 997 else 998 { 999 scsi_low_data_finish(slp); 1000 } 1001 } 1002 break; 1003 } 1004 1005 /************************************************** 1006 * parse scsi phase 1007 **************************************************/ 1008 if (scsi_status & BSR_PHVALID) 1009 { 1010 /************************************************** 1011 * Normal SCSI phase. 1012 **************************************************/ 1013 if ((scsi_status & BSR_CM) == BSR_CMDABT) 1014 { 1015 ct_phase_error(ct, scsi_status); 1016 return 1; 1017 } 1018 1019 switch (scsi_status & BSR_PM) 1020 { 1021 case BSR_DATAOUT: 1022 SCSI_LOW_SETUP_PHASE(ti, PH_DATA); 1023 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0) 1024 { 1025 ct_attention(ct); 1026 } 1027 goto common_data_phase; 1028 1029 case BSR_DATAIN: 1030 SCSI_LOW_SETUP_PHASE(ti, PH_DATA); 1031 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0) 1032 { 1033 ct_attention(ct); 1034 } 1035 1036 common_data_phase: 1037 if (slp->sl_scp.scp_datalen > 0) 1038 { 1039 slp->sl_flags |= HW_PDMASTART; 1040 if ((ct->sc_xmode & CT_XMODE_PIO) != 0) 1041 { 1042 error = (*ct->ct_pio_xfer_start) (ct); 1043 if (error == 0) 1044 { 1045 ct->sc_dma |= CT_DMA_PIOSTART; 1046 return 1; 1047 } 1048 } 1049 1050 if ((ct->sc_xmode & CT_XMODE_DMA) != 0) 1051 { 1052 error = (*ct->ct_dma_xfer_start) (ct); 1053 if (error == 0) 1054 { 1055 ct->sc_dma |= CT_DMA_DMASTART; 1056 return 1; 1057 } 1058 } 1059 } 1060 else 1061 { 1062 if (slp->sl_scp.scp_direction == SCSI_LOW_READ) 1063 { 1064 if (!(slp->sl_flags & HW_READ_PADDING)) 1065 { 1066 device_printf(slp->sl_dev, 1067 "read padding required\n"); 1068 return 1; 1069 } 1070 } 1071 else 1072 { 1073 if (!(slp->sl_flags & HW_WRITE_PADDING)) 1074 { 1075 device_printf(slp->sl_dev, 1076 "write padding required\n"); 1077 return 1; 1078 } 1079 } 1080 slp->sl_flags |= HW_PDMASTART; 1081 } 1082 1083 ct_io_xfer(ct); 1084 return 1; 1085 1086 case BSR_CMDOUT: 1087 SCSI_LOW_SETUP_PHASE(ti, PH_CMD); 1088 if (scsi_low_cmd(slp, ti) != 0) 1089 { 1090 ct_attention(ct); 1091 } 1092 1093 if (ct_xfer(ct, slp->sl_scp.scp_cmd, 1094 slp->sl_scp.scp_cmdlen, 1095 SCSI_LOW_WRITE, &derror) != 0) 1096 { 1097 device_printf(slp->sl_dev, 1098 "scsi cmd xfer short\n"); 1099 } 1100 return 1; 1101 1102 case BSR_STATIN: 1103 SCSI_LOW_SETUP_PHASE(ti, PH_STAT); 1104 if ((ct_io_control & CT_USE_CCSEQ) != 0) 1105 { 1106 if (scsi_low_is_msgout_continue(ti, 0) != 0 || 1107 ct->sc_atten != 0) 1108 { 1109 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, 1110 &derror); 1111 scsi_low_statusin(slp, ti, 1112 regv | derror); 1113 } 1114 else 1115 { 1116 ct->sc_satgo |= CT_SAT_GOING; 1117 cthw_set_count(chp, 0); 1118 cthw_phase_bypass(ct, 0x41); 1119 } 1120 } 1121 else 1122 { 1123 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror); 1124 scsi_low_statusin(slp, ti, regv | derror); 1125 } 1126 return 1; 1127 1128 case BSR_UNSPINFO0: 1129 case BSR_UNSPINFO1: 1130 device_printf(slp->sl_dev, "illegal bus phase (0x%x)\n", 1131 (u_int) scsi_status); 1132 scsi_low_print(slp, ti); 1133 return 1; 1134 1135 case BSR_MSGOUT: 1136 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); 1137 flags = SCSI_LOW_MSGOUT_UNIFY; 1138 if (ti->ti_ophase != ti->ti_phase) 1139 flags |= SCSI_LOW_MSGOUT_INIT; 1140 len = scsi_low_msgout(slp, ti, flags); 1141 1142 if (len > 1 && slp->sl_atten == 0) 1143 { 1144 ct_attention(ct); 1145 } 1146 1147 if (ct_xfer(ct, ti->ti_msgoutstr, len, 1148 SCSI_LOW_WRITE, &derror) != 0) 1149 { 1150 device_printf(slp->sl_dev, 1151 "scsi msgout xfer short\n"); 1152 } 1153 SCSI_LOW_DEASSERT_ATN(slp); 1154 ct->sc_atten = 0; 1155 return 1; 1156 1157 case BSR_MSGIN:/* msg in */ 1158 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN); 1159 1160 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror); 1161 if (scsi_low_msgin(slp, ti, regv | derror) == 0) 1162 { 1163 if (scsi_low_is_msgout_continue(ti, 0) != 0) 1164 { 1165 /* XXX: scsi_low_attetion */ 1166 scsi_low_attention(slp); 1167 } 1168 } 1169 1170 if ((ct_io_control & CT_FAST_INTR) != 0) 1171 { 1172 if (ct_catch_intr(ct) == 0) 1173 goto again; 1174 } 1175 return 1; 1176 } 1177 } 1178 else 1179 { 1180 /************************************************** 1181 * Special SCSI phase 1182 **************************************************/ 1183 switch (scsi_status) 1184 { 1185 case BSR_SATSDP: /* SAT with save data pointer */ 1186 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN); 1187 ct->sc_satgo |= CT_SAT_GOING; 1188 scsi_low_msgin(slp, ti, MSG_SAVESP); 1189 cthw_phase_bypass(ct, 0x41); 1190 return 1; 1191 1192 case BSR_SATFIN: /* SAT COMPLETE */ 1193 /* 1194 * emulate statusin => msgin 1195 */ 1196 SCSI_LOW_SETUP_PHASE(ti, PH_STAT); 1197 scsi_low_statusin(slp, ti, ct_cr_read_1(chp, wd3s_lun)); 1198 1199 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN); 1200 scsi_low_msgin(slp, ti, MSG_COMP); 1201 1202 scsi_low_disconnected(slp, ti); 1203 return 1; 1204 1205 case BSR_ACKREQ: /* negate ACK */ 1206 if (ct->sc_atten != 0) 1207 { 1208 ct_attention(ct); 1209 } 1210 1211 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK); 1212 if ((ct_io_control & CT_FAST_INTR) != 0) 1213 { 1214 /* XXX: 1215 * Should clear a pending interrupt and 1216 * sync with a next interrupt! 1217 */ 1218 ct_catch_intr(ct); 1219 } 1220 return 1; 1221 1222 case BSR_DISC: /* disconnect */ 1223 if (slp->sl_msgphase == MSGPH_NULL && 1224 (satgo & CT_SAT_GOING) != 0) 1225 { 1226 /* 1227 * emulate disconnect msg 1228 */ 1229 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN); 1230 scsi_low_msgin(slp, ti, MSG_DISCON); 1231 } 1232 scsi_low_disconnected(slp, ti); 1233 return 1; 1234 1235 default: 1236 break; 1237 } 1238 } 1239 1240 ct_phase_error(ct, scsi_status); 1241 return 1; 1242 }
Cache object: 40b98160e8c09430be058b5f8903c090
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