FreeBSD/Linux Kernel Cross Reference
sys/dev/ct/ct.c
1 /* $NecBSD: ct.c,v 1.13.12.5 2001/06/26 07:31:53 honda Exp $ */
2
3 #include <sys/cdefs.h>
4 __FBSDID("$FreeBSD: releng/5.2/sys/dev/ct/ct.c 119418 2003-08-24 17:55:58Z obrien $");
5 /* $NetBSD$ */
6
7 #define CT_DEBUG
8 #define CT_IO_CONTROL_FLAGS (CT_USE_CCSEQ | CT_FAST_INTR)
9
10 /*
11 * [NetBSD for NEC PC-98 series]
12 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
13 * NetBSD/pc98 porting staff. All rights reserved.
14 *
15 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
16 * Naofumi HONDA. All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
20 * are met:
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * 3. The name of the author may not be used to endorse or promote products
27 * derived from this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
33 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 */
41
42 #include "opt_ddb.h"
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #if defined(__FreeBSD__) && __FreeBSD_version > 500001
48 #include <sys/bio.h>
49 #endif /* __ FreeBSD__ */
50 #include <sys/buf.h>
51 #include <sys/queue.h>
52 #include <sys/malloc.h>
53 #include <sys/errno.h>
54
55 #ifdef __NetBSD__
56 #include <sys/device.h>
57
58 #include <machine/bus.h>
59 #include <machine/intr.h>
60
61 #include <dev/scsipi/scsi_all.h>
62 #include <dev/scsipi/scsipi_all.h>
63 #include <dev/scsipi/scsiconf.h>
64 #include <dev/scsipi/scsi_disk.h>
65
66 #include <machine/dvcfg.h>
67 #include <machine/physio_proc.h>
68
69 #include <i386/Cbus/dev/scsi_low.h>
70
71 #include <dev/ic/wd33c93reg.h>
72 #include <i386/Cbus/dev/ct/ctvar.h>
73 #include <i386/Cbus/dev/ct/ct_machdep.h>
74 #endif /* __NetBSD__ */
75
76 #ifdef __FreeBSD__
77 #include <machine/bus.h>
78
79 #include <machine/dvcfg.h>
80 #include <machine/physio_proc.h>
81
82 #include <cam/scsi/scsi_low.h>
83
84 #include <dev/ic/wd33c93reg.h>
85 #include <dev/ct/ctvar.h>
86 #include <dev/ct/ct_machdep.h>
87 #endif /* __FreeBSD__ */
88
89 #define CT_NTARGETS 8
90 #define CT_NLUNS 8
91 #define CT_RESET_DEFAULT 2000
92 #define CT_DELAY_MAX (2 * 1000 * 1000)
93 #define CT_DELAY_INTERVAL (1)
94
95 /***************************************************
96 * DEBUG
97 ***************************************************/
98 #ifdef CT_DEBUG
99 int ct_debug;
100 #endif /* CT_DEBUG */
101
102 /***************************************************
103 * IO control
104 ***************************************************/
105 #define CT_USE_CCSEQ 0x0100
106 #define CT_FAST_INTR 0x0200
107
108 u_int ct_io_control = CT_IO_CONTROL_FLAGS;
109
110 /***************************************************
111 * default data
112 ***************************************************/
113 u_int8_t cthw_cmdlevel[256] = {
114 /* 0 1 2 3 4 5 6 7 8 9 A B C E D F */
115 /**/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
116 /*1*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
117 /*2*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
118 /*3*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
119 /*4*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
120 /*5*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
121 /*6*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
122 /*7*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
123 /*8*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
124 /*9*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
125 /*A*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
126 /*B*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
127 /*C*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
128 /*D*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
129 /*E*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
130 /*F*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
131 };
132
133 #if 0
134 /* default synch data table */
135 /* A 10 6.6 5.0 4.0 3.3 2.8 2.5 2.0 M/s */
136 /* X 100 150 200 250 300 350 400 500 ns */
137 static struct ct_synch_data ct_synch_data_FSCSI[] = {
138 {25, 0xa0}, {37, 0xb0}, {50, 0x20}, {62, 0xd0}, {75, 0x30},
139 {87, 0xf0}, {100, 0x40}, {125, 0x50}, {0, 0}
140 };
141
142 static struct ct_synch_data ct_synch_data_SCSI[] = {
143 {50, 0x20}, {75, 0x30}, {100, 0x40}, {125, 0x50}, {0, 0}
144 };
145 #endif
146 /***************************************************
147 * DEVICE STRUCTURE
148 ***************************************************/
149 extern struct cfdriver ct_cd;
150
151 /*****************************************************************
152 * Interface functions
153 *****************************************************************/
154 static int ct_xfer(struct ct_softc *, u_int8_t *, int, int, u_int *);
155 static void ct_io_xfer(struct ct_softc *);
156 static int ct_reselected(struct ct_softc *, u_int8_t);
157 static void ct_phase_error(struct ct_softc *, u_int8_t);
158 static int ct_start_selection(struct ct_softc *, struct slccb *);
159 static int ct_msg(struct ct_softc *, struct targ_info *, u_int);
160 static int ct_world_start(struct ct_softc *, int);
161 static __inline void cthw_phase_bypass(struct ct_softc *, u_int8_t);
162 static int cthw_chip_reset(struct ct_bus_access_handle *, int *, int, int);
163 static void cthw_bus_reset(struct ct_softc *);
164 static int ct_ccb_nexus_establish(struct ct_softc *);
165 static int ct_lun_nexus_establish(struct ct_softc *);
166 static int ct_target_nexus_establish(struct ct_softc *, int, int);
167 static void cthw_attention(struct ct_softc *);
168 static int ct_targ_init(struct ct_softc *, struct targ_info *, int);
169 static int ct_unbusy(struct ct_softc *);
170 static void ct_attention(struct ct_softc *);
171 static struct ct_synch_data *ct_make_synch_table(struct ct_softc *);
172 static int ct_catch_intr(struct ct_softc *);
173
174 struct scsi_low_funcs ct_funcs = {
175 SC_LOW_INIT_T ct_world_start,
176 SC_LOW_BUSRST_T cthw_bus_reset,
177 SC_LOW_TARG_INIT_T ct_targ_init,
178 SC_LOW_LUN_INIT_T NULL,
179
180 SC_LOW_SELECT_T ct_start_selection,
181 SC_LOW_NEXUS_T ct_lun_nexus_establish,
182 SC_LOW_NEXUS_T ct_ccb_nexus_establish,
183
184 SC_LOW_ATTEN_T cthw_attention,
185 SC_LOW_MSG_T ct_msg,
186
187 SC_LOW_TIMEOUT_T NULL,
188 SC_LOW_POLL_T ctintr,
189
190 NULL, /* SC_LOW_POWER_T cthw_power, */
191 };
192
193 /**************************************************
194 * HW functions
195 **************************************************/
196 static __inline void
197 cthw_phase_bypass(ct, ph)
198 struct ct_softc *ct;
199 u_int8_t ph;
200 {
201 struct ct_bus_access_handle *chp = &ct->sc_ch;
202
203 ct_cr_write_1(chp, wd3s_cph, ph);
204 ct_cr_write_1(chp, wd3s_cmd, WD3S_SELECT_ATN_TFR);
205 }
206
207 static void
208 cthw_bus_reset(ct)
209 struct ct_softc *ct;
210 {
211
212 /*
213 * wd33c93 does not have bus reset function.
214 */
215 if (ct->ct_bus_reset != NULL)
216 ((*ct->ct_bus_reset) (ct));
217 }
218
219 static int
220 cthw_chip_reset(chp, chiprevp, chipclk, hostid)
221 struct ct_bus_access_handle *chp;
222 int *chiprevp;
223 int chipclk, hostid;
224 {
225 #define CT_SELTIMEOUT_20MHz_REGV (0x80)
226 u_int8_t aux, regv;
227 u_int seltout;
228 int wc;
229
230 /* issue abort cmd */
231 ct_cr_write_1(chp, wd3s_cmd, WD3S_ABORT);
232 SCSI_LOW_DELAY(1000); /* 1ms wait */
233 (void) ct_stat_read_1(chp);
234 (void) ct_cr_read_1(chp, wd3s_stat);
235
236 /* setup chip registers */
237 regv = 0;
238 seltout = CT_SELTIMEOUT_20MHz_REGV;
239 switch (chipclk)
240 {
241 case 8:
242 case 10:
243 seltout = (seltout * chipclk) / 20;
244 regv = IDR_FS_8_10;
245 break;
246
247 case 12:
248 case 15:
249 seltout = (seltout * chipclk) / 20;
250 regv = IDR_FS_12_15;
251 break;
252
253 case 16:
254 case 20:
255 seltout = (seltout * chipclk) / 20;
256 regv = IDR_FS_16_20;
257 break;
258
259 default:
260 panic("ct: illegal chip clk rate");
261 break;
262 }
263
264 regv |= IDR_EHP | hostid | IDR_RAF | IDR_EAF;
265 ct_cr_write_1(chp, wd3s_oid, regv);
266
267 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
268 for (wc = CT_RESET_DEFAULT; wc > 0; wc --)
269 {
270 aux = ct_stat_read_1(chp);
271 if (aux != 0xff && (aux & STR_INT))
272 {
273 regv = ct_cr_read_1(chp, wd3s_stat);
274 if (regv == BSR_RESET || regv == BSR_AFM_RESET)
275 break;
276
277 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
278 }
279 SCSI_LOW_DELAY(1);
280 }
281 if (wc == 0)
282 return ENXIO;
283
284 ct_cr_write_1(chp, wd3s_tout, seltout);
285 ct_cr_write_1(chp, wd3s_sid, SIDR_RESEL);
286 ct_cr_write_1(chp, wd3s_ctrl, CR_DEFAULT);
287 ct_cr_write_1(chp, wd3s_synch, 0);
288 if (chiprevp != NULL)
289 {
290 *chiprevp = CT_WD33C93;
291 if (regv == BSR_RESET)
292 goto out;
293
294 *chiprevp = CT_WD33C93_A;
295 ct_cr_write_1(chp, wd3s_qtag, 0xaa);
296 if (ct_cr_read_1(chp, wd3s_qtag) != 0xaa)
297 {
298 ct_cr_write_1(chp, wd3s_qtag, 0x0);
299 goto out;
300 }
301 ct_cr_write_1(chp, wd3s_qtag, 0x55);
302 if (ct_cr_read_1(chp, wd3s_qtag) != 0x55)
303 {
304 ct_cr_write_1(chp, wd3s_qtag, 0x0);
305 goto out;
306 }
307 ct_cr_write_1(chp, wd3s_qtag, 0x0);
308 *chiprevp = CT_WD33C93_B;
309 }
310
311 out:
312 (void) ct_stat_read_1(chp);
313 (void) ct_cr_read_1(chp, wd3s_stat);
314 return 0;
315 }
316
317 static struct ct_synch_data *
318 ct_make_synch_table(ct)
319 struct ct_softc *ct;
320 {
321 struct ct_synch_data *sdtp, *sdp;
322 u_int base, i, period;
323
324 sdtp = sdp = &ct->sc_default_sdt[0];
325
326 if ((ct->sc_chipclk % 5) == 0)
327 base = 1000 / (5 * 2); /* 5 MHz type */
328 else
329 base = 1000 / (4 * 2); /* 4 MHz type */
330
331 if (ct->sc_chiprev >= CT_WD33C93_B)
332 {
333 /* fast scsi */
334 for (i = 2; i < 8; i ++, sdp ++)
335 {
336 period = (base * i) / 2;
337 if (period >= 200) /* 5 MHz */
338 break;
339 sdp->cs_period = period / 4;
340 sdp->cs_syncr = (i * 0x10) | 0x80;
341 }
342 }
343
344 for (i = 2; i < 8; i ++, sdp ++)
345 {
346 period = (base * i);
347 if (period > 500) /* 2 MHz */
348 break;
349 sdp->cs_period = period / 4;
350 sdp->cs_syncr = (i * 0x10);
351 }
352
353 sdp->cs_period = 0;
354 sdp->cs_syncr = 0;
355 return sdtp;
356 }
357
358 /**************************************************
359 * Attach & Probe
360 **************************************************/
361 int
362 ctprobesubr(chp, dvcfg, hsid, chipclk, chiprevp)
363 struct ct_bus_access_handle *chp;
364 u_int dvcfg, chipclk;
365 int hsid;
366 int *chiprevp;
367 {
368
369 #if 0
370 if ((ct_stat_read_1(chp) & STR_BSY) != 0)
371 return 0;
372 #endif
373 if (cthw_chip_reset(chp, chiprevp, chipclk, hsid) != 0)
374 return 0;
375 return 1;
376 }
377
378 int
379 ctprint(aux, name)
380 void *aux;
381 const char *name;
382 {
383
384 if (name != NULL)
385 printf("%s: scsibus ", name);
386 return UNCONF;
387 }
388
389 void
390 ctattachsubr(ct)
391 struct ct_softc *ct;
392 {
393 struct scsi_low_softc *slp = &ct->sc_sclow;
394
395 ct->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */
396 slp->sl_funcs = &ct_funcs;
397 slp->sl_flags |= HW_READ_PADDING;
398 (void) scsi_low_attach(slp, 0, CT_NTARGETS, CT_NLUNS,
399 sizeof(struct ct_targ_info), 0);
400 }
401
402 /**************************************************
403 * SCSI LOW interface functions
404 **************************************************/
405 static void
406 cthw_attention(ct)
407 struct ct_softc *ct;
408 {
409 struct ct_bus_access_handle *chp = &ct->sc_ch;
410
411 ct->sc_atten = 1;
412 if ((ct_stat_read_1(chp) & (STR_BSY | STR_CIP)) != 0)
413 return;
414
415 ct_cr_write_1(chp, wd3s_cmd, WD3S_ASSERT_ATN);
416 SCSI_LOW_DELAY(10);
417 if ((ct_stat_read_1(chp) & STR_LCI) == 0)
418 ct->sc_atten = 0;
419 ct_unbusy(ct);
420 return;
421 }
422
423 static void
424 ct_attention(ct)
425 struct ct_softc *ct;
426 {
427 struct scsi_low_softc *slp = &ct->sc_sclow;
428
429 if (slp->sl_atten == 0)
430 {
431 ct_unbusy(ct);
432 scsi_low_attention(slp);
433 }
434 else if (ct->sc_atten != 0)
435 {
436 ct_unbusy(ct);
437 cthw_attention(ct);
438 }
439 }
440
441 static int
442 ct_targ_init(ct, ti, action)
443 struct ct_softc *ct;
444 struct targ_info *ti;
445 int action;
446 {
447 struct ct_targ_info *cti = (void *) ti;
448
449 if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE)
450 {
451 if (ct->sc_sdp == NULL)
452 {
453 ct->sc_sdp = ct_make_synch_table(ct);
454 }
455
456 switch (ct->sc_chiprev)
457 {
458 default:
459 ti->ti_maxsynch.offset = 5;
460 break;
461
462 case CT_WD33C93_A:
463 case CT_AM33C93_A:
464 ti->ti_maxsynch.offset = 12;
465 break;
466
467 case CT_WD33C93_B:
468 case CT_WD33C93_C:
469 ti->ti_maxsynch.offset = 12;
470 break;
471 }
472
473 ti->ti_maxsynch.period = ct->sc_sdp[0].cs_period;
474 ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
475 cti->cti_syncreg = 0;
476 }
477
478 return 0;
479 }
480
481 static int
482 ct_world_start(ct, fdone)
483 struct ct_softc *ct;
484 int fdone;
485 {
486 struct scsi_low_softc *slp = &ct->sc_sclow;
487 struct ct_bus_access_handle *chp = &ct->sc_ch;
488
489 if (ct->sc_sdp == NULL)
490 {
491 ct->sc_sdp = ct_make_synch_table(ct);
492 }
493
494 if (slp->sl_cfgflags & CFG_NOPARITY)
495 ct->sc_creg = CR_DEFAULT;
496 else
497 ct->sc_creg = CR_DEFAULT_HP;
498
499 if (ct->sc_dma & CT_DMA_DMASTART)
500 (*ct->ct_dma_xfer_stop) (ct);
501 if (ct->sc_dma & CT_DMA_PIOSTART)
502 (*ct->ct_pio_xfer_stop) (ct);
503 ct->sc_dma = 0;
504 ct->sc_atten = 0;
505
506 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
507 scsi_low_bus_reset(slp);
508 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
509
510 SOFT_INTR_REQUIRED(slp);
511 return 0;
512 }
513
514 static int
515 ct_start_selection(ct, cb)
516 struct ct_softc *ct;
517 struct slccb *cb;
518 {
519 struct scsi_low_softc *slp = &ct->sc_sclow;
520 struct ct_bus_access_handle *chp = &ct->sc_ch;
521
522 struct targ_info *ti = slp->sl_Tnexus;
523 struct lun_info *li = slp->sl_Lnexus;
524 int s, satok;
525 u_int8_t cmd;
526
527 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
528 ct->sc_atten = 0;
529 satok = 0;
530
531 if (scsi_low_is_disconnect_ok(cb) != 0)
532 {
533 if (ct->sc_chiprev >= CT_WD33C93_A)
534 satok = 1;
535 else if (cthw_cmdlevel[slp->sl_scp.scp_cmd[0]] != 0)
536 satok = 1;
537 }
538
539 if (satok != 0 &&
540 scsi_low_is_msgout_continue(ti, SCSI_LOW_MSG_IDENTIFY) == 0)
541 {
542 cmd = WD3S_SELECT_ATN_TFR;
543 ct->sc_satgo = CT_SAT_GOING;
544 }
545 else
546 {
547 cmd = WD3S_SELECT_ATN;
548 ct->sc_satgo = 0;
549 }
550
551 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) != 0)
552 return SCSI_LOW_START_FAIL;
553
554 if ((ct->sc_satgo & CT_SAT_GOING) != 0)
555 {
556 (void) scsi_low_msgout(slp, ti, SCSI_LOW_MSGOUT_INIT);
557 scsi_low_cmd(slp, ti);
558 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
559 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
560 }
561 else
562 {
563 /* anyway attention assert */
564 SCSI_LOW_ASSERT_ATN(slp);
565 }
566
567 ct_target_nexus_establish(ct, li->li_lun, slp->sl_scp.scp_direction);
568
569 s = splhigh();
570 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) == 0)
571 {
572 /* XXX:
573 * Reload a lun again here.
574 */
575 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
576 ct_cr_write_1(chp, wd3s_cmd, cmd);
577 if ((ct_stat_read_1(chp) & STR_LCI) == 0)
578 {
579 splx(s);
580 SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART);
581 return SCSI_LOW_START_OK;
582 }
583 }
584 splx(s);
585 return SCSI_LOW_START_FAIL;
586 }
587
588 static int
589 ct_msg(ct, ti, msg)
590 struct ct_softc *ct;
591 struct targ_info *ti;
592 u_int msg;
593 {
594 struct ct_bus_access_handle *chp = &ct->sc_ch;
595 struct ct_targ_info *cti = (void *) ti;
596 struct ct_synch_data *csp = ct->sc_sdp;
597 u_int offset, period;
598 int error;
599
600 if ((msg & SCSI_LOW_MSG_WIDE) != 0)
601 {
602 if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8)
603 {
604 ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
605 return EINVAL;
606 }
607 return 0;
608 }
609
610 if ((msg & SCSI_LOW_MSG_SYNCH) == 0)
611 return 0;
612
613 offset = ti->ti_maxsynch.offset;
614 period = ti->ti_maxsynch.period;
615 for ( ; csp->cs_period != 0; csp ++)
616 {
617 if (period == csp->cs_period)
618 break;
619 }
620
621 if (ti->ti_maxsynch.period != 0 && csp->cs_period == 0)
622 {
623 ti->ti_maxsynch.period = 0;
624 ti->ti_maxsynch.offset = 0;
625 cti->cti_syncreg = 0;
626 error = EINVAL;
627 }
628 else
629 {
630 cti->cti_syncreg = ((offset & 0x0f) | csp->cs_syncr);
631 error = 0;
632 }
633
634 if (ct->ct_synch_setup != 0)
635 (*ct->ct_synch_setup) (ct, ti);
636 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
637 return error;
638 }
639
640 /*************************************************
641 * <DATA PHASE>
642 *************************************************/
643 static int
644 ct_xfer(ct, data, len, direction, statp)
645 struct ct_softc *ct;
646 u_int8_t *data;
647 int len, direction;
648 u_int *statp;
649 {
650 struct ct_bus_access_handle *chp = &ct->sc_ch;
651 int wc;
652 register u_int8_t aux;
653
654 *statp = 0;
655 if (len == 1)
656 {
657 ct_cr_write_1(chp, wd3s_cmd, WD3S_SBT | WD3S_TFR_INFO);
658 }
659 else
660 {
661 cthw_set_count(chp, len);
662 ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
663 }
664
665 aux = ct_stat_read_1(chp);
666 if ((aux & STR_LCI) != 0)
667 {
668 cthw_set_count(chp, 0);
669 return len;
670 }
671
672 for (wc = 0; wc < ct->sc_tmaxcnt; wc ++)
673 {
674 /* check data ready */
675 if ((aux & (STR_BSY | STR_DBR)) == (STR_BSY | STR_DBR))
676 {
677 if (direction == SCSI_LOW_READ)
678 {
679 *data = ct_cr_read_1(chp, wd3s_data);
680 if ((aux & STR_PE) != 0)
681 *statp |= SCSI_LOW_DATA_PE;
682 }
683 else
684 {
685 ct_cr_write_1(chp, wd3s_data, *data);
686 }
687 len --;
688 if (len <= 0)
689 break;
690 data ++;
691 }
692 else
693 {
694 SCSI_LOW_DELAY(1);
695 }
696
697 /* check phase miss */
698 aux = ct_stat_read_1(chp);
699 if ((aux & STR_INT) != 0)
700 break;
701 }
702 return len;
703 }
704
705 #define CT_PADDING_BUF_SIZE 32
706
707 static void
708 ct_io_xfer(ct)
709 struct ct_softc *ct;
710 {
711 struct scsi_low_softc *slp = &ct->sc_sclow;
712 struct ct_bus_access_handle *chp = &ct->sc_ch;
713 struct sc_p *sp = &slp->sl_scp;
714 u_int stat;
715 int len;
716 u_int8_t pbuf[CT_PADDING_BUF_SIZE];
717
718 /* polling mode */
719 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg);
720
721 if (sp->scp_datalen <= 0)
722 {
723 slp->sl_error |= PDMAERR;
724
725 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
726 SCSI_LOW_BZERO(pbuf, CT_PADDING_BUF_SIZE);
727 ct_xfer(ct, pbuf, CT_PADDING_BUF_SIZE,
728 sp->scp_direction, &stat);
729 }
730 else
731 {
732 len = ct_xfer(ct, sp->scp_data, sp->scp_datalen,
733 sp->scp_direction, &stat);
734 sp->scp_data += (sp->scp_datalen - len);
735 sp->scp_datalen = len;
736 }
737 }
738
739 /**************************************************
740 * <PHASE ERROR>
741 **************************************************/
742 struct ct_err {
743 u_char *pe_msg;
744 u_int pe_err;
745 u_int pe_errmsg;
746 int pe_done;
747 };
748
749 struct ct_err ct_cmderr[] = {
750 /**/ { "illegal cmd", FATALIO, SCSI_LOW_MSG_ABORT, 1},
751 /*1*/ { "unexpected bus free", FATALIO, 0, 1},
752 /*2*/ { NULL, SELTIMEOUTIO, 0, 1},
753 /*3*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
754 /*4*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
755 /*5*/ { "unknown" , FATALIO, SCSI_LOW_MSG_ABORT, 1},
756 /*6*/ { "miss reselection (target mode)", FATALIO, SCSI_LOW_MSG_ABORT, 0},
757 /*7*/ { "wrong status byte", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
758 };
759
760 static void
761 ct_phase_error(ct, scsi_status)
762 struct ct_softc *ct;
763 u_int8_t scsi_status;
764 {
765 struct scsi_low_softc *slp = &ct->sc_sclow;
766 struct targ_info *ti = slp->sl_Tnexus;
767 struct ct_err *pep;
768 u_int msg = 0;
769
770 if ((scsi_status & BSR_CM) == BSR_CMDERR &&
771 (scsi_status & BSR_PHVALID) == 0)
772 {
773 pep = &ct_cmderr[scsi_status & BSR_PM];
774 slp->sl_error |= pep->pe_err;
775 if ((pep->pe_err & PARITYERR) != 0)
776 {
777 if (ti->ti_phase == PH_MSGIN)
778 msg = SCSI_LOW_MSG_PARITY;
779 else
780 msg = SCSI_LOW_MSG_ERROR;
781 }
782 else
783 msg = pep->pe_errmsg;
784
785 if (msg != 0)
786 scsi_low_assert_msg(slp, slp->sl_Tnexus, msg, 1);
787
788 if (pep->pe_msg != NULL)
789 {
790 printf("%s: phase error: %s",
791 slp->sl_xname, pep->pe_msg);
792 scsi_low_print(slp, slp->sl_Tnexus);
793 }
794
795 if (pep->pe_done != 0)
796 scsi_low_disconnected(slp, ti);
797 }
798 else
799 {
800 slp->sl_error |= FATALIO;
801 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD, "phase error");
802 }
803 }
804
805 /**************************************************
806 * ### SCSI PHASE SEQUENCER ###
807 **************************************************/
808 static int
809 ct_reselected(ct, scsi_status)
810 struct ct_softc *ct;
811 u_int8_t scsi_status;
812 {
813 struct scsi_low_softc *slp = &ct->sc_sclow;
814 struct ct_bus_access_handle *chp = &ct->sc_ch;
815 struct targ_info *ti;
816 u_int sid;
817 u_int8_t regv;
818
819 ct->sc_atten = 0;
820 ct->sc_satgo &= ~CT_SAT_GOING;
821 regv = ct_cr_read_1(chp, wd3s_sid);
822 if ((regv & SIDR_VALID) == 0)
823 return EJUSTRETURN;
824
825 sid = regv & SIDR_IDM;
826 if ((ti = scsi_low_reselected(slp, sid)) == NULL)
827 return EJUSTRETURN;
828
829 ct_target_nexus_establish(ct, 0, SCSI_LOW_READ);
830 if (scsi_status != BSR_AFM_RESEL)
831 return EJUSTRETURN;
832
833 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
834 regv = ct_cr_read_1(chp, wd3s_data);
835 if (scsi_low_msgin(slp, ti, (u_int) regv) == 0)
836 {
837 if (scsi_low_is_msgout_continue(ti, 0) != 0)
838 {
839 /* XXX: scsi_low_attetion */
840 scsi_low_attention(slp);
841 }
842 }
843
844 if (ct->sc_atten != 0)
845 {
846 ct_attention(ct);
847 }
848
849 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
850 return EJUSTRETURN;
851 }
852
853 static int
854 ct_target_nexus_establish(ct, lun, dir)
855 struct ct_softc *ct;
856 int lun, dir;
857 {
858 struct scsi_low_softc *slp = &ct->sc_sclow;
859 struct ct_bus_access_handle *chp = &ct->sc_ch;
860 struct targ_info *ti = slp->sl_Tnexus;
861 struct ct_targ_info *cti = (void *) ti;
862
863 if (dir == SCSI_LOW_WRITE)
864 ct_cr_write_1(chp, wd3s_did, ti->ti_id);
865 else
866 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
867 ct_cr_write_1(chp, wd3s_lun, lun);
868 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
869 ct_cr_write_1(chp, wd3s_cph, 0);
870 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
871 cthw_set_count(chp, 0);
872 return 0;
873 }
874
875 static int
876 ct_lun_nexus_establish(ct)
877 struct ct_softc *ct;
878 {
879 struct scsi_low_softc *slp = &ct->sc_sclow;
880 struct ct_bus_access_handle *chp = &ct->sc_ch;
881 struct lun_info *li = slp->sl_Lnexus;
882
883 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
884 return 0;
885 }
886
887 static int
888 ct_ccb_nexus_establish(ct)
889 struct ct_softc *ct;
890 {
891 struct scsi_low_softc *slp = &ct->sc_sclow;
892 struct ct_bus_access_handle *chp = &ct->sc_ch;
893 struct lun_info *li = slp->sl_Lnexus;
894 struct targ_info *ti = slp->sl_Tnexus;
895 struct ct_targ_info *cti = (void *) ti;
896 struct slccb *cb = slp->sl_Qnexus;
897
898 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
899
900 if ((ct->sc_satgo & CT_SAT_GOING) != 0)
901 {
902 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
903 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
904 }
905 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
906 ct_cr_write_1(chp, wd3s_did, ti->ti_id);
907 else
908 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
909 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
910 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
911 return 0;
912 }
913
914 static int
915 ct_unbusy(ct)
916 struct ct_softc *ct;
917 {
918 struct scsi_low_softc *slp = &ct->sc_sclow;
919 struct ct_bus_access_handle *chp = &ct->sc_ch;
920 int wc;
921 register u_int8_t regv;
922
923 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
924 {
925 regv = ct_stat_read_1(chp);
926 if ((regv & (STR_BSY | STR_CIP)) == 0)
927 return 0;
928 if (regv == (u_int8_t) -1)
929 return EIO;
930
931 SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
932 }
933
934 printf("%s: unbusy timeout\n", slp->sl_xname);
935 return EBUSY;
936 }
937
938 static int
939 ct_catch_intr(ct)
940 struct ct_softc *ct;
941 {
942 struct ct_bus_access_handle *chp = &ct->sc_ch;
943 int wc;
944 register u_int8_t regv;
945
946 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
947 {
948 regv = ct_stat_read_1(chp);
949 if ((regv & (STR_INT | STR_BSY | STR_CIP)) == STR_INT)
950 return 0;
951
952 SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
953 }
954 return EJUSTRETURN;
955 }
956
957 int
958 ctintr(arg)
959 void *arg;
960 {
961 struct ct_softc *ct = arg;
962 struct scsi_low_softc *slp = &ct->sc_sclow;
963 struct ct_bus_access_handle *chp = &ct->sc_ch;
964 struct targ_info *ti;
965 struct physio_proc *pp;
966 struct buf *bp;
967 u_int derror, flags;
968 int len, satgo, error;
969 u_int8_t scsi_status, regv;
970
971 again:
972 if (slp->sl_flags & HW_INACTIVE)
973 return 0;
974
975 /**************************************************
976 * Get status & bus phase
977 **************************************************/
978 if ((ct_stat_read_1(chp) & STR_INT) == 0)
979 return 0;
980
981 scsi_status = ct_cr_read_1(chp, wd3s_stat);
982 if (scsi_status == ((u_int8_t) -1))
983 return 1;
984
985 /**************************************************
986 * Check reselection, or nexus
987 **************************************************/
988 if (scsi_status == BSR_RESEL || scsi_status == BSR_AFM_RESEL)
989 {
990 if (ct_reselected(ct, scsi_status) == EJUSTRETURN)
991 return 1;
992 }
993
994 if ((ti = slp->sl_Tnexus) == NULL)
995 return 1;
996
997 /**************************************************
998 * Debug section
999 **************************************************/
1000 #ifdef CT_DEBUG
1001 if (ct_debug > 0)
1002 {
1003 scsi_low_print(slp, NULL);
1004 printf("%s: scsi_status 0x%x\n\n", slp->sl_xname,
1005 (u_int) scsi_status);
1006 #ifdef DDB
1007 if (ct_debug > 1)
1008 SCSI_LOW_DEBUGGER("ct");
1009 #endif /* DDB */
1010 }
1011 #endif /* CT_DEBUG */
1012
1013 /**************************************************
1014 * Internal scsi phase
1015 **************************************************/
1016 satgo = ct->sc_satgo;
1017 ct->sc_satgo &= ~CT_SAT_GOING;
1018
1019 switch (ti->ti_phase)
1020 {
1021 case PH_SELSTART:
1022 if ((satgo & CT_SAT_GOING) == 0)
1023 {
1024 if (scsi_status != BSR_SELECTED)
1025 {
1026 ct_phase_error(ct, scsi_status);
1027 return 1;
1028 }
1029 scsi_low_arbit_win(slp);
1030 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED);
1031 return 1;
1032 }
1033 else
1034 {
1035 scsi_low_arbit_win(slp);
1036 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); /* XXX */
1037 }
1038 break;
1039
1040 case PH_RESEL:
1041 if ((scsi_status & BSR_PHVALID) == 0 ||
1042 (scsi_status & BSR_PM) != BSR_MSGIN)
1043 {
1044 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD,
1045 "phase miss after reselect");
1046 return 1;
1047 }
1048 break;
1049
1050 default:
1051 if (slp->sl_flags & HW_PDMASTART)
1052 {
1053 slp->sl_flags &= ~HW_PDMASTART;
1054 if (ct->sc_dma & CT_DMA_DMASTART)
1055 {
1056 (*ct->ct_dma_xfer_stop) (ct);
1057 ct->sc_dma &= ~CT_DMA_DMASTART;
1058 }
1059 else if (ct->sc_dma & CT_DMA_PIOSTART)
1060 {
1061 (*ct->ct_pio_xfer_stop) (ct);
1062 ct->sc_dma &= ~CT_DMA_PIOSTART;
1063 }
1064 else
1065 {
1066 scsi_low_data_finish(slp);
1067 }
1068 }
1069 break;
1070 }
1071
1072 /**************************************************
1073 * parse scsi phase
1074 **************************************************/
1075 if (scsi_status & BSR_PHVALID)
1076 {
1077 /**************************************************
1078 * Normal SCSI phase.
1079 **************************************************/
1080 if ((scsi_status & BSR_CM) == BSR_CMDABT)
1081 {
1082 ct_phase_error(ct, scsi_status);
1083 return 1;
1084 }
1085
1086 switch (scsi_status & BSR_PM)
1087 {
1088 case BSR_DATAOUT:
1089 SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1090 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0)
1091 {
1092 ct_attention(ct);
1093 }
1094 goto common_data_phase;
1095
1096 case BSR_DATAIN:
1097 SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1098 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0)
1099 {
1100 ct_attention(ct);
1101 }
1102
1103 common_data_phase:
1104 if (slp->sl_scp.scp_datalen > 0)
1105 {
1106 slp->sl_flags |= HW_PDMASTART;
1107 if ((ct->sc_xmode & CT_XMODE_PIO) != 0)
1108 {
1109 pp = physio_proc_enter(bp);
1110 error = (*ct->ct_pio_xfer_start) (ct);
1111 physio_proc_leave(pp);
1112 if (error == 0)
1113 {
1114 ct->sc_dma |= CT_DMA_PIOSTART;
1115 return 1;
1116 }
1117 }
1118
1119 if ((ct->sc_xmode & CT_XMODE_DMA) != 0)
1120 {
1121 error = (*ct->ct_dma_xfer_start) (ct);
1122 if (error == 0)
1123 {
1124 ct->sc_dma |= CT_DMA_DMASTART;
1125 return 1;
1126 }
1127 }
1128 }
1129 else
1130 {
1131 if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
1132 {
1133 if (!(slp->sl_flags & HW_READ_PADDING))
1134 {
1135 printf("%s: read padding required\n", slp->sl_xname);
1136 return 1;
1137 }
1138 }
1139 else
1140 {
1141 if (!(slp->sl_flags & HW_WRITE_PADDING))
1142 {
1143 printf("%s: write padding required\n", slp->sl_xname);
1144 return 1;
1145 }
1146 }
1147 slp->sl_flags |= HW_PDMASTART;
1148 }
1149
1150 ct_io_xfer(ct);
1151 return 1;
1152
1153 case BSR_CMDOUT:
1154 SCSI_LOW_SETUP_PHASE(ti, PH_CMD);
1155 if (scsi_low_cmd(slp, ti) != 0)
1156 {
1157 ct_attention(ct);
1158 }
1159
1160 if (ct_xfer(ct, slp->sl_scp.scp_cmd,
1161 slp->sl_scp.scp_cmdlen,
1162 SCSI_LOW_WRITE, &derror) != 0)
1163 {
1164 printf("%s: scsi cmd xfer short\n",
1165 slp->sl_xname);
1166 }
1167 return 1;
1168
1169 case BSR_STATIN:
1170 SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
1171 if ((ct_io_control & CT_USE_CCSEQ) != 0)
1172 {
1173 if (scsi_low_is_msgout_continue(ti, 0) != 0 ||
1174 ct->sc_atten != 0)
1175 {
1176 ct_xfer(ct, ®v, 1, SCSI_LOW_READ,
1177 &derror);
1178 scsi_low_statusin(slp, ti,
1179 regv | derror);
1180 }
1181 else
1182 {
1183 ct->sc_satgo |= CT_SAT_GOING;
1184 cthw_set_count(chp, 0);
1185 cthw_phase_bypass(ct, 0x41);
1186 }
1187 }
1188 else
1189 {
1190 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror);
1191 scsi_low_statusin(slp, ti, regv | derror);
1192 }
1193 return 1;
1194
1195 case BSR_UNSPINFO0:
1196 case BSR_UNSPINFO1:
1197 printf("%s: illegal bus phase (0x%x)\n", slp->sl_xname,
1198 (u_int) scsi_status);
1199 scsi_low_print(slp, ti);
1200 return 1;
1201
1202 case BSR_MSGOUT:
1203 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT);
1204 flags = SCSI_LOW_MSGOUT_UNIFY;
1205 if (ti->ti_ophase != ti->ti_phase)
1206 flags |= SCSI_LOW_MSGOUT_INIT;
1207 len = scsi_low_msgout(slp, ti, flags);
1208
1209 if (len > 1 && slp->sl_atten == 0)
1210 {
1211 ct_attention(ct);
1212 }
1213
1214 if (ct_xfer(ct, ti->ti_msgoutstr, len,
1215 SCSI_LOW_WRITE, &derror) != 0)
1216 {
1217 printf("%s: scsi msgout xfer short\n",
1218 slp->sl_xname);
1219 }
1220 SCSI_LOW_DEASSERT_ATN(slp);
1221 ct->sc_atten = 0;
1222 return 1;
1223
1224 case BSR_MSGIN:/* msg in */
1225 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1226
1227 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror);
1228 if (scsi_low_msgin(slp, ti, regv | derror) == 0)
1229 {
1230 if (scsi_low_is_msgout_continue(ti, 0) != 0)
1231 {
1232 /* XXX: scsi_low_attetion */
1233 scsi_low_attention(slp);
1234 }
1235 }
1236
1237 if ((ct_io_control & CT_FAST_INTR) != 0)
1238 {
1239 if (ct_catch_intr(ct) == 0)
1240 goto again;
1241 }
1242 return 1;
1243 }
1244 }
1245 else
1246 {
1247 /**************************************************
1248 * Special SCSI phase
1249 **************************************************/
1250 switch (scsi_status)
1251 {
1252 case BSR_SATSDP: /* SAT with save data pointer */
1253 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1254 ct->sc_satgo |= CT_SAT_GOING;
1255 scsi_low_msgin(slp, ti, MSG_SAVESP);
1256 cthw_phase_bypass(ct, 0x41);
1257 return 1;
1258
1259 case BSR_SATFIN: /* SAT COMPLETE */
1260 /*
1261 * emulate statusin => msgin
1262 */
1263 SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
1264 scsi_low_statusin(slp, ti, ct_cr_read_1(chp, wd3s_lun));
1265
1266 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1267 scsi_low_msgin(slp, ti, MSG_COMP);
1268
1269 scsi_low_disconnected(slp, ti);
1270 return 1;
1271
1272 case BSR_ACKREQ: /* negate ACK */
1273 if (ct->sc_atten != 0)
1274 {
1275 ct_attention(ct);
1276 }
1277
1278 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
1279 if ((ct_io_control & CT_FAST_INTR) != 0)
1280 {
1281 /* XXX:
1282 * Should clear a pending interrupt and
1283 * sync with a next interrupt!
1284 */
1285 ct_catch_intr(ct);
1286 }
1287 return 1;
1288
1289 case BSR_DISC: /* disconnect */
1290 if (slp->sl_msgphase == MSGPH_NULL &&
1291 (satgo & CT_SAT_GOING) != 0)
1292 {
1293 /*
1294 * emulate disconnect msg
1295 */
1296 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1297 scsi_low_msgin(slp, ti, MSG_DISCON);
1298 }
1299 scsi_low_disconnected(slp, ti);
1300 return 1;
1301
1302 default:
1303 break;
1304 }
1305 }
1306
1307 ct_phase_error(ct, scsi_status);
1308 return 1;
1309 }
Cache object: eff6bb5623a56264a83cef79b16780c7
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