Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ct/ct_isa.c
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1 /* $FreeBSD: releng/5.0/sys/dev/ct/ct_isa.c 103708 2002-09-20 18:15:40Z phk $ */ 2 /* $NecBSD: ct_isa.c,v 1.6 1999/07/26 06:32:01 honda Exp $ */ 3 /* $NetBSD$ */ 4 5 /* 6 * [NetBSD for NEC PC-98 series] 7 * Copyright (c) 1995, 1996, 1997, 1998 8 * NetBSD/pc98 porting staff. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #define SCSIBUS_RESCAN 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/bio.h> 40 #include <sys/buf.h> 41 #include <sys/queue.h> 42 #include <sys/malloc.h> 43 #include <sys/device_port.h> 44 #include <sys/errno.h> 45 46 #include <vm/vm.h> 47 48 #ifdef __NetBSD__ 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include <dev/scsipi/scsi_all.h> 53 #include <dev/scsipi/scsipi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 #include <dev/scsipi/scsi_disk.h> 56 57 #include <dev/isa/isareg.h> 58 #include <dev/isa/isavar.h> 59 #include <dev/isa/isadmavar.h> 60 61 #include <machine/dvcfg.h> 62 #include <machine/physio_proc.h> 63 #include <machine/syspmgr.h> 64 65 #include <i386/Cbus/dev/scsi_low.h> 66 67 #include <dev/ic/wd33c93reg.h> 68 #include <i386/Cbus/dev/ct/ctvar.h> 69 #include <i386/Cbus/dev/ct/bshwvar.h> 70 #endif /* __NetBSD__ */ 71 72 #ifdef __FreeBSD__ 73 #include <machine/bus.h> 74 #include <machine/resource.h> 75 #include <sys/bus.h> 76 #include <sys/rman.h> 77 #include <machine/md_var.h> 78 79 #include <pc98/pc98/pc98.h> 80 #include <isa/isavar.h> 81 82 #include <machine/dvcfg.h> 83 #include <machine/physio_proc.h> 84 85 #include <cam/scsi/scsi_low.h> 86 87 #include <dev/ic/wd33c93reg.h> 88 #include <dev/ct/ctvar.h> 89 #include <dev/ct/bshwvar.h> 90 #endif /* __FreeBSD__ */ 91 92 #define BSHW_IOSZ 0x08 93 #define BSHW_IOBASE 0xcc0 94 #define BSHW_MEMSZ (PAGE_SIZE * 2) 95 96 static int ct_isa_match(device_t); 97 static int ct_isa_attach(device_t); 98 static int ct_space_map(device_t, struct bshw *, 99 struct resource **, struct resource **); 100 static void ct_space_unmap(device_t, struct ct_softc *); 101 static struct bshw *ct_find_hw(device_t); 102 static void ct_dmamap(void *, bus_dma_segment_t *, int, int); 103 static void ct_isa_bus_access_weight(struct ct_bus_access_handle *); 104 static void ct_isa_dmasync_before(struct ct_softc *); 105 static void ct_isa_dmasync_after(struct ct_softc *); 106 107 struct ct_isa_softc { 108 struct ct_softc sc_ct; 109 struct bshw_softc sc_bshw; 110 }; 111 112 static struct isa_pnp_id ct_pnp_ids[] = { 113 { 0x0100e7b1, "Logitec LHA-301" }, 114 { 0x110154dc, "I-O DATA SC-98III" }, 115 { 0x4120acb4, "MELCO IFC-NN" }, 116 { 0, NULL } 117 }; 118 119 static device_method_t ct_isa_methods[] = { 120 /* Device interface */ 121 DEVMETHOD(device_probe, ct_isa_match), 122 DEVMETHOD(device_attach, ct_isa_attach), 123 { 0, 0 } 124 }; 125 126 static driver_t ct_isa_driver = { 127 "ct", ct_isa_methods, sizeof(struct ct_isa_softc), 128 }; 129 130 static devclass_t ct_devclass; 131 132 DRIVER_MODULE(ct, isa, ct_isa_driver, ct_devclass, 0, 0); 133 134 static int 135 ct_isa_match(device_t dev) 136 { 137 struct bshw *hw; 138 struct resource *port_res, *mem_res; 139 struct ct_bus_access_handle ch; 140 int rv; 141 142 if (ISA_PNP_PROBE(device_get_parent(dev), dev, ct_pnp_ids) == ENXIO) 143 return ENXIO; 144 145 if (isa_get_port(dev) == -1) 146 bus_set_resource(dev, SYS_RES_IOPORT, 0, 147 BSHW_IOBASE, BSHW_IOSZ); 148 149 if ((hw = ct_find_hw(dev)) == NULL) 150 return ENXIO; 151 if (ct_space_map(dev, hw, &port_res, &mem_res) != 0) 152 return ENXIO; 153 154 bzero(&ch, sizeof(ch)); 155 ch.ch_iot = rman_get_bustag(port_res); 156 ch.ch_ioh = rman_get_bushandle(port_res), 157 ch.ch_bus_weight = ct_isa_bus_access_weight; 158 159 rv = ctprobesubr(&ch, 0, BSHW_DEFAULT_HOSTID, 160 BSHW_DEFAULT_CHIPCLK, NULL); 161 if (rv != 0) 162 { 163 struct bshw_softc bshw_tab; 164 struct bshw_softc *bs = &bshw_tab; 165 166 memset(bs, 0, sizeof(*bs)); 167 bshw_read_settings(&ch, bs); 168 bus_set_resource(dev, SYS_RES_IRQ, 0, bs->sc_irq, 1); 169 bus_set_resource(dev, SYS_RES_DRQ, 0, bs->sc_drq, 1); 170 } 171 172 bus_release_resource(dev, SYS_RES_IOPORT, 0, port_res); 173 if (mem_res != NULL) 174 bus_release_resource(dev, SYS_RES_MEMORY, 0, mem_res); 175 176 if (rv != 0) 177 return 0; 178 return ENXIO; 179 } 180 181 static int 182 ct_isa_attach(device_t dev) 183 { 184 struct ct_isa_softc *pct = device_get_softc(dev); 185 struct ct_softc *ct = &pct->sc_ct; 186 struct ct_bus_access_handle *chp = &ct->sc_ch; 187 struct scsi_low_softc *slp = &ct->sc_sclow; 188 struct bshw_softc *bs = &pct->sc_bshw; 189 struct bshw *hw; 190 int irq_rid, drq_rid, chiprev; 191 u_int8_t *vaddr; 192 bus_addr_t addr; 193 intrmask_t s; 194 195 hw = ct_find_hw(dev); 196 if (ct_space_map(dev, hw, &ct->port_res, &ct->mem_res) != 0) { 197 device_printf(dev, "bus io mem map failed\n"); 198 return ENXIO; 199 } 200 201 bzero(chp, sizeof(*chp)); 202 chp->ch_iot = rman_get_bustag(ct->port_res); 203 chp->ch_ioh = rman_get_bushandle(ct->port_res); 204 if (ct->mem_res) { 205 chp->ch_memt = rman_get_bustag(ct->mem_res); 206 chp->ch_memh = rman_get_bushandle(ct->mem_res); 207 } 208 chp->ch_bus_weight = ct_isa_bus_access_weight; 209 210 irq_rid = 0; 211 ct->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, 0, ~0, 212 1, RF_ACTIVE); 213 drq_rid = 0; 214 ct->drq_res = bus_alloc_resource(dev, SYS_RES_DRQ, &drq_rid, 0, ~0, 215 1, RF_ACTIVE); 216 if (ct->irq_res == NULL || ct->drq_res == NULL) { 217 ct_space_unmap(dev, ct); 218 return ENXIO; 219 } 220 221 if (ctprobesubr(chp, 0, BSHW_DEFAULT_HOSTID, 222 BSHW_DEFAULT_CHIPCLK, &chiprev) == 0) 223 { 224 device_printf(dev, "hardware missing\n"); 225 ct_space_unmap(dev, ct); 226 return ENXIO; 227 } 228 229 /* setup DMA map */ 230 if (bus_dma_tag_create(NULL, 1, 0, 231 BUS_SPACE_MAXADDR_24BIT, BUS_SPACE_MAXADDR, 232 NULL, NULL, MAXBSIZE, 1, 233 BUS_SPACE_MAXSIZE_32BIT, 234 BUS_DMA_ALLOCNOW, &ct->sc_dmat) != 0) { 235 device_printf(dev, "can't set up ISA DMA map\n"); 236 ct_space_unmap(dev, ct); 237 return ENXIO; 238 } 239 240 if (bus_dmamem_alloc(ct->sc_dmat, (void **)&vaddr, BUS_DMA_NOWAIT, 241 &ct->sc_dmamapt) != 0) { 242 device_printf(dev, "can't set up ISA DMA map\n"); 243 ct_space_unmap(dev, ct); 244 return ENXIO; 245 } 246 247 bus_dmamap_load(ct->sc_dmat, ct->sc_dmamapt, vaddr, MAXBSIZE, 248 ct_dmamap, &addr, 0); 249 250 /* setup machdep softc */ 251 bs->sc_hw = hw; 252 bs->sc_io_control = 0; 253 bs->sc_bounce_phys = (u_int8_t *)addr; 254 bs->sc_bounce_addr = vaddr; 255 bs->sc_bounce_size = MAXBSIZE; 256 bs->sc_minphys = (1 << 24); 257 bs->sc_dmasync_before = ct_isa_dmasync_before; 258 bs->sc_dmasync_after = ct_isa_dmasync_after; 259 bshw_read_settings(chp, bs); 260 261 /* setup ct driver softc */ 262 ct->ct_hw = bs; 263 ct->ct_dma_xfer_start = bshw_dma_xfer_start; 264 ct->ct_pio_xfer_start = bshw_smit_xfer_start; 265 ct->ct_dma_xfer_stop = bshw_dma_xfer_stop; 266 ct->ct_pio_xfer_stop = bshw_smit_xfer_stop; 267 ct->ct_bus_reset = bshw_bus_reset; 268 ct->ct_synch_setup = bshw_synch_setup; 269 270 ct->sc_xmode = CT_XMODE_DMA; 271 if (chp->ch_memh != NULL) 272 ct->sc_xmode |= CT_XMODE_PIO; 273 274 ct->sc_chiprev = chiprev; 275 switch (chiprev) 276 { 277 case CT_WD33C93: 278 /* s = "WD33C93"; */ 279 ct->sc_chipclk = 8; 280 break; 281 case CT_WD33C93_A: 282 if (DVCFG_MAJOR(device_get_flags(dev)) > 0) 283 { 284 /* s = "AM33C93_A"; */ 285 ct->sc_chipclk = 20; 286 ct->sc_chiprev = CT_AM33C93_A; 287 } 288 else 289 { 290 /* s = "WD33C93_A"; */ 291 ct->sc_chipclk = 10; 292 } 293 break; 294 295 case CT_AM33C93_A: 296 /* s = "AM33C93_A"; */ 297 ct->sc_chipclk = 20; 298 break; 299 300 default: 301 case CT_WD33C93_B: 302 /* s = "WD33C93_B"; */ 303 ct->sc_chipclk = 20; 304 break; 305 } 306 #if 0 307 printf("%s: chiprev %s chipclk %d Mhz\n", 308 slp->sl_dev.dv_xname, s, ct->sc_chipclk); 309 #endif 310 311 slp->sl_dev = dev; 312 slp->sl_hostid = bs->sc_hostid; 313 slp->sl_irq = isa_get_irq(dev); 314 slp->sl_cfgflags = device_get_flags(dev); 315 316 s = splcam(); 317 ctattachsubr(ct); 318 splx(s); 319 320 if (bus_setup_intr(dev, ct->irq_res, INTR_TYPE_CAM, 321 (driver_intr_t *)ctintr, ct, &ct->sc_ih)) { 322 ct_space_unmap(dev, ct); 323 return ENXIO; 324 } 325 326 return 0; 327 } 328 329 static struct bshw * 330 ct_find_hw(device_t dev) 331 { 332 return DVCFG_HW(&bshw_hwsel, DVCFG_MAJOR(device_get_flags(dev))); 333 } 334 335 static int 336 ct_space_map(device_t dev, struct bshw *hw, 337 struct resource **iohp, struct resource **memhp) 338 { 339 int port_rid, mem_rid; 340 341 *memhp = NULL; 342 343 port_rid = 0; 344 *iohp = bus_alloc_resource(dev, SYS_RES_IOPORT, &port_rid, 0, ~0, 345 BSHW_IOSZ, RF_ACTIVE); 346 if (*iohp == NULL) 347 return ENXIO; 348 349 if ((hw->hw_flags & BSHW_SMFIFO) == 0 || isa_get_maddr(dev) == -1) 350 return 0; 351 352 mem_rid = 0; 353 *memhp = bus_alloc_resource(dev, SYS_RES_MEMORY, &mem_rid, 0, ~0, 354 BSHW_MEMSZ, RF_ACTIVE); 355 if (*memhp == NULL) { 356 bus_release_resource(dev, SYS_RES_IOPORT, port_rid, *iohp); 357 return ENXIO; 358 } 359 360 return 0; 361 } 362 363 static void 364 ct_space_unmap(device_t dev, struct ct_softc *ct) 365 { 366 if (ct->port_res != NULL) 367 bus_release_resource(dev, SYS_RES_IOPORT, 0, ct->port_res); 368 if (ct->mem_res != NULL) 369 bus_release_resource(dev, SYS_RES_MEMORY, 0, ct->mem_res); 370 if (ct->irq_res != NULL) 371 bus_release_resource(dev, SYS_RES_IRQ, 0, ct->irq_res); 372 if (ct->drq_res != NULL) 373 bus_release_resource(dev, SYS_RES_DRQ, 0, ct->drq_res); 374 } 375 376 static void 377 ct_dmamap(void *arg, bus_dma_segment_t *seg, int nseg, int error) 378 { 379 bus_addr_t *addr = (bus_addr_t *)arg; 380 381 *addr = seg->ds_addr; 382 } 383 384 static void 385 ct_isa_bus_access_weight(chp) 386 struct ct_bus_access_handle *chp; 387 { 388 389 outb(0x5f, 0); 390 } 391 392 static void 393 ct_isa_dmasync_before(ct) 394 struct ct_softc *ct; 395 { 396 397 if (need_pre_dma_flush) 398 wbinvd(); 399 } 400 401 static void 402 ct_isa_dmasync_after(ct) 403 struct ct_softc *ct; 404 { 405 406 if (need_post_dma_flush) 407 invd(); 408 }
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