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sys/dev/ctau/ctau.c
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1 /*- 2 * Low-level subroutines for Cronyx-Tau adapter. 3 * 4 * Copyright (C) 1994-2001 Cronyx Engineering. 5 * Author: Serge Vakulenko, <vak@cronyx.ru> 6 * 7 * Copyright (C) 2003 Cronyx Engineering. 8 * Author: Roman Kurakin, <rik@cronyx.ru> 9 * 10 * This software is distributed with NO WARRANTIES, not even the implied 11 * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 12 * 13 * Authors grant any other persons or organisations permission to use 14 * or modify this software as long as this message is kept with the software, 15 * all derivative works or modified versions. 16 * 17 * Cronyx Id: ctau.c,v 1.1.2.4 2003/12/11 17:33:43 rik Exp $ 18 */ 19 #include <sys/cdefs.h> 20 __FBSDID("$FreeBSD$"); 21 22 #include <dev/cx/machdep.h> 23 #include <dev/ctau/ctddk.h> 24 #include <dev/ctau/ctaureg.h> 25 #include <dev/ctau/hdc64570.h> 26 #include <dev/ctau/ds2153.h> 27 #include <dev/ctau/am8530.h> 28 #include <dev/ctau/lxt318.h> 29 #include <dev/cx/cronyxfw.h> 30 31 #define DMA_MASK 0xd4 /* DMA mask register */ 32 #define DMA_MASK_CLEAR 0x04 /* DMA clear mask */ 33 #define DMA_MODE 0xd6 /* DMA mode register */ 34 #define DMA_MODE_MASTER 0xc0 /* DMA master mode */ 35 36 #define BYTE *(unsigned char*)& 37 38 static unsigned char irqmask [] = { 39 BCR0_IRQ_DIS, BCR0_IRQ_DIS, BCR0_IRQ_DIS, BCR0_IRQ_3, 40 BCR0_IRQ_DIS, BCR0_IRQ_5, BCR0_IRQ_DIS, BCR0_IRQ_7, 41 BCR0_IRQ_DIS, BCR0_IRQ_DIS, BCR0_IRQ_10, BCR0_IRQ_11, 42 BCR0_IRQ_12, BCR0_IRQ_DIS, BCR0_IRQ_DIS, BCR0_IRQ_15, 43 }; 44 45 static unsigned char dmamask [] = { 46 BCR0_DMA_DIS, BCR0_DMA_DIS, BCR0_DMA_DIS, BCR0_DMA_DIS, 47 BCR0_DMA_DIS, BCR0_DMA_5, BCR0_DMA_6, BCR0_DMA_7, 48 }; 49 50 static short porttab [] = { /* standard base port set */ 51 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 52 0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0, 0 53 }; 54 55 static short irqtab [] = { 3, 5, 7, 10, 11, 12, 15, 0 }; 56 static short dmatab [] = { 5, 6, 7, 0 }; 57 58 static int valid (short value, short *list) 59 { 60 while (*list) 61 if (value == *list++) 62 return 1; 63 return 0; 64 } 65 66 long ct_baud = 256000; /* default baud rate */ 67 unsigned char ct_chan_mode = M_HDLC; /* default mode */ 68 69 static void ct_init_chan (ct_board_t *b, int num); 70 static void ct_enable_loop (ct_chan_t *c); 71 static void ct_disable_loop (ct_chan_t *c); 72 73 int ct_download (port_t port, const unsigned char *firmware, 74 long bits, const cr_dat_tst_t *tst) 75 { 76 unsigned char cr1, sr2; 77 long i, n, maxn = (bits + 7) >> 3; 78 int v, b; 79 80 inb (BSR3(port)); 81 for (i=n=0; n<maxn; ++n) { 82 v = ((firmware[n] ^ ' ') << 1) | ((firmware[n] >> 7) & 1); 83 for (b=0; b<7; b+=2, i+=2) { 84 if (i >= bits) 85 break; 86 cr1 = 0; 87 if (v >> b & 1) 88 cr1 |= BCR1_TMS; 89 if (v >> b & 2) 90 cr1 |= BCR1_TDI; 91 outb (BCR1(port), cr1); 92 sr2 = inb (BSR2(port)); 93 outb (BCR0(port), BCR0_TCK); 94 outb (BCR0(port), 0); 95 if (i >= tst->end) 96 ++tst; 97 if (i >= tst->start && (sr2 & BSR2_LERR)) 98 return (0); 99 } 100 } 101 return (1); 102 } 103 104 /* 105 * Firmware unpack algorithm. 106 */ 107 typedef struct { 108 const unsigned char *ptr; 109 unsigned char byte; 110 unsigned char count; 111 } unpack_t; 112 113 static unsigned short unpack_init (unpack_t *t, const unsigned char *ptr) 114 { 115 unsigned short len; 116 117 len = *ptr++; 118 len |= *ptr++ << 8; 119 t->ptr = ptr; 120 t->byte = 0; 121 t->count = 0; 122 return len; 123 } 124 125 static unsigned char unpack_getchar (unpack_t *t) 126 { 127 if (t->count > 0) { 128 --t->count; 129 return t->byte; 130 } 131 t->byte = *t->ptr++; 132 if (t->byte == 0) 133 t->count = *t->ptr++; 134 return t->byte; 135 } 136 137 /* 138 * Firmware download signals. 139 */ 140 #define nstatus(b) (inb(BSR3(b)) & BSR3_NSTATUS) 141 142 #define confdone(b) (inb(BSR3(b)) & BSR3_CONF_DN) 143 144 #define nconfig_set(b) outb (bcr1_port, (bcr1 &= ~BCR1_NCONFIGI)) 145 #define nconfig_clr(b) outb (bcr1_port, (bcr1 |= BCR1_NCONFIGI)) 146 147 #define dclk_tick(b) outb (BCR3(b), 0) 148 149 #define putbit(b,bit) { if (bit) bcr1 |= BCR1_1KDAT; \ 150 else bcr1 &= ~BCR1_1KDAT; \ 151 outb (bcr1_port, bcr1); \ 152 dclk_tick (b); } 153 154 #define CTAU_DEBUG(x) /*trace_str x*/ 155 156 int ct_download2 (port_t port, const unsigned char *fwaddr) 157 { 158 unsigned short bytes; 159 unsigned char bcr1, val; 160 port_t bcr1_port; 161 unpack_t t; 162 163 /* 164 * Set NCONFIG and wait until NSTATUS is set. 165 */ 166 bcr1_port = BCR1(port); 167 bcr1 = 0; 168 nconfig_set(port); 169 for (val=0; val<255; ++val) 170 if (nstatus(port)) 171 break; 172 173 /* 174 * Clear NCONFIG, wait 2 usec and check that NSTATUS is cleared. 175 */ 176 nconfig_clr(port); 177 for (val=0; val<2*3; ++val) 178 nconfig_clr(port); 179 if (nstatus(port)) { 180 CTAU_DEBUG (("Bad nstatus, downloading aborted (bsr3=0x%x).\n", inb(BSR3(port)))); 181 nconfig_set(port); 182 return 0; 183 } 184 185 /* 186 * Set NCONFIG and wait 5 usec. 187 */ 188 nconfig_set(port); 189 for (val=0; val<5*3; ++val) /* Delay 5 msec. */ 190 nconfig_set(port); 191 192 /* 193 * С адреса `fwaddr' в памяти должны лежать упакованные данные 194 * для загрузки firmware. Значение должно быть согласовано с параметром 195 * вызова утилиты `megaprog' в скрипте загрузки (и Makefile). 196 */ 197 bytes = unpack_init (&t, fwaddr); 198 for (; bytes>0; --bytes) { 199 val = unpack_getchar (&t); 200 201 if (nstatus(port) == 0) { 202 CTAU_DEBUG (("Bad nstatus, %d bytes remaining.\n", bytes)); 203 goto failed; 204 } 205 206 if (confdone(port)) { 207 /* Ten extra clocks. Hope 50 is enough. */ 208 for (val=0; val<50; ++val) 209 dclk_tick (port); 210 211 if (nstatus(port) == 0) { 212 CTAU_DEBUG (("Bad nstatus after confdone, %d bytes remaining (%d).\n", 213 bytes, t.ptr - fwaddr)); 214 goto failed; 215 } 216 217 /* Succeeded. */ 218 /*CTAU_DEBUG (("Download succeeded.\n"));*/ 219 return 1; 220 } 221 222 putbit (port, val & 0x01); 223 putbit (port, val & 0x02); 224 putbit (port, val & 0x04); 225 putbit (port, val & 0x08); 226 putbit (port, val & 0x10); 227 putbit (port, val & 0x20); 228 putbit (port, val & 0x40); 229 putbit (port, val & 0x80); 230 231 /* if ((bytes & 1023) == 0) putch ('.'); */ 232 } 233 234 CTAU_DEBUG (("Bad confdone.\n")); 235 failed: 236 CTAU_DEBUG (("Downloading aborted.\n")); 237 return 0; 238 } 239 240 /* 241 * Detect Tau2 adapter. 242 */ 243 static int ct_probe2_board (port_t port) 244 { 245 unsigned char sr3, osr3; 246 int i; 247 248 if (! valid (port, porttab)) 249 return 0; 250 251 osr3 = inb (BSR3(port)); 252 if ((osr3 & (BSR3_IB | BSR3_IB_NEG)) != BSR3_IB && 253 (osr3 & (BSR3_IB | BSR3_IB_NEG)) != BSR3_IB_NEG) 254 return (0); 255 for (i=0; i<100; ++i) { 256 /* Do it twice */ 257 sr3 = inb (BSR3(port)); 258 sr3 = inb (BSR3(port)); 259 if (((sr3 ^ osr3) & (BSR3_IB | BSR3_IB_NEG | BSR3_ZERO)) != 260 (BSR3_IB | BSR3_IB_NEG)) 261 return (0); 262 osr3 = sr3; 263 } 264 /* Reset the controller. */ 265 outb (BCR0(port), 0); 266 return 1; 267 } 268 269 /* 270 * Check if the Tau board is present at the given base port. 271 * Read board status register 1 and check identification bits 272 * which should invert every next read. 273 * The "zero" bit should remain stable. 274 */ 275 int ct_probe_board (port_t port, int irq, int dma) 276 { 277 unsigned char sr3, osr3; 278 int i; 279 280 if (! valid (port, porttab)) 281 return 0; 282 283 if ((irq > 0) && (!valid (irq, irqtab))) 284 return 0; 285 286 if ((dma > 0) && (!valid (dma, dmatab))) 287 return 0; 288 289 osr3 = inb (BSR3(port)); 290 if ((osr3 & (BSR3_IB | BSR3_IB_NEG)) != BSR3_IB && 291 (osr3 & (BSR3_IB | BSR3_IB_NEG)) != BSR3_IB_NEG) 292 return (0); 293 for (i=0; i<100; ++i) { 294 sr3 = inb (BSR3(port)); 295 if (((sr3 ^ osr3) & (BSR3_IB | BSR3_IB_NEG | BSR3_ZERO)) != 296 (BSR3_IB | BSR3_IB_NEG)) 297 return ct_probe2_board (port); 298 osr3 = sr3; 299 } 300 /* Reset the controller. */ 301 outb (BCR0(port), 0); 302 return (1); 303 } 304 305 /* 306 * Check that the irq is functional. 307 * irq>0 - activate the interrupt from the adapter (irq=on) 308 * irq<0 - deactivate the interrupt (irq=off) 309 * irq==0 - free the interrupt line (irq=tri-state) 310 * Return the interrupt mask _before_ activating irq. 311 */ 312 int ct_probe_irq (ct_board_t *b, int irq) 313 { 314 int mask; 315 316 outb (0x20, 0x0a); 317 mask = inb (0x20); 318 outb (0xa0, 0x0a); 319 mask |= inb (0xa0) << 8; 320 321 if (irq > 0) { 322 outb (BCR0(b->port), BCR0_HDRUN | irqmask[irq]); 323 outb (R(b->port,HD_TEPR_0R), 0); 324 outw (R(b->port,HD_TCONR_0R), 1); 325 outw (R(b->port,HD_TCNT_0R), 0); 326 outb (R(b->port,HD_TCSR_0R), TCSR_ENABLE | TCSR_INTR); 327 outb (IER2(b->port), IER2_RX_TME_0); 328 } else if (irq < 0) { 329 outb (BCR0(b->port), BCR0_HDRUN | irqmask[-irq]); 330 outb (IER0(b->port), 0); 331 outb (IER1(b->port), 0); 332 outb (IER2(b->port), 0); 333 outb (R(b->port,HD_TCSR_0R), 0); 334 cte_out (E1CS0 (b->port), DS_IMR2, 0); 335 cte_out (E1CS1 (b->port), DS_IMR2, 0); 336 if (-irq > 7) { 337 outb (0xa0, 0x60 | ((-irq) & 7)); 338 outb (0x20, 0x62); 339 } else 340 outb (0x20, 0x60 | (-irq)); 341 } else { 342 outb (BCR0(b->port), b->bcr0); 343 cte_out (E1CS0 (b->port), DS_IMR2, SR2_SEC); 344 cte_out (E1CS1 (b->port), DS_IMR2, SR2_SEC); 345 } 346 347 return mask; 348 } 349 350 void ct_init_board (ct_board_t *b, int num, port_t port, int irq, int dma, 351 int type, long osc) 352 { 353 int i; 354 355 /* Initialize board structure. */ 356 b->type = type; 357 b->port = port; 358 b->num = num; 359 b->irq = irq; 360 b->dma = dma; 361 b->osc = osc; 362 363 /* Get the board type. */ 364 if (b->type == B_TAU) strcpy (b->name, "Tau"); 365 else if (b->type == B_TAU_E1) strcpy (b->name, "Tau/E1"); 366 else if (b->type == B_TAU_E1C) strcpy (b->name, "Tau/E1c"); 367 else if (b->type == B_TAU_E1D) strcpy (b->name, "Tau/E1d"); 368 else if (b->type == B_TAU_G703) strcpy (b->name, "Tau/G.703"); 369 else if (b->type == B_TAU_G703C) strcpy (b->name, "Tau/G.703c"); 370 else if (b->type == B_TAU2) strcpy (b->name, "Tau2"); 371 else if (b->type == B_TAU2_E1) strcpy (b->name, "Tau2/E1"); 372 else if (b->type == B_TAU2_E1D) strcpy (b->name, "Tau2/E1d"); 373 else if (b->type == B_TAU2_G703) strcpy (b->name, "Tau2/G.703"); 374 else strcpy (b->name, "Tau/???"); 375 376 /* Set DMA and IRQ. */ 377 b->bcr0 = BCR0_HDRUN | dmamask[b->dma] | irqmask[b->irq]; 378 379 /* Clear DTR[0..1]. */ 380 b->bcr1 = 0; 381 b->e1cfg = 0; 382 383 /* Initialize channel structures. */ 384 for (i=0; i<NCHAN; ++i) 385 ct_init_chan (b, i); 386 ct_reinit_board (b); 387 } 388 389 /* 390 * Initialize the board structure. 391 */ 392 void ct_init (ct_board_t *b, int num, port_t port, int irq, int dma, 393 const unsigned char *firmware, long bits, const cr_dat_tst_t *tst, 394 const unsigned char *firmware2) 395 { 396 static long tlen = 182; 397 static cr_dat_tst_t tvec [] = {{ 114, 178 }, { 182, 182 }}; 398 static cr_dat_tst_t tvec2 [] = {{ 50, 178 }, { 182, 182 }}; 399 static unsigned char tau [] = { 155,153,113,48,64,236, 400 48,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,183,}; 401 static unsigned char e1 [] = { 155,153,113,48,64,236, 402 112,37,49,37,33,116,101,100,112,37,49,37,33,116,101,100,230,}; 403 static unsigned char e1_2 [] = { 155,153,113,48,64,236, 404 112,37,49,37,33,116,101,100,96,97,53,49,49,96,97,100,230,}; 405 static unsigned char e1_3 [] = { 155,153,113,48,64,236, 406 96,97,53,49,49,96,97,100,96,97,53,49,49,96,97,100,230,}; 407 static unsigned char e1_4 [] = { 155,153,113,48,64,236, 408 96,97,53,49,49,96,97,100,112,37,49,37,33,116,101,100,230,}; 409 static unsigned char g703 [] = { 155,153,113,48,64,236, 410 112,37,49,37,33,116,101,32,117,37,49,37,33,116,101,100,230,}; 411 static unsigned char g703_2 [] = { 155,153,113,48,64,236, 412 112,37,49,37,33,116,101,32,101,97,53,49,49,96,97,100,230,}; 413 static unsigned char g703_3 [] = { 155,153,113,48,64,236, 414 96,97,53,49,49,96,97,32,101,97,53,49,49,96,97,100,230,}; 415 static unsigned char g703_4 [] = { 155,153,113,48,64,236, 416 96,97,53,49,49,96,97,32,117,37,49,37,33,116,101,100,230,}; 417 418 int type = B_TAU; 419 long osc = (inb (BSR3(port)) & BSR3_ZERO) ? 8192000 : 10000000; 420 421 /* Get the board type. */ 422 if (ct_probe2_board (port) && ct_download2 (port, firmware2)) { 423 /* Tau2, 1k30-based model */ 424 unsigned char sr0 = inb (BSR0(port)); 425 if (! (sr0 & BSR0_T703)) 426 type = B_TAU2_G703; 427 else if (sr0 & BSR0_TE1) 428 type = B_TAU2; 429 else if (inb(E1SR(port)) & E1SR_REV) 430 type = B_TAU2_E1D; 431 else 432 type = B_TAU2_E1; 433 } else if (ct_download (port, tau, tlen, tvec)) { 434 if (! ct_download (port, firmware, bits, tst)) 435 type = B_TAU; 436 else { 437 unsigned char sr0 = inb (BSR0(port)); 438 if (! (sr0 & BSR0_T703)) 439 type = B_TAU_G703C; 440 else if (sr0 & BSR0_TE1) 441 type = B_TAU; 442 else if (inb(E1SR(port)) & E1SR_REV) 443 type = B_TAU_E1D; 444 else 445 type = B_TAU_E1C; 446 } 447 } else if (ct_download (port, e1, tlen, tvec2) || 448 ct_download (port, e1_2, tlen, tvec2) || 449 ct_download (port, e1_3, tlen, tvec2) || 450 ct_download (port, e1_4, tlen, tvec2)) 451 type = B_TAU_E1; 452 else if (ct_download (port, g703, tlen, tvec2) || 453 ct_download (port, g703_2, tlen, tvec2) || 454 ct_download (port, g703_3, tlen, tvec2) || 455 ct_download (port, g703_4, tlen, tvec2)) 456 type = B_TAU_G703; 457 ct_init_board (b, num, port, irq, dma, type, osc); 458 } 459 460 /* 461 * Initialize the channel structure. 462 */ 463 static void ct_init_chan (ct_board_t *b, int i) 464 { 465 ct_chan_t *c = b->chan + i; 466 port_t port = b->port; 467 468 c->num = i; 469 c->board = b; 470 switch (b->type) { 471 case B_TAU: 472 case B_TAU2: c->type = T_SERIAL; break; 473 case B_TAU_E1: 474 case B_TAU_E1C: 475 case B_TAU_E1D: 476 case B_TAU2_E1: 477 case B_TAU2_E1D: c->type = T_E1; break; 478 case B_TAU_G703: 479 case B_TAU_G703C: 480 case B_TAU2_G703: c->type = T_G703; break; 481 } 482 if (c->num) 483 c->type |= T_SERIAL; 484 485 #define reg(X,N) HD_##X##_##N 486 #define set(X,N) c->X = R(port,reg(X,N)) 487 #define srx(X,N) c->RX.X = R(port,reg(X,N##R)) 488 #define stx(X,N) c->TX.X = R(port,reg(X,N##T)) 489 if (i == 0) { 490 set(MD0, 0); set(MD1, 0); set(MD2, 0); set(CTL, 0); 491 set(RXS, 0); set(TXS, 0); set(TMC, 0); set(CMD, 0); 492 set(ST0, 0); set(ST1, 0); set(ST2, 0); set(ST3, 0); 493 set(FST, 0); set(IE0, 0); set(IE1, 0); set(IE2, 0); 494 set(FST, 0); set(IE0, 0); set(IE1, 0); set(IE2, 0); 495 set(FIE, 0); set(SA0, 0); set(SA1, 0); set(IDL, 0); 496 set(TRB, 0); set(RRC, 0); set(TRC0,0); set(TRC1,0); 497 set(CST, 0); 498 srx(DAR, 0); srx(DARB,0); srx(SAR, 0); srx(SARB,0); 499 srx(CDA, 0); srx(EDA, 0); srx(BFL, 0); srx(BCR, 0); 500 srx(DSR, 0); srx(DMR, 0); srx(FCT, 0); srx(DIR, 0); 501 srx(DCR, 0); 502 srx(TCNT,0); srx(TCONR,0); srx(TCSR,0); srx(TEPR,0); 503 stx(DAR, 0); stx(DARB,0); stx(SAR, 0); stx(SARB,0); 504 stx(CDA, 0); stx(EDA, 0); stx(BCR, 0); 505 stx(DSR, 0); stx(DMR, 0); stx(FCT, 0); stx(DIR, 0); 506 stx(DCR, 0); 507 stx(TCNT,0); stx(TCONR,0); stx(TCSR,0); stx(TEPR,0); 508 } else { 509 set(MD0, 1); set(MD1, 1); set(MD2, 1); set(CTL, 1); 510 set(RXS, 1); set(TXS, 1); set(TMC, 1); set(CMD, 1); 511 set(ST0, 1); set(ST1, 1); set(ST2, 1); set(ST3, 1); 512 set(FST, 1); set(IE0, 1); set(IE1, 1); set(IE2, 1); 513 set(FST, 1); set(IE0, 1); set(IE1, 1); set(IE2, 1); 514 set(FIE, 1); set(SA0, 1); set(SA1, 1); set(IDL, 1); 515 set(TRB, 1); set(RRC, 1); set(TRC0,1); set(TRC1,1); 516 set(CST, 1); 517 srx(DAR, 1); srx(DARB,1); srx(SAR, 1); srx(SARB,1); 518 srx(CDA, 1); srx(EDA, 1); srx(BFL, 1); srx(BCR, 1); 519 srx(DSR, 1); srx(DMR, 1); srx(FCT, 1); srx(DIR, 1); 520 srx(DCR, 1); 521 srx(TCNT,1); srx(TCONR,1); srx(TCSR,1); srx(TEPR,1); 522 stx(DAR, 1); stx(DARB,1); stx(SAR, 1); stx(SARB,1); 523 stx(CDA, 1); stx(EDA, 1); stx(BCR, 1); 524 stx(DSR, 1); stx(DMR, 1); stx(FCT, 1); stx(DIR, 1); 525 stx(DCR, 1); 526 stx(TCNT,1); stx(TCONR,1); stx(TCSR,1); stx(TEPR,1); 527 } 528 #undef set 529 #undef srx 530 #undef stx 531 #undef reg 532 } 533 534 /* 535 * Reinitialize the channels, using new options. 536 */ 537 void ct_reinit_chan (ct_chan_t *c) 538 { 539 ct_board_t *b = c->board; 540 long s; 541 int i; 542 543 if (c->hopt.txs == CLK_LINE) { 544 /* External clock mode -- set zero baud rate. */ 545 if (c->mode != M_ASYNC) 546 c->baud = 0; 547 } else if (c->baud == 0) { 548 /* No baud rate in internal clock mode -- set default values. */ 549 if (c->mode == M_ASYNC) 550 c->baud = 9600; 551 else if (c->mode == M_HDLC) 552 c->baud = 64000; 553 } 554 switch (c->type) { 555 case T_E1_SERIAL: 556 if (b->opt.cfg == CFG_B) 557 break; 558 /* Fall through... */ 559 case T_E1: 560 c->mode = M_E1; 561 c->hopt.txs = CLK_LINE; 562 563 /* Compute the baud value. */ 564 if (c->num) { 565 s = b->opt.s1; 566 if (b->opt.cfg == CFG_C) 567 s &=~ b->opt.s0; 568 } else 569 s = b->opt.s0; 570 /* Skip timeslot 16 in CAS mode. */ 571 if (c->gopt.cas) 572 s &=~ (1L << 16); 573 574 c->baud = 0; 575 for (i=0; i<32; ++i) 576 if ((s >> i) & 1) 577 c->baud += 64000; 578 c->gopt.rate = c->baud / 1000; 579 580 /* Set NRZ and clear INVCLK. */ 581 c->opt.md2.encod = MD2_ENCOD_NRZ; 582 c->board->opt.bcr2 &= c->num ? 583 ~(BCR2_INVTXC1 | BCR2_INVRXC1) : 584 ~(BCR2_INVTXC0 | BCR2_INVRXC0); 585 break; 586 587 case T_G703_SERIAL: 588 if (b->opt.cfg == CFG_B) 589 break; 590 /* Fall through... */ 591 case T_G703: 592 c->mode = M_G703; 593 c->hopt.txs = CLK_LINE; 594 c->baud = c->gopt.rate * 1000L; 595 596 /* Set NRZ/NRZI and clear INVCLK. */ 597 if (c->opt.md2.encod != MD2_ENCOD_NRZ && 598 c->opt.md2.encod != MD2_ENCOD_NRZI) 599 c->opt.md2.encod = MD2_ENCOD_NRZ; 600 c->board->opt.bcr2 &= c->num ? 601 ~(BCR2_INVTXC1 | BCR2_INVRXC1) : 602 ~(BCR2_INVTXC0 | BCR2_INVRXC0); 603 break; 604 } 605 } 606 607 /* 608 * Reinitialize all channels, using new options and baud rate. 609 */ 610 void ct_reinit_board (ct_board_t *b) 611 { 612 ct_chan_t *c; 613 614 b->opt = ct_board_opt_dflt; 615 for (c=b->chan; c<b->chan+NCHAN; ++c) { 616 c->opt = ct_chan_opt_dflt; 617 c->hopt = ct_opt_hdlc_dflt; 618 c->gopt = ct_opt_g703_dflt; 619 c->mode = ct_chan_mode; 620 c->baud = ct_baud; 621 622 ct_reinit_chan (c); 623 } 624 } 625 626 /* 627 * Set up the E1 controller of the Tau/E1 board. 628 * Frame sync signals: 629 * Configuration Rsync0 Tsync0 Rsync1 Tsync1 630 * --------------------------------------------------- 631 * A (II) out out out out 632 * B,C,D (HI,K,D) in out in out 633 * --------------------------------------------------- 634 * BI out out in in -- not implemented 635 * old B,C,D (HI,K,D) out in out in -- old 636 */ 637 static void ct_setup_ctlr (ct_chan_t *c) 638 { 639 ct_board_t *b = c->board; 640 port_t p = c->num ? E1CS1 (b->port) : E1CS0 (b->port); 641 unsigned char rcr1, rcr2, tcr1, tcr2, ccr1, licr; 642 unsigned long xcbr, tir; 643 int i; 644 645 rcr2 = RCR2_RSCLKM; 646 tcr1 = TCR1_TSIS | TCR1_TSO; 647 tcr2 = 0; 648 ccr1 = 0; 649 licr = 0; 650 651 if (b->opt.cfg != CFG_D) { 652 /* Enable monitoring channel, when not in telephony mode. */ 653 rcr2 |= RCR2_SA_4; 654 tcr2 |= TCR2_SA_4; 655 } 656 if (b->opt.cfg == CFG_A) { 657 rcr1 = RCR1_RSO; 658 } else { 659 rcr1 = RCR1_RSI; 660 rcr2 |= RCR2_RESE; 661 } 662 663 if (c->gopt.cas) 664 tcr1 |= TCR1_T16S; 665 else 666 ccr1 |= CCR1_CCS; 667 668 if (c->gopt.hdb3) 669 ccr1 |= CCR1_THDB3 | CCR1_RHDB3; 670 671 if (c->gopt.crc4) { 672 ccr1 |= CCR1_TCRC4 | CCR1_RCRC4; 673 tcr2 |= TCR2_AEBE; 674 } 675 676 if (c->gopt.higain) 677 licr |= LICR_HIGAIN; 678 if (inb (E1SR (b->port)) & (c->num ? E1SR_TP1 : E1SR_TP0)) 679 licr |= LICR_LB120P; 680 else 681 licr |= LICR_LB75P; 682 683 cte_out (p, DS_RCR1, rcr1); /* receive control 1 */ 684 cte_out (p, DS_RCR2, rcr2); /* receive control 2 */ 685 cte_out (p, DS_TCR1, tcr1); /* transmit control 1 */ 686 cte_out (p, DS_TCR2, tcr2); /* transmit control 2 */ 687 cte_out (p, DS_CCR1, ccr1); /* common control 1 */ 688 cte_out (p, DS_CCR2, CCR2_CNTCV | CCR2_AUTORA | CCR2_LOFA1); /* common control 2 */ 689 cte_out (p, DS_CCR3, CCR3_TSCLKM); /* common control 3 */ 690 cte_out (p, DS_LICR, licr); /* line interface control */ 691 cte_out (p, DS_IMR1, 0); /* interrupt mask 1 */ 692 cte_out (p, DS_IMR2, SR2_SEC); /* interrupt mask 2 */ 693 cte_out (p, DS_TEST1, 0); 694 cte_out (p, DS_TEST2, 0); 695 cte_out (p, DS_TAF, 0x9b); /* transmit align frame */ 696 cte_out (p, DS_TNAF, 0xdf); /* transmit non-align frame */ 697 cte_out (p, DS_TIDR, 0xff); /* transmit idle definition */ 698 699 cte_out (p, DS_TS, 0x0b); /* transmit signaling 1 */ 700 for (i=1; i<16; ++i) 701 /* transmit signaling 2..16 */ 702 cte_out (p, (unsigned char) (DS_TS+i), 0xff); 703 704 /* 705 * S0 == list of timeslots for channel 0 706 * S1 == list of timeslots for channel 1 707 * S2 == list of timeslots for E1 subchannel (pass through) 708 * 709 * Each channel uses the same timeslots for receive and transmit, 710 * i.e. RCBRi == TCBRi. 711 */ 712 if (b->opt.cfg == CFG_B) 713 b->opt.s1 = 0; 714 else if (b->opt.cfg == CFG_C) 715 b->opt.s1 &=~ b->opt.s0; 716 if (c->gopt.cas) { 717 /* Skip timeslot 16 in CAS mode. */ 718 b->opt.s0 &=~ (1L << 16); 719 b->opt.s1 &=~ (1L << 16); 720 } 721 b->opt.s2 &=~ b->opt.s0; 722 b->opt.s2 &=~ b->opt.s1; 723 724 /* 725 * Configuration A: 726 * xCBRi := Si 727 * TIRi := ~Si 728 * 729 * Configuration B: 730 * xCBRi := Si 731 * TIRi := 0 732 * 733 * Configuration C: (S0 & S2 == 0) 734 * xCBR0 := S0 735 * xCBR1 := 0 736 * TIR0 := ~S0 & ~S2 737 * TIR1 := ~S2 738 * 739 * Configuration D: (Si & Sj == 0) 740 * xCBR0 := S0 741 * xCBR1 := S1 742 * TIR0 := ~S0 & ~S1 & ~S2 743 * TIR1 := ~S2 744 */ 745 xcbr = c->num ? b->opt.s1 : b->opt.s0; 746 if (b->opt.cfg == CFG_A) 747 tir = ~xcbr; 748 else if (b->opt.cfg == CFG_D) 749 tir = 0; 750 else if (c->num == 0) 751 tir = ~(b->opt.s0 | b->opt.s1 | b->opt.s2); 752 else 753 tir = ~b->opt.s2; 754 755 /* Mark idle channels. */ 756 cte_out (p, DS_TIR, (unsigned char) (tir & 0xfe)); 757 cte_out (p, DS_TIR+1, (unsigned char) (tir >> 8)); 758 cte_out (p, DS_TIR+2, (unsigned char) (tir >> 16)); 759 cte_out (p, DS_TIR+3, (unsigned char) (tir >> 24)); 760 761 /* Set up rx/tx timeslots. */ 762 cte_out (p, DS_RCBR, (unsigned char) (xcbr & 0xfe)); 763 cte_out (p, DS_RCBR+1, (unsigned char) (xcbr >> 8)); 764 cte_out (p, DS_RCBR+2, (unsigned char) (xcbr >> 16)); 765 cte_out (p, DS_RCBR+3, (unsigned char) (xcbr >> 24)); 766 cte_out (p, DS_TCBR, (unsigned char) (xcbr & 0xfe)); 767 cte_out (p, DS_TCBR+1, (unsigned char) (xcbr >> 8)); 768 cte_out (p, DS_TCBR+2, (unsigned char) (xcbr >> 16)); 769 cte_out (p, DS_TCBR+3, (unsigned char) (xcbr >> 24)); 770 771 /* Reset the line interface. */ 772 cte_out (p, DS_CCR3, CCR3_TSCLKM | CCR3_LIRESET); 773 cte_out (p, DS_CCR3, CCR3_TSCLKM); 774 775 /* Reset the elastic store. */ 776 cte_out (p, DS_CCR3, CCR3_TSCLKM | CCR3_ESRESET); 777 cte_out (p, DS_CCR3, CCR3_TSCLKM); 778 779 /* Clear status registers. */ 780 cte_ins (p, DS_SR1, 0xff); 781 cte_ins (p, DS_SR2, 0xff); 782 cte_ins (p, DS_RIR, 0xff); 783 } 784 785 /* 786 * Set up the serial controller of the Tau/E1 board. 787 */ 788 static void ct_setup_scc (port_t port) 789 { 790 #define SET(r,v) { cte_out2 (port, r, v); cte_out2 (port, AM_A | r, v); } 791 792 /* hardware reset */ 793 cte_out2 (port, AM_MICR, MICR_RESET_HW); 794 795 SET (AM_PMR, 0x0c); /* 2 stop bits */ 796 SET (AM_IMR, 0); /* no W/REQ signal */ 797 cte_out2 (port, AM_IVR, 0); /* interrupt vector */ 798 SET (AM_RCR, 0xc0); /* rx 8 bits/char */ 799 SET (AM_TCR, 0x60); /* tx 8 bits/char */ 800 SET (AM_SAF, 0); /* sync address field */ 801 SET (AM_SFR, 0x7e); /* sync flag register */ 802 cte_out2 (port, AM_MICR, 0); /* master interrupt control */ 803 SET (AM_MCR, 0); /* NRZ mode */ 804 SET (AM_CMR, 0x08); /* rxclk=RTxC, txclk=TRxC */ 805 SET (AM_TCL, 0); /* time constant low */ 806 SET (AM_TCH, 0); /* time constant high */ 807 SET (AM_BCR, 0); /* disable baud rate generator */ 808 809 SET (AM_RCR, 0xc1); /* enable rx */ 810 SET (AM_TCR, 0x68); /* enable tx */ 811 812 SET (AM_SICR, 0); /* no status interrupt */ 813 SET (AM_CR, CR_RST_EXTINT); /* reset external status */ 814 SET (AM_CR, CR_RST_EXTINT); /* reset ext/status twice */ 815 #undef SET 816 } 817 818 /* 819 * Set up the Tau/E1 board. 820 */ 821 void ct_setup_e1 (ct_board_t *b) 822 { 823 /* 824 * Control register 0: 825 * 1) board configuration 826 * 2) clock modes 827 */ 828 b->e1cfg &= E1CFG_LED; 829 switch (b->opt.cfg){ 830 case CFG_C: b->e1cfg |= E1CFG_K; break; 831 case CFG_B: b->e1cfg |= E1CFG_HI; break; 832 case CFG_D: b->e1cfg |= E1CFG_D; break; 833 default: b->e1cfg |= E1CFG_II; break; 834 } 835 836 if (b->opt.clk0 == GCLK_RCV) b->e1cfg |= E1CFG_CLK0_RCV; 837 if (b->opt.clk0 == GCLK_RCLKO) b->e1cfg |= E1CFG_CLK0_RCLK1; 838 else b->e1cfg |= E1CFG_CLK0_INT; 839 if (b->opt.clk1 == GCLK_RCV) b->e1cfg |= E1CFG_CLK1_RCV; 840 if (b->opt.clk1 == GCLK_RCLKO) b->e1cfg |= E1CFG_CLK1_RCLK0; 841 else b->e1cfg |= E1CFG_CLK1_INT; 842 843 outb (E1CFG (b->port), b->e1cfg); 844 845 /* 846 * Set up serial controller. 847 */ 848 ct_setup_scc (b->port); 849 850 /* 851 * Set up E1 controllers. 852 */ 853 ct_setup_ctlr (b->chan + 0); /* channel 0 */ 854 ct_setup_ctlr (b->chan + 1); /* channel 1 */ 855 856 /* Start the board (GRUN). */ 857 b->e1cfg |= E1CFG_GRUN; 858 outb (E1CFG (b->port), b->e1cfg); 859 } 860 861 /* 862 * Set up the G.703 controller of the Tau/G.703 board. 863 */ 864 static void ct_setup_lxt (ct_chan_t *c) 865 { 866 ctg_outx (c, LX_CCR1, LX_RESET); /* reset the chip */ 867 /* Delay */ 868 ctg_inx (c, LX_CCR1); 869 c->lx = LX_LOS; /* disable loss of sync interrupt */ 870 if (c->num && c->board->opt.cfg == CFG_B) 871 c->lx |= LX_TAOS; /* idle channel--transmit all ones */ 872 if (c->gopt.hdb3) 873 c->lx |= LX_HDB3; /* enable HDB3 encoding */ 874 ctg_outx (c, LX_CCR1, c->lx); /* setup the new mode */ 875 ctg_outx (c, LX_CCR2, LX_CCR2_LH); /* setup Long Haul mode */ 876 ctg_outx (c, LX_CCR3, LX_CCR3_E1_LH); /* setup Long Haul mode */ 877 } 878 879 /* 880 * Set up the Tau/G.703 board. 881 */ 882 void ct_setup_g703 (ct_board_t *b) 883 { 884 b->gmd0 = GMD_2048; 885 if (b->chan[0].gopt.pce) { 886 if (b->chan[0].gopt.pce2) b->gmd0 |= GMD_PCE_PCM2; 887 else b->gmd0 |= GMD_PCE_PCM2D; 888 } 889 if (b->opt.clk0) 890 b->gmd0 |= GMD_RSYNC; 891 892 b->gmd1 = 0; 893 if (b->chan[1].gopt.pce) { 894 if (b->chan[1].gopt.pce2) b->gmd1 |= GMD_PCE_PCM2; 895 else b->gmd1 |= GMD_PCE_PCM2D; 896 } 897 if (b->opt.clk1) 898 b->gmd1 |= GMD_RSYNC; 899 900 switch (b->chan[0].gopt.rate) { 901 case 2048: b->gmd0 |= GMD_2048; break; 902 case 1024: b->gmd0 |= GMD_1024; break; 903 case 512: b->gmd0 |= GMD_512; break; 904 case 256: b->gmd0 |= GMD_256; break; 905 case 128: b->gmd0 |= GMD_128; break; 906 case 64: b->gmd0 |= GMD_64; break; 907 } 908 switch (b->chan[1].gopt.rate) { 909 case 2048: b->gmd1 |= GMD_2048; break; 910 case 1024: b->gmd1 |= GMD_1024; break; 911 case 512: b->gmd1 |= GMD_512; break; 912 case 256: b->gmd1 |= GMD_256; break; 913 914 case 128: b->gmd1 |= GMD_128; break; 915 case 64: b->gmd1 |= GMD_64; break; 916 } 917 918 outb (GMD0(b->port), b->gmd0); 919 outb (GMD1(b->port), b->gmd1 | GMD1_NCS0 | GMD1_NCS1); 920 921 b->gmd2 &= GMD2_LED; 922 if (b->opt.cfg == CFG_B) b->gmd2 |= GMD2_SERIAL; 923 outb (GMD2(b->port), b->gmd2); 924 925 /* Set up G.703 controllers. */ 926 if ((b->chan + 0)->lx & LX_LLOOP) { 927 ct_setup_lxt (b->chan + 0); /* channel 0 */ 928 ct_enable_loop (b->chan + 0); 929 } else { 930 ct_setup_lxt (b->chan + 0); /* channel 0 */ 931 } 932 if ((b->chan + 1)->lx & LX_LLOOP) { 933 ct_setup_lxt (b->chan + 1); /* channel 1 */ 934 ct_enable_loop (b->chan + 1); 935 } else { 936 ct_setup_lxt (b->chan + 1); /* channel 1 */ 937 } 938 939 /* Clear errors. */ 940 outb (GERR(b->port), 0xff); 941 outb (GLDR(b->port), 0xff); 942 } 943 944 /* 945 * Set up the board. 946 */ 947 int ct_setup_board (ct_board_t *b, const unsigned char *firmware, 948 long bits, const cr_dat_tst_t *tst) 949 { 950 ct_chan_t *c; 951 952 /* Disable DMA channel. */ 953 outb (DMA_MASK, (b->dma & 3) | DMA_MASK_CLEAR); 954 955 /* Reset the controller. */ 956 outb (BCR0(b->port), 0); 957 958 /* Load the firmware. */ 959 if (firmware && (b->type == B_TAU || b->type == B_TAU_E1 || 960 b->type == B_TAU_G703) && 961 ! ct_download (b->port, firmware, bits, tst)) 962 return (0); 963 if (firmware && (b->type == B_TAU2 || b->type == B_TAU2_E1 || 964 b->type == B_TAU2_E1D || b->type == B_TAU2_G703) && 965 ! ct_download2 (b->port, firmware)) 966 return (0); 967 968 /* Enable DMA and IRQ. */ 969 outb (BCR0(b->port), BCR0_HDRUN); 970 outb (BCR0(b->port), b->bcr0); 971 972 /* Clear DTR[0..1]. */ 973 outb (BCR1(b->port), b->bcr1); 974 975 /* Set bus timing. */ 976 b->bcr2 = b->opt.bcr2; 977 outb (BCR2(b->port), b->bcr2); 978 979 /* 980 * Initialize the controller. 981 */ 982 /* Zero wait state mode. */ 983 outb (WCRL(b->port), 0); 984 outb (WCRM(b->port), 0); 985 outb (WCRH(b->port), 0); 986 987 /* Clear interrupt modified vector register. */ 988 outb (IMVR(b->port), 0); 989 outb (ITCR(b->port), ITCR_CYCLE_SINGLE | ITCR_VECT_MOD); 990 991 /* Disable all interrupts. */ 992 outb (IER0(b->port), 0); 993 outb (IER1(b->port), 0); 994 outb (IER2(b->port), 0); 995 996 /* Set DMA parameters, enable master DMA mode. */ 997 outb (PCR(b->port), BYTE b->opt.pcr); 998 outb (DMER(b->port), DME_ENABLE); 999 1000 /* Set up DMA channel to master mode. */ 1001 outb (DMA_MODE, (b->dma & 3) | DMA_MODE_MASTER); 1002 1003 /* Enable DMA channel. */ 1004 outb (DMA_MASK, b->dma & 3); 1005 1006 /* Disable byte-sync mode for Tau/G.703. */ 1007 if (b->type == B_TAU_G703) 1008 outb (GMD2(b->port), 0); 1009 1010 /* Initialize all channels. */ 1011 for (c=b->chan; c<b->chan+NCHAN; ++c) 1012 ct_setup_chan (c); 1013 1014 switch (b->type) { 1015 case B_TAU_G703: 1016 case B_TAU_G703C: 1017 case B_TAU2_G703: 1018 ct_setup_g703 (b); 1019 break; 1020 case B_TAU_E1: 1021 case B_TAU_E1C: 1022 case B_TAU_E1D: 1023 case B_TAU2_E1: 1024 case B_TAU2_E1D: 1025 ct_setup_e1 (b); 1026 break; 1027 } 1028 return (1); 1029 } 1030 1031 /* 1032 * Update the channel mode options. 1033 */ 1034 void ct_update_chan (ct_chan_t *c) 1035 { 1036 int txbr, rxbr, tmc, txcout; 1037 unsigned char rxs, txs, dmr = 0; 1038 ct_md0_async_t amd0; 1039 ct_md0_hdlc_t hmd0; 1040 ct_md1_async_t amd1; 1041 1042 switch (c->mode) { /* initialize the channel mode */ 1043 case M_ASYNC: default: 1044 rxs = CLK_INT; 1045 txs = CLK_INT; 1046 1047 amd0.mode = MD0_MODE_ASYNC; 1048 amd0.stopb = MD0_STOPB_1; 1049 amd0.cts_rts_dcd = 0; 1050 1051 amd1.clk = MD1_CLK_16; 1052 amd1.txclen = amd1.rxclen = MD1_CLEN_8; 1053 amd1.parmode = MD1_PAR_NO; 1054 1055 outb (c->MD0, BYTE amd0); 1056 outb (c->MD1, BYTE amd1); 1057 outb (c->CTL, c->rts ? 0 : CTL_RTS_INV); 1058 break; 1059 1060 case M_E1: 1061 case M_G703: 1062 case M_HDLC: 1063 rxs = c->hopt.rxs; 1064 txs = c->hopt.txs; 1065 1066 if (c->mode == M_E1 && c->board->opt.cfg == CFG_D) { 1067 hmd0 = c->hopt.md0; 1068 hmd0.crc = 0; 1069 1070 outb (c->MD0, BYTE hmd0); 1071 outb (c->MD1, BYTE c->hopt.md1); 1072 outb (c->CTL, c->hopt.ctl & ~CTL_IDLE_PTRN); 1073 outb (c->SA0, c->hopt.sa0); 1074 outb (c->SA1, c->hopt.sa1); 1075 outb (c->IDL, 0x7e); /* HDLC flag 01111110 */ 1076 } else { 1077 outb (c->MD0, BYTE c->hopt.md0); 1078 outb (c->MD1, BYTE c->hopt.md1); 1079 outb (c->SA0, c->hopt.sa0); 1080 outb (c->SA1, c->hopt.sa1); 1081 outb (c->IDL, 0x7e); /* HDLC flag 01111110 */ 1082 1083 if (c->rts) 1084 outb (c->CTL, c->hopt.ctl & ~CTL_RTS_INV); 1085 else 1086 outb (c->CTL, c->hopt.ctl | CTL_RTS_INV); 1087 } 1088 1089 /* Chained-block DMA mode with frame counter. */ 1090 dmr |= DMR_CHAIN_CNTE | DMR_CHAIN_NF | DMR_TMOD; 1091 break; 1092 1093 } 1094 outb (c->RX.DMR, dmr); 1095 outb (c->TX.DMR, dmr); 1096 1097 /* set mode-independent options */ 1098 c->opt.md2.dpll_clk = MD2_DPLL_CLK_8; 1099 outb (c->MD2, BYTE c->opt.md2); 1100 1101 /* set up receiver and transmitter clocks */ 1102 if (c->baud > 1024000) { 1103 /* turn off DPLL if the baud rate is too high */ 1104 if (rxs == CLK_RXS_LINE_NS) rxs = CLK_LINE; 1105 else if (rxs == CLK_RXS_DPLL_INT) rxs = CLK_INT; 1106 } 1107 if (rxs == CLK_RXS_LINE_NS || rxs == CLK_RXS_DPLL_INT) { 1108 /* Using 1:8 sampling rate. */ 1109 ct_compute_clock (c->board->osc, c->baud * 8, &rxbr, &tmc); 1110 txbr = rxbr + 3; 1111 } else if (c->mode == M_ASYNC) { 1112 /* Using 1:16 sampling rate. */ 1113 ct_compute_clock (c->board->osc, c->baud * 8, &rxbr, &tmc); 1114 --rxbr; 1115 txbr = rxbr; 1116 } else { 1117 ct_compute_clock (c->board->osc, c->baud, &rxbr, &tmc); 1118 txbr = rxbr; 1119 } 1120 txs |= txbr; 1121 rxs |= rxbr; 1122 outb (c->TMC, tmc); 1123 outb (c->RXS, rxs); 1124 1125 /* Disable TXCOUT before changing TXS 1126 * to avoid two transmitters on the same line. 1127 * Enable it after TXS is set, if needed. */ 1128 txcout = c->num ? BCR1_TXCOUT1 : BCR1_TXCOUT0; 1129 c->board->bcr1 &= ~txcout; 1130 outb (BCR1(c->board->port), c->board->bcr1); 1131 outb (c->TXS, txs); 1132 if ((txs & CLK_MASK) != CLK_LINE) { 1133 c->board->bcr1 |= txcout; 1134 outb (BCR1(c->board->port), c->board->bcr1); 1135 } 1136 if (c->board->type == B_TAU_E1D || 1137 c->board->type == B_TAU2_E1D) 1138 ct_set_phony (c, c->gopt.phony); 1139 } 1140 1141 /* 1142 * Initialize the channel. 1143 */ 1144 void ct_setup_chan (ct_chan_t *c) 1145 { 1146 /* reset the channel */ 1147 outb (c->RX.DSR, DSR_DMA_DISABLE); 1148 outb (c->TX.DSR, DSR_DMA_DISABLE); 1149 outb (c->CMD, CMD_TX_RESET); 1150 outb (c->CMD, CMD_TX_ABORT); 1151 outb (c->CMD, CMD_CHAN_RESET); 1152 1153 /* disable interrupts */ 1154 outb (c->IE0, 0); 1155 outb (c->IE1, 0); 1156 outb (c->IE2, 0); 1157 outb (c->FIE, 0); 1158 1159 /* clear DTR, RTS */ 1160 ct_set_dtr (c, 0); 1161 ct_set_rts (c, 0); 1162 1163 c->lx = LX_LOS; 1164 ct_update_chan (c); 1165 } 1166 1167 unsigned long ct_get_ts (ct_chan_t *c) 1168 { 1169 return c->num ? c->board->opt.s1 : c->board->opt.s0; 1170 } 1171 1172 /* 1173 * Data transfer speed 1174 */ 1175 unsigned long ct_get_baud (ct_chan_t *c) 1176 { 1177 unsigned long speed; 1178 unsigned long ts; 1179 1180 if (c->mode == M_G703) { 1181 speed = 1000 * c->gopt.rate; 1182 } else if (c->mode == M_E1) { 1183 ts = ct_get_ts (c); 1184 for (speed=0; ts; ts >>= 1) /* Each timeslot is 64 Kbps */ 1185 if (ts & 1) 1186 speed += 64000; 1187 } else 1188 speed = (c->hopt.txs == CLK_INT) ? c->baud : 0; 1189 return speed; 1190 } 1191 1192 /* 1193 * Turn local loopback on 1194 */ 1195 static void ct_enable_loop (ct_chan_t *c) 1196 { 1197 if (c->mode == M_E1) { 1198 unsigned short p = c->num ? E1CS1 (c->board->port) : 1199 E1CS0 (c->board->port); 1200 1201 /* Local loopback. */ 1202 cte_out (p, DS_CCR2, cte_in (p, DS_CCR2) | CCR2_LLOOP); 1203 1204 /* Enable jitter attenuator at the transmit side. */ 1205 cte_out (p, DS_LICR, cte_in (p, DS_LICR) | LICR_JA_TX); 1206 return; 1207 } else if (c->mode == M_G703) { 1208 c->lx = LX_LOS | LX_HDB3; 1209 ctg_outx (c, LX_CCR1, c->lx |= LX_LLOOP); 1210 return; 1211 } else if (c->mode == M_HDLC && ct_get_baud(c)) { 1212 unsigned char rxs = inb (c->RXS) & ~CLK_MASK; 1213 unsigned char txs = inb (c->TXS) & ~CLK_MASK; 1214 int txcout = c->num ? BCR1_TXCOUT1 : BCR1_TXCOUT0; 1215 c->opt.md2.loop = MD2_LLOOP; 1216 1217 /* Disable TXCOUT before changing TXS */ 1218 /* to avoid two transmitters on the same line. */ 1219 /* Enable it after TXS is set. */ 1220 outb (BCR1(c->board->port), c->board->bcr1 & ~txcout); 1221 1222 outb (c->RXS, rxs | CLK_INT); 1223 outb (c->TXS, txs | CLK_INT); 1224 1225 c->board->bcr1 |= txcout; 1226 outb (BCR1(c->board->port), c->board->bcr1); 1227 1228 outb (c->MD2, *(unsigned char*)&c->opt.md2); 1229 return; 1230 } 1231 } 1232 1233 /* 1234 * Turn local loopback off 1235 */ 1236 static void ct_disable_loop (ct_chan_t *c) 1237 { 1238 if (c->mode == M_E1) { 1239 unsigned short p = c->num ? E1CS1 (c->board->port) : 1240 E1CS0 (c->board->port); 1241 1242 /* Local loopback. */ 1243 cte_out (p, DS_CCR2, cte_in (p, DS_CCR2) & ~CCR2_LLOOP); 1244 1245 /* Disable jitter attenuator at the transmit side. */ 1246 cte_out (p, DS_LICR, cte_in (p, DS_LICR) & ~LICR_JA_TX); 1247 return; 1248 } else if (c->mode == M_G703) { 1249 c->lx = LX_LOS | LX_HDB3; 1250 ctg_outx (c, LX_CCR1, c->lx); 1251 return; 1252 } else if (c->mode == M_HDLC && ct_get_baud(c)) { 1253 unsigned char rxs = inb (c->RXS) & ~CLK_MASK; 1254 unsigned char txs = inb (c->TXS) & ~CLK_MASK; 1255 int txcout = c->num ? BCR1_TXCOUT1 : BCR1_TXCOUT0; 1256 c->opt.md2.loop = MD2_FDX; 1257 1258 outb (BCR1(c->board->port), c->board->bcr1 & ~txcout); 1259 1260 outb (c->RXS, rxs | CLK_LINE); 1261 if (ct_get_baud (c)) 1262 outb (c->TXS, txs | CLK_INT); 1263 else 1264 outb (c->TXS, txs | CLK_LINE); 1265 1266 c->board->bcr1 |= txcout; 1267 outb (BCR1(c->board->port), c->board->bcr1); 1268 1269 outb (c->MD2, *(unsigned char*)&c->opt.md2); 1270 return; 1271 } 1272 } 1273 1274 /* 1275 * Turn local loopback on/off 1276 */ 1277 void ct_set_loop (ct_chan_t *c, int on) 1278 { 1279 if (on) 1280 ct_enable_loop (c); 1281 else 1282 ct_disable_loop (c); 1283 } 1284 1285 int ct_get_loop (ct_chan_t *c) 1286 { 1287 if (c->mode == M_E1) { 1288 unsigned short p = c->num ? E1CS1 (c->board->port) : 1289 E1CS0 (c->board->port); 1290 1291 return cte_in (p, DS_CCR2) & CCR2_LLOOP; 1292 } 1293 if (c->mode == M_G703) 1294 return c->lx & LX_LLOOP; 1295 1296 /* M_HDLC */ 1297 return (c->opt.md2.loop & MD2_LLOOP) != 0; 1298 } 1299 1300 void ct_set_phony (ct_chan_t *c, int on) 1301 { 1302 /* Valid only for TauPCI-E1. */ 1303 if (c->board->type != B_TAU_E1D && 1304 c->board->type != B_TAU2_E1D) 1305 return; 1306 c->gopt.phony = (on != 0); 1307 if (c->gopt.phony) { 1308 c->board->e1syn |= c->num ? E1SYN_ENS1 : E1SYN_ENS0; 1309 /* No receive/transmit crc. */ 1310 c->hopt.md0.crc = 0; 1311 } else { 1312 c->board->e1syn &= ~(c->num ? E1SYN_ENS1 : E1SYN_ENS0); 1313 /* Enable crc. */ 1314 c->hopt.md0.crc = 1; 1315 } 1316 outb (c->MD0, BYTE c->hopt.md0); 1317 outb (E1SYN(c->board->port), c->board->e1syn); 1318 } 1319 1320 void ct_start_receiver (ct_chan_t *c, int dma, unsigned long buf, 1321 unsigned len, unsigned long desc, unsigned long lim) 1322 { 1323 int ier0 = inb (IER0(c->board->port)); 1324 int ier1 = inb (IER1(c->board->port)); 1325 int ier2 = inb (IER2(c->board->port)); 1326 int ie0 = inb (c->IE0); 1327 int ie2 = inb (c->IE2); 1328 1329 if (dma) { 1330 ier1 |= c->num ? (IER1_RX_DMERE_1 | IER1_RX_DME_1) : 1331 (IER1_RX_DMERE_0 | IER1_RX_DME_0); 1332 if (c->mode == M_ASYNC) { 1333 ier0 |= c->num ? IER0_RX_INTE_1 : IER0_RX_INTE_0; 1334 ie0 |= IE0_RX_INTE; 1335 ie2 |= IE2_OVRNE | IE2_ASYNC_FRMEE | IE2_ASYNC_PEE; 1336 } 1337 } else { 1338 ier0 |= c->num ? (IER0_RX_INTE_1 | IER0_RX_RDYE_1) : 1339 (IER0_RX_INTE_0 | IER0_RX_RDYE_0); 1340 ie0 |= IE0_RX_INTE | IE0_RX_RDYE; 1341 } 1342 1343 /* Start timer. */ 1344 if (! dma) { 1345 outb (c->RX.TEPR, TEPR_64); /* prescale to 16 kHz */ 1346 outw (c->RX.TCONR, 160); /* period is 10 msec */ 1347 outw (c->RX.TCNT, 0); 1348 outb (c->RX.TCSR, TCSR_ENABLE | TCSR_INTR); 1349 ier2 |= c->num ? IER2_RX_TME_1 : IER2_RX_TME_0; 1350 } 1351 1352 /* Enable interrupts. */ 1353 outb (IER0(c->board->port), ier0); 1354 outb (IER1(c->board->port), ier1); 1355 outb (IER2(c->board->port), ier2); 1356 outb (c->IE0, ie0); 1357 outb (c->IE2, ie2); 1358 1359 /* RXRDY:=1 when the receive buffer has more than RRC chars */ 1360 outb (c->RRC, dma ? c->opt.dma_rrc : c->opt.pio_rrc); 1361 1362 /* Start receiver. */ 1363 if (dma) { 1364 outb (c->RX.DCR, DCR_ABORT); 1365 if (c->mode == M_ASYNC) { 1366 /* Single-buffer DMA mode. */ 1367 outb (c->RX.DARB, (unsigned char) (buf >> 16)); 1368 outw (c->RX.DAR, (unsigned short) buf); 1369 outw (c->RX.BCR, len); 1370 outb (c->RX.DIR, DIR_EOTE); 1371 } else { 1372 /* Chained-buffer DMA mode. */ 1373 outb (c->RX.SARB, (unsigned char) (desc >> 16)); 1374 outw (c->RX.EDA, (unsigned short) lim); 1375 outw (c->RX.CDA, (unsigned short) desc); 1376 outw (c->RX.BFL, len); 1377 outb (c->RX.DIR, DIR_CHAIN_EOME | DIR_CHAIN_BOFE | 1378 DIR_CHAIN_COFE); 1379 } 1380 outb (c->RX.DSR, DSR_DMA_ENABLE); 1381 } 1382 outb (c->CMD, CMD_RX_ENABLE); 1383 } 1384 1385 void ct_start_transmitter (ct_chan_t *c, int dma, unsigned long buf, 1386 unsigned len, unsigned long desc, unsigned long lim) 1387 { 1388 int ier0 = inb (IER0(c->board->port)); 1389 int ier1 = inb (IER1(c->board->port)); 1390 int ie0 = inb (c->IE0); 1391 int ie1 = inb (c->IE1); 1392 1393 /* Enable underrun interrupt in HDLC and raw modes. */ 1394 if (c->mode != M_ASYNC) { 1395 ier0 |= c->num ? IER0_TX_INTE_1 : IER0_TX_INTE_0; 1396 ie0 |= IE0_TX_INTE; 1397 ie1 |= IE1_HDLC_UDRNE; 1398 } 1399 if (dma) 1400 ier1 |= c->num ? (IER1_TX_DMERE_1 | IER1_TX_DME_1) : 1401 (IER1_TX_DMERE_0 | IER1_TX_DME_0); 1402 else { 1403 ier0 |= c->num ? IER0_TX_RDYE_1 : IER0_TX_RDYE_0; 1404 ie0 |= IE0_TX_RDYE; 1405 } 1406 1407 /* Enable interrupts. */ 1408 outb (IER0(c->board->port), ier0); 1409 outb (IER1(c->board->port), ier1); 1410 outb (c->IE0, ie0); 1411 outb (c->IE1, ie1); 1412 1413 /* TXRDY:=1 when the transmit buffer has TRC0 or less chars, 1414 * TXRDY:=0 when the transmit buffer has more than TRC1 chars */ 1415 outb (c->TRC0, dma ? c->opt.dma_trc0 : c->opt.pio_trc0); 1416 outb (c->TRC1, dma ? c->opt.dma_trc1 : c->opt.pio_trc1); 1417 1418 /* Start transmitter. */ 1419 if (dma) { 1420 outb (c->TX.DCR, DCR_ABORT); 1421 if (c->mode == M_ASYNC) { 1422 /* Single-buffer DMA mode. */ 1423 outb (c->TX.SARB, (unsigned char) (buf >> 16)); 1424 outw (c->TX.SAR, (unsigned short) buf); 1425 outw (c->TX.BCR, len); 1426 outb (c->TX.DIR, DIR_EOTE); 1427 } else { 1428 /* Chained-buffer DMA mode. */ 1429 outb (c->TX.SARB, (unsigned char) (desc >> 16)); 1430 outw (c->TX.EDA, (unsigned short) lim); 1431 outw (c->TX.CDA, (unsigned short) desc); 1432 outb (c->TX.DIR, /* DIR_CHAIN_EOME | */ DIR_CHAIN_BOFE | 1433 DIR_CHAIN_COFE); 1434 } 1435 /* Set DSR_DMA_ENABLE to begin! */ 1436 } 1437 outb (c->CMD, CMD_TX_ENABLE); 1438 1439 /* Clear errors. */ 1440 if (c->board->type == B_TAU_G703) { 1441 outb (GERR(c->board->port), 0xff); 1442 outb (GLDR(c->board->port), 0xff); 1443 } 1444 } 1445 1446 /* 1447 * Control DTR signal for the channel. 1448 * Turn it on/off. 1449 */ 1450 void ct_set_dtr (ct_chan_t *c, int on) 1451 { 1452 if (on) { 1453 c->dtr = 1; 1454 c->board->bcr1 |= c->num ? BCR1_DTR1 : BCR1_DTR0; 1455 } else { 1456 c->dtr = 0; 1457 c->board->bcr1 &= ~(c->num ? BCR1_DTR1 : BCR1_DTR0); 1458 } 1459 outb (BCR1(c->board->port), c->board->bcr1); 1460 } 1461 1462 /* 1463 * Control RTS signal for the channel. 1464 * Turn it on/off. 1465 */ 1466 void ct_set_rts (ct_chan_t *c, int on) 1467 { 1468 c->rts = (on != 0); 1469 if (c->rts) 1470 outb (c->CTL, inb (c->CTL) & ~CTL_RTS_INV); 1471 else 1472 outb (c->CTL, inb (c->CTL) | CTL_RTS_INV); 1473 } 1474 1475 /* 1476 * Control BREAK state in asynchronous mode. 1477 * Turn it on/off. 1478 */ 1479 void ct_set_brk (ct_chan_t *c, int on) 1480 { 1481 if (c->mode != M_ASYNC) 1482 return; 1483 if (on) 1484 outb (c->CTL, inb (c->CTL) | CTL_BRK); 1485 else 1486 outb (c->CTL, inb (c->CTL) & ~CTL_BRK); 1487 } 1488 1489 /* 1490 * Get the state of DSR signal of the channel. 1491 */ 1492 int ct_get_dsr (ct_chan_t *c) 1493 { 1494 return (inb (BSR1(c->board->port)) & 1495 (c->num ? BSR1_DSR1 : BSR1_DSR0)) != 0; 1496 } 1497 1498 /* 1499 * Get the G.703 line signal level. 1500 */ 1501 int ct_get_lq (ct_chan_t *c) 1502 { 1503 unsigned char q1, q2, q3; 1504 static int lq_to_santibells [] = { 0, 95, 195, 285 }; 1505 int i; 1506 1507 if (! (c->type & T_G703)) 1508 return 0; 1509 q1 = inb (GLQ (c->board->port)); 1510 /* Repeat reading the register to produce a 10-usec delay. */ 1511 for (i=0; i<20; ++i) 1512 q2 = inb (GLQ (c->board->port)); 1513 for (i=0; i<20; ++i) 1514 q3 = inb (GLQ (c->board->port)); 1515 if (c->num) { 1516 q1 >>= GLQ_SHIFT; 1517 q2 >>= GLQ_SHIFT; 1518 q3 >>= GLQ_SHIFT; 1519 } 1520 q1 &= GLQ_MASK; 1521 q2 &= GLQ_MASK; 1522 q3 &= GLQ_MASK; 1523 if (q1 <= q2 && q2 <= q3) return lq_to_santibells [q2]; 1524 if (q2 <= q3 && q3 <= q1) return lq_to_santibells [q3]; 1525 if (q3 <= q1 && q1 <= q2) return lq_to_santibells [q1]; 1526 if (q1 <= q3 && q3 <= q2) return lq_to_santibells [q3]; 1527 if (q3 <= q2 && q2 <= q1) return lq_to_santibells [q2]; 1528 /* if (q2 <= q1 && q1 <= q3) */ return lq_to_santibells [q1]; 1529 } 1530 1531 /* 1532 * Get the state of CARRIER signal of the channel. 1533 */ 1534 int ct_get_cd (ct_chan_t *c) 1535 { 1536 return (inb (c->ST3) & ST3_DCD_INV) == 0; 1537 } 1538 1539 /* 1540 * Get the state of CTS signal of the channel. 1541 */ 1542 int ct_get_cts (ct_chan_t *c) 1543 { 1544 return (inb (c->ST3) & ST3_CTS_INV) == 0; 1545 } 1546 1547 /* 1548 * Turn LED on/off. 1549 */ 1550 void ct_led (ct_board_t *b, int on) 1551 { 1552 switch (b->type) { 1553 case B_TAU_G703: 1554 case B_TAU_G703C: 1555 case B_TAU2_G703: 1556 if (on) b->gmd2 |= GMD2_LED; 1557 else b->gmd2 &= ~GMD2_LED; 1558 outb (GMD2(b->port), b->gmd2); 1559 break; 1560 default: 1561 if (on) b->e1cfg |= E1CFG_LED; 1562 else b->e1cfg &= ~E1CFG_LED; 1563 outb (E1CFG(b->port), b->e1cfg); 1564 break; 1565 } 1566 } 1567 1568 void ct_disable_dma (ct_board_t *b) 1569 { 1570 /* Disable DMA channel. */ 1571 outb (DMA_MASK, (b->dma & 3) | DMA_MASK_CLEAR); 1572 } 1573 1574 void ct_compute_clock (long hz, long baud, int *txbr, int *tmc) 1575 { 1576 if (baud < 100) 1577 baud = 100; 1578 *txbr = 0; 1579 if (4*baud > 3*hz) 1580 *tmc = 1; 1581 else { 1582 while (((hz / baud) >> ++*txbr) > 256) 1583 continue; 1584 *tmc = (((2 * hz / baud) >> *txbr) + 1) / 2; 1585 } 1586 } 1587 1588 /* 1589 * Access to DS2153 chips on the Tau/E1 board. 1590 * Examples: 1591 * val = cte_in (E1CSi (base), DS_RCR1) 1592 * cte_out (E1CSi (base), DS_CCR1, val) 1593 * val = cte_ins (E1CSi (base), DS_SSR) 1594 */ 1595 unsigned char cte_in (port_t base, unsigned char reg) 1596 { 1597 outb (base, reg); 1598 return inb (E1DAT (base & 0x3e0)); 1599 } 1600 1601 void cte_out (port_t base, unsigned char reg, unsigned char val) 1602 { 1603 outb (base, reg); 1604 outb (E1DAT (base & 0x3e0), val); 1605 } 1606 1607 /* 1608 * Get the DS2153 status register, using write-read-write scheme. 1609 */ 1610 unsigned char cte_ins (port_t base, unsigned char reg, 1611 unsigned char mask) 1612 { 1613 unsigned char val; 1614 port_t rw = E1DAT (base & 0x3e0); 1615 1616 outb (base, reg); outb (rw, mask); /* lock bits */ 1617 outb (base, reg); val = inb (rw) & mask; /* get values */ 1618 outb (base, reg); outb (rw, val); /* unlock bits */ 1619 return val; 1620 } 1621 1622 /* 1623 * Access to 8530 chip on the Tau/E1 board. 1624 * Examples: 1625 * val = cte_in2 (base, AM_RSR | AM_A) 1626 * cte_out2 (base, AM_IMR, val) 1627 */ 1628 unsigned char cte_in2 (port_t base, unsigned char reg) 1629 { 1630 outb (E1CS2(base), E1CS2_SCC | reg >> 4); 1631 outb (E1DAT(base), reg & 15); 1632 return inb (E1DAT(base)); 1633 } 1634 1635 void cte_out2 (port_t base, unsigned char reg, unsigned char val) 1636 { 1637 outb (E1CS2(base), E1CS2_SCC | reg >> 4); 1638 outb (E1DAT(base), reg & 15); 1639 outb (E1DAT(base), val); 1640 } 1641 1642 /* 1643 * Read the data from the 8530 receive fifo. 1644 */ 1645 unsigned char cte_in2d (ct_chan_t *c) 1646 { 1647 outb (E1CS2(c->board->port), E1CS2_SCC | E1CS2_DC | 1648 (c->num ? 0 : E1CS2_AB)); 1649 return inb (E1DAT(c->board->port)); 1650 } 1651 1652 /* 1653 * Send the 8530 command. 1654 */ 1655 void cte_out2c (ct_chan_t *c, unsigned char val) 1656 { 1657 outb (E1CS2(c->board->port), E1CS2_SCC | (c->num ? 0 : E1CS2_AB)); 1658 outb (E1DAT(c->board->port), val); 1659 } 1660 1661 /* 1662 * Write the data to the 8530 transmit fifo. 1663 */ 1664 void cte_out2d (ct_chan_t *c, unsigned char val) 1665 { 1666 outb (E1CS2(c->board->port), E1CS2_SCC | E1CS2_DC | 1667 (c->num ? 0 : E1CS2_AB)); 1668 outb (E1DAT(c->board->port), val); 1669 } 1670 1671 /* 1672 * Access to LXT318 chip on the Tau/G.703 board. 1673 * Examples: 1674 * val = ctg_inx (c) 1675 * ctg_outx (c, val) 1676 */ 1677 static void ctg_output (port_t port, unsigned char val, unsigned char v0) 1678 { 1679 int i; 1680 1681 for (i=0; i<8; ++i) { 1682 unsigned char v = v0; 1683 if ((val >> i) & 1) 1684 v |= GMD0_SDI; 1685 outb (port, v); 1686 outb (port, v); 1687 outb (port, v); 1688 outb (port, v); 1689 outb (port, v | GMD0_SCLK); 1690 outb (port, v | GMD0_SCLK); 1691 outb (port, v | GMD0_SCLK); 1692 outb (port, v | GMD0_SCLK); 1693 } 1694 outb (port, v0); 1695 } 1696 1697 void ctg_outx (ct_chan_t *c, unsigned char reg, unsigned char val) 1698 { 1699 port_t port = GMD0(c->board->port); 1700 1701 outb (GMD1(c->board->port), c->board->gmd1 | GMD1_NCS0 | GMD1_NCS1); 1702 outb (GMD1(c->board->port), c->board->gmd1 | 1703 (c->num ? GMD1_NCS0 : GMD1_NCS1)); 1704 ctg_output (port, (reg << 1) | LX_WRITE, c->board->gmd0); 1705 ctg_output (port, val, c->board->gmd0); 1706 outb (GMD1(c->board->port), c->board->gmd1 | GMD1_NCS0 | GMD1_NCS1); 1707 } 1708 1709 unsigned char ctg_inx (ct_chan_t *c, unsigned char reg) 1710 { 1711 port_t port = GMD0(c->board->port); 1712 port_t data = GLDR(c->board->port); 1713 unsigned char val = 0, mask = c->num ? GLDR_C1 : GLDR_C0; 1714 int i; 1715 1716 outb (GMD1(c->board->port), c->board->gmd1 | GMD1_NCS0 | GMD1_NCS1); 1717 outb (GMD1(c->board->port), c->board->gmd1 | 1718 (c->num ? GMD1_NCS0 : GMD1_NCS1)); 1719 ctg_output (port, (reg << 1) | LX_READ, c->board->gmd0); 1720 for (i=0; i<8; ++i) { 1721 outb (port, c->board->gmd0 | GMD0_SCLK); 1722 if (inb (data) & mask) 1723 val |= 1 << i; 1724 outb (port, c->board->gmd0); 1725 } 1726 outb (GMD1(c->board->port), c->board->gmd1 | GMD1_NCS0 | GMD1_NCS1); 1727 return val; 1728 } 1729 1730 /* 1731 * Adapter options 1732 */ 1733 ct_board_opt_t ct_board_opt_dflt = { 1734 0, /* board control register 2 */ 1735 { /* DMA priority control register */ 1736 PCR_PRIO_ROTATE, 1737 0, /* all channels share the the bus hold */ 1738 0, /* hold the bus until all transfers done */ 1739 }, 1740 CFG_A, /* E1/G.703 config: two independent channels */ 1741 GCLK_INT, /* E1/G.703 chan 0 internal tx clock source */ 1742 GCLK_INT, /* E1/G.703 chan 1 internal tx clock source */ 1743 ~0UL << 1, /* E1 channel 0 timeslots 1..31 */ 1744 ~0UL << 1, /* E1 channel 1 timeslots 1..31 */ 1745 0, /* no E1 subchannel timeslots */ 1746 }; 1747 1748 /* 1749 * Mode-independent channel options 1750 */ 1751 ct_chan_opt_t ct_chan_opt_dflt = { 1752 { /* mode register 2 */ 1753 MD2_FDX, /* full duplex communication */ 1754 0, /* empty ADPLL clock rate */ 1755 MD2_ENCOD_NRZ, /* NRZ encoding */ 1756 }, 1757 /* DMA mode FIFO marks */ 1758 15, 24, 30, /* rx ready, tx empty, tx full */ 1759 /* port i/o mode FIFO marks */ 1760 15, 16, 30, /* rx ready, tx empty, tx full */ 1761 }; 1762 1763 /* 1764 * Default HDLC options 1765 */ 1766 ct_opt_hdlc_t ct_opt_hdlc_dflt = { 1767 { /* mode register 0 */ 1768 1, /* CRC preset to all ones (V.41) */ 1769 1, /* CRC-CCITT */ 1770 1, /* enable CRC */ 1771 0, /* disable automatic CTS/DCD */ 1772 MD0_MODE_HDLC, /* HDLC mode */ 1773 }, 1774 { /* mode register 1 */ 1775 MD1_ADDR_NOCHK, /* do not check address field */ 1776 }, 1777 CTL_IDLE_PTRN | CTL_UDRN_ABORT | CTL_RTS_INV, /* control register */ 1778 0, 0, /* empty sync/address registers 0,1 */ 1779 CLK_LINE, /* receive clock source: RXC line input */ 1780 CLK_LINE, /* transmit clock source: TXC line input */ 1781 }; 1782 1783 /* 1784 * Default E1/G.703 options 1785 */ 1786 ct_opt_g703_t ct_opt_g703_dflt = { 1787 1, /* HDB3 enable */ 1788 0, /* precoder disable */ 1789 GTEST_DIS, /* test disabled, normal operation */ 1790 0, /* CRC4 disable */ 1791 0, /* CCS signaling */ 1792 0, /* low gain */ 1793 0, /* no raw mode */ 1794 0, /* no PCM2 precoder compatibility */ 1795 2048, /* data rate 2048 kbit/sec */ 1796 };
Cache object: 421fb48866e6bc34fe59eeaf1e96eff1
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