Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/cx/cxddk.h
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1 /*- 2 * Defines for Cronyx-Sigma adapter driver. 3 * 4 * Copyright (C) 1994-2001 Cronyx Engineering. 5 * Author: Serge Vakulenko, <vak@cronyx.ru> 6 * 7 * Copyright (C) 1998-2003 Cronyx Engineering. 8 * Author: Roman Kurakin, <rik@cronyx.ru> 9 * 10 * This software is distributed with NO WARRANTIES, not even the implied 11 * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 12 * 13 * Authors grant any other persons or organisations permission to use 14 * or modify this software as long as this message is kept with the software, 15 * all derivative works or modified versions. 16 * 17 * Cronyx Id: cxddk.h,v 1.1.2.1 2003/11/12 17:13:41 rik Exp $ 18 * $FreeBSD: releng/9.0/sys/dev/cx/cxddk.h 180132 2008-06-30 21:18:27Z rik $ 19 */ 20 21 #ifndef port_t 22 # ifdef _M_ALPHA /* port address on Alpha under */ 23 # define port_t unsigned long /* Windows NT is 32 bit long */ 24 # else 25 # define port_t unsigned short /* all other architectures */ 26 # endif /* have 16-bit port addresses */ 27 #endif 28 29 #define NBRD 3 /* the max number of installed boards */ 30 #define NPORT 32 /* the number of i/o ports per board */ 31 #define DMABUFSZ 1600 32 33 /* 34 * Asynchronous channel mode ------------------------------------------------- 35 */ 36 37 /* Parity */ 38 #define PAR_EVEN 0 /* even parity */ 39 #define PAR_ODD 1 /* odd parity */ 40 41 /* Parity mode */ 42 #define PARM_NOPAR 0 /* no parity */ 43 #define PARM_FORCE 1 /* force parity (odd = force 1, even = 0) */ 44 #define PARM_NORMAL 2 /* normal parity */ 45 46 /* Flow control transparency mode */ 47 #define FLOWCC_PASS 0 /* pass flow ctl chars as exceptions */ 48 #define FLOWCC_NOTPASS 1 /* don't pass flow ctl chars to the host */ 49 50 /* Stop bit length */ 51 #define STOPB_1 2 /* 1 stop bit */ 52 #define STOPB_15 3 /* 1.5 stop bits */ 53 #define STOPB_2 4 /* 2 stop bits */ 54 55 /* Action on break condition */ 56 #define BRK_INTR 0 /* generate an exception interrupt */ 57 #define BRK_NULL 1 /* translate to a NULL character */ 58 #define BRK_RESERVED 2 /* reserved */ 59 #define BRK_DISCARD 3 /* discard character */ 60 61 /* Parity/framing error actions */ 62 #define PERR_INTR 0 /* generate an exception interrupt */ 63 #define PERR_NULL 1 /* translate to a NULL character */ 64 #define PERR_IGNORE 2 /* ignore error; char passed as good data */ 65 #define PERR_DISCARD 3 /* discard error character */ 66 #define PERR_FFNULL 5 /* translate to FF NULL char */ 67 68 typedef struct { /* async channel option register 1 */ 69 unsigned charlen : 4; /* character length, 5..8 */ 70 unsigned ignpar : 1; /* ignore parity */ 71 unsigned parmode : 2; /* parity mode */ 72 unsigned parity : 1; /* parity */ 73 } cx_cor1_async_t; 74 75 typedef struct { /* async channel option register 2 */ 76 unsigned dsrae : 1; /* DSR automatic enable */ 77 unsigned ctsae : 1; /* CTS automatic enable */ 78 unsigned rtsao : 1; /* RTS automatic output enable */ 79 unsigned rlm : 1; /* remote loopback mode enable */ 80 unsigned zero : 1; 81 unsigned etc : 1; /* embedded transmitter cmd enable */ 82 unsigned ixon : 1; /* in-band XON/XOFF enable */ 83 unsigned ixany : 1; /* XON on any character */ 84 } cx_cor2_async_t; 85 86 typedef struct { /* async channel option register 3 */ 87 unsigned stopb : 3; /* stop bit length */ 88 unsigned zero : 1; 89 unsigned scde : 1; /* special char detection enable */ 90 unsigned flowct : 1; /* flow control transparency mode */ 91 unsigned rngde : 1; /* range detect enable */ 92 unsigned escde : 1; /* extended spec. char detect enable */ 93 } cx_cor3_async_t; 94 95 typedef struct { /* async channel option register 6 */ 96 unsigned parerr : 3; /* parity/framing error actions */ 97 unsigned brk : 2; /* action on break condition */ 98 unsigned inlcr : 1; /* translate NL to CR on input */ 99 unsigned icrnl : 1; /* translate CR to NL on input */ 100 unsigned igncr : 1; /* discard CR on input */ 101 } cx_cor6_async_t; 102 103 typedef struct { /* async channel option register 7 */ 104 unsigned ocrnl : 1; /* translate CR to NL on output */ 105 unsigned onlcr : 1; /* translate NL to CR on output */ 106 unsigned zero : 3; 107 unsigned fcerr : 1; /* process flow ctl err chars enable */ 108 unsigned lnext : 1; /* LNext option enable */ 109 unsigned istrip : 1; /* strip 8-bit on input */ 110 } cx_cor7_async_t; 111 112 typedef struct { /* async channel options */ 113 cx_cor1_async_t cor1; /* channel option register 1 */ 114 cx_cor2_async_t cor2; /* channel option register 2 */ 115 cx_cor3_async_t cor3; /* option register 3 */ 116 cx_cor6_async_t cor6; /* channel option register 6 */ 117 cx_cor7_async_t cor7; /* channel option register 7 */ 118 unsigned char schr1; /* special character register 1 (XON) */ 119 unsigned char schr2; /* special character register 2 (XOFF) */ 120 unsigned char schr3; /* special character register 3 */ 121 unsigned char schr4; /* special character register 4 */ 122 unsigned char scrl; /* special character range low */ 123 unsigned char scrh; /* special character range high */ 124 unsigned char lnxt; /* LNext character */ 125 } cx_opt_async_t; 126 127 /* 128 * HDLC channel mode --------------------------------------------------------- 129 */ 130 /* Address field length option */ 131 #define AFLO_1OCT 0 /* address field is 1 octet in length */ 132 #define AFLO_2OCT 1 /* address field is 2 octet in length */ 133 134 /* Clear detect for X.21 data transfer phase */ 135 #define CLRDET_DISABLE 0 /* clear detect disabled */ 136 #define CLRDET_ENABLE 1 /* clear detect enabled */ 137 138 /* Addressing mode */ 139 #define ADMODE_NOADDR 0 /* no address */ 140 #define ADMODE_4_1 1 /* 4 * 1 byte */ 141 #define ADMODE_2_2 2 /* 2 * 2 byte */ 142 143 /* FCS append */ 144 #define FCS_NOTPASS 0 /* receive CRC is not passed to the host */ 145 #define FCS_PASS 1 /* receive CRC is passed to the host */ 146 147 /* CRC modes */ 148 #define CRC_INVERT 0 /* CRC is transmitted inverted (CRC V.41) */ 149 #define CRC_DONT_INVERT 1 /* CRC is not transmitted inverted (CRC-16) */ 150 151 /* Send sync pattern */ 152 #define SYNC_00 0 /* send 00h as pad char (NRZI encoding) */ 153 #define SYNC_AA 1 /* send AAh (Manchester/NRZ encoding) */ 154 155 /* FCS preset */ 156 #define FCSP_ONES 0 /* FCS is preset to all ones (CRC V.41) */ 157 #define FCSP_ZEROS 1 /* FCS is preset to all zeros (CRC-16) */ 158 159 /* idle mode */ 160 #define IDLE_FLAG 0 /* idle in flag */ 161 #define IDLE_MARK 1 /* idle in mark */ 162 163 /* CRC polynomial select */ 164 #define POLY_V41 0 /* x^16+x^12+x^5+1 (HDLC, preset to 1) */ 165 #define POLY_16 1 /* x^16+x^15+x^2+1 (bisync, preset to 0) */ 166 167 typedef struct { /* hdlc channel option register 1 */ 168 unsigned ifflags : 4; /* number of inter-frame flags sent */ 169 unsigned admode : 2; /* addressing mode */ 170 unsigned clrdet : 1; /* clear detect for X.21 data transfer phase */ 171 unsigned aflo : 1; /* address field length option */ 172 } cx_cor1_hdlc_t; 173 174 typedef struct { /* hdlc channel option register 2 */ 175 unsigned dsrae : 1; /* DSR automatic enable */ 176 unsigned ctsae : 1; /* CTS automatic enable */ 177 unsigned rtsao : 1; /* RTS automatic output enable */ 178 unsigned zero1 : 1; 179 unsigned crcninv : 1; /* CRC invertion option */ 180 unsigned zero2 : 1; 181 unsigned fcsapd : 1; /* FCS append */ 182 unsigned zero3 : 1; 183 } cx_cor2_hdlc_t; 184 185 typedef struct { /* hdlc channel option register 3 */ 186 unsigned padcnt : 3; /* pad character count */ 187 unsigned idle : 1; /* idle mode */ 188 unsigned nofcs : 1; /* FCS disable */ 189 unsigned fcspre : 1; /* FCS preset */ 190 unsigned syncpat : 1; /* send sync pattern */ 191 unsigned sndpad : 1; /* send pad characters before flag enable */ 192 } cx_cor3_hdlc_t; 193 194 typedef struct { /* hdlc channel options */ 195 cx_cor1_hdlc_t cor1; /* hdlc channel option register 1 */ 196 cx_cor2_hdlc_t cor2; /* hdlc channel option register 2 */ 197 cx_cor3_hdlc_t cor3; /* hdlc channel option register 3 */ 198 unsigned char rfar1; /* receive frame address register 1 */ 199 unsigned char rfar2; /* receive frame address register 2 */ 200 unsigned char rfar3; /* receive frame address register 3 */ 201 unsigned char rfar4; /* receive frame address register 4 */ 202 unsigned char cpsr; /* CRC polynomial select */ 203 } cx_opt_hdlc_t; 204 205 /* 206 * CD2400 channel state structure -------------------------------------------- 207 */ 208 209 /* Signal encoding */ 210 #define ENCOD_NRZ 0 /* NRZ mode */ 211 #define ENCOD_NRZI 1 /* NRZI mode */ 212 #define ENCOD_MANCHESTER 2 /* Manchester mode */ 213 214 /* Clock source */ 215 #define CLK_0 0 /* clock 0 */ 216 #define CLK_1 1 /* clock 1 */ 217 #define CLK_2 2 /* clock 2 */ 218 #define CLK_3 3 /* clock 3 */ 219 #define CLK_4 4 /* clock 4 */ 220 #define CLK_EXT 6 /* external clock */ 221 #define CLK_RCV 7 /* receive clock */ 222 223 /* Board type */ 224 #define B_SIGMA_XXX 0 /* old Sigmas */ 225 #define B_SIGMA_2X 1 /* Sigma-22 */ 226 #define B_SIGMA_800 2 /* Sigma-800 */ 227 228 /* Channel type */ 229 #define T_NONE 0 /* no channel */ 230 #define T_ASYNC 1 /* pure asynchronous RS-232 channel */ 231 #define T_SYNC_RS232 2 /* pure synchronous RS-232 channel */ 232 #define T_SYNC_V35 3 /* pure synchronous V.35 channel */ 233 #define T_SYNC_RS449 4 /* pure synchronous RS-449 channel */ 234 #define T_UNIV_RS232 5 /* sync/async RS-232 channel */ 235 #define T_UNIV_RS449 6 /* sync/async RS-232/RS-449 channel */ 236 #define T_UNIV_V35 7 /* sync/async RS-232/V.35 channel */ 237 #define T_UNIV 8 /* sync/async, unknown interface */ 238 239 #define M_ASYNC 0 /* asynchronous mode */ 240 #define M_HDLC 1 /* bit-sync mode (HDLC) */ 241 242 typedef struct { /* channel option register 4 */ 243 unsigned thr : 4; /* FIFO threshold */ 244 unsigned zero : 1; 245 unsigned cts_zd : 1; /* detect 1 to 0 transition on the CTS */ 246 unsigned cd_zd : 1; /* detect 1 to 0 transition on the CD */ 247 unsigned dsr_zd : 1; /* detect 1 to 0 transition on the DSR */ 248 } cx_cor4_t; 249 250 typedef struct { /* channel option register 5 */ 251 unsigned rx_thr : 4; /* receive flow control FIFO threshold */ 252 unsigned zero : 1; 253 unsigned cts_od : 1; /* detect 0 to 1 transition on the CTS */ 254 unsigned cd_od : 1; /* detect 0 to 1 transition on the CD */ 255 unsigned dsr_od : 1; /* detect 0 to 1 transition on the DSR */ 256 } cx_cor5_t; 257 258 typedef struct { /* receive clock option register */ 259 unsigned clk : 3; /* receive clock source */ 260 unsigned encod : 2; /* signal encoding NRZ/NRZI/Manchester */ 261 unsigned dpll : 1; /* DPLL enable */ 262 unsigned zero : 1; 263 unsigned tlval : 1; /* transmit line value */ 264 } cx_rcor_t; 265 266 typedef struct { /* transmit clock option register */ 267 unsigned zero1 : 1; 268 unsigned llm : 1; /* local loopback mode */ 269 unsigned zero2 : 1; 270 unsigned ext1x : 1; /* external 1x clock mode */ 271 unsigned zero3 : 1; 272 unsigned clk : 3; /* transmit clock source */ 273 } cx_tcor_t; 274 275 typedef struct { 276 cx_cor4_t cor4; /* channel option register 4 */ 277 cx_cor5_t cor5; /* channel option register 5 */ 278 cx_rcor_t rcor; /* receive clock option register */ 279 cx_tcor_t tcor; /* transmit clock option register */ 280 } cx_chan_opt_t; 281 282 typedef enum { /* line break mode */ 283 BRK_IDLE, /* normal line mode */ 284 BRK_SEND, /* start sending break */ 285 BRK_STOP, /* stop sending break */ 286 } cx_break_t; 287 288 #define BUS_NORMAL 0 /* normal bus timing */ 289 #define BUS_FAST 1 /* fast bus timing (Sigma-22 and -800) */ 290 #define BUS_FAST2 2 /* fast bus timing (Sigma-800) */ 291 #define BUS_FAST3 3 /* fast bus timing (Sigma-800) */ 292 293 typedef struct { /* board options */ 294 unsigned char fast; /* bus master timing (Sigma-22 and -800) */ 295 } cx_board_opt_t; 296 297 #define NCHIP 4 /* the number of controllers per board */ 298 #define NCHAN 16 /* the number of channels on the board */ 299 300 typedef struct { 301 unsigned char tbuffer [2] [DMABUFSZ]; 302 unsigned char rbuffer [2] [DMABUFSZ]; 303 } cx_buf_t; 304 305 typedef struct _cx_chan_t { 306 struct _cx_board_t *board; /* board pointer */ 307 unsigned char type; /* channel type */ 308 unsigned char num; /* channel number, 0..15 */ 309 port_t port; /* base port address */ 310 unsigned long oscfreq; /* oscillator frequency in Hz */ 311 unsigned long rxbaud; /* receiver speed */ 312 unsigned long txbaud; /* transmitter speed */ 313 unsigned char mode; /* channel mode */ 314 cx_chan_opt_t opt; /* common channel options */ 315 cx_opt_async_t aopt; /* async mode options */ 316 cx_opt_hdlc_t hopt; /* hdlc mode options */ 317 unsigned char *arbuf; /* receiver A dma buffer */ 318 unsigned char *brbuf; /* receiver B dma buffer */ 319 unsigned char *atbuf; /* transmitter A dma buffer */ 320 unsigned char *btbuf; /* transmitter B dma buffer */ 321 unsigned long arphys; /* receiver A phys address */ 322 unsigned long brphys; /* receiver B phys address */ 323 unsigned long atphys; /* transmitter A phys address */ 324 unsigned long btphys; /* transmitter B phys address */ 325 unsigned char dtr; /* DTR signal value */ 326 unsigned char rts; /* RTS signal value */ 327 328 unsigned long rintr; /* receive interrupts */ 329 unsigned long tintr; /* transmit interrupts */ 330 unsigned long mintr; /* modem interrupts */ 331 unsigned long ibytes; /* input bytes */ 332 unsigned long ipkts; /* input packets */ 333 unsigned long ierrs; /* input errors */ 334 unsigned long obytes; /* output bytes */ 335 unsigned long opkts; /* output packets */ 336 unsigned long oerrs; /* output errors */ 337 338 void *sys; 339 int debug; 340 int debug_shadow; 341 void *attach [2]; 342 char *received_data; 343 int received_len; 344 int overflow; 345 346 void (*call_on_rx) (struct _cx_chan_t*, char*, int); 347 void (*call_on_tx) (struct _cx_chan_t*, void*, int); 348 void (*call_on_msig) (struct _cx_chan_t*); 349 void (*call_on_err) (struct _cx_chan_t*, int); 350 351 } cx_chan_t; 352 353 typedef struct _cx_board_t { 354 unsigned char type; /* board type */ 355 unsigned char num; /* board number, 0..2 */ 356 port_t port; /* base board port, 0..3f0 */ 357 unsigned char irq; /* irq {3 5 7 10 11 12 15} */ 358 unsigned char dma; /* DMA request {5 6 7} */ 359 char name[16]; /* board version name */ 360 unsigned char nuniv; /* number of universal channels */ 361 unsigned char nsync; /* number of sync. channels */ 362 unsigned char nasync; /* number of async. channels */ 363 unsigned char if0type; /* chan0 interface RS-232/RS-449/V.35 */ 364 unsigned char if8type; /* chan8 interface RS-232/RS-449/V.35 */ 365 unsigned short bcr0; /* BCR0 image */ 366 unsigned short bcr0b; /* BCR0b image */ 367 unsigned short bcr1; /* BCR1 image */ 368 unsigned short bcr1b; /* BCR1b image */ 369 cx_board_opt_t opt; /* board options */ 370 cx_chan_t chan[NCHAN]; /* channel structures */ 371 void *sys; 372 } cx_board_t; 373 374 extern long cx_rxbaud, cx_txbaud; 375 extern int cx_univ_mode, cx_sync_mode, cx_iftype; 376 377 extern cx_chan_opt_t chan_opt_dflt; /* default mode-independent options */ 378 extern cx_opt_async_t opt_async_dflt; /* default async options */ 379 extern cx_opt_hdlc_t opt_hdlc_dflt; /* default hdlc options */ 380 extern cx_board_opt_t board_opt_dflt; /* default board options */ 381 382 struct _cr_dat_tst; 383 int cx_probe_board (port_t port, int irq, int dma); 384 void cx_init (cx_board_t *b, int num, port_t port, int irq, int dma); 385 void cx_init_board (cx_board_t *b, int num, port_t port, int irq, int dma, 386 int chain, int rev, int osc, int mod, int rev2, int osc2, int mod2); 387 void cx_init_2x (cx_board_t *b, int num, port_t port, int irq, int dma, 388 int rev, int osc); 389 void cx_init_800 (cx_board_t *b, int num, port_t port, int irq, int dma, 390 int chain); 391 int cx_download (port_t port, const unsigned char *firmware, long bits, 392 const struct _cr_dat_tst *tst); 393 int cx_setup_board (cx_board_t *b, const unsigned char *firmware, 394 long bits, const struct _cr_dat_tst *tst); 395 void cx_setup_chan (cx_chan_t *c); 396 void cx_update_chan (cx_chan_t *c); 397 void cx_set_dtr (cx_chan_t *c, int on); 398 void cx_set_rts (cx_chan_t *c, int on); 399 void cx_led (cx_board_t *b, int on); 400 void cx_cmd (port_t base, int cmd); 401 void cx_disable_dma (cx_board_t *b); 402 void cx_reinit_board (cx_board_t *b); 403 int cx_get_dsr (cx_chan_t *c); 404 int cx_get_cts (cx_chan_t *c); 405 int cx_get_cd (cx_chan_t *c); 406 void cx_clock (long hz, long ba, int *clk, int *div); 407 408 /* DDK errors */ 409 #define CX_FRAME 1 410 #define CX_CRC 2 411 #define CX_OVERRUN 3 412 #define CX_OVERFLOW 4 413 #define CX_UNDERRUN 5 414 #define CX_BREAK 6 415 416 /* clock sources */ 417 #define CX_CLK_INT 0 418 #define CX_CLK_EXT 6 419 #define CX_CLK_RCV 7 420 #define CX_CLK_DPLL 8 421 #define CX_CLK_DPLL_EXT 14 422 423 /* functions dealing with interrupt vector in DOS */ 424 #if defined (MSDOS) || defined (__MSDOS__) 425 int ddk_int_alloc (int irq, void (*func)(), void *arg); 426 int ddk_int_restore (int irq); 427 #endif 428 429 int cx_probe_irq (cx_board_t *b, int irq); 430 void cx_int_handler (cx_board_t *b); 431 432 int cx_find (port_t *board_ports); 433 int cx_open_board (cx_board_t *b, int num, port_t port, int irq, int dma); 434 void cx_close_board (cx_board_t *b); 435 436 void cx_start_chan (cx_chan_t *c, cx_buf_t *cb, unsigned long phys); 437 438 /* 439 Set port type for old models of Sigma 440 */ 441 void cx_set_port (cx_chan_t *c, int iftype); 442 443 /* 444 Get port type for old models of Sigma 445 -1 Fixed port type or auto detect 446 0 RS232 447 1 V35 448 2 RS449 449 */ 450 int cx_get_port (cx_chan_t *c); 451 452 void cx_enable_receive (cx_chan_t *c, int on); 453 void cx_enable_transmit (cx_chan_t *c, int on); 454 int cx_receive_enabled (cx_chan_t *c); 455 int cx_transmit_enabled (cx_chan_t *c); 456 457 void cx_set_baud (cx_chan_t *, unsigned long baud); 458 int cx_set_mode (cx_chan_t *c, int mode); 459 void cx_set_loop (cx_chan_t *c, int on); 460 void cx_set_nrzi (cx_chan_t *c, int nrzi); 461 void cx_set_dpll (cx_chan_t *c, int on); 462 463 unsigned long cx_get_baud (cx_chan_t *c); 464 int cx_get_loop (cx_chan_t *c); 465 int cx_get_nrzi (cx_chan_t *c); 466 int cx_get_dpll (cx_chan_t *c); 467 468 int cx_send_packet (cx_chan_t *c, char *data, int len, void *attachment); 469 int cx_buf_free (cx_chan_t *c); 470 471 void cx_register_transmit (cx_chan_t *c, 472 void (*func) (cx_chan_t *c, void *attachment, int len)); 473 void cx_register_receive (cx_chan_t *c, 474 void (*func) (cx_chan_t *c, char *data, int len)); 475 void cx_register_modem (cx_chan_t *c, void (*func) (cx_chan_t *c)); 476 void cx_register_error (cx_chan_t *c, void (*func) (cx_chan_t *c, int data)); 477 void cx_intr_off (cx_board_t *b); 478 void cx_intr_on (cx_board_t *b); 479 int cx_checkintr (cx_board_t *b); 480 481 /* Async functions */ 482 void cx_transmitter_ctl (cx_chan_t *c, int start); 483 void cx_flush_transmit (cx_chan_t *c); 484 void cx_xflow_ctl (cx_chan_t *c, int on); 485 void cx_send_break (cx_chan_t *c, int msec); 486 void cx_set_async_param (cx_chan_t *c, int baud, int bits, int parity, 487 int stop2, int ignpar, int rtscts, 488 int ixon, int ixany, int symstart, int symstop);
Cache object: 1b6a19a515523145e1e004ea49ca2483
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