1 /**************************************************************************
2
3 Copyright (c) 2007-2009, Chelsio Inc.
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
15
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
27
28 $FreeBSD: releng/8.0/sys/dev/cxgb/common/cxgb_common.h 192540 2009-05-21 15:08:03Z gnn $
29
30 ***************************************************************************/
31 #ifndef __CHELSIO_COMMON_H
32 #define __CHELSIO_COMMON_H
33
34 #include <cxgb_osdep.h>
35
36 enum {
37 MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */
38 EEPROMSIZE = 8192, /* Serial EEPROM size */
39 SERNUM_LEN = 16, /* Serial # length */
40 ECNUM_LEN = 16, /* EC # length */
41 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
42 TCB_SIZE = 128, /* TCB size */
43 NMTUS = 16, /* size of MTU table */
44 NCCTRL_WIN = 32, /* # of congestion control windows */
45 NTX_SCHED = 8, /* # of HW Tx scheduling queues */
46 PROTO_SRAM_LINES = 128, /* size of protocol sram */
47 EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */
48 };
49
50 #define MAX_RX_COALESCING_LEN 12288U
51
52 enum {
53 PAUSE_RX = 1 << 0,
54 PAUSE_TX = 1 << 1,
55 PAUSE_AUTONEG = 1 << 2
56 };
57
58 enum {
59 SUPPORTED_IRQ = 1 << 24
60 };
61
62 enum { /* adapter interrupt-maintained statistics */
63 STAT_ULP_CH0_PBL_OOB,
64 STAT_ULP_CH1_PBL_OOB,
65 STAT_PCI_CORR_ECC,
66
67 IRQ_NUM_STATS /* keep last */
68 };
69
70 enum {
71 TP_VERSION_MAJOR = 1,
72 TP_VERSION_MINOR = 1,
73 TP_VERSION_MICRO = 0
74 };
75
76 #define S_TP_VERSION_MAJOR 16
77 #define M_TP_VERSION_MAJOR 0xFF
78 #define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR)
79 #define G_TP_VERSION_MAJOR(x) \
80 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
81
82 #define S_TP_VERSION_MINOR 8
83 #define M_TP_VERSION_MINOR 0xFF
84 #define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR)
85 #define G_TP_VERSION_MINOR(x) \
86 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
87
88 #define S_TP_VERSION_MICRO 0
89 #define M_TP_VERSION_MICRO 0xFF
90 #define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO)
91 #define G_TP_VERSION_MICRO(x) \
92 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
93
94 enum {
95 FW_VERSION_MAJOR = 7,
96 FW_VERSION_MINOR = 1,
97 FW_VERSION_MICRO = 0
98 };
99
100 enum {
101 LA_CTRL = 0x80,
102 LA_DATA = 0x84,
103 LA_ENTRIES = 512
104 };
105
106 enum {
107 IOQ_ENTRIES = 7
108 };
109
110 enum {
111 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
112 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
113 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
114 };
115
116 enum sge_context_type { /* SGE egress context types */
117 SGE_CNTXT_RDMA = 0,
118 SGE_CNTXT_ETH = 2,
119 SGE_CNTXT_OFLD = 4,
120 SGE_CNTXT_CTRL = 5
121 };
122
123 enum {
124 AN_PKT_SIZE = 32, /* async notification packet size */
125 IMMED_PKT_SIZE = 48 /* packet size for immediate data */
126 };
127
128 struct sg_ent { /* SGE scatter/gather entry */
129 __be32 len[2];
130 __be64 addr[2];
131 };
132
133 #ifndef SGE_NUM_GENBITS
134 /* Must be 1 or 2 */
135 # define SGE_NUM_GENBITS 2
136 #endif
137
138 #define TX_DESC_FLITS 16U
139 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
140
141 #define MAX_PHYINTRS 4
142
143 struct cphy;
144
145 struct mdio_ops {
146 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
147 int reg_addr, unsigned int *val);
148 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
149 int reg_addr, unsigned int val);
150 };
151
152 struct adapter_info {
153 unsigned char nports0; /* # of ports on channel 0 */
154 unsigned char nports1; /* # of ports on channel 1 */
155 unsigned char phy_base_addr; /* MDIO PHY base address */
156 unsigned int gpio_out; /* GPIO output settings */
157 unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */
158 unsigned long caps; /* adapter capabilities */
159 const struct mdio_ops *mdio_ops; /* MDIO operations */
160 const char *desc; /* product description */
161 };
162
163 struct mc5_stats {
164 unsigned long parity_err;
165 unsigned long active_rgn_full;
166 unsigned long nfa_srch_err;
167 unsigned long unknown_cmd;
168 unsigned long reqq_parity_err;
169 unsigned long dispq_parity_err;
170 unsigned long del_act_empty;
171 };
172
173 struct mc7_stats {
174 unsigned long corr_err;
175 unsigned long uncorr_err;
176 unsigned long parity_err;
177 unsigned long addr_err;
178 };
179
180 struct mac_stats {
181 u64 tx_octets; /* total # of octets in good frames */
182 u64 tx_octets_bad; /* total # of octets in error frames */
183 u64 tx_frames; /* all good frames */
184 u64 tx_mcast_frames; /* good multicast frames */
185 u64 tx_bcast_frames; /* good broadcast frames */
186 u64 tx_pause; /* # of transmitted pause frames */
187 u64 tx_deferred; /* frames with deferred transmissions */
188 u64 tx_late_collisions; /* # of late collisions */
189 u64 tx_total_collisions; /* # of total collisions */
190 u64 tx_excess_collisions; /* frame errors from excessive collissions */
191 u64 tx_underrun; /* # of Tx FIFO underruns */
192 u64 tx_len_errs; /* # of Tx length errors */
193 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
194 u64 tx_excess_deferral; /* # of frames with excessive deferral */
195 u64 tx_fcs_errs; /* # of frames with bad FCS */
196
197 u64 tx_frames_64; /* # of Tx frames in a particular range */
198 u64 tx_frames_65_127;
199 u64 tx_frames_128_255;
200 u64 tx_frames_256_511;
201 u64 tx_frames_512_1023;
202 u64 tx_frames_1024_1518;
203 u64 tx_frames_1519_max;
204
205 u64 rx_octets; /* total # of octets in good frames */
206 u64 rx_octets_bad; /* total # of octets in error frames */
207 u64 rx_frames; /* all good frames */
208 u64 rx_mcast_frames; /* good multicast frames */
209 u64 rx_bcast_frames; /* good broadcast frames */
210 u64 rx_pause; /* # of received pause frames */
211 u64 rx_fcs_errs; /* # of received frames with bad FCS */
212 u64 rx_align_errs; /* alignment errors */
213 u64 rx_symbol_errs; /* symbol errors */
214 u64 rx_data_errs; /* data errors */
215 u64 rx_sequence_errs; /* sequence errors */
216 u64 rx_runt; /* # of runt frames */
217 u64 rx_jabber; /* # of jabber frames */
218 u64 rx_short; /* # of short frames */
219 u64 rx_too_long; /* # of oversized frames */
220 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
221
222 u64 rx_frames_64; /* # of Rx frames in a particular range */
223 u64 rx_frames_65_127;
224 u64 rx_frames_128_255;
225 u64 rx_frames_256_511;
226 u64 rx_frames_512_1023;
227 u64 rx_frames_1024_1518;
228 u64 rx_frames_1519_max;
229
230 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */
231
232 unsigned long tx_fifo_parity_err;
233 unsigned long rx_fifo_parity_err;
234 unsigned long tx_fifo_urun;
235 unsigned long rx_fifo_ovfl;
236 unsigned long serdes_signal_loss;
237 unsigned long xaui_pcs_ctc_err;
238 unsigned long xaui_pcs_align_change;
239
240 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
241 unsigned long num_resets; /* # times reset due to stuck TX */
242
243 unsigned long link_faults; /* # detected link faults */
244 };
245
246 struct tp_mib_stats {
247 u32 ipInReceive_hi;
248 u32 ipInReceive_lo;
249 u32 ipInHdrErrors_hi;
250 u32 ipInHdrErrors_lo;
251 u32 ipInAddrErrors_hi;
252 u32 ipInAddrErrors_lo;
253 u32 ipInUnknownProtos_hi;
254 u32 ipInUnknownProtos_lo;
255 u32 ipInDiscards_hi;
256 u32 ipInDiscards_lo;
257 u32 ipInDelivers_hi;
258 u32 ipInDelivers_lo;
259 u32 ipOutRequests_hi;
260 u32 ipOutRequests_lo;
261 u32 ipOutDiscards_hi;
262 u32 ipOutDiscards_lo;
263 u32 ipOutNoRoutes_hi;
264 u32 ipOutNoRoutes_lo;
265 u32 ipReasmTimeout;
266 u32 ipReasmReqds;
267 u32 ipReasmOKs;
268 u32 ipReasmFails;
269
270 u32 reserved[8];
271
272 u32 tcpActiveOpens;
273 u32 tcpPassiveOpens;
274 u32 tcpAttemptFails;
275 u32 tcpEstabResets;
276 u32 tcpOutRsts;
277 u32 tcpCurrEstab;
278 u32 tcpInSegs_hi;
279 u32 tcpInSegs_lo;
280 u32 tcpOutSegs_hi;
281 u32 tcpOutSegs_lo;
282 u32 tcpRetransSeg_hi;
283 u32 tcpRetransSeg_lo;
284 u32 tcpInErrs_hi;
285 u32 tcpInErrs_lo;
286 u32 tcpRtoMin;
287 u32 tcpRtoMax;
288 };
289
290 struct tp_params {
291 unsigned int nchan; /* # of channels */
292 unsigned int pmrx_size; /* total PMRX capacity */
293 unsigned int pmtx_size; /* total PMTX capacity */
294 unsigned int cm_size; /* total CM capacity */
295 unsigned int chan_rx_size; /* per channel Rx size */
296 unsigned int chan_tx_size; /* per channel Tx size */
297 unsigned int rx_pg_size; /* Rx page size */
298 unsigned int tx_pg_size; /* Tx page size */
299 unsigned int rx_num_pgs; /* # of Rx pages */
300 unsigned int tx_num_pgs; /* # of Tx pages */
301 unsigned int ntimer_qs; /* # of timer queues */
302 unsigned int tre; /* log2 of core clocks per TP tick */
303 unsigned int dack_re; /* DACK timer resolution */
304 };
305
306 struct qset_params { /* SGE queue set parameters */
307 unsigned int polling; /* polling/interrupt service for rspq */
308 unsigned int lro; /* large receive offload */
309 unsigned int coalesce_usecs; /* irq coalescing timer */
310 unsigned int rspq_size; /* # of entries in response queue */
311 unsigned int fl_size; /* # of entries in regular free list */
312 unsigned int jumbo_size; /* # of entries in jumbo free list */
313 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
314 unsigned int cong_thres; /* FL congestion threshold */
315 unsigned int vector; /* Interrupt (line or vector) number */
316 };
317
318 struct sge_params {
319 unsigned int max_pkt_size; /* max offload pkt size */
320 struct qset_params qset[SGE_QSETS];
321 };
322
323 struct mc5_params {
324 unsigned int mode; /* selects MC5 width */
325 unsigned int nservers; /* size of server region */
326 unsigned int nfilters; /* size of filter region */
327 unsigned int nroutes; /* size of routing region */
328 };
329
330 /* Default MC5 region sizes */
331 enum {
332 DEFAULT_NSERVERS = 512,
333 DEFAULT_NFILTERS = 128
334 };
335
336 /* MC5 modes, these must be non-0 */
337 enum {
338 MC5_MODE_144_BIT = 1,
339 MC5_MODE_72_BIT = 2
340 };
341
342 /* MC5 min active region size */
343 enum { MC5_MIN_TIDS = 16 };
344
345 struct vpd_params {
346 unsigned int cclk;
347 unsigned int mclk;
348 unsigned int uclk;
349 unsigned int mdc;
350 unsigned int mem_timing;
351 u8 sn[SERNUM_LEN + 1];
352 u8 ec[ECNUM_LEN + 1];
353 u8 eth_base[6];
354 u8 port_type[MAX_NPORTS];
355 unsigned short xauicfg[2];
356 };
357
358 struct generic_vpd {
359 u32 offset;
360 u32 len;
361 u8 *data;
362 };
363
364 enum { MAX_VPD_BYTES = 32000 };
365
366 struct pci_params {
367 unsigned int vpd_cap_addr;
368 unsigned int pcie_cap_addr;
369 unsigned short speed;
370 unsigned char width;
371 unsigned char variant;
372 };
373
374 enum {
375 PCI_VARIANT_PCI,
376 PCI_VARIANT_PCIX_MODE1_PARITY,
377 PCI_VARIANT_PCIX_MODE1_ECC,
378 PCI_VARIANT_PCIX_266_MODE2,
379 PCI_VARIANT_PCIE
380 };
381
382 struct adapter_params {
383 struct sge_params sge;
384 struct mc5_params mc5;
385 struct tp_params tp;
386 struct vpd_params vpd;
387 struct pci_params pci;
388
389 const struct adapter_info *info;
390
391 #ifdef CONFIG_CHELSIO_T3_CORE
392 unsigned short mtus[NMTUS];
393 unsigned short a_wnd[NCCTRL_WIN];
394 unsigned short b_wnd[NCCTRL_WIN];
395 #endif
396 unsigned int nports; /* # of ethernet ports */
397 unsigned int chan_map; /* bitmap of in-use Tx channels */
398 unsigned int stats_update_period; /* MAC stats accumulation period */
399 unsigned int linkpoll_period; /* link poll period in 0.1s */
400 unsigned int rev; /* chip revision */
401 unsigned int offload;
402 };
403
404 enum { /* chip revisions */
405 T3_REV_A = 0,
406 T3_REV_B = 2,
407 T3_REV_B2 = 3,
408 T3_REV_C = 4,
409 };
410
411 struct trace_params {
412 u32 sip;
413 u32 sip_mask;
414 u32 dip;
415 u32 dip_mask;
416 u16 sport;
417 u16 sport_mask;
418 u16 dport;
419 u16 dport_mask;
420 u32 vlan:12;
421 u32 vlan_mask:12;
422 u32 intf:4;
423 u32 intf_mask:4;
424 u8 proto;
425 u8 proto_mask;
426 };
427
428 struct link_config {
429 unsigned int supported; /* link capabilities */
430 unsigned int advertising; /* advertised capabilities */
431 unsigned short requested_speed; /* speed user has requested */
432 unsigned short speed; /* actual link speed */
433 unsigned char requested_duplex; /* duplex user has requested */
434 unsigned char duplex; /* actual link duplex */
435 unsigned char requested_fc; /* flow control user has requested */
436 unsigned char fc; /* actual link flow control */
437 unsigned char autoneg; /* autonegotiating? */
438 unsigned int link_ok; /* link up? */
439 };
440
441 #define SPEED_INVALID 0xffff
442 #define DUPLEX_INVALID 0xff
443
444 struct mc5 {
445 adapter_t *adapter;
446 unsigned int tcam_size;
447 unsigned char part_type;
448 unsigned char parity_enabled;
449 unsigned char mode;
450 struct mc5_stats stats;
451 };
452
453 static inline unsigned int t3_mc5_size(const struct mc5 *p)
454 {
455 return p->tcam_size;
456 }
457
458 struct mc7 {
459 adapter_t *adapter; /* backpointer to adapter */
460 unsigned int size; /* memory size in bytes */
461 unsigned int width; /* MC7 interface width */
462 unsigned int offset; /* register address offset for MC7 instance */
463 const char *name; /* name of MC7 instance */
464 struct mc7_stats stats; /* MC7 statistics */
465 };
466
467 static inline unsigned int t3_mc7_size(const struct mc7 *p)
468 {
469 return p->size;
470 }
471
472 struct cmac {
473 adapter_t *adapter;
474 unsigned int offset;
475 unsigned char nucast; /* # of address filters for unicast MACs */
476 unsigned char multiport; /* multiple ports connected to this MAC */
477 unsigned char ext_port; /* external MAC port */
478 unsigned char promisc_map; /* which external ports are promiscuous */
479 unsigned int tx_tcnt;
480 unsigned int tx_xcnt;
481 u64 tx_mcnt;
482 unsigned int rx_xcnt;
483 unsigned int rx_ocnt;
484 u64 rx_mcnt;
485 unsigned int toggle_cnt;
486 unsigned int txen;
487 u64 rx_pause;
488 struct mac_stats stats;
489 };
490
491 enum {
492 MAC_DIRECTION_RX = 1,
493 MAC_DIRECTION_TX = 2,
494 MAC_RXFIFO_SIZE = 32768
495 };
496
497 /* IEEE 802.3 specified MDIO devices */
498 enum {
499 MDIO_DEV_PMA_PMD = 1,
500 MDIO_DEV_WIS = 2,
501 MDIO_DEV_PCS = 3,
502 MDIO_DEV_XGXS = 4,
503 MDIO_DEV_ANEG = 7,
504 MDIO_DEV_VEND1 = 30,
505 MDIO_DEV_VEND2 = 31
506 };
507
508 /* LASI control and status registers */
509 enum {
510 RX_ALARM_CTRL = 0x9000,
511 TX_ALARM_CTRL = 0x9001,
512 LASI_CTRL = 0x9002,
513 RX_ALARM_STAT = 0x9003,
514 TX_ALARM_STAT = 0x9004,
515 LASI_STAT = 0x9005
516 };
517
518 /* PHY loopback direction */
519 enum {
520 PHY_LOOPBACK_TX = 1,
521 PHY_LOOPBACK_RX = 2
522 };
523
524 /* PHY interrupt types */
525 enum {
526 cphy_cause_link_change = 1,
527 cphy_cause_fifo_error = 2,
528 cphy_cause_module_change = 4,
529 };
530
531 /* PHY module types */
532 enum {
533 phy_modtype_none,
534 phy_modtype_sr,
535 phy_modtype_lr,
536 phy_modtype_lrm,
537 phy_modtype_twinax,
538 phy_modtype_twinax_long,
539 phy_modtype_unknown
540 };
541
542 /* PHY operations */
543 struct cphy_ops {
544 int (*reset)(struct cphy *phy, int wait);
545
546 int (*intr_enable)(struct cphy *phy);
547 int (*intr_disable)(struct cphy *phy);
548 int (*intr_clear)(struct cphy *phy);
549 int (*intr_handler)(struct cphy *phy);
550
551 int (*autoneg_enable)(struct cphy *phy);
552 int (*autoneg_restart)(struct cphy *phy);
553
554 int (*advertise)(struct cphy *phy, unsigned int advertise_map);
555 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
556 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
557 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
558 int *duplex, int *fc);
559 int (*power_down)(struct cphy *phy, int enable);
560 };
561
562 /* A PHY instance */
563 struct cphy {
564 u8 addr; /* PHY address */
565 u8 modtype; /* PHY module type */
566 short priv; /* scratch pad */
567 unsigned int caps; /* PHY capabilities */
568 adapter_t *adapter; /* associated adapter */
569 const char *desc; /* PHY description */
570 unsigned long fifo_errors; /* FIFO over/under-flows */
571 const struct cphy_ops *ops; /* PHY operations */
572 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
573 int reg_addr, unsigned int *val);
574 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
575 int reg_addr, unsigned int val);
576 };
577
578 /* Convenience MDIO read/write wrappers */
579 static inline int mdio_read(struct cphy *phy, int mmd, int reg,
580 unsigned int *valp)
581 {
582 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
583 }
584
585 static inline int mdio_write(struct cphy *phy, int mmd, int reg,
586 unsigned int val)
587 {
588 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
589 }
590
591 /* Convenience initializer */
592 static inline void cphy_init(struct cphy *phy, adapter_t *adapter,
593 int phy_addr, struct cphy_ops *phy_ops,
594 const struct mdio_ops *mdio_ops, unsigned int caps,
595 const char *desc)
596 {
597 phy->addr = (u8)phy_addr;
598 phy->caps = caps;
599 phy->adapter = adapter;
600 phy->desc = desc;
601 phy->ops = phy_ops;
602 if (mdio_ops) {
603 phy->mdio_read = mdio_ops->read;
604 phy->mdio_write = mdio_ops->write;
605 }
606 }
607
608 /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
609 #define MAC_STATS_ACCUM_SECS 180
610
611 /* The external MAC needs accumulation every 30 seconds */
612 #define VSC_STATS_ACCUM_SECS 30
613
614 #define XGM_REG(reg_addr, idx) \
615 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
616
617 struct addr_val_pair {
618 unsigned int reg_addr;
619 unsigned int val;
620 };
621
622 #include <cxgb_adapter.h>
623
624 #ifndef PCI_VENDOR_ID_CHELSIO
625 # define PCI_VENDOR_ID_CHELSIO 0x1425
626 #endif
627
628 #define for_each_port(adapter, iter) \
629 for (iter = 0; iter < (adapter)->params.nports; ++iter)
630
631 #define adapter_info(adap) ((adap)->params.info)
632
633 static inline int uses_xaui(const adapter_t *adap)
634 {
635 return adapter_info(adap)->caps & SUPPORTED_AUI;
636 }
637
638 static inline int is_10G(const adapter_t *adap)
639 {
640 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
641 }
642
643 static inline int is_offload(const adapter_t *adap)
644 {
645 #if defined(CONFIG_CHELSIO_T3_CORE)
646 return adap->params.offload;
647 #else
648 return 0;
649 #endif
650 }
651
652 static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
653 {
654 return adap->params.vpd.cclk / 1000;
655 }
656
657 static inline unsigned int dack_ticks_to_usec(const adapter_t *adap,
658 unsigned int ticks)
659 {
660 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
661 }
662
663 static inline unsigned int is_pcie(const adapter_t *adap)
664 {
665 return adap->params.pci.variant == PCI_VARIANT_PCIE;
666 }
667
668 void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val);
669 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n,
670 unsigned int offset);
671 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,
672 int attempts, int delay, u32 *valp);
673
674 static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask,
675 int polarity, int attempts, int delay)
676 {
677 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
678 delay, NULL);
679 }
680
681 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
682 unsigned int set);
683 int t3_phy_reset(struct cphy *phy, int mmd, int wait);
684 int t3_phy_advertise(struct cphy *phy, unsigned int advert);
685 int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert);
686 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
687 int t3_phy_lasi_intr_enable(struct cphy *phy);
688 int t3_phy_lasi_intr_disable(struct cphy *phy);
689 int t3_phy_lasi_intr_clear(struct cphy *phy);
690 int t3_phy_lasi_intr_handler(struct cphy *phy);
691
692 void t3_intr_enable(adapter_t *adapter);
693 void t3_intr_disable(adapter_t *adapter);
694 void t3_intr_clear(adapter_t *adapter);
695 void t3_xgm_intr_enable(adapter_t *adapter, int idx);
696 void t3_xgm_intr_disable(adapter_t *adapter, int idx);
697 void t3_port_intr_enable(adapter_t *adapter, int idx);
698 void t3_port_intr_disable(adapter_t *adapter, int idx);
699 void t3_port_intr_clear(adapter_t *adapter, int idx);
700 int t3_slow_intr_handler(adapter_t *adapter);
701 int t3_phy_intr_handler(adapter_t *adapter);
702
703 void t3_link_changed(adapter_t *adapter, int port_id);
704 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
705 const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
706 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
707 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
708 int t3_seeprom_wp(adapter_t *adapter, int enable);
709 int t3_get_vpd_len(adapter_t *adapter, struct generic_vpd *vpd);
710 int t3_read_vpd(adapter_t *adapter, struct generic_vpd *vpd);
711 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
712 u32 *data, int byte_oriented);
713 int t3_get_tp_version(adapter_t *adapter, u32 *vers);
714 int t3_check_tpsram_version(adapter_t *adapter);
715 int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size);
716 int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size);
717 int t3_get_fw_version(adapter_t *adapter, u32 *vers);
718 int t3_check_fw_version(adapter_t *adapter);
719 int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size);
720 int t3_init_hw(adapter_t *adapter, u32 fw_params);
721 void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
722 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
723 int t3_reset_adapter(adapter_t *adapter);
724 int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
725 int t3_reinit_adapter(adapter_t *adap);
726 void t3_led_ready(adapter_t *adapter);
727 void t3_fatal_err(adapter_t *adapter);
728 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
729 void t3_enable_filters(adapter_t *adap);
730 void t3_disable_filters(adapter_t *adap);
731 void t3_tp_set_offload_mode(adapter_t *adap, int enable);
732 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
733 const u16 *rspq);
734 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
735 int t3_set_proto_sram(adapter_t *adap, const u8 *data);
736 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
737 void t3_port_failover(adapter_t *adapter, int port);
738 void t3_failover_done(adapter_t *adapter, int port);
739 void t3_failover_clear(adapter_t *adapter);
740 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
741 unsigned int *valp);
742 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
743 u64 *buf);
744
745 int t3_mac_reset(struct cmac *mac);
746 void t3b_pcs_reset(struct cmac *mac);
747 void t3_mac_disable_exact_filters(struct cmac *mac);
748 void t3_mac_enable_exact_filters(struct cmac *mac);
749 int t3_mac_enable(struct cmac *mac, int which);
750 int t3_mac_disable(struct cmac *mac, int which);
751 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
752 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
753 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
754 int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n);
755 const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
756 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
757 int fc);
758 int t3b2_mac_watchdog_task(struct cmac *mac);
759
760 void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode);
761 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
762 unsigned int nroutes);
763 void t3_mc5_intr_handler(struct mc5 *mc5);
764 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
765 u32 *buf);
766
767 #ifdef CONFIG_CHELSIO_T3_CORE
768 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh);
769 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size);
770 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps);
771 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
772 unsigned short alpha[NCCTRL_WIN],
773 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
774 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]);
775 void t3_get_cong_cntl_tab(adapter_t *adap,
776 unsigned short incr[NMTUS][NCCTRL_WIN]);
777 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
778 int filter_index, int invert, int enable);
779 void t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp,
780 int filter_index, int *inverted, int *enabled);
781 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched);
782 int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg);
783 void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps,
784 unsigned int *ipg);
785 void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]);
786 void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals,
787 unsigned int start, unsigned int n);
788 #endif
789
790 int t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index,
791 u32 *size, void *data);
792 int t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data);
793
794 void t3_sge_prep(adapter_t *adap, struct sge_params *p);
795 void t3_sge_init(adapter_t *adap, struct sge_params *p);
796 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable,
797 enum sge_context_type type, int respq, u64 base_addr,
798 unsigned int size, unsigned int token, int gen,
799 unsigned int cidx);
800 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable,
801 u64 base_addr, unsigned int size, unsigned int esize,
802 unsigned int cong_thres, int gen, unsigned int cidx);
803 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx,
804 u64 base_addr, unsigned int size,
805 unsigned int fl_thres, int gen, unsigned int cidx);
806 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr,
807 unsigned int size, int rspq, int ovfl_mode,
808 unsigned int credits, unsigned int credit_thres);
809 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable);
810 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id);
811 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id);
812 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id);
813 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]);
814 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]);
815 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]);
816 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]);
817 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
818 unsigned int credits);
819
820 int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n);
821 int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n);
822 int t3_vsc7323_init(adapter_t *adap, int nports);
823 int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port);
824 int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port);
825 int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port);
826 int t3_vsc7323_enable(adapter_t *adap, int port, int which);
827 int t3_vsc7323_disable(adapter_t *adap, int port, int which);
828 const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac);
829
830 int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr,
831 unsigned int *valp);
832 int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr,
833 unsigned int val);
834
835 int t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
836 const struct mdio_ops *mdio_ops);
837 int t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
838 const struct mdio_ops *mdio_ops);
839 int t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
840 const struct mdio_ops *mdio_ops);
841 int t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
842 const struct mdio_ops *mdio_ops);
843 int t3_ael2005_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
844 const struct mdio_ops *mdio_ops);
845 int t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
846 const struct mdio_ops *mdio_ops);
847 int t3_tn1010_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
848 const struct mdio_ops *mdio_ops);
849 int t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
850 const struct mdio_ops *mdio_ops);
851 #endif /* __CHELSIO_COMMON_H */
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