1 /**************************************************************************
2
3 Copyright (c) 2007, Chelsio Inc.
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
15
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
27
28 $FreeBSD: releng/11.0/sys/dev/cxgb/common/cxgb_regs.h 197791 2009-10-05 20:21:41Z np $
29
30 ***************************************************************************/
31 /* This file is automatically generated --- do not edit */
32
33 /* registers for module SGE3 */
34 #define SGE3_BASE_ADDR 0x0
35
36 #define A_SG_CONTROL 0x0
37
38 #define S_CONGMODE 29
39 #define V_CONGMODE(x) ((x) << S_CONGMODE)
40 #define F_CONGMODE V_CONGMODE(1U)
41
42 #define S_TNLFLMODE 28
43 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE)
44 #define F_TNLFLMODE V_TNLFLMODE(1U)
45
46 #define S_FATLPERREN 27
47 #define V_FATLPERREN(x) ((x) << S_FATLPERREN)
48 #define F_FATLPERREN V_FATLPERREN(1U)
49
50 #define S_URGTNL 26
51 #define V_URGTNL(x) ((x) << S_URGTNL)
52 #define F_URGTNL V_URGTNL(1U)
53
54 #define S_NEWNOTIFY 25
55 #define V_NEWNOTIFY(x) ((x) << S_NEWNOTIFY)
56 #define F_NEWNOTIFY V_NEWNOTIFY(1U)
57
58 #define S_AVOIDCQOVFL 24
59 #define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL)
60 #define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U)
61
62 #define S_OPTONEINTMULTQ 23
63 #define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ)
64 #define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U)
65
66 #define S_CQCRDTCTRL 22
67 #define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL)
68 #define F_CQCRDTCTRL V_CQCRDTCTRL(1U)
69
70 #define S_EGRENUPBP 21
71 #define V_EGRENUPBP(x) ((x) << S_EGRENUPBP)
72 #define F_EGRENUPBP V_EGRENUPBP(1U)
73
74 #define S_DROPPKT 20
75 #define V_DROPPKT(x) ((x) << S_DROPPKT)
76 #define F_DROPPKT V_DROPPKT(1U)
77
78 #define S_EGRGENCTRL 19
79 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL)
80 #define F_EGRGENCTRL V_EGRGENCTRL(1U)
81
82 #define S_USERSPACESIZE 14
83 #define M_USERSPACESIZE 0x1f
84 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE)
85 #define G_USERSPACESIZE(x) (((x) >> S_USERSPACESIZE) & M_USERSPACESIZE)
86
87 #define S_HOSTPAGESIZE 11
88 #define M_HOSTPAGESIZE 0x7
89 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE)
90 #define G_HOSTPAGESIZE(x) (((x) >> S_HOSTPAGESIZE) & M_HOSTPAGESIZE)
91
92 #define S_PCIRELAX 10
93 #define V_PCIRELAX(x) ((x) << S_PCIRELAX)
94 #define F_PCIRELAX V_PCIRELAX(1U)
95
96 #define S_FLMODE 9
97 #define V_FLMODE(x) ((x) << S_FLMODE)
98 #define F_FLMODE V_FLMODE(1U)
99
100 #define S_PKTSHIFT 6
101 #define M_PKTSHIFT 0x7
102 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
103 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
104
105 #define S_ONEINTMULTQ 5
106 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ)
107 #define F_ONEINTMULTQ V_ONEINTMULTQ(1U)
108
109 #define S_FLPICKAVAIL 4
110 #define V_FLPICKAVAIL(x) ((x) << S_FLPICKAVAIL)
111 #define F_FLPICKAVAIL V_FLPICKAVAIL(1U)
112
113 #define S_BIGENDIANEGRESS 3
114 #define V_BIGENDIANEGRESS(x) ((x) << S_BIGENDIANEGRESS)
115 #define F_BIGENDIANEGRESS V_BIGENDIANEGRESS(1U)
116
117 #define S_BIGENDIANINGRESS 2
118 #define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS)
119 #define F_BIGENDIANINGRESS V_BIGENDIANINGRESS(1U)
120
121 #define S_ISCSICOALESCING 1
122 #define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING)
123 #define F_ISCSICOALESCING V_ISCSICOALESCING(1U)
124
125 #define S_GLOBALENABLE 0
126 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
127 #define F_GLOBALENABLE V_GLOBALENABLE(1U)
128
129 #define A_SG_KDOORBELL 0x4
130
131 #define S_SELEGRCNTX 31
132 #define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX)
133 #define F_SELEGRCNTX V_SELEGRCNTX(1U)
134
135 #define S_EGRCNTX 0
136 #define M_EGRCNTX 0xffff
137 #define V_EGRCNTX(x) ((x) << S_EGRCNTX)
138 #define G_EGRCNTX(x) (((x) >> S_EGRCNTX) & M_EGRCNTX)
139
140 #define A_SG_GTS 0x8
141
142 #define S_RSPQ 29
143 #define M_RSPQ 0x7
144 #define V_RSPQ(x) ((x) << S_RSPQ)
145 #define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ)
146
147 #define S_NEWTIMER 16
148 #define M_NEWTIMER 0x1fff
149 #define V_NEWTIMER(x) ((x) << S_NEWTIMER)
150 #define G_NEWTIMER(x) (((x) >> S_NEWTIMER) & M_NEWTIMER)
151
152 #define S_NEWINDEX 0
153 #define M_NEWINDEX 0xffff
154 #define V_NEWINDEX(x) ((x) << S_NEWINDEX)
155 #define G_NEWINDEX(x) (((x) >> S_NEWINDEX) & M_NEWINDEX)
156
157 #define A_SG_CONTEXT_CMD 0xc
158
159 #define S_CONTEXT_CMD_OPCODE 28
160 #define M_CONTEXT_CMD_OPCODE 0xf
161 #define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE)
162 #define G_CONTEXT_CMD_OPCODE(x) (((x) >> S_CONTEXT_CMD_OPCODE) & M_CONTEXT_CMD_OPCODE)
163
164 #define S_CONTEXT_CMD_BUSY 27
165 #define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY)
166 #define F_CONTEXT_CMD_BUSY V_CONTEXT_CMD_BUSY(1U)
167
168 #define S_CQ_CREDIT 20
169 #define M_CQ_CREDIT 0x7f
170 #define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT)
171 #define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT)
172
173 #define S_CQ 19
174 #define V_CQ(x) ((x) << S_CQ)
175 #define F_CQ V_CQ(1U)
176
177 #define S_RESPONSEQ 18
178 #define V_RESPONSEQ(x) ((x) << S_RESPONSEQ)
179 #define F_RESPONSEQ V_RESPONSEQ(1U)
180
181 #define S_EGRESS 17
182 #define V_EGRESS(x) ((x) << S_EGRESS)
183 #define F_EGRESS V_EGRESS(1U)
184
185 #define S_FREELIST 16
186 #define V_FREELIST(x) ((x) << S_FREELIST)
187 #define F_FREELIST V_FREELIST(1U)
188
189 #define S_CONTEXT 0
190 #define M_CONTEXT 0xffff
191 #define V_CONTEXT(x) ((x) << S_CONTEXT)
192 #define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT)
193
194 #define A_SG_CONTEXT_DATA0 0x10
195 #define A_SG_CONTEXT_DATA1 0x14
196 #define A_SG_CONTEXT_DATA2 0x18
197 #define A_SG_CONTEXT_DATA3 0x1c
198 #define A_SG_CONTEXT_MASK0 0x20
199 #define A_SG_CONTEXT_MASK1 0x24
200 #define A_SG_CONTEXT_MASK2 0x28
201 #define A_SG_CONTEXT_MASK3 0x2c
202 #define A_SG_RSPQ_CREDIT_RETURN 0x30
203
204 #define S_CREDITS 0
205 #define M_CREDITS 0xffff
206 #define V_CREDITS(x) ((x) << S_CREDITS)
207 #define G_CREDITS(x) (((x) >> S_CREDITS) & M_CREDITS)
208
209 #define A_SG_DATA_INTR 0x34
210
211 #define S_ERRINTR 31
212 #define V_ERRINTR(x) ((x) << S_ERRINTR)
213 #define F_ERRINTR V_ERRINTR(1U)
214
215 #define S_DATAINTR 0
216 #define M_DATAINTR 0xff
217 #define V_DATAINTR(x) ((x) << S_DATAINTR)
218 #define G_DATAINTR(x) (((x) >> S_DATAINTR) & M_DATAINTR)
219
220 #define A_SG_HI_DRB_HI_THRSH 0x38
221
222 #define S_HIDRBHITHRSH 0
223 #define M_HIDRBHITHRSH 0x3ff
224 #define V_HIDRBHITHRSH(x) ((x) << S_HIDRBHITHRSH)
225 #define G_HIDRBHITHRSH(x) (((x) >> S_HIDRBHITHRSH) & M_HIDRBHITHRSH)
226
227 #define A_SG_HI_DRB_LO_THRSH 0x3c
228
229 #define S_HIDRBLOTHRSH 0
230 #define M_HIDRBLOTHRSH 0x3ff
231 #define V_HIDRBLOTHRSH(x) ((x) << S_HIDRBLOTHRSH)
232 #define G_HIDRBLOTHRSH(x) (((x) >> S_HIDRBLOTHRSH) & M_HIDRBLOTHRSH)
233
234 #define A_SG_LO_DRB_HI_THRSH 0x40
235
236 #define S_LODRBHITHRSH 0
237 #define M_LODRBHITHRSH 0x3ff
238 #define V_LODRBHITHRSH(x) ((x) << S_LODRBHITHRSH)
239 #define G_LODRBHITHRSH(x) (((x) >> S_LODRBHITHRSH) & M_LODRBHITHRSH)
240
241 #define A_SG_LO_DRB_LO_THRSH 0x44
242
243 #define S_LODRBLOTHRSH 0
244 #define M_LODRBLOTHRSH 0x3ff
245 #define V_LODRBLOTHRSH(x) ((x) << S_LODRBLOTHRSH)
246 #define G_LODRBLOTHRSH(x) (((x) >> S_LODRBLOTHRSH) & M_LODRBLOTHRSH)
247
248 #define A_SG_ONE_INT_MULT_Q_COALESCING_TIMER 0x48
249 #define A_SG_RSPQ_FL_STATUS 0x4c
250
251 #define S_RSPQ0STARVED 0
252 #define V_RSPQ0STARVED(x) ((x) << S_RSPQ0STARVED)
253 #define F_RSPQ0STARVED V_RSPQ0STARVED(1U)
254
255 #define S_RSPQ1STARVED 1
256 #define V_RSPQ1STARVED(x) ((x) << S_RSPQ1STARVED)
257 #define F_RSPQ1STARVED V_RSPQ1STARVED(1U)
258
259 #define S_RSPQ2STARVED 2
260 #define V_RSPQ2STARVED(x) ((x) << S_RSPQ2STARVED)
261 #define F_RSPQ2STARVED V_RSPQ2STARVED(1U)
262
263 #define S_RSPQ3STARVED 3
264 #define V_RSPQ3STARVED(x) ((x) << S_RSPQ3STARVED)
265 #define F_RSPQ3STARVED V_RSPQ3STARVED(1U)
266
267 #define S_RSPQ4STARVED 4
268 #define V_RSPQ4STARVED(x) ((x) << S_RSPQ4STARVED)
269 #define F_RSPQ4STARVED V_RSPQ4STARVED(1U)
270
271 #define S_RSPQ5STARVED 5
272 #define V_RSPQ5STARVED(x) ((x) << S_RSPQ5STARVED)
273 #define F_RSPQ5STARVED V_RSPQ5STARVED(1U)
274
275 #define S_RSPQ6STARVED 6
276 #define V_RSPQ6STARVED(x) ((x) << S_RSPQ6STARVED)
277 #define F_RSPQ6STARVED V_RSPQ6STARVED(1U)
278
279 #define S_RSPQ7STARVED 7
280 #define V_RSPQ7STARVED(x) ((x) << S_RSPQ7STARVED)
281 #define F_RSPQ7STARVED V_RSPQ7STARVED(1U)
282
283 #define S_RSPQXSTARVED 0
284 #define M_RSPQXSTARVED 0xff
285 #define V_RSPQXSTARVED(x) ((x) << S_RSPQXSTARVED)
286 #define G_RSPQXSTARVED(x) (((x) >> S_RSPQXSTARVED) & M_RSPQXSTARVED)
287
288 #define S_RSPQ0DISABLED 8
289 #define V_RSPQ0DISABLED(x) ((x) << S_RSPQ0DISABLED)
290 #define F_RSPQ0DISABLED V_RSPQ0DISABLED(1U)
291
292 #define S_RSPQ1DISABLED 9
293 #define V_RSPQ1DISABLED(x) ((x) << S_RSPQ1DISABLED)
294 #define F_RSPQ1DISABLED V_RSPQ1DISABLED(1U)
295
296 #define S_RSPQ2DISABLED 10
297 #define V_RSPQ2DISABLED(x) ((x) << S_RSPQ2DISABLED)
298 #define F_RSPQ2DISABLED V_RSPQ2DISABLED(1U)
299
300 #define S_RSPQ3DISABLED 11
301 #define V_RSPQ3DISABLED(x) ((x) << S_RSPQ3DISABLED)
302 #define F_RSPQ3DISABLED V_RSPQ3DISABLED(1U)
303
304 #define S_RSPQ4DISABLED 12
305 #define V_RSPQ4DISABLED(x) ((x) << S_RSPQ4DISABLED)
306 #define F_RSPQ4DISABLED V_RSPQ4DISABLED(1U)
307
308 #define S_RSPQ5DISABLED 13
309 #define V_RSPQ5DISABLED(x) ((x) << S_RSPQ5DISABLED)
310 #define F_RSPQ5DISABLED V_RSPQ5DISABLED(1U)
311
312 #define S_RSPQ6DISABLED 14
313 #define V_RSPQ6DISABLED(x) ((x) << S_RSPQ6DISABLED)
314 #define F_RSPQ6DISABLED V_RSPQ6DISABLED(1U)
315
316 #define S_RSPQ7DISABLED 15
317 #define V_RSPQ7DISABLED(x) ((x) << S_RSPQ7DISABLED)
318 #define F_RSPQ7DISABLED V_RSPQ7DISABLED(1U)
319
320 #define S_FL0EMPTY 16
321 #define V_FL0EMPTY(x) ((x) << S_FL0EMPTY)
322 #define F_FL0EMPTY V_FL0EMPTY(1U)
323
324 #define S_FL1EMPTY 17
325 #define V_FL1EMPTY(x) ((x) << S_FL1EMPTY)
326 #define F_FL1EMPTY V_FL1EMPTY(1U)
327
328 #define S_FL2EMPTY 18
329 #define V_FL2EMPTY(x) ((x) << S_FL2EMPTY)
330 #define F_FL2EMPTY V_FL2EMPTY(1U)
331
332 #define S_FL3EMPTY 19
333 #define V_FL3EMPTY(x) ((x) << S_FL3EMPTY)
334 #define F_FL3EMPTY V_FL3EMPTY(1U)
335
336 #define S_FL4EMPTY 20
337 #define V_FL4EMPTY(x) ((x) << S_FL4EMPTY)
338 #define F_FL4EMPTY V_FL4EMPTY(1U)
339
340 #define S_FL5EMPTY 21
341 #define V_FL5EMPTY(x) ((x) << S_FL5EMPTY)
342 #define F_FL5EMPTY V_FL5EMPTY(1U)
343
344 #define S_FL6EMPTY 22
345 #define V_FL6EMPTY(x) ((x) << S_FL6EMPTY)
346 #define F_FL6EMPTY V_FL6EMPTY(1U)
347
348 #define S_FL7EMPTY 23
349 #define V_FL7EMPTY(x) ((x) << S_FL7EMPTY)
350 #define F_FL7EMPTY V_FL7EMPTY(1U)
351
352 #define S_FL8EMPTY 24
353 #define V_FL8EMPTY(x) ((x) << S_FL8EMPTY)
354 #define F_FL8EMPTY V_FL8EMPTY(1U)
355
356 #define S_FL9EMPTY 25
357 #define V_FL9EMPTY(x) ((x) << S_FL9EMPTY)
358 #define F_FL9EMPTY V_FL9EMPTY(1U)
359
360 #define S_FL10EMPTY 26
361 #define V_FL10EMPTY(x) ((x) << S_FL10EMPTY)
362 #define F_FL10EMPTY V_FL10EMPTY(1U)
363
364 #define S_FL11EMPTY 27
365 #define V_FL11EMPTY(x) ((x) << S_FL11EMPTY)
366 #define F_FL11EMPTY V_FL11EMPTY(1U)
367
368 #define S_FL12EMPTY 28
369 #define V_FL12EMPTY(x) ((x) << S_FL12EMPTY)
370 #define F_FL12EMPTY V_FL12EMPTY(1U)
371
372 #define S_FL13EMPTY 29
373 #define V_FL13EMPTY(x) ((x) << S_FL13EMPTY)
374 #define F_FL13EMPTY V_FL13EMPTY(1U)
375
376 #define S_FL14EMPTY 30
377 #define V_FL14EMPTY(x) ((x) << S_FL14EMPTY)
378 #define F_FL14EMPTY V_FL14EMPTY(1U)
379
380 #define S_FL15EMPTY 31
381 #define V_FL15EMPTY(x) ((x) << S_FL15EMPTY)
382 #define F_FL15EMPTY V_FL15EMPTY(1U)
383
384 #define S_FLXEMPTY 16
385 #define M_FLXEMPTY 0xffff
386 #define V_FLXEMPTY(x) ((x) << S_FLXEMPTY)
387 #define G_FLXEMPTY(x) (((x) >> S_FLXEMPTY) & M_FLXEMPTY)
388
389 #define A_SG_EGR_PRI_CNT 0x50
390
391 #define S_EGRERROPCODE 24
392 #define M_EGRERROPCODE 0xff
393 #define V_EGRERROPCODE(x) ((x) << S_EGRERROPCODE)
394 #define G_EGRERROPCODE(x) (((x) >> S_EGRERROPCODE) & M_EGRERROPCODE)
395
396 #define S_EGRHIOPCODE 16
397 #define M_EGRHIOPCODE 0xff
398 #define V_EGRHIOPCODE(x) ((x) << S_EGRHIOPCODE)
399 #define G_EGRHIOPCODE(x) (((x) >> S_EGRHIOPCODE) & M_EGRHIOPCODE)
400
401 #define S_EGRLOOPCODE 8
402 #define M_EGRLOOPCODE 0xff
403 #define V_EGRLOOPCODE(x) ((x) << S_EGRLOOPCODE)
404 #define G_EGRLOOPCODE(x) (((x) >> S_EGRLOOPCODE) & M_EGRLOOPCODE)
405
406 #define S_EGRPRICNT 0
407 #define M_EGRPRICNT 0x1f
408 #define V_EGRPRICNT(x) ((x) << S_EGRPRICNT)
409 #define G_EGRPRICNT(x) (((x) >> S_EGRPRICNT) & M_EGRPRICNT)
410
411 #define A_SG_EGR_RCQ_DRB_THRSH 0x54
412
413 #define S_HIRCQDRBTHRSH 16
414 #define M_HIRCQDRBTHRSH 0x7ff
415 #define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH)
416 #define G_HIRCQDRBTHRSH(x) (((x) >> S_HIRCQDRBTHRSH) & M_HIRCQDRBTHRSH)
417
418 #define S_LORCQDRBTHRSH 0
419 #define M_LORCQDRBTHRSH 0x7ff
420 #define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH)
421 #define G_LORCQDRBTHRSH(x) (((x) >> S_LORCQDRBTHRSH) & M_LORCQDRBTHRSH)
422
423 #define A_SG_EGR_CNTX_BADDR 0x58
424
425 #define S_EGRCNTXBADDR 5
426 #define M_EGRCNTXBADDR 0x7ffffff
427 #define V_EGRCNTXBADDR(x) ((x) << S_EGRCNTXBADDR)
428 #define G_EGRCNTXBADDR(x) (((x) >> S_EGRCNTXBADDR) & M_EGRCNTXBADDR)
429
430 #define A_SG_INT_CAUSE 0x5c
431
432 #define S_HIRCQPARITYERROR 31
433 #define V_HIRCQPARITYERROR(x) ((x) << S_HIRCQPARITYERROR)
434 #define F_HIRCQPARITYERROR V_HIRCQPARITYERROR(1U)
435
436 #define S_LORCQPARITYERROR 30
437 #define V_LORCQPARITYERROR(x) ((x) << S_LORCQPARITYERROR)
438 #define F_LORCQPARITYERROR V_LORCQPARITYERROR(1U)
439
440 #define S_HIDRBPARITYERROR 29
441 #define V_HIDRBPARITYERROR(x) ((x) << S_HIDRBPARITYERROR)
442 #define F_HIDRBPARITYERROR V_HIDRBPARITYERROR(1U)
443
444 #define S_LODRBPARITYERROR 28
445 #define V_LODRBPARITYERROR(x) ((x) << S_LODRBPARITYERROR)
446 #define F_LODRBPARITYERROR V_LODRBPARITYERROR(1U)
447
448 #define S_FLPARITYERROR 22
449 #define M_FLPARITYERROR 0x3f
450 #define V_FLPARITYERROR(x) ((x) << S_FLPARITYERROR)
451 #define G_FLPARITYERROR(x) (((x) >> S_FLPARITYERROR) & M_FLPARITYERROR)
452
453 #define S_ITPARITYERROR 20
454 #define M_ITPARITYERROR 0x3
455 #define V_ITPARITYERROR(x) ((x) << S_ITPARITYERROR)
456 #define G_ITPARITYERROR(x) (((x) >> S_ITPARITYERROR) & M_ITPARITYERROR)
457
458 #define S_IRPARITYERROR 19
459 #define V_IRPARITYERROR(x) ((x) << S_IRPARITYERROR)
460 #define F_IRPARITYERROR V_IRPARITYERROR(1U)
461
462 #define S_RCPARITYERROR 18
463 #define V_RCPARITYERROR(x) ((x) << S_RCPARITYERROR)
464 #define F_RCPARITYERROR V_RCPARITYERROR(1U)
465
466 #define S_OCPARITYERROR 17
467 #define V_OCPARITYERROR(x) ((x) << S_OCPARITYERROR)
468 #define F_OCPARITYERROR V_OCPARITYERROR(1U)
469
470 #define S_CPPARITYERROR 16
471 #define V_CPPARITYERROR(x) ((x) << S_CPPARITYERROR)
472 #define F_CPPARITYERROR V_CPPARITYERROR(1U)
473
474 #define S_R_REQ_FRAMINGERROR 15
475 #define V_R_REQ_FRAMINGERROR(x) ((x) << S_R_REQ_FRAMINGERROR)
476 #define F_R_REQ_FRAMINGERROR V_R_REQ_FRAMINGERROR(1U)
477
478 #define S_UC_REQ_FRAMINGERROR 14
479 #define V_UC_REQ_FRAMINGERROR(x) ((x) << S_UC_REQ_FRAMINGERROR)
480 #define F_UC_REQ_FRAMINGERROR V_UC_REQ_FRAMINGERROR(1U)
481
482 #define S_HICTLDRBDROPERR 13
483 #define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR)
484 #define F_HICTLDRBDROPERR V_HICTLDRBDROPERR(1U)
485
486 #define S_LOCTLDRBDROPERR 12
487 #define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR)
488 #define F_LOCTLDRBDROPERR V_LOCTLDRBDROPERR(1U)
489
490 #define S_HIPIODRBDROPERR 11
491 #define V_HIPIODRBDROPERR(x) ((x) << S_HIPIODRBDROPERR)
492 #define F_HIPIODRBDROPERR V_HIPIODRBDROPERR(1U)
493
494 #define S_LOPIODRBDROPERR 10
495 #define V_LOPIODRBDROPERR(x) ((x) << S_LOPIODRBDROPERR)
496 #define F_LOPIODRBDROPERR V_LOPIODRBDROPERR(1U)
497
498 #define S_HICRDTUNDFLOWERR 9
499 #define V_HICRDTUNDFLOWERR(x) ((x) << S_HICRDTUNDFLOWERR)
500 #define F_HICRDTUNDFLOWERR V_HICRDTUNDFLOWERR(1U)
501
502 #define S_LOCRDTUNDFLOWERR 8
503 #define V_LOCRDTUNDFLOWERR(x) ((x) << S_LOCRDTUNDFLOWERR)
504 #define F_LOCRDTUNDFLOWERR V_LOCRDTUNDFLOWERR(1U)
505
506 #define S_HIPRIORITYDBFULL 7
507 #define V_HIPRIORITYDBFULL(x) ((x) << S_HIPRIORITYDBFULL)
508 #define F_HIPRIORITYDBFULL V_HIPRIORITYDBFULL(1U)
509
510 #define S_HIPRIORITYDBEMPTY 6
511 #define V_HIPRIORITYDBEMPTY(x) ((x) << S_HIPRIORITYDBEMPTY)
512 #define F_HIPRIORITYDBEMPTY V_HIPRIORITYDBEMPTY(1U)
513
514 #define S_LOPRIORITYDBFULL 5
515 #define V_LOPRIORITYDBFULL(x) ((x) << S_LOPRIORITYDBFULL)
516 #define F_LOPRIORITYDBFULL V_LOPRIORITYDBFULL(1U)
517
518 #define S_LOPRIORITYDBEMPTY 4
519 #define V_LOPRIORITYDBEMPTY(x) ((x) << S_LOPRIORITYDBEMPTY)
520 #define F_LOPRIORITYDBEMPTY V_LOPRIORITYDBEMPTY(1U)
521
522 #define S_RSPQDISABLED 3
523 #define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED)
524 #define F_RSPQDISABLED V_RSPQDISABLED(1U)
525
526 #define S_RSPQCREDITOVERFOW 2
527 #define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW)
528 #define F_RSPQCREDITOVERFOW V_RSPQCREDITOVERFOW(1U)
529
530 #define S_FLEMPTY 1
531 #define V_FLEMPTY(x) ((x) << S_FLEMPTY)
532 #define F_FLEMPTY V_FLEMPTY(1U)
533
534 #define S_RSPQSTARVE 0
535 #define V_RSPQSTARVE(x) ((x) << S_RSPQSTARVE)
536 #define F_RSPQSTARVE V_RSPQSTARVE(1U)
537
538 #define A_SG_INT_ENABLE 0x60
539 #define A_SG_CMDQ_CREDIT_TH 0x64
540
541 #define S_TIMEOUT 8
542 #define M_TIMEOUT 0xffffff
543 #define V_TIMEOUT(x) ((x) << S_TIMEOUT)
544 #define G_TIMEOUT(x) (((x) >> S_TIMEOUT) & M_TIMEOUT)
545
546 #define S_THRESHOLD 0
547 #define M_THRESHOLD 0xff
548 #define V_THRESHOLD(x) ((x) << S_THRESHOLD)
549 #define G_THRESHOLD(x) (((x) >> S_THRESHOLD) & M_THRESHOLD)
550
551 #define A_SG_TIMER_TICK 0x68
552 #define A_SG_CQ_CONTEXT_BADDR 0x6c
553
554 #define S_BASEADDR 5
555 #define M_BASEADDR 0x7ffffff
556 #define V_BASEADDR(x) ((x) << S_BASEADDR)
557 #define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)
558
559 #define A_SG_OCO_BASE 0x70
560
561 #define S_BASE1 16
562 #define M_BASE1 0xffff
563 #define V_BASE1(x) ((x) << S_BASE1)
564 #define G_BASE1(x) (((x) >> S_BASE1) & M_BASE1)
565
566 #define S_BASE0 0
567 #define M_BASE0 0xffff
568 #define V_BASE0(x) ((x) << S_BASE0)
569 #define G_BASE0(x) (((x) >> S_BASE0) & M_BASE0)
570
571 #define A_SG_DRB_PRI_THRESH 0x74
572
573 #define S_DRBPRITHRSH 0
574 #define M_DRBPRITHRSH 0xffff
575 #define V_DRBPRITHRSH(x) ((x) << S_DRBPRITHRSH)
576 #define G_DRBPRITHRSH(x) (((x) >> S_DRBPRITHRSH) & M_DRBPRITHRSH)
577
578 #define A_SG_DEBUG_INDEX 0x78
579 #define A_SG_DEBUG_DATA 0x7c
580
581 /* registers for module PCIX1 */
582 #define PCIX1_BASE_ADDR 0x80
583
584 #define A_PCIX_INT_ENABLE 0x80
585
586 #define S_MSIXPARERR 22
587 #define M_MSIXPARERR 0x7
588 #define V_MSIXPARERR(x) ((x) << S_MSIXPARERR)
589 #define G_MSIXPARERR(x) (((x) >> S_MSIXPARERR) & M_MSIXPARERR)
590
591 #define S_CFPARERR 18
592 #define M_CFPARERR 0xf
593 #define V_CFPARERR(x) ((x) << S_CFPARERR)
594 #define G_CFPARERR(x) (((x) >> S_CFPARERR) & M_CFPARERR)
595
596 #define S_RFPARERR 14
597 #define M_RFPARERR 0xf
598 #define V_RFPARERR(x) ((x) << S_RFPARERR)
599 #define G_RFPARERR(x) (((x) >> S_RFPARERR) & M_RFPARERR)
600
601 #define S_WFPARERR 12
602 #define M_WFPARERR 0x3
603 #define V_WFPARERR(x) ((x) << S_WFPARERR)
604 #define G_WFPARERR(x) (((x) >> S_WFPARERR) & M_WFPARERR)
605
606 #define S_PIOPARERR 11
607 #define V_PIOPARERR(x) ((x) << S_PIOPARERR)
608 #define F_PIOPARERR V_PIOPARERR(1U)
609
610 #define S_DETUNCECCERR 10
611 #define V_DETUNCECCERR(x) ((x) << S_DETUNCECCERR)
612 #define F_DETUNCECCERR V_DETUNCECCERR(1U)
613
614 #define S_DETCORECCERR 9
615 #define V_DETCORECCERR(x) ((x) << S_DETCORECCERR)
616 #define F_DETCORECCERR V_DETCORECCERR(1U)
617
618 #define S_RCVSPLCMPERR 8
619 #define V_RCVSPLCMPERR(x) ((x) << S_RCVSPLCMPERR)
620 #define F_RCVSPLCMPERR V_RCVSPLCMPERR(1U)
621
622 #define S_UNXSPLCMP 7
623 #define V_UNXSPLCMP(x) ((x) << S_UNXSPLCMP)
624 #define F_UNXSPLCMP V_UNXSPLCMP(1U)
625
626 #define S_SPLCMPDIS 6
627 #define V_SPLCMPDIS(x) ((x) << S_SPLCMPDIS)
628 #define F_SPLCMPDIS V_SPLCMPDIS(1U)
629
630 #define S_DETPARERR 5
631 #define V_DETPARERR(x) ((x) << S_DETPARERR)
632 #define F_DETPARERR V_DETPARERR(1U)
633
634 #define S_SIGSYSERR 4
635 #define V_SIGSYSERR(x) ((x) << S_SIGSYSERR)
636 #define F_SIGSYSERR V_SIGSYSERR(1U)
637
638 #define S_RCVMSTABT 3
639 #define V_RCVMSTABT(x) ((x) << S_RCVMSTABT)
640 #define F_RCVMSTABT V_RCVMSTABT(1U)
641
642 #define S_RCVTARABT 2
643 #define V_RCVTARABT(x) ((x) << S_RCVTARABT)
644 #define F_RCVTARABT V_RCVTARABT(1U)
645
646 #define S_SIGTARABT 1
647 #define V_SIGTARABT(x) ((x) << S_SIGTARABT)
648 #define F_SIGTARABT V_SIGTARABT(1U)
649
650 #define S_MSTDETPARERR 0
651 #define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR)
652 #define F_MSTDETPARERR V_MSTDETPARERR(1U)
653
654 #define A_PCIX_INT_CAUSE 0x84
655 #define A_PCIX_CFG 0x88
656
657 #define S_DMASTOPEN 19
658 #define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)
659 #define F_DMASTOPEN V_DMASTOPEN(1U)
660
661 #define S_CLIDECEN 18
662 #define V_CLIDECEN(x) ((x) << S_CLIDECEN)
663 #define F_CLIDECEN V_CLIDECEN(1U)
664
665 #define S_LATTMRDIS 17
666 #define V_LATTMRDIS(x) ((x) << S_LATTMRDIS)
667 #define F_LATTMRDIS V_LATTMRDIS(1U)
668
669 #define S_LOWPWREN 16
670 #define V_LOWPWREN(x) ((x) << S_LOWPWREN)
671 #define F_LOWPWREN V_LOWPWREN(1U)
672
673 #define S_ASYNCINTVEC 11
674 #define M_ASYNCINTVEC 0x1f
675 #define V_ASYNCINTVEC(x) ((x) << S_ASYNCINTVEC)
676 #define G_ASYNCINTVEC(x) (((x) >> S_ASYNCINTVEC) & M_ASYNCINTVEC)
677
678 #define S_MAXSPLTRNC 8
679 #define M_MAXSPLTRNC 0x7
680 #define V_MAXSPLTRNC(x) ((x) << S_MAXSPLTRNC)
681 #define G_MAXSPLTRNC(x) (((x) >> S_MAXSPLTRNC) & M_MAXSPLTRNC)
682
683 #define S_MAXSPLTRNR 5
684 #define M_MAXSPLTRNR 0x7
685 #define V_MAXSPLTRNR(x) ((x) << S_MAXSPLTRNR)
686 #define G_MAXSPLTRNR(x) (((x) >> S_MAXSPLTRNR) & M_MAXSPLTRNR)
687
688 #define S_MAXWRBYTECNT 3
689 #define M_MAXWRBYTECNT 0x3
690 #define V_MAXWRBYTECNT(x) ((x) << S_MAXWRBYTECNT)
691 #define G_MAXWRBYTECNT(x) (((x) >> S_MAXWRBYTECNT) & M_MAXWRBYTECNT)
692
693 #define S_WRREQATOMICEN 2
694 #define V_WRREQATOMICEN(x) ((x) << S_WRREQATOMICEN)
695 #define F_WRREQATOMICEN V_WRREQATOMICEN(1U)
696
697 #define S_RSTWRMMODE 1
698 #define V_RSTWRMMODE(x) ((x) << S_RSTWRMMODE)
699 #define F_RSTWRMMODE V_RSTWRMMODE(1U)
700
701 #define S_PIOACK64EN 0
702 #define V_PIOACK64EN(x) ((x) << S_PIOACK64EN)
703 #define F_PIOACK64EN V_PIOACK64EN(1U)
704
705 #define A_PCIX_MODE 0x8c
706
707 #define S_PCLKRANGE 6
708 #define M_PCLKRANGE 0x3
709 #define V_PCLKRANGE(x) ((x) << S_PCLKRANGE)
710 #define G_PCLKRANGE(x) (((x) >> S_PCLKRANGE) & M_PCLKRANGE)
711
712 #define S_PCIXINITPAT 2
713 #define M_PCIXINITPAT 0xf
714 #define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT)
715 #define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT)
716
717 #define S_66MHZ 1
718 #define V_66MHZ(x) ((x) << S_66MHZ)
719 #define F_66MHZ V_66MHZ(1U)
720
721 #define S_64BIT 0
722 #define V_64BIT(x) ((x) << S_64BIT)
723 #define F_64BIT V_64BIT(1U)
724
725 #define A_PCIX_CAL 0x90
726
727 #define S_BUSY 31
728 #define V_BUSY(x) ((x) << S_BUSY)
729 #define F_BUSY V_BUSY(1U)
730
731 #define S_PERCALDIV 22
732 #define M_PERCALDIV 0xff
733 #define V_PERCALDIV(x) ((x) << S_PERCALDIV)
734 #define G_PERCALDIV(x) (((x) >> S_PERCALDIV) & M_PERCALDIV)
735
736 #define S_PERCALEN 21
737 #define V_PERCALEN(x) ((x) << S_PERCALEN)
738 #define F_PERCALEN V_PERCALEN(1U)
739
740 #define S_SGLCALEN 20
741 #define V_SGLCALEN(x) ((x) << S_SGLCALEN)
742 #define F_SGLCALEN V_SGLCALEN(1U)
743
744 #define S_ZINUPDMODE 19
745 #define V_ZINUPDMODE(x) ((x) << S_ZINUPDMODE)
746 #define F_ZINUPDMODE V_ZINUPDMODE(1U)
747
748 #define S_ZINSEL 18
749 #define V_ZINSEL(x) ((x) << S_ZINSEL)
750 #define F_ZINSEL V_ZINSEL(1U)
751
752 #define S_ZPDMAN 15
753 #define M_ZPDMAN 0x7
754 #define V_ZPDMAN(x) ((x) << S_ZPDMAN)
755 #define G_ZPDMAN(x) (((x) >> S_ZPDMAN) & M_ZPDMAN)
756
757 #define S_ZPUMAN 12
758 #define M_ZPUMAN 0x7
759 #define V_ZPUMAN(x) ((x) << S_ZPUMAN)
760 #define G_ZPUMAN(x) (((x) >> S_ZPUMAN) & M_ZPUMAN)
761
762 #define S_ZPDOUT 9
763 #define M_ZPDOUT 0x7
764 #define V_ZPDOUT(x) ((x) << S_ZPDOUT)
765 #define G_ZPDOUT(x) (((x) >> S_ZPDOUT) & M_ZPDOUT)
766
767 #define S_ZPUOUT 6
768 #define M_ZPUOUT 0x7
769 #define V_ZPUOUT(x) ((x) << S_ZPUOUT)
770 #define G_ZPUOUT(x) (((x) >> S_ZPUOUT) & M_ZPUOUT)
771
772 #define S_ZPDIN 3
773 #define M_ZPDIN 0x7
774 #define V_ZPDIN(x) ((x) << S_ZPDIN)
775 #define G_ZPDIN(x) (((x) >> S_ZPDIN) & M_ZPDIN)
776
777 #define S_ZPUIN 0
778 #define M_ZPUIN 0x7
779 #define V_ZPUIN(x) ((x) << S_ZPUIN)
780 #define G_ZPUIN(x) (((x) >> S_ZPUIN) & M_ZPUIN)
781
782 #define A_PCIX_WOL 0x94
783
784 #define S_WAKEUP1 3
785 #define V_WAKEUP1(x) ((x) << S_WAKEUP1)
786 #define F_WAKEUP1 V_WAKEUP1(1U)
787
788 #define S_WAKEUP0 2
789 #define V_WAKEUP0(x) ((x) << S_WAKEUP0)
790 #define F_WAKEUP0 V_WAKEUP0(1U)
791
792 #define S_SLEEPMODE1 1
793 #define V_SLEEPMODE1(x) ((x) << S_SLEEPMODE1)
794 #define F_SLEEPMODE1 V_SLEEPMODE1(1U)
795
796 #define S_SLEEPMODE0 0
797 #define V_SLEEPMODE0(x) ((x) << S_SLEEPMODE0)
798 #define F_SLEEPMODE0 V_SLEEPMODE0(1U)
799
800 #define A_PCIX_STAT0 0x98
801
802 #define S_PIOREQFIFOLEVEL 26
803 #define M_PIOREQFIFOLEVEL 0x3f
804 #define V_PIOREQFIFOLEVEL(x) ((x) << S_PIOREQFIFOLEVEL)
805 #define G_PIOREQFIFOLEVEL(x) (((x) >> S_PIOREQFIFOLEVEL) & M_PIOREQFIFOLEVEL)
806
807 #define S_RFINIST 24
808 #define M_RFINIST 0x3
809 #define V_RFINIST(x) ((x) << S_RFINIST)
810 #define G_RFINIST(x) (((x) >> S_RFINIST) & M_RFINIST)
811
812 #define S_RFRESPRDST 22
813 #define M_RFRESPRDST 0x3
814 #define V_RFRESPRDST(x) ((x) << S_RFRESPRDST)
815 #define G_RFRESPRDST(x) (((x) >> S_RFRESPRDST) & M_RFRESPRDST)
816
817 #define S_TARCST 19
818 #define M_TARCST 0x7
819 #define V_TARCST(x) ((x) << S_TARCST)
820 #define G_TARCST(x) (((x) >> S_TARCST) & M_TARCST)
821
822 #define S_TARXST 16
823 #define M_TARXST 0x7
824 #define V_TARXST(x) ((x) << S_TARXST)
825 #define G_TARXST(x) (((x) >> S_TARXST) & M_TARXST)
826
827 #define S_WFREQWRST 13
828 #define M_WFREQWRST 0x7
829 #define V_WFREQWRST(x) ((x) << S_WFREQWRST)
830 #define G_WFREQWRST(x) (((x) >> S_WFREQWRST) & M_WFREQWRST)
831
832 #define S_WFRESPFIFOEMPTY 12
833 #define V_WFRESPFIFOEMPTY(x) ((x) << S_WFRESPFIFOEMPTY)
834 #define F_WFRESPFIFOEMPTY V_WFRESPFIFOEMPTY(1U)
835
836 #define S_WFREQFIFOEMPTY 11
837 #define V_WFREQFIFOEMPTY(x) ((x) << S_WFREQFIFOEMPTY)
838 #define F_WFREQFIFOEMPTY V_WFREQFIFOEMPTY(1U)
839
840 #define S_RFRESPFIFOEMPTY 10
841 #define V_RFRESPFIFOEMPTY(x) ((x) << S_RFRESPFIFOEMPTY)
842 #define F_RFRESPFIFOEMPTY V_RFRESPFIFOEMPTY(1U)
843
844 #define S_RFREQFIFOEMPTY 9
845 #define V_RFREQFIFOEMPTY(x) ((x) << S_RFREQFIFOEMPTY)
846 #define F_RFREQFIFOEMPTY V_RFREQFIFOEMPTY(1U)
847
848 #define S_PIORESPFIFOLEVEL 7
849 #define M_PIORESPFIFOLEVEL 0x3
850 #define V_PIORESPFIFOLEVEL(x) ((x) << S_PIORESPFIFOLEVEL)
851 #define G_PIORESPFIFOLEVEL(x) (((x) >> S_PIORESPFIFOLEVEL) & M_PIORESPFIFOLEVEL)
852
853 #define S_CFRESPFIFOEMPTY 6
854 #define V_CFRESPFIFOEMPTY(x) ((x) << S_CFRESPFIFOEMPTY)
855 #define F_CFRESPFIFOEMPTY V_CFRESPFIFOEMPTY(1U)
856
857 #define S_CFREQFIFOEMPTY 5
858 #define V_CFREQFIFOEMPTY(x) ((x) << S_CFREQFIFOEMPTY)
859 #define F_CFREQFIFOEMPTY V_CFREQFIFOEMPTY(1U)
860
861 #define S_VPDRESPFIFOEMPTY 4
862 #define V_VPDRESPFIFOEMPTY(x) ((x) << S_VPDRESPFIFOEMPTY)
863 #define F_VPDRESPFIFOEMPTY V_VPDRESPFIFOEMPTY(1U)
864
865 #define S_VPDREQFIFOEMPTY 3
866 #define V_VPDREQFIFOEMPTY(x) ((x) << S_VPDREQFIFOEMPTY)
867 #define F_VPDREQFIFOEMPTY V_VPDREQFIFOEMPTY(1U)
868
869 #define S_PIO_RSPPND 2
870 #define V_PIO_RSPPND(x) ((x) << S_PIO_RSPPND)
871 #define F_PIO_RSPPND V_PIO_RSPPND(1U)
872
873 #define S_DLYTRNPND 1
874 #define V_DLYTRNPND(x) ((x) << S_DLYTRNPND)
875 #define F_DLYTRNPND V_DLYTRNPND(1U)
876
877 #define S_SPLTRNPND 0
878 #define V_SPLTRNPND(x) ((x) << S_SPLTRNPND)
879 #define F_SPLTRNPND V_SPLTRNPND(1U)
880
881 #define A_PCIX_STAT1 0x9c
882
883 #define S_WFINIST 26
884 #define M_WFINIST 0xf
885 #define V_WFINIST(x) ((x) << S_WFINIST)
886 #define G_WFINIST(x) (((x) >> S_WFINIST) & M_WFINIST)
887
888 #define S_ARBST 23
889 #define M_ARBST 0x7
890 #define V_ARBST(x) ((x) << S_ARBST)
891 #define G_ARBST(x) (((x) >> S_ARBST) & M_ARBST)
892
893 #define S_PMIST 21
894 #define M_PMIST 0x3
895 #define V_PMIST(x) ((x) << S_PMIST)
896 #define G_PMIST(x) (((x) >> S_PMIST) & M_PMIST)
897
898 #define S_CALST 19
899 #define M_CALST 0x3
900 #define V_CALST(x) ((x) << S_CALST)
901 #define G_CALST(x) (((x) >> S_CALST) & M_CALST)
902
903 #define S_CFREQRDST 17
904 #define M_CFREQRDST 0x3
905 #define V_CFREQRDST(x) ((x) << S_CFREQRDST)
906 #define G_CFREQRDST(x) (((x) >> S_CFREQRDST) & M_CFREQRDST)
907
908 #define S_CFINIST 15
909 #define M_CFINIST 0x3
910 #define V_CFINIST(x) ((x) << S_CFINIST)
911 #define G_CFINIST(x) (((x) >> S_CFINIST) & M_CFINIST)
912
913 #define S_CFRESPRDST 13
914 #define M_CFRESPRDST 0x3
915 #define V_CFRESPRDST(x) ((x) << S_CFRESPRDST)
916 #define G_CFRESPRDST(x) (((x) >> S_CFRESPRDST) & M_CFRESPRDST)
917
918 #define S_INICST 10
919 #define M_INICST 0x7
920 #define V_INICST(x) ((x) << S_INICST)
921 #define G_INICST(x) (((x) >> S_INICST) & M_INICST)
922
923 #define S_INIXST 7
924 #define M_INIXST 0x7
925 #define V_INIXST(x) ((x) << S_INIXST)
926 #define G_INIXST(x) (((x) >> S_INIXST) & M_INIXST)
927
928 #define S_INTST 4
929 #define M_INTST 0x7
930 #define V_INTST(x) ((x) << S_INTST)
931 #define G_INTST(x) (((x) >> S_INTST) & M_INTST)
932
933 #define S_PIOST 2
934 #define M_PIOST 0x3
935 #define V_PIOST(x) ((x) << S_PIOST)
936 #define G_PIOST(x) (((x) >> S_PIOST) & M_PIOST)
937
938 #define S_RFREQRDST 0
939 #define M_RFREQRDST 0x3
940 #define V_RFREQRDST(x) ((x) << S_RFREQRDST)
941 #define G_RFREQRDST(x) (((x) >> S_RFREQRDST) & M_RFREQRDST)
942
943 /* registers for module PCIE0 */
944 #define PCIE0_BASE_ADDR 0x80
945
946 #define A_PCIE_INT_ENABLE 0x80
947
948 #define S_BISTERR 19
949 #define M_BISTERR 0xff
950 #define V_BISTERR(x) ((x) << S_BISTERR)
951 #define G_BISTERR(x) (((x) >> S_BISTERR) & M_BISTERR)
952
953 #define S_TXPARERR 18
954 #define V_TXPARERR(x) ((x) << S_TXPARERR)
955 #define F_TXPARERR V_TXPARERR(1U)
956
957 #define S_RXPARERR 17
958 #define V_RXPARERR(x) ((x) << S_RXPARERR)
959 #define F_RXPARERR V_RXPARERR(1U)
960
961 #define S_RETRYLUTPARERR 16
962 #define V_RETRYLUTPARERR(x) ((x) << S_RETRYLUTPARERR)
963 #define F_RETRYLUTPARERR V_RETRYLUTPARERR(1U)
964
965 #define S_RETRYBUFPARERR 15
966 #define V_RETRYBUFPARERR(x) ((x) << S_RETRYBUFPARERR)
967 #define F_RETRYBUFPARERR V_RETRYBUFPARERR(1U)
968
969 #define S_PCIE_MSIXPARERR 12
970 #define M_PCIE_MSIXPARERR 0x7
971 #define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR)
972 #define G_PCIE_MSIXPARERR(x) (((x) >> S_PCIE_MSIXPARERR) & M_PCIE_MSIXPARERR)
973
974 #define S_PCIE_CFPARERR 11
975 #define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR)
976 #define F_PCIE_CFPARERR V_PCIE_CFPARERR(1U)
977
978 #define S_PCIE_RFPARERR 10
979 #define V_PCIE_RFPARERR(x) ((x) << S_PCIE_RFPARERR)
980 #define F_PCIE_RFPARERR V_PCIE_RFPARERR(1U)
981
982 #define S_PCIE_WFPARERR 9
983 #define V_PCIE_WFPARERR(x) ((x) << S_PCIE_WFPARERR)
984 #define F_PCIE_WFPARERR V_PCIE_WFPARERR(1U)
985
986 #define S_PCIE_PIOPARERR 8
987 #define V_PCIE_PIOPARERR(x) ((x) << S_PCIE_PIOPARERR)
988 #define F_PCIE_PIOPARERR V_PCIE_PIOPARERR(1U)
989
990 #define S_UNXSPLCPLERRC 7
991 #define V_UNXSPLCPLERRC(x) ((x) << S_UNXSPLCPLERRC)
992 #define F_UNXSPLCPLERRC V_UNXSPLCPLERRC(1U)
993
994 #define S_UNXSPLCPLERRR 6
995 #define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR)
996 #define F_UNXSPLCPLERRR V_UNXSPLCPLERRR(1U)
997
998 #define S_VPDADDRCHNG 5
999 #define V_VPDADDRCHNG(x) ((x) << S_VPDADDRCHNG)
1000 #define F_VPDADDRCHNG V_VPDADDRCHNG(1U)
1001
1002 #define S_BUSMSTREN 4
1003 #define V_BUSMSTREN(x) ((x) << S_BUSMSTREN)
1004 #define F_BUSMSTREN V_BUSMSTREN(1U)
1005
1006 #define S_PMSTCHNG 3
1007 #define V_PMSTCHNG(x) ((x) << S_PMSTCHNG)
1008 #define F_PMSTCHNG V_PMSTCHNG(1U)
1009
1010 #define S_PEXMSG 2
1011 #define V_PEXMSG(x) ((x) << S_PEXMSG)
1012 #define F_PEXMSG V_PEXMSG(1U)
1013
1014 #define S_ZEROLENRD 1
1015 #define V_ZEROLENRD(x) ((x) << S_ZEROLENRD)
1016 #define F_ZEROLENRD V_ZEROLENRD(1U)
1017
1018 #define S_PEXERR 0
1019 #define V_PEXERR(x) ((x) << S_PEXERR)
1020 #define F_PEXERR V_PEXERR(1U)
1021
1022 #define A_PCIE_INT_CAUSE 0x84
1023 #define A_PCIE_CFG 0x88
1024
1025 #define S_PCIE_DMASTOPEN 24
1026 #define V_PCIE_DMASTOPEN(x) ((x) << S_PCIE_DMASTOPEN)
1027 #define F_PCIE_DMASTOPEN V_PCIE_DMASTOPEN(1U)
1028
1029 #define S_PRIORITYINTA 23
1030 #define V_PRIORITYINTA(x) ((x) << S_PRIORITYINTA)
1031 #define F_PRIORITYINTA V_PRIORITYINTA(1U)
1032
1033 #define S_INIFULLPKT 22
1034 #define V_INIFULLPKT(x) ((x) << S_INIFULLPKT)
1035 #define F_INIFULLPKT V_INIFULLPKT(1U)
1036
1037 #define S_ENABLELINKDWNDRST 21
1038 #define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST)
1039 #define F_ENABLELINKDWNDRST V_ENABLELINKDWNDRST(1U)
1040
1041 #define S_ENABLELINKDOWNRST 20
1042 #define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST)
1043 #define F_ENABLELINKDOWNRST V_ENABLELINKDOWNRST(1U)
1044
1045 #define S_ENABLEHOTRST 19
1046 #define V_ENABLEHOTRST(x) ((x) << S_ENABLEHOTRST)
1047 #define F_ENABLEHOTRST V_ENABLEHOTRST(1U)
1048
1049 #define S_INIWAITFORGNT 18
1050 #define V_INIWAITFORGNT(x) ((x) << S_INIWAITFORGNT)
1051 #define F_INIWAITFORGNT V_INIWAITFORGNT(1U)
1052
1053 #define S_INIBEDIS 17
1054 #define V_INIBEDIS(x) ((x) << S_INIBEDIS)
1055 #define F_INIBEDIS V_INIBEDIS(1U)
1056
1057 #define S_PCIE_CLIDECEN 16
1058 #define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN)
1059 #define F_PCIE_CLIDECEN V_PCIE_CLIDECEN(1U)
1060
1061 #define S_PCIE_MAXSPLTRNC 7
1062 #define M_PCIE_MAXSPLTRNC 0xf
1063 #define V_PCIE_MAXSPLTRNC(x) ((x) << S_PCIE_MAXSPLTRNC)
1064 #define G_PCIE_MAXSPLTRNC(x) (((x) >> S_PCIE_MAXSPLTRNC) & M_PCIE_MAXSPLTRNC)
1065
1066 #define S_PCIE_MAXSPLTRNR 1
1067 #define M_PCIE_MAXSPLTRNR 0x3f
1068 #define V_PCIE_MAXSPLTRNR(x) ((x) << S_PCIE_MAXSPLTRNR)
1069 #define G_PCIE_MAXSPLTRNR(x) (((x) >> S_PCIE_MAXSPLTRNR) & M_PCIE_MAXSPLTRNR)
1070
1071 #define S_CRSTWRMMODE 0
1072 #define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE)
1073 #define F_CRSTWRMMODE V_CRSTWRMMODE(1U)
1074
1075 #define A_PCIE_MODE 0x8c
1076
1077 #define S_TAR_STATE 29
1078 #define M_TAR_STATE 0x7
1079 #define V_TAR_STATE(x) ((x) << S_TAR_STATE)
1080 #define G_TAR_STATE(x) (((x) >> S_TAR_STATE) & M_TAR_STATE)
1081
1082 #define S_RF_STATEINI 26
1083 #define M_RF_STATEINI 0x7
1084 #define V_RF_STATEINI(x) ((x) << S_RF_STATEINI)
1085 #define G_RF_STATEINI(x) (((x) >> S_RF_STATEINI) & M_RF_STATEINI)
1086
1087 #define S_CF_STATEINI 23
1088 #define M_CF_STATEINI 0x7
1089 #define V_CF_STATEINI(x) ((x) << S_CF_STATEINI)
1090 #define G_CF_STATEINI(x) (((x) >> S_CF_STATEINI) & M_CF_STATEINI)
1091
1092 #define S_PIO_STATEPL 20
1093 #define M_PIO_STATEPL 0x7
1094 #define V_PIO_STATEPL(x) ((x) << S_PIO_STATEPL)
1095 #define G_PIO_STATEPL(x) (((x) >> S_PIO_STATEPL) & M_PIO_STATEPL)
1096
1097 #define S_PIO_STATEISC 18
1098 #define M_PIO_STATEISC 0x3
1099 #define V_PIO_STATEISC(x) ((x) << S_PIO_STATEISC)
1100 #define G_PIO_STATEISC(x) (((x) >> S_PIO_STATEISC) & M_PIO_STATEISC)
1101
1102 #define S_NUMFSTTRNSEQRX 10
1103 #define M_NUMFSTTRNSEQRX 0xff
1104 #define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX)
1105 #define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX)
1106
1107 #define S_LNKCNTLSTATE 2
1108 #define M_LNKCNTLSTATE 0xff
1109 #define V_LNKCNTLSTATE(x) ((x) << S_LNKCNTLSTATE)
1110 #define G_LNKCNTLSTATE(x) (((x) >> S_LNKCNTLSTATE) & M_LNKCNTLSTATE)
1111
1112 #define S_VC0UP 1
1113 #define V_VC0UP(x) ((x) << S_VC0UP)
1114 #define F_VC0UP V_VC0UP(1U)
1115
1116 #define S_LNKINITIAL 0
1117 #define V_LNKINITIAL(x) ((x) << S_LNKINITIAL)
1118 #define F_LNKINITIAL V_LNKINITIAL(1U)
1119
1120 #define A_PCIE_STAT 0x90
1121
1122 #define S_INI_STATE 28
1123 #define M_INI_STATE 0xf
1124 #define V_INI_STATE(x) ((x) << S_INI_STATE)
1125 #define G_INI_STATE(x) (((x) >> S_INI_STATE) & M_INI_STATE)
1126
1127 #define S_WF_STATEINI 24
1128 #define M_WF_STATEINI 0xf
1129 #define V_WF_STATEINI(x) ((x) << S_WF_STATEINI)
1130 #define G_WF_STATEINI(x) (((x) >> S_WF_STATEINI) & M_WF_STATEINI)
1131
1132 #define S_PLM_REQFIFOCNT 22
1133 #define M_PLM_REQFIFOCNT 0x3
1134 #define V_PLM_REQFIFOCNT(x) ((x) << S_PLM_REQFIFOCNT)
1135 #define G_PLM_REQFIFOCNT(x) (((x) >> S_PLM_REQFIFOCNT) & M_PLM_REQFIFOCNT)
1136
1137 #define S_ER_REQFIFOEMPTY 21
1138 #define V_ER_REQFIFOEMPTY(x) ((x) << S_ER_REQFIFOEMPTY)
1139 #define F_ER_REQFIFOEMPTY V_ER_REQFIFOEMPTY(1U)
1140
1141 #define S_WF_RSPFIFOEMPTY 20
1142 #define V_WF_RSPFIFOEMPTY(x) ((x) << S_WF_RSPFIFOEMPTY)
1143 #define F_WF_RSPFIFOEMPTY V_WF_RSPFIFOEMPTY(1U)
1144
1145 #define S_WF_REQFIFOEMPTY 19
1146 #define V_WF_REQFIFOEMPTY(x) ((x) << S_WF_REQFIFOEMPTY)
1147 #define F_WF_REQFIFOEMPTY V_WF_REQFIFOEMPTY(1U)
1148
1149 #define S_RF_RSPFIFOEMPTY 18
1150 #define V_RF_RSPFIFOEMPTY(x) ((x) << S_RF_RSPFIFOEMPTY)
1151 #define F_RF_RSPFIFOEMPTY V_RF_RSPFIFOEMPTY(1U)
1152
1153 #define S_RF_REQFIFOEMPTY 17
1154 #define V_RF_REQFIFOEMPTY(x) ((x) << S_RF_REQFIFOEMPTY)
1155 #define F_RF_REQFIFOEMPTY V_RF_REQFIFOEMPTY(1U)
1156
1157 #define S_RF_ACTEMPTY 16
1158 #define V_RF_ACTEMPTY(x) ((x) << S_RF_ACTEMPTY)
1159 #define F_RF_ACTEMPTY V_RF_ACTEMPTY(1U)
1160
1161 #define S_PIO_RSPFIFOCNT 11
1162 #define M_PIO_RSPFIFOCNT 0x1f
1163 #define V_PIO_RSPFIFOCNT(x) ((x) << S_PIO_RSPFIFOCNT)
1164 #define G_PIO_RSPFIFOCNT(x) (((x) >> S_PIO_RSPFIFOCNT) & M_PIO_RSPFIFOCNT)
1165
1166 #define S_PIO_REQFIFOCNT 5
1167 #define M_PIO_REQFIFOCNT 0x3f
1168 #define V_PIO_REQFIFOCNT(x) ((x) << S_PIO_REQFIFOCNT)
1169 #define G_PIO_REQFIFOCNT(x) (((x) >> S_PIO_REQFIFOCNT) & M_PIO_REQFIFOCNT)
1170
1171 #define S_CF_RSPFIFOEMPTY 4
1172 #define V_CF_RSPFIFOEMPTY(x) ((x) << S_CF_RSPFIFOEMPTY)
1173 #define F_CF_RSPFIFOEMPTY V_CF_RSPFIFOEMPTY(1U)
1174
1175 #define S_CF_REQFIFOEMPTY 3
1176 #define V_CF_REQFIFOEMPTY(x) ((x) << S_CF_REQFIFOEMPTY)
1177 #define F_CF_REQFIFOEMPTY V_CF_REQFIFOEMPTY(1U)
1178
1179 #define S_CF_ACTEMPTY 2
1180 #define V_CF_ACTEMPTY(x) ((x) << S_CF_ACTEMPTY)
1181 #define F_CF_ACTEMPTY V_CF_ACTEMPTY(1U)
1182
1183 #define S_VPD_RSPFIFOEMPTY 1
1184 #define V_VPD_RSPFIFOEMPTY(x) ((x) << S_VPD_RSPFIFOEMPTY)
1185 #define F_VPD_RSPFIFOEMPTY V_VPD_RSPFIFOEMPTY(1U)
1186
1187 #define S_VPD_REQFIFOEMPTY 0
1188 #define V_VPD_REQFIFOEMPTY(x) ((x) << S_VPD_REQFIFOEMPTY)
1189 #define F_VPD_REQFIFOEMPTY V_VPD_REQFIFOEMPTY(1U)
1190
1191 #define A_PCIE_CAL 0x90
1192
1193 #define S_CALBUSY 31
1194 #define V_CALBUSY(x) ((x) << S_CALBUSY)
1195 #define F_CALBUSY V_CALBUSY(1U)
1196
1197 #define S_CALFAULT 30
1198 #define V_CALFAULT(x) ((x) << S_CALFAULT)
1199 #define F_CALFAULT V_CALFAULT(1U)
1200
1201 #define S_PCIE_ZINSEL 11
1202 #define V_PCIE_ZINSEL(x) ((x) << S_PCIE_ZINSEL)
1203 #define F_PCIE_ZINSEL V_PCIE_ZINSEL(1U)
1204
1205 #define S_ZMAN 8
1206 #define M_ZMAN 0x7
1207 #define V_ZMAN(x) ((x) << S_ZMAN)
1208 #define G_ZMAN(x) (((x) >> S_ZMAN) & M_ZMAN)
1209
1210 #define S_ZOUT 3
1211 #define M_ZOUT 0x1f
1212 #define V_ZOUT(x) ((x) << S_ZOUT)
1213 #define G_ZOUT(x) (((x) >> S_ZOUT) & M_ZOUT)
1214
1215 #define S_ZIN 0
1216 #define M_ZIN 0x7
1217 #define V_ZIN(x) ((x) << S_ZIN)
1218 #define G_ZIN(x) (((x) >> S_ZIN) & M_ZIN)
1219
1220 #define A_PCIE_WOL 0x94
1221
1222 #define S_CF_RSPSTATE 12
1223 #define M_CF_RSPSTATE 0x3
1224 #define V_CF_RSPSTATE(x) ((x) << S_CF_RSPSTATE)
1225 #define G_CF_RSPSTATE(x) (((x) >> S_CF_RSPSTATE) & M_CF_RSPSTATE)
1226
1227 #define S_RF_RSPSTATE 10
1228 #define M_RF_RSPSTATE 0x3
1229 #define V_RF_RSPSTATE(x) ((x) << S_RF_RSPSTATE)
1230 #define G_RF_RSPSTATE(x) (((x) >> S_RF_RSPSTATE) & M_RF_RSPSTATE)
1231
1232 #define S_PME_STATE 7
1233 #define M_PME_STATE 0x7
1234 #define V_PME_STATE(x) ((x) << S_PME_STATE)
1235 #define G_PME_STATE(x) (((x) >> S_PME_STATE) & M_PME_STATE)
1236
1237 #define S_INT_STATE 4
1238 #define M_INT_STATE 0x7
1239 #define V_INT_STATE(x) ((x) << S_INT_STATE)
1240 #define G_INT_STATE(x) (((x) >> S_INT_STATE) & M_INT_STATE)
1241
1242 #define A_PCIE_PEX_CTRL0 0x98
1243
1244 #define S_CPLTIMEOUTRETRY 31
1245 #define V_CPLTIMEOUTRETRY(x) ((x) << S_CPLTIMEOUTRETRY)
1246 #define F_CPLTIMEOUTRETRY V_CPLTIMEOUTRETRY(1U)
1247
1248 #define S_STRICTTSMN 30
1249 #define V_STRICTTSMN(x) ((x) << S_STRICTTSMN)
1250 #define F_STRICTTSMN V_STRICTTSMN(1U)
1251
1252 #define S_NUMFSTTRNSEQ 22
1253 #define M_NUMFSTTRNSEQ 0xff
1254 #define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ)
1255 #define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ)
1256
1257 #define S_REPLAYLMT 2
1258 #define M_REPLAYLMT 0xfffff
1259 #define V_REPLAYLMT(x) ((x) << S_REPLAYLMT)
1260 #define G_REPLAYLMT(x) (((x) >> S_REPLAYLMT) & M_REPLAYLMT)
1261
1262 #define S_TXPNDCHKEN 1
1263 #define V_TXPNDCHKEN(x) ((x) << S_TXPNDCHKEN)
1264 #define F_TXPNDCHKEN V_TXPNDCHKEN(1U)
1265
1266 #define S_CPLPNDCHKEN 0
1267 #define V_CPLPNDCHKEN(x) ((x) << S_CPLPNDCHKEN)
1268 #define F_CPLPNDCHKEN V_CPLPNDCHKEN(1U)
1269
1270 #define A_PCIE_PEX_CTRL1 0x9c
1271
1272 #define S_RXPHYERREN 31
1273 #define V_RXPHYERREN(x) ((x) << S_RXPHYERREN)
1274 #define F_RXPHYERREN V_RXPHYERREN(1U)
1275
1276 #define S_DLLPTIMEOUTLMT 13
1277 #define M_DLLPTIMEOUTLMT 0x3ffff
1278 #define V_DLLPTIMEOUTLMT(x) ((x) << S_DLLPTIMEOUTLMT)
1279 #define G_DLLPTIMEOUTLMT(x) (((x) >> S_DLLPTIMEOUTLMT) & M_DLLPTIMEOUTLMT)
1280
1281 #define S_ACKLAT 0
1282 #define M_ACKLAT 0x1fff
1283 #define V_ACKLAT(x) ((x) << S_ACKLAT)
1284 #define G_ACKLAT(x) (((x) >> S_ACKLAT) & M_ACKLAT)
1285
1286 #define S_T3A_DLLPTIMEOUTLMT 11
1287 #define M_T3A_DLLPTIMEOUTLMT 0xfffff
1288 #define V_T3A_DLLPTIMEOUTLMT(x) ((x) << S_T3A_DLLPTIMEOUTLMT)
1289 #define G_T3A_DLLPTIMEOUTLMT(x) (((x) >> S_T3A_DLLPTIMEOUTLMT) & M_T3A_DLLPTIMEOUTLMT)
1290
1291 #define S_T3A_ACKLAT 0
1292 #define M_T3A_ACKLAT 0x7ff
1293 #define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT)
1294 #define G_T3A_ACKLAT(x) (((x) >> S_T3A_ACKLAT) & M_T3A_ACKLAT)
1295
1296 #define A_PCIE_PEX_CTRL2 0xa0
1297
1298 #define S_LNKCNTLDETDIR 30
1299 #define V_LNKCNTLDETDIR(x) ((x) << S_LNKCNTLDETDIR)
1300 #define F_LNKCNTLDETDIR V_LNKCNTLDETDIR(1U)
1301
1302 #define S_ENTERL1REN 29
1303 #define V_ENTERL1REN(x) ((x) << S_ENTERL1REN)
1304 #define F_ENTERL1REN V_ENTERL1REN(1U)
1305
1306 #define S_PMEXITL1REQ 28
1307 #define V_PMEXITL1REQ(x) ((x) << S_PMEXITL1REQ)
1308 #define F_PMEXITL1REQ V_PMEXITL1REQ(1U)
1309
1310 #define S_PMTXIDLE 27
1311 #define V_PMTXIDLE(x) ((x) << S_PMTXIDLE)
1312 #define F_PMTXIDLE V_PMTXIDLE(1U)
1313
1314 #define S_PCIMODELOOP 26
1315 #define V_PCIMODELOOP(x) ((x) << S_PCIMODELOOP)
1316 #define F_PCIMODELOOP V_PCIMODELOOP(1U)
1317
1318 #define S_L1ASPMTXRXL0STIME 14
1319 #define M_L1ASPMTXRXL0STIME 0xfff
1320 #define V_L1ASPMTXRXL0STIME(x) ((x) << S_L1ASPMTXRXL0STIME)
1321 #define G_L1ASPMTXRXL0STIME(x) (((x) >> S_L1ASPMTXRXL0STIME) & M_L1ASPMTXRXL0STIME)
1322
1323 #define S_L0SIDLETIME 3
1324 #define M_L0SIDLETIME 0x7ff
1325 #define V_L0SIDLETIME(x) ((x) << S_L0SIDLETIME)
1326 #define G_L0SIDLETIME(x) (((x) >> S_L0SIDLETIME) & M_L0SIDLETIME)
1327
1328 #define S_ENTERL1ASPMEN 2
1329 #define V_ENTERL1ASPMEN(x) ((x) << S_ENTERL1ASPMEN)
1330 #define F_ENTERL1ASPMEN V_ENTERL1ASPMEN(1U)
1331
1332 #define S_ENTERL1EN 1
1333 #define V_ENTERL1EN(x) ((x) << S_ENTERL1EN)
1334 #define F_ENTERL1EN V_ENTERL1EN(1U)
1335
1336 #define S_ENTERL0SEN 0
1337 #define V_ENTERL0SEN(x) ((x) << S_ENTERL0SEN)
1338 #define F_ENTERL0SEN V_ENTERL0SEN(1U)
1339
1340 #define S_ENTERL23 3
1341 #define V_ENTERL23(x) ((x) << S_ENTERL23)
1342 #define F_ENTERL23 V_ENTERL23(1U)
1343
1344 #define A_PCIE_PEX_ERR 0xa4
1345
1346 #define S_CPLTIMEOUTID 18
1347 #define M_CPLTIMEOUTID 0x7f
1348 #define V_CPLTIMEOUTID(x) ((x) << S_CPLTIMEOUTID)
1349 #define G_CPLTIMEOUTID(x) (((x) >> S_CPLTIMEOUTID) & M_CPLTIMEOUTID)
1350
1351 #define S_FLOWCTLOFLOWERR 17
1352 #define V_FLOWCTLOFLOWERR(x) ((x) << S_FLOWCTLOFLOWERR)
1353 #define F_FLOWCTLOFLOWERR V_FLOWCTLOFLOWERR(1U)
1354
1355 #define S_REPLAYTIMEOUT 16
1356 #define V_REPLAYTIMEOUT(x) ((x) << S_REPLAYTIMEOUT)
1357 #define F_REPLAYTIMEOUT V_REPLAYTIMEOUT(1U)
1358
1359 #define S_REPLAYROLLOVER 15
1360 #define V_REPLAYROLLOVER(x) ((x) << S_REPLAYROLLOVER)
1361 #define F_REPLAYROLLOVER V_REPLAYROLLOVER(1U)
1362
1363 #define S_BADDLLP 14
1364 #define V_BADDLLP(x) ((x) << S_BADDLLP)
1365 #define F_BADDLLP V_BADDLLP(1U)
1366
1367 #define S_DLLPERR 13
1368 #define V_DLLPERR(x) ((x) << S_DLLPERR)
1369 #define F_DLLPERR V_DLLPERR(1U)
1370
1371 #define S_FLOWCTLPROTERR 12
1372 #define V_FLOWCTLPROTERR(x) ((x) << S_FLOWCTLPROTERR)
1373 #define F_FLOWCTLPROTERR V_FLOWCTLPROTERR(1U)
1374
1375 #define S_CPLTIMEOUT 11
1376 #define V_CPLTIMEOUT(x) ((x) << S_CPLTIMEOUT)
1377 #define F_CPLTIMEOUT V_CPLTIMEOUT(1U)
1378
1379 #define S_PHYRCVERR 10
1380 #define V_PHYRCVERR(x) ((x) << S_PHYRCVERR)
1381 #define F_PHYRCVERR V_PHYRCVERR(1U)
1382
1383 #define S_DISTLP 9
1384 #define V_DISTLP(x) ((x) << S_DISTLP)
1385 #define F_DISTLP V_DISTLP(1U)
1386
1387 #define S_BADECRC 8
1388 #define V_BADECRC(x) ((x) << S_BADECRC)
1389 #define F_BADECRC V_BADECRC(1U)
1390
1391 #define S_BADTLP 7
1392 #define V_BADTLP(x) ((x) << S_BADTLP)
1393 #define F_BADTLP V_BADTLP(1U)
1394
1395 #define S_MALTLP 6
1396 #define V_MALTLP(x) ((x) << S_MALTLP)
1397 #define F_MALTLP V_MALTLP(1U)
1398
1399 #define S_UNXCPL 5
1400 #define V_UNXCPL(x) ((x) << S_UNXCPL)
1401 #define F_UNXCPL V_UNXCPL(1U)
1402
1403 #define S_UNSREQ 4
1404 #define V_UNSREQ(x) ((x) << S_UNSREQ)
1405 #define F_UNSREQ V_UNSREQ(1U)
1406
1407 #define S_PSNREQ 3
1408 #define V_PSNREQ(x) ((x) << S_PSNREQ)
1409 #define F_PSNREQ V_PSNREQ(1U)
1410
1411 #define S_UNSCPL 2
1412 #define V_UNSCPL(x) ((x) << S_UNSCPL)
1413 #define F_UNSCPL V_UNSCPL(1U)
1414
1415 #define S_CPLABT 1
1416 #define V_CPLABT(x) ((x) << S_CPLABT)
1417 #define F_CPLABT V_CPLABT(1U)
1418
1419 #define S_PSNCPL 0
1420 #define V_PSNCPL(x) ((x) << S_PSNCPL)
1421 #define F_PSNCPL V_PSNCPL(1U)
1422
1423 #define A_PCIE_SERDES_CTRL 0xa8
1424
1425 #define S_PMASEL 3
1426 #define V_PMASEL(x) ((x) << S_PMASEL)
1427 #define F_PMASEL V_PMASEL(1U)
1428
1429 #define S_LANE 0
1430 #define M_LANE 0x7
1431 #define V_LANE(x) ((x) << S_LANE)
1432 #define G_LANE(x) (((x) >> S_LANE) & M_LANE)
1433
1434 #define A_PCIE_PIPE_CTRL 0xa8
1435
1436 #define S_RECDETUSEC 19
1437 #define M_RECDETUSEC 0x7
1438 #define V_RECDETUSEC(x) ((x) << S_RECDETUSEC)
1439 #define G_RECDETUSEC(x) (((x) >> S_RECDETUSEC) & M_RECDETUSEC)
1440
1441 #define S_PLLLCKCYC 6
1442 #define M_PLLLCKCYC 0x1fff
1443 #define V_PLLLCKCYC(x) ((x) << S_PLLLCKCYC)
1444 #define G_PLLLCKCYC(x) (((x) >> S_PLLLCKCYC) & M_PLLLCKCYC)
1445
1446 #define S_ELECIDLEDETCYC 3
1447 #define M_ELECIDLEDETCYC 0x7
1448 #define V_ELECIDLEDETCYC(x) ((x) << S_ELECIDLEDETCYC)
1449 #define G_ELECIDLEDETCYC(x) (((x) >> S_ELECIDLEDETCYC) & M_ELECIDLEDETCYC)
1450
1451 #define S_USECDRLOS 2
1452 #define V_USECDRLOS(x) ((x) << S_USECDRLOS)
1453 #define F_USECDRLOS V_USECDRLOS(1U)
1454
1455 #define S_PCLKREQINP1 1
1456 #define V_PCLKREQINP1(x) ((x) << S_PCLKREQINP1)
1457 #define F_PCLKREQINP1 V_PCLKREQINP1(1U)
1458
1459 #define S_PCLKOFFINP1 0
1460 #define V_PCLKOFFINP1(x) ((x) << S_PCLKOFFINP1)
1461 #define F_PCLKOFFINP1 V_PCLKOFFINP1(1U)
1462
1463 #define A_PCIE_SERDES_QUAD_CTRL0 0xac
1464
1465 #define S_TESTSIG 10
1466 #define M_TESTSIG 0x7ffff
1467 #define V_TESTSIG(x) ((x) << S_TESTSIG)
1468 #define G_TESTSIG(x) (((x) >> S_TESTSIG) & M_TESTSIG)
1469
1470 #define S_OFFSET 2
1471 #define M_OFFSET 0xff
1472 #define V_OFFSET(x) ((x) << S_OFFSET)
1473 #define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET)
1474
1475 #define S_OFFSETEN 1
1476 #define V_OFFSETEN(x) ((x) << S_OFFSETEN)
1477 #define F_OFFSETEN V_OFFSETEN(1U)
1478
1479 #define S_IDDQB 0
1480 #define V_IDDQB(x) ((x) << S_IDDQB)
1481 #define F_IDDQB V_IDDQB(1U)
1482
1483 #define S_MANMODE 31
1484 #define V_MANMODE(x) ((x) << S_MANMODE)
1485 #define F_MANMODE V_MANMODE(1U)
1486
1487 #define S_MANLPBKEN 29
1488 #define M_MANLPBKEN 0x3
1489 #define V_MANLPBKEN(x) ((x) << S_MANLPBKEN)
1490 #define G_MANLPBKEN(x) (((x) >> S_MANLPBKEN) & M_MANLPBKEN)
1491
1492 #define S_MANTXRECDETEN 28
1493 #define V_MANTXRECDETEN(x) ((x) << S_MANTXRECDETEN)
1494 #define F_MANTXRECDETEN V_MANTXRECDETEN(1U)
1495
1496 #define S_MANTXBEACON 27
1497 #define V_MANTXBEACON(x) ((x) << S_MANTXBEACON)
1498 #define F_MANTXBEACON V_MANTXBEACON(1U)
1499
1500 #define S_MANTXEI 26
1501 #define V_MANTXEI(x) ((x) << S_MANTXEI)
1502 #define F_MANTXEI V_MANTXEI(1U)
1503
1504 #define S_MANRXPOLARITY 25
1505 #define V_MANRXPOLARITY(x) ((x) << S_MANRXPOLARITY)
1506 #define F_MANRXPOLARITY V_MANRXPOLARITY(1U)
1507
1508 #define S_MANTXRST 24
1509 #define V_MANTXRST(x) ((x) << S_MANTXRST)
1510 #define F_MANTXRST V_MANTXRST(1U)
1511
1512 #define S_MANRXRST 23
1513 #define V_MANRXRST(x) ((x) << S_MANRXRST)
1514 #define F_MANRXRST V_MANRXRST(1U)
1515
1516 #define S_MANTXEN 22
1517 #define V_MANTXEN(x) ((x) << S_MANTXEN)
1518 #define F_MANTXEN V_MANTXEN(1U)
1519
1520 #define S_MANRXEN 21
1521 #define V_MANRXEN(x) ((x) << S_MANRXEN)
1522 #define F_MANRXEN V_MANRXEN(1U)
1523
1524 #define S_MANEN 20
1525 #define V_MANEN(x) ((x) << S_MANEN)
1526 #define F_MANEN V_MANEN(1U)
1527
1528 #define S_PCIE_CMURANGE 17
1529 #define M_PCIE_CMURANGE 0x7
1530 #define V_PCIE_CMURANGE(x) ((x) << S_PCIE_CMURANGE)
1531 #define G_PCIE_CMURANGE(x) (((x) >> S_PCIE_CMURANGE) & M_PCIE_CMURANGE)
1532
1533 #define S_PCIE_BGENB 16
1534 #define V_PCIE_BGENB(x) ((x) << S_PCIE_BGENB)
1535 #define F_PCIE_BGENB V_PCIE_BGENB(1U)
1536
1537 #define S_PCIE_ENSKPDROP 15
1538 #define V_PCIE_ENSKPDROP(x) ((x) << S_PCIE_ENSKPDROP)
1539 #define F_PCIE_ENSKPDROP V_PCIE_ENSKPDROP(1U)
1540
1541 #define S_PCIE_ENCOMMA 14
1542 #define V_PCIE_ENCOMMA(x) ((x) << S_PCIE_ENCOMMA)
1543 #define F_PCIE_ENCOMMA V_PCIE_ENCOMMA(1U)
1544
1545 #define S_PCIE_EN8B10B 13
1546 #define V_PCIE_EN8B10B(x) ((x) << S_PCIE_EN8B10B)
1547 #define F_PCIE_EN8B10B V_PCIE_EN8B10B(1U)
1548
1549 #define S_PCIE_ENELBUF 12
1550 #define V_PCIE_ENELBUF(x) ((x) << S_PCIE_ENELBUF)
1551 #define F_PCIE_ENELBUF V_PCIE_ENELBUF(1U)
1552
1553 #define S_PCIE_GAIN 7
1554 #define M_PCIE_GAIN 0x1f
1555 #define V_PCIE_GAIN(x) ((x) << S_PCIE_GAIN)
1556 #define G_PCIE_GAIN(x) (((x) >> S_PCIE_GAIN) & M_PCIE_GAIN)
1557
1558 #define S_PCIE_BANDGAP 3
1559 #define M_PCIE_BANDGAP 0xf
1560 #define V_PCIE_BANDGAP(x) ((x) << S_PCIE_BANDGAP)
1561 #define G_PCIE_BANDGAP(x) (((x) >> S_PCIE_BANDGAP) & M_PCIE_BANDGAP)
1562
1563 #define S_RXCOMADJ 2
1564 #define V_RXCOMADJ(x) ((x) << S_RXCOMADJ)
1565 #define F_RXCOMADJ V_RXCOMADJ(1U)
1566
1567 #define S_PREEMPH 0
1568 #define M_PREEMPH 0x3
1569 #define V_PREEMPH(x) ((x) << S_PREEMPH)
1570 #define G_PREEMPH(x) (((x) >> S_PREEMPH) & M_PREEMPH)
1571
1572 #define A_PCIE_SERDES_QUAD_CTRL1 0xb0
1573
1574 #define S_FASTINIT 28
1575 #define V_FASTINIT(x) ((x) << S_FASTINIT)
1576 #define F_FASTINIT V_FASTINIT(1U)
1577
1578 #define S_CTCDISABLE 27
1579 #define V_CTCDISABLE(x) ((x) << S_CTCDISABLE)
1580 #define F_CTCDISABLE V_CTCDISABLE(1U)
1581
1582 #define S_MANRESETPLL 26
1583 #define V_MANRESETPLL(x) ((x) << S_MANRESETPLL)
1584 #define F_MANRESETPLL V_MANRESETPLL(1U)
1585
1586 #define S_MANL2PWRDN 25
1587 #define V_MANL2PWRDN(x) ((x) << S_MANL2PWRDN)
1588 #define F_MANL2PWRDN V_MANL2PWRDN(1U)
1589
1590 #define S_MANQUADEN 24
1591 #define V_MANQUADEN(x) ((x) << S_MANQUADEN)
1592 #define F_MANQUADEN V_MANQUADEN(1U)
1593
1594 #define S_RXEQCTL 22
1595 #define M_RXEQCTL 0x3
1596 #define V_RXEQCTL(x) ((x) << S_RXEQCTL)
1597 #define G_RXEQCTL(x) (((x) >> S_RXEQCTL) & M_RXEQCTL)
1598
1599 #define S_HIVMODE 21
1600 #define V_HIVMODE(x) ((x) << S_HIVMODE)
1601 #define F_HIVMODE V_HIVMODE(1U)
1602
1603 #define S_REFSEL 19
1604 #define M_REFSEL 0x3
1605 #define V_REFSEL(x) ((x) << S_REFSEL)
1606 #define G_REFSEL(x) (((x) >> S_REFSEL) & M_REFSEL)
1607
1608 #define S_RXTERMADJ 17
1609 #define M_RXTERMADJ 0x3
1610 #define V_RXTERMADJ(x) ((x) << S_RXTERMADJ)
1611 #define G_RXTERMADJ(x) (((x) >> S_RXTERMADJ) & M_RXTERMADJ)
1612
1613 #define S_TXTERMADJ 15
1614 #define M_TXTERMADJ 0x3
1615 #define V_TXTERMADJ(x) ((x) << S_TXTERMADJ)
1616 #define G_TXTERMADJ(x) (((x) >> S_TXTERMADJ) & M_TXTERMADJ)
1617
1618 #define S_DEQ 11
1619 #define M_DEQ 0xf
1620 #define V_DEQ(x) ((x) << S_DEQ)
1621 #define G_DEQ(x) (((x) >> S_DEQ) & M_DEQ)
1622
1623 #define S_DTX 7
1624 #define M_DTX 0xf
1625 #define V_DTX(x) ((x) << S_DTX)
1626 #define G_DTX(x) (((x) >> S_DTX) & M_DTX)
1627
1628 #define S_LODRV 6
1629 #define V_LODRV(x) ((x) << S_LODRV)
1630 #define F_LODRV V_LODRV(1U)
1631
1632 #define S_HIDRV 5
1633 #define V_HIDRV(x) ((x) << S_HIDRV)
1634 #define F_HIDRV V_HIDRV(1U)
1635
1636 #define S_INTPARRESET 4
1637 #define V_INTPARRESET(x) ((x) << S_INTPARRESET)
1638 #define F_INTPARRESET V_INTPARRESET(1U)
1639
1640 #define S_INTPARLPBK 3
1641 #define V_INTPARLPBK(x) ((x) << S_INTPARLPBK)
1642 #define F_INTPARLPBK V_INTPARLPBK(1U)
1643
1644 #define S_INTSERLPBKWDRV 2
1645 #define V_INTSERLPBKWDRV(x) ((x) << S_INTSERLPBKWDRV)
1646 #define F_INTSERLPBKWDRV V_INTSERLPBKWDRV(1U)
1647
1648 #define S_PW 1
1649 #define V_PW(x) ((x) << S_PW)
1650 #define F_PW V_PW(1U)
1651
1652 #define S_PCLKDETECT 0
1653 #define V_PCLKDETECT(x) ((x) << S_PCLKDETECT)
1654 #define F_PCLKDETECT V_PCLKDETECT(1U)
1655
1656 #define A_PCIE_SERDES_STATUS0 0xb0
1657
1658 #define S_RXERRLANE7 21
1659 #define M_RXERRLANE7 0x7
1660 #define V_RXERRLANE7(x) ((x) << S_RXERRLANE7)
1661 #define G_RXERRLANE7(x) (((x) >> S_RXERRLANE7) & M_RXERRLANE7)
1662
1663 #define S_RXERRLANE6 18
1664 #define M_RXERRLANE6 0x7
1665 #define V_RXERRLANE6(x) ((x) << S_RXERRLANE6)
1666 #define G_RXERRLANE6(x) (((x) >> S_RXERRLANE6) & M_RXERRLANE6)
1667
1668 #define S_RXERRLANE5 15
1669 #define M_RXERRLANE5 0x7
1670 #define V_RXERRLANE5(x) ((x) << S_RXERRLANE5)
1671 #define G_RXERRLANE5(x) (((x) >> S_RXERRLANE5) & M_RXERRLANE5)
1672
1673 #define S_RXERRLANE4 12
1674 #define M_RXERRLANE4 0x7
1675 #define V_RXERRLANE4(x) ((x) << S_RXERRLANE4)
1676 #define G_RXERRLANE4(x) (((x) >> S_RXERRLANE4) & M_RXERRLANE4)
1677
1678 #define S_PCIE_RXERRLANE3 9
1679 #define M_PCIE_RXERRLANE3 0x7
1680 #define V_PCIE_RXERRLANE3(x) ((x) << S_PCIE_RXERRLANE3)
1681 #define G_PCIE_RXERRLANE3(x) (((x) >> S_PCIE_RXERRLANE3) & M_PCIE_RXERRLANE3)
1682
1683 #define S_PCIE_RXERRLANE2 6
1684 #define M_PCIE_RXERRLANE2 0x7
1685 #define V_PCIE_RXERRLANE2(x) ((x) << S_PCIE_RXERRLANE2)
1686 #define G_PCIE_RXERRLANE2(x) (((x) >> S_PCIE_RXERRLANE2) & M_PCIE_RXERRLANE2)
1687
1688 #define S_PCIE_RXERRLANE1 3
1689 #define M_PCIE_RXERRLANE1 0x7
1690 #define V_PCIE_RXERRLANE1(x) ((x) << S_PCIE_RXERRLANE1)
1691 #define G_PCIE_RXERRLANE1(x) (((x) >> S_PCIE_RXERRLANE1) & M_PCIE_RXERRLANE1)
1692
1693 #define S_PCIE_RXERRLANE0 0
1694 #define M_PCIE_RXERRLANE0 0x7
1695 #define V_PCIE_RXERRLANE0(x) ((x) << S_PCIE_RXERRLANE0)
1696 #define G_PCIE_RXERRLANE0(x) (((x) >> S_PCIE_RXERRLANE0) & M_PCIE_RXERRLANE0)
1697
1698 #define A_PCIE_SERDES_LANE_CTRL 0xb4
1699
1700 #define S_EXTBISTCHKERRCLR 22
1701 #define V_EXTBISTCHKERRCLR(x) ((x) << S_EXTBISTCHKERRCLR)
1702 #define F_EXTBISTCHKERRCLR V_EXTBISTCHKERRCLR(1U)
1703
1704 #define S_EXTBISTCHKEN 21
1705 #define V_EXTBISTCHKEN(x) ((x) << S_EXTBISTCHKEN)
1706 #define F_EXTBISTCHKEN V_EXTBISTCHKEN(1U)
1707
1708 #define S_EXTBISTGENEN 20
1709 #define V_EXTBISTGENEN(x) ((x) << S_EXTBISTGENEN)
1710 #define F_EXTBISTGENEN V_EXTBISTGENEN(1U)
1711
1712 #define S_EXTBISTPAT 17
1713 #define M_EXTBISTPAT 0x7
1714 #define V_EXTBISTPAT(x) ((x) << S_EXTBISTPAT)
1715 #define G_EXTBISTPAT(x) (((x) >> S_EXTBISTPAT) & M_EXTBISTPAT)
1716
1717 #define S_EXTPARRESET 16
1718 #define V_EXTPARRESET(x) ((x) << S_EXTPARRESET)
1719 #define F_EXTPARRESET V_EXTPARRESET(1U)
1720
1721 #define S_EXTPARLPBK 15
1722 #define V_EXTPARLPBK(x) ((x) << S_EXTPARLPBK)
1723 #define F_EXTPARLPBK V_EXTPARLPBK(1U)
1724
1725 #define S_MANRXTERMEN 14
1726 #define V_MANRXTERMEN(x) ((x) << S_MANRXTERMEN)
1727 #define F_MANRXTERMEN V_MANRXTERMEN(1U)
1728
1729 #define S_MANBEACONTXEN 13
1730 #define V_MANBEACONTXEN(x) ((x) << S_MANBEACONTXEN)
1731 #define F_MANBEACONTXEN V_MANBEACONTXEN(1U)
1732
1733 #define S_MANRXDETECTEN 12
1734 #define V_MANRXDETECTEN(x) ((x) << S_MANRXDETECTEN)
1735 #define F_MANRXDETECTEN V_MANRXDETECTEN(1U)
1736
1737 #define S_MANTXIDLEEN 11
1738 #define V_MANTXIDLEEN(x) ((x) << S_MANTXIDLEEN)
1739 #define F_MANTXIDLEEN V_MANTXIDLEEN(1U)
1740
1741 #define S_MANRXIDLEEN 10
1742 #define V_MANRXIDLEEN(x) ((x) << S_MANRXIDLEEN)
1743 #define F_MANRXIDLEEN V_MANRXIDLEEN(1U)
1744
1745 #define S_MANL1PWRDN 9
1746 #define V_MANL1PWRDN(x) ((x) << S_MANL1PWRDN)
1747 #define F_MANL1PWRDN V_MANL1PWRDN(1U)
1748
1749 #define S_MANRESET 8
1750 #define V_MANRESET(x) ((x) << S_MANRESET)
1751 #define F_MANRESET V_MANRESET(1U)
1752
1753 #define S_MANFMOFFSET 3
1754 #define M_MANFMOFFSET 0x1f
1755 #define V_MANFMOFFSET(x) ((x) << S_MANFMOFFSET)
1756 #define G_MANFMOFFSET(x) (((x) >> S_MANFMOFFSET) & M_MANFMOFFSET)
1757
1758 #define S_MANFMOFFSETEN 2
1759 #define V_MANFMOFFSETEN(x) ((x) << S_MANFMOFFSETEN)
1760 #define F_MANFMOFFSETEN V_MANFMOFFSETEN(1U)
1761
1762 #define S_MANLANEEN 1
1763 #define V_MANLANEEN(x) ((x) << S_MANLANEEN)
1764 #define F_MANLANEEN V_MANLANEEN(1U)
1765
1766 #define S_INTSERLPBK 0
1767 #define V_INTSERLPBK(x) ((x) << S_INTSERLPBK)
1768 #define F_INTSERLPBK V_INTSERLPBK(1U)
1769
1770 #define A_PCIE_SERDES_STATUS1 0xb4
1771
1772 #define S_CMULOCK 31
1773 #define V_CMULOCK(x) ((x) << S_CMULOCK)
1774 #define F_CMULOCK V_CMULOCK(1U)
1775
1776 #define S_RXKLOCKLANE7 23
1777 #define V_RXKLOCKLANE7(x) ((x) << S_RXKLOCKLANE7)
1778 #define F_RXKLOCKLANE7 V_RXKLOCKLANE7(1U)
1779
1780 #define S_RXKLOCKLANE6 22
1781 #define V_RXKLOCKLANE6(x) ((x) << S_RXKLOCKLANE6)
1782 #define F_RXKLOCKLANE6 V_RXKLOCKLANE6(1U)
1783
1784 #define S_RXKLOCKLANE5 21
1785 #define V_RXKLOCKLANE5(x) ((x) << S_RXKLOCKLANE5)
1786 #define F_RXKLOCKLANE5 V_RXKLOCKLANE5(1U)
1787
1788 #define S_RXKLOCKLANE4 20
1789 #define V_RXKLOCKLANE4(x) ((x) << S_RXKLOCKLANE4)
1790 #define F_RXKLOCKLANE4 V_RXKLOCKLANE4(1U)
1791
1792 #define S_PCIE_RXKLOCKLANE3 19
1793 #define V_PCIE_RXKLOCKLANE3(x) ((x) << S_PCIE_RXKLOCKLANE3)
1794 #define F_PCIE_RXKLOCKLANE3 V_PCIE_RXKLOCKLANE3(1U)
1795
1796 #define S_PCIE_RXKLOCKLANE2 18
1797 #define V_PCIE_RXKLOCKLANE2(x) ((x) << S_PCIE_RXKLOCKLANE2)
1798 #define F_PCIE_RXKLOCKLANE2 V_PCIE_RXKLOCKLANE2(1U)
1799
1800 #define S_PCIE_RXKLOCKLANE1 17
1801 #define V_PCIE_RXKLOCKLANE1(x) ((x) << S_PCIE_RXKLOCKLANE1)
1802 #define F_PCIE_RXKLOCKLANE1 V_PCIE_RXKLOCKLANE1(1U)
1803
1804 #define S_PCIE_RXKLOCKLANE0 16
1805 #define V_PCIE_RXKLOCKLANE0(x) ((x) << S_PCIE_RXKLOCKLANE0)
1806 #define F_PCIE_RXKLOCKLANE0 V_PCIE_RXKLOCKLANE0(1U)
1807
1808 #define S_RXUFLOWLANE7 15
1809 #define V_RXUFLOWLANE7(x) ((x) << S_RXUFLOWLANE7)
1810 #define F_RXUFLOWLANE7 V_RXUFLOWLANE7(1U)
1811
1812 #define S_RXUFLOWLANE6 14
1813 #define V_RXUFLOWLANE6(x) ((x) << S_RXUFLOWLANE6)
1814 #define F_RXUFLOWLANE6 V_RXUFLOWLANE6(1U)
1815
1816 #define S_RXUFLOWLANE5 13
1817 #define V_RXUFLOWLANE5(x) ((x) << S_RXUFLOWLANE5)
1818 #define F_RXUFLOWLANE5 V_RXUFLOWLANE5(1U)
1819
1820 #define S_RXUFLOWLANE4 12
1821 #define V_RXUFLOWLANE4(x) ((x) << S_RXUFLOWLANE4)
1822 #define F_RXUFLOWLANE4 V_RXUFLOWLANE4(1U)
1823
1824 #define S_PCIE_RXUFLOWLANE3 11
1825 #define V_PCIE_RXUFLOWLANE3(x) ((x) << S_PCIE_RXUFLOWLANE3)
1826 #define F_PCIE_RXUFLOWLANE3 V_PCIE_RXUFLOWLANE3(1U)
1827
1828 #define S_PCIE_RXUFLOWLANE2 10
1829 #define V_PCIE_RXUFLOWLANE2(x) ((x) << S_PCIE_RXUFLOWLANE2)
1830 #define F_PCIE_RXUFLOWLANE2 V_PCIE_RXUFLOWLANE2(1U)
1831
1832 #define S_PCIE_RXUFLOWLANE1 9
1833 #define V_PCIE_RXUFLOWLANE1(x) ((x) << S_PCIE_RXUFLOWLANE1)
1834 #define F_PCIE_RXUFLOWLANE1 V_PCIE_RXUFLOWLANE1(1U)
1835
1836 #define S_PCIE_RXUFLOWLANE0 8
1837 #define V_PCIE_RXUFLOWLANE0(x) ((x) << S_PCIE_RXUFLOWLANE0)
1838 #define F_PCIE_RXUFLOWLANE0 V_PCIE_RXUFLOWLANE0(1U)
1839
1840 #define S_RXOFLOWLANE7 7
1841 #define V_RXOFLOWLANE7(x) ((x) << S_RXOFLOWLANE7)
1842 #define F_RXOFLOWLANE7 V_RXOFLOWLANE7(1U)
1843
1844 #define S_RXOFLOWLANE6 6
1845 #define V_RXOFLOWLANE6(x) ((x) << S_RXOFLOWLANE6)
1846 #define F_RXOFLOWLANE6 V_RXOFLOWLANE6(1U)
1847
1848 #define S_RXOFLOWLANE5 5
1849 #define V_RXOFLOWLANE5(x) ((x) << S_RXOFLOWLANE5)
1850 #define F_RXOFLOWLANE5 V_RXOFLOWLANE5(1U)
1851
1852 #define S_RXOFLOWLANE4 4
1853 #define V_RXOFLOWLANE4(x) ((x) << S_RXOFLOWLANE4)
1854 #define F_RXOFLOWLANE4 V_RXOFLOWLANE4(1U)
1855
1856 #define S_PCIE_RXOFLOWLANE3 3
1857 #define V_PCIE_RXOFLOWLANE3(x) ((x) << S_PCIE_RXOFLOWLANE3)
1858 #define F_PCIE_RXOFLOWLANE3 V_PCIE_RXOFLOWLANE3(1U)
1859
1860 #define S_PCIE_RXOFLOWLANE2 2
1861 #define V_PCIE_RXOFLOWLANE2(x) ((x) << S_PCIE_RXOFLOWLANE2)
1862 #define F_PCIE_RXOFLOWLANE2 V_PCIE_RXOFLOWLANE2(1U)
1863
1864 #define S_PCIE_RXOFLOWLANE1 1
1865 #define V_PCIE_RXOFLOWLANE1(x) ((x) << S_PCIE_RXOFLOWLANE1)
1866 #define F_PCIE_RXOFLOWLANE1 V_PCIE_RXOFLOWLANE1(1U)
1867
1868 #define S_PCIE_RXOFLOWLANE0 0
1869 #define V_PCIE_RXOFLOWLANE0(x) ((x) << S_PCIE_RXOFLOWLANE0)
1870 #define F_PCIE_RXOFLOWLANE0 V_PCIE_RXOFLOWLANE0(1U)
1871
1872 #define A_PCIE_SERDES_LANE_STAT 0xb8
1873
1874 #define S_EXTBISTCHKERRCNT 8
1875 #define M_EXTBISTCHKERRCNT 0xffffff
1876 #define V_EXTBISTCHKERRCNT(x) ((x) << S_EXTBISTCHKERRCNT)
1877 #define G_EXTBISTCHKERRCNT(x) (((x) >> S_EXTBISTCHKERRCNT) & M_EXTBISTCHKERRCNT)
1878
1879 #define S_EXTBISTCHKFMD 7
1880 #define V_EXTBISTCHKFMD(x) ((x) << S_EXTBISTCHKFMD)
1881 #define F_EXTBISTCHKFMD V_EXTBISTCHKFMD(1U)
1882
1883 #define S_BEACONDETECTCHG 6
1884 #define V_BEACONDETECTCHG(x) ((x) << S_BEACONDETECTCHG)
1885 #define F_BEACONDETECTCHG V_BEACONDETECTCHG(1U)
1886
1887 #define S_RXDETECTCHG 5
1888 #define V_RXDETECTCHG(x) ((x) << S_RXDETECTCHG)
1889 #define F_RXDETECTCHG V_RXDETECTCHG(1U)
1890
1891 #define S_TXIDLEDETECTCHG 4
1892 #define V_TXIDLEDETECTCHG(x) ((x) << S_TXIDLEDETECTCHG)
1893 #define F_TXIDLEDETECTCHG V_TXIDLEDETECTCHG(1U)
1894
1895 #define S_BEACONDETECT 2
1896 #define V_BEACONDETECT(x) ((x) << S_BEACONDETECT)
1897 #define F_BEACONDETECT V_BEACONDETECT(1U)
1898
1899 #define S_RXDETECT 1
1900 #define V_RXDETECT(x) ((x) << S_RXDETECT)
1901 #define F_RXDETECT V_RXDETECT(1U)
1902
1903 #define S_TXIDLEDETECT 0
1904 #define V_TXIDLEDETECT(x) ((x) << S_TXIDLEDETECT)
1905 #define F_TXIDLEDETECT V_TXIDLEDETECT(1U)
1906
1907 #define A_PCIE_SERDES_STATUS2 0xb8
1908
1909 #define S_TXRECDETLANE7 31
1910 #define V_TXRECDETLANE7(x) ((x) << S_TXRECDETLANE7)
1911 #define F_TXRECDETLANE7 V_TXRECDETLANE7(1U)
1912
1913 #define S_TXRECDETLANE6 30
1914 #define V_TXRECDETLANE6(x) ((x) << S_TXRECDETLANE6)
1915 #define F_TXRECDETLANE6 V_TXRECDETLANE6(1U)
1916
1917 #define S_TXRECDETLANE5 29
1918 #define V_TXRECDETLANE5(x) ((x) << S_TXRECDETLANE5)
1919 #define F_TXRECDETLANE5 V_TXRECDETLANE5(1U)
1920
1921 #define S_TXRECDETLANE4 28
1922 #define V_TXRECDETLANE4(x) ((x) << S_TXRECDETLANE4)
1923 #define F_TXRECDETLANE4 V_TXRECDETLANE4(1U)
1924
1925 #define S_TXRECDETLANE3 27
1926 #define V_TXRECDETLANE3(x) ((x) << S_TXRECDETLANE3)
1927 #define F_TXRECDETLANE3 V_TXRECDETLANE3(1U)
1928
1929 #define S_TXRECDETLANE2 26
1930 #define V_TXRECDETLANE2(x) ((x) << S_TXRECDETLANE2)
1931 #define F_TXRECDETLANE2 V_TXRECDETLANE2(1U)
1932
1933 #define S_TXRECDETLANE1 25
1934 #define V_TXRECDETLANE1(x) ((x) << S_TXRECDETLANE1)
1935 #define F_TXRECDETLANE1 V_TXRECDETLANE1(1U)
1936
1937 #define S_TXRECDETLANE0 24
1938 #define V_TXRECDETLANE0(x) ((x) << S_TXRECDETLANE0)
1939 #define F_TXRECDETLANE0 V_TXRECDETLANE0(1U)
1940
1941 #define S_RXEIDLANE7 23
1942 #define V_RXEIDLANE7(x) ((x) << S_RXEIDLANE7)
1943 #define F_RXEIDLANE7 V_RXEIDLANE7(1U)
1944
1945 #define S_RXEIDLANE6 22
1946 #define V_RXEIDLANE6(x) ((x) << S_RXEIDLANE6)
1947 #define F_RXEIDLANE6 V_RXEIDLANE6(1U)
1948
1949 #define S_RXEIDLANE5 21
1950 #define V_RXEIDLANE5(x) ((x) << S_RXEIDLANE5)
1951 #define F_RXEIDLANE5 V_RXEIDLANE5(1U)
1952
1953 #define S_RXEIDLANE4 20
1954 #define V_RXEIDLANE4(x) ((x) << S_RXEIDLANE4)
1955 #define F_RXEIDLANE4 V_RXEIDLANE4(1U)
1956
1957 #define S_RXEIDLANE3 19
1958 #define V_RXEIDLANE3(x) ((x) << S_RXEIDLANE3)
1959 #define F_RXEIDLANE3 V_RXEIDLANE3(1U)
1960
1961 #define S_RXEIDLANE2 18
1962 #define V_RXEIDLANE2(x) ((x) << S_RXEIDLANE2)
1963 #define F_RXEIDLANE2 V_RXEIDLANE2(1U)
1964
1965 #define S_RXEIDLANE1 17
1966 #define V_RXEIDLANE1(x) ((x) << S_RXEIDLANE1)
1967 #define F_RXEIDLANE1 V_RXEIDLANE1(1U)
1968
1969 #define S_RXEIDLANE0 16
1970 #define V_RXEIDLANE0(x) ((x) << S_RXEIDLANE0)
1971 #define F_RXEIDLANE0 V_RXEIDLANE0(1U)
1972
1973 #define S_RXREMSKIPLANE7 15
1974 #define V_RXREMSKIPLANE7(x) ((x) << S_RXREMSKIPLANE7)
1975 #define F_RXREMSKIPLANE7 V_RXREMSKIPLANE7(1U)
1976
1977 #define S_RXREMSKIPLANE6 14
1978 #define V_RXREMSKIPLANE6(x) ((x) << S_RXREMSKIPLANE6)
1979 #define F_RXREMSKIPLANE6 V_RXREMSKIPLANE6(1U)
1980
1981 #define S_RXREMSKIPLANE5 13
1982 #define V_RXREMSKIPLANE5(x) ((x) << S_RXREMSKIPLANE5)
1983 #define F_RXREMSKIPLANE5 V_RXREMSKIPLANE5(1U)
1984
1985 #define S_RXREMSKIPLANE4 12
1986 #define V_RXREMSKIPLANE4(x) ((x) << S_RXREMSKIPLANE4)
1987 #define F_RXREMSKIPLANE4 V_RXREMSKIPLANE4(1U)
1988
1989 #define S_PCIE_RXREMSKIPLANE3 11
1990 #define V_PCIE_RXREMSKIPLANE3(x) ((x) << S_PCIE_RXREMSKIPLANE3)
1991 #define F_PCIE_RXREMSKIPLANE3 V_PCIE_RXREMSKIPLANE3(1U)
1992
1993 #define S_PCIE_RXREMSKIPLANE2 10
1994 #define V_PCIE_RXREMSKIPLANE2(x) ((x) << S_PCIE_RXREMSKIPLANE2)
1995 #define F_PCIE_RXREMSKIPLANE2 V_PCIE_RXREMSKIPLANE2(1U)
1996
1997 #define S_PCIE_RXREMSKIPLANE1 9
1998 #define V_PCIE_RXREMSKIPLANE1(x) ((x) << S_PCIE_RXREMSKIPLANE1)
1999 #define F_PCIE_RXREMSKIPLANE1 V_PCIE_RXREMSKIPLANE1(1U)
2000
2001 #define S_PCIE_RXREMSKIPLANE0 8
2002 #define V_PCIE_RXREMSKIPLANE0(x) ((x) << S_PCIE_RXREMSKIPLANE0)
2003 #define F_PCIE_RXREMSKIPLANE0 V_PCIE_RXREMSKIPLANE0(1U)
2004
2005 #define S_RXADDSKIPLANE7 7
2006 #define V_RXADDSKIPLANE7(x) ((x) << S_RXADDSKIPLANE7)
2007 #define F_RXADDSKIPLANE7 V_RXADDSKIPLANE7(1U)
2008
2009 #define S_RXADDSKIPLANE6 6
2010 #define V_RXADDSKIPLANE6(x) ((x) << S_RXADDSKIPLANE6)
2011 #define F_RXADDSKIPLANE6 V_RXADDSKIPLANE6(1U)
2012
2013 #define S_RXADDSKIPLANE5 5
2014 #define V_RXADDSKIPLANE5(x) ((x) << S_RXADDSKIPLANE5)
2015 #define F_RXADDSKIPLANE5 V_RXADDSKIPLANE5(1U)
2016
2017 #define S_RXADDSKIPLANE4 4
2018 #define V_RXADDSKIPLANE4(x) ((x) << S_RXADDSKIPLANE4)
2019 #define F_RXADDSKIPLANE4 V_RXADDSKIPLANE4(1U)
2020
2021 #define S_PCIE_RXADDSKIPLANE3 3
2022 #define V_PCIE_RXADDSKIPLANE3(x) ((x) << S_PCIE_RXADDSKIPLANE3)
2023 #define F_PCIE_RXADDSKIPLANE3 V_PCIE_RXADDSKIPLANE3(1U)
2024
2025 #define S_PCIE_RXADDSKIPLANE2 2
2026 #define V_PCIE_RXADDSKIPLANE2(x) ((x) << S_PCIE_RXADDSKIPLANE2)
2027 #define F_PCIE_RXADDSKIPLANE2 V_PCIE_RXADDSKIPLANE2(1U)
2028
2029 #define S_PCIE_RXADDSKIPLANE1 1
2030 #define V_PCIE_RXADDSKIPLANE1(x) ((x) << S_PCIE_RXADDSKIPLANE1)
2031 #define F_PCIE_RXADDSKIPLANE1 V_PCIE_RXADDSKIPLANE1(1U)
2032
2033 #define S_PCIE_RXADDSKIPLANE0 0
2034 #define V_PCIE_RXADDSKIPLANE0(x) ((x) << S_PCIE_RXADDSKIPLANE0)
2035 #define F_PCIE_RXADDSKIPLANE0 V_PCIE_RXADDSKIPLANE0(1U)
2036
2037 #define A_PCIE_PEX_WMARK 0xbc
2038
2039 #define S_P_WMARK 18
2040 #define M_P_WMARK 0x7ff
2041 #define V_P_WMARK(x) ((x) << S_P_WMARK)
2042 #define G_P_WMARK(x) (((x) >> S_P_WMARK) & M_P_WMARK)
2043
2044 #define S_NP_WMARK 11
2045 #define M_NP_WMARK 0x7f
2046 #define V_NP_WMARK(x) ((x) << S_NP_WMARK)
2047 #define G_NP_WMARK(x) (((x) >> S_NP_WMARK) & M_NP_WMARK)
2048
2049 #define S_CPL_WMARK 0
2050 #define M_CPL_WMARK 0x7ff
2051 #define V_CPL_WMARK(x) ((x) << S_CPL_WMARK)
2052 #define G_CPL_WMARK(x) (((x) >> S_CPL_WMARK) & M_CPL_WMARK)
2053
2054 #define A_PCIE_SERDES_BIST 0xbc
2055
2056 #define S_PCIE_BISTDONE 24
2057 #define M_PCIE_BISTDONE 0xff
2058 #define V_PCIE_BISTDONE(x) ((x) << S_PCIE_BISTDONE)
2059 #define G_PCIE_BISTDONE(x) (((x) >> S_PCIE_BISTDONE) & M_PCIE_BISTDONE)
2060
2061 #define S_PCIE_BISTCYCLETHRESH 3
2062 #define M_PCIE_BISTCYCLETHRESH 0xffff
2063 #define V_PCIE_BISTCYCLETHRESH(x) ((x) << S_PCIE_BISTCYCLETHRESH)
2064 #define G_PCIE_BISTCYCLETHRESH(x) (((x) >> S_PCIE_BISTCYCLETHRESH) & M_PCIE_BISTCYCLETHRESH)
2065
2066 #define S_BISTMODE 0
2067 #define M_BISTMODE 0x7
2068 #define V_BISTMODE(x) ((x) << S_BISTMODE)
2069 #define G_BISTMODE(x) (((x) >> S_BISTMODE) & M_BISTMODE)
2070
2071 /* registers for module T3DBG */
2072 #define T3DBG_BASE_ADDR 0xc0
2073
2074 #define A_T3DBG_DBG0_CFG 0xc0
2075
2076 #define S_REGSELECT 9
2077 #define M_REGSELECT 0xff
2078 #define V_REGSELECT(x) ((x) << S_REGSELECT)
2079 #define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT)
2080
2081 #define S_MODULESELECT 4
2082 #define M_MODULESELECT 0x1f
2083 #define V_MODULESELECT(x) ((x) << S_MODULESELECT)
2084 #define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT)
2085
2086 #define S_CLKSELECT 0
2087 #define M_CLKSELECT 0xf
2088 #define V_CLKSELECT(x) ((x) << S_CLKSELECT)
2089 #define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT)
2090
2091 #define A_T3DBG_DBG0_EN 0xc4
2092
2093 #define S_SDRBYTE0 8
2094 #define V_SDRBYTE0(x) ((x) << S_SDRBYTE0)
2095 #define F_SDRBYTE0 V_SDRBYTE0(1U)
2096
2097 #define S_DDREN 4
2098 #define V_DDREN(x) ((x) << S_DDREN)
2099 #define F_DDREN V_DDREN(1U)
2100
2101 #define S_PORTEN 0
2102 #define V_PORTEN(x) ((x) << S_PORTEN)
2103 #define F_PORTEN V_PORTEN(1U)
2104
2105 #define A_T3DBG_DBG1_CFG 0xc8
2106 #define A_T3DBG_DBG1_EN 0xcc
2107 #define A_T3DBG_GPIO_EN 0xd0
2108
2109 #define S_GPIO11_OEN 27
2110 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
2111 #define F_GPIO11_OEN V_GPIO11_OEN(1U)
2112
2113 #define S_GPIO10_OEN 26
2114 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
2115 #define F_GPIO10_OEN V_GPIO10_OEN(1U)
2116
2117 #define S_GPIO9_OEN 25
2118 #define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN)
2119 #define F_GPIO9_OEN V_GPIO9_OEN(1U)
2120
2121 #define S_GPIO8_OEN 24
2122 #define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN)
2123 #define F_GPIO8_OEN V_GPIO8_OEN(1U)
2124
2125 #define S_GPIO7_OEN 23
2126 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
2127 #define F_GPIO7_OEN V_GPIO7_OEN(1U)
2128
2129 #define S_GPIO6_OEN 22
2130 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
2131 #define F_GPIO6_OEN V_GPIO6_OEN(1U)
2132
2133 #define S_GPIO5_OEN 21
2134 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
2135 #define F_GPIO5_OEN V_GPIO5_OEN(1U)
2136
2137 #define S_GPIO4_OEN 20
2138 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
2139 #define F_GPIO4_OEN V_GPIO4_OEN(1U)
2140
2141 #define S_GPIO3_OEN 19
2142 #define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN)
2143 #define F_GPIO3_OEN V_GPIO3_OEN(1U)
2144
2145 #define S_GPIO2_OEN 18
2146 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
2147 #define F_GPIO2_OEN V_GPIO2_OEN(1U)
2148
2149 #define S_GPIO1_OEN 17
2150 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
2151 #define F_GPIO1_OEN V_GPIO1_OEN(1U)
2152
2153 #define S_GPIO0_OEN 16
2154 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
2155 #define F_GPIO0_OEN V_GPIO0_OEN(1U)
2156
2157 #define S_GPIO11_OUT_VAL 11
2158 #define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL)
2159 #define F_GPIO11_OUT_VAL V_GPIO11_OUT_VAL(1U)
2160
2161 #define S_GPIO10_OUT_VAL 10
2162 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
2163 #define F_GPIO10_OUT_VAL V_GPIO10_OUT_VAL(1U)
2164
2165 #define S_GPIO9_OUT_VAL 9
2166 #define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL)
2167 #define F_GPIO9_OUT_VAL V_GPIO9_OUT_VAL(1U)
2168
2169 #define S_GPIO8_OUT_VAL 8
2170 #define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL)
2171 #define F_GPIO8_OUT_VAL V_GPIO8_OUT_VAL(1U)
2172
2173 #define S_GPIO7_OUT_VAL 7
2174 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
2175 #define F_GPIO7_OUT_VAL V_GPIO7_OUT_VAL(1U)
2176
2177 #define S_GPIO6_OUT_VAL 6
2178 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
2179 #define F_GPIO6_OUT_VAL V_GPIO6_OUT_VAL(1U)
2180
2181 #define S_GPIO5_OUT_VAL 5
2182 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
2183 #define F_GPIO5_OUT_VAL V_GPIO5_OUT_VAL(1U)
2184
2185 #define S_GPIO4_OUT_VAL 4
2186 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
2187 #define F_GPIO4_OUT_VAL V_GPIO4_OUT_VAL(1U)
2188
2189 #define S_GPIO3_OUT_VAL 3
2190 #define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL)
2191 #define F_GPIO3_OUT_VAL V_GPIO3_OUT_VAL(1U)
2192
2193 #define S_GPIO2_OUT_VAL 2
2194 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
2195 #define F_GPIO2_OUT_VAL V_GPIO2_OUT_VAL(1U)
2196
2197 #define S_GPIO1_OUT_VAL 1
2198 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
2199 #define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U)
2200
2201 #define S_GPIO0_OUT_VAL 0
2202 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
2203 #define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U)
2204
2205 #define A_T3DBG_GPIO_IN 0xd4
2206
2207 #define S_GPIO11_CHG_DET 27
2208 #define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET)
2209 #define F_GPIO11_CHG_DET V_GPIO11_CHG_DET(1U)
2210
2211 #define S_GPIO10_CHG_DET 26
2212 #define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET)
2213 #define F_GPIO10_CHG_DET V_GPIO10_CHG_DET(1U)
2214
2215 #define S_GPIO9_CHG_DET 25
2216 #define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET)
2217 #define F_GPIO9_CHG_DET V_GPIO9_CHG_DET(1U)
2218
2219 #define S_GPIO8_CHG_DET 24
2220 #define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET)
2221 #define F_GPIO8_CHG_DET V_GPIO8_CHG_DET(1U)
2222
2223 #define S_GPIO7_CHG_DET 23
2224 #define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET)
2225 #define F_GPIO7_CHG_DET V_GPIO7_CHG_DET(1U)
2226
2227 #define S_GPIO6_CHG_DET 22
2228 #define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET)
2229 #define F_GPIO6_CHG_DET V_GPIO6_CHG_DET(1U)
2230
2231 #define S_GPIO5_CHG_DET 21
2232 #define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET)
2233 #define F_GPIO5_CHG_DET V_GPIO5_CHG_DET(1U)
2234
2235 #define S_GPIO4_CHG_DET 20
2236 #define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET)
2237 #define F_GPIO4_CHG_DET V_GPIO4_CHG_DET(1U)
2238
2239 #define S_GPIO3_CHG_DET 19
2240 #define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET)
2241 #define F_GPIO3_CHG_DET V_GPIO3_CHG_DET(1U)
2242
2243 #define S_GPIO2_CHG_DET 18
2244 #define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET)
2245 #define F_GPIO2_CHG_DET V_GPIO2_CHG_DET(1U)
2246
2247 #define S_GPIO1_CHG_DET 17
2248 #define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET)
2249 #define F_GPIO1_CHG_DET V_GPIO1_CHG_DET(1U)
2250
2251 #define S_GPIO0_CHG_DET 16
2252 #define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET)
2253 #define F_GPIO0_CHG_DET V_GPIO0_CHG_DET(1U)
2254
2255 #define S_GPIO11_IN 11
2256 #define V_GPIO11_IN(x) ((x) << S_GPIO11_IN)
2257 #define F_GPIO11_IN V_GPIO11_IN(1U)
2258
2259 #define S_GPIO10_IN 10
2260 #define V_GPIO10_IN(x) ((x) << S_GPIO10_IN)
2261 #define F_GPIO10_IN V_GPIO10_IN(1U)
2262
2263 #define S_GPIO9_IN 9
2264 #define V_GPIO9_IN(x) ((x) << S_GPIO9_IN)
2265 #define F_GPIO9_IN V_GPIO9_IN(1U)
2266
2267 #define S_GPIO8_IN 8
2268 #define V_GPIO8_IN(x) ((x) << S_GPIO8_IN)
2269 #define F_GPIO8_IN V_GPIO8_IN(1U)
2270
2271 #define S_GPIO7_IN 7
2272 #define V_GPIO7_IN(x) ((x) << S_GPIO7_IN)
2273 #define F_GPIO7_IN V_GPIO7_IN(1U)
2274
2275 #define S_GPIO6_IN 6
2276 #define V_GPIO6_IN(x) ((x) << S_GPIO6_IN)
2277 #define F_GPIO6_IN V_GPIO6_IN(1U)
2278
2279 #define S_GPIO5_IN 5
2280 #define V_GPIO5_IN(x) ((x) << S_GPIO5_IN)
2281 #define F_GPIO5_IN V_GPIO5_IN(1U)
2282
2283 #define S_GPIO4_IN 4
2284 #define V_GPIO4_IN(x) ((x) << S_GPIO4_IN)
2285 #define F_GPIO4_IN V_GPIO4_IN(1U)
2286
2287 #define S_GPIO3_IN 3
2288 #define V_GPIO3_IN(x) ((x) << S_GPIO3_IN)
2289 #define F_GPIO3_IN V_GPIO3_IN(1U)
2290
2291 #define S_GPIO2_IN 2
2292 #define V_GPIO2_IN(x) ((x) << S_GPIO2_IN)
2293 #define F_GPIO2_IN V_GPIO2_IN(1U)
2294
2295 #define S_GPIO1_IN 1
2296 #define V_GPIO1_IN(x) ((x) << S_GPIO1_IN)
2297 #define F_GPIO1_IN V_GPIO1_IN(1U)
2298
2299 #define S_GPIO0_IN 0
2300 #define V_GPIO0_IN(x) ((x) << S_GPIO0_IN)
2301 #define F_GPIO0_IN V_GPIO0_IN(1U)
2302
2303 #define A_T3DBG_INT_ENABLE 0xd8
2304
2305 #define S_C_LOCK 21
2306 #define V_C_LOCK(x) ((x) << S_C_LOCK)
2307 #define F_C_LOCK V_C_LOCK(1U)
2308
2309 #define S_M_LOCK 20
2310 #define V_M_LOCK(x) ((x) << S_M_LOCK)
2311 #define F_M_LOCK V_M_LOCK(1U)
2312
2313 #define S_U_LOCK 19
2314 #define V_U_LOCK(x) ((x) << S_U_LOCK)
2315 #define F_U_LOCK V_U_LOCK(1U)
2316
2317 #define S_R_LOCK 18
2318 #define V_R_LOCK(x) ((x) << S_R_LOCK)
2319 #define F_R_LOCK V_R_LOCK(1U)
2320
2321 #define S_PX_LOCK 17
2322 #define V_PX_LOCK(x) ((x) << S_PX_LOCK)
2323 #define F_PX_LOCK V_PX_LOCK(1U)
2324
2325 #define S_GPIO11 11
2326 #define V_GPIO11(x) ((x) << S_GPIO11)
2327 #define F_GPIO11 V_GPIO11(1U)
2328
2329 #define S_GPIO10 10
2330 #define V_GPIO10(x) ((x) << S_GPIO10)
2331 #define F_GPIO10 V_GPIO10(1U)
2332
2333 #define S_GPIO9 9
2334 #define V_GPIO9(x) ((x) << S_GPIO9)
2335 #define F_GPIO9 V_GPIO9(1U)
2336
2337 #define S_GPIO8 8
2338 #define V_GPIO8(x) ((x) << S_GPIO8)
2339 #define F_GPIO8 V_GPIO8(1U)
2340
2341 #define S_GPIO7 7
2342 #define V_GPIO7(x) ((x) << S_GPIO7)
2343 #define F_GPIO7 V_GPIO7(1U)
2344
2345 #define S_GPIO6 6
2346 #define V_GPIO6(x) ((x) << S_GPIO6)
2347 #define F_GPIO6 V_GPIO6(1U)
2348
2349 #define S_GPIO5 5
2350 #define V_GPIO5(x) ((x) << S_GPIO5)
2351 #define F_GPIO5 V_GPIO5(1U)
2352
2353 #define S_GPIO4 4
2354 #define V_GPIO4(x) ((x) << S_GPIO4)
2355 #define F_GPIO4 V_GPIO4(1U)
2356
2357 #define S_GPIO3 3
2358 #define V_GPIO3(x) ((x) << S_GPIO3)
2359 #define F_GPIO3 V_GPIO3(1U)
2360
2361 #define S_GPIO2 2
2362 #define V_GPIO2(x) ((x) << S_GPIO2)
2363 #define F_GPIO2 V_GPIO2(1U)
2364
2365 #define S_GPIO1 1
2366 #define V_GPIO1(x) ((x) << S_GPIO1)
2367 #define F_GPIO1 V_GPIO1(1U)
2368
2369 #define S_GPIO0 0
2370 #define V_GPIO0(x) ((x) << S_GPIO0)
2371 #define F_GPIO0 V_GPIO0(1U)
2372
2373 #define S_PE_LOCK 16
2374 #define V_PE_LOCK(x) ((x) << S_PE_LOCK)
2375 #define F_PE_LOCK V_PE_LOCK(1U)
2376
2377 #define A_T3DBG_INT_CAUSE 0xdc
2378 #define A_T3DBG_DBG0_RST_VALUE 0xe0
2379
2380 #define S_DEBUGDATA 0
2381 #define M_DEBUGDATA 0xff
2382 #define V_DEBUGDATA(x) ((x) << S_DEBUGDATA)
2383 #define G_DEBUGDATA(x) (((x) >> S_DEBUGDATA) & M_DEBUGDATA)
2384
2385 #define A_T3DBG_PLL_OCLK_PAD_EN 0xe4
2386
2387 #define S_PCIE_OCLK_EN 20
2388 #define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN)
2389 #define F_PCIE_OCLK_EN V_PCIE_OCLK_EN(1U)
2390
2391 #define S_PCLKTREE_DBG_EN 17
2392 #define V_PCLKTREE_DBG_EN(x) ((x) << S_PCLKTREE_DBG_EN)
2393 #define F_PCLKTREE_DBG_EN V_PCLKTREE_DBG_EN(1U)
2394
2395 #define S_PCIX_OCLK_EN 16
2396 #define V_PCIX_OCLK_EN(x) ((x) << S_PCIX_OCLK_EN)
2397 #define F_PCIX_OCLK_EN V_PCIX_OCLK_EN(1U)
2398
2399 #define S_U_OCLK_EN 12
2400 #define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN)
2401 #define F_U_OCLK_EN V_U_OCLK_EN(1U)
2402
2403 #define S_R_OCLK_EN 8
2404 #define V_R_OCLK_EN(x) ((x) << S_R_OCLK_EN)
2405 #define F_R_OCLK_EN V_R_OCLK_EN(1U)
2406
2407 #define S_M_OCLK_EN 4
2408 #define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN)
2409 #define F_M_OCLK_EN V_M_OCLK_EN(1U)
2410
2411 #define S_C_OCLK_EN 0
2412 #define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN)
2413 #define F_C_OCLK_EN V_C_OCLK_EN(1U)
2414
2415 #define A_T3DBG_PLL_LOCK 0xe8
2416
2417 #define S_PCIX_LOCK 16
2418 #define V_PCIX_LOCK(x) ((x) << S_PCIX_LOCK)
2419 #define F_PCIX_LOCK V_PCIX_LOCK(1U)
2420
2421 #define S_PLL_U_LOCK 12
2422 #define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK)
2423 #define F_PLL_U_LOCK V_PLL_U_LOCK(1U)
2424
2425 #define S_PLL_R_LOCK 8
2426 #define V_PLL_R_LOCK(x) ((x) << S_PLL_R_LOCK)
2427 #define F_PLL_R_LOCK V_PLL_R_LOCK(1U)
2428
2429 #define S_PLL_M_LOCK 4
2430 #define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK)
2431 #define F_PLL_M_LOCK V_PLL_M_LOCK(1U)
2432
2433 #define S_PLL_C_LOCK 0
2434 #define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK)
2435 #define F_PLL_C_LOCK V_PLL_C_LOCK(1U)
2436
2437 #define S_PCIE_LOCK 20
2438 #define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK)
2439 #define F_PCIE_LOCK V_PCIE_LOCK(1U)
2440
2441 #define A_T3DBG_SERDES_RBC_CFG 0xec
2442
2443 #define S_X_RBC_LANE_SEL 16
2444 #define M_X_RBC_LANE_SEL 0x3
2445 #define V_X_RBC_LANE_SEL(x) ((x) << S_X_RBC_LANE_SEL)
2446 #define G_X_RBC_LANE_SEL(x) (((x) >> S_X_RBC_LANE_SEL) & M_X_RBC_LANE_SEL)
2447
2448 #define S_X_RBC_DBG_EN 12
2449 #define V_X_RBC_DBG_EN(x) ((x) << S_X_RBC_DBG_EN)
2450 #define F_X_RBC_DBG_EN V_X_RBC_DBG_EN(1U)
2451
2452 #define S_X_SERDES_SEL 8
2453 #define V_X_SERDES_SEL(x) ((x) << S_X_SERDES_SEL)
2454 #define F_X_SERDES_SEL V_X_SERDES_SEL(1U)
2455
2456 #define S_PE_RBC_LANE_SEL 4
2457 #define M_PE_RBC_LANE_SEL 0x7
2458 #define V_PE_RBC_LANE_SEL(x) ((x) << S_PE_RBC_LANE_SEL)
2459 #define G_PE_RBC_LANE_SEL(x) (((x) >> S_PE_RBC_LANE_SEL) & M_PE_RBC_LANE_SEL)
2460
2461 #define S_PE_RBC_DBG_EN 0
2462 #define V_PE_RBC_DBG_EN(x) ((x) << S_PE_RBC_DBG_EN)
2463 #define F_PE_RBC_DBG_EN V_PE_RBC_DBG_EN(1U)
2464
2465 #define A_T3DBG_GPIO_ACT_LOW 0xf0
2466
2467 #define S_C_LOCK_ACT_LOW 21
2468 #define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW)
2469 #define F_C_LOCK_ACT_LOW V_C_LOCK_ACT_LOW(1U)
2470
2471 #define S_M_LOCK_ACT_LOW 20
2472 #define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW)
2473 #define F_M_LOCK_ACT_LOW V_M_LOCK_ACT_LOW(1U)
2474
2475 #define S_U_LOCK_ACT_LOW 19
2476 #define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW)
2477 #define F_U_LOCK_ACT_LOW V_U_LOCK_ACT_LOW(1U)
2478
2479 #define S_R_LOCK_ACT_LOW 18
2480 #define V_R_LOCK_ACT_LOW(x) ((x) << S_R_LOCK_ACT_LOW)
2481 #define F_R_LOCK_ACT_LOW V_R_LOCK_ACT_LOW(1U)
2482
2483 #define S_PX_LOCK_ACT_LOW 17
2484 #define V_PX_LOCK_ACT_LOW(x) ((x) << S_PX_LOCK_ACT_LOW)
2485 #define F_PX_LOCK_ACT_LOW V_PX_LOCK_ACT_LOW(1U)
2486
2487 #define S_GPIO11_ACT_LOW 11
2488 #define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW)
2489 #define F_GPIO11_ACT_LOW V_GPIO11_ACT_LOW(1U)
2490
2491 #define S_GPIO10_ACT_LOW 10
2492 #define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW)
2493 #define F_GPIO10_ACT_LOW V_GPIO10_ACT_LOW(1U)
2494
2495 #define S_GPIO9_ACT_LOW 9
2496 #define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW)
2497 #define F_GPIO9_ACT_LOW V_GPIO9_ACT_LOW(1U)
2498
2499 #define S_GPIO8_ACT_LOW 8
2500 #define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW)
2501 #define F_GPIO8_ACT_LOW V_GPIO8_ACT_LOW(1U)
2502
2503 #define S_GPIO7_ACT_LOW 7
2504 #define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW)
2505 #define F_GPIO7_ACT_LOW V_GPIO7_ACT_LOW(1U)
2506
2507 #define S_GPIO6_ACT_LOW 6
2508 #define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW)
2509 #define F_GPIO6_ACT_LOW V_GPIO6_ACT_LOW(1U)
2510
2511 #define S_GPIO5_ACT_LOW 5
2512 #define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW)
2513 #define F_GPIO5_ACT_LOW V_GPIO5_ACT_LOW(1U)
2514
2515 #define S_GPIO4_ACT_LOW 4
2516 #define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW)
2517 #define F_GPIO4_ACT_LOW V_GPIO4_ACT_LOW(1U)
2518
2519 #define S_GPIO3_ACT_LOW 3
2520 #define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW)
2521 #define F_GPIO3_ACT_LOW V_GPIO3_ACT_LOW(1U)
2522
2523 #define S_GPIO2_ACT_LOW 2
2524 #define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW)
2525 #define F_GPIO2_ACT_LOW V_GPIO2_ACT_LOW(1U)
2526
2527 #define S_GPIO1_ACT_LOW 1
2528 #define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW)
2529 #define F_GPIO1_ACT_LOW V_GPIO1_ACT_LOW(1U)
2530
2531 #define S_GPIO0_ACT_LOW 0
2532 #define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW)
2533 #define F_GPIO0_ACT_LOW V_GPIO0_ACT_LOW(1U)
2534
2535 #define S_PE_LOCK_ACT_LOW 16
2536 #define V_PE_LOCK_ACT_LOW(x) ((x) << S_PE_LOCK_ACT_LOW)
2537 #define F_PE_LOCK_ACT_LOW V_PE_LOCK_ACT_LOW(1U)
2538
2539 #define A_T3DBG_PMON_CFG 0xf4
2540
2541 #define S_PMON_DONE 29
2542 #define V_PMON_DONE(x) ((x) << S_PMON_DONE)
2543 #define F_PMON_DONE V_PMON_DONE(1U)
2544
2545 #define S_PMON_FAIL 28
2546 #define V_PMON_FAIL(x) ((x) << S_PMON_FAIL)
2547 #define F_PMON_FAIL V_PMON_FAIL(1U)
2548
2549 #define S_PMON_FDEL_AUTO 22
2550 #define M_PMON_FDEL_AUTO 0x3f
2551 #define V_PMON_FDEL_AUTO(x) ((x) << S_PMON_FDEL_AUTO)
2552 #define G_PMON_FDEL_AUTO(x) (((x) >> S_PMON_FDEL_AUTO) & M_PMON_FDEL_AUTO)
2553
2554 #define S_PMON_CDEL_AUTO 16
2555 #define M_PMON_CDEL_AUTO 0x3f
2556 #define V_PMON_CDEL_AUTO(x) ((x) << S_PMON_CDEL_AUTO)
2557 #define G_PMON_CDEL_AUTO(x) (((x) >> S_PMON_CDEL_AUTO) & M_PMON_CDEL_AUTO)
2558
2559 #define S_PMON_FDEL_MANUAL 10
2560 #define M_PMON_FDEL_MANUAL 0x3f
2561 #define V_PMON_FDEL_MANUAL(x) ((x) << S_PMON_FDEL_MANUAL)
2562 #define G_PMON_FDEL_MANUAL(x) (((x) >> S_PMON_FDEL_MANUAL) & M_PMON_FDEL_MANUAL)
2563
2564 #define S_PMON_CDEL_MANUAL 4
2565 #define M_PMON_CDEL_MANUAL 0x3f
2566 #define V_PMON_CDEL_MANUAL(x) ((x) << S_PMON_CDEL_MANUAL)
2567 #define G_PMON_CDEL_MANUAL(x) (((x) >> S_PMON_CDEL_MANUAL) & M_PMON_CDEL_MANUAL)
2568
2569 #define S_PMON_MANUAL 1
2570 #define V_PMON_MANUAL(x) ((x) << S_PMON_MANUAL)
2571 #define F_PMON_MANUAL V_PMON_MANUAL(1U)
2572
2573 #define S_PMON_AUTO 0
2574 #define V_PMON_AUTO(x) ((x) << S_PMON_AUTO)
2575 #define F_PMON_AUTO V_PMON_AUTO(1U)
2576
2577 #define A_T3DBG_SERDES_REFCLK_CFG 0xf8
2578
2579 #define S_PE_REFCLK_DBG_EN 12
2580 #define V_PE_REFCLK_DBG_EN(x) ((x) << S_PE_REFCLK_DBG_EN)
2581 #define F_PE_REFCLK_DBG_EN V_PE_REFCLK_DBG_EN(1U)
2582
2583 #define S_X_REFCLK_DBG_EN 8
2584 #define V_X_REFCLK_DBG_EN(x) ((x) << S_X_REFCLK_DBG_EN)
2585 #define F_X_REFCLK_DBG_EN V_X_REFCLK_DBG_EN(1U)
2586
2587 #define S_PE_REFCLK_TERMADJ 5
2588 #define M_PE_REFCLK_TERMADJ 0x3
2589 #define V_PE_REFCLK_TERMADJ(x) ((x) << S_PE_REFCLK_TERMADJ)
2590 #define G_PE_REFCLK_TERMADJ(x) (((x) >> S_PE_REFCLK_TERMADJ) & M_PE_REFCLK_TERMADJ)
2591
2592 #define S_PE_REFCLK_PD 4
2593 #define V_PE_REFCLK_PD(x) ((x) << S_PE_REFCLK_PD)
2594 #define F_PE_REFCLK_PD V_PE_REFCLK_PD(1U)
2595
2596 #define S_X_REFCLK_TERMADJ 1
2597 #define M_X_REFCLK_TERMADJ 0x3
2598 #define V_X_REFCLK_TERMADJ(x) ((x) << S_X_REFCLK_TERMADJ)
2599 #define G_X_REFCLK_TERMADJ(x) (((x) >> S_X_REFCLK_TERMADJ) & M_X_REFCLK_TERMADJ)
2600
2601 #define S_X_REFCLK_PD 0
2602 #define V_X_REFCLK_PD(x) ((x) << S_X_REFCLK_PD)
2603 #define F_X_REFCLK_PD V_X_REFCLK_PD(1U)
2604
2605 #define A_T3DBG_PCIE_PMA_BSPIN_CFG 0xfc
2606
2607 #define S_BSMODEQUAD1 31
2608 #define V_BSMODEQUAD1(x) ((x) << S_BSMODEQUAD1)
2609 #define F_BSMODEQUAD1 V_BSMODEQUAD1(1U)
2610
2611 #define S_BSINSELLANE7 29
2612 #define M_BSINSELLANE7 0x3
2613 #define V_BSINSELLANE7(x) ((x) << S_BSINSELLANE7)
2614 #define G_BSINSELLANE7(x) (((x) >> S_BSINSELLANE7) & M_BSINSELLANE7)
2615
2616 #define S_BSENLANE7 28
2617 #define V_BSENLANE7(x) ((x) << S_BSENLANE7)
2618 #define F_BSENLANE7 V_BSENLANE7(1U)
2619
2620 #define S_BSINSELLANE6 25
2621 #define M_BSINSELLANE6 0x3
2622 #define V_BSINSELLANE6(x) ((x) << S_BSINSELLANE6)
2623 #define G_BSINSELLANE6(x) (((x) >> S_BSINSELLANE6) & M_BSINSELLANE6)
2624
2625 #define S_BSENLANE6 24
2626 #define V_BSENLANE6(x) ((x) << S_BSENLANE6)
2627 #define F_BSENLANE6 V_BSENLANE6(1U)
2628
2629 #define S_BSINSELLANE5 21
2630 #define M_BSINSELLANE5 0x3
2631 #define V_BSINSELLANE5(x) ((x) << S_BSINSELLANE5)
2632 #define G_BSINSELLANE5(x) (((x) >> S_BSINSELLANE5) & M_BSINSELLANE5)
2633
2634 #define S_BSENLANE5 20
2635 #define V_BSENLANE5(x) ((x) << S_BSENLANE5)
2636 #define F_BSENLANE5 V_BSENLANE5(1U)
2637
2638 #define S_BSINSELLANE4 17
2639 #define M_BSINSELLANE4 0x3
2640 #define V_BSINSELLANE4(x) ((x) << S_BSINSELLANE4)
2641 #define G_BSINSELLANE4(x) (((x) >> S_BSINSELLANE4) & M_BSINSELLANE4)
2642
2643 #define S_BSENLANE4 16
2644 #define V_BSENLANE4(x) ((x) << S_BSENLANE4)
2645 #define F_BSENLANE4 V_BSENLANE4(1U)
2646
2647 #define S_BSMODEQUAD0 15
2648 #define V_BSMODEQUAD0(x) ((x) << S_BSMODEQUAD0)
2649 #define F_BSMODEQUAD0 V_BSMODEQUAD0(1U)
2650
2651 #define S_BSINSELLANE3 13
2652 #define M_BSINSELLANE3 0x3
2653 #define V_BSINSELLANE3(x) ((x) << S_BSINSELLANE3)
2654 #define G_BSINSELLANE3(x) (((x) >> S_BSINSELLANE3) & M_BSINSELLANE3)
2655
2656 #define S_BSENLANE3 12
2657 #define V_BSENLANE3(x) ((x) << S_BSENLANE3)
2658 #define F_BSENLANE3 V_BSENLANE3(1U)
2659
2660 #define S_BSINSELLANE2 9
2661 #define M_BSINSELLANE2 0x3
2662 #define V_BSINSELLANE2(x) ((x) << S_BSINSELLANE2)
2663 #define G_BSINSELLANE2(x) (((x) >> S_BSINSELLANE2) & M_BSINSELLANE2)
2664
2665 #define S_BSENLANE2 8
2666 #define V_BSENLANE2(x) ((x) << S_BSENLANE2)
2667 #define F_BSENLANE2 V_BSENLANE2(1U)
2668
2669 #define S_BSINSELLANE1 5
2670 #define M_BSINSELLANE1 0x3
2671 #define V_BSINSELLANE1(x) ((x) << S_BSINSELLANE1)
2672 #define G_BSINSELLANE1(x) (((x) >> S_BSINSELLANE1) & M_BSINSELLANE1)
2673
2674 #define S_BSENLANE1 4
2675 #define V_BSENLANE1(x) ((x) << S_BSENLANE1)
2676 #define F_BSENLANE1 V_BSENLANE1(1U)
2677
2678 #define S_BSINSELLANE0 1
2679 #define M_BSINSELLANE0 0x3
2680 #define V_BSINSELLANE0(x) ((x) << S_BSINSELLANE0)
2681 #define G_BSINSELLANE0(x) (((x) >> S_BSINSELLANE0) & M_BSINSELLANE0)
2682
2683 #define S_BSENLANE0 0
2684 #define V_BSENLANE0(x) ((x) << S_BSENLANE0)
2685 #define F_BSENLANE0 V_BSENLANE0(1U)
2686
2687 /* registers for module MC7_PMRX */
2688 #define MC7_PMRX_BASE_ADDR 0x100
2689
2690 #define A_MC7_CFG 0x100
2691
2692 #define S_IMPSETUPDATE 14
2693 #define V_IMPSETUPDATE(x) ((x) << S_IMPSETUPDATE)
2694 #define F_IMPSETUPDATE V_IMPSETUPDATE(1U)
2695
2696 #define S_IFEN 13
2697 #define V_IFEN(x) ((x) << S_IFEN)
2698 #define F_IFEN V_IFEN(1U)
2699
2700 #define S_TERM300 12
2701 #define V_TERM300(x) ((x) << S_TERM300)
2702 #define F_TERM300 V_TERM300(1U)
2703
2704 #define S_TERM150 11
2705 #define V_TERM150(x) ((x) << S_TERM150)
2706 #define F_TERM150 V_TERM150(1U)
2707
2708 #define S_SLOW 10
2709 #define V_SLOW(x) ((x) << S_SLOW)
2710 #define F_SLOW V_SLOW(1U)
2711
2712 #define S_WIDTH 8
2713 #define M_WIDTH 0x3
2714 #define V_WIDTH(x) ((x) << S_WIDTH)
2715 #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
2716
2717 #define S_ODTEN 7
2718 #define V_ODTEN(x) ((x) << S_ODTEN)
2719 #define F_ODTEN V_ODTEN(1U)
2720
2721 #define S_BKS 6
2722 #define V_BKS(x) ((x) << S_BKS)
2723 #define F_BKS V_BKS(1U)
2724
2725 #define S_ORG 5
2726 #define V_ORG(x) ((x) << S_ORG)
2727 #define F_ORG V_ORG(1U)
2728
2729 #define S_DEN 2
2730 #define M_DEN 0x7
2731 #define V_DEN(x) ((x) << S_DEN)
2732 #define G_DEN(x) (((x) >> S_DEN) & M_DEN)
2733
2734 #define S_RDY 1
2735 #define V_RDY(x) ((x) << S_RDY)
2736 #define F_RDY V_RDY(1U)
2737
2738 #define S_CLKEN 0
2739 #define V_CLKEN(x) ((x) << S_CLKEN)
2740 #define F_CLKEN V_CLKEN(1U)
2741
2742 #define A_MC7_MODE 0x104
2743
2744 #define S_MODE 0
2745 #define M_MODE 0xffff
2746 #define V_MODE(x) ((x) << S_MODE)
2747 #define G_MODE(x) (((x) >> S_MODE) & M_MODE)
2748
2749 #define A_MC7_EXT_MODE1 0x108
2750
2751 #define S_OCDADJUSTMODE 20
2752 #define V_OCDADJUSTMODE(x) ((x) << S_OCDADJUSTMODE)
2753 #define F_OCDADJUSTMODE V_OCDADJUSTMODE(1U)
2754
2755 #define S_OCDCODE 16
2756 #define M_OCDCODE 0xf
2757 #define V_OCDCODE(x) ((x) << S_OCDCODE)
2758 #define G_OCDCODE(x) (((x) >> S_OCDCODE) & M_OCDCODE)
2759
2760 #define S_EXTMODE1 0
2761 #define M_EXTMODE1 0xffff
2762 #define V_EXTMODE1(x) ((x) << S_EXTMODE1)
2763 #define G_EXTMODE1(x) (((x) >> S_EXTMODE1) & M_EXTMODE1)
2764
2765 #define A_MC7_EXT_MODE2 0x10c
2766
2767 #define S_EXTMODE2 0
2768 #define M_EXTMODE2 0xffff
2769 #define V_EXTMODE2(x) ((x) << S_EXTMODE2)
2770 #define G_EXTMODE2(x) (((x) >> S_EXTMODE2) & M_EXTMODE2)
2771
2772 #define A_MC7_EXT_MODE3 0x110
2773
2774 #define S_EXTMODE3 0
2775 #define M_EXTMODE3 0xffff
2776 #define V_EXTMODE3(x) ((x) << S_EXTMODE3)
2777 #define G_EXTMODE3(x) (((x) >> S_EXTMODE3) & M_EXTMODE3)
2778
2779 #define A_MC7_PRE 0x114
2780 #define A_MC7_REF 0x118
2781
2782 #define S_PREREFDIV 1
2783 #define M_PREREFDIV 0x3fff
2784 #define V_PREREFDIV(x) ((x) << S_PREREFDIV)
2785 #define G_PREREFDIV(x) (((x) >> S_PREREFDIV) & M_PREREFDIV)
2786
2787 #define S_PERREFEN 0
2788 #define V_PERREFEN(x) ((x) << S_PERREFEN)
2789 #define F_PERREFEN V_PERREFEN(1U)
2790
2791 #define A_MC7_DLL 0x11c
2792
2793 #define S_DLLLOCK 31
2794 #define V_DLLLOCK(x) ((x) << S_DLLLOCK)
2795 #define F_DLLLOCK V_DLLLOCK(1U)
2796
2797 #define S_DLLDELTA 24
2798 #define M_DLLDELTA 0x7f
2799 #define V_DLLDELTA(x) ((x) << S_DLLDELTA)
2800 #define G_DLLDELTA(x) (((x) >> S_DLLDELTA) & M_DLLDELTA)
2801
2802 #define S_MANDELTA 3
2803 #define M_MANDELTA 0x7f
2804 #define V_MANDELTA(x) ((x) << S_MANDELTA)
2805 #define G_MANDELTA(x) (((x) >> S_MANDELTA) & M_MANDELTA)
2806
2807 #define S_DLLDELTASEL 2
2808 #define V_DLLDELTASEL(x) ((x) << S_DLLDELTASEL)
2809 #define F_DLLDELTASEL V_DLLDELTASEL(1U)
2810
2811 #define S_DLLENB 1
2812 #define V_DLLENB(x) ((x) << S_DLLENB)
2813 #define F_DLLENB V_DLLENB(1U)
2814
2815 #define S_DLLRST 0
2816 #define V_DLLRST(x) ((x) << S_DLLRST)
2817 #define F_DLLRST V_DLLRST(1U)
2818
2819 #define A_MC7_PARM 0x120
2820
2821 #define S_ACTTOPREDLY 26
2822 #define M_ACTTOPREDLY 0xf
2823 #define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY)
2824 #define G_ACTTOPREDLY(x) (((x) >> S_ACTTOPREDLY) & M_ACTTOPREDLY)
2825
2826 #define S_ACTTORDWRDLY 23
2827 #define M_ACTTORDWRDLY 0x7
2828 #define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY)
2829 #define G_ACTTORDWRDLY(x) (((x) >> S_ACTTORDWRDLY) & M_ACTTORDWRDLY)
2830
2831 #define S_PRECYC 20
2832 #define M_PRECYC 0x7
2833 #define V_PRECYC(x) ((x) << S_PRECYC)
2834 #define G_PRECYC(x) (((x) >> S_PRECYC) & M_PRECYC)
2835
2836 #define S_REFCYC 13
2837 #define M_REFCYC 0x7f
2838 #define V_REFCYC(x) ((x) << S_REFCYC)
2839 #define G_REFCYC(x) (((x) >> S_REFCYC) & M_REFCYC)
2840
2841 #define S_BKCYC 8
2842 #define M_BKCYC 0x1f
2843 #define V_BKCYC(x) ((x) << S_BKCYC)
2844 #define G_BKCYC(x) (((x) >> S_BKCYC) & M_BKCYC)
2845
2846 #define S_WRTORDDLY 4
2847 #define M_WRTORDDLY 0xf
2848 #define V_WRTORDDLY(x) ((x) << S_WRTORDDLY)
2849 #define G_WRTORDDLY(x) (((x) >> S_WRTORDDLY) & M_WRTORDDLY)
2850
2851 #define S_RDTOWRDLY 0
2852 #define M_RDTOWRDLY 0xf
2853 #define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY)
2854 #define G_RDTOWRDLY(x) (((x) >> S_RDTOWRDLY) & M_RDTOWRDLY)
2855
2856 #define A_MC7_HWM_WRR 0x124
2857
2858 #define S_MEM_HWM 26
2859 #define M_MEM_HWM 0x3f
2860 #define V_MEM_HWM(x) ((x) << S_MEM_HWM)
2861 #define G_MEM_HWM(x) (((x) >> S_MEM_HWM) & M_MEM_HWM)
2862
2863 #define S_ULP_HWM 22
2864 #define M_ULP_HWM 0xf
2865 #define V_ULP_HWM(x) ((x) << S_ULP_HWM)
2866 #define G_ULP_HWM(x) (((x) >> S_ULP_HWM) & M_ULP_HWM)
2867
2868 #define S_TOT_RLD_WT 14
2869 #define M_TOT_RLD_WT 0xff
2870 #define V_TOT_RLD_WT(x) ((x) << S_TOT_RLD_WT)
2871 #define G_TOT_RLD_WT(x) (((x) >> S_TOT_RLD_WT) & M_TOT_RLD_WT)
2872
2873 #define S_MEM_RLD_WT 7
2874 #define M_MEM_RLD_WT 0x7f
2875 #define V_MEM_RLD_WT(x) ((x) << S_MEM_RLD_WT)
2876 #define G_MEM_RLD_WT(x) (((x) >> S_MEM_RLD_WT) & M_MEM_RLD_WT)
2877
2878 #define S_ULP_RLD_WT 0
2879 #define M_ULP_RLD_WT 0x7f
2880 #define V_ULP_RLD_WT(x) ((x) << S_ULP_RLD_WT)
2881 #define G_ULP_RLD_WT(x) (((x) >> S_ULP_RLD_WT) & M_ULP_RLD_WT)
2882
2883 #define A_MC7_CAL 0x128
2884
2885 #define S_BUSY 31
2886 #define V_BUSY(x) ((x) << S_BUSY)
2887 #define F_BUSY V_BUSY(1U)
2888
2889 #define S_CAL_FAULT 30
2890 #define V_CAL_FAULT(x) ((x) << S_CAL_FAULT)
2891 #define F_CAL_FAULT V_CAL_FAULT(1U)
2892
2893 #define S_PER_CAL_DIV 22
2894 #define M_PER_CAL_DIV 0xff
2895 #define V_PER_CAL_DIV(x) ((x) << S_PER_CAL_DIV)
2896 #define G_PER_CAL_DIV(x) (((x) >> S_PER_CAL_DIV) & M_PER_CAL_DIV)
2897
2898 #define S_PER_CAL_EN 21
2899 #define V_PER_CAL_EN(x) ((x) << S_PER_CAL_EN)
2900 #define F_PER_CAL_EN V_PER_CAL_EN(1U)
2901
2902 #define S_SGL_CAL_EN 20
2903 #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN)
2904 #define F_SGL_CAL_EN V_SGL_CAL_EN(1U)
2905
2906 #define S_IMP_UPD_MODE 19
2907 #define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE)
2908 #define F_IMP_UPD_MODE V_IMP_UPD_MODE(1U)
2909
2910 #define S_IMP_SEL 18
2911 #define V_IMP_SEL(x) ((x) << S_IMP_SEL)
2912 #define F_IMP_SEL V_IMP_SEL(1U)
2913
2914 #define S_IMP_MAN_PD 15
2915 #define M_IMP_MAN_PD 0x7
2916 #define V_IMP_MAN_PD(x) ((x) << S_IMP_MAN_PD)
2917 #define G_IMP_MAN_PD(x) (((x) >> S_IMP_MAN_PD) & M_IMP_MAN_PD)
2918
2919 #define S_IMP_MAN_PU 12
2920 #define M_IMP_MAN_PU 0x7
2921 #define V_IMP_MAN_PU(x) ((x) << S_IMP_MAN_PU)
2922 #define G_IMP_MAN_PU(x) (((x) >> S_IMP_MAN_PU) & M_IMP_MAN_PU)
2923
2924 #define S_IMP_CAL_PD 9
2925 #define M_IMP_CAL_PD 0x7
2926 #define V_IMP_CAL_PD(x) ((x) << S_IMP_CAL_PD)
2927 #define G_IMP_CAL_PD(x) (((x) >> S_IMP_CAL_PD) & M_IMP_CAL_PD)
2928
2929 #define S_IMP_CAL_PU 6
2930 #define M_IMP_CAL_PU 0x7
2931 #define V_IMP_CAL_PU(x) ((x) << S_IMP_CAL_PU)
2932 #define G_IMP_CAL_PU(x) (((x) >> S_IMP_CAL_PU) & M_IMP_CAL_PU)
2933
2934 #define S_IMP_SET_PD 3
2935 #define M_IMP_SET_PD 0x7
2936 #define V_IMP_SET_PD(x) ((x) << S_IMP_SET_PD)
2937 #define G_IMP_SET_PD(x) (((x) >> S_IMP_SET_PD) & M_IMP_SET_PD)
2938
2939 #define S_IMP_SET_PU 0
2940 #define M_IMP_SET_PU 0x7
2941 #define V_IMP_SET_PU(x) ((x) << S_IMP_SET_PU)
2942 #define G_IMP_SET_PU(x) (((x) >> S_IMP_SET_PU) & M_IMP_SET_PU)
2943
2944 #define A_MC7_ERR_ADDR 0x12c
2945
2946 #define S_ERRADDRESS 3
2947 #define M_ERRADDRESS 0x1fffffff
2948 #define V_ERRADDRESS(x) ((x) << S_ERRADDRESS)
2949 #define G_ERRADDRESS(x) (((x) >> S_ERRADDRESS) & M_ERRADDRESS)
2950
2951 #define S_ERRAGENT 1
2952 #define M_ERRAGENT 0x3
2953 #define V_ERRAGENT(x) ((x) << S_ERRAGENT)
2954 #define G_ERRAGENT(x) (((x) >> S_ERRAGENT) & M_ERRAGENT)
2955
2956 #define S_ERROP 0
2957 #define V_ERROP(x) ((x) << S_ERROP)
2958 #define F_ERROP V_ERROP(1U)
2959
2960 #define A_MC7_ECC 0x130
2961
2962 #define S_UECNT 10
2963 #define M_UECNT 0xff
2964 #define V_UECNT(x) ((x) << S_UECNT)
2965 #define G_UECNT(x) (((x) >> S_UECNT) & M_UECNT)
2966
2967 #define S_CECNT 2
2968 #define M_CECNT 0xff
2969 #define V_CECNT(x) ((x) << S_CECNT)
2970 #define G_CECNT(x) (((x) >> S_CECNT) & M_CECNT)
2971
2972 #define S_ECCCHKEN 1
2973 #define V_ECCCHKEN(x) ((x) << S_ECCCHKEN)
2974 #define F_ECCCHKEN V_ECCCHKEN(1U)
2975
2976 #define S_ECCGENEN 0
2977 #define V_ECCGENEN(x) ((x) << S_ECCGENEN)
2978 #define F_ECCGENEN V_ECCGENEN(1U)
2979
2980 #define A_MC7_CE_ADDR 0x134
2981 #define A_MC7_CE_DATA0 0x138
2982 #define A_MC7_CE_DATA1 0x13c
2983 #define A_MC7_CE_DATA2 0x140
2984
2985 #define S_DATA 0
2986 #define M_DATA 0xff
2987 #define V_DATA(x) ((x) << S_DATA)
2988 #define G_DATA(x) (((x) >> S_DATA) & M_DATA)
2989
2990 #define A_MC7_UE_ADDR 0x144
2991 #define A_MC7_UE_DATA0 0x148
2992 #define A_MC7_UE_DATA1 0x14c
2993 #define A_MC7_UE_DATA2 0x150
2994 #define A_MC7_BD_ADDR 0x154
2995
2996 #define S_ADDR 3
2997 #define M_ADDR 0x1fffffff
2998 #define V_ADDR(x) ((x) << S_ADDR)
2999 #define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR)
3000
3001 #define A_MC7_BD_DATA0 0x158
3002 #define A_MC7_BD_DATA1 0x15c
3003 #define A_MC7_BD_DATA2 0x160
3004 #define A_MC7_BD_OP 0x164
3005
3006 #define S_OP 0
3007 #define V_OP(x) ((x) << S_OP)
3008 #define F_OP V_OP(1U)
3009
3010 #define A_MC7_BIST_ADDR_BEG 0x168
3011
3012 #define S_ADDRBEG 5
3013 #define M_ADDRBEG 0x7ffffff
3014 #define V_ADDRBEG(x) ((x) << S_ADDRBEG)
3015 #define G_ADDRBEG(x) (((x) >> S_ADDRBEG) & M_ADDRBEG)
3016
3017 #define A_MC7_BIST_ADDR_END 0x16c
3018
3019 #define S_ADDREND 5
3020 #define M_ADDREND 0x7ffffff
3021 #define V_ADDREND(x) ((x) << S_ADDREND)
3022 #define G_ADDREND(x) (((x) >> S_ADDREND) & M_ADDREND)
3023
3024 #define A_MC7_BIST_DATA 0x170
3025 #define A_MC7_BIST_OP 0x174
3026
3027 #define S_GAP 4
3028 #define M_GAP 0x1f
3029 #define V_GAP(x) ((x) << S_GAP)
3030 #define G_GAP(x) (((x) >> S_GAP) & M_GAP)
3031
3032 #define S_CONT 3
3033 #define V_CONT(x) ((x) << S_CONT)
3034 #define F_CONT V_CONT(1U)
3035
3036 #define S_DATAPAT 1
3037 #define M_DATAPAT 0x3
3038 #define V_DATAPAT(x) ((x) << S_DATAPAT)
3039 #define G_DATAPAT(x) (((x) >> S_DATAPAT) & M_DATAPAT)
3040
3041 #define A_MC7_INT_ENABLE 0x178
3042
3043 #define S_AE 17
3044 #define V_AE(x) ((x) << S_AE)
3045 #define F_AE V_AE(1U)
3046
3047 #define S_PE 2
3048 #define M_PE 0x7fff
3049 #define V_PE(x) ((x) << S_PE)
3050 #define G_PE(x) (((x) >> S_PE) & M_PE)
3051
3052 #define S_UE 1
3053 #define V_UE(x) ((x) << S_UE)
3054 #define F_UE V_UE(1U)
3055
3056 #define S_CE 0
3057 #define V_CE(x) ((x) << S_CE)
3058 #define F_CE V_CE(1U)
3059
3060 #define A_MC7_INT_CAUSE 0x17c
3061
3062 /* registers for module MC7_PMTX */
3063 #define MC7_PMTX_BASE_ADDR 0x180
3064
3065 /* registers for module MC7_CM */
3066 #define MC7_CM_BASE_ADDR 0x200
3067
3068 /* registers for module CIM */
3069 #define CIM_BASE_ADDR 0x280
3070
3071 #define A_CIM_BOOT_CFG 0x280
3072
3073 #define S_BOOTADDR 2
3074 #define M_BOOTADDR 0x3fffffff
3075 #define V_BOOTADDR(x) ((x) << S_BOOTADDR)
3076 #define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR)
3077
3078 #define S_BOOTSDRAM 1
3079 #define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM)
3080 #define F_BOOTSDRAM V_BOOTSDRAM(1U)
3081
3082 #define S_UPCRST 0
3083 #define V_UPCRST(x) ((x) << S_UPCRST)
3084 #define F_UPCRST V_UPCRST(1U)
3085
3086 #define A_CIM_FLASH_BASE_ADDR 0x284
3087
3088 #define S_FLASHBASEADDR 2
3089 #define M_FLASHBASEADDR 0x3fffff
3090 #define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR)
3091 #define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR)
3092
3093 #define A_CIM_FLASH_ADDR_SIZE 0x288
3094
3095 #define S_FLASHADDRSIZE 2
3096 #define M_FLASHADDRSIZE 0x3fffff
3097 #define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE)
3098 #define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE)
3099
3100 #define A_CIM_SDRAM_BASE_ADDR 0x28c
3101
3102 #define S_SDRAMBASEADDR 2
3103 #define M_SDRAMBASEADDR 0x3fffffff
3104 #define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR)
3105 #define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR)
3106
3107 #define A_CIM_SDRAM_ADDR_SIZE 0x290
3108
3109 #define S_SDRAMADDRSIZE 2
3110 #define M_SDRAMADDRSIZE 0x3fffffff
3111 #define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE)
3112 #define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE)
3113
3114 #define A_CIM_UP_SPARE_INT 0x294
3115
3116 #define S_UPSPAREINT 0
3117 #define M_UPSPAREINT 0x7
3118 #define V_UPSPAREINT(x) ((x) << S_UPSPAREINT)
3119 #define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT)
3120
3121 #define A_CIM_HOST_INT_ENABLE 0x298
3122
3123 #define S_DTAGPARERR 28
3124 #define V_DTAGPARERR(x) ((x) << S_DTAGPARERR)
3125 #define F_DTAGPARERR V_DTAGPARERR(1U)
3126
3127 #define S_ITAGPARERR 27
3128 #define V_ITAGPARERR(x) ((x) << S_ITAGPARERR)
3129 #define F_ITAGPARERR V_ITAGPARERR(1U)
3130
3131 #define S_IBQTPPARERR 26
3132 #define V_IBQTPPARERR(x) ((x) << S_IBQTPPARERR)
3133 #define F_IBQTPPARERR V_IBQTPPARERR(1U)
3134
3135 #define S_IBQULPPARERR 25
3136 #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
3137 #define F_IBQULPPARERR V_IBQULPPARERR(1U)
3138
3139 #define S_IBQSGEHIPARERR 24
3140 #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
3141 #define F_IBQSGEHIPARERR V_IBQSGEHIPARERR(1U)
3142
3143 #define S_IBQSGELOPARERR 23
3144 #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
3145 #define F_IBQSGELOPARERR V_IBQSGELOPARERR(1U)
3146
3147 #define S_OBQULPLOPARERR 22
3148 #define V_OBQULPLOPARERR(x) ((x) << S_OBQULPLOPARERR)
3149 #define F_OBQULPLOPARERR V_OBQULPLOPARERR(1U)
3150
3151 #define S_OBQULPHIPARERR 21
3152 #define V_OBQULPHIPARERR(x) ((x) << S_OBQULPHIPARERR)
3153 #define F_OBQULPHIPARERR V_OBQULPHIPARERR(1U)
3154
3155 #define S_OBQSGEPARERR 20
3156 #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
3157 #define F_OBQSGEPARERR V_OBQSGEPARERR(1U)
3158
3159 #define S_DCACHEPARERR 19
3160 #define V_DCACHEPARERR(x) ((x) << S_DCACHEPARERR)
3161 #define F_DCACHEPARERR V_DCACHEPARERR(1U)
3162
3163 #define S_ICACHEPARERR 18
3164 #define V_ICACHEPARERR(x) ((x) << S_ICACHEPARERR)
3165 #define F_ICACHEPARERR V_ICACHEPARERR(1U)
3166
3167 #define S_DRAMPARERR 17
3168 #define V_DRAMPARERR(x) ((x) << S_DRAMPARERR)
3169 #define F_DRAMPARERR V_DRAMPARERR(1U)
3170
3171 #define S_TIMER1INTEN 15
3172 #define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN)
3173 #define F_TIMER1INTEN V_TIMER1INTEN(1U)
3174
3175 #define S_TIMER0INTEN 14
3176 #define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN)
3177 #define F_TIMER0INTEN V_TIMER0INTEN(1U)
3178
3179 #define S_PREFDROPINTEN 13
3180 #define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN)
3181 #define F_PREFDROPINTEN V_PREFDROPINTEN(1U)
3182
3183 #define S_BLKWRPLINTEN 12
3184 #define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN)
3185 #define F_BLKWRPLINTEN V_BLKWRPLINTEN(1U)
3186
3187 #define S_BLKRDPLINTEN 11
3188 #define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN)
3189 #define F_BLKRDPLINTEN V_BLKRDPLINTEN(1U)
3190
3191 #define S_BLKWRCTLINTEN 10
3192 #define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN)
3193 #define F_BLKWRCTLINTEN V_BLKWRCTLINTEN(1U)
3194
3195 #define S_BLKRDCTLINTEN 9
3196 #define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN)
3197 #define F_BLKRDCTLINTEN V_BLKRDCTLINTEN(1U)
3198
3199 #define S_BLKWRFLASHINTEN 8
3200 #define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN)
3201 #define F_BLKWRFLASHINTEN V_BLKWRFLASHINTEN(1U)
3202
3203 #define S_BLKRDFLASHINTEN 7
3204 #define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN)
3205 #define F_BLKRDFLASHINTEN V_BLKRDFLASHINTEN(1U)
3206
3207 #define S_SGLWRFLASHINTEN 6
3208 #define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN)
3209 #define F_SGLWRFLASHINTEN V_SGLWRFLASHINTEN(1U)
3210
3211 #define S_WRBLKFLASHINTEN 5
3212 #define V_WRBLKFLASHINTEN(x) ((x) << S_WRBLKFLASHINTEN)
3213 #define F_WRBLKFLASHINTEN V_WRBLKFLASHINTEN(1U)
3214
3215 #define S_BLKWRBOOTINTEN 4
3216 #define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN)
3217 #define F_BLKWRBOOTINTEN V_BLKWRBOOTINTEN(1U)
3218
3219 #define S_BLKRDBOOTINTEN 3
3220 #define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN)
3221 #define F_BLKRDBOOTINTEN V_BLKRDBOOTINTEN(1U)
3222
3223 #define S_FLASHRANGEINTEN 2
3224 #define V_FLASHRANGEINTEN(x) ((x) << S_FLASHRANGEINTEN)
3225 #define F_FLASHRANGEINTEN V_FLASHRANGEINTEN(1U)
3226
3227 #define S_SDRAMRANGEINTEN 1
3228 #define V_SDRAMRANGEINTEN(x) ((x) << S_SDRAMRANGEINTEN)
3229 #define F_SDRAMRANGEINTEN V_SDRAMRANGEINTEN(1U)
3230
3231 #define S_RSVDSPACEINTEN 0
3232 #define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN)
3233 #define F_RSVDSPACEINTEN V_RSVDSPACEINTEN(1U)
3234
3235 #define A_CIM_HOST_INT_CAUSE 0x29c
3236
3237 #define S_TIMER1INT 15
3238 #define V_TIMER1INT(x) ((x) << S_TIMER1INT)
3239 #define F_TIMER1INT V_TIMER1INT(1U)
3240
3241 #define S_TIMER0INT 14
3242 #define V_TIMER0INT(x) ((x) << S_TIMER0INT)
3243 #define F_TIMER0INT V_TIMER0INT(1U)
3244
3245 #define S_PREFDROPINT 13
3246 #define V_PREFDROPINT(x) ((x) << S_PREFDROPINT)
3247 #define F_PREFDROPINT V_PREFDROPINT(1U)
3248
3249 #define S_BLKWRPLINT 12
3250 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
3251 #define F_BLKWRPLINT V_BLKWRPLINT(1U)
3252
3253 #define S_BLKRDPLINT 11
3254 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
3255 #define F_BLKRDPLINT V_BLKRDPLINT(1U)
3256
3257 #define S_BLKWRCTLINT 10
3258 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
3259 #define F_BLKWRCTLINT V_BLKWRCTLINT(1U)
3260
3261 #define S_BLKRDCTLINT 9
3262 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
3263 #define F_BLKRDCTLINT V_BLKRDCTLINT(1U)
3264
3265 #define S_BLKWRFLASHINT 8
3266 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
3267 #define F_BLKWRFLASHINT V_BLKWRFLASHINT(1U)
3268
3269 #define S_BLKRDFLASHINT 7
3270 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
3271 #define F_BLKRDFLASHINT V_BLKRDFLASHINT(1U)
3272
3273 #define S_SGLWRFLASHINT 6
3274 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
3275 #define F_SGLWRFLASHINT V_SGLWRFLASHINT(1U)
3276
3277 #define S_WRBLKFLASHINT 5
3278 #define V_WRBLKFLASHINT(x) ((x) << S_WRBLKFLASHINT)
3279 #define F_WRBLKFLASHINT V_WRBLKFLASHINT(1U)
3280
3281 #define S_BLKWRBOOTINT 4
3282 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
3283 #define F_BLKWRBOOTINT V_BLKWRBOOTINT(1U)
3284
3285 #define S_BLKRDBOOTINT 3
3286 #define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT)
3287 #define F_BLKRDBOOTINT V_BLKRDBOOTINT(1U)
3288
3289 #define S_FLASHRANGEINT 2
3290 #define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT)
3291 #define F_FLASHRANGEINT V_FLASHRANGEINT(1U)
3292
3293 #define S_SDRAMRANGEINT 1
3294 #define V_SDRAMRANGEINT(x) ((x) << S_SDRAMRANGEINT)
3295 #define F_SDRAMRANGEINT V_SDRAMRANGEINT(1U)
3296
3297 #define S_RSVDSPACEINT 0
3298 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
3299 #define F_RSVDSPACEINT V_RSVDSPACEINT(1U)
3300
3301 #define A_CIM_UP_INT_ENABLE 0x2a0
3302
3303 #define S_MSTPLINTEN 16
3304 #define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN)
3305 #define F_MSTPLINTEN V_MSTPLINTEN(1U)
3306
3307 #define A_CIM_UP_INT_CAUSE 0x2a4
3308
3309 #define S_MSTPLINT 16
3310 #define V_MSTPLINT(x) ((x) << S_MSTPLINT)
3311 #define F_MSTPLINT V_MSTPLINT(1U)
3312
3313 #define A_CIM_IBQ_FULLA_THRSH 0x2a8
3314
3315 #define S_IBQ0FULLTHRSH 0
3316 #define M_IBQ0FULLTHRSH 0x1ff
3317 #define V_IBQ0FULLTHRSH(x) ((x) << S_IBQ0FULLTHRSH)
3318 #define G_IBQ0FULLTHRSH(x) (((x) >> S_IBQ0FULLTHRSH) & M_IBQ0FULLTHRSH)
3319
3320 #define S_IBQ1FULLTHRSH 16
3321 #define M_IBQ1FULLTHRSH 0x1ff
3322 #define V_IBQ1FULLTHRSH(x) ((x) << S_IBQ1FULLTHRSH)
3323 #define G_IBQ1FULLTHRSH(x) (((x) >> S_IBQ1FULLTHRSH) & M_IBQ1FULLTHRSH)
3324
3325 #define A_CIM_IBQ_FULLB_THRSH 0x2ac
3326
3327 #define S_IBQ2FULLTHRSH 0
3328 #define M_IBQ2FULLTHRSH 0x1ff
3329 #define V_IBQ2FULLTHRSH(x) ((x) << S_IBQ2FULLTHRSH)
3330 #define G_IBQ2FULLTHRSH(x) (((x) >> S_IBQ2FULLTHRSH) & M_IBQ2FULLTHRSH)
3331
3332 #define S_IBQ3FULLTHRSH 16
3333 #define M_IBQ3FULLTHRSH 0x1ff
3334 #define V_IBQ3FULLTHRSH(x) ((x) << S_IBQ3FULLTHRSH)
3335 #define G_IBQ3FULLTHRSH(x) (((x) >> S_IBQ3FULLTHRSH) & M_IBQ3FULLTHRSH)
3336
3337 #define A_CIM_HOST_ACC_CTRL 0x2b0
3338
3339 #define S_HOSTBUSY 17
3340 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
3341 #define F_HOSTBUSY V_HOSTBUSY(1U)
3342
3343 #define S_HOSTWRITE 16
3344 #define V_HOSTWRITE(x) ((x) << S_HOSTWRITE)
3345 #define F_HOSTWRITE V_HOSTWRITE(1U)
3346
3347 #define S_HOSTADDR 0
3348 #define M_HOSTADDR 0xffff
3349 #define V_HOSTADDR(x) ((x) << S_HOSTADDR)
3350 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)
3351
3352 #define A_CIM_HOST_ACC_DATA 0x2b4
3353 #define A_CIM_IBQ_DBG_CFG 0x2c0
3354
3355 #define S_IBQDBGADDR 16
3356 #define M_IBQDBGADDR 0x1ff
3357 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
3358 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
3359
3360 #define S_IBQDBGQID 3
3361 #define M_IBQDBGQID 0x3
3362 #define V_IBQDBGQID(x) ((x) << S_IBQDBGQID)
3363 #define G_IBQDBGQID(x) (((x) >> S_IBQDBGQID) & M_IBQDBGQID)
3364
3365 #define S_IBQDBGWR 2
3366 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
3367 #define F_IBQDBGWR V_IBQDBGWR(1U)
3368
3369 #define S_IBQDBGBUSY 1
3370 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
3371 #define F_IBQDBGBUSY V_IBQDBGBUSY(1U)
3372
3373 #define S_IBQDBGEN 0
3374 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
3375 #define F_IBQDBGEN V_IBQDBGEN(1U)
3376
3377 #define A_CIM_OBQ_DBG_CFG 0x2c4
3378
3379 #define S_OBQDBGADDR 16
3380 #define M_OBQDBGADDR 0x1ff
3381 #define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR)
3382 #define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR)
3383
3384 #define S_OBQDBGQID 3
3385 #define M_OBQDBGQID 0x3
3386 #define V_OBQDBGQID(x) ((x) << S_OBQDBGQID)
3387 #define G_OBQDBGQID(x) (((x) >> S_OBQDBGQID) & M_OBQDBGQID)
3388
3389 #define S_OBQDBGWR 2
3390 #define V_OBQDBGWR(x) ((x) << S_OBQDBGWR)
3391 #define F_OBQDBGWR V_OBQDBGWR(1U)
3392
3393 #define S_OBQDBGBUSY 1
3394 #define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY)
3395 #define F_OBQDBGBUSY V_OBQDBGBUSY(1U)
3396
3397 #define S_OBQDBGEN 0
3398 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
3399 #define F_OBQDBGEN V_OBQDBGEN(1U)
3400
3401 #define A_CIM_IBQ_DBG_DATA 0x2c8
3402 #define A_CIM_OBQ_DBG_DATA 0x2cc
3403 #define A_CIM_CDEBUGDATA 0x2d0
3404
3405 #define S_CDEBUGDATAH 16
3406 #define M_CDEBUGDATAH 0xffff
3407 #define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH)
3408 #define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH)
3409
3410 #define S_CDEBUGDATAL 0
3411 #define M_CDEBUGDATAL 0xffff
3412 #define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL)
3413 #define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL)
3414
3415 #define A_CIM_DEBUGCFG 0x2e0
3416
3417 #define S_POLADBGRDPTR 23
3418 #define M_POLADBGRDPTR 0x1ff
3419 #define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR)
3420 #define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR)
3421
3422 #define S_PILADBGRDPTR 14
3423 #define M_PILADBGRDPTR 0x1ff
3424 #define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR)
3425 #define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR)
3426
3427 #define S_CIM_LADBGEN 12
3428 #define V_CIM_LADBGEN(x) ((x) << S_CIM_LADBGEN)
3429 #define F_CIM_LADBGEN V_CIM_LADBGEN(1U)
3430
3431 #define S_DEBUGSELHI 5
3432 #define M_DEBUGSELHI 0x1f
3433 #define V_DEBUGSELHI(x) ((x) << S_DEBUGSELHI)
3434 #define G_DEBUGSELHI(x) (((x) >> S_DEBUGSELHI) & M_DEBUGSELHI)
3435
3436 #define S_DEBUGSELLO 0
3437 #define M_DEBUGSELLO 0x1f
3438 #define V_DEBUGSELLO(x) ((x) << S_DEBUGSELLO)
3439 #define G_DEBUGSELLO(x) (((x) >> S_DEBUGSELLO) & M_DEBUGSELLO)
3440
3441 #define A_CIM_DEBUGSTS 0x2e4
3442
3443 #define S_POLADBGWRPTR 16
3444 #define M_POLADBGWRPTR 0x1ff
3445 #define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR)
3446 #define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR)
3447
3448 #define S_PILADBGWRPTR 0
3449 #define M_PILADBGWRPTR 0x1ff
3450 #define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR)
3451 #define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR)
3452
3453 #define A_CIM_PO_LA_DEBUGDATA 0x2e8
3454 #define A_CIM_PI_LA_DEBUGDATA 0x2ec
3455
3456 /* registers for module TP1 */
3457 #define TP1_BASE_ADDR 0x300
3458
3459 #define A_TP_IN_CONFIG 0x300
3460
3461 #define S_RXFBARBPRIO 25
3462 #define V_RXFBARBPRIO(x) ((x) << S_RXFBARBPRIO)
3463 #define F_RXFBARBPRIO V_RXFBARBPRIO(1U)
3464
3465 #define S_TXFBARBPRIO 24
3466 #define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO)
3467 #define F_TXFBARBPRIO V_TXFBARBPRIO(1U)
3468
3469 #define S_DBMAXOPCNT 16
3470 #define M_DBMAXOPCNT 0xff
3471 #define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT)
3472 #define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT)
3473
3474 #define S_IPV6ENABLE 15
3475 #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
3476 #define F_IPV6ENABLE V_IPV6ENABLE(1U)
3477
3478 #define S_NICMODE 14
3479 #define V_NICMODE(x) ((x) << S_NICMODE)
3480 #define F_NICMODE V_NICMODE(1U)
3481
3482 #define S_ECHECKSUMCHECKTCP 13
3483 #define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP)
3484 #define F_ECHECKSUMCHECKTCP V_ECHECKSUMCHECKTCP(1U)
3485
3486 #define S_ECHECKSUMCHECKIP 12
3487 #define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP)
3488 #define F_ECHECKSUMCHECKIP V_ECHECKSUMCHECKIP(1U)
3489
3490 #define S_ECPL 10
3491 #define V_ECPL(x) ((x) << S_ECPL)
3492 #define F_ECPL V_ECPL(1U)
3493
3494 #define S_EETHERNET 8
3495 #define V_EETHERNET(x) ((x) << S_EETHERNET)
3496 #define F_EETHERNET V_EETHERNET(1U)
3497
3498 #define S_ETUNNEL 7
3499 #define V_ETUNNEL(x) ((x) << S_ETUNNEL)
3500 #define F_ETUNNEL V_ETUNNEL(1U)
3501
3502 #define S_CCHECKSUMCHECKTCP 6
3503 #define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP)
3504 #define F_CCHECKSUMCHECKTCP V_CCHECKSUMCHECKTCP(1U)
3505
3506 #define S_CCHECKSUMCHECKIP 5
3507 #define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP)
3508 #define F_CCHECKSUMCHECKIP V_CCHECKSUMCHECKIP(1U)
3509
3510 #define S_CCPL 3
3511 #define V_CCPL(x) ((x) << S_CCPL)
3512 #define F_CCPL V_CCPL(1U)
3513
3514 #define S_CETHERNET 1
3515 #define V_CETHERNET(x) ((x) << S_CETHERNET)
3516 #define F_CETHERNET V_CETHERNET(1U)
3517
3518 #define S_CTUNNEL 0
3519 #define V_CTUNNEL(x) ((x) << S_CTUNNEL)
3520 #define F_CTUNNEL V_CTUNNEL(1U)
3521
3522 #define A_TP_OUT_CONFIG 0x304
3523
3524 #define S_IPIDSPLITMODE 16
3525 #define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE)
3526 #define F_IPIDSPLITMODE V_IPIDSPLITMODE(1U)
3527
3528 #define S_VLANEXTRACTIONENABLE2NDPORT 13
3529 #define V_VLANEXTRACTIONENABLE2NDPORT(x) ((x) << S_VLANEXTRACTIONENABLE2NDPORT)
3530 #define F_VLANEXTRACTIONENABLE2NDPORT V_VLANEXTRACTIONENABLE2NDPORT(1U)
3531
3532 #define S_VLANEXTRACTIONENABLE 12
3533 #define V_VLANEXTRACTIONENABLE(x) ((x) << S_VLANEXTRACTIONENABLE)
3534 #define F_VLANEXTRACTIONENABLE V_VLANEXTRACTIONENABLE(1U)
3535
3536 #define S_ECHECKSUMGENERATETCP 11
3537 #define V_ECHECKSUMGENERATETCP(x) ((x) << S_ECHECKSUMGENERATETCP)
3538 #define F_ECHECKSUMGENERATETCP V_ECHECKSUMGENERATETCP(1U)
3539
3540 #define S_ECHECKSUMGENERATEIP 10
3541 #define V_ECHECKSUMGENERATEIP(x) ((x) << S_ECHECKSUMGENERATEIP)
3542 #define F_ECHECKSUMGENERATEIP V_ECHECKSUMGENERATEIP(1U)
3543
3544 #define S_OUT_ECPL 8
3545 #define V_OUT_ECPL(x) ((x) << S_OUT_ECPL)
3546 #define F_OUT_ECPL V_OUT_ECPL(1U)
3547
3548 #define S_OUT_EETHERNET 6
3549 #define V_OUT_EETHERNET(x) ((x) << S_OUT_EETHERNET)
3550 #define F_OUT_EETHERNET V_OUT_EETHERNET(1U)
3551
3552 #define S_CCHECKSUMGENERATETCP 5
3553 #define V_CCHECKSUMGENERATETCP(x) ((x) << S_CCHECKSUMGENERATETCP)
3554 #define F_CCHECKSUMGENERATETCP V_CCHECKSUMGENERATETCP(1U)
3555
3556 #define S_CCHECKSUMGENERATEIP 4
3557 #define V_CCHECKSUMGENERATEIP(x) ((x) << S_CCHECKSUMGENERATEIP)
3558 #define F_CCHECKSUMGENERATEIP V_CCHECKSUMGENERATEIP(1U)
3559
3560 #define S_OUT_CCPL 2
3561 #define V_OUT_CCPL(x) ((x) << S_OUT_CCPL)
3562 #define F_OUT_CCPL V_OUT_CCPL(1U)
3563
3564 #define S_OUT_CETHERNET 0
3565 #define V_OUT_CETHERNET(x) ((x) << S_OUT_CETHERNET)
3566 #define F_OUT_CETHERNET V_OUT_CETHERNET(1U)
3567
3568 #define A_TP_GLOBAL_CONFIG 0x308
3569
3570 #define S_SYNCOOKIEPARAMS 26
3571 #define M_SYNCOOKIEPARAMS 0x3f
3572 #define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS)
3573 #define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS)
3574
3575 #define S_RXFLOWCONTROLDISABLE 25
3576 #define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE)
3577 #define F_RXFLOWCONTROLDISABLE V_RXFLOWCONTROLDISABLE(1U)
3578
3579 #define S_TXPACINGENABLE 24
3580 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
3581 #define F_TXPACINGENABLE V_TXPACINGENABLE(1U)
3582
3583 #define S_ATTACKFILTERENABLE 23
3584 #define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE)
3585 #define F_ATTACKFILTERENABLE V_ATTACKFILTERENABLE(1U)
3586
3587 #define S_SYNCOOKIENOOPTIONS 22
3588 #define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS)
3589 #define F_SYNCOOKIENOOPTIONS V_SYNCOOKIENOOPTIONS(1U)
3590
3591 #define S_PROTECTEDMODE 21
3592 #define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE)
3593 #define F_PROTECTEDMODE V_PROTECTEDMODE(1U)
3594
3595 #define S_PINGDROP 20
3596 #define V_PINGDROP(x) ((x) << S_PINGDROP)
3597 #define F_PINGDROP V_PINGDROP(1U)
3598
3599 #define S_FRAGMENTDROP 19
3600 #define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP)
3601 #define F_FRAGMENTDROP V_FRAGMENTDROP(1U)
3602
3603 #define S_FIVETUPLELOOKUP 17
3604 #define M_FIVETUPLELOOKUP 0x3
3605 #define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP)
3606 #define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP)
3607
3608 #define S_PATHMTU 15
3609 #define V_PATHMTU(x) ((x) << S_PATHMTU)
3610 #define F_PATHMTU V_PATHMTU(1U)
3611
3612 #define S_IPIDENTSPLIT 14
3613 #define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT)
3614 #define F_IPIDENTSPLIT V_IPIDENTSPLIT(1U)
3615
3616 #define S_IPCHECKSUMOFFLOAD 13
3617 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
3618 #define F_IPCHECKSUMOFFLOAD V_IPCHECKSUMOFFLOAD(1U)
3619
3620 #define S_UDPCHECKSUMOFFLOAD 12
3621 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
3622 #define F_UDPCHECKSUMOFFLOAD V_UDPCHECKSUMOFFLOAD(1U)
3623
3624 #define S_TCPCHECKSUMOFFLOAD 11
3625 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
3626 #define F_TCPCHECKSUMOFFLOAD V_TCPCHECKSUMOFFLOAD(1U)
3627
3628 #define S_QOSMAPPING 10
3629 #define V_QOSMAPPING(x) ((x) << S_QOSMAPPING)
3630 #define F_QOSMAPPING V_QOSMAPPING(1U)
3631
3632 #define S_TCAMSERVERUSE 8
3633 #define M_TCAMSERVERUSE 0x3
3634 #define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE)
3635 #define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE)
3636
3637 #define S_IPTTL 0
3638 #define M_IPTTL 0xff
3639 #define V_IPTTL(x) ((x) << S_IPTTL)
3640 #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)
3641
3642 #define A_TP_GLOBAL_RX_CREDIT 0x30c
3643 #define A_TP_CMM_SIZE 0x310
3644
3645 #define S_CMMEMMGRSIZE 0
3646 #define M_CMMEMMGRSIZE 0xfffffff
3647 #define V_CMMEMMGRSIZE(x) ((x) << S_CMMEMMGRSIZE)
3648 #define G_CMMEMMGRSIZE(x) (((x) >> S_CMMEMMGRSIZE) & M_CMMEMMGRSIZE)
3649
3650 #define A_TP_CMM_MM_BASE 0x314
3651
3652 #define S_CMMEMMGRBASE 0
3653 #define M_CMMEMMGRBASE 0xfffffff
3654 #define V_CMMEMMGRBASE(x) ((x) << S_CMMEMMGRBASE)
3655 #define G_CMMEMMGRBASE(x) (((x) >> S_CMMEMMGRBASE) & M_CMMEMMGRBASE)
3656
3657 #define A_TP_CMM_TIMER_BASE 0x318
3658
3659 #define S_CMTIMERMAXNUM 28
3660 #define M_CMTIMERMAXNUM 0x3
3661 #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
3662 #define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM)
3663
3664 #define S_CMTIMERBASE 0
3665 #define M_CMTIMERBASE 0xfffffff
3666 #define V_CMTIMERBASE(x) ((x) << S_CMTIMERBASE)
3667 #define G_CMTIMERBASE(x) (((x) >> S_CMTIMERBASE) & M_CMTIMERBASE)
3668
3669 #define A_TP_PMM_SIZE 0x31c
3670
3671 #define S_PMSIZE 0
3672 #define M_PMSIZE 0xfffffff
3673 #define V_PMSIZE(x) ((x) << S_PMSIZE)
3674 #define G_PMSIZE(x) (((x) >> S_PMSIZE) & M_PMSIZE)
3675
3676 #define A_TP_PMM_TX_BASE 0x320
3677 #define A_TP_PMM_DEFRAG_BASE 0x324
3678 #define A_TP_PMM_RX_BASE 0x328
3679 #define A_TP_PMM_RX_PAGE_SIZE 0x32c
3680 #define A_TP_PMM_RX_MAX_PAGE 0x330
3681
3682 #define S_PMRXMAXPAGE 0
3683 #define M_PMRXMAXPAGE 0x1fffff
3684 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
3685 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)
3686
3687 #define A_TP_PMM_TX_PAGE_SIZE 0x334
3688 #define A_TP_PMM_TX_MAX_PAGE 0x338
3689
3690 #define S_PMTXMAXPAGE 0
3691 #define M_PMTXMAXPAGE 0x1fffff
3692 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
3693 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)
3694
3695 #define A_TP_TCP_OPTIONS 0x340
3696
3697 #define S_MTUDEFAULT 16
3698 #define M_MTUDEFAULT 0xffff
3699 #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
3700 #define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT)
3701
3702 #define S_MTUENABLE 10
3703 #define V_MTUENABLE(x) ((x) << S_MTUENABLE)
3704 #define F_MTUENABLE V_MTUENABLE(1U)
3705
3706 #define S_SACKTX 9
3707 #define V_SACKTX(x) ((x) << S_SACKTX)
3708 #define F_SACKTX V_SACKTX(1U)
3709
3710 #define S_SACKRX 8
3711 #define V_SACKRX(x) ((x) << S_SACKRX)
3712 #define F_SACKRX V_SACKRX(1U)
3713
3714 #define S_SACKMODE 4
3715 #define M_SACKMODE 0x3
3716 #define V_SACKMODE(x) ((x) << S_SACKMODE)
3717 #define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE)
3718
3719 #define S_WINDOWSCALEMODE 2
3720 #define M_WINDOWSCALEMODE 0x3
3721 #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
3722 #define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE)
3723
3724 #define S_TIMESTAMPSMODE 0
3725 #define M_TIMESTAMPSMODE 0x3
3726 #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
3727 #define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE)
3728
3729 #define A_TP_DACK_CONFIG 0x344
3730
3731 #define S_AUTOSTATE3 30
3732 #define M_AUTOSTATE3 0x3
3733 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
3734 #define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3)
3735
3736 #define S_AUTOSTATE2 28
3737 #define M_AUTOSTATE2 0x3
3738 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
3739 #define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2)
3740
3741 #define S_AUTOSTATE1 26
3742 #define M_AUTOSTATE1 0x3
3743 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
3744 #define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1)
3745
3746 #define S_BYTETHRESHOLD 5
3747 #define M_BYTETHRESHOLD 0xfffff
3748 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
3749 #define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD)
3750
3751 #define S_MSSTHRESHOLD 3
3752 #define M_MSSTHRESHOLD 0x3
3753 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
3754 #define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD)
3755
3756 #define S_AUTOCAREFUL 2
3757 #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
3758 #define F_AUTOCAREFUL V_AUTOCAREFUL(1U)
3759
3760 #define S_AUTOENABLE 1
3761 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
3762 #define F_AUTOENABLE V_AUTOENABLE(1U)
3763
3764 #define S_DACK_MODE 0
3765 #define V_DACK_MODE(x) ((x) << S_DACK_MODE)
3766 #define F_DACK_MODE V_DACK_MODE(1U)
3767
3768 #define A_TP_PC_CONFIG 0x348
3769
3770 #define S_CMCACHEDISABLE 31
3771 #define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE)
3772 #define F_CMCACHEDISABLE V_CMCACHEDISABLE(1U)
3773
3774 #define S_ENABLEOCSPIFULL 30
3775 #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
3776 #define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U)
3777
3778 #define S_ENABLEFLMERRORDDP 29
3779 #define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP)
3780 #define F_ENABLEFLMERRORDDP V_ENABLEFLMERRORDDP(1U)
3781
3782 #define S_LOCKTID 28
3783 #define V_LOCKTID(x) ((x) << S_LOCKTID)
3784 #define F_LOCKTID V_LOCKTID(1U)
3785
3786 #define S_FIXRCVWND 27
3787 #define V_FIXRCVWND(x) ((x) << S_FIXRCVWND)
3788 #define F_FIXRCVWND V_FIXRCVWND(1U)
3789
3790 #define S_TXTOSQUEUEMAPMODE 26
3791 #define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE)
3792 #define F_TXTOSQUEUEMAPMODE V_TXTOSQUEUEMAPMODE(1U)
3793
3794 #define S_RDDPCONGEN 25
3795 #define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN)
3796 #define F_RDDPCONGEN V_RDDPCONGEN(1U)
3797
3798 #define S_ENABLEONFLYPDU 24
3799 #define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU)
3800 #define F_ENABLEONFLYPDU V_ENABLEONFLYPDU(1U)
3801
3802 #define S_ENABLEEPCMDAFULL 23
3803 #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
3804 #define F_ENABLEEPCMDAFULL V_ENABLEEPCMDAFULL(1U)
3805
3806 #define S_MODULATEUNIONMODE 22
3807 #define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE)
3808 #define F_MODULATEUNIONMODE V_MODULATEUNIONMODE(1U)
3809
3810 #define S_TXDATAACKRATEENABLE 21
3811 #define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE)
3812 #define F_TXDATAACKRATEENABLE V_TXDATAACKRATEENABLE(1U)
3813
3814 #define S_TXDEFERENABLE 20
3815 #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
3816 #define F_TXDEFERENABLE V_TXDEFERENABLE(1U)
3817
3818 #define S_RXCONGESTIONMODE 19
3819 #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
3820 #define F_RXCONGESTIONMODE V_RXCONGESTIONMODE(1U)
3821
3822 #define S_HEARBEATONCEDACK 18
3823 #define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK)
3824 #define F_HEARBEATONCEDACK V_HEARBEATONCEDACK(1U)
3825
3826 #define S_HEARBEATONCEHEAP 17
3827 #define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP)
3828 #define F_HEARBEATONCEHEAP V_HEARBEATONCEHEAP(1U)
3829
3830 #define S_HEARBEATDACK 16
3831 #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
3832 #define F_HEARBEATDACK V_HEARBEATDACK(1U)
3833
3834 #define S_TXCONGESTIONMODE 15
3835 #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
3836 #define F_TXCONGESTIONMODE V_TXCONGESTIONMODE(1U)
3837
3838 #define S_ACCEPTLATESTRCVADV 14
3839 #define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV)
3840 #define F_ACCEPTLATESTRCVADV V_ACCEPTLATESTRCVADV(1U)
3841
3842 #define S_DISABLESYNDATA 13
3843 #define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA)
3844 #define F_DISABLESYNDATA V_DISABLESYNDATA(1U)
3845
3846 #define S_DISABLEWINDOWPSH 12
3847 #define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH)
3848 #define F_DISABLEWINDOWPSH V_DISABLEWINDOWPSH(1U)
3849
3850 #define S_DISABLEFINOLDDATA 11
3851 #define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA)
3852 #define F_DISABLEFINOLDDATA V_DISABLEFINOLDDATA(1U)
3853
3854 #define S_ENABLEFLMERROR 10
3855 #define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR)
3856 #define F_ENABLEFLMERROR V_ENABLEFLMERROR(1U)
3857
3858 #define S_DISABLENEXTMTU 9
3859 #define V_DISABLENEXTMTU(x) ((x) << S_DISABLENEXTMTU)
3860 #define F_DISABLENEXTMTU V_DISABLENEXTMTU(1U)
3861
3862 #define S_FILTERPEERFIN 8
3863 #define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN)
3864 #define F_FILTERPEERFIN V_FILTERPEERFIN(1U)
3865
3866 #define S_ENABLEFEEDBACKSEND 7
3867 #define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND)
3868 #define F_ENABLEFEEDBACKSEND V_ENABLEFEEDBACKSEND(1U)
3869
3870 #define S_ENABLERDMAERROR 6
3871 #define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR)
3872 #define F_ENABLERDMAERROR V_ENABLERDMAERROR(1U)
3873
3874 #define S_ENABLEDDPFLOWCONTROL 5
3875 #define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL)
3876 #define F_ENABLEDDPFLOWCONTROL V_ENABLEDDPFLOWCONTROL(1U)
3877
3878 #define S_DISABLEHELDFIN 4
3879 #define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN)
3880 #define F_DISABLEHELDFIN V_DISABLEHELDFIN(1U)
3881
3882 #define S_TABLELATENCYDELTA 0
3883 #define M_TABLELATENCYDELTA 0xf
3884 #define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA)
3885 #define G_TABLELATENCYDELTA(x) (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA)
3886
3887 #define A_TP_PC_CONFIG2 0x34c
3888
3889 #define S_DISBLEDAPARBIT0 15
3890 #define V_DISBLEDAPARBIT0(x) ((x) << S_DISBLEDAPARBIT0)
3891 #define F_DISBLEDAPARBIT0 V_DISBLEDAPARBIT0(1U)
3892
3893 #define S_ENABLEARPMISS 13
3894 #define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)
3895 #define F_ENABLEARPMISS V_ENABLEARPMISS(1U)
3896
3897 #define S_ENABLENONOFDTNLSYN 12
3898 #define V_ENABLENONOFDTNLSYN(x) ((x) << S_ENABLENONOFDTNLSYN)
3899 #define F_ENABLENONOFDTNLSYN V_ENABLENONOFDTNLSYN(1U)
3900
3901 #define S_ENABLEIPV6RSS 11
3902 #define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)
3903 #define F_ENABLEIPV6RSS V_ENABLEIPV6RSS(1U)
3904
3905 #define S_ENABLEDROPRQEMPTYPKT 10
3906 #define V_ENABLEDROPRQEMPTYPKT(x) ((x) << S_ENABLEDROPRQEMPTYPKT)
3907 #define F_ENABLEDROPRQEMPTYPKT V_ENABLEDROPRQEMPTYPKT(1U)
3908
3909 #define S_ENABLETXPORTFROMDA2 9
3910 #define V_ENABLETXPORTFROMDA2(x) ((x) << S_ENABLETXPORTFROMDA2)
3911 #define F_ENABLETXPORTFROMDA2 V_ENABLETXPORTFROMDA2(1U)
3912
3913 #define S_ENABLERXPKTTMSTPRSS 8
3914 #define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS)
3915 #define F_ENABLERXPKTTMSTPRSS V_ENABLERXPKTTMSTPRSS(1U)
3916
3917 #define S_ENABLESNDUNAINRXDATA 7
3918 #define V_ENABLESNDUNAINRXDATA(x) ((x) << S_ENABLESNDUNAINRXDATA)
3919 #define F_ENABLESNDUNAINRXDATA V_ENABLESNDUNAINRXDATA(1U)
3920
3921 #define S_ENABLERXPORTFROMADDR 6
3922 #define V_ENABLERXPORTFROMADDR(x) ((x) << S_ENABLERXPORTFROMADDR)
3923 #define F_ENABLERXPORTFROMADDR V_ENABLERXPORTFROMADDR(1U)
3924
3925 #define S_ENABLETXPORTFROMDA 5
3926 #define V_ENABLETXPORTFROMDA(x) ((x) << S_ENABLETXPORTFROMDA)
3927 #define F_ENABLETXPORTFROMDA V_ENABLETXPORTFROMDA(1U)
3928
3929 #define S_ENABLECHDRAFULL 4
3930 #define V_ENABLECHDRAFULL(x) ((x) << S_ENABLECHDRAFULL)
3931 #define F_ENABLECHDRAFULL V_ENABLECHDRAFULL(1U)
3932
3933 #define S_ENABLENONOFDSCBBIT 3
3934 #define V_ENABLENONOFDSCBBIT(x) ((x) << S_ENABLENONOFDSCBBIT)
3935 #define F_ENABLENONOFDSCBBIT V_ENABLENONOFDSCBBIT(1U)
3936
3937 #define S_ENABLENONOFDTIDRSS 2
3938 #define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS)
3939 #define F_ENABLENONOFDTIDRSS V_ENABLENONOFDTIDRSS(1U)
3940
3941 #define S_ENABLENONOFDTCBRSS 1
3942 #define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS)
3943 #define F_ENABLENONOFDTCBRSS V_ENABLENONOFDTCBRSS(1U)
3944
3945 #define S_ENABLEOLDRXFORWARD 0
3946 #define V_ENABLEOLDRXFORWARD(x) ((x) << S_ENABLEOLDRXFORWARD)
3947 #define F_ENABLEOLDRXFORWARD V_ENABLEOLDRXFORWARD(1U)
3948
3949 #define S_CHDRAFULL 4
3950 #define V_CHDRAFULL(x) ((x) << S_CHDRAFULL)
3951 #define F_CHDRAFULL V_CHDRAFULL(1U)
3952
3953 #define A_TP_TCP_BACKOFF_REG0 0x350
3954
3955 #define S_TIMERBACKOFFINDEX3 24
3956 #define M_TIMERBACKOFFINDEX3 0xff
3957 #define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3)
3958 #define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3)
3959
3960 #define S_TIMERBACKOFFINDEX2 16
3961 #define M_TIMERBACKOFFINDEX2 0xff
3962 #define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2)
3963 #define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2)
3964
3965 #define S_TIMERBACKOFFINDEX1 8
3966 #define M_TIMERBACKOFFINDEX1 0xff
3967 #define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1)
3968 #define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1)
3969
3970 #define S_TIMERBACKOFFINDEX0 0
3971 #define M_TIMERBACKOFFINDEX0 0xff
3972 #define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0)
3973 #define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0)
3974
3975 #define A_TP_TCP_BACKOFF_REG1 0x354
3976
3977 #define S_TIMERBACKOFFINDEX7 24
3978 #define M_TIMERBACKOFFINDEX7 0xff
3979 #define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7)
3980 #define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7)
3981
3982 #define S_TIMERBACKOFFINDEX6 16
3983 #define M_TIMERBACKOFFINDEX6 0xff
3984 #define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6)
3985 #define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6)
3986
3987 #define S_TIMERBACKOFFINDEX5 8
3988 #define M_TIMERBACKOFFINDEX5 0xff
3989 #define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5)
3990 #define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5)
3991
3992 #define S_TIMERBACKOFFINDEX4 0
3993 #define M_TIMERBACKOFFINDEX4 0xff
3994 #define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4)
3995 #define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4)
3996
3997 #define A_TP_TCP_BACKOFF_REG2 0x358
3998
3999 #define S_TIMERBACKOFFINDEX11 24
4000 #define M_TIMERBACKOFFINDEX11 0xff
4001 #define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11)
4002 #define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11)
4003
4004 #define S_TIMERBACKOFFINDEX10 16
4005 #define M_TIMERBACKOFFINDEX10 0xff
4006 #define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10)
4007 #define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10)
4008
4009 #define S_TIMERBACKOFFINDEX9 8
4010 #define M_TIMERBACKOFFINDEX9 0xff
4011 #define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9)
4012 #define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9)
4013
4014 #define S_TIMERBACKOFFINDEX8 0
4015 #define M_TIMERBACKOFFINDEX8 0xff
4016 #define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8)
4017 #define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8)
4018
4019 #define A_TP_TCP_BACKOFF_REG3 0x35c
4020
4021 #define S_TIMERBACKOFFINDEX15 24
4022 #define M_TIMERBACKOFFINDEX15 0xff
4023 #define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15)
4024 #define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15)
4025
4026 #define S_TIMERBACKOFFINDEX14 16
4027 #define M_TIMERBACKOFFINDEX14 0xff
4028 #define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14)
4029 #define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14)
4030
4031 #define S_TIMERBACKOFFINDEX13 8
4032 #define M_TIMERBACKOFFINDEX13 0xff
4033 #define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13)
4034 #define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13)
4035
4036 #define S_TIMERBACKOFFINDEX12 0
4037 #define M_TIMERBACKOFFINDEX12 0xff
4038 #define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12)
4039 #define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12)
4040
4041 #define A_TP_PARA_REG0 0x360
4042
4043 #define S_INITCWND 24
4044 #define M_INITCWND 0x7
4045 #define V_INITCWND(x) ((x) << S_INITCWND)
4046 #define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND)
4047
4048 #define S_DUPACKTHRESH 20
4049 #define M_DUPACKTHRESH 0xf
4050 #define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH)
4051 #define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH)
4052
4053 #define A_TP_PARA_REG1 0x364
4054
4055 #define S_INITRWND 16
4056 #define M_INITRWND 0xffff
4057 #define V_INITRWND(x) ((x) << S_INITRWND)
4058 #define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND)
4059
4060 #define S_INITIALSSTHRESH 0
4061 #define M_INITIALSSTHRESH 0xffff
4062 #define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH)
4063 #define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH)
4064
4065 #define A_TP_PARA_REG2 0x368
4066
4067 #define S_MAXRXDATA 16
4068 #define M_MAXRXDATA 0xffff
4069 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
4070 #define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA)
4071
4072 #define S_RXCOALESCESIZE 0
4073 #define M_RXCOALESCESIZE 0xffff
4074 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
4075 #define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE)
4076
4077 #define A_TP_PARA_REG3 0x36c
4078
4079 #define S_TUNNELCNGDROP1 21
4080 #define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1)
4081 #define F_TUNNELCNGDROP1 V_TUNNELCNGDROP1(1U)
4082
4083 #define S_TUNNELCNGDROP0 20
4084 #define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0)
4085 #define F_TUNNELCNGDROP0 V_TUNNELCNGDROP0(1U)
4086
4087 #define S_TXDATAACKIDX 16
4088 #define M_TXDATAACKIDX 0xf
4089 #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
4090 #define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX)
4091
4092 #define S_RXFRAGENABLE 12
4093 #define M_RXFRAGENABLE 0x7
4094 #define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE)
4095 #define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE)
4096
4097 #define S_TXPACEFIXEDSTRICT 11
4098 #define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT)
4099 #define F_TXPACEFIXEDSTRICT V_TXPACEFIXEDSTRICT(1U)
4100
4101 #define S_TXPACEAUTOSTRICT 10
4102 #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
4103 #define F_TXPACEAUTOSTRICT V_TXPACEAUTOSTRICT(1U)
4104
4105 #define S_TXPACEFIXED 9
4106 #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
4107 #define F_TXPACEFIXED V_TXPACEFIXED(1U)
4108
4109 #define S_TXPACEAUTO 8
4110 #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
4111 #define F_TXPACEAUTO V_TXPACEAUTO(1U)
4112
4113 #define S_RXURGTUNNEL 6
4114 #define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL)
4115 #define F_RXURGTUNNEL V_RXURGTUNNEL(1U)
4116
4117 #define S_RXURGMODE 5
4118 #define V_RXURGMODE(x) ((x) << S_RXURGMODE)
4119 #define F_RXURGMODE V_RXURGMODE(1U)
4120
4121 #define S_TXURGMODE 4
4122 #define V_TXURGMODE(x) ((x) << S_TXURGMODE)
4123 #define F_TXURGMODE V_TXURGMODE(1U)
4124
4125 #define S_CNGCTRLMODE 2
4126 #define M_CNGCTRLMODE 0x3
4127 #define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE)
4128 #define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE)
4129
4130 #define S_RXCOALESCEENABLE 1
4131 #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
4132 #define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U)
4133
4134 #define S_RXCOALESCEPSHEN 0
4135 #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
4136 #define F_RXCOALESCEPSHEN V_RXCOALESCEPSHEN(1U)
4137
4138 #define A_TP_PARA_REG4 0x370
4139
4140 #define S_HIGHSPEEDCFG 24
4141 #define M_HIGHSPEEDCFG 0xff
4142 #define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG)
4143 #define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG)
4144
4145 #define S_NEWRENOCFG 16
4146 #define M_NEWRENOCFG 0xff
4147 #define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG)
4148 #define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG)
4149
4150 #define S_TAHOECFG 8
4151 #define M_TAHOECFG 0xff
4152 #define V_TAHOECFG(x) ((x) << S_TAHOECFG)
4153 #define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG)
4154
4155 #define S_RENOCFG 0
4156 #define M_RENOCFG 0xff
4157 #define V_RENOCFG(x) ((x) << S_RENOCFG)
4158 #define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG)
4159
4160 #define A_TP_PARA_REG5 0x374
4161
4162 #define S_INDICATESIZE 16
4163 #define M_INDICATESIZE 0xffff
4164 #define V_INDICATESIZE(x) ((x) << S_INDICATESIZE)
4165 #define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE)
4166
4167 #define S_SCHDENABLE 8
4168 #define V_SCHDENABLE(x) ((x) << S_SCHDENABLE)
4169 #define F_SCHDENABLE V_SCHDENABLE(1U)
4170
4171 #define S_RXDDPOFFINIT 3
4172 #define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)
4173 #define F_RXDDPOFFINIT V_RXDDPOFFINIT(1U)
4174
4175 #define S_ONFLYDDPENABLE 2
4176 #define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE)
4177 #define F_ONFLYDDPENABLE V_ONFLYDDPENABLE(1U)
4178
4179 #define S_DACKTIMERSPIN 1
4180 #define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN)
4181 #define F_DACKTIMERSPIN V_DACKTIMERSPIN(1U)
4182
4183 #define S_PUSHTIMERENABLE 0
4184 #define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE)
4185 #define F_PUSHTIMERENABLE V_PUSHTIMERENABLE(1U)
4186
4187 #define A_TP_PARA_REG6 0x378
4188
4189 #define S_TXPDUSIZEADJ 16
4190 #define M_TXPDUSIZEADJ 0xff
4191 #define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ)
4192 #define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ)
4193
4194 #define S_ENABLEDEFERACK 12
4195 #define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK)
4196 #define F_ENABLEDEFERACK V_ENABLEDEFERACK(1U)
4197
4198 #define S_ENABLEESND 11
4199 #define V_ENABLEESND(x) ((x) << S_ENABLEESND)
4200 #define F_ENABLEESND V_ENABLEESND(1U)
4201
4202 #define S_ENABLECSND 10
4203 #define V_ENABLECSND(x) ((x) << S_ENABLECSND)
4204 #define F_ENABLECSND V_ENABLECSND(1U)
4205
4206 #define S_ENABLEPDUE 9
4207 #define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE)
4208 #define F_ENABLEPDUE V_ENABLEPDUE(1U)
4209
4210 #define S_ENABLEPDUC 8
4211 #define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC)
4212 #define F_ENABLEPDUC V_ENABLEPDUC(1U)
4213
4214 #define S_ENABLEBUFI 7
4215 #define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI)
4216 #define F_ENABLEBUFI V_ENABLEBUFI(1U)
4217
4218 #define S_ENABLEBUFE 6
4219 #define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE)
4220 #define F_ENABLEBUFE V_ENABLEBUFE(1U)
4221
4222 #define S_ENABLEDEFER 5
4223 #define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER)
4224 #define F_ENABLEDEFER V_ENABLEDEFER(1U)
4225
4226 #define S_ENABLECLEARRXMTOOS 4
4227 #define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS)
4228 #define F_ENABLECLEARRXMTOOS V_ENABLECLEARRXMTOOS(1U)
4229
4230 #define S_DISABLEPDUCNG 3
4231 #define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG)
4232 #define F_DISABLEPDUCNG V_DISABLEPDUCNG(1U)
4233
4234 #define S_DISABLEPDUTIMEOUT 2
4235 #define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT)
4236 #define F_DISABLEPDUTIMEOUT V_DISABLEPDUTIMEOUT(1U)
4237
4238 #define S_DISABLEPDURXMT 1
4239 #define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT)
4240 #define F_DISABLEPDURXMT V_DISABLEPDURXMT(1U)
4241
4242 #define S_DISABLEPDUXMT 0
4243 #define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT)
4244 #define F_DISABLEPDUXMT V_DISABLEPDUXMT(1U)
4245
4246 #define S_ENABLEEPDU 14
4247 #define V_ENABLEEPDU(x) ((x) << S_ENABLEEPDU)
4248 #define F_ENABLEEPDU V_ENABLEEPDU(1U)
4249
4250 #define S_T3A_ENABLEESND 13
4251 #define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND)
4252 #define F_T3A_ENABLEESND V_T3A_ENABLEESND(1U)
4253
4254 #define S_T3A_ENABLECSND 12
4255 #define V_T3A_ENABLECSND(x) ((x) << S_T3A_ENABLECSND)
4256 #define F_T3A_ENABLECSND V_T3A_ENABLECSND(1U)
4257
4258 #define S_T3A_ENABLEDEFERACK 9
4259 #define V_T3A_ENABLEDEFERACK(x) ((x) << S_T3A_ENABLEDEFERACK)
4260 #define F_T3A_ENABLEDEFERACK V_T3A_ENABLEDEFERACK(1U)
4261
4262 #define S_ENABLEPDUI 7
4263 #define V_ENABLEPDUI(x) ((x) << S_ENABLEPDUI)
4264 #define F_ENABLEPDUI V_ENABLEPDUI(1U)
4265
4266 #define S_T3A_ENABLEPDUE 6
4267 #define V_T3A_ENABLEPDUE(x) ((x) << S_T3A_ENABLEPDUE)
4268 #define F_T3A_ENABLEPDUE V_T3A_ENABLEPDUE(1U)
4269
4270 #define A_TP_PARA_REG7 0x37c
4271
4272 #define S_PMMAXXFERLEN1 16
4273 #define M_PMMAXXFERLEN1 0xffff
4274 #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
4275 #define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1)
4276
4277 #define S_PMMAXXFERLEN0 0
4278 #define M_PMMAXXFERLEN0 0xffff
4279 #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
4280 #define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0)
4281
4282 #define A_TP_TIMER_RESOLUTION 0x390
4283
4284 #define S_TIMERRESOLUTION 16
4285 #define M_TIMERRESOLUTION 0xff
4286 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
4287 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
4288
4289 #define S_TIMESTAMPRESOLUTION 8
4290 #define M_TIMESTAMPRESOLUTION 0xff
4291 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
4292 #define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)
4293
4294 #define S_DELAYEDACKRESOLUTION 0
4295 #define M_DELAYEDACKRESOLUTION 0xff
4296 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
4297 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
4298
4299 #define A_TP_MSL 0x394
4300
4301 #define S_MSL 0
4302 #define M_MSL 0x3fffffff
4303 #define V_MSL(x) ((x) << S_MSL)
4304 #define G_MSL(x) (((x) >> S_MSL) & M_MSL)
4305
4306 #define A_TP_RXT_MIN 0x398
4307
4308 #define S_RXTMIN 0
4309 #define M_RXTMIN 0x3fffffff
4310 #define V_RXTMIN(x) ((x) << S_RXTMIN)
4311 #define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN)
4312
4313 #define A_TP_RXT_MAX 0x39c
4314
4315 #define S_RXTMAX 0
4316 #define M_RXTMAX 0x3fffffff
4317 #define V_RXTMAX(x) ((x) << S_RXTMAX)
4318 #define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX)
4319
4320 #define A_TP_PERS_MIN 0x3a0
4321
4322 #define S_PERSMIN 0
4323 #define M_PERSMIN 0x3fffffff
4324 #define V_PERSMIN(x) ((x) << S_PERSMIN)
4325 #define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN)
4326
4327 #define A_TP_PERS_MAX 0x3a4
4328
4329 #define S_PERSMAX 0
4330 #define M_PERSMAX 0x3fffffff
4331 #define V_PERSMAX(x) ((x) << S_PERSMAX)
4332 #define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX)
4333
4334 #define A_TP_KEEP_IDLE 0x3a8
4335
4336 #define S_KEEPALIVEIDLE 0
4337 #define M_KEEPALIVEIDLE 0x3fffffff
4338 #define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE)
4339 #define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE)
4340
4341 #define A_TP_KEEP_INTVL 0x3ac
4342
4343 #define S_KEEPALIVEINTVL 0
4344 #define M_KEEPALIVEINTVL 0x3fffffff
4345 #define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL)
4346 #define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL)
4347
4348 #define A_TP_INIT_SRTT 0x3b0
4349
4350 #define S_INITSRTT 0
4351 #define M_INITSRTT 0xffff
4352 #define V_INITSRTT(x) ((x) << S_INITSRTT)
4353 #define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT)
4354
4355 #define A_TP_DACK_TIMER 0x3b4
4356
4357 #define S_DACKTIME 0
4358 #define M_DACKTIME 0xfff
4359 #define V_DACKTIME(x) ((x) << S_DACKTIME)
4360 #define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME)
4361
4362 #define A_TP_FINWAIT2_TIMER 0x3b8
4363
4364 #define S_FINWAIT2TIME 0
4365 #define M_FINWAIT2TIME 0x3fffffff
4366 #define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME)
4367 #define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME)
4368
4369 #define A_TP_FAST_FINWAIT2_TIMER 0x3bc
4370
4371 #define S_FASTFINWAIT2TIME 0
4372 #define M_FASTFINWAIT2TIME 0x3fffffff
4373 #define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME)
4374 #define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME)
4375
4376 #define A_TP_SHIFT_CNT 0x3c0
4377
4378 #define S_SYNSHIFTMAX 24
4379 #define M_SYNSHIFTMAX 0xff
4380 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
4381 #define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX)
4382
4383 #define S_RXTSHIFTMAXR1 20
4384 #define M_RXTSHIFTMAXR1 0xf
4385 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
4386 #define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1)
4387
4388 #define S_RXTSHIFTMAXR2 16
4389 #define M_RXTSHIFTMAXR2 0xf
4390 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
4391 #define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2)
4392
4393 #define S_PERSHIFTBACKOFFMAX 12
4394 #define M_PERSHIFTBACKOFFMAX 0xf
4395 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
4396 #define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)
4397
4398 #define S_PERSHIFTMAX 8
4399 #define M_PERSHIFTMAX 0xf
4400 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
4401 #define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX)
4402
4403 #define S_KEEPALIVEMAX 0
4404 #define M_KEEPALIVEMAX 0xff
4405 #define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX)
4406 #define G_KEEPALIVEMAX(x) (((x) >> S_KEEPALIVEMAX) & M_KEEPALIVEMAX)
4407
4408 #define A_TP_TIME_HI 0x3c8
4409 #define A_TP_TIME_LO 0x3cc
4410 #define A_TP_MTU_PORT_TABLE 0x3d0
4411
4412 #define S_PORT1MTUVALUE 16
4413 #define M_PORT1MTUVALUE 0xffff
4414 #define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE)
4415 #define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE)
4416
4417 #define S_PORT0MTUVALUE 0
4418 #define M_PORT0MTUVALUE 0xffff
4419 #define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE)
4420 #define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE)
4421
4422 #define A_TP_ULP_TABLE 0x3d4
4423
4424 #define S_ULPTYPE7FIELD 28
4425 #define M_ULPTYPE7FIELD 0xf
4426 #define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD)
4427 #define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD)
4428
4429 #define S_ULPTYPE6FIELD 24
4430 #define M_ULPTYPE6FIELD 0xf
4431 #define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD)
4432 #define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD)
4433
4434 #define S_ULPTYPE5FIELD 20
4435 #define M_ULPTYPE5FIELD 0xf
4436 #define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD)
4437 #define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD)
4438
4439 #define S_ULPTYPE4FIELD 16
4440 #define M_ULPTYPE4FIELD 0xf
4441 #define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD)
4442 #define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD)
4443
4444 #define S_ULPTYPE3FIELD 12
4445 #define M_ULPTYPE3FIELD 0xf
4446 #define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD)
4447 #define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD)
4448
4449 #define S_ULPTYPE2FIELD 8
4450 #define M_ULPTYPE2FIELD 0xf
4451 #define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD)
4452 #define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD)
4453
4454 #define S_ULPTYPE1FIELD 4
4455 #define M_ULPTYPE1FIELD 0xf
4456 #define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD)
4457 #define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD)
4458
4459 #define S_ULPTYPE0FIELD 0
4460 #define M_ULPTYPE0FIELD 0xf
4461 #define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD)
4462 #define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD)
4463
4464 #define A_TP_PACE_TABLE 0x3d8
4465 #define A_TP_CCTRL_TABLE 0x3dc
4466 #define A_TP_TOS_TABLE 0x3e0
4467 #define A_TP_MTU_TABLE 0x3e4
4468 #define A_TP_RSS_MAP_TABLE 0x3e8
4469 #define A_TP_RSS_LKP_TABLE 0x3ec
4470 #define A_TP_RSS_CONFIG 0x3f0
4471
4472 #define S_TNL4TUPEN 29
4473 #define V_TNL4TUPEN(x) ((x) << S_TNL4TUPEN)
4474 #define F_TNL4TUPEN V_TNL4TUPEN(1U)
4475
4476 #define S_TNL2TUPEN 28
4477 #define V_TNL2TUPEN(x) ((x) << S_TNL2TUPEN)
4478 #define F_TNL2TUPEN V_TNL2TUPEN(1U)
4479
4480 #define S_TNLPRTEN 26
4481 #define V_TNLPRTEN(x) ((x) << S_TNLPRTEN)
4482 #define F_TNLPRTEN V_TNLPRTEN(1U)
4483
4484 #define S_TNLMAPEN 25
4485 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
4486 #define F_TNLMAPEN V_TNLMAPEN(1U)
4487
4488 #define S_TNLLKPEN 24
4489 #define V_TNLLKPEN(x) ((x) << S_TNLLKPEN)
4490 #define F_TNLLKPEN V_TNLLKPEN(1U)
4491
4492 #define S_OFD4TUPEN 21
4493 #define V_OFD4TUPEN(x) ((x) << S_OFD4TUPEN)
4494 #define F_OFD4TUPEN V_OFD4TUPEN(1U)
4495
4496 #define S_OFD2TUPEN 20
4497 #define V_OFD2TUPEN(x) ((x) << S_OFD2TUPEN)
4498 #define F_OFD2TUPEN V_OFD2TUPEN(1U)
4499
4500 #define S_OFDMAPEN 17
4501 #define V_OFDMAPEN(x) ((x) << S_OFDMAPEN)
4502 #define F_OFDMAPEN V_OFDMAPEN(1U)
4503
4504 #define S_OFDLKPEN 16
4505 #define V_OFDLKPEN(x) ((x) << S_OFDLKPEN)
4506 #define F_OFDLKPEN V_OFDLKPEN(1U)
4507
4508 #define S_SYN4TUPEN 13
4509 #define V_SYN4TUPEN(x) ((x) << S_SYN4TUPEN)
4510 #define F_SYN4TUPEN V_SYN4TUPEN(1U)
4511
4512 #define S_SYN2TUPEN 12
4513 #define V_SYN2TUPEN(x) ((x) << S_SYN2TUPEN)
4514 #define F_SYN2TUPEN V_SYN2TUPEN(1U)
4515
4516 #define S_SYNMAPEN 9
4517 #define V_SYNMAPEN(x) ((x) << S_SYNMAPEN)
4518 #define F_SYNMAPEN V_SYNMAPEN(1U)
4519
4520 #define S_SYNLKPEN 8
4521 #define V_SYNLKPEN(x) ((x) << S_SYNLKPEN)
4522 #define F_SYNLKPEN V_SYNLKPEN(1U)
4523
4524 #define S_RRCPLMAPEN 7
4525 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
4526 #define F_RRCPLMAPEN V_RRCPLMAPEN(1U)
4527
4528 #define S_RRCPLCPUSIZE 4
4529 #define M_RRCPLCPUSIZE 0x7
4530 #define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE)
4531 #define G_RRCPLCPUSIZE(x) (((x) >> S_RRCPLCPUSIZE) & M_RRCPLCPUSIZE)
4532
4533 #define S_RQFEEDBACKENABLE 3
4534 #define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE)
4535 #define F_RQFEEDBACKENABLE V_RQFEEDBACKENABLE(1U)
4536
4537 #define S_HASHTOEPLITZ 2
4538 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
4539 #define F_HASHTOEPLITZ V_HASHTOEPLITZ(1U)
4540
4541 #define S_HASHSAVE 1
4542 #define V_HASHSAVE(x) ((x) << S_HASHSAVE)
4543 #define F_HASHSAVE V_HASHSAVE(1U)
4544
4545 #define S_DISABLE 0
4546 #define V_DISABLE(x) ((x) << S_DISABLE)
4547 #define F_DISABLE V_DISABLE(1U)
4548
4549 #define A_TP_RSS_CONFIG_TNL 0x3f4
4550
4551 #define S_MASKSIZE 28
4552 #define M_MASKSIZE 0x7
4553 #define V_MASKSIZE(x) ((x) << S_MASKSIZE)
4554 #define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE)
4555
4556 #define S_DEFAULTCPUBASE 22
4557 #define M_DEFAULTCPUBASE 0x3f
4558 #define V_DEFAULTCPUBASE(x) ((x) << S_DEFAULTCPUBASE)
4559 #define G_DEFAULTCPUBASE(x) (((x) >> S_DEFAULTCPUBASE) & M_DEFAULTCPUBASE)
4560
4561 #define S_DEFAULTCPU 16
4562 #define M_DEFAULTCPU 0x3f
4563 #define V_DEFAULTCPU(x) ((x) << S_DEFAULTCPU)
4564 #define G_DEFAULTCPU(x) (((x) >> S_DEFAULTCPU) & M_DEFAULTCPU)
4565
4566 #define S_DEFAULTQUEUE 0
4567 #define M_DEFAULTQUEUE 0xffff
4568 #define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE)
4569 #define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE)
4570
4571 #define A_TP_RSS_CONFIG_OFD 0x3f8
4572 #define A_TP_RSS_CONFIG_SYN 0x3fc
4573 #define A_TP_RSS_SECRET_KEY0 0x400
4574 #define A_TP_RSS_SECRET_KEY1 0x404
4575 #define A_TP_RSS_SECRET_KEY2 0x408
4576 #define A_TP_RSS_SECRET_KEY3 0x40c
4577 #define A_TP_TM_PIO_ADDR 0x418
4578 #define A_TP_TM_PIO_DATA 0x41c
4579 #define A_TP_TX_MOD_QUE_TABLE 0x420
4580 #define A_TP_TX_RESOURCE_LIMIT 0x424
4581
4582 #define S_TX_RESOURCE_LIMIT_CH1_PC 24
4583 #define M_TX_RESOURCE_LIMIT_CH1_PC 0xff
4584 #define V_TX_RESOURCE_LIMIT_CH1_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_PC)
4585 #define G_TX_RESOURCE_LIMIT_CH1_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_PC) & M_TX_RESOURCE_LIMIT_CH1_PC)
4586
4587 #define S_TX_RESOURCE_LIMIT_CH1_NON_PC 16
4588 #define M_TX_RESOURCE_LIMIT_CH1_NON_PC 0xff
4589 #define V_TX_RESOURCE_LIMIT_CH1_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_NON_PC)
4590 #define G_TX_RESOURCE_LIMIT_CH1_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_NON_PC) & M_TX_RESOURCE_LIMIT_CH1_NON_PC)
4591
4592 #define S_TX_RESOURCE_LIMIT_CH0_PC 8
4593 #define M_TX_RESOURCE_LIMIT_CH0_PC 0xff
4594 #define V_TX_RESOURCE_LIMIT_CH0_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_PC)
4595 #define G_TX_RESOURCE_LIMIT_CH0_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_PC) & M_TX_RESOURCE_LIMIT_CH0_PC)
4596
4597 #define S_TX_RESOURCE_LIMIT_CH0_NON_PC 0
4598 #define M_TX_RESOURCE_LIMIT_CH0_NON_PC 0xff
4599 #define V_TX_RESOURCE_LIMIT_CH0_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_NON_PC)
4600 #define G_TX_RESOURCE_LIMIT_CH0_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_NON_PC) & M_TX_RESOURCE_LIMIT_CH0_NON_PC)
4601
4602 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428
4603
4604 #define S_RX_MOD_WEIGHT 24
4605 #define M_RX_MOD_WEIGHT 0xff
4606 #define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT)
4607 #define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT)
4608
4609 #define S_TX_MOD_WEIGHT 16
4610 #define M_TX_MOD_WEIGHT 0xff
4611 #define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT)
4612 #define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT)
4613
4614 #define S_TX_MOD_TIMER_MODE 8
4615 #define M_TX_MOD_TIMER_MODE 0xff
4616 #define V_TX_MOD_TIMER_MODE(x) ((x) << S_TX_MOD_TIMER_MODE)
4617 #define G_TX_MOD_TIMER_MODE(x) (((x) >> S_TX_MOD_TIMER_MODE) & M_TX_MOD_TIMER_MODE)
4618
4619 #define S_TX_MOD_QUEUE_REQ_MAP 0
4620 #define M_TX_MOD_QUEUE_REQ_MAP 0xff
4621 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
4622 #define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)
4623
4624 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c
4625
4626 #define S_TP_TX_MODQ_WGHT7 24
4627 #define M_TP_TX_MODQ_WGHT7 0xff
4628 #define V_TP_TX_MODQ_WGHT7(x) ((x) << S_TP_TX_MODQ_WGHT7)
4629 #define G_TP_TX_MODQ_WGHT7(x) (((x) >> S_TP_TX_MODQ_WGHT7) & M_TP_TX_MODQ_WGHT7)
4630
4631 #define S_TP_TX_MODQ_WGHT6 16
4632 #define M_TP_TX_MODQ_WGHT6 0xff
4633 #define V_TP_TX_MODQ_WGHT6(x) ((x) << S_TP_TX_MODQ_WGHT6)
4634 #define G_TP_TX_MODQ_WGHT6(x) (((x) >> S_TP_TX_MODQ_WGHT6) & M_TP_TX_MODQ_WGHT6)
4635
4636 #define S_TP_TX_MODQ_WGHT5 8
4637 #define M_TP_TX_MODQ_WGHT5 0xff
4638 #define V_TP_TX_MODQ_WGHT5(x) ((x) << S_TP_TX_MODQ_WGHT5)
4639 #define G_TP_TX_MODQ_WGHT5(x) (((x) >> S_TP_TX_MODQ_WGHT5) & M_TP_TX_MODQ_WGHT5)
4640
4641 #define S_TP_TX_MODQ_WGHT4 0
4642 #define M_TP_TX_MODQ_WGHT4 0xff
4643 #define V_TP_TX_MODQ_WGHT4(x) ((x) << S_TP_TX_MODQ_WGHT4)
4644 #define G_TP_TX_MODQ_WGHT4(x) (((x) >> S_TP_TX_MODQ_WGHT4) & M_TP_TX_MODQ_WGHT4)
4645
4646 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430
4647
4648 #define S_TP_TX_MODQ_WGHT3 24
4649 #define M_TP_TX_MODQ_WGHT3 0xff
4650 #define V_TP_TX_MODQ_WGHT3(x) ((x) << S_TP_TX_MODQ_WGHT3)
4651 #define G_TP_TX_MODQ_WGHT3(x) (((x) >> S_TP_TX_MODQ_WGHT3) & M_TP_TX_MODQ_WGHT3)
4652
4653 #define S_TP_TX_MODQ_WGHT2 16
4654 #define M_TP_TX_MODQ_WGHT2 0xff
4655 #define V_TP_TX_MODQ_WGHT2(x) ((x) << S_TP_TX_MODQ_WGHT2)
4656 #define G_TP_TX_MODQ_WGHT2(x) (((x) >> S_TP_TX_MODQ_WGHT2) & M_TP_TX_MODQ_WGHT2)
4657
4658 #define S_TP_TX_MODQ_WGHT1 8
4659 #define M_TP_TX_MODQ_WGHT1 0xff
4660 #define V_TP_TX_MODQ_WGHT1(x) ((x) << S_TP_TX_MODQ_WGHT1)
4661 #define G_TP_TX_MODQ_WGHT1(x) (((x) >> S_TP_TX_MODQ_WGHT1) & M_TP_TX_MODQ_WGHT1)
4662
4663 #define S_TP_TX_MODQ_WGHT0 0
4664 #define M_TP_TX_MODQ_WGHT0 0xff
4665 #define V_TP_TX_MODQ_WGHT0(x) ((x) << S_TP_TX_MODQ_WGHT0)
4666 #define G_TP_TX_MODQ_WGHT0(x) (((x) >> S_TP_TX_MODQ_WGHT0) & M_TP_TX_MODQ_WGHT0)
4667
4668 #define A_TP_MOD_CHANNEL_WEIGHT 0x434
4669
4670 #define S_RX_MOD_CHANNEL_WEIGHT1 24
4671 #define M_RX_MOD_CHANNEL_WEIGHT1 0xff
4672 #define V_RX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT1)
4673 #define G_RX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT1) & M_RX_MOD_CHANNEL_WEIGHT1)
4674
4675 #define S_RX_MOD_CHANNEL_WEIGHT0 16
4676 #define M_RX_MOD_CHANNEL_WEIGHT0 0xff
4677 #define V_RX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT0)
4678 #define G_RX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT0) & M_RX_MOD_CHANNEL_WEIGHT0)
4679
4680 #define S_TX_MOD_CHANNEL_WEIGHT1 8
4681 #define M_TX_MOD_CHANNEL_WEIGHT1 0xff
4682 #define V_TX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT1)
4683 #define G_TX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT1) & M_TX_MOD_CHANNEL_WEIGHT1)
4684
4685 #define S_TX_MOD_CHANNEL_WEIGHT0 0
4686 #define M_TX_MOD_CHANNEL_WEIGHT0 0xff
4687 #define V_TX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT0)
4688 #define G_TX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT0) & M_TX_MOD_CHANNEL_WEIGHT0)
4689
4690 #define A_TP_MOD_RATE_LIMIT 0x438
4691
4692 #define S_RX_MOD_RATE_LIMIT_INC 24
4693 #define M_RX_MOD_RATE_LIMIT_INC 0xff
4694 #define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC)
4695 #define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC)
4696
4697 #define S_RX_MOD_RATE_LIMIT_TICK 16
4698 #define M_RX_MOD_RATE_LIMIT_TICK 0xff
4699 #define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK)
4700 #define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK)
4701
4702 #define S_TX_MOD_RATE_LIMIT_INC 8
4703 #define M_TX_MOD_RATE_LIMIT_INC 0xff
4704 #define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC)
4705 #define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC)
4706
4707 #define S_TX_MOD_RATE_LIMIT_TICK 0
4708 #define M_TX_MOD_RATE_LIMIT_TICK 0xff
4709 #define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK)
4710 #define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK)
4711
4712 #define A_TP_PIO_ADDR 0x440
4713 #define A_TP_PIO_DATA 0x444
4714 #define A_TP_RESET 0x44c
4715
4716 #define S_FLSTINITENABLE 1
4717 #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
4718 #define F_FLSTINITENABLE V_FLSTINITENABLE(1U)
4719
4720 #define S_TPRESET 0
4721 #define V_TPRESET(x) ((x) << S_TPRESET)
4722 #define F_TPRESET V_TPRESET(1U)
4723
4724 #define A_TP_MIB_INDEX 0x450
4725 #define A_TP_MIB_RDATA 0x454
4726 #define A_TP_SYNC_TIME_HI 0x458
4727 #define A_TP_SYNC_TIME_LO 0x45c
4728 #define A_TP_CMM_MM_RX_FLST_BASE 0x460
4729
4730 #define S_CMRXFLSTBASE 0
4731 #define M_CMRXFLSTBASE 0xfffffff
4732 #define V_CMRXFLSTBASE(x) ((x) << S_CMRXFLSTBASE)
4733 #define G_CMRXFLSTBASE(x) (((x) >> S_CMRXFLSTBASE) & M_CMRXFLSTBASE)
4734
4735 #define A_TP_CMM_MM_TX_FLST_BASE 0x464
4736
4737 #define S_CMTXFLSTBASE 0
4738 #define M_CMTXFLSTBASE 0xfffffff
4739 #define V_CMTXFLSTBASE(x) ((x) << S_CMTXFLSTBASE)
4740 #define G_CMTXFLSTBASE(x) (((x) >> S_CMTXFLSTBASE) & M_CMTXFLSTBASE)
4741
4742 #define A_TP_CMM_MM_PS_FLST_BASE 0x468
4743
4744 #define S_CMPSFLSTBASE 0
4745 #define M_CMPSFLSTBASE 0xfffffff
4746 #define V_CMPSFLSTBASE(x) ((x) << S_CMPSFLSTBASE)
4747 #define G_CMPSFLSTBASE(x) (((x) >> S_CMPSFLSTBASE) & M_CMPSFLSTBASE)
4748
4749 #define A_TP_CMM_MM_MAX_PSTRUCT 0x46c
4750
4751 #define S_CMMAXPSTRUCT 0
4752 #define M_CMMAXPSTRUCT 0x1fffff
4753 #define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT)
4754 #define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT)
4755
4756 #define A_TP_INT_ENABLE 0x470
4757
4758 #define S_FLMTXFLSTEMPTY 30
4759 #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
4760 #define F_FLMTXFLSTEMPTY V_FLMTXFLSTEMPTY(1U)
4761
4762 #define S_FLMRXFLSTEMPTY 29
4763 #define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY)
4764 #define F_FLMRXFLSTEMPTY V_FLMRXFLSTEMPTY(1U)
4765
4766 #define S_FLMPERRSET 28
4767 #define V_FLMPERRSET(x) ((x) << S_FLMPERRSET)
4768 #define F_FLMPERRSET V_FLMPERRSET(1U)
4769
4770 #define S_PROTOCOLSRAMPERR 27
4771 #define V_PROTOCOLSRAMPERR(x) ((x) << S_PROTOCOLSRAMPERR)
4772 #define F_PROTOCOLSRAMPERR V_PROTOCOLSRAMPERR(1U)
4773
4774 #define S_ARPLUTPERR 26
4775 #define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)
4776 #define F_ARPLUTPERR V_ARPLUTPERR(1U)
4777
4778 #define S_CMRCFOPPERR 25
4779 #define V_CMRCFOPPERR(x) ((x) << S_CMRCFOPPERR)
4780 #define F_CMRCFOPPERR V_CMRCFOPPERR(1U)
4781
4782 #define S_CMCACHEPERR 24
4783 #define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)
4784 #define F_CMCACHEPERR V_CMCACHEPERR(1U)
4785
4786 #define S_CMRCFDATAPERR 23
4787 #define V_CMRCFDATAPERR(x) ((x) << S_CMRCFDATAPERR)
4788 #define F_CMRCFDATAPERR V_CMRCFDATAPERR(1U)
4789
4790 #define S_DBL2TLUTPERR 22
4791 #define V_DBL2TLUTPERR(x) ((x) << S_DBL2TLUTPERR)
4792 #define F_DBL2TLUTPERR V_DBL2TLUTPERR(1U)
4793
4794 #define S_DBTXTIDPERR 21
4795 #define V_DBTXTIDPERR(x) ((x) << S_DBTXTIDPERR)
4796 #define F_DBTXTIDPERR V_DBTXTIDPERR(1U)
4797
4798 #define S_DBEXTPERR 20
4799 #define V_DBEXTPERR(x) ((x) << S_DBEXTPERR)
4800 #define F_DBEXTPERR V_DBEXTPERR(1U)
4801
4802 #define S_DBOPPERR 19
4803 #define V_DBOPPERR(x) ((x) << S_DBOPPERR)
4804 #define F_DBOPPERR V_DBOPPERR(1U)
4805
4806 #define S_TMCACHEPERR 18
4807 #define V_TMCACHEPERR(x) ((x) << S_TMCACHEPERR)
4808 #define F_TMCACHEPERR V_TMCACHEPERR(1U)
4809
4810 #define S_ETPOUTCPLFIFOPERR 17
4811 #define V_ETPOUTCPLFIFOPERR(x) ((x) << S_ETPOUTCPLFIFOPERR)
4812 #define F_ETPOUTCPLFIFOPERR V_ETPOUTCPLFIFOPERR(1U)
4813
4814 #define S_ETPOUTTCPFIFOPERR 16
4815 #define V_ETPOUTTCPFIFOPERR(x) ((x) << S_ETPOUTTCPFIFOPERR)
4816 #define F_ETPOUTTCPFIFOPERR V_ETPOUTTCPFIFOPERR(1U)
4817
4818 #define S_ETPOUTIPFIFOPERR 15
4819 #define V_ETPOUTIPFIFOPERR(x) ((x) << S_ETPOUTIPFIFOPERR)
4820 #define F_ETPOUTIPFIFOPERR V_ETPOUTIPFIFOPERR(1U)
4821
4822 #define S_ETPOUTETHFIFOPERR 14
4823 #define V_ETPOUTETHFIFOPERR(x) ((x) << S_ETPOUTETHFIFOPERR)
4824 #define F_ETPOUTETHFIFOPERR V_ETPOUTETHFIFOPERR(1U)
4825
4826 #define S_ETPINCPLFIFOPERR 13
4827 #define V_ETPINCPLFIFOPERR(x) ((x) << S_ETPINCPLFIFOPERR)
4828 #define F_ETPINCPLFIFOPERR V_ETPINCPLFIFOPERR(1U)
4829
4830 #define S_ETPINTCPOPTFIFOPERR 12
4831 #define V_ETPINTCPOPTFIFOPERR(x) ((x) << S_ETPINTCPOPTFIFOPERR)
4832 #define F_ETPINTCPOPTFIFOPERR V_ETPINTCPOPTFIFOPERR(1U)
4833
4834 #define S_ETPINTCPFIFOPERR 11
4835 #define V_ETPINTCPFIFOPERR(x) ((x) << S_ETPINTCPFIFOPERR)
4836 #define F_ETPINTCPFIFOPERR V_ETPINTCPFIFOPERR(1U)
4837
4838 #define S_ETPINIPFIFOPERR 10
4839 #define V_ETPINIPFIFOPERR(x) ((x) << S_ETPINIPFIFOPERR)
4840 #define F_ETPINIPFIFOPERR V_ETPINIPFIFOPERR(1U)
4841
4842 #define S_ETPINETHFIFOPERR 9
4843 #define V_ETPINETHFIFOPERR(x) ((x) << S_ETPINETHFIFOPERR)
4844 #define F_ETPINETHFIFOPERR V_ETPINETHFIFOPERR(1U)
4845
4846 #define S_CTPOUTCPLFIFOPERR 8
4847 #define V_CTPOUTCPLFIFOPERR(x) ((x) << S_CTPOUTCPLFIFOPERR)
4848 #define F_CTPOUTCPLFIFOPERR V_CTPOUTCPLFIFOPERR(1U)
4849
4850 #define S_CTPOUTTCPFIFOPERR 7
4851 #define V_CTPOUTTCPFIFOPERR(x) ((x) << S_CTPOUTTCPFIFOPERR)
4852 #define F_CTPOUTTCPFIFOPERR V_CTPOUTTCPFIFOPERR(1U)
4853
4854 #define S_CTPOUTIPFIFOPERR 6
4855 #define V_CTPOUTIPFIFOPERR(x) ((x) << S_CTPOUTIPFIFOPERR)
4856 #define F_CTPOUTIPFIFOPERR V_CTPOUTIPFIFOPERR(1U)
4857
4858 #define S_CTPOUTETHFIFOPERR 5
4859 #define V_CTPOUTETHFIFOPERR(x) ((x) << S_CTPOUTETHFIFOPERR)
4860 #define F_CTPOUTETHFIFOPERR V_CTPOUTETHFIFOPERR(1U)
4861
4862 #define S_CTPINCPLFIFOPERR 4
4863 #define V_CTPINCPLFIFOPERR(x) ((x) << S_CTPINCPLFIFOPERR)
4864 #define F_CTPINCPLFIFOPERR V_CTPINCPLFIFOPERR(1U)
4865
4866 #define S_CTPINTCPOPFIFOPERR 3
4867 #define V_CTPINTCPOPFIFOPERR(x) ((x) << S_CTPINTCPOPFIFOPERR)
4868 #define F_CTPINTCPOPFIFOPERR V_CTPINTCPOPFIFOPERR(1U)
4869
4870 #define S_CTPINTCPFIFOPERR 2
4871 #define V_CTPINTCPFIFOPERR(x) ((x) << S_CTPINTCPFIFOPERR)
4872 #define F_CTPINTCPFIFOPERR V_CTPINTCPFIFOPERR(1U)
4873
4874 #define S_CTPINIPFIFOPERR 1
4875 #define V_CTPINIPFIFOPERR(x) ((x) << S_CTPINIPFIFOPERR)
4876 #define F_CTPINIPFIFOPERR V_CTPINIPFIFOPERR(1U)
4877
4878 #define S_CTPINETHFIFOPERR 0
4879 #define V_CTPINETHFIFOPERR(x) ((x) << S_CTPINETHFIFOPERR)
4880 #define F_CTPINETHFIFOPERR V_CTPINETHFIFOPERR(1U)
4881
4882 #define A_TP_INT_CAUSE 0x474
4883 #define A_TP_FLM_FREE_PS_CNT 0x480
4884
4885 #define S_FREEPSTRUCTCOUNT 0
4886 #define M_FREEPSTRUCTCOUNT 0x1fffff
4887 #define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT)
4888 #define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT)
4889
4890 #define A_TP_FLM_FREE_RX_CNT 0x484
4891
4892 #define S_FREERXPAGECOUNT 0
4893 #define M_FREERXPAGECOUNT 0x1fffff
4894 #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
4895 #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
4896
4897 #define A_TP_FLM_FREE_TX_CNT 0x488
4898
4899 #define S_FREETXPAGECOUNT 0
4900 #define M_FREETXPAGECOUNT 0x1fffff
4901 #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
4902 #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
4903
4904 #define A_TP_TM_HEAP_PUSH_CNT 0x48c
4905 #define A_TP_TM_HEAP_POP_CNT 0x490
4906 #define A_TP_TM_DACK_PUSH_CNT 0x494
4907 #define A_TP_TM_DACK_POP_CNT 0x498
4908 #define A_TP_TM_MOD_PUSH_CNT 0x49c
4909 #define A_TP_MOD_POP_CNT 0x4a0
4910 #define A_TP_TIMER_SEPARATOR 0x4a4
4911 #define A_TP_DEBUG_SEL 0x4a8
4912 #define A_TP_DEBUG_FLAGS 0x4ac
4913
4914 #define S_RXTIMERDACKFIRST 26
4915 #define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST)
4916 #define F_RXTIMERDACKFIRST V_RXTIMERDACKFIRST(1U)
4917
4918 #define S_RXTIMERDACK 25
4919 #define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK)
4920 #define F_RXTIMERDACK V_RXTIMERDACK(1U)
4921
4922 #define S_RXTIMERHEARTBEAT 24
4923 #define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT)
4924 #define F_RXTIMERHEARTBEAT V_RXTIMERHEARTBEAT(1U)
4925
4926 #define S_RXPAWSDROP 23
4927 #define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP)
4928 #define F_RXPAWSDROP V_RXPAWSDROP(1U)
4929
4930 #define S_RXURGDATADROP 22
4931 #define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP)
4932 #define F_RXURGDATADROP V_RXURGDATADROP(1U)
4933
4934 #define S_RXFUTUREDATA 21
4935 #define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA)
4936 #define F_RXFUTUREDATA V_RXFUTUREDATA(1U)
4937
4938 #define S_RXRCVRXMDATA 20
4939 #define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA)
4940 #define F_RXRCVRXMDATA V_RXRCVRXMDATA(1U)
4941
4942 #define S_RXRCVOOODATAFIN 19
4943 #define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN)
4944 #define F_RXRCVOOODATAFIN V_RXRCVOOODATAFIN(1U)
4945
4946 #define S_RXRCVOOODATA 18
4947 #define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA)
4948 #define F_RXRCVOOODATA V_RXRCVOOODATA(1U)
4949
4950 #define S_RXRCVWNDZERO 17
4951 #define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO)
4952 #define F_RXRCVWNDZERO V_RXRCVWNDZERO(1U)
4953
4954 #define S_RXRCVWNDLTMSS 16
4955 #define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS)
4956 #define F_RXRCVWNDLTMSS V_RXRCVWNDLTMSS(1U)
4957
4958 #define S_TXDUPACKINC 11
4959 #define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC)
4960 #define F_TXDUPACKINC V_TXDUPACKINC(1U)
4961
4962 #define S_TXRXMURG 10
4963 #define V_TXRXMURG(x) ((x) << S_TXRXMURG)
4964 #define F_TXRXMURG V_TXRXMURG(1U)
4965
4966 #define S_TXRXMFIN 9
4967 #define V_TXRXMFIN(x) ((x) << S_TXRXMFIN)
4968 #define F_TXRXMFIN V_TXRXMFIN(1U)
4969
4970 #define S_TXRXMSYN 8
4971 #define V_TXRXMSYN(x) ((x) << S_TXRXMSYN)
4972 #define F_TXRXMSYN V_TXRXMSYN(1U)
4973
4974 #define S_TXRXMNEWRENO 7
4975 #define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO)
4976 #define F_TXRXMNEWRENO V_TXRXMNEWRENO(1U)
4977
4978 #define S_TXRXMFAST 6
4979 #define V_TXRXMFAST(x) ((x) << S_TXRXMFAST)
4980 #define F_TXRXMFAST V_TXRXMFAST(1U)
4981
4982 #define S_TXRXMTIMER 5
4983 #define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER)
4984 #define F_TXRXMTIMER V_TXRXMTIMER(1U)
4985
4986 #define S_TXRXMTIMERKEEPALIVE 4
4987 #define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE)
4988 #define F_TXRXMTIMERKEEPALIVE V_TXRXMTIMERKEEPALIVE(1U)
4989
4990 #define S_TXRXMTIMERPERSIST 3
4991 #define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST)
4992 #define F_TXRXMTIMERPERSIST V_TXRXMTIMERPERSIST(1U)
4993
4994 #define S_TXRCVADVSHRUNK 2
4995 #define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK)
4996 #define F_TXRCVADVSHRUNK V_TXRCVADVSHRUNK(1U)
4997
4998 #define S_TXRCVADVZERO 1
4999 #define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO)
5000 #define F_TXRCVADVZERO V_TXRCVADVZERO(1U)
5001
5002 #define S_TXRCVADVLTMSS 0
5003 #define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS)
5004 #define F_TXRCVADVLTMSS V_TXRCVADVLTMSS(1U)
5005
5006 #define S_RXDEBUGFLAGS 16
5007 #define M_RXDEBUGFLAGS 0xffff
5008 #define V_RXDEBUGFLAGS(x) ((x) << S_RXDEBUGFLAGS)
5009 #define G_RXDEBUGFLAGS(x) (((x) >> S_RXDEBUGFLAGS) & M_RXDEBUGFLAGS)
5010
5011 #define S_TXDEBUGFLAGS 0
5012 #define M_TXDEBUGFLAGS 0xffff
5013 #define V_TXDEBUGFLAGS(x) ((x) << S_TXDEBUGFLAGS)
5014 #define G_TXDEBUGFLAGS(x) (((x) >> S_TXDEBUGFLAGS) & M_TXDEBUGFLAGS)
5015
5016 #define A_TP_PROXY_FLOW_CNTL 0x4b0
5017 #define A_TP_CM_FLOW_CNTL_MODE 0x4b0
5018
5019 #define S_CMFLOWCACHEDISABLE 0
5020 #define V_CMFLOWCACHEDISABLE(x) ((x) << S_CMFLOWCACHEDISABLE)
5021 #define F_CMFLOWCACHEDISABLE V_CMFLOWCACHEDISABLE(1U)
5022
5023 #define A_TP_PC_CONGESTION_CNTL 0x4b4
5024
5025 #define S_EDROPTUNNEL 19
5026 #define V_EDROPTUNNEL(x) ((x) << S_EDROPTUNNEL)
5027 #define F_EDROPTUNNEL V_EDROPTUNNEL(1U)
5028
5029 #define S_CDROPTUNNEL 18
5030 #define V_CDROPTUNNEL(x) ((x) << S_CDROPTUNNEL)
5031 #define F_CDROPTUNNEL V_CDROPTUNNEL(1U)
5032
5033 #define S_ETHRESHOLD 12
5034 #define M_ETHRESHOLD 0x3f
5035 #define V_ETHRESHOLD(x) ((x) << S_ETHRESHOLD)
5036 #define G_ETHRESHOLD(x) (((x) >> S_ETHRESHOLD) & M_ETHRESHOLD)
5037
5038 #define S_CTHRESHOLD 6
5039 #define M_CTHRESHOLD 0x3f
5040 #define V_CTHRESHOLD(x) ((x) << S_CTHRESHOLD)
5041 #define G_CTHRESHOLD(x) (((x) >> S_CTHRESHOLD) & M_CTHRESHOLD)
5042
5043 #define S_TXTHRESHOLD 0
5044 #define M_TXTHRESHOLD 0x3f
5045 #define V_TXTHRESHOLD(x) ((x) << S_TXTHRESHOLD)
5046 #define G_TXTHRESHOLD(x) (((x) >> S_TXTHRESHOLD) & M_TXTHRESHOLD)
5047
5048 #define A_TP_TX_DROP_COUNT 0x4bc
5049 #define A_TP_CLEAR_DEBUG 0x4c0
5050
5051 #define S_CLRDEBUG 0
5052 #define V_CLRDEBUG(x) ((x) << S_CLRDEBUG)
5053 #define F_CLRDEBUG V_CLRDEBUG(1U)
5054
5055 #define A_TP_DEBUG_VEC 0x4c4
5056 #define A_TP_DEBUG_VEC2 0x4c8
5057 #define A_TP_DEBUG_REG_SEL 0x4cc
5058 #define A_TP_DEBUG 0x4d0
5059 #define A_TP_DBG_LA_CONFIG 0x4d4
5060 #define A_TP_DBG_LA_DATAH 0x4d8
5061 #define A_TP_DBG_LA_DATAL 0x4dc
5062 #define A_TP_EMBED_OP_FIELD0 0x4e8
5063 #define A_TP_EMBED_OP_FIELD1 0x4ec
5064 #define A_TP_EMBED_OP_FIELD2 0x4f0
5065 #define A_TP_EMBED_OP_FIELD3 0x4f4
5066 #define A_TP_EMBED_OP_FIELD4 0x4f8
5067 #define A_TP_EMBED_OP_FIELD5 0x4fc
5068 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
5069 #define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1
5070 #define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2
5071 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
5072 #define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4
5073 #define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5
5074 #define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6
5075 #define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7
5076 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
5077 #define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9
5078 #define A_TP_TX_TRC_KEY0 0x20
5079 #define A_TP_TX_TRC_MASK0 0x21
5080 #define A_TP_TX_TRC_KEY1 0x22
5081 #define A_TP_TX_TRC_MASK1 0x23
5082 #define A_TP_TX_TRC_KEY2 0x24
5083 #define A_TP_TX_TRC_MASK2 0x25
5084 #define A_TP_TX_TRC_KEY3 0x26
5085 #define A_TP_TX_TRC_MASK3 0x27
5086 #define A_TP_IPMI_CFG1 0x28
5087
5088 #define S_VLANENABLE 31
5089 #define V_VLANENABLE(x) ((x) << S_VLANENABLE)
5090 #define F_VLANENABLE V_VLANENABLE(1U)
5091
5092 #define S_PRIMARYPORTENABLE 30
5093 #define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE)
5094 #define F_PRIMARYPORTENABLE V_PRIMARYPORTENABLE(1U)
5095
5096 #define S_SECUREPORTENABLE 29
5097 #define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE)
5098 #define F_SECUREPORTENABLE V_SECUREPORTENABLE(1U)
5099
5100 #define S_ARPENABLE 28
5101 #define V_ARPENABLE(x) ((x) << S_ARPENABLE)
5102 #define F_ARPENABLE V_ARPENABLE(1U)
5103
5104 #define S_VLAN 0
5105 #define M_VLAN 0xffff
5106 #define V_VLAN(x) ((x) << S_VLAN)
5107 #define G_VLAN(x) (((x) >> S_VLAN) & M_VLAN)
5108
5109 #define A_TP_IPMI_CFG2 0x29
5110
5111 #define S_SECUREPORT 16
5112 #define M_SECUREPORT 0xffff
5113 #define V_SECUREPORT(x) ((x) << S_SECUREPORT)
5114 #define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT)
5115
5116 #define S_PRIMARYPORT 0
5117 #define M_PRIMARYPORT 0xffff
5118 #define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT)
5119 #define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT)
5120
5121 #define A_TP_RX_TRC_KEY0 0x120
5122 #define A_TP_RX_TRC_MASK0 0x121
5123 #define A_TP_RX_TRC_KEY1 0x122
5124 #define A_TP_RX_TRC_MASK1 0x123
5125 #define A_TP_RX_TRC_KEY2 0x124
5126 #define A_TP_RX_TRC_MASK2 0x125
5127 #define A_TP_RX_TRC_KEY3 0x126
5128 #define A_TP_RX_TRC_MASK3 0x127
5129 #define A_TP_QOS_RX_TOS_MAP_H 0x128
5130 #define A_TP_QOS_RX_TOS_MAP_L 0x129
5131 #define A_TP_QOS_RX_MAP_MODE 0x12a
5132
5133 #define S_DEFAULTCH 11
5134 #define V_DEFAULTCH(x) ((x) << S_DEFAULTCH)
5135 #define F_DEFAULTCH V_DEFAULTCH(1U)
5136
5137 #define S_RXMAPMODE 8
5138 #define M_RXMAPMODE 0x7
5139 #define V_RXMAPMODE(x) ((x) << S_RXMAPMODE)
5140 #define G_RXMAPMODE(x) (((x) >> S_RXMAPMODE) & M_RXMAPMODE)
5141
5142 #define S_RXVLANMAP 7
5143 #define V_RXVLANMAP(x) ((x) << S_RXVLANMAP)
5144 #define F_RXVLANMAP V_RXVLANMAP(1U)
5145
5146 #define A_TP_TX_DROP_CFG_CH0 0x12b
5147
5148 #define S_TIMERENABLED 31
5149 #define V_TIMERENABLED(x) ((x) << S_TIMERENABLED)
5150 #define F_TIMERENABLED V_TIMERENABLED(1U)
5151
5152 #define S_TIMERERRORENABLE 30
5153 #define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE)
5154 #define F_TIMERERRORENABLE V_TIMERERRORENABLE(1U)
5155
5156 #define S_TIMERTHRESHOLD 4
5157 #define M_TIMERTHRESHOLD 0x3ffffff
5158 #define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD)
5159 #define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD)
5160
5161 #define S_PACKETDROPS 0
5162 #define M_PACKETDROPS 0xf
5163 #define V_PACKETDROPS(x) ((x) << S_PACKETDROPS)
5164 #define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS)
5165
5166 #define A_TP_TX_DROP_CFG_CH1 0x12c
5167 #define A_TP_TX_DROP_CNT_CH0 0x12d
5168
5169 #define S_TXDROPCNTCH0SENT 16
5170 #define M_TXDROPCNTCH0SENT 0xffff
5171 #define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT)
5172 #define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT)
5173
5174 #define S_TXDROPCNTCH0RCVD 0
5175 #define M_TXDROPCNTCH0RCVD 0xffff
5176 #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
5177 #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD)
5178
5179 #define A_TP_TX_DROP_CNT_CH1 0x12e
5180
5181 #define S_TXDROPCNTCH1SENT 16
5182 #define M_TXDROPCNTCH1SENT 0xffff
5183 #define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT)
5184 #define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT)
5185
5186 #define S_TXDROPCNTCH1RCVD 0
5187 #define M_TXDROPCNTCH1RCVD 0xffff
5188 #define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD)
5189 #define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD)
5190
5191 #define A_TP_TX_DROP_MODE 0x12f
5192
5193 #define S_TXDROPMODECH1 1
5194 #define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1)
5195 #define F_TXDROPMODECH1 V_TXDROPMODECH1(1U)
5196
5197 #define S_TXDROPMODECH0 0
5198 #define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0)
5199 #define F_TXDROPMODECH0 V_TXDROPMODECH0(1U)
5200
5201 #define A_TP_VLAN_PRI_MAP 0x137
5202
5203 #define S_VLANPRIMAP7 14
5204 #define M_VLANPRIMAP7 0x3
5205 #define V_VLANPRIMAP7(x) ((x) << S_VLANPRIMAP7)
5206 #define G_VLANPRIMAP7(x) (((x) >> S_VLANPRIMAP7) & M_VLANPRIMAP7)
5207
5208 #define S_VLANPRIMAP6 12
5209 #define M_VLANPRIMAP6 0x3
5210 #define V_VLANPRIMAP6(x) ((x) << S_VLANPRIMAP6)
5211 #define G_VLANPRIMAP6(x) (((x) >> S_VLANPRIMAP6) & M_VLANPRIMAP6)
5212
5213 #define S_VLANPRIMAP5 10
5214 #define M_VLANPRIMAP5 0x3
5215 #define V_VLANPRIMAP5(x) ((x) << S_VLANPRIMAP5)
5216 #define G_VLANPRIMAP5(x) (((x) >> S_VLANPRIMAP5) & M_VLANPRIMAP5)
5217
5218 #define S_VLANPRIMAP4 8
5219 #define M_VLANPRIMAP4 0x3
5220 #define V_VLANPRIMAP4(x) ((x) << S_VLANPRIMAP4)
5221 #define G_VLANPRIMAP4(x) (((x) >> S_VLANPRIMAP4) & M_VLANPRIMAP4)
5222
5223 #define S_VLANPRIMAP3 6
5224 #define M_VLANPRIMAP3 0x3
5225 #define V_VLANPRIMAP3(x) ((x) << S_VLANPRIMAP3)
5226 #define G_VLANPRIMAP3(x) (((x) >> S_VLANPRIMAP3) & M_VLANPRIMAP3)
5227
5228 #define S_VLANPRIMAP2 4
5229 #define M_VLANPRIMAP2 0x3
5230 #define V_VLANPRIMAP2(x) ((x) << S_VLANPRIMAP2)
5231 #define G_VLANPRIMAP2(x) (((x) >> S_VLANPRIMAP2) & M_VLANPRIMAP2)
5232
5233 #define S_VLANPRIMAP1 2
5234 #define M_VLANPRIMAP1 0x3
5235 #define V_VLANPRIMAP1(x) ((x) << S_VLANPRIMAP1)
5236 #define G_VLANPRIMAP1(x) (((x) >> S_VLANPRIMAP1) & M_VLANPRIMAP1)
5237
5238 #define S_VLANPRIMAP0 0
5239 #define M_VLANPRIMAP0 0x3
5240 #define V_VLANPRIMAP0(x) ((x) << S_VLANPRIMAP0)
5241 #define G_VLANPRIMAP0(x) (((x) >> S_VLANPRIMAP0) & M_VLANPRIMAP0)
5242
5243 #define A_TP_MAC_MATCH_MAP0 0x138
5244
5245 #define S_MACMATCHMAP7 21
5246 #define M_MACMATCHMAP7 0x7
5247 #define V_MACMATCHMAP7(x) ((x) << S_MACMATCHMAP7)
5248 #define G_MACMATCHMAP7(x) (((x) >> S_MACMATCHMAP7) & M_MACMATCHMAP7)
5249
5250 #define S_MACMATCHMAP6 18
5251 #define M_MACMATCHMAP6 0x7
5252 #define V_MACMATCHMAP6(x) ((x) << S_MACMATCHMAP6)
5253 #define G_MACMATCHMAP6(x) (((x) >> S_MACMATCHMAP6) & M_MACMATCHMAP6)
5254
5255 #define S_MACMATCHMAP5 15
5256 #define M_MACMATCHMAP5 0x7
5257 #define V_MACMATCHMAP5(x) ((x) << S_MACMATCHMAP5)
5258 #define G_MACMATCHMAP5(x) (((x) >> S_MACMATCHMAP5) & M_MACMATCHMAP5)
5259
5260 #define S_MACMATCHMAP4 12
5261 #define M_MACMATCHMAP4 0x7
5262 #define V_MACMATCHMAP4(x) ((x) << S_MACMATCHMAP4)
5263 #define G_MACMATCHMAP4(x) (((x) >> S_MACMATCHMAP4) & M_MACMATCHMAP4)
5264
5265 #define S_MACMATCHMAP3 9
5266 #define M_MACMATCHMAP3 0x7
5267 #define V_MACMATCHMAP3(x) ((x) << S_MACMATCHMAP3)
5268 #define G_MACMATCHMAP3(x) (((x) >> S_MACMATCHMAP3) & M_MACMATCHMAP3)
5269
5270 #define S_MACMATCHMAP2 6
5271 #define M_MACMATCHMAP2 0x7
5272 #define V_MACMATCHMAP2(x) ((x) << S_MACMATCHMAP2)
5273 #define G_MACMATCHMAP2(x) (((x) >> S_MACMATCHMAP2) & M_MACMATCHMAP2)
5274
5275 #define S_MACMATCHMAP1 3
5276 #define M_MACMATCHMAP1 0x7
5277 #define V_MACMATCHMAP1(x) ((x) << S_MACMATCHMAP1)
5278 #define G_MACMATCHMAP1(x) (((x) >> S_MACMATCHMAP1) & M_MACMATCHMAP1)
5279
5280 #define S_MACMATCHMAP0 0
5281 #define M_MACMATCHMAP0 0x7
5282 #define V_MACMATCHMAP0(x) ((x) << S_MACMATCHMAP0)
5283 #define G_MACMATCHMAP0(x) (((x) >> S_MACMATCHMAP0) & M_MACMATCHMAP0)
5284
5285 #define A_TP_MAC_MATCH_MAP1 0x139
5286 #define A_TP_INGRESS_CONFIG 0x141
5287
5288 #define S_LOOKUPEVERYPKT 28
5289 #define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT)
5290 #define F_LOOKUPEVERYPKT V_LOOKUPEVERYPKT(1U)
5291
5292 #define S_ENABLEINSERTIONSFD 27
5293 #define V_ENABLEINSERTIONSFD(x) ((x) << S_ENABLEINSERTIONSFD)
5294 #define F_ENABLEINSERTIONSFD V_ENABLEINSERTIONSFD(1U)
5295
5296 #define S_ENABLEINSERTION 26
5297 #define V_ENABLEINSERTION(x) ((x) << S_ENABLEINSERTION)
5298 #define F_ENABLEINSERTION V_ENABLEINSERTION(1U)
5299
5300 #define S_ENABLEEXTRACTIONSFD 25
5301 #define V_ENABLEEXTRACTIONSFD(x) ((x) << S_ENABLEEXTRACTIONSFD)
5302 #define F_ENABLEEXTRACTIONSFD V_ENABLEEXTRACTIONSFD(1U)
5303
5304 #define S_ENABLEEXTRACT 24
5305 #define V_ENABLEEXTRACT(x) ((x) << S_ENABLEEXTRACT)
5306 #define F_ENABLEEXTRACT V_ENABLEEXTRACT(1U)
5307
5308 #define S_BITPOS3 18
5309 #define M_BITPOS3 0x3f
5310 #define V_BITPOS3(x) ((x) << S_BITPOS3)
5311 #define G_BITPOS3(x) (((x) >> S_BITPOS3) & M_BITPOS3)
5312
5313 #define S_BITPOS2 12
5314 #define M_BITPOS2 0x3f
5315 #define V_BITPOS2(x) ((x) << S_BITPOS2)
5316 #define G_BITPOS2(x) (((x) >> S_BITPOS2) & M_BITPOS2)
5317
5318 #define S_BITPOS1 6
5319 #define M_BITPOS1 0x3f
5320 #define V_BITPOS1(x) ((x) << S_BITPOS1)
5321 #define G_BITPOS1(x) (((x) >> S_BITPOS1) & M_BITPOS1)
5322
5323 #define S_BITPOS0 0
5324 #define M_BITPOS0 0x3f
5325 #define V_BITPOS0(x) ((x) << S_BITPOS0)
5326 #define G_BITPOS0(x) (((x) >> S_BITPOS0) & M_BITPOS0)
5327
5328 #define A_TP_PREAMBLE_MSB 0x142
5329 #define A_TP_PREAMBLE_LSB 0x143
5330 #define A_TP_EGRESS_CONFIG 0x145
5331
5332 #define S_REWRITEFORCETOSIZE 0
5333 #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
5334 #define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U)
5335
5336 #define A_TP_INTF_FROM_TX_PKT 0x244
5337
5338 #define S_INTFFROMTXPKT 0
5339 #define V_INTFFROMTXPKT(x) ((x) << S_INTFFROMTXPKT)
5340 #define F_INTFFROMTXPKT V_INTFFROMTXPKT(1U)
5341
5342 #define A_TP_FIFO_CONFIG 0x8c0
5343
5344 #define S_RXFIFOCONFIG 10
5345 #define M_RXFIFOCONFIG 0x3f
5346 #define V_RXFIFOCONFIG(x) ((x) << S_RXFIFOCONFIG)
5347 #define G_RXFIFOCONFIG(x) (((x) >> S_RXFIFOCONFIG) & M_RXFIFOCONFIG)
5348
5349 #define S_TXFIFOCONFIG 2
5350 #define M_TXFIFOCONFIG 0x3f
5351 #define V_TXFIFOCONFIG(x) ((x) << S_TXFIFOCONFIG)
5352 #define G_TXFIFOCONFIG(x) (((x) >> S_TXFIFOCONFIG) & M_TXFIFOCONFIG)
5353
5354 /* registers for module ULP2_RX */
5355 #define ULP2_RX_BASE_ADDR 0x500
5356
5357 #define A_ULPRX_CTL 0x500
5358
5359 #define S_PCMD1THRESHOLD 24
5360 #define M_PCMD1THRESHOLD 0xff
5361 #define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD)
5362 #define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD)
5363
5364 #define S_PCMD0THRESHOLD 16
5365 #define M_PCMD0THRESHOLD 0xff
5366 #define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD)
5367 #define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD)
5368
5369 #define S_ROUND_ROBIN 4
5370 #define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN)
5371 #define F_ROUND_ROBIN V_ROUND_ROBIN(1U)
5372
5373 #define S_RDMA_PERMISSIVE_MODE 3
5374 #define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE)
5375 #define F_RDMA_PERMISSIVE_MODE V_RDMA_PERMISSIVE_MODE(1U)
5376
5377 #define S_PAGEPODME 2
5378 #define V_PAGEPODME(x) ((x) << S_PAGEPODME)
5379 #define F_PAGEPODME V_PAGEPODME(1U)
5380
5381 #define S_ISCSITAGTCB 1
5382 #define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB)
5383 #define F_ISCSITAGTCB V_ISCSITAGTCB(1U)
5384
5385 #define S_TDDPTAGTCB 0
5386 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
5387 #define F_TDDPTAGTCB V_TDDPTAGTCB(1U)
5388
5389 #define A_ULPRX_INT_ENABLE 0x504
5390
5391 #define S_DATASELFRAMEERR0 7
5392 #define V_DATASELFRAMEERR0(x) ((x) << S_DATASELFRAMEERR0)
5393 #define F_DATASELFRAMEERR0 V_DATASELFRAMEERR0(1U)
5394
5395 #define S_DATASELFRAMEERR1 6
5396 #define V_DATASELFRAMEERR1(x) ((x) << S_DATASELFRAMEERR1)
5397 #define F_DATASELFRAMEERR1 V_DATASELFRAMEERR1(1U)
5398
5399 #define S_PCMDMUXPERR 5
5400 #define V_PCMDMUXPERR(x) ((x) << S_PCMDMUXPERR)
5401 #define F_PCMDMUXPERR V_PCMDMUXPERR(1U)
5402
5403 #define S_ARBFPERR 4
5404 #define V_ARBFPERR(x) ((x) << S_ARBFPERR)
5405 #define F_ARBFPERR V_ARBFPERR(1U)
5406
5407 #define S_ARBPF0PERR 3
5408 #define V_ARBPF0PERR(x) ((x) << S_ARBPF0PERR)
5409 #define F_ARBPF0PERR V_ARBPF0PERR(1U)
5410
5411 #define S_ARBPF1PERR 2
5412 #define V_ARBPF1PERR(x) ((x) << S_ARBPF1PERR)
5413 #define F_ARBPF1PERR V_ARBPF1PERR(1U)
5414
5415 #define S_PARERRPCMD 1
5416 #define V_PARERRPCMD(x) ((x) << S_PARERRPCMD)
5417 #define F_PARERRPCMD V_PARERRPCMD(1U)
5418
5419 #define S_PARERRDATA 0
5420 #define V_PARERRDATA(x) ((x) << S_PARERRDATA)
5421 #define F_PARERRDATA V_PARERRDATA(1U)
5422
5423 #define S_PARERR 0
5424 #define V_PARERR(x) ((x) << S_PARERR)
5425 #define F_PARERR V_PARERR(1U)
5426
5427 #define A_ULPRX_INT_CAUSE 0x508
5428 #define A_ULPRX_ISCSI_LLIMIT 0x50c
5429
5430 #define S_ISCSILLIMIT 6
5431 #define M_ISCSILLIMIT 0x3ffffff
5432 #define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT)
5433 #define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT)
5434
5435 #define A_ULPRX_ISCSI_ULIMIT 0x510
5436
5437 #define S_ISCSIULIMIT 6
5438 #define M_ISCSIULIMIT 0x3ffffff
5439 #define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT)
5440 #define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT)
5441
5442 #define A_ULPRX_ISCSI_TAGMASK 0x514
5443
5444 #define S_ISCSITAGMASK 6
5445 #define M_ISCSITAGMASK 0x3ffffff
5446 #define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK)
5447 #define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK)
5448
5449 #define A_ULPRX_ISCSI_PSZ 0x518
5450
5451 #define S_HPZ3 24
5452 #define M_HPZ3 0xf
5453 #define V_HPZ3(x) ((x) << S_HPZ3)
5454 #define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3)
5455
5456 #define S_HPZ2 16
5457 #define M_HPZ2 0xf
5458 #define V_HPZ2(x) ((x) << S_HPZ2)
5459 #define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2)
5460
5461 #define S_HPZ1 8
5462 #define M_HPZ1 0xf
5463 #define V_HPZ1(x) ((x) << S_HPZ1)
5464 #define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1)
5465
5466 #define S_HPZ0 0
5467 #define M_HPZ0 0xf
5468 #define V_HPZ0(x) ((x) << S_HPZ0)
5469 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
5470
5471 #define A_ULPRX_TDDP_LLIMIT 0x51c
5472
5473 #define S_TDDPLLIMIT 6
5474 #define M_TDDPLLIMIT 0x3ffffff
5475 #define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT)
5476 #define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT)
5477
5478 #define A_ULPRX_TDDP_ULIMIT 0x520
5479
5480 #define S_TDDPULIMIT 6
5481 #define M_TDDPULIMIT 0x3ffffff
5482 #define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT)
5483 #define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT)
5484
5485 #define A_ULPRX_TDDP_TAGMASK 0x524
5486
5487 #define S_TDDPTAGMASK 6
5488 #define M_TDDPTAGMASK 0x3ffffff
5489 #define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK)
5490 #define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK)
5491
5492 #define A_ULPRX_TDDP_PSZ 0x528
5493 #define A_ULPRX_STAG_LLIMIT 0x52c
5494 #define A_ULPRX_STAG_ULIMIT 0x530
5495 #define A_ULPRX_RQ_LLIMIT 0x534
5496 #define A_ULPRX_RQ_ULIMIT 0x538
5497 #define A_ULPRX_PBL_LLIMIT 0x53c
5498 #define A_ULPRX_PBL_ULIMIT 0x540
5499
5500 /* registers for module ULP2_TX */
5501 #define ULP2_TX_BASE_ADDR 0x580
5502
5503 #define A_ULPTX_CONFIG 0x580
5504
5505 #define S_CFG_CQE_SOP_MASK 1
5506 #define V_CFG_CQE_SOP_MASK(x) ((x) << S_CFG_CQE_SOP_MASK)
5507 #define F_CFG_CQE_SOP_MASK V_CFG_CQE_SOP_MASK(1U)
5508
5509 #define S_CFG_RR_ARB 0
5510 #define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB)
5511 #define F_CFG_RR_ARB V_CFG_RR_ARB(1U)
5512
5513 #define A_ULPTX_INT_ENABLE 0x584
5514
5515 #define S_CMD_FIFO_PERR_SET1 7
5516 #define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1)
5517 #define F_CMD_FIFO_PERR_SET1 V_CMD_FIFO_PERR_SET1(1U)
5518
5519 #define S_CMD_FIFO_PERR_SET0 6
5520 #define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0)
5521 #define F_CMD_FIFO_PERR_SET0 V_CMD_FIFO_PERR_SET0(1U)
5522
5523 #define S_LSO_HDR_SRAM_PERR_SET1 5
5524 #define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1)
5525 #define F_LSO_HDR_SRAM_PERR_SET1 V_LSO_HDR_SRAM_PERR_SET1(1U)
5526
5527 #define S_LSO_HDR_SRAM_PERR_SET0 4
5528 #define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0)
5529 #define F_LSO_HDR_SRAM_PERR_SET0 V_LSO_HDR_SRAM_PERR_SET0(1U)
5530
5531 #define S_IMM_DATA_PERR_SET_CH1 3
5532 #define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1)
5533 #define F_IMM_DATA_PERR_SET_CH1 V_IMM_DATA_PERR_SET_CH1(1U)
5534
5535 #define S_IMM_DATA_PERR_SET_CH0 2
5536 #define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0)
5537 #define F_IMM_DATA_PERR_SET_CH0 V_IMM_DATA_PERR_SET_CH0(1U)
5538
5539 #define S_PBL_BOUND_ERR_CH1 1
5540 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
5541 #define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U)
5542
5543 #define S_PBL_BOUND_ERR_CH0 0
5544 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
5545 #define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U)
5546
5547 #define A_ULPTX_INT_CAUSE 0x588
5548 #define A_ULPTX_TPT_LLIMIT 0x58c
5549 #define A_ULPTX_TPT_ULIMIT 0x590
5550 #define A_ULPTX_PBL_LLIMIT 0x594
5551 #define A_ULPTX_PBL_ULIMIT 0x598
5552 #define A_ULPTX_CPL_ERR_OFFSET 0x59c
5553 #define A_ULPTX_CPL_ERR_MASK 0x5a0
5554 #define A_ULPTX_CPL_ERR_VALUE 0x5a4
5555 #define A_ULPTX_CPL_PACK_SIZE 0x5a8
5556
5557 #define S_VALUE 24
5558 #define M_VALUE 0xff
5559 #define V_VALUE(x) ((x) << S_VALUE)
5560 #define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE)
5561
5562 #define S_CH1SIZE2 24
5563 #define M_CH1SIZE2 0xff
5564 #define V_CH1SIZE2(x) ((x) << S_CH1SIZE2)
5565 #define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2)
5566
5567 #define S_CH1SIZE1 16
5568 #define M_CH1SIZE1 0xff
5569 #define V_CH1SIZE1(x) ((x) << S_CH1SIZE1)
5570 #define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1)
5571
5572 #define S_CH0SIZE2 8
5573 #define M_CH0SIZE2 0xff
5574 #define V_CH0SIZE2(x) ((x) << S_CH0SIZE2)
5575 #define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2)
5576
5577 #define S_CH0SIZE1 0
5578 #define M_CH0SIZE1 0xff
5579 #define V_CH0SIZE1(x) ((x) << S_CH0SIZE1)
5580 #define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1)
5581
5582 #define A_ULPTX_DMA_WEIGHT 0x5ac
5583
5584 #define S_D1_WEIGHT 16
5585 #define M_D1_WEIGHT 0xffff
5586 #define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT)
5587 #define G_D1_WEIGHT(x) (((x) >> S_D1_WEIGHT) & M_D1_WEIGHT)
5588
5589 #define S_D0_WEIGHT 0
5590 #define M_D0_WEIGHT 0xffff
5591 #define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT)
5592 #define G_D0_WEIGHT(x) (((x) >> S_D0_WEIGHT) & M_D0_WEIGHT)
5593
5594 /* registers for module PM1_RX */
5595 #define PM1_RX_BASE_ADDR 0x5c0
5596
5597 #define A_PM1_RX_CFG 0x5c0
5598 #define A_PM1_RX_MODE 0x5c4
5599
5600 #define S_STAT_CHANNEL 1
5601 #define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL)
5602 #define F_STAT_CHANNEL V_STAT_CHANNEL(1U)
5603
5604 #define S_PRIORITY_CH 0
5605 #define V_PRIORITY_CH(x) ((x) << S_PRIORITY_CH)
5606 #define F_PRIORITY_CH V_PRIORITY_CH(1U)
5607
5608 #define A_PM1_RX_STAT_CONFIG 0x5c8
5609 #define A_PM1_RX_STAT_COUNT 0x5cc
5610 #define A_PM1_RX_STAT_MSB 0x5d0
5611 #define A_PM1_RX_STAT_LSB 0x5d4
5612 #define A_PM1_RX_INT_ENABLE 0x5d8
5613
5614 #define S_ZERO_E_CMD_ERROR 18
5615 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
5616 #define F_ZERO_E_CMD_ERROR V_ZERO_E_CMD_ERROR(1U)
5617
5618 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR 17
5619 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
5620 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
5621
5622 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR 16
5623 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
5624 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
5625
5626 #define S_IESPI0_RX_FRAMING_ERROR 15
5627 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
5628 #define F_IESPI0_RX_FRAMING_ERROR V_IESPI0_RX_FRAMING_ERROR(1U)
5629
5630 #define S_IESPI1_RX_FRAMING_ERROR 14
5631 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
5632 #define F_IESPI1_RX_FRAMING_ERROR V_IESPI1_RX_FRAMING_ERROR(1U)
5633
5634 #define S_IESPI0_TX_FRAMING_ERROR 13
5635 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
5636 #define F_IESPI0_TX_FRAMING_ERROR V_IESPI0_TX_FRAMING_ERROR(1U)
5637
5638 #define S_IESPI1_TX_FRAMING_ERROR 12
5639 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
5640 #define F_IESPI1_TX_FRAMING_ERROR V_IESPI1_TX_FRAMING_ERROR(1U)
5641
5642 #define S_OCSPI0_RX_FRAMING_ERROR 11
5643 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
5644 #define F_OCSPI0_RX_FRAMING_ERROR V_OCSPI0_RX_FRAMING_ERROR(1U)
5645
5646 #define S_OCSPI1_RX_FRAMING_ERROR 10
5647 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
5648 #define F_OCSPI1_RX_FRAMING_ERROR V_OCSPI1_RX_FRAMING_ERROR(1U)
5649
5650 #define S_OCSPI0_TX_FRAMING_ERROR 9
5651 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
5652 #define F_OCSPI0_TX_FRAMING_ERROR V_OCSPI0_TX_FRAMING_ERROR(1U)
5653
5654 #define S_OCSPI1_TX_FRAMING_ERROR 8
5655 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
5656 #define F_OCSPI1_TX_FRAMING_ERROR V_OCSPI1_TX_FRAMING_ERROR(1U)
5657
5658 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR 7
5659 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
5660 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
5661
5662 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR 6
5663 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
5664 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
5665
5666 #define S_IESPI_PAR_ERROR 3
5667 #define M_IESPI_PAR_ERROR 0x7
5668 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
5669 #define G_IESPI_PAR_ERROR(x) (((x) >> S_IESPI_PAR_ERROR) & M_IESPI_PAR_ERROR)
5670
5671 #define S_OCSPI_PAR_ERROR 0
5672 #define M_OCSPI_PAR_ERROR 0x7
5673 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
5674 #define G_OCSPI_PAR_ERROR(x) (((x) >> S_OCSPI_PAR_ERROR) & M_OCSPI_PAR_ERROR)
5675
5676 #define A_PM1_RX_INT_CAUSE 0x5dc
5677
5678 /* registers for module PM1_TX */
5679 #define PM1_TX_BASE_ADDR 0x5e0
5680
5681 #define A_PM1_TX_CFG 0x5e0
5682 #define A_PM1_TX_MODE 0x5e4
5683 #define A_PM1_TX_STAT_CONFIG 0x5e8
5684 #define A_PM1_TX_STAT_COUNT 0x5ec
5685 #define A_PM1_TX_STAT_MSB 0x5f0
5686 #define A_PM1_TX_STAT_LSB 0x5f4
5687 #define A_PM1_TX_INT_ENABLE 0x5f8
5688
5689 #define S_ZERO_C_CMD_ERROR 18
5690 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
5691 #define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U)
5692
5693 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR 17
5694 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
5695 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
5696
5697 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR 16
5698 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
5699 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
5700
5701 #define S_ICSPI0_RX_FRAMING_ERROR 15
5702 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
5703 #define F_ICSPI0_RX_FRAMING_ERROR V_ICSPI0_RX_FRAMING_ERROR(1U)
5704
5705 #define S_ICSPI1_RX_FRAMING_ERROR 14
5706 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
5707 #define F_ICSPI1_RX_FRAMING_ERROR V_ICSPI1_RX_FRAMING_ERROR(1U)
5708
5709 #define S_ICSPI0_TX_FRAMING_ERROR 13
5710 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
5711 #define F_ICSPI0_TX_FRAMING_ERROR V_ICSPI0_TX_FRAMING_ERROR(1U)
5712
5713 #define S_ICSPI1_TX_FRAMING_ERROR 12
5714 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
5715 #define F_ICSPI1_TX_FRAMING_ERROR V_ICSPI1_TX_FRAMING_ERROR(1U)
5716
5717 #define S_OESPI0_RX_FRAMING_ERROR 11
5718 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
5719 #define F_OESPI0_RX_FRAMING_ERROR V_OESPI0_RX_FRAMING_ERROR(1U)
5720
5721 #define S_OESPI1_RX_FRAMING_ERROR 10
5722 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
5723 #define F_OESPI1_RX_FRAMING_ERROR V_OESPI1_RX_FRAMING_ERROR(1U)
5724
5725 #define S_OESPI0_TX_FRAMING_ERROR 9
5726 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
5727 #define F_OESPI0_TX_FRAMING_ERROR V_OESPI0_TX_FRAMING_ERROR(1U)
5728
5729 #define S_OESPI1_TX_FRAMING_ERROR 8
5730 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
5731 #define F_OESPI1_TX_FRAMING_ERROR V_OESPI1_TX_FRAMING_ERROR(1U)
5732
5733 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR 7
5734 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
5735 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
5736
5737 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR 6
5738 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
5739 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
5740
5741 #define S_ICSPI_PAR_ERROR 3
5742 #define M_ICSPI_PAR_ERROR 0x7
5743 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
5744 #define G_ICSPI_PAR_ERROR(x) (((x) >> S_ICSPI_PAR_ERROR) & M_ICSPI_PAR_ERROR)
5745
5746 #define S_OESPI_PAR_ERROR 0
5747 #define M_OESPI_PAR_ERROR 0x7
5748 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
5749 #define G_OESPI_PAR_ERROR(x) (((x) >> S_OESPI_PAR_ERROR) & M_OESPI_PAR_ERROR)
5750
5751 #define A_PM1_TX_INT_CAUSE 0x5fc
5752
5753 /* registers for module MPS0 */
5754 #define MPS0_BASE_ADDR 0x600
5755
5756 #define A_MPS_CFG 0x600
5757
5758 #define S_ENFORCEPKT 11
5759 #define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT)
5760 #define F_ENFORCEPKT V_ENFORCEPKT(1U)
5761
5762 #define S_SGETPQID 8
5763 #define M_SGETPQID 0x7
5764 #define V_SGETPQID(x) ((x) << S_SGETPQID)
5765 #define G_SGETPQID(x) (((x) >> S_SGETPQID) & M_SGETPQID)
5766
5767 #define S_TPRXPORTSIZE 7
5768 #define V_TPRXPORTSIZE(x) ((x) << S_TPRXPORTSIZE)
5769 #define F_TPRXPORTSIZE V_TPRXPORTSIZE(1U)
5770
5771 #define S_TPTXPORT1SIZE 6
5772 #define V_TPTXPORT1SIZE(x) ((x) << S_TPTXPORT1SIZE)
5773 #define F_TPTXPORT1SIZE V_TPTXPORT1SIZE(1U)
5774
5775 #define S_TPTXPORT0SIZE 5
5776 #define V_TPTXPORT0SIZE(x) ((x) << S_TPTXPORT0SIZE)
5777 #define F_TPTXPORT0SIZE V_TPTXPORT0SIZE(1U)
5778
5779 #define S_TPRXPORTEN 4
5780 #define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN)
5781 #define F_TPRXPORTEN V_TPRXPORTEN(1U)
5782
5783 #define S_TPTXPORT1EN 3
5784 #define V_TPTXPORT1EN(x) ((x) << S_TPTXPORT1EN)
5785 #define F_TPTXPORT1EN V_TPTXPORT1EN(1U)
5786
5787 #define S_TPTXPORT0EN 2
5788 #define V_TPTXPORT0EN(x) ((x) << S_TPTXPORT0EN)
5789 #define F_TPTXPORT0EN V_TPTXPORT0EN(1U)
5790
5791 #define S_PORT1ACTIVE 1
5792 #define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE)
5793 #define F_PORT1ACTIVE V_PORT1ACTIVE(1U)
5794
5795 #define S_PORT0ACTIVE 0
5796 #define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE)
5797 #define F_PORT0ACTIVE V_PORT0ACTIVE(1U)
5798
5799 #define A_MPS_DRR_CFG1 0x604
5800
5801 #define S_RLDWTTPD1 11
5802 #define M_RLDWTTPD1 0x7ff
5803 #define V_RLDWTTPD1(x) ((x) << S_RLDWTTPD1)
5804 #define G_RLDWTTPD1(x) (((x) >> S_RLDWTTPD1) & M_RLDWTTPD1)
5805
5806 #define S_RLDWTTPD0 0
5807 #define M_RLDWTTPD0 0x7ff
5808 #define V_RLDWTTPD0(x) ((x) << S_RLDWTTPD0)
5809 #define G_RLDWTTPD0(x) (((x) >> S_RLDWTTPD0) & M_RLDWTTPD0)
5810
5811 #define A_MPS_DRR_CFG2 0x608
5812
5813 #define S_RLDWTTOTAL 0
5814 #define M_RLDWTTOTAL 0xfff
5815 #define V_RLDWTTOTAL(x) ((x) << S_RLDWTTOTAL)
5816 #define G_RLDWTTOTAL(x) (((x) >> S_RLDWTTOTAL) & M_RLDWTTOTAL)
5817
5818 #define A_MPS_MCA_STATUS 0x60c
5819
5820 #define S_MCAPKTCNT 12
5821 #define M_MCAPKTCNT 0xfffff
5822 #define V_MCAPKTCNT(x) ((x) << S_MCAPKTCNT)
5823 #define G_MCAPKTCNT(x) (((x) >> S_MCAPKTCNT) & M_MCAPKTCNT)
5824
5825 #define S_MCADEPTH 0
5826 #define M_MCADEPTH 0xfff
5827 #define V_MCADEPTH(x) ((x) << S_MCADEPTH)
5828 #define G_MCADEPTH(x) (((x) >> S_MCADEPTH) & M_MCADEPTH)
5829
5830 #define A_MPS_TX0_TP_CNT 0x610
5831
5832 #define S_TX0TPDISCNT 24
5833 #define M_TX0TPDISCNT 0xff
5834 #define V_TX0TPDISCNT(x) ((x) << S_TX0TPDISCNT)
5835 #define G_TX0TPDISCNT(x) (((x) >> S_TX0TPDISCNT) & M_TX0TPDISCNT)
5836
5837 #define S_TX0TPCNT 0
5838 #define M_TX0TPCNT 0xffffff
5839 #define V_TX0TPCNT(x) ((x) << S_TX0TPCNT)
5840 #define G_TX0TPCNT(x) (((x) >> S_TX0TPCNT) & M_TX0TPCNT)
5841
5842 #define A_MPS_TX1_TP_CNT 0x614
5843
5844 #define S_TX1TPDISCNT 24
5845 #define M_TX1TPDISCNT 0xff
5846 #define V_TX1TPDISCNT(x) ((x) << S_TX1TPDISCNT)
5847 #define G_TX1TPDISCNT(x) (((x) >> S_TX1TPDISCNT) & M_TX1TPDISCNT)
5848
5849 #define S_TX1TPCNT 0
5850 #define M_TX1TPCNT 0xffffff
5851 #define V_TX1TPCNT(x) ((x) << S_TX1TPCNT)
5852 #define G_TX1TPCNT(x) (((x) >> S_TX1TPCNT) & M_TX1TPCNT)
5853
5854 #define A_MPS_RX_TP_CNT 0x618
5855
5856 #define S_RXTPDISCNT 24
5857 #define M_RXTPDISCNT 0xff
5858 #define V_RXTPDISCNT(x) ((x) << S_RXTPDISCNT)
5859 #define G_RXTPDISCNT(x) (((x) >> S_RXTPDISCNT) & M_RXTPDISCNT)
5860
5861 #define S_RXTPCNT 0
5862 #define M_RXTPCNT 0xffffff
5863 #define V_RXTPCNT(x) ((x) << S_RXTPCNT)
5864 #define G_RXTPCNT(x) (((x) >> S_RXTPCNT) & M_RXTPCNT)
5865
5866 #define A_MPS_INT_ENABLE 0x61c
5867
5868 #define S_MCAPARERRENB 6
5869 #define M_MCAPARERRENB 0x7
5870 #define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB)
5871 #define G_MCAPARERRENB(x) (((x) >> S_MCAPARERRENB) & M_MCAPARERRENB)
5872
5873 #define S_RXTPPARERRENB 4
5874 #define M_RXTPPARERRENB 0x3
5875 #define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB)
5876 #define G_RXTPPARERRENB(x) (((x) >> S_RXTPPARERRENB) & M_RXTPPARERRENB)
5877
5878 #define S_TX1TPPARERRENB 2
5879 #define M_TX1TPPARERRENB 0x3
5880 #define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB)
5881 #define G_TX1TPPARERRENB(x) (((x) >> S_TX1TPPARERRENB) & M_TX1TPPARERRENB)
5882
5883 #define S_TX0TPPARERRENB 0
5884 #define M_TX0TPPARERRENB 0x3
5885 #define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB)
5886 #define G_TX0TPPARERRENB(x) (((x) >> S_TX0TPPARERRENB) & M_TX0TPPARERRENB)
5887
5888 #define A_MPS_INT_CAUSE 0x620
5889
5890 #define S_MCAPARERR 6
5891 #define M_MCAPARERR 0x7
5892 #define V_MCAPARERR(x) ((x) << S_MCAPARERR)
5893 #define G_MCAPARERR(x) (((x) >> S_MCAPARERR) & M_MCAPARERR)
5894
5895 #define S_RXTPPARERR 4
5896 #define M_RXTPPARERR 0x3
5897 #define V_RXTPPARERR(x) ((x) << S_RXTPPARERR)
5898 #define G_RXTPPARERR(x) (((x) >> S_RXTPPARERR) & M_RXTPPARERR)
5899
5900 #define S_TX1TPPARERR 2
5901 #define M_TX1TPPARERR 0x3
5902 #define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR)
5903 #define G_TX1TPPARERR(x) (((x) >> S_TX1TPPARERR) & M_TX1TPPARERR)
5904
5905 #define S_TX0TPPARERR 0
5906 #define M_TX0TPPARERR 0x3
5907 #define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR)
5908 #define G_TX0TPPARERR(x) (((x) >> S_TX0TPPARERR) & M_TX0TPPARERR)
5909
5910 /* registers for module CPL_SWITCH */
5911 #define CPL_SWITCH_BASE_ADDR 0x640
5912
5913 #define A_CPL_SWITCH_CNTRL 0x640
5914
5915 #define S_CPL_PKT_TID 8
5916 #define M_CPL_PKT_TID 0xffffff
5917 #define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID)
5918 #define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID)
5919
5920 #define S_CIM_TO_UP_FULL_SIZE 4
5921 #define V_CIM_TO_UP_FULL_SIZE(x) ((x) << S_CIM_TO_UP_FULL_SIZE)
5922 #define F_CIM_TO_UP_FULL_SIZE V_CIM_TO_UP_FULL_SIZE(1U)
5923
5924 #define S_CPU_NO_3F_CIM_ENABLE 3
5925 #define V_CPU_NO_3F_CIM_ENABLE(x) ((x) << S_CPU_NO_3F_CIM_ENABLE)
5926 #define F_CPU_NO_3F_CIM_ENABLE V_CPU_NO_3F_CIM_ENABLE(1U)
5927
5928 #define S_SWITCH_TABLE_ENABLE 2
5929 #define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE)
5930 #define F_SWITCH_TABLE_ENABLE V_SWITCH_TABLE_ENABLE(1U)
5931
5932 #define S_SGE_ENABLE 1
5933 #define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE)
5934 #define F_SGE_ENABLE V_SGE_ENABLE(1U)
5935
5936 #define S_CIM_ENABLE 0
5937 #define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE)
5938 #define F_CIM_ENABLE V_CIM_ENABLE(1U)
5939
5940 #define A_CPL_SWITCH_TBL_IDX 0x644
5941
5942 #define S_SWITCH_TBL_IDX 0
5943 #define M_SWITCH_TBL_IDX 0xf
5944 #define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX)
5945 #define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX)
5946
5947 #define A_CPL_SWITCH_TBL_DATA 0x648
5948 #define A_CPL_SWITCH_ZERO_ERROR 0x64c
5949
5950 #define S_ZERO_CMD 0
5951 #define M_ZERO_CMD 0xff
5952 #define V_ZERO_CMD(x) ((x) << S_ZERO_CMD)
5953 #define G_ZERO_CMD(x) (((x) >> S_ZERO_CMD) & M_ZERO_CMD)
5954
5955 #define A_CPL_INTR_ENABLE 0x650
5956
5957 #define S_CIM_OP_MAP_PERR 5
5958 #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
5959 #define F_CIM_OP_MAP_PERR V_CIM_OP_MAP_PERR(1U)
5960
5961 #define S_CIM_OVFL_ERROR 4
5962 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
5963 #define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U)
5964
5965 #define S_TP_FRAMING_ERROR 3
5966 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
5967 #define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U)
5968
5969 #define S_SGE_FRAMING_ERROR 2
5970 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
5971 #define F_SGE_FRAMING_ERROR V_SGE_FRAMING_ERROR(1U)
5972
5973 #define S_CIM_FRAMING_ERROR 1
5974 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
5975 #define F_CIM_FRAMING_ERROR V_CIM_FRAMING_ERROR(1U)
5976
5977 #define S_ZERO_SWITCH_ERROR 0
5978 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
5979 #define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U)
5980
5981 #define A_CPL_INTR_CAUSE 0x654
5982 #define A_CPL_MAP_TBL_IDX 0x658
5983
5984 #define S_CPL_MAP_TBL_IDX 0
5985 #define M_CPL_MAP_TBL_IDX 0xff
5986 #define V_CPL_MAP_TBL_IDX(x) ((x) << S_CPL_MAP_TBL_IDX)
5987 #define G_CPL_MAP_TBL_IDX(x) (((x) >> S_CPL_MAP_TBL_IDX) & M_CPL_MAP_TBL_IDX)
5988
5989 #define A_CPL_MAP_TBL_DATA 0x65c
5990
5991 #define S_CPL_MAP_TBL_DATA 0
5992 #define M_CPL_MAP_TBL_DATA 0xff
5993 #define V_CPL_MAP_TBL_DATA(x) ((x) << S_CPL_MAP_TBL_DATA)
5994 #define G_CPL_MAP_TBL_DATA(x) (((x) >> S_CPL_MAP_TBL_DATA) & M_CPL_MAP_TBL_DATA)
5995
5996 /* registers for module SMB0 */
5997 #define SMB0_BASE_ADDR 0x660
5998
5999 #define A_SMB_GLOBAL_TIME_CFG 0x660
6000
6001 #define S_LADBGWRPTR 24
6002 #define M_LADBGWRPTR 0xff
6003 #define V_LADBGWRPTR(x) ((x) << S_LADBGWRPTR)
6004 #define G_LADBGWRPTR(x) (((x) >> S_LADBGWRPTR) & M_LADBGWRPTR)
6005
6006 #define S_LADBGRDPTR 16
6007 #define M_LADBGRDPTR 0xff
6008 #define V_LADBGRDPTR(x) ((x) << S_LADBGRDPTR)
6009 #define G_LADBGRDPTR(x) (((x) >> S_LADBGRDPTR) & M_LADBGRDPTR)
6010
6011 #define S_LADBGEN 13
6012 #define V_LADBGEN(x) ((x) << S_LADBGEN)
6013 #define F_LADBGEN V_LADBGEN(1U)
6014
6015 #define S_MACROCNTCFG 8
6016 #define M_MACROCNTCFG 0x1f
6017 #define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG)
6018 #define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG)
6019
6020 #define S_MICROCNTCFG 0
6021 #define M_MICROCNTCFG 0xff
6022 #define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG)
6023 #define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG)
6024
6025 #define A_SMB_MST_TIMEOUT_CFG 0x664
6026
6027 #define S_DEBUGSELH 28
6028 #define M_DEBUGSELH 0xf
6029 #define V_DEBUGSELH(x) ((x) << S_DEBUGSELH)
6030 #define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH)
6031
6032 #define S_DEBUGSELL 24
6033 #define M_DEBUGSELL 0xf
6034 #define V_DEBUGSELL(x) ((x) << S_DEBUGSELL)
6035 #define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL)
6036
6037 #define S_MSTTIMEOUTCFG 0
6038 #define M_MSTTIMEOUTCFG 0xffffff
6039 #define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG)
6040 #define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG)
6041
6042 #define A_SMB_MST_CTL_CFG 0x668
6043
6044 #define S_MSTFIFODBG 31
6045 #define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG)
6046 #define F_MSTFIFODBG V_MSTFIFODBG(1U)
6047
6048 #define S_MSTFIFODBGCLR 30
6049 #define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR)
6050 #define F_MSTFIFODBGCLR V_MSTFIFODBGCLR(1U)
6051
6052 #define S_MSTRXBYTECFG 12
6053 #define M_MSTRXBYTECFG 0x3f
6054 #define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG)
6055 #define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG)
6056
6057 #define S_MSTTXBYTECFG 6
6058 #define M_MSTTXBYTECFG 0x3f
6059 #define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG)
6060 #define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG)
6061
6062 #define S_MSTRESET 1
6063 #define V_MSTRESET(x) ((x) << S_MSTRESET)
6064 #define F_MSTRESET V_MSTRESET(1U)
6065
6066 #define S_MSTCTLEN 0
6067 #define V_MSTCTLEN(x) ((x) << S_MSTCTLEN)
6068 #define F_MSTCTLEN V_MSTCTLEN(1U)
6069
6070 #define A_SMB_MST_CTL_STS 0x66c
6071
6072 #define S_MSTRXBYTECNT 12
6073 #define M_MSTRXBYTECNT 0x3f
6074 #define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT)
6075 #define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT)
6076
6077 #define S_MSTTXBYTECNT 6
6078 #define M_MSTTXBYTECNT 0x3f
6079 #define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT)
6080 #define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT)
6081
6082 #define S_MSTBUSYSTS 0
6083 #define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS)
6084 #define F_MSTBUSYSTS V_MSTBUSYSTS(1U)
6085
6086 #define A_SMB_MST_TX_FIFO_RDWR 0x670
6087 #define A_SMB_MST_RX_FIFO_RDWR 0x674
6088 #define A_SMB_SLV_TIMEOUT_CFG 0x678
6089
6090 #define S_SLVTIMEOUTCFG 0
6091 #define M_SLVTIMEOUTCFG 0xffffff
6092 #define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG)
6093 #define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG)
6094
6095 #define A_SMB_SLV_CTL_CFG 0x67c
6096
6097 #define S_SLVFIFODBG 31
6098 #define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG)
6099 #define F_SLVFIFODBG V_SLVFIFODBG(1U)
6100
6101 #define S_SLVFIFODBGCLR 30
6102 #define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR)
6103 #define F_SLVFIFODBGCLR V_SLVFIFODBGCLR(1U)
6104
6105 #define S_SLVADDRCFG 4
6106 #define M_SLVADDRCFG 0x7f
6107 #define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG)
6108 #define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG)
6109
6110 #define S_SLVALRTSET 2
6111 #define V_SLVALRTSET(x) ((x) << S_SLVALRTSET)
6112 #define F_SLVALRTSET V_SLVALRTSET(1U)
6113
6114 #define S_SLVRESET 1
6115 #define V_SLVRESET(x) ((x) << S_SLVRESET)
6116 #define F_SLVRESET V_SLVRESET(1U)
6117
6118 #define S_SLVCTLEN 0
6119 #define V_SLVCTLEN(x) ((x) << S_SLVCTLEN)
6120 #define F_SLVCTLEN V_SLVCTLEN(1U)
6121
6122 #define A_SMB_SLV_CTL_STS 0x680
6123
6124 #define S_SLVFIFOTXCNT 12
6125 #define M_SLVFIFOTXCNT 0x3f
6126 #define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT)
6127 #define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT)
6128
6129 #define S_SLVFIFOCNT 6
6130 #define M_SLVFIFOCNT 0x3f
6131 #define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT)
6132 #define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT)
6133
6134 #define S_SLVALRTSTS 2
6135 #define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS)
6136 #define F_SLVALRTSTS V_SLVALRTSTS(1U)
6137
6138 #define S_SLVBUSYSTS 0
6139 #define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS)
6140 #define F_SLVBUSYSTS V_SLVBUSYSTS(1U)
6141
6142 #define A_SMB_SLV_FIFO_RDWR 0x684
6143 #define A_SMB_SLV_CMD_FIFO_RDWR 0x688
6144 #define A_SMB_INT_ENABLE 0x68c
6145
6146 #define S_SLVTIMEOUTINTEN 7
6147 #define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN)
6148 #define F_SLVTIMEOUTINTEN V_SLVTIMEOUTINTEN(1U)
6149
6150 #define S_SLVERRINTEN 6
6151 #define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN)
6152 #define F_SLVERRINTEN V_SLVERRINTEN(1U)
6153
6154 #define S_SLVDONEINTEN 5
6155 #define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN)
6156 #define F_SLVDONEINTEN V_SLVDONEINTEN(1U)
6157
6158 #define S_SLVRXRDYINTEN 4
6159 #define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN)
6160 #define F_SLVRXRDYINTEN V_SLVRXRDYINTEN(1U)
6161
6162 #define S_MSTTIMEOUTINTEN 3
6163 #define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN)
6164 #define F_MSTTIMEOUTINTEN V_MSTTIMEOUTINTEN(1U)
6165
6166 #define S_MSTNACKINTEN 2
6167 #define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN)
6168 #define F_MSTNACKINTEN V_MSTNACKINTEN(1U)
6169
6170 #define S_MSTLOSTARBINTEN 1
6171 #define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN)
6172 #define F_MSTLOSTARBINTEN V_MSTLOSTARBINTEN(1U)
6173
6174 #define S_MSTDONEINTEN 0
6175 #define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN)
6176 #define F_MSTDONEINTEN V_MSTDONEINTEN(1U)
6177
6178 #define A_SMB_INT_CAUSE 0x690
6179
6180 #define S_SLVTIMEOUTINT 7
6181 #define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT)
6182 #define F_SLVTIMEOUTINT V_SLVTIMEOUTINT(1U)
6183
6184 #define S_SLVERRINT 6
6185 #define V_SLVERRINT(x) ((x) << S_SLVERRINT)
6186 #define F_SLVERRINT V_SLVERRINT(1U)
6187
6188 #define S_SLVDONEINT 5
6189 #define V_SLVDONEINT(x) ((x) << S_SLVDONEINT)
6190 #define F_SLVDONEINT V_SLVDONEINT(1U)
6191
6192 #define S_SLVRXRDYINT 4
6193 #define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT)
6194 #define F_SLVRXRDYINT V_SLVRXRDYINT(1U)
6195
6196 #define S_MSTTIMEOUTINT 3
6197 #define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT)
6198 #define F_MSTTIMEOUTINT V_MSTTIMEOUTINT(1U)
6199
6200 #define S_MSTNACKINT 2
6201 #define V_MSTNACKINT(x) ((x) << S_MSTNACKINT)
6202 #define F_MSTNACKINT V_MSTNACKINT(1U)
6203
6204 #define S_MSTLOSTARBINT 1
6205 #define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT)
6206 #define F_MSTLOSTARBINT V_MSTLOSTARBINT(1U)
6207
6208 #define S_MSTDONEINT 0
6209 #define V_MSTDONEINT(x) ((x) << S_MSTDONEINT)
6210 #define F_MSTDONEINT V_MSTDONEINT(1U)
6211
6212 #define A_SMB_DEBUG_DATA 0x694
6213
6214 #define S_DEBUGDATAH 16
6215 #define M_DEBUGDATAH 0xffff
6216 #define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH)
6217 #define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH)
6218
6219 #define S_DEBUGDATAL 0
6220 #define M_DEBUGDATAL 0xffff
6221 #define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL)
6222 #define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL)
6223
6224 #define A_SMB_DEBUG_LA 0x69c
6225
6226 #define S_DEBUGLAREQADDR 0
6227 #define M_DEBUGLAREQADDR 0x3ff
6228 #define V_DEBUGLAREQADDR(x) ((x) << S_DEBUGLAREQADDR)
6229 #define G_DEBUGLAREQADDR(x) (((x) >> S_DEBUGLAREQADDR) & M_DEBUGLAREQADDR)
6230
6231 /* registers for module I2CM0 */
6232 #define I2CM0_BASE_ADDR 0x6a0
6233
6234 #define A_I2C_CFG 0x6a0
6235
6236 #define S_I2C_CLKDIV 0
6237 #define M_I2C_CLKDIV 0xfff
6238 #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
6239 #define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV)
6240
6241 #define A_I2C_DATA 0x6a4
6242 #define A_I2C_OP 0x6a8
6243
6244 #define S_ACK 30
6245 #define V_ACK(x) ((x) << S_ACK)
6246 #define F_ACK V_ACK(1U)
6247
6248 #define S_I2C_DATA 0
6249 #define M_I2C_DATA 0xff
6250 #define V_I2C_DATA(x) ((x) << S_I2C_DATA)
6251 #define G_I2C_DATA(x) (((x) >> S_I2C_DATA) & M_I2C_DATA)
6252
6253 #define S_I2C_BUSY 31
6254 #define V_I2C_BUSY(x) ((x) << S_I2C_BUSY)
6255 #define F_I2C_BUSY V_I2C_BUSY(1U)
6256
6257 #define S_I2C_ACK 30
6258 #define V_I2C_ACK(x) ((x) << S_I2C_ACK)
6259 #define F_I2C_ACK V_I2C_ACK(1U)
6260
6261 #define S_I2C_CONT 1
6262 #define V_I2C_CONT(x) ((x) << S_I2C_CONT)
6263 #define F_I2C_CONT V_I2C_CONT(1U)
6264
6265 #define S_I2C_RDWR 0
6266 #define V_I2C_RDWR(x) ((x) << S_I2C_RDWR)
6267 #define F_I2C_READ V_I2C_RDWR(0U)
6268 #define F_I2C_WRITE V_I2C_RDWR(1U)
6269
6270 /* registers for module MI1 */
6271 #define MI1_BASE_ADDR 0x6b0
6272
6273 #define A_MI1_CFG 0x6b0
6274
6275 #define S_CLKDIV 5
6276 #define M_CLKDIV 0xff
6277 #define V_CLKDIV(x) ((x) << S_CLKDIV)
6278 #define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV)
6279
6280 #define S_ST 3
6281 #define M_ST 0x3
6282 #define V_ST(x) ((x) << S_ST)
6283 #define G_ST(x) (((x) >> S_ST) & M_ST)
6284
6285 #define S_PREEN 2
6286 #define V_PREEN(x) ((x) << S_PREEN)
6287 #define F_PREEN V_PREEN(1U)
6288
6289 #define S_MDIINV 1
6290 #define V_MDIINV(x) ((x) << S_MDIINV)
6291 #define F_MDIINV V_MDIINV(1U)
6292
6293 #define S_MDIEN 0
6294 #define V_MDIEN(x) ((x) << S_MDIEN)
6295 #define F_MDIEN V_MDIEN(1U)
6296
6297 #define A_MI1_ADDR 0x6b4
6298
6299 #define S_PHYADDR 5
6300 #define M_PHYADDR 0x1f
6301 #define V_PHYADDR(x) ((x) << S_PHYADDR)
6302 #define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR)
6303
6304 #define S_REGADDR 0
6305 #define M_REGADDR 0x1f
6306 #define V_REGADDR(x) ((x) << S_REGADDR)
6307 #define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR)
6308
6309 #define A_MI1_DATA 0x6b8
6310
6311 #define S_MDI_DATA 0
6312 #define M_MDI_DATA 0xffff
6313 #define V_MDI_DATA(x) ((x) << S_MDI_DATA)
6314 #define G_MDI_DATA(x) (((x) >> S_MDI_DATA) & M_MDI_DATA)
6315
6316 #define A_MI1_OP 0x6bc
6317
6318 #define S_INC 2
6319 #define V_INC(x) ((x) << S_INC)
6320 #define F_INC V_INC(1U)
6321
6322 #define S_MDI_OP 0
6323 #define M_MDI_OP 0x3
6324 #define V_MDI_OP(x) ((x) << S_MDI_OP)
6325 #define G_MDI_OP(x) (((x) >> S_MDI_OP) & M_MDI_OP)
6326
6327 /* registers for module JM1 */
6328 #define JM1_BASE_ADDR 0x6c0
6329
6330 #define A_JM_CFG 0x6c0
6331
6332 #define S_JM_CLKDIV 2
6333 #define M_JM_CLKDIV 0xff
6334 #define V_JM_CLKDIV(x) ((x) << S_JM_CLKDIV)
6335 #define G_JM_CLKDIV(x) (((x) >> S_JM_CLKDIV) & M_JM_CLKDIV)
6336
6337 #define S_TRST 1
6338 #define V_TRST(x) ((x) << S_TRST)
6339 #define F_TRST V_TRST(1U)
6340
6341 #define S_EN 0
6342 #define V_EN(x) ((x) << S_EN)
6343 #define F_EN V_EN(1U)
6344
6345 #define A_JM_MODE 0x6c4
6346 #define A_JM_DATA 0x6c8
6347 #define A_JM_OP 0x6cc
6348
6349 #define S_CNT 0
6350 #define M_CNT 0x1f
6351 #define V_CNT(x) ((x) << S_CNT)
6352 #define G_CNT(x) (((x) >> S_CNT) & M_CNT)
6353
6354 /* registers for module SF1 */
6355 #define SF1_BASE_ADDR 0x6d8
6356
6357 #define A_SF_DATA 0x6d8
6358 #define A_SF_OP 0x6dc
6359
6360 #define S_BYTECNT 1
6361 #define M_BYTECNT 0x3
6362 #define V_BYTECNT(x) ((x) << S_BYTECNT)
6363 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
6364
6365 /* registers for module PL3 */
6366 #define PL3_BASE_ADDR 0x6e0
6367
6368 #define A_PL_INT_ENABLE0 0x6e0
6369
6370 #define S_SW 25
6371 #define V_SW(x) ((x) << S_SW)
6372 #define F_SW V_SW(1U)
6373
6374 #define S_EXT 24
6375 #define V_EXT(x) ((x) << S_EXT)
6376 #define F_EXT V_EXT(1U)
6377
6378 #define S_T3DBG 23
6379 #define V_T3DBG(x) ((x) << S_T3DBG)
6380 #define F_T3DBG V_T3DBG(1U)
6381
6382 #define S_XGMAC0_1 20
6383 #define V_XGMAC0_1(x) ((x) << S_XGMAC0_1)
6384 #define F_XGMAC0_1 V_XGMAC0_1(1U)
6385
6386 #define S_XGMAC0_0 19
6387 #define V_XGMAC0_0(x) ((x) << S_XGMAC0_0)
6388 #define F_XGMAC0_0 V_XGMAC0_0(1U)
6389
6390 #define S_MC5A 18
6391 #define V_MC5A(x) ((x) << S_MC5A)
6392 #define F_MC5A V_MC5A(1U)
6393
6394 #define S_SF1 17
6395 #define V_SF1(x) ((x) << S_SF1)
6396 #define F_SF1 V_SF1(1U)
6397
6398 #define S_SMB0 15
6399 #define V_SMB0(x) ((x) << S_SMB0)
6400 #define F_SMB0 V_SMB0(1U)
6401
6402 #define S_I2CM0 14
6403 #define V_I2CM0(x) ((x) << S_I2CM0)
6404 #define F_I2CM0 V_I2CM0(1U)
6405
6406 #define S_MI1 13
6407 #define V_MI1(x) ((x) << S_MI1)
6408 #define F_MI1 V_MI1(1U)
6409
6410 #define S_CPL_SWITCH 12
6411 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
6412 #define F_CPL_SWITCH V_CPL_SWITCH(1U)
6413
6414 #define S_MPS0 11
6415 #define V_MPS0(x) ((x) << S_MPS0)
6416 #define F_MPS0 V_MPS0(1U)
6417
6418 #define S_PM1_TX 10
6419 #define V_PM1_TX(x) ((x) << S_PM1_TX)
6420 #define F_PM1_TX V_PM1_TX(1U)
6421
6422 #define S_PM1_RX 9
6423 #define V_PM1_RX(x) ((x) << S_PM1_RX)
6424 #define F_PM1_RX V_PM1_RX(1U)
6425
6426 #define S_ULP2_TX 8
6427 #define V_ULP2_TX(x) ((x) << S_ULP2_TX)
6428 #define F_ULP2_TX V_ULP2_TX(1U)
6429
6430 #define S_ULP2_RX 7
6431 #define V_ULP2_RX(x) ((x) << S_ULP2_RX)
6432 #define F_ULP2_RX V_ULP2_RX(1U)
6433
6434 #define S_TP1 6
6435 #define V_TP1(x) ((x) << S_TP1)
6436 #define F_TP1 V_TP1(1U)
6437
6438 #define S_CIM 5
6439 #define V_CIM(x) ((x) << S_CIM)
6440 #define F_CIM V_CIM(1U)
6441
6442 #define S_MC7_CM 4
6443 #define V_MC7_CM(x) ((x) << S_MC7_CM)
6444 #define F_MC7_CM V_MC7_CM(1U)
6445
6446 #define S_MC7_PMTX 3
6447 #define V_MC7_PMTX(x) ((x) << S_MC7_PMTX)
6448 #define F_MC7_PMTX V_MC7_PMTX(1U)
6449
6450 #define S_MC7_PMRX 2
6451 #define V_MC7_PMRX(x) ((x) << S_MC7_PMRX)
6452 #define F_MC7_PMRX V_MC7_PMRX(1U)
6453
6454 #define S_PCIM0 1
6455 #define V_PCIM0(x) ((x) << S_PCIM0)
6456 #define F_PCIM0 V_PCIM0(1U)
6457
6458 #define S_SGE3 0
6459 #define V_SGE3(x) ((x) << S_SGE3)
6460 #define F_SGE3 V_SGE3(1U)
6461
6462 #define A_PL_INT_CAUSE0 0x6e4
6463 #define A_PL_INT_ENABLE1 0x6e8
6464 #define A_PL_INT_CAUSE1 0x6ec
6465 #define A_PL_RST 0x6f0
6466
6467 #define S_FATALPERREN 4
6468 #define V_FATALPERREN(x) ((x) << S_FATALPERREN)
6469 #define F_FATALPERREN V_FATALPERREN(1U)
6470
6471 #define S_SWINT1 3
6472 #define V_SWINT1(x) ((x) << S_SWINT1)
6473 #define F_SWINT1 V_SWINT1(1U)
6474
6475 #define S_SWINT0 2
6476 #define V_SWINT0(x) ((x) << S_SWINT0)
6477 #define F_SWINT0 V_SWINT0(1U)
6478
6479 #define S_CRSTWRM 1
6480 #define V_CRSTWRM(x) ((x) << S_CRSTWRM)
6481 #define F_CRSTWRM V_CRSTWRM(1U)
6482
6483 #define A_PL_REV 0x6f4
6484
6485 #define S_REV 0
6486 #define M_REV 0xf
6487 #define V_REV(x) ((x) << S_REV)
6488 #define G_REV(x) (((x) >> S_REV) & M_REV)
6489
6490 #define A_PL_CLI 0x6f8
6491 #define A_PL_LCK 0x6fc
6492
6493 #define S_LCK 0
6494 #define M_LCK 0x3
6495 #define V_LCK(x) ((x) << S_LCK)
6496 #define G_LCK(x) (((x) >> S_LCK) & M_LCK)
6497
6498 /* registers for module MC5A */
6499 #define MC5A_BASE_ADDR 0x700
6500
6501 #define A_MC5_BUF_CONFIG 0x700
6502
6503 #define S_TERM300_240 31
6504 #define V_TERM300_240(x) ((x) << S_TERM300_240)
6505 #define F_TERM300_240 V_TERM300_240(1U)
6506
6507 #define S_MC5_TERM150 30
6508 #define V_MC5_TERM150(x) ((x) << S_MC5_TERM150)
6509 #define F_MC5_TERM150 V_MC5_TERM150(1U)
6510
6511 #define S_TERM60 29
6512 #define V_TERM60(x) ((x) << S_TERM60)
6513 #define F_TERM60 V_TERM60(1U)
6514
6515 #define S_GDDRIII 28
6516 #define V_GDDRIII(x) ((x) << S_GDDRIII)
6517 #define F_GDDRIII V_GDDRIII(1U)
6518
6519 #define S_GDDRII 27
6520 #define V_GDDRII(x) ((x) << S_GDDRII)
6521 #define F_GDDRII V_GDDRII(1U)
6522
6523 #define S_GDDRI 26
6524 #define V_GDDRI(x) ((x) << S_GDDRI)
6525 #define F_GDDRI V_GDDRI(1U)
6526
6527 #define S_READ 25
6528 #define V_READ(x) ((x) << S_READ)
6529 #define F_READ V_READ(1U)
6530
6531 #define S_IMP_SET_UPDATE 24
6532 #define V_IMP_SET_UPDATE(x) ((x) << S_IMP_SET_UPDATE)
6533 #define F_IMP_SET_UPDATE V_IMP_SET_UPDATE(1U)
6534
6535 #define S_CAL_UPDATE 23
6536 #define V_CAL_UPDATE(x) ((x) << S_CAL_UPDATE)
6537 #define F_CAL_UPDATE V_CAL_UPDATE(1U)
6538
6539 #define S_CAL_BUSY 22
6540 #define V_CAL_BUSY(x) ((x) << S_CAL_BUSY)
6541 #define F_CAL_BUSY V_CAL_BUSY(1U)
6542
6543 #define S_CAL_ERROR 21
6544 #define V_CAL_ERROR(x) ((x) << S_CAL_ERROR)
6545 #define F_CAL_ERROR V_CAL_ERROR(1U)
6546
6547 #define S_SGL_CAL_EN 20
6548 #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN)
6549 #define F_SGL_CAL_EN V_SGL_CAL_EN(1U)
6550
6551 #define S_IMP_UPD_MODE 19
6552 #define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE)
6553 #define F_IMP_UPD_MODE V_IMP_UPD_MODE(1U)
6554
6555 #define S_IMP_SEL 18
6556 #define V_IMP_SEL(x) ((x) << S_IMP_SEL)
6557 #define F_IMP_SEL V_IMP_SEL(1U)
6558
6559 #define S_MAN_PU 15
6560 #define M_MAN_PU 0x7
6561 #define V_MAN_PU(x) ((x) << S_MAN_PU)
6562 #define G_MAN_PU(x) (((x) >> S_MAN_PU) & M_MAN_PU)
6563
6564 #define S_MAN_PD 12
6565 #define M_MAN_PD 0x7
6566 #define V_MAN_PD(x) ((x) << S_MAN_PD)
6567 #define G_MAN_PD(x) (((x) >> S_MAN_PD) & M_MAN_PD)
6568
6569 #define S_CAL_PU 9
6570 #define M_CAL_PU 0x7
6571 #define V_CAL_PU(x) ((x) << S_CAL_PU)
6572 #define G_CAL_PU(x) (((x) >> S_CAL_PU) & M_CAL_PU)
6573
6574 #define S_CAL_PD 6
6575 #define M_CAL_PD 0x7
6576 #define V_CAL_PD(x) ((x) << S_CAL_PD)
6577 #define G_CAL_PD(x) (((x) >> S_CAL_PD) & M_CAL_PD)
6578
6579 #define S_SET_PU 3
6580 #define M_SET_PU 0x7
6581 #define V_SET_PU(x) ((x) << S_SET_PU)
6582 #define G_SET_PU(x) (((x) >> S_SET_PU) & M_SET_PU)
6583
6584 #define S_SET_PD 0
6585 #define M_SET_PD 0x7
6586 #define V_SET_PD(x) ((x) << S_SET_PD)
6587 #define G_SET_PD(x) (((x) >> S_SET_PD) & M_SET_PD)
6588
6589 #define S_CAL_IMP_UPD 23
6590 #define V_CAL_IMP_UPD(x) ((x) << S_CAL_IMP_UPD)
6591 #define F_CAL_IMP_UPD V_CAL_IMP_UPD(1U)
6592
6593 #define A_MC5_DB_CONFIG 0x704
6594
6595 #define S_TMCFGWRLOCK 31
6596 #define V_TMCFGWRLOCK(x) ((x) << S_TMCFGWRLOCK)
6597 #define F_TMCFGWRLOCK V_TMCFGWRLOCK(1U)
6598
6599 #define S_TMTYPEHI 30
6600 #define V_TMTYPEHI(x) ((x) << S_TMTYPEHI)
6601 #define F_TMTYPEHI V_TMTYPEHI(1U)
6602
6603 #define S_TMPARTSIZE 28
6604 #define M_TMPARTSIZE 0x3
6605 #define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE)
6606 #define G_TMPARTSIZE(x) (((x) >> S_TMPARTSIZE) & M_TMPARTSIZE)
6607
6608 #define S_TMTYPE 26
6609 #define M_TMTYPE 0x3
6610 #define V_TMTYPE(x) ((x) << S_TMTYPE)
6611 #define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE)
6612
6613 #define S_TMPARTCOUNT 24
6614 #define M_TMPARTCOUNT 0x3
6615 #define V_TMPARTCOUNT(x) ((x) << S_TMPARTCOUNT)
6616 #define G_TMPARTCOUNT(x) (((x) >> S_TMPARTCOUNT) & M_TMPARTCOUNT)
6617
6618 #define S_NLIP 18
6619 #define M_NLIP 0x3f
6620 #define V_NLIP(x) ((x) << S_NLIP)
6621 #define G_NLIP(x) (((x) >> S_NLIP) & M_NLIP)
6622
6623 #define S_COMPEN 17
6624 #define V_COMPEN(x) ((x) << S_COMPEN)
6625 #define F_COMPEN V_COMPEN(1U)
6626
6627 #define S_BUILD 16
6628 #define V_BUILD(x) ((x) << S_BUILD)
6629 #define F_BUILD V_BUILD(1U)
6630
6631 #define S_FILTEREN 11
6632 #define V_FILTEREN(x) ((x) << S_FILTEREN)
6633 #define F_FILTEREN V_FILTEREN(1U)
6634
6635 #define S_CLIPUPDATE 10
6636 #define V_CLIPUPDATE(x) ((x) << S_CLIPUPDATE)
6637 #define F_CLIPUPDATE V_CLIPUPDATE(1U)
6638
6639 #define S_TM_IO_PDOWN 9
6640 #define V_TM_IO_PDOWN(x) ((x) << S_TM_IO_PDOWN)
6641 #define F_TM_IO_PDOWN V_TM_IO_PDOWN(1U)
6642
6643 #define S_SYNMODE 7
6644 #define M_SYNMODE 0x3
6645 #define V_SYNMODE(x) ((x) << S_SYNMODE)
6646 #define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE)
6647
6648 #define S_PRTYEN 6
6649 #define V_PRTYEN(x) ((x) << S_PRTYEN)
6650 #define F_PRTYEN V_PRTYEN(1U)
6651
6652 #define S_MBUSEN 5
6653 #define V_MBUSEN(x) ((x) << S_MBUSEN)
6654 #define F_MBUSEN V_MBUSEN(1U)
6655
6656 #define S_DBGIEN 4
6657 #define V_DBGIEN(x) ((x) << S_DBGIEN)
6658 #define F_DBGIEN V_DBGIEN(1U)
6659
6660 #define S_TCMCFGOVR 3
6661 #define V_TCMCFGOVR(x) ((x) << S_TCMCFGOVR)
6662 #define F_TCMCFGOVR V_TCMCFGOVR(1U)
6663
6664 #define S_TMRDY 2
6665 #define V_TMRDY(x) ((x) << S_TMRDY)
6666 #define F_TMRDY V_TMRDY(1U)
6667
6668 #define S_TMRST 1
6669 #define V_TMRST(x) ((x) << S_TMRST)
6670 #define F_TMRST V_TMRST(1U)
6671
6672 #define S_TMMODE 0
6673 #define V_TMMODE(x) ((x) << S_TMMODE)
6674 #define F_TMMODE V_TMMODE(1U)
6675
6676 #define A_MC5_MISC 0x708
6677
6678 #define S_LIP_CMP_UNAVAILABLE 0
6679 #define M_LIP_CMP_UNAVAILABLE 0xf
6680 #define V_LIP_CMP_UNAVAILABLE(x) ((x) << S_LIP_CMP_UNAVAILABLE)
6681 #define G_LIP_CMP_UNAVAILABLE(x) (((x) >> S_LIP_CMP_UNAVAILABLE) & M_LIP_CMP_UNAVAILABLE)
6682
6683 #define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c
6684
6685 #define S_RTINDX 0
6686 #define M_RTINDX 0x3fffff
6687 #define V_RTINDX(x) ((x) << S_RTINDX)
6688 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)
6689
6690 #define A_MC5_DB_FILTER_TABLE 0x710
6691
6692 #define S_SRINDX 0
6693 #define M_SRINDX 0x3fffff
6694 #define V_SRINDX(x) ((x) << S_SRINDX)
6695 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)
6696
6697 #define A_MC5_DB_SERVER_INDEX 0x714
6698 #define A_MC5_DB_LIP_RAM_ADDR 0x718
6699
6700 #define S_RAMWR 8
6701 #define V_RAMWR(x) ((x) << S_RAMWR)
6702 #define F_RAMWR V_RAMWR(1U)
6703
6704 #define S_RAMADDR 0
6705 #define M_RAMADDR 0x3f
6706 #define V_RAMADDR(x) ((x) << S_RAMADDR)
6707 #define G_RAMADDR(x) (((x) >> S_RAMADDR) & M_RAMADDR)
6708
6709 #define A_MC5_DB_LIP_RAM_DATA 0x71c
6710 #define A_MC5_DB_RSP_LATENCY 0x720
6711
6712 #define S_RDLAT 16
6713 #define M_RDLAT 0x1f
6714 #define V_RDLAT(x) ((x) << S_RDLAT)
6715 #define G_RDLAT(x) (((x) >> S_RDLAT) & M_RDLAT)
6716
6717 #define S_LRNLAT 8
6718 #define M_LRNLAT 0x1f
6719 #define V_LRNLAT(x) ((x) << S_LRNLAT)
6720 #define G_LRNLAT(x) (((x) >> S_LRNLAT) & M_LRNLAT)
6721
6722 #define S_SRCHLAT 0
6723 #define M_SRCHLAT 0x1f
6724 #define V_SRCHLAT(x) ((x) << S_SRCHLAT)
6725 #define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT)
6726
6727 #define A_MC5_DB_PARITY_LATENCY 0x724
6728
6729 #define S_PARLAT 0
6730 #define M_PARLAT 0xf
6731 #define V_PARLAT(x) ((x) << S_PARLAT)
6732 #define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT)
6733
6734 #define A_MC5_DB_WR_LRN_VERIFY 0x728
6735
6736 #define S_VWVEREN 2
6737 #define V_VWVEREN(x) ((x) << S_VWVEREN)
6738 #define F_VWVEREN V_VWVEREN(1U)
6739
6740 #define S_LRNVEREN 1
6741 #define V_LRNVEREN(x) ((x) << S_LRNVEREN)
6742 #define F_LRNVEREN V_LRNVEREN(1U)
6743
6744 #define S_POVEREN 0
6745 #define V_POVEREN(x) ((x) << S_POVEREN)
6746 #define F_POVEREN V_POVEREN(1U)
6747
6748 #define A_MC5_DB_PART_ID_INDEX 0x72c
6749
6750 #define S_IDINDEX 0
6751 #define M_IDINDEX 0xf
6752 #define V_IDINDEX(x) ((x) << S_IDINDEX)
6753 #define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX)
6754
6755 #define A_MC5_DB_RESET_MAX 0x730
6756
6757 #define S_RSTMAX 0
6758 #define M_RSTMAX 0xf
6759 #define V_RSTMAX(x) ((x) << S_RSTMAX)
6760 #define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX)
6761
6762 #define A_MC5_DB_ACT_CNT 0x734
6763
6764 #define S_ACTCNT 0
6765 #define M_ACTCNT 0xfffff
6766 #define V_ACTCNT(x) ((x) << S_ACTCNT)
6767 #define G_ACTCNT(x) (((x) >> S_ACTCNT) & M_ACTCNT)
6768
6769 #define A_MC5_DB_CLIP_MAP 0x738
6770
6771 #define S_CLIPMAPOP 31
6772 #define V_CLIPMAPOP(x) ((x) << S_CLIPMAPOP)
6773 #define F_CLIPMAPOP V_CLIPMAPOP(1U)
6774
6775 #define S_CLIPMAPVAL 16
6776 #define M_CLIPMAPVAL 0x3f
6777 #define V_CLIPMAPVAL(x) ((x) << S_CLIPMAPVAL)
6778 #define G_CLIPMAPVAL(x) (((x) >> S_CLIPMAPVAL) & M_CLIPMAPVAL)
6779
6780 #define S_CLIPMAPADDR 0
6781 #define M_CLIPMAPADDR 0x3f
6782 #define V_CLIPMAPADDR(x) ((x) << S_CLIPMAPADDR)
6783 #define G_CLIPMAPADDR(x) (((x) >> S_CLIPMAPADDR) & M_CLIPMAPADDR)
6784
6785 #define A_MC5_DB_SIZE 0x73c
6786 #define A_MC5_DB_INT_ENABLE 0x740
6787
6788 #define S_MSGSEL 28
6789 #define M_MSGSEL 0xf
6790 #define V_MSGSEL(x) ((x) << S_MSGSEL)
6791 #define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL)
6792
6793 #define S_DELACTEMPTY 18
6794 #define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY)
6795 #define F_DELACTEMPTY V_DELACTEMPTY(1U)
6796
6797 #define S_DISPQPARERR 17
6798 #define V_DISPQPARERR(x) ((x) << S_DISPQPARERR)
6799 #define F_DISPQPARERR V_DISPQPARERR(1U)
6800
6801 #define S_REQQPARERR 16
6802 #define V_REQQPARERR(x) ((x) << S_REQQPARERR)
6803 #define F_REQQPARERR V_REQQPARERR(1U)
6804
6805 #define S_UNKNOWNCMD 15
6806 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
6807 #define F_UNKNOWNCMD V_UNKNOWNCMD(1U)
6808
6809 #define S_SYNCOOKIEOFF 11
6810 #define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF)
6811 #define F_SYNCOOKIEOFF V_SYNCOOKIEOFF(1U)
6812
6813 #define S_SYNCOOKIEBAD 10
6814 #define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD)
6815 #define F_SYNCOOKIEBAD V_SYNCOOKIEBAD(1U)
6816
6817 #define S_SYNCOOKIE 9
6818 #define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE)
6819 #define F_SYNCOOKIE V_SYNCOOKIE(1U)
6820
6821 #define S_NFASRCHFAIL 8
6822 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
6823 #define F_NFASRCHFAIL V_NFASRCHFAIL(1U)
6824
6825 #define S_ACTRGNFULL 7
6826 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
6827 #define F_ACTRGNFULL V_ACTRGNFULL(1U)
6828
6829 #define S_PARITYERR 6
6830 #define V_PARITYERR(x) ((x) << S_PARITYERR)
6831 #define F_PARITYERR V_PARITYERR(1U)
6832
6833 #define S_LIPMISS 5
6834 #define V_LIPMISS(x) ((x) << S_LIPMISS)
6835 #define F_LIPMISS V_LIPMISS(1U)
6836
6837 #define S_LIP0 4
6838 #define V_LIP0(x) ((x) << S_LIP0)
6839 #define F_LIP0 V_LIP0(1U)
6840
6841 #define S_MISS 3
6842 #define V_MISS(x) ((x) << S_MISS)
6843 #define F_MISS V_MISS(1U)
6844
6845 #define S_ROUTINGHIT 2
6846 #define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT)
6847 #define F_ROUTINGHIT V_ROUTINGHIT(1U)
6848
6849 #define S_ACTIVEHIT 1
6850 #define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT)
6851 #define F_ACTIVEHIT V_ACTIVEHIT(1U)
6852
6853 #define S_ACTIVEOUTHIT 0
6854 #define V_ACTIVEOUTHIT(x) ((x) << S_ACTIVEOUTHIT)
6855 #define F_ACTIVEOUTHIT V_ACTIVEOUTHIT(1U)
6856
6857 #define A_MC5_DB_INT_CAUSE 0x744
6858 #define A_MC5_DB_INT_TID 0x748
6859
6860 #define S_INTTID 0
6861 #define M_INTTID 0xfffff
6862 #define V_INTTID(x) ((x) << S_INTTID)
6863 #define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID)
6864
6865 #define A_MC5_DB_INT_PTID 0x74c
6866
6867 #define S_INTPTID 0
6868 #define M_INTPTID 0xfffff
6869 #define V_INTPTID(x) ((x) << S_INTPTID)
6870 #define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID)
6871
6872 #define A_MC5_DB_DBGI_CONFIG 0x774
6873
6874 #define S_WRREQSIZE 22
6875 #define M_WRREQSIZE 0x3ff
6876 #define V_WRREQSIZE(x) ((x) << S_WRREQSIZE)
6877 #define G_WRREQSIZE(x) (((x) >> S_WRREQSIZE) & M_WRREQSIZE)
6878
6879 #define S_SADRSEL 4
6880 #define V_SADRSEL(x) ((x) << S_SADRSEL)
6881 #define F_SADRSEL V_SADRSEL(1U)
6882
6883 #define S_CMDMODE 0
6884 #define M_CMDMODE 0x7
6885 #define V_CMDMODE(x) ((x) << S_CMDMODE)
6886 #define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE)
6887
6888 #define A_MC5_DB_DBGI_REQ_CMD 0x778
6889
6890 #define S_MBUSCMD 0
6891 #define M_MBUSCMD 0xf
6892 #define V_MBUSCMD(x) ((x) << S_MBUSCMD)
6893 #define G_MBUSCMD(x) (((x) >> S_MBUSCMD) & M_MBUSCMD)
6894
6895 #define S_IDTCMDHI 11
6896 #define M_IDTCMDHI 0x7
6897 #define V_IDTCMDHI(x) ((x) << S_IDTCMDHI)
6898 #define G_IDTCMDHI(x) (((x) >> S_IDTCMDHI) & M_IDTCMDHI)
6899
6900 #define S_IDTCMDLO 0
6901 #define M_IDTCMDLO 0xf
6902 #define V_IDTCMDLO(x) ((x) << S_IDTCMDLO)
6903 #define G_IDTCMDLO(x) (((x) >> S_IDTCMDLO) & M_IDTCMDLO)
6904
6905 #define S_IDTCMD 0
6906 #define M_IDTCMD 0xfffff
6907 #define V_IDTCMD(x) ((x) << S_IDTCMD)
6908 #define G_IDTCMD(x) (((x) >> S_IDTCMD) & M_IDTCMD)
6909
6910 #define S_LCMDB 16
6911 #define M_LCMDB 0x7ff
6912 #define V_LCMDB(x) ((x) << S_LCMDB)
6913 #define G_LCMDB(x) (((x) >> S_LCMDB) & M_LCMDB)
6914
6915 #define S_LCMDA 0
6916 #define M_LCMDA 0x7ff
6917 #define V_LCMDA(x) ((x) << S_LCMDA)
6918 #define G_LCMDA(x) (((x) >> S_LCMDA) & M_LCMDA)
6919
6920 #define A_MC5_DB_DBGI_REQ_ADDR0 0x77c
6921 #define A_MC5_DB_DBGI_REQ_ADDR1 0x780
6922 #define A_MC5_DB_DBGI_REQ_ADDR2 0x784
6923
6924 #define S_DBGIREQADRHI 0
6925 #define M_DBGIREQADRHI 0xff
6926 #define V_DBGIREQADRHI(x) ((x) << S_DBGIREQADRHI)
6927 #define G_DBGIREQADRHI(x) (((x) >> S_DBGIREQADRHI) & M_DBGIREQADRHI)
6928
6929 #define A_MC5_DB_DBGI_REQ_DATA0 0x788
6930 #define A_MC5_DB_DBGI_REQ_DATA1 0x78c
6931 #define A_MC5_DB_DBGI_REQ_DATA2 0x790
6932 #define A_MC5_DB_DBGI_REQ_DATA3 0x794
6933 #define A_MC5_DB_DBGI_REQ_DATA4 0x798
6934
6935 #define S_DBGIREQDATA4 0
6936 #define M_DBGIREQDATA4 0xffff
6937 #define V_DBGIREQDATA4(x) ((x) << S_DBGIREQDATA4)
6938 #define G_DBGIREQDATA4(x) (((x) >> S_DBGIREQDATA4) & M_DBGIREQDATA4)
6939
6940 #define A_MC5_DB_DBGI_REQ_MASK0 0x79c
6941 #define A_MC5_DB_DBGI_REQ_MASK1 0x7a0
6942 #define A_MC5_DB_DBGI_REQ_MASK2 0x7a4
6943 #define A_MC5_DB_DBGI_REQ_MASK3 0x7a8
6944 #define A_MC5_DB_DBGI_REQ_MASK4 0x7ac
6945
6946 #define S_DBGIREQMSK4 0
6947 #define M_DBGIREQMSK4 0xffff
6948 #define V_DBGIREQMSK4(x) ((x) << S_DBGIREQMSK4)
6949 #define G_DBGIREQMSK4(x) (((x) >> S_DBGIREQMSK4) & M_DBGIREQMSK4)
6950
6951 #define A_MC5_DB_DBGI_RSP_STATUS 0x7b0
6952
6953 #define S_DBGIRSPMSG 8
6954 #define M_DBGIRSPMSG 0xf
6955 #define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG)
6956 #define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG)
6957
6958 #define S_DBGIRSPMSGVLD 2
6959 #define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD)
6960 #define F_DBGIRSPMSGVLD V_DBGIRSPMSGVLD(1U)
6961
6962 #define S_DBGIRSPHIT 1
6963 #define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT)
6964 #define F_DBGIRSPHIT V_DBGIRSPHIT(1U)
6965
6966 #define S_DBGIRSPVALID 0
6967 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
6968 #define F_DBGIRSPVALID V_DBGIRSPVALID(1U)
6969
6970 #define A_MC5_DB_DBGI_RSP_DATA0 0x7b4
6971 #define A_MC5_DB_DBGI_RSP_DATA1 0x7b8
6972 #define A_MC5_DB_DBGI_RSP_DATA2 0x7bc
6973 #define A_MC5_DB_DBGI_RSP_DATA3 0x7c0
6974 #define A_MC5_DB_DBGI_RSP_DATA4 0x7c4
6975
6976 #define S_DBGIRSPDATA3 0
6977 #define M_DBGIRSPDATA3 0xffff
6978 #define V_DBGIRSPDATA3(x) ((x) << S_DBGIRSPDATA3)
6979 #define G_DBGIRSPDATA3(x) (((x) >> S_DBGIRSPDATA3) & M_DBGIRSPDATA3)
6980
6981 #define A_MC5_DB_DBGI_RSP_LAST_CMD 0x7c8
6982
6983 #define S_LASTCMDB 16
6984 #define M_LASTCMDB 0x7ff
6985 #define V_LASTCMDB(x) ((x) << S_LASTCMDB)
6986 #define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB)
6987
6988 #define S_LASTCMDA 0
6989 #define M_LASTCMDA 0x7ff
6990 #define V_LASTCMDA(x) ((x) << S_LASTCMDA)
6991 #define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA)
6992
6993 #define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc
6994
6995 #define S_PO_DWR 0
6996 #define M_PO_DWR 0xfffff
6997 #define V_PO_DWR(x) ((x) << S_PO_DWR)
6998 #define G_PO_DWR(x) (((x) >> S_PO_DWR) & M_PO_DWR)
6999
7000 #define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0
7001
7002 #define S_PO_MWR 0
7003 #define M_PO_MWR 0xfffff
7004 #define V_PO_MWR(x) ((x) << S_PO_MWR)
7005 #define G_PO_MWR(x) (((x) >> S_PO_MWR) & M_PO_MWR)
7006
7007 #define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4
7008
7009 #define S_AO_SRCH 0
7010 #define M_AO_SRCH 0xfffff
7011 #define V_AO_SRCH(x) ((x) << S_AO_SRCH)
7012 #define G_AO_SRCH(x) (((x) >> S_AO_SRCH) & M_AO_SRCH)
7013
7014 #define A_MC5_DB_AOPEN_LRN_CMD 0x7d8
7015
7016 #define S_AO_LRN 0
7017 #define M_AO_LRN 0xfffff
7018 #define V_AO_LRN(x) ((x) << S_AO_LRN)
7019 #define G_AO_LRN(x) (((x) >> S_AO_LRN) & M_AO_LRN)
7020
7021 #define A_MC5_DB_SYN_SRCH_CMD 0x7dc
7022
7023 #define S_SYN_SRCH 0
7024 #define M_SYN_SRCH 0xfffff
7025 #define V_SYN_SRCH(x) ((x) << S_SYN_SRCH)
7026 #define G_SYN_SRCH(x) (((x) >> S_SYN_SRCH) & M_SYN_SRCH)
7027
7028 #define A_MC5_DB_SYN_LRN_CMD 0x7e0
7029
7030 #define S_SYN_LRN 0
7031 #define M_SYN_LRN 0xfffff
7032 #define V_SYN_LRN(x) ((x) << S_SYN_LRN)
7033 #define G_SYN_LRN(x) (((x) >> S_SYN_LRN) & M_SYN_LRN)
7034
7035 #define A_MC5_DB_ACK_SRCH_CMD 0x7e4
7036
7037 #define S_ACK_SRCH 0
7038 #define M_ACK_SRCH 0xfffff
7039 #define V_ACK_SRCH(x) ((x) << S_ACK_SRCH)
7040 #define G_ACK_SRCH(x) (((x) >> S_ACK_SRCH) & M_ACK_SRCH)
7041
7042 #define A_MC5_DB_ACK_LRN_CMD 0x7e8
7043
7044 #define S_ACK_LRN 0
7045 #define M_ACK_LRN 0xfffff
7046 #define V_ACK_LRN(x) ((x) << S_ACK_LRN)
7047 #define G_ACK_LRN(x) (((x) >> S_ACK_LRN) & M_ACK_LRN)
7048
7049 #define A_MC5_DB_ILOOKUP_CMD 0x7ec
7050
7051 #define S_I_SRCH 0
7052 #define M_I_SRCH 0xfffff
7053 #define V_I_SRCH(x) ((x) << S_I_SRCH)
7054 #define G_I_SRCH(x) (((x) >> S_I_SRCH) & M_I_SRCH)
7055
7056 #define A_MC5_DB_ELOOKUP_CMD 0x7f0
7057
7058 #define S_E_SRCH 0
7059 #define M_E_SRCH 0xfffff
7060 #define V_E_SRCH(x) ((x) << S_E_SRCH)
7061 #define G_E_SRCH(x) (((x) >> S_E_SRCH) & M_E_SRCH)
7062
7063 #define A_MC5_DB_DATA_WRITE_CMD 0x7f4
7064
7065 #define S_WRITE 0
7066 #define M_WRITE 0xfffff
7067 #define V_WRITE(x) ((x) << S_WRITE)
7068 #define G_WRITE(x) (((x) >> S_WRITE) & M_WRITE)
7069
7070 #define A_MC5_DB_DATA_READ_CMD 0x7f8
7071
7072 #define S_READCMD 0
7073 #define M_READCMD 0xfffff
7074 #define V_READCMD(x) ((x) << S_READCMD)
7075 #define G_READCMD(x) (((x) >> S_READCMD) & M_READCMD)
7076
7077 #define A_MC5_DB_MASK_WRITE_CMD 0x7fc
7078
7079 #define S_MASKWR 0
7080 #define M_MASKWR 0xffff
7081 #define V_MASKWR(x) ((x) << S_MASKWR)
7082 #define G_MASKWR(x) (((x) >> S_MASKWR) & M_MASKWR)
7083
7084 /* registers for module XGMAC0_0 */
7085 #define XGMAC0_0_BASE_ADDR 0x800
7086
7087 #define A_XGM_TX_CTRL 0x800
7088
7089 #define S_SENDPAUSE 2
7090 #define V_SENDPAUSE(x) ((x) << S_SENDPAUSE)
7091 #define F_SENDPAUSE V_SENDPAUSE(1U)
7092
7093 #define S_SENDZEROPAUSE 1
7094 #define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE)
7095 #define F_SENDZEROPAUSE V_SENDZEROPAUSE(1U)
7096
7097 #define S_TXEN 0
7098 #define V_TXEN(x) ((x) << S_TXEN)
7099 #define F_TXEN V_TXEN(1U)
7100
7101 #define A_XGM_TX_CFG 0x804
7102
7103 #define S_CFGCLKSPEED 2
7104 #define M_CFGCLKSPEED 0x7
7105 #define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED)
7106 #define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED)
7107
7108 #define S_STRETCHMODE 1
7109 #define V_STRETCHMODE(x) ((x) << S_STRETCHMODE)
7110 #define F_STRETCHMODE V_STRETCHMODE(1U)
7111
7112 #define S_TXPAUSEEN 0
7113 #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
7114 #define F_TXPAUSEEN V_TXPAUSEEN(1U)
7115
7116 #define A_XGM_TX_PAUSE_QUANTA 0x808
7117
7118 #define S_TXPAUSEQUANTA 0
7119 #define M_TXPAUSEQUANTA 0xffff
7120 #define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA)
7121 #define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA)
7122
7123 #define A_XGM_RX_CTRL 0x80c
7124
7125 #define S_RXEN 0
7126 #define V_RXEN(x) ((x) << S_RXEN)
7127 #define F_RXEN V_RXEN(1U)
7128
7129 #define A_XGM_RX_CFG 0x810
7130
7131 #define S_CON802_3PREAMBLE 12
7132 #define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE)
7133 #define F_CON802_3PREAMBLE V_CON802_3PREAMBLE(1U)
7134
7135 #define S_ENNON802_3PREAMBLE 11
7136 #define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE)
7137 #define F_ENNON802_3PREAMBLE V_ENNON802_3PREAMBLE(1U)
7138
7139 #define S_COPYPREAMBLE 10
7140 #define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE)
7141 #define F_COPYPREAMBLE V_COPYPREAMBLE(1U)
7142
7143 #define S_DISPAUSEFRAMES 9
7144 #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
7145 #define F_DISPAUSEFRAMES V_DISPAUSEFRAMES(1U)
7146
7147 #define S_EN1536BFRAMES 8
7148 #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
7149 #define F_EN1536BFRAMES V_EN1536BFRAMES(1U)
7150
7151 #define S_ENJUMBO 7
7152 #define V_ENJUMBO(x) ((x) << S_ENJUMBO)
7153 #define F_ENJUMBO V_ENJUMBO(1U)
7154
7155 #define S_RMFCS 6
7156 #define V_RMFCS(x) ((x) << S_RMFCS)
7157 #define F_RMFCS V_RMFCS(1U)
7158
7159 #define S_DISNONVLAN 5
7160 #define V_DISNONVLAN(x) ((x) << S_DISNONVLAN)
7161 #define F_DISNONVLAN V_DISNONVLAN(1U)
7162
7163 #define S_ENEXTMATCH 4
7164 #define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH)
7165 #define F_ENEXTMATCH V_ENEXTMATCH(1U)
7166
7167 #define S_ENHASHUCAST 3
7168 #define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST)
7169 #define F_ENHASHUCAST V_ENHASHUCAST(1U)
7170
7171 #define S_ENHASHMCAST 2
7172 #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
7173 #define F_ENHASHMCAST V_ENHASHMCAST(1U)
7174
7175 #define S_DISBCAST 1
7176 #define V_DISBCAST(x) ((x) << S_DISBCAST)
7177 #define F_DISBCAST V_DISBCAST(1U)
7178
7179 #define S_COPYALLFRAMES 0
7180 #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
7181 #define F_COPYALLFRAMES V_COPYALLFRAMES(1U)
7182
7183 #define A_XGM_RX_HASH_LOW 0x814
7184 #define A_XGM_RX_HASH_HIGH 0x818
7185 #define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c
7186 #define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820
7187
7188 #define S_ADDRESS_HIGH 0
7189 #define M_ADDRESS_HIGH 0xffff
7190 #define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH)
7191 #define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH)
7192
7193 #define A_XGM_RX_EXACT_MATCH_LOW_2 0x824
7194 #define A_XGM_RX_EXACT_MATCH_HIGH_2 0x828
7195 #define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c
7196 #define A_XGM_RX_EXACT_MATCH_HIGH_3 0x830
7197 #define A_XGM_RX_EXACT_MATCH_LOW_4 0x834
7198 #define A_XGM_RX_EXACT_MATCH_HIGH_4 0x838
7199 #define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c
7200 #define A_XGM_RX_EXACT_MATCH_HIGH_5 0x840
7201 #define A_XGM_RX_EXACT_MATCH_LOW_6 0x844
7202 #define A_XGM_RX_EXACT_MATCH_HIGH_6 0x848
7203 #define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c
7204 #define A_XGM_RX_EXACT_MATCH_HIGH_7 0x850
7205 #define A_XGM_RX_EXACT_MATCH_LOW_8 0x854
7206 #define A_XGM_RX_EXACT_MATCH_HIGH_8 0x858
7207 #define A_XGM_RX_TYPE_MATCH_1 0x85c
7208
7209 #define S_ENTYPEMATCH 31
7210 #define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH)
7211 #define F_ENTYPEMATCH V_ENTYPEMATCH(1U)
7212
7213 #define S_TYPE 0
7214 #define M_TYPE 0xffff
7215 #define V_TYPE(x) ((x) << S_TYPE)
7216 #define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE)
7217
7218 #define A_XGM_RX_TYPE_MATCH_2 0x860
7219 #define A_XGM_RX_TYPE_MATCH_3 0x864
7220 #define A_XGM_RX_TYPE_MATCH_4 0x868
7221 #define A_XGM_INT_STATUS 0x86c
7222
7223 #define S_XGMIIEXTINT 10
7224 #define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT)
7225 #define F_XGMIIEXTINT V_XGMIIEXTINT(1U)
7226
7227 #define S_LINKFAULTCHANGE 9
7228 #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE)
7229 #define F_LINKFAULTCHANGE V_LINKFAULTCHANGE(1U)
7230
7231 #define S_PHYFRAMECOMPLETE 8
7232 #define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE)
7233 #define F_PHYFRAMECOMPLETE V_PHYFRAMECOMPLETE(1U)
7234
7235 #define S_PAUSEFRAMETXMT 7
7236 #define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT)
7237 #define F_PAUSEFRAMETXMT V_PAUSEFRAMETXMT(1U)
7238
7239 #define S_PAUSECNTRTIMEOUT 6
7240 #define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT)
7241 #define F_PAUSECNTRTIMEOUT V_PAUSECNTRTIMEOUT(1U)
7242
7243 #define S_NON0PAUSERCVD 5
7244 #define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD)
7245 #define F_NON0PAUSERCVD V_NON0PAUSERCVD(1U)
7246
7247 #define S_STATOFLOW 4
7248 #define V_STATOFLOW(x) ((x) << S_STATOFLOW)
7249 #define F_STATOFLOW V_STATOFLOW(1U)
7250
7251 #define S_TXERRFIFO 3
7252 #define V_TXERRFIFO(x) ((x) << S_TXERRFIFO)
7253 #define F_TXERRFIFO V_TXERRFIFO(1U)
7254
7255 #define S_TXUFLOW 2
7256 #define V_TXUFLOW(x) ((x) << S_TXUFLOW)
7257 #define F_TXUFLOW V_TXUFLOW(1U)
7258
7259 #define S_FRAMETXMT 1
7260 #define V_FRAMETXMT(x) ((x) << S_FRAMETXMT)
7261 #define F_FRAMETXMT V_FRAMETXMT(1U)
7262
7263 #define S_FRAMERCVD 0
7264 #define V_FRAMERCVD(x) ((x) << S_FRAMERCVD)
7265 #define F_FRAMERCVD V_FRAMERCVD(1U)
7266
7267 #define A_XGM_XGM_INT_MASK 0x870
7268 #define A_XGM_XGM_INT_ENABLE 0x874
7269 #define A_XGM_XGM_INT_DISABLE 0x878
7270 #define A_XGM_TX_PAUSE_TIMER 0x87c
7271
7272 #define S_CURPAUSETIMER 0
7273 #define M_CURPAUSETIMER 0xffff
7274 #define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER)
7275 #define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER)
7276
7277 #define A_XGM_STAT_CTRL 0x880
7278
7279 #define S_READSNPSHOT 4
7280 #define V_READSNPSHOT(x) ((x) << S_READSNPSHOT)
7281 #define F_READSNPSHOT V_READSNPSHOT(1U)
7282
7283 #define S_TAKESNPSHOT 3
7284 #define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT)
7285 #define F_TAKESNPSHOT V_TAKESNPSHOT(1U)
7286
7287 #define S_CLRSTATS 2
7288 #define V_CLRSTATS(x) ((x) << S_CLRSTATS)
7289 #define F_CLRSTATS V_CLRSTATS(1U)
7290
7291 #define S_INCRSTATS 1
7292 #define V_INCRSTATS(x) ((x) << S_INCRSTATS)
7293 #define F_INCRSTATS V_INCRSTATS(1U)
7294
7295 #define S_ENTESTMODEWR 0
7296 #define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR)
7297 #define F_ENTESTMODEWR V_ENTESTMODEWR(1U)
7298
7299 #define A_XGM_RXFIFO_CFG 0x884
7300
7301 #define S_RXFIFO_EMPTY 31
7302 #define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY)
7303 #define F_RXFIFO_EMPTY V_RXFIFO_EMPTY(1U)
7304
7305 #define S_RXFIFO_FULL 30
7306 #define V_RXFIFO_FULL(x) ((x) << S_RXFIFO_FULL)
7307 #define F_RXFIFO_FULL V_RXFIFO_FULL(1U)
7308
7309 #define S_RXFIFOPAUSEHWM 17
7310 #define M_RXFIFOPAUSEHWM 0xfff
7311 #define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM)
7312 #define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM)
7313
7314 #define S_RXFIFOPAUSELWM 5
7315 #define M_RXFIFOPAUSELWM 0xfff
7316 #define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM)
7317 #define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM)
7318
7319 #define S_FORCEDPAUSE 4
7320 #define V_FORCEDPAUSE(x) ((x) << S_FORCEDPAUSE)
7321 #define F_FORCEDPAUSE V_FORCEDPAUSE(1U)
7322
7323 #define S_EXTERNLOOPBACK 3
7324 #define V_EXTERNLOOPBACK(x) ((x) << S_EXTERNLOOPBACK)
7325 #define F_EXTERNLOOPBACK V_EXTERNLOOPBACK(1U)
7326
7327 #define S_RXBYTESWAP 2
7328 #define V_RXBYTESWAP(x) ((x) << S_RXBYTESWAP)
7329 #define F_RXBYTESWAP V_RXBYTESWAP(1U)
7330
7331 #define S_RXSTRFRWRD 1
7332 #define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD)
7333 #define F_RXSTRFRWRD V_RXSTRFRWRD(1U)
7334
7335 #define S_DISERRFRAMES 0
7336 #define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES)
7337 #define F_DISERRFRAMES V_DISERRFRAMES(1U)
7338
7339 #define A_XGM_TXFIFO_CFG 0x888
7340
7341 #define S_TXFIFO_EMPTY 31
7342 #define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY)
7343 #define F_TXFIFO_EMPTY V_TXFIFO_EMPTY(1U)
7344
7345 #define S_TXFIFO_FULL 30
7346 #define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL)
7347 #define F_TXFIFO_FULL V_TXFIFO_FULL(1U)
7348
7349 #define S_UNDERUNFIX 22
7350 #define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX)
7351 #define F_UNDERUNFIX V_UNDERUNFIX(1U)
7352
7353 #define S_ENDROPPKT 21
7354 #define V_ENDROPPKT(x) ((x) << S_ENDROPPKT)
7355 #define F_ENDROPPKT V_ENDROPPKT(1U)
7356
7357 #define S_TXIPG 13
7358 #define M_TXIPG 0xff
7359 #define V_TXIPG(x) ((x) << S_TXIPG)
7360 #define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
7361
7362 #define S_TXFIFOTHRESH 4
7363 #define M_TXFIFOTHRESH 0x1ff
7364 #define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH)
7365 #define G_TXFIFOTHRESH(x) (((x) >> S_TXFIFOTHRESH) & M_TXFIFOTHRESH)
7366
7367 #define S_INTERNLOOPBACK 3
7368 #define V_INTERNLOOPBACK(x) ((x) << S_INTERNLOOPBACK)
7369 #define F_INTERNLOOPBACK V_INTERNLOOPBACK(1U)
7370
7371 #define S_TXBYTESWAP 2
7372 #define V_TXBYTESWAP(x) ((x) << S_TXBYTESWAP)
7373 #define F_TXBYTESWAP V_TXBYTESWAP(1U)
7374
7375 #define S_DISCRC 1
7376 #define V_DISCRC(x) ((x) << S_DISCRC)
7377 #define F_DISCRC V_DISCRC(1U)
7378
7379 #define S_DISPREAMBLE 0
7380 #define V_DISPREAMBLE(x) ((x) << S_DISPREAMBLE)
7381 #define F_DISPREAMBLE V_DISPREAMBLE(1U)
7382
7383 #define A_XGM_SLOW_TIMER 0x88c
7384
7385 #define S_PAUSESLOWTIMEREN 31
7386 #define V_PAUSESLOWTIMEREN(x) ((x) << S_PAUSESLOWTIMEREN)
7387 #define F_PAUSESLOWTIMEREN V_PAUSESLOWTIMEREN(1U)
7388
7389 #define S_PAUSESLOWTIMER 0
7390 #define M_PAUSESLOWTIMER 0xfffff
7391 #define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER)
7392 #define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER)
7393
7394 #define A_XGM_PAUSE_TIMER 0x890
7395
7396 #define S_PAUSETIMER 0
7397 #define M_PAUSETIMER 0xfffff
7398 #define V_PAUSETIMER(x) ((x) << S_PAUSETIMER)
7399 #define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER)
7400
7401 #define A_XGM_SERDES_CTRL 0x890
7402
7403 #define S_SERDESEN 25
7404 #define V_SERDESEN(x) ((x) << S_SERDESEN)
7405 #define F_SERDESEN V_SERDESEN(1U)
7406
7407 #define S_SERDESRESET_ 24
7408 #define V_SERDESRESET_(x) ((x) << S_SERDESRESET_)
7409 #define F_SERDESRESET_ V_SERDESRESET_(1U)
7410
7411 #define S_CMURANGE 21
7412 #define M_CMURANGE 0x7
7413 #define V_CMURANGE(x) ((x) << S_CMURANGE)
7414 #define G_CMURANGE(x) (((x) >> S_CMURANGE) & M_CMURANGE)
7415
7416 #define S_BGENB 20
7417 #define V_BGENB(x) ((x) << S_BGENB)
7418 #define F_BGENB V_BGENB(1U)
7419
7420 #define S_ENSKPDROP 19
7421 #define V_ENSKPDROP(x) ((x) << S_ENSKPDROP)
7422 #define F_ENSKPDROP V_ENSKPDROP(1U)
7423
7424 #define S_ENCOMMA 18
7425 #define V_ENCOMMA(x) ((x) << S_ENCOMMA)
7426 #define F_ENCOMMA V_ENCOMMA(1U)
7427
7428 #define S_EN8B10B 17
7429 #define V_EN8B10B(x) ((x) << S_EN8B10B)
7430 #define F_EN8B10B V_EN8B10B(1U)
7431
7432 #define S_ENELBUF 16
7433 #define V_ENELBUF(x) ((x) << S_ENELBUF)
7434 #define F_ENELBUF V_ENELBUF(1U)
7435
7436 #define S_GAIN 11
7437 #define M_GAIN 0x1f
7438 #define V_GAIN(x) ((x) << S_GAIN)
7439 #define G_GAIN(x) (((x) >> S_GAIN) & M_GAIN)
7440
7441 #define S_BANDGAP 7
7442 #define M_BANDGAP 0xf
7443 #define V_BANDGAP(x) ((x) << S_BANDGAP)
7444 #define G_BANDGAP(x) (((x) >> S_BANDGAP) & M_BANDGAP)
7445
7446 #define S_LPBKEN 5
7447 #define M_LPBKEN 0x3
7448 #define V_LPBKEN(x) ((x) << S_LPBKEN)
7449 #define G_LPBKEN(x) (((x) >> S_LPBKEN) & M_LPBKEN)
7450
7451 #define S_RXENABLE 4
7452 #define V_RXENABLE(x) ((x) << S_RXENABLE)
7453 #define F_RXENABLE V_RXENABLE(1U)
7454
7455 #define S_TXENABLE 3
7456 #define V_TXENABLE(x) ((x) << S_TXENABLE)
7457 #define F_TXENABLE V_TXENABLE(1U)
7458
7459 #define A_XGM_XAUI_PCS_TEST 0x894
7460
7461 #define S_TESTPATTERN 1
7462 #define M_TESTPATTERN 0x3
7463 #define V_TESTPATTERN(x) ((x) << S_TESTPATTERN)
7464 #define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN)
7465
7466 #define S_ENTEST 0
7467 #define V_ENTEST(x) ((x) << S_ENTEST)
7468 #define F_ENTEST V_ENTEST(1U)
7469
7470 #define A_XGM_RGMII_CTRL 0x898
7471
7472 #define S_PHALIGNFIFOTHRESH 1
7473 #define M_PHALIGNFIFOTHRESH 0x3
7474 #define V_PHALIGNFIFOTHRESH(x) ((x) << S_PHALIGNFIFOTHRESH)
7475 #define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH)
7476
7477 #define S_TXCLK90SHIFT 0
7478 #define V_TXCLK90SHIFT(x) ((x) << S_TXCLK90SHIFT)
7479 #define F_TXCLK90SHIFT V_TXCLK90SHIFT(1U)
7480
7481 #define A_XGM_RGMII_IMP 0x89c
7482
7483 #define S_CALRESET 8
7484 #define V_CALRESET(x) ((x) << S_CALRESET)
7485 #define F_CALRESET V_CALRESET(1U)
7486
7487 #define S_CALUPDATE 7
7488 #define V_CALUPDATE(x) ((x) << S_CALUPDATE)
7489 #define F_CALUPDATE V_CALUPDATE(1U)
7490
7491 #define S_XGM_IMPSETUPDATE 6
7492 #define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE)
7493 #define F_XGM_IMPSETUPDATE V_XGM_IMPSETUPDATE(1U)
7494
7495 #define S_RGMIIIMPPD 3
7496 #define M_RGMIIIMPPD 0x7
7497 #define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD)
7498 #define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD)
7499
7500 #define S_RGMIIIMPPU 0
7501 #define M_RGMIIIMPPU 0x7
7502 #define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU)
7503 #define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU)
7504
7505 #define A_XGM_XAUI_IMP 0x8a0
7506
7507 #define S_XGM_CALFAULT 29
7508 #define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT)
7509 #define F_XGM_CALFAULT V_XGM_CALFAULT(1U)
7510
7511 #define S_CALIMP 24
7512 #define M_CALIMP 0x1f
7513 #define V_CALIMP(x) ((x) << S_CALIMP)
7514 #define G_CALIMP(x) (((x) >> S_CALIMP) & M_CALIMP)
7515
7516 #define S_XAUIIMP 0
7517 #define M_XAUIIMP 0x7
7518 #define V_XAUIIMP(x) ((x) << S_XAUIIMP)
7519 #define G_XAUIIMP(x) (((x) >> S_XAUIIMP) & M_XAUIIMP)
7520
7521 #define A_XGM_SERDES_BIST 0x8a4
7522
7523 #define S_BISTDONE 28
7524 #define M_BISTDONE 0xf
7525 #define V_BISTDONE(x) ((x) << S_BISTDONE)
7526 #define G_BISTDONE(x) (((x) >> S_BISTDONE) & M_BISTDONE)
7527
7528 #define S_BISTCYCLETHRESH 3
7529 #define M_BISTCYCLETHRESH 0x1ffff
7530 #define V_BISTCYCLETHRESH(x) ((x) << S_BISTCYCLETHRESH)
7531 #define G_BISTCYCLETHRESH(x) (((x) >> S_BISTCYCLETHRESH) & M_BISTCYCLETHRESH)
7532
7533 #define A_XGM_RX_MAX_PKT_SIZE 0x8a8
7534
7535 #define S_RXMAXFRAMERSIZE 17
7536 #define M_RXMAXFRAMERSIZE 0x3fff
7537 #define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE)
7538 #define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE)
7539
7540 #define S_RXENERRORGATHER 16
7541 #define V_RXENERRORGATHER(x) ((x) << S_RXENERRORGATHER)
7542 #define F_RXENERRORGATHER V_RXENERRORGATHER(1U)
7543
7544 #define S_RXENSINGLEFLIT 15
7545 #define V_RXENSINGLEFLIT(x) ((x) << S_RXENSINGLEFLIT)
7546 #define F_RXENSINGLEFLIT V_RXENSINGLEFLIT(1U)
7547
7548 #define S_RXENFRAMER 14
7549 #define V_RXENFRAMER(x) ((x) << S_RXENFRAMER)
7550 #define F_RXENFRAMER V_RXENFRAMER(1U)
7551
7552 #define S_RXMAXPKTSIZE 0
7553 #define M_RXMAXPKTSIZE 0x3fff
7554 #define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE)
7555 #define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE)
7556
7557 #define A_XGM_RESET_CTRL 0x8ac
7558
7559 #define S_XGMAC_STOP_EN 4
7560 #define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN)
7561 #define F_XGMAC_STOP_EN V_XGMAC_STOP_EN(1U)
7562
7563 #define S_XG2G_RESET_ 3
7564 #define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_)
7565 #define F_XG2G_RESET_ V_XG2G_RESET_(1U)
7566
7567 #define S_RGMII_RESET_ 2
7568 #define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_)
7569 #define F_RGMII_RESET_ V_RGMII_RESET_(1U)
7570
7571 #define S_PCS_RESET_ 1
7572 #define V_PCS_RESET_(x) ((x) << S_PCS_RESET_)
7573 #define F_PCS_RESET_ V_PCS_RESET_(1U)
7574
7575 #define S_MAC_RESET_ 0
7576 #define V_MAC_RESET_(x) ((x) << S_MAC_RESET_)
7577 #define F_MAC_RESET_ V_MAC_RESET_(1U)
7578
7579 #define A_XGM_XAUI1G_CTRL 0x8b0
7580
7581 #define S_XAUI1GLINKID 0
7582 #define M_XAUI1GLINKID 0x3
7583 #define V_XAUI1GLINKID(x) ((x) << S_XAUI1GLINKID)
7584 #define G_XAUI1GLINKID(x) (((x) >> S_XAUI1GLINKID) & M_XAUI1GLINKID)
7585
7586 #define A_XGM_SERDES_LANE_CTRL 0x8b4
7587
7588 #define S_LANEREVERSAL 8
7589 #define V_LANEREVERSAL(x) ((x) << S_LANEREVERSAL)
7590 #define F_LANEREVERSAL V_LANEREVERSAL(1U)
7591
7592 #define S_TXPOLARITY 4
7593 #define M_TXPOLARITY 0xf
7594 #define V_TXPOLARITY(x) ((x) << S_TXPOLARITY)
7595 #define G_TXPOLARITY(x) (((x) >> S_TXPOLARITY) & M_TXPOLARITY)
7596
7597 #define S_RXPOLARITY 0
7598 #define M_RXPOLARITY 0xf
7599 #define V_RXPOLARITY(x) ((x) << S_RXPOLARITY)
7600 #define G_RXPOLARITY(x) (((x) >> S_RXPOLARITY) & M_RXPOLARITY)
7601
7602 #define A_XGM_PORT_CFG 0x8b8
7603
7604 #define S_SAFESPEEDCHANGE 4
7605 #define V_SAFESPEEDCHANGE(x) ((x) << S_SAFESPEEDCHANGE)
7606 #define F_SAFESPEEDCHANGE V_SAFESPEEDCHANGE(1U)
7607
7608 #define S_CLKDIVRESET_ 3
7609 #define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_)
7610 #define F_CLKDIVRESET_ V_CLKDIVRESET_(1U)
7611
7612 #define S_PORTSPEED 1
7613 #define M_PORTSPEED 0x3
7614 #define V_PORTSPEED(x) ((x) << S_PORTSPEED)
7615 #define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)
7616
7617 #define S_ENRGMII 0
7618 #define V_ENRGMII(x) ((x) << S_ENRGMII)
7619 #define F_ENRGMII V_ENRGMII(1U)
7620
7621 #define A_XGM_EPIO_DATA0 0x8c0
7622 #define A_XGM_EPIO_DATA1 0x8c4
7623 #define A_XGM_EPIO_DATA2 0x8c8
7624 #define A_XGM_EPIO_DATA3 0x8cc
7625 #define A_XGM_EPIO_OP 0x8d0
7626
7627 #define S_PIO_READY 31
7628 #define V_PIO_READY(x) ((x) << S_PIO_READY)
7629 #define F_PIO_READY V_PIO_READY(1U)
7630
7631 #define S_PIO_WRRD 24
7632 #define V_PIO_WRRD(x) ((x) << S_PIO_WRRD)
7633 #define F_PIO_WRRD V_PIO_WRRD(1U)
7634
7635 #define S_PIO_ADDRESS 0
7636 #define M_PIO_ADDRESS 0xff
7637 #define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS)
7638 #define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS)
7639
7640 #define A_XGM_INT_ENABLE 0x8d4
7641
7642 #define S_XAUIPCSDECERR 24
7643 #define V_XAUIPCSDECERR(x) ((x) << S_XAUIPCSDECERR)
7644 #define F_XAUIPCSDECERR V_XAUIPCSDECERR(1U)
7645
7646 #define S_RGMIIRXFIFOOVERFLOW 23
7647 #define V_RGMIIRXFIFOOVERFLOW(x) ((x) << S_RGMIIRXFIFOOVERFLOW)
7648 #define F_RGMIIRXFIFOOVERFLOW V_RGMIIRXFIFOOVERFLOW(1U)
7649
7650 #define S_RGMIIRXFIFOUNDERFLOW 22
7651 #define V_RGMIIRXFIFOUNDERFLOW(x) ((x) << S_RGMIIRXFIFOUNDERFLOW)
7652 #define F_RGMIIRXFIFOUNDERFLOW V_RGMIIRXFIFOUNDERFLOW(1U)
7653
7654 #define S_RXPKTSIZEERROR 21
7655 #define V_RXPKTSIZEERROR(x) ((x) << S_RXPKTSIZEERROR)
7656 #define F_RXPKTSIZEERROR V_RXPKTSIZEERROR(1U)
7657
7658 #define S_WOLPATDETECTED 20
7659 #define V_WOLPATDETECTED(x) ((x) << S_WOLPATDETECTED)
7660 #define F_WOLPATDETECTED V_WOLPATDETECTED(1U)
7661
7662 #define S_TXFIFO_PRTY_ERR 17
7663 #define M_TXFIFO_PRTY_ERR 0x7
7664 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
7665 #define G_TXFIFO_PRTY_ERR(x) (((x) >> S_TXFIFO_PRTY_ERR) & M_TXFIFO_PRTY_ERR)
7666
7667 #define S_RXFIFO_PRTY_ERR 14
7668 #define M_RXFIFO_PRTY_ERR 0x7
7669 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
7670 #define G_RXFIFO_PRTY_ERR(x) (((x) >> S_RXFIFO_PRTY_ERR) & M_RXFIFO_PRTY_ERR)
7671
7672 #define S_TXFIFO_UNDERRUN 13
7673 #define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN)
7674 #define F_TXFIFO_UNDERRUN V_TXFIFO_UNDERRUN(1U)
7675
7676 #define S_RXFIFO_OVERFLOW 12
7677 #define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW)
7678 #define F_RXFIFO_OVERFLOW V_RXFIFO_OVERFLOW(1U)
7679
7680 #define S_SERDESBISTERR 8
7681 #define M_SERDESBISTERR 0xf
7682 #define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR)
7683 #define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR)
7684
7685 #define S_SERDESLOWSIGCHANGE 4
7686 #define M_SERDESLOWSIGCHANGE 0xf
7687 #define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE)
7688 #define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE)
7689
7690 #define S_XAUIPCSCTCERR 3
7691 #define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR)
7692 #define F_XAUIPCSCTCERR V_XAUIPCSCTCERR(1U)
7693
7694 #define S_XAUIPCSALIGNCHANGE 2
7695 #define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE)
7696 #define F_XAUIPCSALIGNCHANGE V_XAUIPCSALIGNCHANGE(1U)
7697
7698 #define S_RGMIILINKSTSCHANGE 1
7699 #define V_RGMIILINKSTSCHANGE(x) ((x) << S_RGMIILINKSTSCHANGE)
7700 #define F_RGMIILINKSTSCHANGE V_RGMIILINKSTSCHANGE(1U)
7701
7702 #define S_XGM_INT 0
7703 #define V_XGM_INT(x) ((x) << S_XGM_INT)
7704 #define F_XGM_INT V_XGM_INT(1U)
7705
7706 #define S_SERDESCMULOCK_LOSS 24
7707 #define V_SERDESCMULOCK_LOSS(x) ((x) << S_SERDESCMULOCK_LOSS)
7708 #define F_SERDESCMULOCK_LOSS V_SERDESCMULOCK_LOSS(1U)
7709
7710 #define S_SERDESBIST_ERR 8
7711 #define M_SERDESBIST_ERR 0xf
7712 #define V_SERDESBIST_ERR(x) ((x) << S_SERDESBIST_ERR)
7713 #define G_SERDESBIST_ERR(x) (((x) >> S_SERDESBIST_ERR) & M_SERDESBIST_ERR)
7714
7715 #define S_SERDES_LOS 4
7716 #define M_SERDES_LOS 0xf
7717 #define V_SERDES_LOS(x) ((x) << S_SERDES_LOS)
7718 #define G_SERDES_LOS(x) (((x) >> S_SERDES_LOS) & M_SERDES_LOS)
7719
7720 #define A_XGM_INT_CAUSE 0x8d8
7721 #define A_XGM_XAUI_ACT_CTRL 0x8dc
7722
7723 #define S_TXACTENABLE 1
7724 #define V_TXACTENABLE(x) ((x) << S_TXACTENABLE)
7725 #define F_TXACTENABLE V_TXACTENABLE(1U)
7726
7727 #define A_XGM_SERDES_CTRL0 0x8e0
7728
7729 #define S_INTSERLPBK3 27
7730 #define V_INTSERLPBK3(x) ((x) << S_INTSERLPBK3)
7731 #define F_INTSERLPBK3 V_INTSERLPBK3(1U)
7732
7733 #define S_INTSERLPBK2 26
7734 #define V_INTSERLPBK2(x) ((x) << S_INTSERLPBK2)
7735 #define F_INTSERLPBK2 V_INTSERLPBK2(1U)
7736
7737 #define S_INTSERLPBK1 25
7738 #define V_INTSERLPBK1(x) ((x) << S_INTSERLPBK1)
7739 #define F_INTSERLPBK1 V_INTSERLPBK1(1U)
7740
7741 #define S_INTSERLPBK0 24
7742 #define V_INTSERLPBK0(x) ((x) << S_INTSERLPBK0)
7743 #define F_INTSERLPBK0 V_INTSERLPBK0(1U)
7744
7745 #define S_RESET3 23
7746 #define V_RESET3(x) ((x) << S_RESET3)
7747 #define F_RESET3 V_RESET3(1U)
7748
7749 #define S_RESET2 22
7750 #define V_RESET2(x) ((x) << S_RESET2)
7751 #define F_RESET2 V_RESET2(1U)
7752
7753 #define S_RESET1 21
7754 #define V_RESET1(x) ((x) << S_RESET1)
7755 #define F_RESET1 V_RESET1(1U)
7756
7757 #define S_RESET0 20
7758 #define V_RESET0(x) ((x) << S_RESET0)
7759 #define F_RESET0 V_RESET0(1U)
7760
7761 #define S_PWRDN3 19
7762 #define V_PWRDN3(x) ((x) << S_PWRDN3)
7763 #define F_PWRDN3 V_PWRDN3(1U)
7764
7765 #define S_PWRDN2 18
7766 #define V_PWRDN2(x) ((x) << S_PWRDN2)
7767 #define F_PWRDN2 V_PWRDN2(1U)
7768
7769 #define S_PWRDN1 17
7770 #define V_PWRDN1(x) ((x) << S_PWRDN1)
7771 #define F_PWRDN1 V_PWRDN1(1U)
7772
7773 #define S_PWRDN0 16
7774 #define V_PWRDN0(x) ((x) << S_PWRDN0)
7775 #define F_PWRDN0 V_PWRDN0(1U)
7776
7777 #define S_RESETPLL23 15
7778 #define V_RESETPLL23(x) ((x) << S_RESETPLL23)
7779 #define F_RESETPLL23 V_RESETPLL23(1U)
7780
7781 #define S_RESETPLL01 14
7782 #define V_RESETPLL01(x) ((x) << S_RESETPLL01)
7783 #define F_RESETPLL01 V_RESETPLL01(1U)
7784
7785 #define S_PW23 12
7786 #define M_PW23 0x3
7787 #define V_PW23(x) ((x) << S_PW23)
7788 #define G_PW23(x) (((x) >> S_PW23) & M_PW23)
7789
7790 #define S_PW01 10
7791 #define M_PW01 0x3
7792 #define V_PW01(x) ((x) << S_PW01)
7793 #define G_PW01(x) (((x) >> S_PW01) & M_PW01)
7794
7795 #define S_XGM_DEQ 6
7796 #define M_XGM_DEQ 0xf
7797 #define V_XGM_DEQ(x) ((x) << S_XGM_DEQ)
7798 #define G_XGM_DEQ(x) (((x) >> S_XGM_DEQ) & M_XGM_DEQ)
7799
7800 #define S_XGM_DTX 2
7801 #define M_XGM_DTX 0xf
7802 #define V_XGM_DTX(x) ((x) << S_XGM_DTX)
7803 #define G_XGM_DTX(x) (((x) >> S_XGM_DTX) & M_XGM_DTX)
7804
7805 #define S_XGM_LODRV 1
7806 #define V_XGM_LODRV(x) ((x) << S_XGM_LODRV)
7807 #define F_XGM_LODRV V_XGM_LODRV(1U)
7808
7809 #define S_XGM_HIDRV 0
7810 #define V_XGM_HIDRV(x) ((x) << S_XGM_HIDRV)
7811 #define F_XGM_HIDRV V_XGM_HIDRV(1U)
7812
7813 #define A_XGM_SERDES_CTRL1 0x8e4
7814
7815 #define S_FMOFFSET3 19
7816 #define M_FMOFFSET3 0x1f
7817 #define V_FMOFFSET3(x) ((x) << S_FMOFFSET3)
7818 #define G_FMOFFSET3(x) (((x) >> S_FMOFFSET3) & M_FMOFFSET3)
7819
7820 #define S_FMOFFSETEN3 18
7821 #define V_FMOFFSETEN3(x) ((x) << S_FMOFFSETEN3)
7822 #define F_FMOFFSETEN3 V_FMOFFSETEN3(1U)
7823
7824 #define S_FMOFFSET2 13
7825 #define M_FMOFFSET2 0x1f
7826 #define V_FMOFFSET2(x) ((x) << S_FMOFFSET2)
7827 #define G_FMOFFSET2(x) (((x) >> S_FMOFFSET2) & M_FMOFFSET2)
7828
7829 #define S_FMOFFSETEN2 12
7830 #define V_FMOFFSETEN2(x) ((x) << S_FMOFFSETEN2)
7831 #define F_FMOFFSETEN2 V_FMOFFSETEN2(1U)
7832
7833 #define S_FMOFFSET1 7
7834 #define M_FMOFFSET1 0x1f
7835 #define V_FMOFFSET1(x) ((x) << S_FMOFFSET1)
7836 #define G_FMOFFSET1(x) (((x) >> S_FMOFFSET1) & M_FMOFFSET1)
7837
7838 #define S_FMOFFSETEN1 6
7839 #define V_FMOFFSETEN1(x) ((x) << S_FMOFFSETEN1)
7840 #define F_FMOFFSETEN1 V_FMOFFSETEN1(1U)
7841
7842 #define S_FMOFFSET0 1
7843 #define M_FMOFFSET0 0x1f
7844 #define V_FMOFFSET0(x) ((x) << S_FMOFFSET0)
7845 #define G_FMOFFSET0(x) (((x) >> S_FMOFFSET0) & M_FMOFFSET0)
7846
7847 #define S_FMOFFSETEN0 0
7848 #define V_FMOFFSETEN0(x) ((x) << S_FMOFFSETEN0)
7849 #define F_FMOFFSETEN0 V_FMOFFSETEN0(1U)
7850
7851 #define A_XGM_SERDES_CTRL2 0x8e8
7852
7853 #define S_DNIN3 11
7854 #define V_DNIN3(x) ((x) << S_DNIN3)
7855 #define F_DNIN3 V_DNIN3(1U)
7856
7857 #define S_UPIN3 10
7858 #define V_UPIN3(x) ((x) << S_UPIN3)
7859 #define F_UPIN3 V_UPIN3(1U)
7860
7861 #define S_RXSLAVE3 9
7862 #define V_RXSLAVE3(x) ((x) << S_RXSLAVE3)
7863 #define F_RXSLAVE3 V_RXSLAVE3(1U)
7864
7865 #define S_DNIN2 8
7866 #define V_DNIN2(x) ((x) << S_DNIN2)
7867 #define F_DNIN2 V_DNIN2(1U)
7868
7869 #define S_UPIN2 7
7870 #define V_UPIN2(x) ((x) << S_UPIN2)
7871 #define F_UPIN2 V_UPIN2(1U)
7872
7873 #define S_RXSLAVE2 6
7874 #define V_RXSLAVE2(x) ((x) << S_RXSLAVE2)
7875 #define F_RXSLAVE2 V_RXSLAVE2(1U)
7876
7877 #define S_DNIN1 5
7878 #define V_DNIN1(x) ((x) << S_DNIN1)
7879 #define F_DNIN1 V_DNIN1(1U)
7880
7881 #define S_UPIN1 4
7882 #define V_UPIN1(x) ((x) << S_UPIN1)
7883 #define F_UPIN1 V_UPIN1(1U)
7884
7885 #define S_RXSLAVE1 3
7886 #define V_RXSLAVE1(x) ((x) << S_RXSLAVE1)
7887 #define F_RXSLAVE1 V_RXSLAVE1(1U)
7888
7889 #define S_DNIN0 2
7890 #define V_DNIN0(x) ((x) << S_DNIN0)
7891 #define F_DNIN0 V_DNIN0(1U)
7892
7893 #define S_UPIN0 1
7894 #define V_UPIN0(x) ((x) << S_UPIN0)
7895 #define F_UPIN0 V_UPIN0(1U)
7896
7897 #define S_RXSLAVE0 0
7898 #define V_RXSLAVE0(x) ((x) << S_RXSLAVE0)
7899 #define F_RXSLAVE0 V_RXSLAVE0(1U)
7900
7901 #define A_XGM_SERDES_CTRL3 0x8ec
7902
7903 #define S_EXTBISTCHKERRCLR3 31
7904 #define V_EXTBISTCHKERRCLR3(x) ((x) << S_EXTBISTCHKERRCLR3)
7905 #define F_EXTBISTCHKERRCLR3 V_EXTBISTCHKERRCLR3(1U)
7906
7907 #define S_EXTBISTCHKEN3 30
7908 #define V_EXTBISTCHKEN3(x) ((x) << S_EXTBISTCHKEN3)
7909 #define F_EXTBISTCHKEN3 V_EXTBISTCHKEN3(1U)
7910
7911 #define S_EXTBISTGENEN3 29
7912 #define V_EXTBISTGENEN3(x) ((x) << S_EXTBISTGENEN3)
7913 #define F_EXTBISTGENEN3 V_EXTBISTGENEN3(1U)
7914
7915 #define S_EXTBISTPAT3 26
7916 #define M_EXTBISTPAT3 0x7
7917 #define V_EXTBISTPAT3(x) ((x) << S_EXTBISTPAT3)
7918 #define G_EXTBISTPAT3(x) (((x) >> S_EXTBISTPAT3) & M_EXTBISTPAT3)
7919
7920 #define S_EXTPARRESET3 25
7921 #define V_EXTPARRESET3(x) ((x) << S_EXTPARRESET3)
7922 #define F_EXTPARRESET3 V_EXTPARRESET3(1U)
7923
7924 #define S_EXTPARLPBK3 24
7925 #define V_EXTPARLPBK3(x) ((x) << S_EXTPARLPBK3)
7926 #define F_EXTPARLPBK3 V_EXTPARLPBK3(1U)
7927
7928 #define S_EXTBISTCHKERRCLR2 23
7929 #define V_EXTBISTCHKERRCLR2(x) ((x) << S_EXTBISTCHKERRCLR2)
7930 #define F_EXTBISTCHKERRCLR2 V_EXTBISTCHKERRCLR2(1U)
7931
7932 #define S_EXTBISTCHKEN2 22
7933 #define V_EXTBISTCHKEN2(x) ((x) << S_EXTBISTCHKEN2)
7934 #define F_EXTBISTCHKEN2 V_EXTBISTCHKEN2(1U)
7935
7936 #define S_EXTBISTGENEN2 21
7937 #define V_EXTBISTGENEN2(x) ((x) << S_EXTBISTGENEN2)
7938 #define F_EXTBISTGENEN2 V_EXTBISTGENEN2(1U)
7939
7940 #define S_EXTBISTPAT2 18
7941 #define M_EXTBISTPAT2 0x7
7942 #define V_EXTBISTPAT2(x) ((x) << S_EXTBISTPAT2)
7943 #define G_EXTBISTPAT2(x) (((x) >> S_EXTBISTPAT2) & M_EXTBISTPAT2)
7944
7945 #define S_EXTPARRESET2 17
7946 #define V_EXTPARRESET2(x) ((x) << S_EXTPARRESET2)
7947 #define F_EXTPARRESET2 V_EXTPARRESET2(1U)
7948
7949 #define S_EXTPARLPBK2 16
7950 #define V_EXTPARLPBK2(x) ((x) << S_EXTPARLPBK2)
7951 #define F_EXTPARLPBK2 V_EXTPARLPBK2(1U)
7952
7953 #define S_EXTBISTCHKERRCLR1 15
7954 #define V_EXTBISTCHKERRCLR1(x) ((x) << S_EXTBISTCHKERRCLR1)
7955 #define F_EXTBISTCHKERRCLR1 V_EXTBISTCHKERRCLR1(1U)
7956
7957 #define S_EXTBISTCHKEN1 14
7958 #define V_EXTBISTCHKEN1(x) ((x) << S_EXTBISTCHKEN1)
7959 #define F_EXTBISTCHKEN1 V_EXTBISTCHKEN1(1U)
7960
7961 #define S_EXTBISTGENEN1 13
7962 #define V_EXTBISTGENEN1(x) ((x) << S_EXTBISTGENEN1)
7963 #define F_EXTBISTGENEN1 V_EXTBISTGENEN1(1U)
7964
7965 #define S_EXTBISTPAT1 10
7966 #define M_EXTBISTPAT1 0x7
7967 #define V_EXTBISTPAT1(x) ((x) << S_EXTBISTPAT1)
7968 #define G_EXTBISTPAT1(x) (((x) >> S_EXTBISTPAT1) & M_EXTBISTPAT1)
7969
7970 #define S_EXTPARRESET1 9
7971 #define V_EXTPARRESET1(x) ((x) << S_EXTPARRESET1)
7972 #define F_EXTPARRESET1 V_EXTPARRESET1(1U)
7973
7974 #define S_EXTPARLPBK1 8
7975 #define V_EXTPARLPBK1(x) ((x) << S_EXTPARLPBK1)
7976 #define F_EXTPARLPBK1 V_EXTPARLPBK1(1U)
7977
7978 #define S_EXTBISTCHKERRCLR0 7
7979 #define V_EXTBISTCHKERRCLR0(x) ((x) << S_EXTBISTCHKERRCLR0)
7980 #define F_EXTBISTCHKERRCLR0 V_EXTBISTCHKERRCLR0(1U)
7981
7982 #define S_EXTBISTCHKEN0 6
7983 #define V_EXTBISTCHKEN0(x) ((x) << S_EXTBISTCHKEN0)
7984 #define F_EXTBISTCHKEN0 V_EXTBISTCHKEN0(1U)
7985
7986 #define S_EXTBISTGENEN0 5
7987 #define V_EXTBISTGENEN0(x) ((x) << S_EXTBISTGENEN0)
7988 #define F_EXTBISTGENEN0 V_EXTBISTGENEN0(1U)
7989
7990 #define S_EXTBISTPAT0 2
7991 #define M_EXTBISTPAT0 0x7
7992 #define V_EXTBISTPAT0(x) ((x) << S_EXTBISTPAT0)
7993 #define G_EXTBISTPAT0(x) (((x) >> S_EXTBISTPAT0) & M_EXTBISTPAT0)
7994
7995 #define S_EXTPARRESET0 1
7996 #define V_EXTPARRESET0(x) ((x) << S_EXTPARRESET0)
7997 #define F_EXTPARRESET0 V_EXTPARRESET0(1U)
7998
7999 #define S_EXTPARLPBK0 0
8000 #define V_EXTPARLPBK0(x) ((x) << S_EXTPARLPBK0)
8001 #define F_EXTPARLPBK0 V_EXTPARLPBK0(1U)
8002
8003 #define A_XGM_SERDES_STAT0 0x8f0
8004
8005 #define S_EXTBISTCHKERRCNT0 4
8006 #define M_EXTBISTCHKERRCNT0 0xffffff
8007 #define V_EXTBISTCHKERRCNT0(x) ((x) << S_EXTBISTCHKERRCNT0)
8008 #define G_EXTBISTCHKERRCNT0(x) (((x) >> S_EXTBISTCHKERRCNT0) & M_EXTBISTCHKERRCNT0)
8009
8010 #define S_EXTBISTCHKFMD0 3
8011 #define V_EXTBISTCHKFMD0(x) ((x) << S_EXTBISTCHKFMD0)
8012 #define F_EXTBISTCHKFMD0 V_EXTBISTCHKFMD0(1U)
8013
8014 #define S_LOWSIGFORCEEN0 2
8015 #define V_LOWSIGFORCEEN0(x) ((x) << S_LOWSIGFORCEEN0)
8016 #define F_LOWSIGFORCEEN0 V_LOWSIGFORCEEN0(1U)
8017
8018 #define S_LOWSIGFORCEVALUE0 1
8019 #define V_LOWSIGFORCEVALUE0(x) ((x) << S_LOWSIGFORCEVALUE0)
8020 #define F_LOWSIGFORCEVALUE0 V_LOWSIGFORCEVALUE0(1U)
8021
8022 #define S_LOWSIG0 0
8023 #define V_LOWSIG0(x) ((x) << S_LOWSIG0)
8024 #define F_LOWSIG0 V_LOWSIG0(1U)
8025
8026 #define A_XGM_SERDES_STAT1 0x8f4
8027
8028 #define S_EXTBISTCHKERRCNT1 4
8029 #define M_EXTBISTCHKERRCNT1 0xffffff
8030 #define V_EXTBISTCHKERRCNT1(x) ((x) << S_EXTBISTCHKERRCNT1)
8031 #define G_EXTBISTCHKERRCNT1(x) (((x) >> S_EXTBISTCHKERRCNT1) & M_EXTBISTCHKERRCNT1)
8032
8033 #define S_EXTBISTCHKFMD1 3
8034 #define V_EXTBISTCHKFMD1(x) ((x) << S_EXTBISTCHKFMD1)
8035 #define F_EXTBISTCHKFMD1 V_EXTBISTCHKFMD1(1U)
8036
8037 #define S_LOWSIGFORCEEN1 2
8038 #define V_LOWSIGFORCEEN1(x) ((x) << S_LOWSIGFORCEEN1)
8039 #define F_LOWSIGFORCEEN1 V_LOWSIGFORCEEN1(1U)
8040
8041 #define S_LOWSIGFORCEVALUE1 1
8042 #define V_LOWSIGFORCEVALUE1(x) ((x) << S_LOWSIGFORCEVALUE1)
8043 #define F_LOWSIGFORCEVALUE1 V_LOWSIGFORCEVALUE1(1U)
8044
8045 #define S_LOWSIG1 0
8046 #define V_LOWSIG1(x) ((x) << S_LOWSIG1)
8047 #define F_LOWSIG1 V_LOWSIG1(1U)
8048
8049 #define A_XGM_SERDES_STAT2 0x8f8
8050
8051 #define S_EXTBISTCHKERRCNT2 4
8052 #define M_EXTBISTCHKERRCNT2 0xffffff
8053 #define V_EXTBISTCHKERRCNT2(x) ((x) << S_EXTBISTCHKERRCNT2)
8054 #define G_EXTBISTCHKERRCNT2(x) (((x) >> S_EXTBISTCHKERRCNT2) & M_EXTBISTCHKERRCNT2)
8055
8056 #define S_EXTBISTCHKFMD2 3
8057 #define V_EXTBISTCHKFMD2(x) ((x) << S_EXTBISTCHKFMD2)
8058 #define F_EXTBISTCHKFMD2 V_EXTBISTCHKFMD2(1U)
8059
8060 #define S_LOWSIGFORCEEN2 2
8061 #define V_LOWSIGFORCEEN2(x) ((x) << S_LOWSIGFORCEEN2)
8062 #define F_LOWSIGFORCEEN2 V_LOWSIGFORCEEN2(1U)
8063
8064 #define S_LOWSIGFORCEVALUE2 1
8065 #define V_LOWSIGFORCEVALUE2(x) ((x) << S_LOWSIGFORCEVALUE2)
8066 #define F_LOWSIGFORCEVALUE2 V_LOWSIGFORCEVALUE2(1U)
8067
8068 #define S_LOWSIG2 0
8069 #define V_LOWSIG2(x) ((x) << S_LOWSIG2)
8070 #define F_LOWSIG2 V_LOWSIG2(1U)
8071
8072 #define A_XGM_SERDES_STAT3 0x8fc
8073
8074 #define S_EXTBISTCHKERRCNT3 4
8075 #define M_EXTBISTCHKERRCNT3 0xffffff
8076 #define V_EXTBISTCHKERRCNT3(x) ((x) << S_EXTBISTCHKERRCNT3)
8077 #define G_EXTBISTCHKERRCNT3(x) (((x) >> S_EXTBISTCHKERRCNT3) & M_EXTBISTCHKERRCNT3)
8078
8079 #define S_EXTBISTCHKFMD3 3
8080 #define V_EXTBISTCHKFMD3(x) ((x) << S_EXTBISTCHKFMD3)
8081 #define F_EXTBISTCHKFMD3 V_EXTBISTCHKFMD3(1U)
8082
8083 #define S_LOWSIGFORCEEN3 2
8084 #define V_LOWSIGFORCEEN3(x) ((x) << S_LOWSIGFORCEEN3)
8085 #define F_LOWSIGFORCEEN3 V_LOWSIGFORCEEN3(1U)
8086
8087 #define S_LOWSIGFORCEVALUE3 1
8088 #define V_LOWSIGFORCEVALUE3(x) ((x) << S_LOWSIGFORCEVALUE3)
8089 #define F_LOWSIGFORCEVALUE3 V_LOWSIGFORCEVALUE3(1U)
8090
8091 #define S_LOWSIG3 0
8092 #define V_LOWSIG3(x) ((x) << S_LOWSIG3)
8093 #define F_LOWSIG3 V_LOWSIG3(1U)
8094
8095 #define A_XGM_STAT_TX_BYTE_LOW 0x900
8096 #define A_XGM_STAT_TX_BYTE_HIGH 0x904
8097
8098 #define S_TXBYTES_HIGH 0
8099 #define M_TXBYTES_HIGH 0x1fff
8100 #define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH)
8101 #define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH)
8102
8103 #define A_XGM_STAT_TX_FRAME_LOW 0x908
8104 #define A_XGM_STAT_TX_FRAME_HIGH 0x90c
8105
8106 #define S_TXFRAMES_HIGH 0
8107 #define M_TXFRAMES_HIGH 0xf
8108 #define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH)
8109 #define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH)
8110
8111 #define A_XGM_STAT_TX_BCAST 0x910
8112 #define A_XGM_STAT_TX_MCAST 0x914
8113 #define A_XGM_STAT_TX_PAUSE 0x918
8114 #define A_XGM_STAT_TX_64B_FRAMES 0x91c
8115 #define A_XGM_STAT_TX_65_127B_FRAMES 0x920
8116 #define A_XGM_STAT_TX_128_255B_FRAMES 0x924
8117 #define A_XGM_STAT_TX_256_511B_FRAMES 0x928
8118 #define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c
8119 #define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930
8120 #define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934
8121 #define A_XGM_STAT_TX_ERR_FRAMES 0x938
8122 #define A_XGM_STAT_RX_BYTES_LOW 0x93c
8123 #define A_XGM_STAT_RX_BYTES_HIGH 0x940
8124
8125 #define S_RXBYTES_HIGH 0
8126 #define M_RXBYTES_HIGH 0x1fff
8127 #define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH)
8128 #define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH)
8129
8130 #define A_XGM_STAT_RX_FRAMES_LOW 0x944
8131 #define A_XGM_STAT_RX_FRAMES_HIGH 0x948
8132
8133 #define S_RXFRAMES_HIGH 0
8134 #define M_RXFRAMES_HIGH 0xf
8135 #define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH)
8136 #define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH)
8137
8138 #define A_XGM_STAT_RX_BCAST_FRAMES 0x94c
8139 #define A_XGM_STAT_RX_MCAST_FRAMES 0x950
8140 #define A_XGM_STAT_RX_PAUSE_FRAMES 0x954
8141
8142 #define S_RXPAUSEFRAMES 0
8143 #define M_RXPAUSEFRAMES 0xffff
8144 #define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES)
8145 #define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES)
8146
8147 #define A_XGM_STAT_RX_64B_FRAMES 0x958
8148 #define A_XGM_STAT_RX_65_127B_FRAMES 0x95c
8149 #define A_XGM_STAT_RX_128_255B_FRAMES 0x960
8150 #define A_XGM_STAT_RX_256_511B_FRAMES 0x964
8151 #define A_XGM_STAT_RX_512_1023B_FRAMES 0x968
8152 #define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c
8153 #define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970
8154 #define A_XGM_STAT_RX_SHORT_FRAMES 0x974
8155
8156 #define S_RXSHORTFRAMES 0
8157 #define M_RXSHORTFRAMES 0xffff
8158 #define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES)
8159 #define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES)
8160
8161 #define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978
8162
8163 #define S_RXOVERSIZEFRAMES 0
8164 #define M_RXOVERSIZEFRAMES 0xffff
8165 #define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES)
8166 #define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES)
8167
8168 #define A_XGM_STAT_RX_JABBER_FRAMES 0x97c
8169
8170 #define S_RXJABBERFRAMES 0
8171 #define M_RXJABBERFRAMES 0xffff
8172 #define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES)
8173 #define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES)
8174
8175 #define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980
8176
8177 #define S_RXCRCERRFRAMES 0
8178 #define M_RXCRCERRFRAMES 0xffff
8179 #define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES)
8180 #define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES)
8181
8182 #define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984
8183
8184 #define S_RXLENGTHERRFRAMES 0
8185 #define M_RXLENGTHERRFRAMES 0xffff
8186 #define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES)
8187 #define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES)
8188
8189 #define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988
8190
8191 #define S_RXSYMCODEERRFRAMES 0
8192 #define M_RXSYMCODEERRFRAMES 0xffff
8193 #define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES)
8194 #define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES)
8195
8196 #define A_XGM_SERDES_STATUS0 0x98c
8197
8198 #define S_RXERRLANE3 9
8199 #define M_RXERRLANE3 0x7
8200 #define V_RXERRLANE3(x) ((x) << S_RXERRLANE3)
8201 #define G_RXERRLANE3(x) (((x) >> S_RXERRLANE3) & M_RXERRLANE3)
8202
8203 #define S_RXERRLANE2 6
8204 #define M_RXERRLANE2 0x7
8205 #define V_RXERRLANE2(x) ((x) << S_RXERRLANE2)
8206 #define G_RXERRLANE2(x) (((x) >> S_RXERRLANE2) & M_RXERRLANE2)
8207
8208 #define S_RXERRLANE1 3
8209 #define M_RXERRLANE1 0x7
8210 #define V_RXERRLANE1(x) ((x) << S_RXERRLANE1)
8211 #define G_RXERRLANE1(x) (((x) >> S_RXERRLANE1) & M_RXERRLANE1)
8212
8213 #define S_RXERRLANE0 0
8214 #define M_RXERRLANE0 0x7
8215 #define V_RXERRLANE0(x) ((x) << S_RXERRLANE0)
8216 #define G_RXERRLANE0(x) (((x) >> S_RXERRLANE0) & M_RXERRLANE0)
8217
8218 #define A_XGM_SERDES_STATUS1 0x990
8219
8220 #define S_RXKLOCKLANE3 11
8221 #define V_RXKLOCKLANE3(x) ((x) << S_RXKLOCKLANE3)
8222 #define F_RXKLOCKLANE3 V_RXKLOCKLANE3(1U)
8223
8224 #define S_RXKLOCKLANE2 10
8225 #define V_RXKLOCKLANE2(x) ((x) << S_RXKLOCKLANE2)
8226 #define F_RXKLOCKLANE2 V_RXKLOCKLANE2(1U)
8227
8228 #define S_RXKLOCKLANE1 9
8229 #define V_RXKLOCKLANE1(x) ((x) << S_RXKLOCKLANE1)
8230 #define F_RXKLOCKLANE1 V_RXKLOCKLANE1(1U)
8231
8232 #define S_RXKLOCKLANE0 8
8233 #define V_RXKLOCKLANE0(x) ((x) << S_RXKLOCKLANE0)
8234 #define F_RXKLOCKLANE0 V_RXKLOCKLANE0(1U)
8235
8236 #define S_RXUFLOWLANE3 7
8237 #define V_RXUFLOWLANE3(x) ((x) << S_RXUFLOWLANE3)
8238 #define F_RXUFLOWLANE3 V_RXUFLOWLANE3(1U)
8239
8240 #define S_RXUFLOWLANE2 6
8241 #define V_RXUFLOWLANE2(x) ((x) << S_RXUFLOWLANE2)
8242 #define F_RXUFLOWLANE2 V_RXUFLOWLANE2(1U)
8243
8244 #define S_RXUFLOWLANE1 5
8245 #define V_RXUFLOWLANE1(x) ((x) << S_RXUFLOWLANE1)
8246 #define F_RXUFLOWLANE1 V_RXUFLOWLANE1(1U)
8247
8248 #define S_RXUFLOWLANE0 4
8249 #define V_RXUFLOWLANE0(x) ((x) << S_RXUFLOWLANE0)
8250 #define F_RXUFLOWLANE0 V_RXUFLOWLANE0(1U)
8251
8252 #define S_RXOFLOWLANE3 3
8253 #define V_RXOFLOWLANE3(x) ((x) << S_RXOFLOWLANE3)
8254 #define F_RXOFLOWLANE3 V_RXOFLOWLANE3(1U)
8255
8256 #define S_RXOFLOWLANE2 2
8257 #define V_RXOFLOWLANE2(x) ((x) << S_RXOFLOWLANE2)
8258 #define F_RXOFLOWLANE2 V_RXOFLOWLANE2(1U)
8259
8260 #define S_RXOFLOWLANE1 1
8261 #define V_RXOFLOWLANE1(x) ((x) << S_RXOFLOWLANE1)
8262 #define F_RXOFLOWLANE1 V_RXOFLOWLANE1(1U)
8263
8264 #define S_RXOFLOWLANE0 0
8265 #define V_RXOFLOWLANE0(x) ((x) << S_RXOFLOWLANE0)
8266 #define F_RXOFLOWLANE0 V_RXOFLOWLANE0(1U)
8267
8268 #define A_XGM_SERDES_STATUS2 0x994
8269
8270 #define S_XGM_RXEIDLANE3 11
8271 #define V_XGM_RXEIDLANE3(x) ((x) << S_XGM_RXEIDLANE3)
8272 #define F_XGM_RXEIDLANE3 V_XGM_RXEIDLANE3(1U)
8273
8274 #define S_XGM_RXEIDLANE2 10
8275 #define V_XGM_RXEIDLANE2(x) ((x) << S_XGM_RXEIDLANE2)
8276 #define F_XGM_RXEIDLANE2 V_XGM_RXEIDLANE2(1U)
8277
8278 #define S_XGM_RXEIDLANE1 9
8279 #define V_XGM_RXEIDLANE1(x) ((x) << S_XGM_RXEIDLANE1)
8280 #define F_XGM_RXEIDLANE1 V_XGM_RXEIDLANE1(1U)
8281
8282 #define S_XGM_RXEIDLANE0 8
8283 #define V_XGM_RXEIDLANE0(x) ((x) << S_XGM_RXEIDLANE0)
8284 #define F_XGM_RXEIDLANE0 V_XGM_RXEIDLANE0(1U)
8285
8286 #define S_RXREMSKIPLANE3 7
8287 #define V_RXREMSKIPLANE3(x) ((x) << S_RXREMSKIPLANE3)
8288 #define F_RXREMSKIPLANE3 V_RXREMSKIPLANE3(1U)
8289
8290 #define S_RXREMSKIPLANE2 6
8291 #define V_RXREMSKIPLANE2(x) ((x) << S_RXREMSKIPLANE2)
8292 #define F_RXREMSKIPLANE2 V_RXREMSKIPLANE2(1U)
8293
8294 #define S_RXREMSKIPLANE1 5
8295 #define V_RXREMSKIPLANE1(x) ((x) << S_RXREMSKIPLANE1)
8296 #define F_RXREMSKIPLANE1 V_RXREMSKIPLANE1(1U)
8297
8298 #define S_RXREMSKIPLANE0 4
8299 #define V_RXREMSKIPLANE0(x) ((x) << S_RXREMSKIPLANE0)
8300 #define F_RXREMSKIPLANE0 V_RXREMSKIPLANE0(1U)
8301
8302 #define S_RXADDSKIPLANE3 3
8303 #define V_RXADDSKIPLANE3(x) ((x) << S_RXADDSKIPLANE3)
8304 #define F_RXADDSKIPLANE3 V_RXADDSKIPLANE3(1U)
8305
8306 #define S_RXADDSKIPLANE2 2
8307 #define V_RXADDSKIPLANE2(x) ((x) << S_RXADDSKIPLANE2)
8308 #define F_RXADDSKIPLANE2 V_RXADDSKIPLANE2(1U)
8309
8310 #define S_RXADDSKIPLANE1 1
8311 #define V_RXADDSKIPLANE1(x) ((x) << S_RXADDSKIPLANE1)
8312 #define F_RXADDSKIPLANE1 V_RXADDSKIPLANE1(1U)
8313
8314 #define S_RXADDSKIPLANE0 0
8315 #define V_RXADDSKIPLANE0(x) ((x) << S_RXADDSKIPLANE0)
8316 #define F_RXADDSKIPLANE0 V_RXADDSKIPLANE0(1U)
8317
8318 #define A_XGM_XAUI_PCS_ERR 0x998
8319
8320 #define S_PCS_SYNCSTATUS 5
8321 #define M_PCS_SYNCSTATUS 0xf
8322 #define V_PCS_SYNCSTATUS(x) ((x) << S_PCS_SYNCSTATUS)
8323 #define G_PCS_SYNCSTATUS(x) (((x) >> S_PCS_SYNCSTATUS) & M_PCS_SYNCSTATUS)
8324
8325 #define S_PCS_CTCFIFOERR 1
8326 #define M_PCS_CTCFIFOERR 0xf
8327 #define V_PCS_CTCFIFOERR(x) ((x) << S_PCS_CTCFIFOERR)
8328 #define G_PCS_CTCFIFOERR(x) (((x) >> S_PCS_CTCFIFOERR) & M_PCS_CTCFIFOERR)
8329
8330 #define S_PCS_NOTALIGNED 0
8331 #define V_PCS_NOTALIGNED(x) ((x) << S_PCS_NOTALIGNED)
8332 #define F_PCS_NOTALIGNED V_PCS_NOTALIGNED(1U)
8333
8334 #define A_XGM_RGMII_STATUS 0x99c
8335
8336 #define S_GMIIDUPLEX 3
8337 #define V_GMIIDUPLEX(x) ((x) << S_GMIIDUPLEX)
8338 #define F_GMIIDUPLEX V_GMIIDUPLEX(1U)
8339
8340 #define S_GMIISPEED 1
8341 #define M_GMIISPEED 0x3
8342 #define V_GMIISPEED(x) ((x) << S_GMIISPEED)
8343 #define G_GMIISPEED(x) (((x) >> S_GMIISPEED) & M_GMIISPEED)
8344
8345 #define S_GMIILINKSTATUS 0
8346 #define V_GMIILINKSTATUS(x) ((x) << S_GMIILINKSTATUS)
8347 #define F_GMIILINKSTATUS V_GMIILINKSTATUS(1U)
8348
8349 #define A_XGM_WOL_STATUS 0x9a0
8350
8351 #define S_PATDETECTED 31
8352 #define V_PATDETECTED(x) ((x) << S_PATDETECTED)
8353 #define F_PATDETECTED V_PATDETECTED(1U)
8354
8355 #define S_MATCHEDFILTER 0
8356 #define M_MATCHEDFILTER 0x7
8357 #define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER)
8358 #define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER)
8359
8360 #define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
8361 #define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8
8362
8363 #define S_TXSPI4SOPCNT 16
8364 #define M_TXSPI4SOPCNT 0xffff
8365 #define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
8366 #define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
8367
8368 #define S_TXSPI4EOPCNT 0
8369 #define M_TXSPI4EOPCNT 0xffff
8370 #define V_TXSPI4EOPCNT(x) ((x) << S_TXSPI4EOPCNT)
8371 #define G_TXSPI4EOPCNT(x) (((x) >> S_TXSPI4EOPCNT) & M_TXSPI4EOPCNT)
8372
8373 #define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac
8374
8375 #define S_RXSPI4SOPCNT 16
8376 #define M_RXSPI4SOPCNT 0xffff
8377 #define V_RXSPI4SOPCNT(x) ((x) << S_RXSPI4SOPCNT)
8378 #define G_RXSPI4SOPCNT(x) (((x) >> S_RXSPI4SOPCNT) & M_RXSPI4SOPCNT)
8379
8380 #define S_RXSPI4EOPCNT 0
8381 #define M_RXSPI4EOPCNT 0xffff
8382 #define V_RXSPI4EOPCNT(x) ((x) << S_RXSPI4EOPCNT)
8383 #define G_RXSPI4EOPCNT(x) (((x) >> S_RXSPI4EOPCNT) & M_RXSPI4EOPCNT)
8384
8385 /* registers for module XGMAC0_1 */
8386 #define XGMAC0_1_BASE_ADDR 0xa00
Cache object: 989ba8f3380728421f54d6c83f4cf1c9
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