The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/cxgb/common/cxgb_t3_cpl.h

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    1 /**************************************************************************
    2 
    3 Copyright (c) 2007-2009 Chelsio Inc.
    4 All rights reserved.
    5 
    6 Redistribution and use in source and binary forms, with or without
    7 modification, are permitted provided that the following conditions are met:
    8 
    9  1. Redistributions of source code must retain the above copyright notice,
   10     this list of conditions and the following disclaimer.
   11 
   12  2. Neither the name of the Chelsio Corporation nor the names of its
   13     contributors may be used to endorse or promote products derived from
   14     this software without specific prior written permission.
   15 
   16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   26 POSSIBILITY OF SUCH DAMAGE.
   27 
   28 $FreeBSD: releng/10.0/sys/dev/cxgb/common/cxgb_t3_cpl.h 194521 2009-06-19 23:34:32Z kmacy $
   29 
   30 ***************************************************************************/
   31 #ifndef T3_CPL_H
   32 #define T3_CPL_H
   33 
   34 enum CPL_opcode {
   35         CPL_PASS_OPEN_REQ     = 0x1,
   36         CPL_PASS_ACCEPT_RPL   = 0x2,
   37         CPL_ACT_OPEN_REQ      = 0x3,
   38         CPL_SET_TCB           = 0x4,
   39         CPL_SET_TCB_FIELD     = 0x5,
   40         CPL_GET_TCB           = 0x6,
   41         CPL_PCMD              = 0x7,
   42         CPL_CLOSE_CON_REQ     = 0x8,
   43         CPL_CLOSE_LISTSRV_REQ = 0x9,
   44         CPL_ABORT_REQ         = 0xA,
   45         CPL_ABORT_RPL         = 0xB,
   46         CPL_TX_DATA           = 0xC,
   47         CPL_RX_DATA_ACK       = 0xD,
   48         CPL_TX_PKT            = 0xE,
   49         CPL_RTE_DELETE_REQ    = 0xF,
   50         CPL_RTE_WRITE_REQ     = 0x10,
   51         CPL_RTE_READ_REQ      = 0x11,
   52         CPL_L2T_WRITE_REQ     = 0x12,
   53         CPL_L2T_READ_REQ      = 0x13,
   54         CPL_SMT_WRITE_REQ     = 0x14,
   55         CPL_SMT_READ_REQ      = 0x15,
   56         CPL_TX_PKT_LSO        = 0x16,
   57         CPL_PCMD_READ         = 0x17,
   58         CPL_BARRIER           = 0x18,
   59         CPL_TID_RELEASE       = 0x1A,
   60 
   61         CPL_CLOSE_LISTSRV_RPL = 0x20,
   62         CPL_ERROR             = 0x21,
   63         CPL_GET_TCB_RPL       = 0x22,
   64         CPL_L2T_WRITE_RPL     = 0x23,
   65         CPL_PCMD_READ_RPL     = 0x24,
   66         CPL_PCMD_RPL          = 0x25,
   67         CPL_PEER_CLOSE        = 0x26,
   68         CPL_RTE_DELETE_RPL    = 0x27,
   69         CPL_RTE_WRITE_RPL     = 0x28,
   70         CPL_RX_DDP_COMPLETE   = 0x29,
   71         CPL_RX_PHYS_ADDR      = 0x2A,
   72         CPL_RX_PKT            = 0x2B,
   73         CPL_RX_URG_NOTIFY     = 0x2C,
   74         CPL_SET_TCB_RPL       = 0x2D,
   75         CPL_SMT_WRITE_RPL     = 0x2E,
   76         CPL_TX_DATA_ACK       = 0x2F,
   77 
   78         CPL_ABORT_REQ_RSS     = 0x30,
   79         CPL_ABORT_RPL_RSS     = 0x31,
   80         CPL_CLOSE_CON_RPL     = 0x32,
   81         CPL_ISCSI_HDR         = 0x33,
   82         CPL_L2T_READ_RPL      = 0x34,
   83         CPL_RDMA_CQE          = 0x35,
   84         CPL_RDMA_CQE_READ_RSP = 0x36,
   85         CPL_RDMA_CQE_ERR      = 0x37,
   86         CPL_RTE_READ_RPL      = 0x38,
   87         CPL_RX_DATA           = 0x39,
   88 
   89         CPL_ACT_OPEN_RPL      = 0x40,
   90         CPL_PASS_OPEN_RPL     = 0x41,
   91         CPL_RX_DATA_DDP       = 0x42,
   92         CPL_SMT_READ_RPL      = 0x43,
   93 
   94         CPL_ACT_ESTABLISH     = 0x50,
   95         CPL_PASS_ESTABLISH    = 0x51,
   96 
   97         CPL_PASS_ACCEPT_REQ   = 0x70,
   98 
   99         CPL_ASYNC_NOTIF       = 0x80, /* fake opcode for async notifications */
  100 
  101         CPL_TX_DMA_ACK        = 0xA0,
  102         CPL_RDMA_READ_REQ     = 0xA1,
  103         CPL_RDMA_TERMINATE    = 0xA2,
  104         CPL_TRACE_PKT         = 0xA3,
  105         CPL_RDMA_EC_STATUS    = 0xA5,
  106         CPL_SGE_EC_CR_RETURN  = 0xA6,
  107 
  108         NUM_CPL_CMDS    /* must be last and previous entries must be sorted */
  109 };
  110 
  111 enum CPL_error {
  112         CPL_ERR_NONE               = 0,
  113         CPL_ERR_TCAM_PARITY        = 1,
  114         CPL_ERR_TCAM_FULL          = 3,
  115         CPL_ERR_CONN_RESET         = 20,
  116         CPL_ERR_CONN_EXIST         = 22,
  117         CPL_ERR_ARP_MISS           = 23,
  118         CPL_ERR_BAD_SYN            = 24,
  119         CPL_ERR_CONN_TIMEDOUT      = 30,
  120         CPL_ERR_XMIT_TIMEDOUT      = 31,
  121         CPL_ERR_PERSIST_TIMEDOUT   = 32,
  122         CPL_ERR_FINWAIT2_TIMEDOUT  = 33,
  123         CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
  124         CPL_ERR_RTX_NEG_ADVICE     = 35,
  125         CPL_ERR_PERSIST_NEG_ADVICE = 36,
  126         CPL_ERR_ABORT_FAILED       = 42,
  127         CPL_ERR_GENERAL            = 99
  128 };
  129 
  130 enum {
  131         CPL_CONN_POLICY_AUTO = 0,
  132         CPL_CONN_POLICY_ASK  = 1,
  133         CPL_CONN_POLICY_FILTER = 2,
  134         CPL_CONN_POLICY_DENY = 3
  135 };
  136 
  137 enum {
  138         ULP_MODE_NONE          = 0,
  139         ULP_MODE_TCP_DDP       = 1,
  140         ULP_MODE_ISCSI         = 2,
  141         ULP_MODE_RDMA          = 4,
  142         ULP_MODE_TCPDDP        = 5
  143 };
  144 
  145 enum {
  146         ULP_CRC_HEADER = 1 << 0,
  147         ULP_CRC_DATA   = 1 << 1
  148 };
  149 
  150 enum {
  151         CPL_PASS_OPEN_ACCEPT,
  152         CPL_PASS_OPEN_REJECT,
  153         CPL_PASS_OPEN_ACCEPT_TNL
  154 };
  155 
  156 enum {
  157         CPL_ABORT_SEND_RST = 0,
  158         CPL_ABORT_NO_RST,
  159         CPL_ABORT_POST_CLOSE_REQ = 2
  160 };
  161 
  162 enum {                     /* TX_PKT_LSO ethernet types */
  163         CPL_ETH_II,
  164         CPL_ETH_II_VLAN,
  165         CPL_ETH_802_3,
  166         CPL_ETH_802_3_VLAN
  167 };
  168 
  169 enum {                     /* TCP congestion control algorithms */
  170         CONG_ALG_RENO,
  171         CONG_ALG_TAHOE,
  172         CONG_ALG_NEWRENO,
  173         CONG_ALG_HIGHSPEED
  174 };
  175 
  176 enum {                     /* RSS hash type */
  177         RSS_HASH_NONE = 0,
  178         RSS_HASH_2_TUPLE = 1,
  179         RSS_HASH_4_TUPLE = 2,
  180         RSS_HASH_TCPV6 = 3
  181 };
  182 
  183 union opcode_tid {
  184         __be32 opcode_tid;
  185         __u8 opcode;
  186 };
  187 
  188 #define S_OPCODE 24
  189 #define V_OPCODE(x) ((x) << S_OPCODE)
  190 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
  191 #define G_TID(x)    ((x) & 0xFFFFFF)
  192 
  193 /* tid is assumed to be 24-bits */
  194 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
  195 
  196 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
  197 
  198 /* extract the TID from a CPL command */
  199 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
  200 
  201 struct tcp_options {
  202         __be16 mss;
  203         __u8 wsf;
  204 #if defined(__LITTLE_ENDIAN_BITFIELD)
  205         __u8 :5;
  206         __u8 ecn:1;
  207         __u8 sack:1;
  208         __u8 tstamp:1;
  209 #else
  210         __u8 tstamp:1;
  211         __u8 sack:1;
  212         __u8 ecn:1;
  213         __u8 :5;
  214 #endif
  215 };
  216 
  217 struct rss_header {
  218         __u8 opcode;
  219 #if defined(__LITTLE_ENDIAN_BITFIELD)
  220         __u8 cpu_idx:6;
  221         __u8 hash_type:2;
  222 #else
  223         __u8 hash_type:2;
  224         __u8 cpu_idx:6;
  225 #endif
  226         __be16 cq_idx;
  227         __be32 rss_hash_val;
  228 };
  229 
  230 #define S_HASHTYPE 22
  231 #define M_HASHTYPE 0x3
  232 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
  233 
  234 #define S_QNUM 0
  235 #define M_QNUM 0xFFFF
  236 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM)
  237 
  238 #ifndef CHELSIO_FW
  239 struct work_request_hdr {
  240         union {
  241                 struct {
  242                         __be32 wr_hi;
  243                         __be32 wr_lo;
  244                 } ilp32;
  245                 struct {
  246                         __be64 wr_hilo;
  247                 } lp64;
  248         } u;
  249 };
  250 
  251 #define wrh_hi          u.ilp32.wr_hi
  252 #define wrh_lo          u.ilp32.wr_lo
  253 #define wrh_hilo        u.lp64.wr_hilo
  254 
  255 /* wr_hi fields */
  256 #define S_WR_SGE_CREDITS    0
  257 #define M_WR_SGE_CREDITS    0xFF
  258 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS)
  259 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS)
  260 
  261 #define S_WR_SGLSFLT    8
  262 #define M_WR_SGLSFLT    0xFF
  263 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT)
  264 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT)
  265 
  266 #define S_WR_BCNTLFLT    16
  267 #define M_WR_BCNTLFLT    0xF
  268 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
  269 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
  270 
  271 /*
  272  * Applicable to BYPASS WRs only: the uP will add a CPL_BARRIER before
  273  * and after the BYPASS WR if the ATOMIC bit is set.
  274  */
  275 #define S_WR_ATOMIC     16
  276 #define V_WR_ATOMIC(x)  ((x) << S_WR_ATOMIC)
  277 #define F_WR_ATOMIC     V_WR_ATOMIC(1U)
  278 
  279 /*
  280  * Applicable to BYPASS WRs only: the uP will flush buffered non abort
  281  * related WRs.
  282  */
  283 #define S_WR_FLUSH      17
  284 #define V_WR_FLUSH(x)   ((x) << S_WR_FLUSH)
  285 #define F_WR_FLUSH      V_WR_FLUSH(1U)
  286 
  287 #define S_WR_CHN        18
  288 #define V_WR_CHN(x)     ((x) << S_WR_CHN)
  289 #define F_WR_CHN        V_WR_CHN(1U)
  290 
  291 #define S_WR_CHN_VLD    19
  292 #define V_WR_CHN_VLD(x) ((x) << S_WR_CHN_VLD)
  293 #define F_WR_CHN_VLD    V_WR_CHN_VLD(1U)
  294 
  295 #define S_WR_DATATYPE    20
  296 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
  297 #define F_WR_DATATYPE    V_WR_DATATYPE(1U)
  298 
  299 #define S_WR_COMPL    21
  300 #define V_WR_COMPL(x) ((x) << S_WR_COMPL)
  301 #define F_WR_COMPL    V_WR_COMPL(1U)
  302 
  303 #define S_WR_EOP    22
  304 #define V_WR_EOP(x) ((x) << S_WR_EOP)
  305 #define F_WR_EOP    V_WR_EOP(1U)
  306 
  307 #define S_WR_SOP    23
  308 #define V_WR_SOP(x) ((x) << S_WR_SOP)
  309 #define F_WR_SOP    V_WR_SOP(1U)
  310 
  311 #define S_WR_OP    24
  312 #define M_WR_OP    0xFF
  313 #define V_WR_OP(x) ((x) << S_WR_OP)
  314 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
  315 
  316 /* wr_lo fields */
  317 #define S_WR_LEN    0
  318 #define M_WR_LEN    0xFF
  319 #define V_WR_LEN(x) ((x) << S_WR_LEN)
  320 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN)
  321 
  322 #define S_WR_TID    8
  323 #define M_WR_TID    0xFFFFF
  324 #define V_WR_TID(x) ((x) << S_WR_TID)
  325 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID)
  326 
  327 #define S_WR_CR_FLUSH    30
  328 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH)
  329 #define F_WR_CR_FLUSH    V_WR_CR_FLUSH(1U)
  330 
  331 #define S_WR_GEN    31
  332 #define V_WR_GEN(x) ((x) << S_WR_GEN)
  333 #define F_WR_GEN    V_WR_GEN(1U)
  334 #define G_WR_GEN(x) ((x) >> S_WR_GEN)
  335 
  336 # define WR_HDR struct work_request_hdr wr
  337 # define RSS_HDR
  338 #else
  339 # define WR_HDR
  340 # define RSS_HDR struct rss_header rss_hdr;
  341 #endif
  342 
  343 /* option 0 lower-half fields */
  344 #define S_CPL_STATUS    0
  345 #define M_CPL_STATUS    0xFF
  346 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS)
  347 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS)
  348 
  349 #define S_INJECT_TIMER    6
  350 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
  351 #define F_INJECT_TIMER    V_INJECT_TIMER(1U)
  352 
  353 #define S_NO_OFFLOAD    7
  354 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD)
  355 #define F_NO_OFFLOAD    V_NO_OFFLOAD(1U)
  356 
  357 #define S_ULP_MODE    8
  358 #define M_ULP_MODE    0xF
  359 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
  360 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
  361 
  362 #define S_RCV_BUFSIZ    12
  363 #define M_RCV_BUFSIZ    0x3FFF
  364 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
  365 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
  366 
  367 #define S_TOS    26
  368 #define M_TOS    0x3F
  369 #define V_TOS(x) ((x) << S_TOS)
  370 #define G_TOS(x) (((x) >> S_TOS) & M_TOS)
  371 
  372 /* option 0 upper-half fields */
  373 #define S_DELACK    0
  374 #define V_DELACK(x) ((x) << S_DELACK)
  375 #define F_DELACK    V_DELACK(1U)
  376 
  377 #define S_NO_CONG    1
  378 #define V_NO_CONG(x) ((x) << S_NO_CONG)
  379 #define F_NO_CONG    V_NO_CONG(1U)
  380 
  381 #define S_SRC_MAC_SEL    2
  382 #define M_SRC_MAC_SEL    0x3
  383 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL)
  384 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL)
  385 
  386 #define S_L2T_IDX    4
  387 #define M_L2T_IDX    0x7FF
  388 #define V_L2T_IDX(x) ((x) << S_L2T_IDX)
  389 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
  390 
  391 #define S_TX_CHANNEL    15
  392 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL)
  393 #define F_TX_CHANNEL    V_TX_CHANNEL(1U)
  394 
  395 #define S_TCAM_BYPASS    16
  396 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS)
  397 #define F_TCAM_BYPASS    V_TCAM_BYPASS(1U)
  398 
  399 #define S_NAGLE    17
  400 #define V_NAGLE(x) ((x) << S_NAGLE)
  401 #define F_NAGLE    V_NAGLE(1U)
  402 
  403 #define S_WND_SCALE    18
  404 #define M_WND_SCALE    0xF
  405 #define V_WND_SCALE(x) ((x) << S_WND_SCALE)
  406 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
  407 
  408 #define S_KEEP_ALIVE    22
  409 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE)
  410 #define F_KEEP_ALIVE    V_KEEP_ALIVE(1U)
  411 
  412 #define S_MAX_RETRANS    23
  413 #define M_MAX_RETRANS    0xF
  414 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS)
  415 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS)
  416 
  417 #define S_MAX_RETRANS_OVERRIDE    27
  418 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE)
  419 #define F_MAX_RETRANS_OVERRIDE    V_MAX_RETRANS_OVERRIDE(1U)
  420 
  421 #define S_MSS_IDX    28
  422 #define M_MSS_IDX    0xF
  423 #define V_MSS_IDX(x) ((x) << S_MSS_IDX)
  424 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
  425 
  426 /* option 1 fields */
  427 #define S_RSS_ENABLE    0
  428 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE)
  429 #define F_RSS_ENABLE    V_RSS_ENABLE(1U)
  430 
  431 #define S_RSS_MASK_LEN    1
  432 #define M_RSS_MASK_LEN    0x7
  433 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
  434 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
  435 
  436 #define S_CPU_IDX    4
  437 #define M_CPU_IDX    0x3F
  438 #define V_CPU_IDX(x) ((x) << S_CPU_IDX)
  439 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
  440 
  441 #define S_OPT1_VLAN    6
  442 #define M_OPT1_VLAN    0xFFF
  443 #define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN)
  444 #define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN)
  445 
  446 #define S_MAC_MATCH_VALID    18
  447 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
  448 #define F_MAC_MATCH_VALID    V_MAC_MATCH_VALID(1U)
  449 
  450 #define S_CONN_POLICY    19
  451 #define M_CONN_POLICY    0x3
  452 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
  453 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
  454 
  455 #define S_SYN_DEFENSE    21
  456 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
  457 #define F_SYN_DEFENSE    V_SYN_DEFENSE(1U)
  458 
  459 #define S_VLAN_PRI    22
  460 #define M_VLAN_PRI    0x3
  461 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI)
  462 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI)
  463 
  464 #define S_VLAN_PRI_VALID    24
  465 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID)
  466 #define F_VLAN_PRI_VALID    V_VLAN_PRI_VALID(1U)
  467 
  468 #define S_PKT_TYPE    25
  469 #define M_PKT_TYPE    0x3
  470 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE)
  471 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE)
  472 
  473 #define S_MAC_MATCH    27
  474 #define M_MAC_MATCH    0x1F
  475 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH)
  476 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH)
  477 
  478 /* option 2 fields */
  479 #define S_CPU_INDEX    0
  480 #define M_CPU_INDEX    0x7F
  481 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX)
  482 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX)
  483 
  484 #define S_CPU_INDEX_VALID    7
  485 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID)
  486 #define F_CPU_INDEX_VALID    V_CPU_INDEX_VALID(1U)
  487 
  488 #define S_RX_COALESCE    8
  489 #define M_RX_COALESCE    0x3
  490 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
  491 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
  492 
  493 #define S_RX_COALESCE_VALID    10
  494 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
  495 #define F_RX_COALESCE_VALID    V_RX_COALESCE_VALID(1U)
  496 
  497 #define S_CONG_CONTROL_FLAVOR    11
  498 #define M_CONG_CONTROL_FLAVOR    0x3
  499 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR)
  500 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR)
  501 
  502 #define S_PACING_FLAVOR    13
  503 #define M_PACING_FLAVOR    0x3
  504 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR)
  505 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR)
  506 
  507 #define S_FLAVORS_VALID    15
  508 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID)
  509 #define F_FLAVORS_VALID    V_FLAVORS_VALID(1U)
  510 
  511 #define S_RX_FC_DISABLE    16
  512 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
  513 #define F_RX_FC_DISABLE    V_RX_FC_DISABLE(1U)
  514 
  515 #define S_RX_FC_VALID    17
  516 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
  517 #define F_RX_FC_VALID    V_RX_FC_VALID(1U)
  518 
  519 struct cpl_pass_open_req {
  520         WR_HDR;
  521         union opcode_tid ot;
  522         __be16 local_port;
  523         __be16 peer_port;
  524         __be32 local_ip;
  525         __be32 peer_ip;
  526         __be32 opt0h;
  527         __be32 opt0l;
  528         __be32 peer_netmask;
  529         __be32 opt1;
  530 };
  531 
  532 struct cpl_pass_open_rpl {
  533         RSS_HDR
  534         union opcode_tid ot;
  535         __be16 local_port;
  536         __be16 peer_port;
  537         __be32 local_ip;
  538         __be32 peer_ip;
  539         __u8 resvd[7];
  540         __u8 status;
  541 };
  542 
  543 struct cpl_pass_establish {
  544         RSS_HDR
  545         union opcode_tid ot;
  546         __be16 local_port;
  547         __be16 peer_port;
  548         __be32 local_ip;
  549         __be32 peer_ip;
  550         __be32 tos_tid;
  551         __be16 l2t_idx;
  552         __be16 tcp_opt;
  553         __be32 snd_isn;
  554         __be32 rcv_isn;
  555 };
  556 
  557 /* cpl_pass_establish.tos_tid fields */
  558 #define S_PASS_OPEN_TID    0
  559 #define M_PASS_OPEN_TID    0xFFFFFF
  560 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
  561 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
  562 
  563 #define S_PASS_OPEN_TOS    24
  564 #define M_PASS_OPEN_TOS    0xFF
  565 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
  566 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
  567 
  568 /* cpl_pass_establish.l2t_idx fields */
  569 #define S_L2T_IDX16    5
  570 #define M_L2T_IDX16    0x7FF
  571 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16)
  572 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16)
  573 
  574 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */
  575 #define G_TCPOPT_WSCALE_OK(x)  (((x) >> 5) & 1)
  576 #define G_TCPOPT_SACK(x)       (((x) >> 6) & 1)
  577 #define G_TCPOPT_TSTAMP(x)     (((x) >> 7) & 1)
  578 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
  579 #define G_TCPOPT_MSS(x)        (((x) >> 12) & 0xf)
  580 
  581 struct cpl_pass_accept_req {
  582         RSS_HDR
  583         union opcode_tid ot;
  584         __be16 local_port;
  585         __be16 peer_port;
  586         __be32 local_ip;
  587         __be32 peer_ip;
  588         __be32 tos_tid;
  589         struct tcp_options tcp_options;
  590         __u8  dst_mac[6];
  591         __be16 vlan_tag;
  592         __u8  src_mac[6];
  593 #if defined(__LITTLE_ENDIAN_BITFIELD)
  594         __u8  :3;
  595         __u8  addr_idx:3;
  596         __u8  port_idx:1;
  597         __u8  exact_match:1;
  598 #else
  599         __u8  exact_match:1;
  600         __u8  port_idx:1;
  601         __u8  addr_idx:3;
  602         __u8  :3;
  603 #endif
  604         __u8  rsvd;
  605         __be32 rcv_isn;
  606         __be32 rsvd2;
  607 };
  608 
  609 struct cpl_pass_accept_rpl {
  610         WR_HDR;
  611         union opcode_tid ot;
  612         __be32 opt2;
  613         __be32 rsvd;
  614         __be32 peer_ip;
  615         __be32 opt0h;
  616         __be32 opt0l_status;
  617 };
  618 
  619 struct cpl_act_open_req {
  620         WR_HDR;
  621         union opcode_tid ot;
  622         __be16 local_port;
  623         __be16 peer_port;
  624         __be32 local_ip;
  625         __be32 peer_ip;
  626         __be32 opt0h;
  627         __be32 opt0l;
  628         __be32 params;
  629         __be32 opt2;
  630 };
  631 
  632 /* cpl_act_open_req.params fields */
  633 #define S_AOPEN_VLAN_PRI    9
  634 #define M_AOPEN_VLAN_PRI    0x3
  635 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI)
  636 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI)
  637 
  638 #define S_AOPEN_VLAN_PRI_VALID    11
  639 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID)
  640 #define F_AOPEN_VLAN_PRI_VALID    V_AOPEN_VLAN_PRI_VALID(1U)
  641 
  642 #define S_AOPEN_PKT_TYPE    12
  643 #define M_AOPEN_PKT_TYPE    0x3
  644 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE)
  645 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE)
  646 
  647 #define S_AOPEN_MAC_MATCH    14
  648 #define M_AOPEN_MAC_MATCH    0x1F
  649 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH)
  650 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH)
  651 
  652 #define S_AOPEN_MAC_MATCH_VALID    19
  653 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID)
  654 #define F_AOPEN_MAC_MATCH_VALID    V_AOPEN_MAC_MATCH_VALID(1U)
  655 
  656 #define S_AOPEN_IFF_VLAN    20
  657 #define M_AOPEN_IFF_VLAN    0xFFF
  658 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN)
  659 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN)
  660 
  661 struct cpl_act_open_rpl {
  662         RSS_HDR
  663         union opcode_tid ot;
  664         __be16 local_port;
  665         __be16 peer_port;
  666         __be32 local_ip;
  667         __be32 peer_ip;
  668         __be32 atid;
  669         __u8  rsvd[3];
  670         __u8  status;
  671 };
  672 
  673 struct cpl_act_establish {
  674         RSS_HDR
  675         union opcode_tid ot;
  676         __be16 local_port;
  677         __be16 peer_port;
  678         __be32 local_ip;
  679         __be32 peer_ip;
  680         __be32 tos_tid;
  681         __be16 l2t_idx;
  682         __be16 tcp_opt;
  683         __be32 snd_isn;
  684         __be32 rcv_isn;
  685 };
  686 
  687 struct cpl_get_tcb {
  688         WR_HDR;
  689         union opcode_tid ot;
  690         __be16 cpuno;
  691         __be16 rsvd;
  692 };
  693 
  694 struct cpl_get_tcb_rpl {
  695         RSS_HDR
  696         union opcode_tid ot;
  697         __u8 rsvd;
  698         __u8 status;
  699         __be16 len;
  700 };
  701 
  702 struct cpl_set_tcb {
  703         WR_HDR;
  704         union opcode_tid ot;
  705         __u8  reply;
  706         __u8  cpu_idx;
  707         __be16 len;
  708 };
  709 
  710 /* cpl_set_tcb.reply fields */
  711 #define S_NO_REPLY    7
  712 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
  713 #define F_NO_REPLY    V_NO_REPLY(1U)
  714 
  715 struct cpl_set_tcb_field {
  716         WR_HDR;
  717         union opcode_tid ot;
  718         __u8  reply;
  719         __u8  cpu_idx;
  720         __be16 word;
  721         __be64 mask;
  722         __be64 val;
  723 };
  724 
  725 struct cpl_set_tcb_rpl {
  726         RSS_HDR
  727         union opcode_tid ot;
  728         __u8 rsvd[3];
  729         __u8 status;
  730 };
  731 
  732 struct cpl_pcmd {
  733         WR_HDR;
  734         union opcode_tid ot;
  735         __u8 rsvd[3];
  736 #if defined(__LITTLE_ENDIAN_BITFIELD)
  737         __u8 src:1;
  738         __u8 bundle:1;
  739         __u8 channel:1;
  740         __u8 :5;
  741 #else
  742         __u8 :5;
  743         __u8 channel:1;
  744         __u8 bundle:1;
  745         __u8 src:1;
  746 #endif
  747         __be32 pcmd_parm[2];
  748 };
  749 
  750 struct cpl_pcmd_reply {
  751         RSS_HDR
  752         union opcode_tid ot;
  753         __u8  status;
  754         __u8  rsvd;
  755         __be16 len;
  756 };
  757 
  758 struct cpl_close_con_req {
  759         WR_HDR;
  760         union opcode_tid ot;
  761         __be32 rsvd;
  762 };
  763 
  764 struct cpl_close_con_rpl {
  765         RSS_HDR
  766         union opcode_tid ot;
  767         __u8  rsvd[3];
  768         __u8  status;
  769         __be32 snd_nxt;
  770         __be32 rcv_nxt;
  771 };
  772 
  773 struct cpl_close_listserv_req {
  774         WR_HDR;
  775         union opcode_tid ot;
  776         __u8  rsvd0;
  777         __u8  cpu_idx;
  778         __be16 rsvd1;
  779 };
  780 
  781 struct cpl_close_listserv_rpl {
  782         RSS_HDR
  783         union opcode_tid ot;
  784         __u8 rsvd[3];
  785         __u8 status;
  786 };
  787 
  788 struct cpl_abort_req_rss {
  789         RSS_HDR
  790         union opcode_tid ot;
  791         __be32 rsvd0;
  792         __u8  rsvd1;
  793         __u8  status;
  794         __u8  rsvd2[6];
  795 };
  796 
  797 struct cpl_abort_req {
  798         WR_HDR;
  799         union opcode_tid ot;
  800         __be32 rsvd0;
  801         __u8  rsvd1;
  802         __u8  cmd;
  803         __u8  rsvd2[6];
  804 };
  805 
  806 struct cpl_abort_rpl_rss {
  807         RSS_HDR
  808         union opcode_tid ot;
  809         __be32 rsvd0;
  810         __u8  rsvd1;
  811         __u8  status;
  812         __u8  rsvd2[6];
  813 };
  814 
  815 struct cpl_abort_rpl {
  816         WR_HDR;
  817         union opcode_tid ot;
  818         __be32 rsvd0;
  819         __u8  rsvd1;
  820         __u8  cmd;
  821         __u8  rsvd2[6];
  822 };
  823 
  824 struct cpl_peer_close {
  825         RSS_HDR
  826         union opcode_tid ot;
  827         __be32 rcv_nxt;
  828 };
  829 
  830 struct tx_data_wr {
  831         WR_HDR;
  832         __be32 len;
  833         __be32 flags;
  834         __be32 sndseq;
  835         __be32 param;
  836 };
  837 
  838 /* tx_data_wr.flags fields */
  839 #define S_TX_ACK_PAGES          21
  840 #define M_TX_ACK_PAGES          0x7
  841 #define V_TX_ACK_PAGES(x)       ((x) << S_TX_ACK_PAGES)
  842 #define G_TX_ACK_PAGES(x)       (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
  843 
  844 /* tx_data_wr.param fields */
  845 #define S_TX_PORT    0
  846 #define M_TX_PORT    0x7
  847 #define V_TX_PORT(x) ((x) << S_TX_PORT)
  848 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
  849 
  850 #define S_TX_MSS    4
  851 #define M_TX_MSS    0xF
  852 #define V_TX_MSS(x) ((x) << S_TX_MSS)
  853 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
  854 
  855 #define S_TX_QOS    8
  856 #define M_TX_QOS    0xFF
  857 #define V_TX_QOS(x) ((x) << S_TX_QOS)
  858 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
  859 
  860 #define S_TX_SNDBUF 16
  861 #define M_TX_SNDBUF 0xFFFF
  862 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
  863 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
  864 
  865 struct cpl_tx_data {
  866         union opcode_tid ot;
  867         __be32 len;
  868         __be32 rsvd;
  869         __be16 urg;
  870         __be16 flags;
  871 };
  872 
  873 /* cpl_tx_data.flags fields */
  874 #define S_TX_ULP_SUBMODE    6
  875 #define M_TX_ULP_SUBMODE    0xF
  876 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
  877 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
  878 
  879 #define S_TX_ULP_MODE    10
  880 #define M_TX_ULP_MODE    0xF
  881 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
  882 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
  883 
  884 #define S_TX_SHOVE    14
  885 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
  886 #define F_TX_SHOVE    V_TX_SHOVE(1U)
  887 
  888 #define S_TX_MORE    15
  889 #define V_TX_MORE(x) ((x) << S_TX_MORE)
  890 #define F_TX_MORE    V_TX_MORE(1U)
  891 
  892 /* additional tx_data_wr.flags fields */
  893 #define S_TX_CPU_IDX    0
  894 #define M_TX_CPU_IDX    0x3F
  895 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
  896 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
  897 
  898 #define S_TX_URG    16
  899 #define V_TX_URG(x) ((x) << S_TX_URG)
  900 #define F_TX_URG    V_TX_URG(1U)
  901 
  902 #define S_TX_CLOSE    17
  903 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
  904 #define F_TX_CLOSE    V_TX_CLOSE(1U)
  905 
  906 #define S_TX_INIT    18
  907 #define V_TX_INIT(x) ((x) << S_TX_INIT)
  908 #define F_TX_INIT    V_TX_INIT(1U)
  909 
  910 #define S_TX_IMM_ACK    19
  911 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
  912 #define F_TX_IMM_ACK    V_TX_IMM_ACK(1U)
  913 
  914 #define S_TX_IMM_DMA    20
  915 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
  916 #define F_TX_IMM_DMA    V_TX_IMM_DMA(1U)
  917 
  918 struct cpl_tx_data_ack {
  919         RSS_HDR
  920         union opcode_tid ot;
  921         __be32 ack_seq;
  922 };
  923 
  924 struct cpl_wr_ack {
  925         RSS_HDR
  926         union opcode_tid ot;
  927         __be16 credits;
  928         __be16 rsvd;
  929         __be32 snd_nxt;
  930         __be32 snd_una;
  931 };
  932 
  933 struct cpl_sge_ec_cr_return {
  934         RSS_HDR
  935         union opcode_tid ot;
  936         __be16 sge_ec_id;
  937         __u8 cr;
  938         __u8 rsvd;
  939 };
  940 
  941 struct cpl_rdma_ec_status {
  942         RSS_HDR
  943         union opcode_tid ot;
  944         __u8  rsvd[3];
  945         __u8  status;
  946 };
  947 
  948 struct mngt_pktsched_wr {
  949         WR_HDR;
  950         __u8  mngt_opcode;
  951         __u8  rsvd[7];
  952         __u8  sched;
  953         __u8  idx;
  954         __u8  min;
  955         __u8  max;
  956         __u8  binding;
  957         __u8  rsvd1[3];
  958 };
  959 
  960 struct cpl_iscsi_hdr {
  961         RSS_HDR
  962         union opcode_tid ot;
  963         __be16 pdu_len_ddp;
  964         __be16 len;
  965         __be32 seq;
  966         __be16 urg;
  967         __u8  rsvd;
  968         __u8  status;
  969 };
  970 
  971 /* cpl_iscsi_hdr.pdu_len_ddp fields */
  972 #define S_ISCSI_PDU_LEN    0
  973 #define M_ISCSI_PDU_LEN    0x7FFF
  974 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
  975 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
  976 
  977 #define S_ISCSI_DDP    15
  978 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
  979 #define F_ISCSI_DDP    V_ISCSI_DDP(1U)
  980 
  981 struct cpl_rx_data {
  982         RSS_HDR
  983         union opcode_tid ot;
  984         __be16 rsvd;
  985         __be16 len;
  986         __be32 seq;
  987         __be16 urg;
  988 #if defined(__LITTLE_ENDIAN_BITFIELD)
  989         __u8  dack_mode:2;
  990         __u8  psh:1;
  991         __u8  heartbeat:1;
  992         __u8  ddp_off:1;
  993         __u8  :3;
  994 #else
  995         __u8  :3;
  996         __u8  ddp_off:1;
  997         __u8  heartbeat:1;
  998         __u8  psh:1;
  999         __u8  dack_mode:2;
 1000 #endif
 1001         __u8  status;
 1002 };
 1003 
 1004 struct cpl_rx_data_ack {
 1005         WR_HDR;
 1006         union opcode_tid ot;
 1007         __be32 credit_dack;
 1008 };
 1009 
 1010 /* cpl_rx_data_ack.ack_seq fields */
 1011 #define S_RX_CREDITS    0
 1012 #define M_RX_CREDITS    0x7FFFFFF
 1013 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
 1014 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
 1015 
 1016 #define S_RX_MODULATE    27
 1017 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE)
 1018 #define F_RX_MODULATE    V_RX_MODULATE(1U)
 1019 
 1020 #define S_RX_FORCE_ACK    28
 1021 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
 1022 #define F_RX_FORCE_ACK    V_RX_FORCE_ACK(1U)
 1023 
 1024 #define S_RX_DACK_MODE    29
 1025 #define M_RX_DACK_MODE    0x3
 1026 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
 1027 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
 1028 
 1029 #define S_RX_DACK_CHANGE    31
 1030 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
 1031 #define F_RX_DACK_CHANGE    V_RX_DACK_CHANGE(1U)
 1032 
 1033 struct cpl_rx_urg_notify {
 1034         RSS_HDR
 1035         union opcode_tid ot;
 1036         __be32 seq;
 1037 };
 1038 
 1039 struct cpl_rx_ddp_complete {
 1040         RSS_HDR
 1041         union opcode_tid ot;
 1042         __be32 ddp_report;
 1043 };
 1044 
 1045 struct cpl_rx_data_ddp {
 1046         RSS_HDR
 1047         union opcode_tid ot;
 1048         __be16 urg;
 1049         __be16 len;
 1050         __be32 seq;
 1051         union {
 1052                 __be32 nxt_seq;
 1053                 __be32 ddp_report;
 1054         } u;
 1055         __be32 ulp_crc;
 1056         __be32 ddpvld_status;
 1057 };
 1058 
 1059 /* cpl_rx_data_ddp.ddpvld_status fields */
 1060 #define S_DDP_STATUS    0
 1061 #define M_DDP_STATUS    0xFF
 1062 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
 1063 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS)
 1064 
 1065 #define S_DDP_VALID    15
 1066 #define M_DDP_VALID    0x1FFFF
 1067 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
 1068 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
 1069 
 1070 #define S_DDP_PPOD_MISMATCH    15
 1071 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
 1072 #define F_DDP_PPOD_MISMATCH    V_DDP_PPOD_MISMATCH(1U)
 1073 
 1074 #define S_DDP_PDU    16
 1075 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
 1076 #define F_DDP_PDU    V_DDP_PDU(1U)
 1077 
 1078 #define S_DDP_LLIMIT_ERR    17
 1079 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
 1080 #define F_DDP_LLIMIT_ERR    V_DDP_LLIMIT_ERR(1U)
 1081 
 1082 #define S_DDP_PPOD_PARITY_ERR    18
 1083 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
 1084 #define F_DDP_PPOD_PARITY_ERR    V_DDP_PPOD_PARITY_ERR(1U)
 1085 
 1086 #define S_DDP_PADDING_ERR    19
 1087 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
 1088 #define F_DDP_PADDING_ERR    V_DDP_PADDING_ERR(1U)
 1089 
 1090 #define S_DDP_HDRCRC_ERR    20
 1091 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
 1092 #define F_DDP_HDRCRC_ERR    V_DDP_HDRCRC_ERR(1U)
 1093 
 1094 #define S_DDP_DATACRC_ERR    21
 1095 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
 1096 #define F_DDP_DATACRC_ERR    V_DDP_DATACRC_ERR(1U)
 1097 
 1098 #define S_DDP_INVALID_TAG    22
 1099 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
 1100 #define F_DDP_INVALID_TAG    V_DDP_INVALID_TAG(1U)
 1101 
 1102 #define S_DDP_ULIMIT_ERR    23
 1103 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
 1104 #define F_DDP_ULIMIT_ERR    V_DDP_ULIMIT_ERR(1U)
 1105 
 1106 #define S_DDP_OFFSET_ERR    24
 1107 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
 1108 #define F_DDP_OFFSET_ERR    V_DDP_OFFSET_ERR(1U)
 1109 
 1110 #define S_DDP_COLOR_ERR    25
 1111 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
 1112 #define F_DDP_COLOR_ERR    V_DDP_COLOR_ERR(1U)
 1113 
 1114 #define S_DDP_TID_MISMATCH    26
 1115 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
 1116 #define F_DDP_TID_MISMATCH    V_DDP_TID_MISMATCH(1U)
 1117 
 1118 #define S_DDP_INVALID_PPOD    27
 1119 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
 1120 #define F_DDP_INVALID_PPOD    V_DDP_INVALID_PPOD(1U)
 1121 
 1122 #define S_DDP_ULP_MODE    28
 1123 #define M_DDP_ULP_MODE    0xF
 1124 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
 1125 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
 1126 
 1127 /* cpl_rx_data_ddp.ddp_report fields */
 1128 #define S_DDP_OFFSET    0
 1129 #define M_DDP_OFFSET    0x3FFFFF
 1130 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
 1131 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
 1132 
 1133 #define S_DDP_DACK_MODE    22
 1134 #define M_DDP_DACK_MODE    0x3
 1135 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE)
 1136 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE)
 1137 
 1138 #define S_DDP_URG    24
 1139 #define V_DDP_URG(x) ((x) << S_DDP_URG)
 1140 #define F_DDP_URG    V_DDP_URG(1U)
 1141 
 1142 #define S_DDP_PSH    25
 1143 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
 1144 #define F_DDP_PSH    V_DDP_PSH(1U)
 1145 
 1146 #define S_DDP_BUF_COMPLETE    26
 1147 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
 1148 #define F_DDP_BUF_COMPLETE    V_DDP_BUF_COMPLETE(1U)
 1149 
 1150 #define S_DDP_BUF_TIMED_OUT    27
 1151 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
 1152 #define F_DDP_BUF_TIMED_OUT    V_DDP_BUF_TIMED_OUT(1U)
 1153 
 1154 #define S_DDP_BUF_IDX    28
 1155 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
 1156 #define F_DDP_BUF_IDX    V_DDP_BUF_IDX(1U)
 1157 
 1158 struct cpl_tx_pkt {
 1159         WR_HDR;
 1160         __be32 cntrl;
 1161         __be32 len;
 1162 };
 1163 
 1164 struct cpl_tx_pkt_coalesce {
 1165         __be32 cntrl;
 1166         __be32 len;
 1167         __be64 addr;
 1168 };
 1169 
 1170 struct tx_pkt_coalesce_wr {
 1171         WR_HDR;
 1172         struct cpl_tx_pkt_coalesce cpl[0];
 1173 };
 1174 
 1175 struct cpl_tx_pkt_lso {
 1176         WR_HDR;
 1177         __be32 cntrl;
 1178         __be32 len;
 1179 
 1180         __be32 rsvd;
 1181         __be32 lso_info;
 1182 };
 1183 
 1184 struct cpl_tx_pkt_batch_entry {
 1185         __be32 cntrl;
 1186         __be32 len;
 1187         __be64 addr;
 1188 };
 1189 
 1190 struct cpl_tx_pkt_batch {
 1191         WR_HDR;
 1192         struct cpl_tx_pkt_batch_entry pkt_entry[7];
 1193 };
 1194 
 1195 
 1196 /* cpl_tx_pkt*.cntrl fields */
 1197 #define S_TXPKT_VLAN    0
 1198 #define M_TXPKT_VLAN    0xFFFF
 1199 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN)
 1200 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
 1201 
 1202 #define S_TXPKT_INTF    16
 1203 #define M_TXPKT_INTF    0xF
 1204 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
 1205 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
 1206 
 1207 #define S_TXPKT_IPCSUM_DIS    20
 1208 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS)
 1209 #define F_TXPKT_IPCSUM_DIS    V_TXPKT_IPCSUM_DIS(1U)
 1210 
 1211 #define S_TXPKT_L4CSUM_DIS    21
 1212 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS)
 1213 #define F_TXPKT_L4CSUM_DIS    V_TXPKT_L4CSUM_DIS(1U)
 1214 
 1215 #define S_TXPKT_VLAN_VLD    22
 1216 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD)
 1217 #define F_TXPKT_VLAN_VLD    V_TXPKT_VLAN_VLD(1U)
 1218 
 1219 #define S_TXPKT_LOOPBACK    23
 1220 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
 1221 #define F_TXPKT_LOOPBACK    V_TXPKT_LOOPBACK(1U)
 1222 
 1223 #define S_TXPKT_OPCODE    24
 1224 #define M_TXPKT_OPCODE    0xFF
 1225 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
 1226 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
 1227 
 1228 /* cpl_tx_pkt_lso.lso_info fields */
 1229 #define S_LSO_MSS    0
 1230 #define M_LSO_MSS    0x3FFF
 1231 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
 1232 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
 1233 
 1234 #define S_LSO_ETH_TYPE    14
 1235 #define M_LSO_ETH_TYPE    0x3
 1236 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE)
 1237 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE)
 1238 
 1239 #define S_LSO_TCPHDR_WORDS    16
 1240 #define M_LSO_TCPHDR_WORDS    0xF
 1241 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS)
 1242 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS)
 1243 
 1244 #define S_LSO_IPHDR_WORDS    20
 1245 #define M_LSO_IPHDR_WORDS    0xF
 1246 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS)
 1247 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS)
 1248 
 1249 #define S_LSO_IPV6    24
 1250 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
 1251 #define F_LSO_IPV6    V_LSO_IPV6(1U)
 1252 
 1253 struct cpl_trace_pkt {
 1254 #ifdef CHELSIO_FW
 1255         __u8 rss_opcode;
 1256 #if defined(__LITTLE_ENDIAN_BITFIELD)
 1257         __u8 err:1;
 1258         __u8 :7;
 1259 #else
 1260         __u8 :7;
 1261         __u8 err:1;
 1262 #endif
 1263         __u8 rsvd0;
 1264 #if defined(__LITTLE_ENDIAN_BITFIELD)
 1265         __u8 qid:4;
 1266         __u8 :4;
 1267 #else
 1268         __u8 :4;
 1269         __u8 qid:4;
 1270 #endif
 1271         __be32 tstamp;
 1272 #endif /* CHELSIO_FW */
 1273 
 1274         __u8  opcode;
 1275 #if defined(__LITTLE_ENDIAN_BITFIELD)
 1276         __u8  iff:4;
 1277         __u8  :4;
 1278 #else
 1279         __u8  :4;
 1280         __u8  iff:4;
 1281 #endif
 1282         __u8  rsvd[4];
 1283         __be16 len;
 1284 };
 1285 
 1286 struct cpl_rx_pkt {
 1287         RSS_HDR
 1288         __u8 opcode;
 1289 #if defined(__LITTLE_ENDIAN_BITFIELD)
 1290         __u8 iff:4;
 1291         __u8 csum_valid:1;
 1292         __u8 ipmi_pkt:1;
 1293         __u8 vlan_valid:1;
 1294         __u8 fragment:1;
 1295 #else
 1296         __u8 fragment:1;
 1297         __u8 vlan_valid:1;
 1298         __u8 ipmi_pkt:1;
 1299         __u8 csum_valid:1;
 1300         __u8 iff:4;
 1301 #endif
 1302         __be16 csum;
 1303         __be16 vlan;
 1304         __be16 len;
 1305 };
 1306 
 1307 struct cpl_l2t_write_req {
 1308         WR_HDR;
 1309         union opcode_tid ot;
 1310         __be32 params;
 1311         __u8  rsvd;
 1312         __u8  port_idx;
 1313         __u8  dst_mac[6];
 1314 };
 1315 
 1316 /* cpl_l2t_write_req.params fields */
 1317 #define S_L2T_W_IDX    0
 1318 #define M_L2T_W_IDX    0x7FF
 1319 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
 1320 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)
 1321 
 1322 #define S_L2T_W_VLAN    11
 1323 #define M_L2T_W_VLAN    0xFFF
 1324 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN)
 1325 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN)
 1326 
 1327 #define S_L2T_W_IFF    23
 1328 #define M_L2T_W_IFF    0xF
 1329 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF)
 1330 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF)
 1331 
 1332 #define S_L2T_W_PRIO    27
 1333 #define M_L2T_W_PRIO    0x7
 1334 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO)
 1335 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO)
 1336 
 1337 struct cpl_l2t_write_rpl {
 1338         RSS_HDR
 1339         union opcode_tid ot;
 1340         __u8 status;
 1341         __u8 rsvd[3];
 1342 };
 1343 
 1344 struct cpl_l2t_read_req {
 1345         WR_HDR;
 1346         union opcode_tid ot;
 1347         __be16 rsvd;
 1348         __be16 l2t_idx;
 1349 };
 1350 
 1351 struct cpl_l2t_read_rpl {
 1352         RSS_HDR
 1353         union opcode_tid ot;
 1354         __be32 params;
 1355         __u8 rsvd[2];
 1356         __u8 dst_mac[6];
 1357 };
 1358 
 1359 /* cpl_l2t_read_rpl.params fields */
 1360 #define S_L2T_R_PRIO    0
 1361 #define M_L2T_R_PRIO    0x7
 1362 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO)
 1363 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO)
 1364 
 1365 #define S_L2T_R_VLAN    8
 1366 #define M_L2T_R_VLAN    0xFFF
 1367 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN)
 1368 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN)
 1369 
 1370 #define S_L2T_R_IFF    20
 1371 #define M_L2T_R_IFF    0xF
 1372 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF)
 1373 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF)
 1374 
 1375 #define S_L2T_STATUS    24
 1376 #define M_L2T_STATUS    0xFF
 1377 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS)
 1378 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS)
 1379 
 1380 struct cpl_smt_write_req {
 1381         WR_HDR;
 1382         union opcode_tid ot;
 1383         __u8 rsvd0;
 1384 #if defined(__LITTLE_ENDIAN_BITFIELD)
 1385         __u8 mtu_idx:4;
 1386         __u8 iff:4;
 1387 #else
 1388         __u8 iff:4;
 1389         __u8 mtu_idx:4;
 1390 #endif
 1391         __be16 rsvd2;
 1392         __be16 rsvd3;
 1393         __u8  src_mac1[6];
 1394         __be16 rsvd4;
 1395         __u8  src_mac0[6];
 1396 };
 1397 
 1398 struct cpl_smt_write_rpl {
 1399         RSS_HDR
 1400         union opcode_tid ot;
 1401         __u8 status;
 1402         __u8 rsvd[3];
 1403 };
 1404 
 1405 struct cpl_smt_read_req {
 1406         WR_HDR;
 1407         union opcode_tid ot;
 1408         __u8 rsvd0;
 1409 #if defined(__LITTLE_ENDIAN_BITFIELD)
 1410         __u8 :4;
 1411         __u8 iff:4;
 1412 #else
 1413         __u8 iff:4;
 1414         __u8 :4;
 1415 #endif
 1416         __be16 rsvd2;
 1417 };
 1418 
 1419 struct cpl_smt_read_rpl {
 1420         RSS_HDR
 1421         union opcode_tid ot;
 1422         __u8 status;
 1423 #if defined(__LITTLE_ENDIAN_BITFIELD)
 1424         __u8 mtu_idx:4;
 1425         __u8 :4;
 1426 #else
 1427         __u8 :4;
 1428         __u8 mtu_idx:4;
 1429 #endif
 1430         __be16 rsvd2;
 1431         __be16 rsvd3;
 1432         __u8  src_mac1[6];
 1433         __be16 rsvd4;
 1434         __u8  src_mac0[6];
 1435 };
 1436 
 1437 struct cpl_rte_delete_req {
 1438         WR_HDR;
 1439         union opcode_tid ot;
 1440         __be32 params;
 1441 };
 1442 
 1443 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */
 1444 #define S_RTE_REQ_LUT_IX    8
 1445 #define M_RTE_REQ_LUT_IX    0x7FF
 1446 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
 1447 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
 1448 
 1449 #define S_RTE_REQ_LUT_BASE    19
 1450 #define M_RTE_REQ_LUT_BASE    0x7FF
 1451 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
 1452 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
 1453 
 1454 #define S_RTE_READ_REQ_SELECT    31
 1455 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
 1456 #define F_RTE_READ_REQ_SELECT    V_RTE_READ_REQ_SELECT(1U)
 1457 
 1458 struct cpl_rte_delete_rpl {
 1459         RSS_HDR
 1460         union opcode_tid ot;
 1461         __u8 status;
 1462         __u8 rsvd[3];
 1463 };
 1464 
 1465 struct cpl_rte_write_req {
 1466         WR_HDR;
 1467         union opcode_tid ot;
 1468 #if defined(__LITTLE_ENDIAN_BITFIELD)
 1469         __u8 :6;
 1470         __u8 write_tcam:1;
 1471         __u8 write_l2t_lut:1;
 1472 #else
 1473         __u8 write_l2t_lut:1;
 1474         __u8 write_tcam:1;
 1475         __u8 :6;
 1476 #endif
 1477         __u8 rsvd[3];
 1478         __be32 lut_params;
 1479         __be16 rsvd2;
 1480         __be16 l2t_idx;
 1481         __be32 netmask;
 1482         __be32 faddr;
 1483 };
 1484 
 1485 /* cpl_rte_write_req.lut_params fields */
 1486 #define S_RTE_WRITE_REQ_LUT_IX    10
 1487 #define M_RTE_WRITE_REQ_LUT_IX    0x7FF
 1488 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX)
 1489 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX)
 1490 
 1491 #define S_RTE_WRITE_REQ_LUT_BASE    21
 1492 #define M_RTE_WRITE_REQ_LUT_BASE    0x7FF
 1493 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE)
 1494 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE)
 1495 
 1496 struct cpl_rte_write_rpl {
 1497         RSS_HDR
 1498         union opcode_tid ot;
 1499         __u8 status;
 1500         __u8 rsvd[3];
 1501 };
 1502 
 1503 struct cpl_rte_read_req {
 1504         WR_HDR;
 1505         union opcode_tid ot;
 1506         __be32 params;
 1507 };
 1508 
 1509 struct cpl_rte_read_rpl {
 1510         RSS_HDR
 1511         union opcode_tid ot;
 1512         __u8 status;
 1513         __u8 rsvd0;
 1514         __be16 l2t_idx;
 1515 #if defined(__LITTLE_ENDIAN_BITFIELD)
 1516         __u8 :7;
 1517         __u8 select:1;
 1518 #else
 1519         __u8 select:1;
 1520         __u8 :7;
 1521 #endif
 1522         __u8 rsvd2[3];
 1523         __be32 addr;
 1524 };
 1525 
 1526 struct cpl_tid_release {
 1527         WR_HDR;
 1528         union opcode_tid ot;
 1529         __be32 rsvd;
 1530 };
 1531 
 1532 struct cpl_barrier {
 1533         WR_HDR;
 1534         __u8 opcode;
 1535         __u8 rsvd[7];
 1536 };
 1537 
 1538 struct cpl_rdma_read_req {
 1539         __u8 opcode;
 1540         __u8 rsvd[15];
 1541 };
 1542 
 1543 struct cpl_rdma_terminate {
 1544 #ifdef CHELSIO_FW
 1545         __u8 opcode;
 1546         __u8 rsvd[2];
 1547 #if defined(__LITTLE_ENDIAN_BITFIELD)
 1548         __u8 rspq:3;
 1549         __u8 :5;
 1550 #else
 1551         __u8 :5;
 1552         __u8 rspq:3;
 1553 #endif
 1554         __be32 tid_len;
 1555 #endif
 1556         __be32 msn;
 1557         __be32 mo;
 1558         __u8  data[0];
 1559 };
 1560 
 1561 /* cpl_rdma_terminate.tid_len fields */
 1562 #define S_FLIT_CNT    0
 1563 #define M_FLIT_CNT    0xFF
 1564 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT)
 1565 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT)
 1566 
 1567 #define S_TERM_TID    8
 1568 #define M_TERM_TID    0xFFFFF
 1569 #define V_TERM_TID(x) ((x) << S_TERM_TID)
 1570 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
 1571 
 1572 /* ULP_TX opcodes */
 1573 enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 };
 1574 
 1575 #define S_ULPTX_CMD    28
 1576 #define M_ULPTX_CMD    0xF
 1577 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
 1578 
 1579 #define S_ULPTX_NFLITS    0
 1580 #define M_ULPTX_NFLITS    0xFF
 1581 #define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
 1582 
 1583 struct ulp_mem_io {
 1584         WR_HDR;
 1585         __be32 cmd_lock_addr;
 1586         __be32 len;
 1587 };
 1588 
 1589 /* ulp_mem_io.cmd_lock_addr fields */
 1590 #define S_ULP_MEMIO_ADDR    0
 1591 #define M_ULP_MEMIO_ADDR    0x7FFFFFF
 1592 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
 1593 
 1594 #define S_ULP_MEMIO_LOCK    27
 1595 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
 1596 #define F_ULP_MEMIO_LOCK    V_ULP_MEMIO_LOCK(1U)
 1597 
 1598 /* ulp_mem_io.len fields */
 1599 #define S_ULP_MEMIO_DATA_LEN    28
 1600 #define M_ULP_MEMIO_DATA_LEN    0xF
 1601 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
 1602 
 1603 struct ulp_txpkt {
 1604         __be32 cmd_dest;
 1605         __be32 len;
 1606 };
 1607 
 1608 /* ulp_txpkt.cmd_dest fields */
 1609 #define S_ULP_TXPKT_DEST    24
 1610 #define M_ULP_TXPKT_DEST    0xF
 1611 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
 1612 
 1613 #endif  /* T3_CPL_H */

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