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sys/dev/cxgb/common/cxgb_t3_cpl.h
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1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD: releng/6.4/sys/dev/cxgb/common/cxgb_t3_cpl.h 171884 2007-08-18 09:10:26Z kmacy $ 29 30 ***************************************************************************/ 31 #ifndef T3_CPL_H 32 #define T3_CPL_H 33 34 enum CPL_opcode { 35 CPL_PASS_OPEN_REQ = 0x1, 36 CPL_PASS_ACCEPT_RPL = 0x2, 37 CPL_ACT_OPEN_REQ = 0x3, 38 CPL_SET_TCB = 0x4, 39 CPL_SET_TCB_FIELD = 0x5, 40 CPL_GET_TCB = 0x6, 41 CPL_PCMD = 0x7, 42 CPL_CLOSE_CON_REQ = 0x8, 43 CPL_CLOSE_LISTSRV_REQ = 0x9, 44 CPL_ABORT_REQ = 0xA, 45 CPL_ABORT_RPL = 0xB, 46 CPL_TX_DATA = 0xC, 47 CPL_RX_DATA_ACK = 0xD, 48 CPL_TX_PKT = 0xE, 49 CPL_RTE_DELETE_REQ = 0xF, 50 CPL_RTE_WRITE_REQ = 0x10, 51 CPL_RTE_READ_REQ = 0x11, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_L2T_READ_REQ = 0x13, 54 CPL_SMT_WRITE_REQ = 0x14, 55 CPL_SMT_READ_REQ = 0x15, 56 CPL_TX_PKT_LSO = 0x16, 57 CPL_PCMD_READ = 0x17, 58 CPL_BARRIER = 0x18, 59 CPL_TID_RELEASE = 0x1A, 60 61 CPL_CLOSE_LISTSRV_RPL = 0x20, 62 CPL_ERROR = 0x21, 63 CPL_GET_TCB_RPL = 0x22, 64 CPL_L2T_WRITE_RPL = 0x23, 65 CPL_PCMD_READ_RPL = 0x24, 66 CPL_PCMD_RPL = 0x25, 67 CPL_PEER_CLOSE = 0x26, 68 CPL_RTE_DELETE_RPL = 0x27, 69 CPL_RTE_WRITE_RPL = 0x28, 70 CPL_RX_DDP_COMPLETE = 0x29, 71 CPL_RX_PHYS_ADDR = 0x2A, 72 CPL_RX_PKT = 0x2B, 73 CPL_RX_URG_NOTIFY = 0x2C, 74 CPL_SET_TCB_RPL = 0x2D, 75 CPL_SMT_WRITE_RPL = 0x2E, 76 CPL_TX_DATA_ACK = 0x2F, 77 78 CPL_ABORT_REQ_RSS = 0x30, 79 CPL_ABORT_RPL_RSS = 0x31, 80 CPL_CLOSE_CON_RPL = 0x32, 81 CPL_ISCSI_HDR = 0x33, 82 CPL_L2T_READ_RPL = 0x34, 83 CPL_RDMA_CQE = 0x35, 84 CPL_RDMA_CQE_READ_RSP = 0x36, 85 CPL_RDMA_CQE_ERR = 0x37, 86 CPL_RTE_READ_RPL = 0x38, 87 CPL_RX_DATA = 0x39, 88 89 CPL_ACT_OPEN_RPL = 0x40, 90 CPL_PASS_OPEN_RPL = 0x41, 91 CPL_RX_DATA_DDP = 0x42, 92 CPL_SMT_READ_RPL = 0x43, 93 94 CPL_ACT_ESTABLISH = 0x50, 95 CPL_PASS_ESTABLISH = 0x51, 96 97 CPL_PASS_ACCEPT_REQ = 0x70, 98 99 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */ 100 101 CPL_TX_DMA_ACK = 0xA0, 102 CPL_RDMA_READ_REQ = 0xA1, 103 CPL_RDMA_TERMINATE = 0xA2, 104 CPL_TRACE_PKT = 0xA3, 105 CPL_RDMA_EC_STATUS = 0xA5, 106 107 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 108 }; 109 110 enum CPL_error { 111 CPL_ERR_NONE = 0, 112 CPL_ERR_TCAM_PARITY = 1, 113 CPL_ERR_TCAM_FULL = 3, 114 CPL_ERR_CONN_RESET = 20, 115 CPL_ERR_CONN_EXIST = 22, 116 CPL_ERR_ARP_MISS = 23, 117 CPL_ERR_BAD_SYN = 24, 118 CPL_ERR_CONN_TIMEDOUT = 30, 119 CPL_ERR_XMIT_TIMEDOUT = 31, 120 CPL_ERR_PERSIST_TIMEDOUT = 32, 121 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 122 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 123 CPL_ERR_RTX_NEG_ADVICE = 35, 124 CPL_ERR_PERSIST_NEG_ADVICE = 36, 125 CPL_ERR_ABORT_FAILED = 42, 126 CPL_ERR_GENERAL = 99 127 }; 128 129 enum { 130 CPL_CONN_POLICY_AUTO = 0, 131 CPL_CONN_POLICY_ASK = 1, 132 CPL_CONN_POLICY_FILTER = 2, 133 CPL_CONN_POLICY_DENY = 3 134 }; 135 136 enum { 137 ULP_MODE_NONE = 0, 138 ULP_MODE_TCP_DDP = 1, 139 ULP_MODE_ISCSI = 2, 140 ULP_MODE_RDMA = 4, 141 ULP_MODE_TCPDDP = 5 142 }; 143 144 enum { 145 ULP_CRC_HEADER = 1 << 0, 146 ULP_CRC_DATA = 1 << 1 147 }; 148 149 enum { 150 CPL_PASS_OPEN_ACCEPT, 151 CPL_PASS_OPEN_REJECT 152 }; 153 154 enum { 155 CPL_ABORT_SEND_RST = 0, 156 CPL_ABORT_NO_RST, 157 CPL_ABORT_POST_CLOSE_REQ = 2 158 }; 159 160 enum { /* TX_PKT_LSO ethernet types */ 161 CPL_ETH_II, 162 CPL_ETH_II_VLAN, 163 CPL_ETH_802_3, 164 CPL_ETH_802_3_VLAN 165 }; 166 167 enum { /* TCP congestion control algorithms */ 168 CONG_ALG_RENO, 169 CONG_ALG_TAHOE, 170 CONG_ALG_NEWRENO, 171 CONG_ALG_HIGHSPEED 172 }; 173 174 enum { /* RSS hash type */ 175 RSS_HASH_NONE = 0, 176 RSS_HASH_2_TUPLE = 1 << 0, 177 RSS_HASH_4_TUPLE = 1 << 1 178 }; 179 180 union opcode_tid { 181 __be32 opcode_tid; 182 __u8 opcode; 183 }; 184 185 #define S_OPCODE 24 186 #define V_OPCODE(x) ((x) << S_OPCODE) 187 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) 188 #define G_TID(x) ((x) & 0xFFFFFF) 189 190 #define S_HASHTYPE 22 191 #define M_HASHTYPE 0x3 192 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 193 194 #define S_QNUM 0 195 #define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF) 196 197 /* tid is assumed to be 24-bits */ 198 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid)) 199 200 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 201 202 /* extract the TID from a CPL command */ 203 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 204 205 struct tcp_options { 206 __be16 mss; 207 __u8 wsf; 208 #if defined(__LITTLE_ENDIAN_BITFIELD) 209 __u8 :5; 210 __u8 ecn:1; 211 __u8 sack:1; 212 __u8 tstamp:1; 213 #else 214 __u8 tstamp:1; 215 __u8 sack:1; 216 __u8 ecn:1; 217 __u8 :5; 218 #endif 219 }; 220 221 struct rss_header { 222 __u8 opcode; 223 #if defined(__LITTLE_ENDIAN_BITFIELD) 224 __u8 cpu_idx:6; 225 __u8 hash_type:2; 226 #else 227 __u8 hash_type:2; 228 __u8 cpu_idx:6; 229 #endif 230 __be16 cq_idx; 231 __be32 rss_hash_val; 232 }; 233 234 #ifndef CHELSIO_FW 235 struct work_request_hdr { 236 __be32 wr_hi; 237 __be32 wr_lo; 238 }; 239 240 /* wr_hi fields */ 241 #define S_WR_SGE_CREDITS 0 242 #define M_WR_SGE_CREDITS 0xFF 243 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS) 244 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS) 245 246 #define S_WR_SGLSFLT 8 247 #define M_WR_SGLSFLT 0xFF 248 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT) 249 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT) 250 251 #define S_WR_BCNTLFLT 16 252 #define M_WR_BCNTLFLT 0xF 253 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT) 254 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT) 255 256 /* Applicable to BYPASS WRs only: the uP will added a CPL_BARRIER before 257 * and after the BYPASS WR if the ATOMIC bit is set. 258 */ 259 #define S_WR_ATOMIC 16 260 #define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC) 261 #define F_WR_ATOMIC V_WR_ATOMIC(1U) 262 263 /* Applicable to BYPASS WRs only: the uP will flush buffered non abort 264 * related WRs. 265 */ 266 #define S_WR_FLUSH 17 267 #define V_WR_FLUSH(x) ((x) << S_WR_FLUSH) 268 #define F_WR_FLUSH V_WR_FLUSH(1U) 269 270 #define S_WR_DATATYPE 20 271 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE) 272 #define F_WR_DATATYPE V_WR_DATATYPE(1U) 273 274 #define S_WR_COMPL 21 275 #define V_WR_COMPL(x) ((x) << S_WR_COMPL) 276 #define F_WR_COMPL V_WR_COMPL(1U) 277 278 #define S_WR_EOP 22 279 #define V_WR_EOP(x) ((x) << S_WR_EOP) 280 #define F_WR_EOP V_WR_EOP(1U) 281 282 #define S_WR_SOP 23 283 #define V_WR_SOP(x) ((x) << S_WR_SOP) 284 #define F_WR_SOP V_WR_SOP(1U) 285 286 #define S_WR_OP 24 287 #define M_WR_OP 0xFF 288 #define V_WR_OP(x) ((x) << S_WR_OP) 289 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 290 291 /* wr_lo fields */ 292 #define S_WR_LEN 0 293 #define M_WR_LEN 0xFF 294 #define V_WR_LEN(x) ((x) << S_WR_LEN) 295 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN) 296 297 #define S_WR_TID 8 298 #define M_WR_TID 0xFFFFF 299 #define V_WR_TID(x) ((x) << S_WR_TID) 300 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID) 301 302 #define S_WR_CR_FLUSH 30 303 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH) 304 #define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U) 305 306 #define S_WR_GEN 31 307 #define V_WR_GEN(x) ((x) << S_WR_GEN) 308 #define F_WR_GEN V_WR_GEN(1U) 309 310 # define WR_HDR struct work_request_hdr wr 311 # define RSS_HDR 312 #else 313 # define WR_HDR 314 # define RSS_HDR struct rss_header rss_hdr; 315 #endif 316 317 /* option 0 lower-half fields */ 318 #define S_CPL_STATUS 0 319 #define M_CPL_STATUS 0xFF 320 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS) 321 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS) 322 323 #define S_INJECT_TIMER 6 324 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 325 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 326 327 #define S_NO_OFFLOAD 7 328 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD) 329 #define F_NO_OFFLOAD V_NO_OFFLOAD(1U) 330 331 #define S_ULP_MODE 8 332 #define M_ULP_MODE 0xF 333 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 334 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 335 336 #define S_RCV_BUFSIZ 12 337 #define M_RCV_BUFSIZ 0x3FFF 338 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 339 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 340 341 #define S_TOS 26 342 #define M_TOS 0x3F 343 #define V_TOS(x) ((x) << S_TOS) 344 #define G_TOS(x) (((x) >> S_TOS) & M_TOS) 345 346 /* option 0 upper-half fields */ 347 #define S_DELACK 0 348 #define V_DELACK(x) ((x) << S_DELACK) 349 #define F_DELACK V_DELACK(1U) 350 351 #define S_NO_CONG 1 352 #define V_NO_CONG(x) ((x) << S_NO_CONG) 353 #define F_NO_CONG V_NO_CONG(1U) 354 355 #define S_SRC_MAC_SEL 2 356 #define M_SRC_MAC_SEL 0x3 357 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL) 358 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL) 359 360 #define S_L2T_IDX 4 361 #define M_L2T_IDX 0x7FF 362 #define V_L2T_IDX(x) ((x) << S_L2T_IDX) 363 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 364 365 #define S_TX_CHANNEL 15 366 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL) 367 #define F_TX_CHANNEL V_TX_CHANNEL(1U) 368 369 #define S_TCAM_BYPASS 16 370 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS) 371 #define F_TCAM_BYPASS V_TCAM_BYPASS(1U) 372 373 #define S_NAGLE 17 374 #define V_NAGLE(x) ((x) << S_NAGLE) 375 #define F_NAGLE V_NAGLE(1U) 376 377 #define S_WND_SCALE 18 378 #define M_WND_SCALE 0xF 379 #define V_WND_SCALE(x) ((x) << S_WND_SCALE) 380 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 381 382 #define S_KEEP_ALIVE 22 383 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE) 384 #define F_KEEP_ALIVE V_KEEP_ALIVE(1U) 385 386 #define S_MAX_RETRANS 23 387 #define M_MAX_RETRANS 0xF 388 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS) 389 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS) 390 391 #define S_MAX_RETRANS_OVERRIDE 27 392 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE) 393 #define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U) 394 395 #define S_MSS_IDX 28 396 #define M_MSS_IDX 0xF 397 #define V_MSS_IDX(x) ((x) << S_MSS_IDX) 398 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 399 400 /* option 1 fields */ 401 #define S_RSS_ENABLE 0 402 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE) 403 #define F_RSS_ENABLE V_RSS_ENABLE(1U) 404 405 #define S_RSS_MASK_LEN 1 406 #define M_RSS_MASK_LEN 0x7 407 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN) 408 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN) 409 410 #define S_CPU_IDX 4 411 #define M_CPU_IDX 0x3F 412 #define V_CPU_IDX(x) ((x) << S_CPU_IDX) 413 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX) 414 415 #define S_OPT1_VLAN 6 416 #define M_OPT1_VLAN 0xFFF 417 #define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN) 418 #define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN) 419 420 #define S_MAC_MATCH_VALID 18 421 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID) 422 #define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U) 423 424 #define S_CONN_POLICY 19 425 #define M_CONN_POLICY 0x3 426 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 427 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 428 429 #define S_SYN_DEFENSE 21 430 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 431 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 432 433 #define S_VLAN_PRI 22 434 #define M_VLAN_PRI 0x3 435 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI) 436 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI) 437 438 #define S_VLAN_PRI_VALID 24 439 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID) 440 #define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U) 441 442 #define S_PKT_TYPE 25 443 #define M_PKT_TYPE 0x3 444 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE) 445 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE) 446 447 #define S_MAC_MATCH 27 448 #define M_MAC_MATCH 0x1F 449 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH) 450 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH) 451 452 /* option 2 fields */ 453 #define S_CPU_INDEX 0 454 #define M_CPU_INDEX 0x7F 455 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX) 456 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX) 457 458 #define S_CPU_INDEX_VALID 7 459 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID) 460 #define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U) 461 462 #define S_RX_COALESCE 8 463 #define M_RX_COALESCE 0x3 464 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 465 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 466 467 #define S_RX_COALESCE_VALID 10 468 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 469 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 470 471 #define S_CONG_CONTROL_FLAVOR 11 472 #define M_CONG_CONTROL_FLAVOR 0x3 473 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR) 474 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR) 475 476 #define S_PACING_FLAVOR 13 477 #define M_PACING_FLAVOR 0x3 478 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR) 479 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR) 480 481 #define S_FLAVORS_VALID 15 482 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID) 483 #define F_FLAVORS_VALID V_FLAVORS_VALID(1U) 484 485 #define S_RX_FC_DISABLE 16 486 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 487 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 488 489 #define S_RX_FC_VALID 17 490 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 491 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 492 493 struct cpl_pass_open_req { 494 WR_HDR; 495 union opcode_tid ot; 496 __be16 local_port; 497 __be16 peer_port; 498 __be32 local_ip; 499 __be32 peer_ip; 500 __be32 opt0h; 501 __be32 opt0l; 502 __be32 peer_netmask; 503 __be32 opt1; 504 }; 505 506 struct cpl_pass_open_rpl { 507 RSS_HDR 508 union opcode_tid ot; 509 __be16 local_port; 510 __be16 peer_port; 511 __be32 local_ip; 512 __be32 peer_ip; 513 __u8 resvd[7]; 514 __u8 status; 515 }; 516 517 struct cpl_pass_establish { 518 RSS_HDR 519 union opcode_tid ot; 520 __be16 local_port; 521 __be16 peer_port; 522 __be32 local_ip; 523 __be32 peer_ip; 524 __be32 tos_tid; 525 __be16 l2t_idx; 526 __be16 tcp_opt; 527 __be32 snd_isn; 528 __be32 rcv_isn; 529 }; 530 531 /* cpl_pass_establish.tos_tid fields */ 532 #define S_PASS_OPEN_TID 0 533 #define M_PASS_OPEN_TID 0xFFFFFF 534 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 535 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 536 537 #define S_PASS_OPEN_TOS 24 538 #define M_PASS_OPEN_TOS 0xFF 539 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 540 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 541 542 /* cpl_pass_establish.l2t_idx fields */ 543 #define S_L2T_IDX16 5 544 #define M_L2T_IDX16 0x7FF 545 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16) 546 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16) 547 548 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */ 549 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 550 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 551 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 552 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 553 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 554 555 struct cpl_pass_accept_req { 556 RSS_HDR 557 union opcode_tid ot; 558 __be16 local_port; 559 __be16 peer_port; 560 __be32 local_ip; 561 __be32 peer_ip; 562 __be32 tos_tid; 563 struct tcp_options tcp_options; 564 __u8 dst_mac[6]; 565 __be16 vlan_tag; 566 __u8 src_mac[6]; 567 #if defined(__LITTLE_ENDIAN_BITFIELD) 568 __u8 :3; 569 __u8 addr_idx:3; 570 __u8 port_idx:1; 571 __u8 exact_match:1; 572 #else 573 __u8 exact_match:1; 574 __u8 port_idx:1; 575 __u8 addr_idx:3; 576 __u8 :3; 577 #endif 578 __u8 rsvd; 579 __be32 rcv_isn; 580 __be32 rsvd2; 581 }; 582 583 struct cpl_pass_accept_rpl { 584 WR_HDR; 585 union opcode_tid ot; 586 __be32 opt2; 587 __be32 rsvd; 588 __be32 peer_ip; 589 __be32 opt0h; 590 __be32 opt0l_status; 591 }; 592 593 struct cpl_act_open_req { 594 WR_HDR; 595 union opcode_tid ot; 596 __be16 local_port; 597 __be16 peer_port; 598 __be32 local_ip; 599 __be32 peer_ip; 600 __be32 opt0h; 601 __be32 opt0l; 602 __be32 params; 603 __be32 opt2; 604 }; 605 606 /* cpl_act_open_req.params fields */ 607 #define S_AOPEN_VLAN_PRI 9 608 #define M_AOPEN_VLAN_PRI 0x3 609 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI) 610 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI) 611 612 #define S_AOPEN_VLAN_PRI_VALID 11 613 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID) 614 #define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U) 615 616 #define S_AOPEN_PKT_TYPE 12 617 #define M_AOPEN_PKT_TYPE 0x3 618 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE) 619 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE) 620 621 #define S_AOPEN_MAC_MATCH 14 622 #define M_AOPEN_MAC_MATCH 0x1F 623 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH) 624 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH) 625 626 #define S_AOPEN_MAC_MATCH_VALID 19 627 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID) 628 #define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U) 629 630 #define S_AOPEN_IFF_VLAN 20 631 #define M_AOPEN_IFF_VLAN 0xFFF 632 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN) 633 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN) 634 635 struct cpl_act_open_rpl { 636 RSS_HDR 637 union opcode_tid ot; 638 __be16 local_port; 639 __be16 peer_port; 640 __be32 local_ip; 641 __be32 peer_ip; 642 __be32 atid; 643 __u8 rsvd[3]; 644 __u8 status; 645 }; 646 647 struct cpl_act_establish { 648 RSS_HDR 649 union opcode_tid ot; 650 __be16 local_port; 651 __be16 peer_port; 652 __be32 local_ip; 653 __be32 peer_ip; 654 __be32 tos_tid; 655 __be16 l2t_idx; 656 __be16 tcp_opt; 657 __be32 snd_isn; 658 __be32 rcv_isn; 659 }; 660 661 struct cpl_get_tcb { 662 WR_HDR; 663 union opcode_tid ot; 664 __be16 cpuno; 665 __be16 rsvd; 666 }; 667 668 struct cpl_get_tcb_rpl { 669 RSS_HDR 670 union opcode_tid ot; 671 __u8 rsvd; 672 __u8 status; 673 __be16 len; 674 }; 675 676 struct cpl_set_tcb { 677 WR_HDR; 678 union opcode_tid ot; 679 __u8 reply; 680 __u8 cpu_idx; 681 __be16 len; 682 }; 683 684 /* cpl_set_tcb.reply fields */ 685 #define S_NO_REPLY 7 686 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 687 #define F_NO_REPLY V_NO_REPLY(1U) 688 689 struct cpl_set_tcb_field { 690 WR_HDR; 691 union opcode_tid ot; 692 __u8 reply; 693 __u8 cpu_idx; 694 __be16 word; 695 __be64 mask; 696 __be64 val; 697 }; 698 699 struct cpl_set_tcb_rpl { 700 RSS_HDR 701 union opcode_tid ot; 702 __u8 rsvd[3]; 703 __u8 status; 704 }; 705 706 struct cpl_pcmd { 707 WR_HDR; 708 union opcode_tid ot; 709 __u8 rsvd[3]; 710 #if defined(__LITTLE_ENDIAN_BITFIELD) 711 __u8 src:1; 712 __u8 bundle:1; 713 __u8 channel:1; 714 __u8 :5; 715 #else 716 __u8 :5; 717 __u8 channel:1; 718 __u8 bundle:1; 719 __u8 src:1; 720 #endif 721 __be32 pcmd_parm[2]; 722 }; 723 724 struct cpl_pcmd_reply { 725 RSS_HDR 726 union opcode_tid ot; 727 __u8 status; 728 __u8 rsvd; 729 __be16 len; 730 }; 731 732 struct cpl_close_con_req { 733 WR_HDR; 734 union opcode_tid ot; 735 __be32 rsvd; 736 }; 737 738 struct cpl_close_con_rpl { 739 RSS_HDR 740 union opcode_tid ot; 741 __u8 rsvd[3]; 742 __u8 status; 743 __be32 snd_nxt; 744 __be32 rcv_nxt; 745 }; 746 747 struct cpl_close_listserv_req { 748 WR_HDR; 749 union opcode_tid ot; 750 __u8 rsvd0; 751 __u8 cpu_idx; 752 __be16 rsvd1; 753 }; 754 755 struct cpl_close_listserv_rpl { 756 RSS_HDR 757 union opcode_tid ot; 758 __u8 rsvd[3]; 759 __u8 status; 760 }; 761 762 struct cpl_abort_req_rss { 763 RSS_HDR 764 union opcode_tid ot; 765 __be32 rsvd0; 766 __u8 rsvd1; 767 __u8 status; 768 __u8 rsvd2[6]; 769 }; 770 771 struct cpl_abort_req { 772 WR_HDR; 773 union opcode_tid ot; 774 __be32 rsvd0; 775 __u8 rsvd1; 776 __u8 cmd; 777 __u8 rsvd2[6]; 778 }; 779 780 struct cpl_abort_rpl_rss { 781 RSS_HDR 782 union opcode_tid ot; 783 __be32 rsvd0; 784 __u8 rsvd1; 785 __u8 status; 786 __u8 rsvd2[6]; 787 }; 788 789 struct cpl_abort_rpl { 790 WR_HDR; 791 union opcode_tid ot; 792 __be32 rsvd0; 793 __u8 rsvd1; 794 __u8 cmd; 795 __u8 rsvd2[6]; 796 }; 797 798 struct cpl_peer_close { 799 RSS_HDR 800 union opcode_tid ot; 801 __be32 rcv_nxt; 802 }; 803 804 struct tx_data_wr { 805 __be32 wr_hi; 806 __be32 wr_lo; 807 __be32 len; 808 __be32 flags; 809 __be32 sndseq; 810 __be32 param; 811 }; 812 813 /* tx_data_wr.flags fields */ 814 #define S_TX_ACK_PAGES 21 815 #define M_TX_ACK_PAGES 0x7 816 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 817 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 818 819 /* tx_data_wr.param fields */ 820 #define S_TX_PORT 0 821 #define M_TX_PORT 0x7 822 #define V_TX_PORT(x) ((x) << S_TX_PORT) 823 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 824 825 #define S_TX_MSS 4 826 #define M_TX_MSS 0xF 827 #define V_TX_MSS(x) ((x) << S_TX_MSS) 828 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 829 830 #define S_TX_QOS 8 831 #define M_TX_QOS 0xFF 832 #define V_TX_QOS(x) ((x) << S_TX_QOS) 833 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 834 835 #define S_TX_SNDBUF 16 836 #define M_TX_SNDBUF 0xFFFF 837 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 838 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 839 840 struct cpl_tx_data { 841 union opcode_tid ot; 842 __be32 len; 843 __be32 rsvd; 844 __be16 urg; 845 __be16 flags; 846 }; 847 848 /* cpl_tx_data.flags fields */ 849 #define S_TX_ULP_SUBMODE 6 850 #define M_TX_ULP_SUBMODE 0xF 851 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 852 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 853 854 #define S_TX_ULP_MODE 10 855 #define M_TX_ULP_MODE 0xF 856 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 857 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 858 859 #define S_TX_SHOVE 14 860 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 861 #define F_TX_SHOVE V_TX_SHOVE(1U) 862 863 #define S_TX_MORE 15 864 #define V_TX_MORE(x) ((x) << S_TX_MORE) 865 #define F_TX_MORE V_TX_MORE(1U) 866 867 /* additional tx_data_wr.flags fields */ 868 #define S_TX_CPU_IDX 0 869 #define M_TX_CPU_IDX 0x3F 870 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 871 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 872 873 #define S_TX_URG 16 874 #define V_TX_URG(x) ((x) << S_TX_URG) 875 #define F_TX_URG V_TX_URG(1U) 876 877 #define S_TX_CLOSE 17 878 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 879 #define F_TX_CLOSE V_TX_CLOSE(1U) 880 881 #define S_TX_INIT 18 882 #define V_TX_INIT(x) ((x) << S_TX_INIT) 883 #define F_TX_INIT V_TX_INIT(1U) 884 885 #define S_TX_IMM_ACK 19 886 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 887 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 888 889 #define S_TX_IMM_DMA 20 890 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 891 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 892 893 struct cpl_tx_data_ack { 894 RSS_HDR 895 union opcode_tid ot; 896 __be32 ack_seq; 897 }; 898 899 struct cpl_wr_ack { 900 RSS_HDR 901 union opcode_tid ot; 902 __be16 credits; 903 __be16 rsvd; 904 __be32 snd_nxt; 905 __be32 snd_una; 906 }; 907 908 struct cpl_rdma_ec_status { 909 RSS_HDR 910 union opcode_tid ot; 911 __u8 rsvd[3]; 912 __u8 status; 913 }; 914 915 struct mngt_pktsched_wr { 916 __be32 wr_hi; 917 __be32 wr_lo; 918 __u8 mngt_opcode; 919 __u8 rsvd[7]; 920 __u8 sched; 921 __u8 idx; 922 __u8 min; 923 __u8 max; 924 __u8 binding; 925 __u8 rsvd1[3]; 926 }; 927 928 struct cpl_iscsi_hdr { 929 RSS_HDR 930 union opcode_tid ot; 931 __be16 pdu_len_ddp; 932 __be16 len; 933 __be32 seq; 934 __be16 urg; 935 __u8 rsvd; 936 __u8 status; 937 }; 938 939 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 940 #define S_ISCSI_PDU_LEN 0 941 #define M_ISCSI_PDU_LEN 0x7FFF 942 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 943 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 944 945 #define S_ISCSI_DDP 15 946 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 947 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 948 949 struct cpl_rx_data { 950 RSS_HDR 951 union opcode_tid ot; 952 __be16 rsvd; 953 __be16 len; 954 __be32 seq; 955 __be16 urg; 956 #if defined(__LITTLE_ENDIAN_BITFIELD) 957 __u8 dack_mode:2; 958 __u8 psh:1; 959 __u8 heartbeat:1; 960 __u8 :4; 961 #else 962 __u8 :4; 963 __u8 heartbeat:1; 964 __u8 psh:1; 965 __u8 dack_mode:2; 966 #endif 967 __u8 status; 968 }; 969 970 struct cpl_rx_data_ack { 971 WR_HDR; 972 union opcode_tid ot; 973 __be32 credit_dack; 974 }; 975 976 /* cpl_rx_data_ack.ack_seq fields */ 977 #define S_RX_CREDITS 0 978 #define M_RX_CREDITS 0x7FFFFFF 979 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 980 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 981 982 #define S_RX_MODULATE 27 983 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE) 984 #define F_RX_MODULATE V_RX_MODULATE(1U) 985 986 #define S_RX_FORCE_ACK 28 987 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 988 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 989 990 #define S_RX_DACK_MODE 29 991 #define M_RX_DACK_MODE 0x3 992 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 993 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 994 995 #define S_RX_DACK_CHANGE 31 996 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 997 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 998 999 struct cpl_rx_urg_notify { 1000 RSS_HDR 1001 union opcode_tid ot; 1002 __be32 seq; 1003 }; 1004 1005 struct cpl_rx_ddp_complete { 1006 RSS_HDR 1007 union opcode_tid ot; 1008 __be32 ddp_report; 1009 }; 1010 1011 struct cpl_rx_data_ddp { 1012 RSS_HDR 1013 union opcode_tid ot; 1014 __be16 urg; 1015 __be16 len; 1016 __be32 seq; 1017 union { 1018 __be32 nxt_seq; 1019 __be32 ddp_report; 1020 } u; 1021 __be32 ulp_crc; 1022 __be32 ddpvld_status; 1023 }; 1024 1025 /* cpl_rx_data_ddp.ddpvld_status fields */ 1026 #define S_DDP_STATUS 0 1027 #define M_DDP_STATUS 0xFF 1028 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS) 1029 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS) 1030 1031 #define S_DDP_VALID 15 1032 #define M_DDP_VALID 0x1FFFF 1033 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1034 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1035 1036 #define S_DDP_PPOD_MISMATCH 15 1037 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1038 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1039 1040 #define S_DDP_PDU 16 1041 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1042 #define F_DDP_PDU V_DDP_PDU(1U) 1043 1044 #define S_DDP_LLIMIT_ERR 17 1045 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1046 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1047 1048 #define S_DDP_PPOD_PARITY_ERR 18 1049 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1050 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1051 1052 #define S_DDP_PADDING_ERR 19 1053 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1054 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1055 1056 #define S_DDP_HDRCRC_ERR 20 1057 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1058 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1059 1060 #define S_DDP_DATACRC_ERR 21 1061 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1062 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1063 1064 #define S_DDP_INVALID_TAG 22 1065 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1066 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1067 1068 #define S_DDP_ULIMIT_ERR 23 1069 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1070 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1071 1072 #define S_DDP_OFFSET_ERR 24 1073 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1074 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1075 1076 #define S_DDP_COLOR_ERR 25 1077 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1078 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1079 1080 #define S_DDP_TID_MISMATCH 26 1081 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1082 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1083 1084 #define S_DDP_INVALID_PPOD 27 1085 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1086 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1087 1088 #define S_DDP_ULP_MODE 28 1089 #define M_DDP_ULP_MODE 0xF 1090 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1091 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1092 1093 /* cpl_rx_data_ddp.ddp_report fields */ 1094 #define S_DDP_OFFSET 0 1095 #define M_DDP_OFFSET 0x3FFFFF 1096 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1097 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1098 1099 #define S_DDP_URG 24 1100 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1101 #define F_DDP_URG V_DDP_URG(1U) 1102 1103 #define S_DDP_PSH 25 1104 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1105 #define F_DDP_PSH V_DDP_PSH(1U) 1106 1107 #define S_DDP_BUF_COMPLETE 26 1108 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1109 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1110 1111 #define S_DDP_BUF_TIMED_OUT 27 1112 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1113 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1114 1115 #define S_DDP_BUF_IDX 28 1116 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1117 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1118 1119 struct cpl_tx_pkt { 1120 WR_HDR; 1121 __be32 cntrl; 1122 __be32 len; 1123 }; 1124 1125 struct cpl_tx_pkt_lso { 1126 WR_HDR; 1127 __be32 cntrl; 1128 __be32 len; 1129 1130 __be32 rsvd; 1131 __be32 lso_info; 1132 }; 1133 1134 /* cpl_tx_pkt*.cntrl fields */ 1135 #define S_TXPKT_VLAN 0 1136 #define M_TXPKT_VLAN 0xFFFF 1137 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN) 1138 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1139 1140 #define S_TXPKT_INTF 16 1141 #define M_TXPKT_INTF 0xF 1142 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1143 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1144 1145 #define S_TXPKT_IPCSUM_DIS 20 1146 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS) 1147 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U) 1148 1149 #define S_TXPKT_L4CSUM_DIS 21 1150 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS) 1151 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U) 1152 1153 #define S_TXPKT_VLAN_VLD 22 1154 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD) 1155 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U) 1156 1157 #define S_TXPKT_LOOPBACK 23 1158 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1159 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1160 1161 #define S_TXPKT_OPCODE 24 1162 #define M_TXPKT_OPCODE 0xFF 1163 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1164 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1165 1166 /* cpl_tx_pkt_lso.lso_info fields */ 1167 #define S_LSO_MSS 0 1168 #define M_LSO_MSS 0x3FFF 1169 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1170 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1171 1172 #define S_LSO_ETH_TYPE 14 1173 #define M_LSO_ETH_TYPE 0x3 1174 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE) 1175 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE) 1176 1177 #define S_LSO_TCPHDR_WORDS 16 1178 #define M_LSO_TCPHDR_WORDS 0xF 1179 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS) 1180 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS) 1181 1182 #define S_LSO_IPHDR_WORDS 20 1183 #define M_LSO_IPHDR_WORDS 0xF 1184 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS) 1185 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS) 1186 1187 #define S_LSO_IPV6 24 1188 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1189 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1190 1191 struct cpl_trace_pkt { 1192 #ifdef CHELSIO_FW 1193 __u8 rss_opcode; 1194 #if defined(__LITTLE_ENDIAN_BITFIELD) 1195 __u8 err:1; 1196 __u8 :7; 1197 #else 1198 __u8 :7; 1199 __u8 err:1; 1200 #endif 1201 __u8 rsvd0; 1202 #if defined(__LITTLE_ENDIAN_BITFIELD) 1203 __u8 qid:4; 1204 __u8 :4; 1205 #else 1206 __u8 :4; 1207 __u8 qid:4; 1208 #endif 1209 __be32 tstamp; 1210 #endif /* CHELSIO_FW */ 1211 1212 __u8 opcode; 1213 #if defined(__LITTLE_ENDIAN_BITFIELD) 1214 __u8 iff:4; 1215 __u8 :4; 1216 #else 1217 __u8 :4; 1218 __u8 iff:4; 1219 #endif 1220 __u8 rsvd[4]; 1221 __be16 len; 1222 }; 1223 1224 struct cpl_rx_pkt { 1225 RSS_HDR 1226 __u8 opcode; 1227 #if defined(__LITTLE_ENDIAN_BITFIELD) 1228 __u8 iff:4; 1229 __u8 csum_valid:1; 1230 __u8 ipmi_pkt:1; 1231 __u8 vlan_valid:1; 1232 __u8 fragment:1; 1233 #else 1234 __u8 fragment:1; 1235 __u8 vlan_valid:1; 1236 __u8 ipmi_pkt:1; 1237 __u8 csum_valid:1; 1238 __u8 iff:4; 1239 #endif 1240 __be16 csum; 1241 __be16 vlan; 1242 __be16 len; 1243 }; 1244 1245 struct cpl_l2t_write_req { 1246 WR_HDR; 1247 union opcode_tid ot; 1248 __be32 params; 1249 __u8 rsvd[2]; 1250 __u8 dst_mac[6]; 1251 }; 1252 1253 /* cpl_l2t_write_req.params fields */ 1254 #define S_L2T_W_IDX 0 1255 #define M_L2T_W_IDX 0x7FF 1256 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX) 1257 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX) 1258 1259 #define S_L2T_W_VLAN 11 1260 #define M_L2T_W_VLAN 0xFFF 1261 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN) 1262 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN) 1263 1264 #define S_L2T_W_IFF 23 1265 #define M_L2T_W_IFF 0xF 1266 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF) 1267 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF) 1268 1269 #define S_L2T_W_PRIO 27 1270 #define M_L2T_W_PRIO 0x7 1271 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO) 1272 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO) 1273 1274 struct cpl_l2t_write_rpl { 1275 RSS_HDR 1276 union opcode_tid ot; 1277 __u8 status; 1278 __u8 rsvd[3]; 1279 }; 1280 1281 struct cpl_l2t_read_req { 1282 WR_HDR; 1283 union opcode_tid ot; 1284 __be16 rsvd; 1285 __be16 l2t_idx; 1286 }; 1287 1288 struct cpl_l2t_read_rpl { 1289 RSS_HDR 1290 union opcode_tid ot; 1291 __be32 params; 1292 __u8 rsvd[2]; 1293 __u8 dst_mac[6]; 1294 }; 1295 1296 /* cpl_l2t_read_rpl.params fields */ 1297 #define S_L2T_R_PRIO 0 1298 #define M_L2T_R_PRIO 0x7 1299 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO) 1300 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO) 1301 1302 #define S_L2T_R_VLAN 8 1303 #define M_L2T_R_VLAN 0xFFF 1304 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN) 1305 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN) 1306 1307 #define S_L2T_R_IFF 20 1308 #define M_L2T_R_IFF 0xF 1309 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF) 1310 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF) 1311 1312 #define S_L2T_STATUS 24 1313 #define M_L2T_STATUS 0xFF 1314 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS) 1315 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS) 1316 1317 struct cpl_smt_write_req { 1318 WR_HDR; 1319 union opcode_tid ot; 1320 __u8 rsvd0; 1321 #if defined(__LITTLE_ENDIAN_BITFIELD) 1322 __u8 mtu_idx:4; 1323 __u8 iff:4; 1324 #else 1325 __u8 iff:4; 1326 __u8 mtu_idx:4; 1327 #endif 1328 __be16 rsvd2; 1329 __be16 rsvd3; 1330 __u8 src_mac1[6]; 1331 __be16 rsvd4; 1332 __u8 src_mac0[6]; 1333 }; 1334 1335 struct cpl_smt_write_rpl { 1336 RSS_HDR 1337 union opcode_tid ot; 1338 __u8 status; 1339 __u8 rsvd[3]; 1340 }; 1341 1342 struct cpl_smt_read_req { 1343 WR_HDR; 1344 union opcode_tid ot; 1345 __u8 rsvd0; 1346 #if defined(__LITTLE_ENDIAN_BITFIELD) 1347 __u8 :4; 1348 __u8 iff:4; 1349 #else 1350 __u8 iff:4; 1351 __u8 :4; 1352 #endif 1353 __be16 rsvd2; 1354 }; 1355 1356 struct cpl_smt_read_rpl { 1357 RSS_HDR 1358 union opcode_tid ot; 1359 __u8 status; 1360 #if defined(__LITTLE_ENDIAN_BITFIELD) 1361 __u8 mtu_idx:4; 1362 __u8 :4; 1363 #else 1364 __u8 :4; 1365 __u8 mtu_idx:4; 1366 #endif 1367 __be16 rsvd2; 1368 __be16 rsvd3; 1369 __u8 src_mac1[6]; 1370 __be16 rsvd4; 1371 __u8 src_mac0[6]; 1372 }; 1373 1374 struct cpl_rte_delete_req { 1375 WR_HDR; 1376 union opcode_tid ot; 1377 __be32 params; 1378 }; 1379 1380 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */ 1381 #define S_RTE_REQ_LUT_IX 8 1382 #define M_RTE_REQ_LUT_IX 0x7FF 1383 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1384 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1385 1386 #define S_RTE_REQ_LUT_BASE 19 1387 #define M_RTE_REQ_LUT_BASE 0x7FF 1388 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1389 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1390 1391 #define S_RTE_READ_REQ_SELECT 31 1392 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1393 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1394 1395 struct cpl_rte_delete_rpl { 1396 RSS_HDR 1397 union opcode_tid ot; 1398 __u8 status; 1399 __u8 rsvd[3]; 1400 }; 1401 1402 struct cpl_rte_write_req { 1403 WR_HDR; 1404 union opcode_tid ot; 1405 #if defined(__LITTLE_ENDIAN_BITFIELD) 1406 __u8 :6; 1407 __u8 write_tcam:1; 1408 __u8 write_l2t_lut:1; 1409 #else 1410 __u8 write_l2t_lut:1; 1411 __u8 write_tcam:1; 1412 __u8 :6; 1413 #endif 1414 __u8 rsvd[3]; 1415 __be32 lut_params; 1416 __be16 rsvd2; 1417 __be16 l2t_idx; 1418 __be32 netmask; 1419 __be32 faddr; 1420 }; 1421 1422 /* cpl_rte_write_req.lut_params fields */ 1423 #define S_RTE_WRITE_REQ_LUT_IX 10 1424 #define M_RTE_WRITE_REQ_LUT_IX 0x7FF 1425 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX) 1426 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX) 1427 1428 #define S_RTE_WRITE_REQ_LUT_BASE 21 1429 #define M_RTE_WRITE_REQ_LUT_BASE 0x7FF 1430 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE) 1431 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE) 1432 1433 struct cpl_rte_write_rpl { 1434 RSS_HDR 1435 union opcode_tid ot; 1436 __u8 status; 1437 __u8 rsvd[3]; 1438 }; 1439 1440 struct cpl_rte_read_req { 1441 WR_HDR; 1442 union opcode_tid ot; 1443 __be32 params; 1444 }; 1445 1446 struct cpl_rte_read_rpl { 1447 RSS_HDR 1448 union opcode_tid ot; 1449 __u8 status; 1450 __u8 rsvd0; 1451 __be16 l2t_idx; 1452 #if defined(__LITTLE_ENDIAN_BITFIELD) 1453 __u8 :7; 1454 __u8 select:1; 1455 #else 1456 __u8 select:1; 1457 __u8 :7; 1458 #endif 1459 __u8 rsvd2[3]; 1460 __be32 addr; 1461 }; 1462 1463 struct cpl_tid_release { 1464 WR_HDR; 1465 union opcode_tid ot; 1466 __be32 rsvd; 1467 }; 1468 1469 struct cpl_barrier { 1470 WR_HDR; 1471 __u8 opcode; 1472 __u8 rsvd[7]; 1473 }; 1474 1475 struct cpl_rdma_read_req { 1476 __u8 opcode; 1477 __u8 rsvd[15]; 1478 }; 1479 1480 struct cpl_rdma_terminate { 1481 #ifdef CHELSIO_FW 1482 __u8 opcode; 1483 __u8 rsvd[2]; 1484 #if defined(__LITTLE_ENDIAN_BITFIELD) 1485 __u8 rspq:3; 1486 __u8 :5; 1487 #else 1488 __u8 :5; 1489 __u8 rspq:3; 1490 #endif 1491 __be32 tid_len; 1492 #endif 1493 __be32 msn; 1494 __be32 mo; 1495 __u8 data[0]; 1496 }; 1497 1498 /* cpl_rdma_terminate.tid_len fields */ 1499 #define S_FLIT_CNT 0 1500 #define M_FLIT_CNT 0xFF 1501 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT) 1502 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT) 1503 1504 #define S_TERM_TID 8 1505 #define M_TERM_TID 0xFFFFF 1506 #define V_TERM_TID(x) ((x) << S_TERM_TID) 1507 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID) 1508 1509 /* ULP_TX opcodes */ 1510 enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 }; 1511 1512 #define S_ULPTX_CMD 28 1513 #define M_ULPTX_CMD 0xF 1514 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 1515 1516 #define S_ULPTX_NFLITS 0 1517 #define M_ULPTX_NFLITS 0xFF 1518 #define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS) 1519 1520 struct ulp_mem_io { 1521 WR_HDR; 1522 __be32 cmd_lock_addr; 1523 __be32 len; 1524 }; 1525 1526 /* ulp_mem_io.cmd_lock_addr fields */ 1527 #define S_ULP_MEMIO_ADDR 0 1528 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 1529 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 1530 1531 #define S_ULP_MEMIO_LOCK 27 1532 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 1533 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 1534 1535 /* ulp_mem_io.len fields */ 1536 #define S_ULP_MEMIO_DATA_LEN 28 1537 #define M_ULP_MEMIO_DATA_LEN 0xF 1538 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 1539 1540 struct ulp_txpkt { 1541 __be32 cmd_dest; 1542 __be32 len; 1543 }; 1544 1545 /* ulp_txpkt.cmd_dest fields */ 1546 #define S_ULP_TXPKT_DEST 24 1547 #define M_ULP_TXPKT_DEST 0xF 1548 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 1549 1550 #endif /* T3_CPL_H */
Cache object: ec7324a486d5f2b54f906579a16670f1
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