1 /**************************************************************************
2
3 Copyright (c) 2007, Chelsio Inc.
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
15
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
27
28 $FreeBSD: releng/6.4/sys/dev/cxgb/cxgb_adapter.h 174319 2007-12-05 22:05:49Z kmacy $
29
30 ***************************************************************************/
31
32
33
34 #ifndef _CXGB_ADAPTER_H_
35 #define _CXGB_ADAPTER_H_
36
37 #include <sys/lock.h>
38 #include <sys/mutex.h>
39 #include <sys/sx.h>
40 #include <sys/rman.h>
41 #include <sys/mbuf.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44
45 #include <net/ethernet.h>
46 #include <net/if.h>
47 #include <net/if_media.h>
48
49 #include <machine/bus.h>
50 #include <machine/resource.h>
51 #include <sys/bus_dma.h>
52 #include <dev/pci/pcireg.h>
53 #include <dev/pci/pcivar.h>
54
55 #ifdef CONFIG_DEFINED
56 #include <cxgb_osdep.h>
57 #include <ulp/toecore/toedev.h>
58 #include <sys/mbufq.h>
59 #else
60 #include <dev/cxgb/cxgb_osdep.h>
61 #include <dev/cxgb/sys/mbufq.h>
62 #include <dev/cxgb/ulp/toecore/toedev.h>
63 #endif
64
65 #define USE_SX
66
67 struct adapter;
68 struct sge_qset;
69 extern int cxgb_debug;
70
71 #ifdef DEBUG_LOCKING
72 #define MTX_INIT(lock, lockname, class, flags) \
73 do { \
74 printf("initializing %s at %s:%d\n", lockname, __FILE__, __LINE__); \
75 mtx_init((lock), lockname, class, flags); \
76 } while (0)
77
78 #define MTX_DESTROY(lock) \
79 do { \
80 printf("destroying %s at %s:%d\n", (lock)->lock_object.lo_name, __FILE__, __LINE__); \
81 mtx_destroy((lock)); \
82 } while (0)
83
84 #define SX_INIT(lock, lockname) \
85 do { \
86 printf("initializing %s at %s:%d\n", lockname, __FILE__, __LINE__); \
87 sx_init((lock), lockname); \
88 } while (0)
89
90 #define SX_DESTROY(lock) \
91 do { \
92 printf("destroying %s at %s:%d\n", (lock)->lock_object.lo_name, __FILE__, __LINE__); \
93 sx_destroy((lock)); \
94 } while (0)
95 #else
96 #define MTX_INIT mtx_init
97 #define MTX_DESTROY mtx_destroy
98 #define SX_INIT sx_init
99 #define SX_DESTROY sx_destroy
100 #endif
101
102 struct port_info {
103 struct adapter *adapter;
104 struct ifnet *ifp;
105 int if_flags;
106 const struct port_type_info *port_type;
107 struct cphy phy;
108 struct cmac mac;
109 struct link_config link_config;
110 struct ifmedia media;
111 #ifdef USE_SX
112 struct sx lock;
113 #else
114 struct mtx lock;
115 #endif
116 uint8_t port_id;
117 uint8_t tx_chan;
118 uint8_t txpkt_intf;
119 uint8_t nqsets;
120 uint8_t first_qset;
121
122 uint8_t hw_addr[ETHER_ADDR_LEN];
123 struct taskqueue *tq;
124 struct task start_task;
125 struct task timer_reclaim_task;
126 struct cdev *port_cdev;
127
128 #define PORT_NAME_LEN 32
129 #define TASKQ_NAME_LEN 32
130 char lockbuf[PORT_NAME_LEN];
131 char taskqbuf[TASKQ_NAME_LEN];
132 };
133
134 enum { /* adapter flags */
135 FULL_INIT_DONE = (1 << 0),
136 USING_MSI = (1 << 1),
137 USING_MSIX = (1 << 2),
138 QUEUES_BOUND = (1 << 3),
139 FW_UPTODATE = (1 << 4),
140 TPS_UPTODATE = (1 << 5),
141 };
142
143
144 #define FL_Q_SIZE 4096
145 #define JUMBO_Q_SIZE 512
146 #define RSPQ_Q_SIZE 1024
147 #define TX_ETH_Q_SIZE 1024
148
149
150
151 /*
152 * Types of Tx queues in each queue set. Order here matters, do not change.
153 * XXX TOE is not implemented yet, so the extra queues are just placeholders.
154 */
155 enum { TXQ_ETH, TXQ_OFLD, TXQ_CTRL };
156
157
158 /* careful, the following are set on priv_flags and must not collide with
159 * IFF_ flags!
160 */
161 enum {
162 LRO_ACTIVE = (1 << 8),
163 };
164
165 /* Max concurrent LRO sessions per queue set */
166 #define MAX_LRO_SES 8
167
168 struct t3_lro_session {
169 struct mbuf *head;
170 struct mbuf *tail;
171 uint32_t seq;
172 uint16_t ip_len;
173 uint16_t mss;
174 uint16_t vtag;
175 uint8_t npkts;
176 };
177
178 struct lro_state {
179 unsigned short enabled;
180 unsigned short active_idx;
181 unsigned int nactive;
182 struct t3_lro_session sess[MAX_LRO_SES];
183 };
184
185 #define RX_BUNDLE_SIZE 8
186
187 struct rsp_desc;
188
189 struct sge_rspq {
190 uint32_t credits;
191 uint32_t size;
192 uint32_t cidx;
193 uint32_t gen;
194 uint32_t polling;
195 uint32_t holdoff_tmr;
196 uint32_t next_holdoff;
197 uint32_t imm_data;
198 struct rsp_desc *desc;
199 uint32_t cntxt_id;
200 struct mtx lock;
201 struct mbuf *rx_head; /* offload packet receive queue head */
202 struct mbuf *rx_tail; /* offload packet receive queue tail */
203
204 uint32_t offload_pkts;
205 uint32_t offload_bundles;
206 uint32_t pure_rsps;
207 uint32_t unhandled_irqs;
208
209 bus_addr_t phys_addr;
210 bus_dma_tag_t desc_tag;
211 bus_dmamap_t desc_map;
212
213 struct t3_mbuf_hdr rspq_mh;
214 #define RSPQ_NAME_LEN 32
215 char lockbuf[RSPQ_NAME_LEN];
216
217 };
218
219 #ifndef DISABLE_MBUF_IOVEC
220 #define rspq_mbuf rspq_mh.mh_head
221 #endif
222
223 struct rx_desc;
224 struct rx_sw_desc;
225
226 struct sge_fl {
227 uint32_t buf_size;
228 uint32_t credits;
229 uint32_t size;
230 uint32_t cidx;
231 uint32_t pidx;
232 uint32_t gen;
233 struct rx_desc *desc;
234 struct rx_sw_desc *sdesc;
235 bus_addr_t phys_addr;
236 uint32_t cntxt_id;
237 uint64_t empty;
238 bus_dma_tag_t desc_tag;
239 bus_dmamap_t desc_map;
240 bus_dma_tag_t entry_tag;
241 uma_zone_t zone;
242 int type;
243 };
244
245 struct tx_desc;
246 struct tx_sw_desc;
247
248 #define TXQ_TRANSMITTING 0x1
249
250 struct sge_txq {
251 uint64_t flags;
252 uint32_t in_use;
253 uint32_t size;
254 uint32_t processed;
255 uint32_t cleaned;
256 uint32_t stop_thres;
257 uint32_t cidx;
258 uint32_t pidx;
259 uint32_t gen;
260 uint32_t unacked;
261 struct tx_desc *desc;
262 struct tx_sw_desc *sdesc;
263 uint32_t token;
264 bus_addr_t phys_addr;
265 struct task qresume_task;
266 struct task qreclaim_task;
267 struct port_info *port;
268 uint32_t cntxt_id;
269 uint64_t stops;
270 uint64_t restarts;
271 bus_dma_tag_t desc_tag;
272 bus_dmamap_t desc_map;
273 bus_dma_tag_t entry_tag;
274 struct mbuf_head sendq;
275 struct mtx lock;
276 #define TXQ_NAME_LEN 32
277 char lockbuf[TXQ_NAME_LEN];
278 };
279
280
281 enum {
282 SGE_PSTAT_TSO, /* # of TSO requests */
283 SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
284 SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */
285 SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */
286 SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */
287 SGE_PSTATS_LRO_QUEUED, /* # of LRO appended packets */
288 SGE_PSTATS_LRO_FLUSHED, /* # of LRO flushed packets */
289 SGE_PSTATS_LRO_X_STREAMS, /* # of exceeded LRO contexts */
290 };
291
292 #define SGE_PSTAT_MAX (SGE_PSTATS_LRO_X_STREAMS+1)
293
294 struct sge_qset {
295 struct sge_rspq rspq;
296 struct sge_fl fl[SGE_RXQ_PER_SET];
297 struct lro_state lro;
298 struct sge_txq txq[SGE_TXQ_PER_SET];
299 uint32_t txq_stopped; /* which Tx queues are stopped */
300 uint64_t port_stats[SGE_PSTAT_MAX];
301 struct port_info *port;
302 int idx; /* qset # */
303 };
304
305 struct sge {
306 struct sge_qset qs[SGE_QSETS];
307 struct mtx reg_lock;
308 };
309
310 struct filter_info;
311
312 struct adapter {
313 device_t dev;
314 int flags;
315 TAILQ_ENTRY(adapter) adapter_entry;
316
317 /* PCI register resources */
318 int regs_rid;
319 struct resource *regs_res;
320 bus_space_handle_t bh;
321 bus_space_tag_t bt;
322 bus_size_t mmio_len;
323 uint32_t link_width;
324
325 /* DMA resources */
326 bus_dma_tag_t parent_dmat;
327 bus_dma_tag_t rx_dmat;
328 bus_dma_tag_t rx_jumbo_dmat;
329 bus_dma_tag_t tx_dmat;
330
331 /* Interrupt resources */
332 struct resource *irq_res;
333 int irq_rid;
334 void *intr_tag;
335
336 uint32_t msix_regs_rid;
337 struct resource *msix_regs_res;
338
339 struct resource *msix_irq_res[SGE_QSETS];
340 int msix_irq_rid[SGE_QSETS];
341 void *msix_intr_tag[SGE_QSETS];
342 uint8_t rxpkt_map[8]; /* maps RX_PKT interface values to port ids */
343 uint8_t rrss_map[SGE_QSETS]; /* revers RSS map table */
344
345 struct filter_info *filters;
346
347 /* Tasks */
348 struct task ext_intr_task;
349 struct task slow_intr_task;
350 struct task tick_task;
351 struct task process_responses_task;
352 struct taskqueue *tq;
353 struct callout cxgb_tick_ch;
354 struct callout sge_timer_ch;
355
356 /* Register lock for use by the hardware layer */
357 struct mtx mdio_lock;
358 struct mtx elmer_lock;
359
360 /* Bookkeeping for the hardware layer */
361 struct adapter_params params;
362 unsigned int slow_intr_mask;
363 unsigned long irq_stats[IRQ_NUM_STATS];
364
365 struct sge sge;
366 struct mc7 pmrx;
367 struct mc7 pmtx;
368 struct mc7 cm;
369 struct mc5 mc5;
370
371 struct port_info port[MAX_NPORTS];
372 device_t portdev[MAX_NPORTS];
373 struct toedev tdev;
374 char fw_version[64];
375 uint32_t open_device_map;
376 uint32_t registered_device_map;
377 #ifdef USE_SX
378 struct sx lock;
379 #else
380 struct mtx lock;
381 #endif
382 driver_intr_t *cxgb_intr;
383 int msi_count;
384
385 #define ADAPTER_LOCK_NAME_LEN 32
386 char lockbuf[ADAPTER_LOCK_NAME_LEN];
387 char reglockbuf[ADAPTER_LOCK_NAME_LEN];
388 char mdiolockbuf[ADAPTER_LOCK_NAME_LEN];
389 char elmerlockbuf[ADAPTER_LOCK_NAME_LEN];
390 };
391
392 struct t3_rx_mode {
393
394 uint32_t idx;
395 struct port_info *port;
396 };
397
398
399 #define MDIO_LOCK(adapter) mtx_lock(&(adapter)->mdio_lock)
400 #define MDIO_UNLOCK(adapter) mtx_unlock(&(adapter)->mdio_lock)
401 #define ELMR_LOCK(adapter) mtx_lock(&(adapter)->elmer_lock)
402 #define ELMR_UNLOCK(adapter) mtx_unlock(&(adapter)->elmer_lock)
403
404
405 #ifdef USE_SX
406 #define PORT_LOCK(port) sx_xlock(&(port)->lock);
407 #define PORT_UNLOCK(port) sx_xunlock(&(port)->lock);
408 #define PORT_LOCK_INIT(port, name) SX_INIT(&(port)->lock, name)
409 #define PORT_LOCK_DEINIT(port) SX_DESTROY(&(port)->lock)
410 #define PORT_LOCK_ASSERT_OWNED(port) sx_assert(&(port)->lock, SA_LOCKED)
411
412 #define ADAPTER_LOCK(adap) sx_xlock(&(adap)->lock);
413 #define ADAPTER_UNLOCK(adap) sx_xunlock(&(adap)->lock);
414 #define ADAPTER_LOCK_INIT(adap, name) SX_INIT(&(adap)->lock, name)
415 #define ADAPTER_LOCK_DEINIT(adap) SX_DESTROY(&(adap)->lock)
416 #define ADAPTER_LOCK_ASSERT_NOTOWNED(adap) sx_assert(&(adap)->lock, SA_UNLOCKED)
417 #else
418 #define PORT_LOCK(port) mtx_lock(&(port)->lock);
419 #define PORT_UNLOCK(port) mtx_unlock(&(port)->lock);
420 #define PORT_LOCK_INIT(port, name) mtx_init(&(port)->lock, name, 0, MTX_DEF)
421 #define PORT_LOCK_DEINIT(port) mtx_destroy(&(port)->lock)
422 #define PORT_LOCK_ASSERT_OWNED(port) mtx_assert(&(port)->lock, MA_OWNED)
423
424 #define ADAPTER_LOCK(adap) mtx_lock(&(adap)->lock);
425 #define ADAPTER_UNLOCK(adap) mtx_unlock(&(adap)->lock);
426 #define ADAPTER_LOCK_INIT(adap, name) mtx_init(&(adap)->lock, name, 0, MTX_DEF)
427 #define ADAPTER_LOCK_DEINIT(adap) mtx_destroy(&(adap)->lock)
428 #define ADAPTER_LOCK_ASSERT_NOTOWNED(adap) mtx_assert(&(adap)->lock, MO_NOTOWNED)
429 #endif
430
431
432 static __inline uint32_t
433 t3_read_reg(adapter_t *adapter, uint32_t reg_addr)
434 {
435 return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr));
436 }
437
438 static __inline void
439 t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val)
440 {
441 bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val);
442 }
443
444 static __inline void
445 t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val)
446 {
447 *val = pci_read_config(adapter->dev, reg, 4);
448 }
449
450 static __inline void
451 t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val)
452 {
453 pci_write_config(adapter->dev, reg, val, 4);
454 }
455
456 static __inline void
457 t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val)
458 {
459 *val = pci_read_config(adapter->dev, reg, 2);
460 }
461
462 static __inline void
463 t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val)
464 {
465 pci_write_config(adapter->dev, reg, val, 2);
466 }
467
468 static __inline uint8_t *
469 t3_get_next_mcaddr(struct t3_rx_mode *rm)
470 {
471 uint8_t *macaddr = NULL;
472
473 if (rm->idx == 0)
474 macaddr = rm->port->hw_addr;
475
476 rm->idx++;
477 return (macaddr);
478 }
479
480 static __inline void
481 t3_init_rx_mode(struct t3_rx_mode *rm, struct port_info *port)
482 {
483 rm->idx = 0;
484 rm->port = port;
485 }
486
487 static __inline struct port_info *
488 adap2pinfo(struct adapter *adap, int idx)
489 {
490 return &adap->port[idx];
491 }
492
493 int t3_os_find_pci_capability(adapter_t *adapter, int cap);
494 int t3_os_pci_save_state(struct adapter *adapter);
495 int t3_os_pci_restore_state(struct adapter *adapter);
496 void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status,
497 int speed, int duplex, int fc);
498 void t3_sge_err_intr_handler(adapter_t *adapter);
499 int t3_offload_tx(struct toedev *, struct mbuf *);
500 void t3_os_ext_intr_handler(adapter_t *adapter);
501 void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]);
502 int t3_mgmt_tx(adapter_t *adap, struct mbuf *m);
503
504
505 int t3_sge_alloc(struct adapter *);
506 int t3_sge_free(struct adapter *);
507 int t3_sge_alloc_qset(adapter_t *, uint32_t, int, int, const struct qset_params *,
508 int, struct port_info *);
509 void t3_free_sge_resources(adapter_t *);
510 void t3_sge_start(adapter_t *);
511 void t3_sge_stop(adapter_t *);
512 void t3b_intr(void *data);
513 void t3_intr_msi(void *data);
514 void t3_intr_msix(void *data);
515 int t3_encap(struct port_info *, struct mbuf **, int *free);
516
517 int t3_sge_init_adapter(adapter_t *);
518 int t3_sge_init_port(struct port_info *);
519 void t3_sge_deinit_sw(adapter_t *);
520
521 void t3_rx_eth_lro(adapter_t *adap, struct sge_rspq *rq, struct mbuf *m,
522 int ethpad, uint32_t rss_hash, uint32_t rss_csum, int lro);
523 void t3_rx_eth(struct adapter *adap, struct sge_rspq *rq, struct mbuf *m, int ethpad);
524 void t3_lro_flush(adapter_t *adap, struct sge_qset *qs, struct lro_state *state);
525
526 void t3_add_sysctls(adapter_t *sc);
527 int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
528 unsigned char *data);
529 void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
530 /*
531 * XXX figure out how we can return this to being private to sge
532 */
533 #define desc_reclaimable(q) ((int)((q)->processed - (q)->cleaned - TX_MAX_DESC))
534
535 #define container_of(p, stype, field) ((stype *)(((uint8_t *)(p)) - offsetof(stype, field)))
536
537 static __inline struct sge_qset *
538 fl_to_qset(struct sge_fl *q, int qidx)
539 {
540 return container_of(q, struct sge_qset, fl[qidx]);
541 }
542
543 static __inline struct sge_qset *
544 rspq_to_qset(struct sge_rspq *q)
545 {
546 return container_of(q, struct sge_qset, rspq);
547 }
548
549 static __inline struct sge_qset *
550 txq_to_qset(struct sge_txq *q, int qidx)
551 {
552 return container_of(q, struct sge_qset, txq[qidx]);
553 }
554
555 static __inline struct adapter *
556 tdev2adap(struct toedev *d)
557 {
558 return container_of(d, struct adapter, tdev);
559 }
560
561 #undef container_of
562
563 #define OFFLOAD_DEVMAP_BIT 15
564 static inline int offload_running(adapter_t *adapter)
565 {
566 return isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT);
567 }
568
569
570 #endif
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