1 /**************************************************************************
2
3 Copyright (c) 2007-2009, Chelsio Inc.
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
15
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
27
28
29 $FreeBSD: releng/7.4/sys/dev/cxgb/cxgb_adapter.h 211858 2010-08-27 02:46:21Z np $
30
31
32 ***************************************************************************/
33
34
35 #ifndef _CXGB_ADAPTER_H_
36 #define _CXGB_ADAPTER_H_
37
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/rman.h>
41 #include <sys/mbuf.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/condvar.h>
45
46 #include <net/ethernet.h>
47 #include <net/if.h>
48 #include <net/if_media.h>
49 #include <net/if_dl.h>
50 #include <netinet/tcp_lro.h>
51
52 #include <machine/bus.h>
53 #include <machine/resource.h>
54
55 #include <sys/bus_dma.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcivar.h>
58
59
60 #ifdef CONFIG_DEFINED
61 #include <cxgb_osdep.h>
62 #include <t3cdev.h>
63 #include <ulp/toecore/cxgb_toedev.h>
64 #include <sys/mbufq.h>
65 #else
66 #include <dev/cxgb/cxgb_osdep.h>
67 #include <dev/cxgb/t3cdev.h>
68 #include <dev/cxgb/sys/mbufq.h>
69 #include <dev/cxgb/ulp/toecore/cxgb_toedev.h>
70 #endif
71
72 struct adapter;
73 struct sge_qset;
74 extern int cxgb_debug;
75
76 #ifdef DEBUG_LOCKING
77 #define MTX_INIT(lock, lockname, class, flags) \
78 do { \
79 printf("initializing %s at %s:%d\n", lockname, __FILE__, __LINE__); \
80 mtx_init((lock), lockname, class, flags); \
81 } while (0)
82
83 #define MTX_DESTROY(lock) \
84 do { \
85 printf("destroying %s at %s:%d\n", (lock)->lock_object.lo_name, __FILE__, __LINE__); \
86 mtx_destroy((lock)); \
87 } while (0)
88
89 #else
90 #define MTX_INIT mtx_init
91 #define MTX_DESTROY mtx_destroy
92 #endif
93
94 enum {
95 LF_NO = 0,
96 LF_MAYBE,
97 LF_YES
98 };
99
100 struct port_info {
101 struct adapter *adapter;
102 struct ifnet *ifp;
103 int if_flags;
104 int flags;
105 const struct port_type_info *port_type;
106 struct cphy phy;
107 struct cmac mac;
108 struct link_config link_config;
109 struct ifmedia media;
110 struct mtx lock;
111 uint32_t port_id;
112 uint32_t tx_chan;
113 uint32_t txpkt_intf;
114 uint32_t first_qset;
115 uint32_t nqsets;
116 int link_fault;
117
118 uint8_t hw_addr[ETHER_ADDR_LEN];
119 struct callout link_check_ch;
120 struct task link_check_task;
121 struct task timer_reclaim_task;
122 struct cdev *port_cdev;
123
124 #define PORT_LOCK_NAME_LEN 32
125 #define PORT_NAME_LEN 32
126 char lockbuf[PORT_LOCK_NAME_LEN];
127 char namebuf[PORT_NAME_LEN];
128 };
129
130 enum {
131 /* adapter flags */
132 FULL_INIT_DONE = (1 << 0),
133 USING_MSI = (1 << 1),
134 USING_MSIX = (1 << 2),
135 QUEUES_BOUND = (1 << 3),
136 FW_UPTODATE = (1 << 4),
137 TPS_UPTODATE = (1 << 5),
138 CXGB_SHUTDOWN = (1 << 6),
139 CXGB_OFLD_INIT = (1 << 7),
140 TP_PARITY_INIT = (1 << 8),
141 CXGB_BUSY = (1 << 9),
142
143 /* port flags */
144 DOOMED = (1 << 0),
145 };
146 #define IS_DOOMED(p) (p->flags & DOOMED)
147 #define SET_DOOMED(p) do {p->flags |= DOOMED;} while (0)
148 #define IS_BUSY(sc) (sc->flags & CXGB_BUSY)
149 #define SET_BUSY(sc) do {sc->flags |= CXGB_BUSY;} while (0)
150 #define CLR_BUSY(sc) do {sc->flags &= ~CXGB_BUSY;} while (0)
151
152 #define FL_Q_SIZE 4096
153 #define JUMBO_Q_SIZE 1024
154 #define RSPQ_Q_SIZE 2048
155 #define TX_ETH_Q_SIZE 1024
156
157 enum { TXQ_ETH = 0,
158 TXQ_OFLD = 1,
159 TXQ_CTRL = 2, };
160
161
162 /*
163 * work request size in bytes
164 */
165 #define WR_LEN (WR_FLITS * 8)
166 #define PIO_LEN (WR_LEN - sizeof(struct cpl_tx_pkt_lso))
167
168 struct lro_state {
169 unsigned short enabled;
170 struct lro_ctrl ctrl;
171 };
172
173 #define RX_BUNDLE_SIZE 8
174
175 struct rsp_desc;
176
177 struct sge_rspq {
178 uint32_t credits;
179 uint32_t size;
180 uint32_t cidx;
181 uint32_t gen;
182 uint32_t polling;
183 uint32_t holdoff_tmr;
184 uint32_t next_holdoff;
185 uint32_t imm_data;
186 uint32_t async_notif;
187 uint32_t cntxt_id;
188 uint32_t offload_pkts;
189 uint32_t offload_bundles;
190 uint32_t pure_rsps;
191 uint32_t unhandled_irqs;
192 uint32_t starved;
193
194 bus_addr_t phys_addr;
195 bus_dma_tag_t desc_tag;
196 bus_dmamap_t desc_map;
197
198 struct t3_mbuf_hdr rspq_mh;
199 struct rsp_desc *desc;
200 struct mtx lock;
201 #define RSPQ_NAME_LEN 32
202 char lockbuf[RSPQ_NAME_LEN];
203 uint32_t rspq_dump_start;
204 uint32_t rspq_dump_count;
205 };
206
207 #ifndef DISABLE_MBUF_IOVEC
208 #define rspq_mbuf rspq_mh.mh_head
209 #endif
210
211 struct rx_desc;
212 struct rx_sw_desc;
213
214 struct sge_fl {
215 uint32_t buf_size;
216 uint32_t credits;
217 uint32_t size;
218 uint32_t cidx;
219 uint32_t pidx;
220 uint32_t gen;
221 bus_addr_t phys_addr;
222 uint32_t cntxt_id;
223 uint32_t empty;
224 bus_dma_tag_t desc_tag;
225 bus_dmamap_t desc_map;
226 bus_dma_tag_t entry_tag;
227 uma_zone_t zone;
228 struct rx_desc *desc;
229 struct rx_sw_desc *sdesc;
230 int type;
231 };
232
233 struct tx_desc;
234 struct tx_sw_desc;
235
236 #define TXQ_TRANSMITTING 0x1
237
238 struct sge_txq {
239 uint64_t flags;
240 uint32_t in_use;
241 uint32_t size;
242 uint32_t processed;
243 uint32_t cleaned;
244 uint32_t stop_thres;
245 uint32_t cidx;
246 uint32_t pidx;
247 uint32_t gen;
248 uint32_t unacked;
249 struct tx_desc *desc;
250 struct tx_sw_desc *sdesc;
251 uint32_t token;
252 bus_addr_t phys_addr;
253 struct task qresume_task;
254 struct task qreclaim_task;
255 struct port_info *port;
256 uint32_t cntxt_id;
257 uint64_t stops;
258 uint64_t restarts;
259 bus_dma_tag_t desc_tag;
260 bus_dmamap_t desc_map;
261 bus_dma_tag_t entry_tag;
262 struct mbuf_head sendq;
263 /*
264 * cleanq should really be an buf_ring to avoid extra
265 * mbuf touches
266 */
267 struct mbuf_head cleanq;
268 struct buf_ring txq_mr;
269 struct mbuf *immpkt;
270 uint32_t txq_drops;
271 uint32_t txq_skipped;
272 uint32_t txq_coalesced;
273 uint32_t txq_enqueued;
274 uint32_t txq_dump_start;
275 uint32_t txq_dump_count;
276 unsigned long txq_frees;
277 struct mtx lock;
278 struct sg_ent txq_sgl[TX_MAX_SEGS / 2 + 1];
279 #define TXQ_NAME_LEN 32
280 char lockbuf[TXQ_NAME_LEN];
281 };
282
283
284 enum {
285 SGE_PSTAT_TSO, /* # of TSO requests */
286 SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
287 SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */
288 SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */
289 SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */
290 };
291
292 #define SGE_PSTAT_MAX (SGE_PSTAT_VLANINS+1)
293
294 #define QS_EXITING 0x1
295 #define QS_RUNNING 0x2
296 #define QS_BOUND 0x4
297
298 struct sge_qset {
299 struct sge_rspq rspq;
300 struct sge_fl fl[SGE_RXQ_PER_SET];
301 struct lro_state lro;
302 struct sge_txq txq[SGE_TXQ_PER_SET];
303 uint32_t txq_stopped; /* which Tx queues are stopped */
304 uint64_t port_stats[SGE_PSTAT_MAX];
305 struct port_info *port;
306 int idx; /* qset # */
307 int qs_cpuid;
308 int qs_flags;
309 struct cv qs_cv;
310 struct mtx qs_mtx;
311 #define QS_NAME_LEN 32
312 char namebuf[QS_NAME_LEN];
313 };
314
315 struct sge {
316 struct sge_qset qs[SGE_QSETS];
317 struct mtx reg_lock;
318 };
319
320 struct filter_info;
321
322 struct adapter {
323 device_t dev;
324 int flags;
325 TAILQ_ENTRY(adapter) adapter_entry;
326
327 /* PCI register resources */
328 int regs_rid;
329 struct resource *regs_res;
330 int udbs_rid;
331 struct resource *udbs_res;
332 bus_space_handle_t bh;
333 bus_space_tag_t bt;
334 bus_size_t mmio_len;
335 uint32_t link_width;
336
337 /* DMA resources */
338 bus_dma_tag_t parent_dmat;
339 bus_dma_tag_t rx_dmat;
340 bus_dma_tag_t rx_jumbo_dmat;
341 bus_dma_tag_t tx_dmat;
342
343 /* Interrupt resources */
344 struct resource *irq_res;
345 int irq_rid;
346 void *intr_tag;
347
348 uint32_t msix_regs_rid;
349 struct resource *msix_regs_res;
350
351 struct resource *msix_irq_res[SGE_QSETS];
352 int msix_irq_rid[SGE_QSETS];
353 void *msix_intr_tag[SGE_QSETS];
354 uint8_t rxpkt_map[8]; /* maps RX_PKT interface values to port ids */
355 uint8_t rrss_map[SGE_QSETS]; /* revers RSS map table */
356 uint16_t rspq_map[RSS_TABLE_SIZE]; /* maps 7-bit cookie to qidx */
357 union {
358 uint8_t fill[SGE_QSETS];
359 uint64_t coalesce;
360 } u;
361
362 #define tunq_fill u.fill
363 #define tunq_coalesce u.coalesce
364
365 struct filter_info *filters;
366
367 /* Tasks */
368 struct task slow_intr_task;
369 struct task tick_task;
370 struct taskqueue *tq;
371 struct callout cxgb_tick_ch;
372 struct callout sge_timer_ch;
373
374 /* Register lock for use by the hardware layer */
375 struct mtx mdio_lock;
376 struct mtx elmer_lock;
377
378 /* Bookkeeping for the hardware layer */
379 struct adapter_params params;
380 unsigned int slow_intr_mask;
381 unsigned long irq_stats[IRQ_NUM_STATS];
382
383 struct sge sge;
384 struct mc7 pmrx;
385 struct mc7 pmtx;
386 struct mc7 cm;
387 struct mc5 mc5;
388
389 struct port_info port[MAX_NPORTS];
390 device_t portdev[MAX_NPORTS];
391 struct t3cdev tdev;
392 char fw_version[64];
393 char port_types[MAX_NPORTS + 1];
394 uint32_t open_device_map;
395 uint32_t registered_device_map;
396 struct mtx lock;
397 driver_intr_t *cxgb_intr;
398 int msi_count;
399
400 #define ADAPTER_LOCK_NAME_LEN 32
401 char lockbuf[ADAPTER_LOCK_NAME_LEN];
402 char reglockbuf[ADAPTER_LOCK_NAME_LEN];
403 char mdiolockbuf[ADAPTER_LOCK_NAME_LEN];
404 char elmerlockbuf[ADAPTER_LOCK_NAME_LEN];
405 };
406
407 struct t3_rx_mode {
408
409 uint32_t idx;
410 struct port_info *port;
411 };
412
413
414 #define MDIO_LOCK(adapter) mtx_lock(&(adapter)->mdio_lock)
415 #define MDIO_UNLOCK(adapter) mtx_unlock(&(adapter)->mdio_lock)
416 #define ELMR_LOCK(adapter) mtx_lock(&(adapter)->elmer_lock)
417 #define ELMR_UNLOCK(adapter) mtx_unlock(&(adapter)->elmer_lock)
418
419
420 #define PORT_LOCK(port) mtx_lock(&(port)->lock);
421 #define PORT_UNLOCK(port) mtx_unlock(&(port)->lock);
422 #define PORT_LOCK_INIT(port, name) mtx_init(&(port)->lock, name, 0, MTX_DEF)
423 #define PORT_LOCK_DEINIT(port) mtx_destroy(&(port)->lock)
424 #define PORT_LOCK_ASSERT_NOTOWNED(port) mtx_assert(&(port)->lock, MA_NOTOWNED)
425 #define PORT_LOCK_ASSERT_OWNED(port) mtx_assert(&(port)->lock, MA_OWNED)
426
427 #define ADAPTER_LOCK(adap) mtx_lock(&(adap)->lock);
428 #define ADAPTER_UNLOCK(adap) mtx_unlock(&(adap)->lock);
429 #define ADAPTER_LOCK_INIT(adap, name) mtx_init(&(adap)->lock, name, 0, MTX_DEF)
430 #define ADAPTER_LOCK_DEINIT(adap) mtx_destroy(&(adap)->lock)
431 #define ADAPTER_LOCK_ASSERT_NOTOWNED(adap) mtx_assert(&(adap)->lock, MA_NOTOWNED)
432 #define ADAPTER_LOCK_ASSERT_OWNED(adap) mtx_assert(&(adap)->lock, MA_OWNED)
433
434
435 static __inline uint32_t
436 t3_read_reg(adapter_t *adapter, uint32_t reg_addr)
437 {
438 return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr));
439 }
440
441 static __inline void
442 t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val)
443 {
444 bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val);
445 }
446
447 static __inline void
448 t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val)
449 {
450 *val = pci_read_config(adapter->dev, reg, 4);
451 }
452
453 static __inline void
454 t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val)
455 {
456 pci_write_config(adapter->dev, reg, val, 4);
457 }
458
459 static __inline void
460 t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val)
461 {
462 *val = pci_read_config(adapter->dev, reg, 2);
463 }
464
465 static __inline void
466 t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val)
467 {
468 pci_write_config(adapter->dev, reg, val, 2);
469 }
470
471 static __inline uint8_t *
472 t3_get_next_mcaddr(struct t3_rx_mode *rm)
473 {
474 uint8_t *macaddr = NULL;
475 struct ifnet *ifp = rm->port->ifp;
476 struct ifmultiaddr *ifma;
477 int i = 0;
478
479 IF_ADDR_LOCK(ifp);
480 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
481 if (ifma->ifma_addr->sa_family != AF_LINK)
482 continue;
483 if (i == rm->idx) {
484 macaddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
485 break;
486 }
487 i++;
488 }
489 IF_ADDR_UNLOCK(ifp);
490
491
492 rm->idx++;
493 return (macaddr);
494 }
495
496 static __inline void
497 t3_init_rx_mode(struct t3_rx_mode *rm, struct port_info *port)
498 {
499 rm->idx = 0;
500 rm->port = port;
501 }
502
503 static __inline struct port_info *
504 adap2pinfo(struct adapter *adap, int idx)
505 {
506 return &adap->port[idx];
507 }
508
509 int t3_os_find_pci_capability(adapter_t *adapter, int cap);
510 int t3_os_pci_save_state(struct adapter *adapter);
511 int t3_os_pci_restore_state(struct adapter *adapter);
512 void t3_os_link_intr(struct port_info *);
513 void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status,
514 int speed, int duplex, int fc, int mac_was_reset);
515 void t3_os_phymod_changed(struct adapter *adap, int port_id);
516 void t3_sge_err_intr_handler(adapter_t *adapter);
517 int t3_offload_tx(struct t3cdev *, struct mbuf *);
518 void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]);
519 int t3_mgmt_tx(adapter_t *adap, struct mbuf *m);
520
521
522 int t3_sge_alloc(struct adapter *);
523 int t3_sge_free(struct adapter *);
524 int t3_sge_alloc_qset(adapter_t *, uint32_t, int, int, const struct qset_params *,
525 int, struct port_info *);
526 void t3_free_sge_resources(adapter_t *);
527 void t3_sge_start(adapter_t *);
528 void t3_sge_stop(adapter_t *);
529 void t3b_intr(void *data);
530 void t3_intr_msi(void *data);
531 void t3_intr_msix(void *data);
532 int t3_encap(struct sge_qset *, struct mbuf **, int);
533
534 int t3_sge_init_adapter(adapter_t *);
535 int t3_sge_reset_adapter(adapter_t *);
536 int t3_sge_init_port(struct port_info *);
537 void t3_sge_deinit_sw(adapter_t *);
538 void t3_free_tx_desc(struct sge_txq *q, int n);
539 void t3_free_tx_desc_all(struct sge_txq *q);
540
541 void t3_rx_eth(struct adapter *adap, struct sge_rspq *rq, struct mbuf *m, int ethpad);
542
543 void t3_add_attach_sysctls(adapter_t *sc);
544 void t3_add_configured_sysctls(adapter_t *sc);
545 int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
546 unsigned char *data);
547 void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
548
549 /*
550 * XXX figure out how we can return this to being private to sge
551 */
552 #define desc_reclaimable(q) ((int)((q)->processed - (q)->cleaned - TX_MAX_DESC))
553
554 #define container_of(p, stype, field) ((stype *)(((uint8_t *)(p)) - offsetof(stype, field)))
555
556 static __inline struct sge_qset *
557 fl_to_qset(struct sge_fl *q, int qidx)
558 {
559 return container_of(q, struct sge_qset, fl[qidx]);
560 }
561
562 static __inline struct sge_qset *
563 rspq_to_qset(struct sge_rspq *q)
564 {
565 return container_of(q, struct sge_qset, rspq);
566 }
567
568 static __inline struct sge_qset *
569 txq_to_qset(struct sge_txq *q, int qidx)
570 {
571 return container_of(q, struct sge_qset, txq[qidx]);
572 }
573
574 static __inline struct adapter *
575 tdev2adap(struct t3cdev *d)
576 {
577 return container_of(d, struct adapter, tdev);
578 }
579
580 #undef container_of
581
582 #define OFFLOAD_DEVMAP_BIT 15
583 static inline int offload_running(adapter_t *adapter)
584 {
585 return isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT);
586 }
587
588 int cxgb_pcpu_enqueue_packet(struct ifnet *ifp, struct mbuf *m);
589 int cxgb_pcpu_start(struct ifnet *ifp, struct mbuf *m);
590 void cxgb_pcpu_shutdown_threads(struct adapter *sc);
591 void cxgb_pcpu_startup_threads(struct adapter *sc);
592
593 int process_responses(adapter_t *adap, struct sge_qset *qs, int budget);
594 void t3_free_qset(adapter_t *sc, struct sge_qset *q);
595 void cxgb_start(struct ifnet *ifp);
596 void refill_fl_service(adapter_t *adap, struct sge_fl *fl);
597 #endif
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