1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 *
30 */
31
32 #ifndef __CHELSIO_COMMON_H
33 #define __CHELSIO_COMMON_H
34
35 #include "t4_hw.h"
36
37 enum {
38 MAX_NPORTS = 4, /* max # of ports */
39 SERNUM_LEN = 24, /* Serial # length */
40 EC_LEN = 16, /* E/C length */
41 ID_LEN = 16, /* ID length */
42 PN_LEN = 16, /* Part Number length */
43 MD_LEN = 16, /* MFG diags version length */
44 MACADDR_LEN = 12, /* MAC Address length */
45 };
46
47 enum {
48 T4_REGMAP_SIZE = (160 * 1024),
49 T5_REGMAP_SIZE = (332 * 1024),
50 };
51
52 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1, MEM_HMA };
53
54 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
55
56 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
57
58 enum {
59 PAUSE_RX = 1 << 0,
60 PAUSE_TX = 1 << 1,
61 PAUSE_AUTONEG = 1 << 2
62 };
63
64 enum {
65 /*
66 * Real FECs. In the same order as the FEC portion of caps32 so that
67 * the code can do (fec & M_FW_PORT_CAP32_FEC) to get all the real FECs.
68 */
69 FEC_RS = 1 << 0, /* Reed-Solomon */
70 FEC_BASER_RS = 1 << 1, /* BASE-R, aka Firecode */
71 FEC_NONE = 1 << 2, /* no FEC */
72
73 /*
74 * Pseudo FECs that translate to real FECs. The firmware knows nothing
75 * about these and they start at M_FW_PORT_CAP32_FEC + 1. AUTO should
76 * be set all by itself.
77 */
78 FEC_AUTO = 1 << 5,
79 FEC_MODULE = 1 << 6, /* FEC suggested by the cable/transceiver. */
80 };
81
82 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
83
84 struct port_stats {
85 u64 tx_octets; /* total # of octets in good frames */
86 u64 tx_frames; /* all good frames */
87 u64 tx_bcast_frames; /* all broadcast frames */
88 u64 tx_mcast_frames; /* all multicast frames */
89 u64 tx_ucast_frames; /* all unicast frames */
90 u64 tx_error_frames; /* all error frames */
91
92 u64 tx_frames_64; /* # of Tx frames in a particular range */
93 u64 tx_frames_65_127;
94 u64 tx_frames_128_255;
95 u64 tx_frames_256_511;
96 u64 tx_frames_512_1023;
97 u64 tx_frames_1024_1518;
98 u64 tx_frames_1519_max;
99
100 u64 tx_drop; /* # of dropped Tx frames */
101 u64 tx_pause; /* # of transmitted pause frames */
102 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
103 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
104 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
105 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
106 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
107 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
108 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
109 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
110
111 u64 rx_octets; /* total # of octets in good frames */
112 u64 rx_frames; /* all good frames */
113 u64 rx_bcast_frames; /* all broadcast frames */
114 u64 rx_mcast_frames; /* all multicast frames */
115 u64 rx_ucast_frames; /* all unicast frames */
116 u64 rx_too_long; /* # of frames exceeding MTU */
117 u64 rx_jabber; /* # of jabber frames */
118 u64 rx_fcs_err; /* # of received frames with bad FCS */
119 u64 rx_len_err; /* # of received frames with length error */
120 u64 rx_symbol_err; /* symbol errors */
121 u64 rx_runt; /* # of short frames */
122
123 u64 rx_frames_64; /* # of Rx frames in a particular range */
124 u64 rx_frames_65_127;
125 u64 rx_frames_128_255;
126 u64 rx_frames_256_511;
127 u64 rx_frames_512_1023;
128 u64 rx_frames_1024_1518;
129 u64 rx_frames_1519_max;
130
131 u64 rx_pause; /* # of received pause frames */
132 u64 rx_ppp0; /* # of received PPP prio 0 frames */
133 u64 rx_ppp1; /* # of received PPP prio 1 frames */
134 u64 rx_ppp2; /* # of received PPP prio 2 frames */
135 u64 rx_ppp3; /* # of received PPP prio 3 frames */
136 u64 rx_ppp4; /* # of received PPP prio 4 frames */
137 u64 rx_ppp5; /* # of received PPP prio 5 frames */
138 u64 rx_ppp6; /* # of received PPP prio 6 frames */
139 u64 rx_ppp7; /* # of received PPP prio 7 frames */
140
141 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
142 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
143 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
144 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
145 u64 rx_trunc0; /* buffer-group 0 truncated packets */
146 u64 rx_trunc1; /* buffer-group 1 truncated packets */
147 u64 rx_trunc2; /* buffer-group 2 truncated packets */
148 u64 rx_trunc3; /* buffer-group 3 truncated packets */
149 };
150
151 struct lb_port_stats {
152 u64 octets;
153 u64 frames;
154 u64 bcast_frames;
155 u64 mcast_frames;
156 u64 ucast_frames;
157 u64 error_frames;
158
159 u64 frames_64;
160 u64 frames_65_127;
161 u64 frames_128_255;
162 u64 frames_256_511;
163 u64 frames_512_1023;
164 u64 frames_1024_1518;
165 u64 frames_1519_max;
166
167 u64 drop;
168
169 u64 ovflow0;
170 u64 ovflow1;
171 u64 ovflow2;
172 u64 ovflow3;
173 u64 trunc0;
174 u64 trunc1;
175 u64 trunc2;
176 u64 trunc3;
177 };
178
179 struct tp_tcp_stats {
180 u32 tcp_out_rsts;
181 u64 tcp_in_segs;
182 u64 tcp_out_segs;
183 u64 tcp_retrans_segs;
184 };
185
186 struct tp_usm_stats {
187 u32 frames;
188 u32 drops;
189 u64 octets;
190 };
191
192 struct tp_tid_stats {
193 u32 del;
194 u32 inv;
195 u32 act;
196 u32 pas;
197 };
198
199 struct tp_fcoe_stats {
200 u32 frames_ddp;
201 u32 frames_drop;
202 u64 octets_ddp;
203 };
204
205 struct tp_err_stats {
206 u32 mac_in_errs[MAX_NCHAN];
207 u32 hdr_in_errs[MAX_NCHAN];
208 u32 tcp_in_errs[MAX_NCHAN];
209 u32 tnl_cong_drops[MAX_NCHAN];
210 u32 ofld_chan_drops[MAX_NCHAN];
211 u32 tnl_tx_drops[MAX_NCHAN];
212 u32 ofld_vlan_drops[MAX_NCHAN];
213 u32 tcp6_in_errs[MAX_NCHAN];
214 u32 ofld_no_neigh;
215 u32 ofld_cong_defer;
216 };
217
218 struct tp_tnl_stats {
219 u32 out_pkt[MAX_NCHAN];
220 u32 in_pkt[MAX_NCHAN];
221 };
222
223 struct tp_proxy_stats {
224 u32 proxy[MAX_NCHAN];
225 };
226
227 struct tp_cpl_stats {
228 u32 req[MAX_NCHAN];
229 u32 rsp[MAX_NCHAN];
230 };
231
232 struct tp_rdma_stats {
233 u32 rqe_dfr_pkt;
234 u32 rqe_dfr_mod;
235 };
236
237 struct sge_params {
238 int timer_val[SGE_NTIMERS]; /* final, scaled values */
239 int counter_val[SGE_NCOUNTERS];
240 int fl_starve_threshold;
241 int fl_starve_threshold2;
242 int page_shift;
243 int eq_s_qpp;
244 int iq_s_qpp;
245 int spg_len;
246 int pad_boundary;
247 int pack_boundary;
248 int fl_pktshift;
249 u32 sge_control;
250 u32 sge_fl_buffer_size[SGE_FLBUF_SIZES];
251 };
252
253 struct tp_params {
254 unsigned int tre; /* log2 of core clocks per TP tick */
255 unsigned int dack_re; /* DACK timer resolution */
256 unsigned int la_mask; /* what events are recorded by TP LA */
257 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */
258
259 uint16_t filter_mode;
260 uint16_t filter_mask; /* Used by TOE and hashfilters */
261 int vnic_mode;
262 uint32_t max_rx_pdu;
263 uint32_t max_tx_pdu;
264 bool rx_pkt_encap;
265
266 int8_t fcoe_shift;
267 int8_t port_shift;
268 int8_t vnic_shift;
269 int8_t vlan_shift;
270 int8_t tos_shift;
271 int8_t protocol_shift;
272 int8_t ethertype_shift;
273 int8_t macmatch_shift;
274 int8_t matchtype_shift;
275 int8_t frag_shift;
276 };
277
278 struct vpd_params {
279 unsigned int cclk;
280 u8 ec[EC_LEN + 1];
281 u8 sn[SERNUM_LEN + 1];
282 u8 id[ID_LEN + 1];
283 u8 pn[PN_LEN + 1];
284 u8 na[MACADDR_LEN + 1];
285 u8 md[MD_LEN + 1];
286 };
287
288 struct pci_params {
289 unsigned int vpd_cap_addr;
290 unsigned int mps;
291 unsigned short speed;
292 unsigned short width;
293 };
294
295 /*
296 * Firmware device log.
297 */
298 struct devlog_params {
299 u32 memtype; /* which memory (FW_MEMTYPE_* ) */
300 u32 start; /* start of log in firmware memory */
301 u32 size; /* size of log */
302 u32 addr; /* start address in flat addr space */
303 };
304
305 /* Stores chip specific parameters */
306 struct chip_params {
307 u8 nchan;
308 u8 pm_stats_cnt;
309 u8 cng_ch_bits_log; /* congestion channel map bits width */
310 u8 nsched_cls;
311 u8 cim_num_obq;
312 u8 filter_opt_len;
313 u16 mps_rplc_size;
314 u16 vfcount;
315 u32 sge_fl_db;
316 u16 mps_tcam_size;
317 u16 rss_nentries;
318 };
319
320 /* VF-only parameters. */
321
322 /*
323 * Global Receive Side Scaling (RSS) parameters in host-native format.
324 */
325 struct rss_params {
326 unsigned int mode; /* RSS mode */
327 union {
328 struct {
329 u_int synmapen:1; /* SYN Map Enable */
330 u_int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */
331 u_int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */
332 u_int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */
333 u_int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */
334 u_int ofdmapen:1; /* Offload Map Enable */
335 u_int tnlmapen:1; /* Tunnel Map Enable */
336 u_int tnlalllookup:1; /* Tunnel All Lookup */
337 u_int hashtoeplitz:1; /* use Toeplitz hash */
338 } basicvirtual;
339 } u;
340 };
341
342 /*
343 * Maximum resources provisioned for a PCI VF.
344 */
345 struct vf_resources {
346 unsigned int nvi; /* N virtual interfaces */
347 unsigned int neq; /* N egress Qs */
348 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
349 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
350 unsigned int niq; /* N ingress Qs */
351 unsigned int tc; /* PCI-E traffic class */
352 unsigned int pmask; /* port access rights mask */
353 unsigned int nexactf; /* N exact MPS filters */
354 unsigned int r_caps; /* read capabilities */
355 unsigned int wx_caps; /* write/execute capabilities */
356 };
357
358 struct adapter_params {
359 struct sge_params sge;
360 struct tp_params tp; /* PF-only */
361 struct vpd_params vpd;
362 struct pci_params pci;
363 struct devlog_params devlog; /* PF-only */
364 struct rss_params rss; /* VF-only */
365 struct vf_resources vfres; /* VF-only */
366 unsigned int core_vdd;
367
368 unsigned int sf_size; /* serial flash size in bytes */
369 unsigned int sf_nsec; /* # of flash sectors */
370
371 unsigned int fw_vers; /* firmware version */
372 unsigned int bs_vers; /* bootstrap version */
373 unsigned int tp_vers; /* TP microcode version */
374 unsigned int er_vers; /* expansion ROM version */
375 unsigned int scfg_vers; /* Serial Configuration version */
376 unsigned int vpd_vers; /* VPD version */
377
378 unsigned short mtus[NMTUS];
379 unsigned short a_wnd[NCCTRL_WIN];
380 unsigned short b_wnd[NCCTRL_WIN];
381
382 unsigned int cim_la_size;
383
384 uint8_t nports; /* # of ethernet ports */
385 uint8_t portvec;
386 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */
387 unsigned int rev:4; /* chip revision */
388 unsigned int fpga:1; /* this is an FPGA */
389 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card
390 resources for TOE operation. */
391 unsigned int bypass:1; /* this is a bypass card */
392 unsigned int ethoffload:1;
393 unsigned int hash_filter:1;
394 unsigned int filter2_wr_support:1;
395 unsigned int port_caps32:1;
396 unsigned int smac_add_support:1;
397
398 unsigned int ofldq_wr_cred;
399 unsigned int eo_wr_cred;
400
401 unsigned int max_ordird_qp;
402 unsigned int max_ird_adapter;
403
404 uint32_t mps_bg_map; /* rx buffer group map for all ports (upto 4) */
405
406 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
407 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
408 bool dev_512sgl_mr; /* FW support for 512 SGL per FR MR */
409 bool viid_smt_extn_support; /* FW returns vin, vfvld & smt index? */
410 unsigned int max_pkts_per_eth_tx_pkts_wr;
411 uint8_t nsched_cls; /* # of usable sched classes per port */
412 };
413
414 #define CHELSIO_T4 0x4
415 #define CHELSIO_T5 0x5
416 #define CHELSIO_T6 0x6
417
418 /*
419 * State needed to monitor the forward progress of SGE Ingress DMA activities
420 * and possible hangs.
421 */
422 struct sge_idma_monitor_state {
423 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
424 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
425 unsigned int idma_state[2]; /* IDMA Hang detect state */
426 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
427 unsigned int idma_warn[2]; /* time to warning in HZ */
428 };
429
430 struct trace_params {
431 u32 data[TRACE_LEN / 4];
432 u32 mask[TRACE_LEN / 4];
433 unsigned short snap_len;
434 unsigned short min_len;
435 unsigned char skip_ofst;
436 unsigned char skip_len;
437 unsigned char invert;
438 unsigned char port;
439 };
440
441 struct link_config {
442 /* OS-specific code owns all the requested_* fields. */
443 int8_t requested_aneg; /* link autonegotiation */
444 int8_t requested_fc; /* flow control */
445 int8_t requested_fec; /* FEC */
446 int8_t force_fec; /* FORCE_FEC in L1_CFG32 command. */
447 u_int requested_speed; /* speed (Mbps) */
448 uint32_t requested_caps;/* rcap in last l1cfg issued by the driver. */
449
450 /* These are populated with information from the firmware. */
451 uint32_t pcaps; /* link capabilities */
452 uint32_t acaps; /* advertised capabilities */
453 uint32_t lpacaps; /* peer advertised capabilities */
454 u_int speed; /* actual link speed (Mbps) */
455 int8_t fc; /* actual link flow control */
456 int8_t fec_hint; /* cable/transceiver recommended fec */
457 int8_t fec; /* actual FEC */
458 bool link_ok; /* link up? */
459 uint8_t link_down_rc; /* link down reason */
460 };
461
462 #include "adapter.h"
463
464 #ifndef PCI_VENDOR_ID_CHELSIO
465 # define PCI_VENDOR_ID_CHELSIO 0x1425
466 #endif
467
468 #define for_each_port(adapter, iter) \
469 for (iter = 0; iter < (adapter)->params.nports; ++iter)
470
471 static inline int is_ftid(const struct adapter *sc, u_int tid)
472 {
473
474 return (sc->tids.nftids > 0 && tid >= sc->tids.ftid_base &&
475 tid <= sc->tids.ftid_end);
476 }
477
478 static inline int is_hpftid(const struct adapter *sc, u_int tid)
479 {
480
481 return (sc->tids.nhpftids > 0 && tid >= sc->tids.hpftid_base &&
482 tid <= sc->tids.hpftid_end);
483 }
484
485 static inline int is_etid(const struct adapter *sc, u_int tid)
486 {
487
488 return (sc->tids.netids > 0 && tid >= sc->tids.etid_base &&
489 tid <= sc->tids.etid_end);
490 }
491
492 static inline int is_offload(const struct adapter *adap)
493 {
494 return adap->params.offload;
495 }
496
497 static inline int is_ethoffload(const struct adapter *adap)
498 {
499 return adap->params.ethoffload;
500 }
501
502 static inline int is_hashfilter(const struct adapter *adap)
503 {
504 return adap->params.hash_filter;
505 }
506
507 static inline int is_ktls(const struct adapter *adap)
508 {
509 return adap->cryptocaps & FW_CAPS_CONFIG_TLS_HW;
510 }
511
512 static inline int chip_id(struct adapter *adap)
513 {
514 return adap->params.chipid;
515 }
516
517 static inline int chip_rev(struct adapter *adap)
518 {
519 return adap->params.rev;
520 }
521
522 static inline int is_t4(struct adapter *adap)
523 {
524 return adap->params.chipid == CHELSIO_T4;
525 }
526
527 static inline int is_t5(struct adapter *adap)
528 {
529 return adap->params.chipid == CHELSIO_T5;
530 }
531
532 static inline int is_t6(struct adapter *adap)
533 {
534 return adap->params.chipid == CHELSIO_T6;
535 }
536
537 static inline int is_fpga(struct adapter *adap)
538 {
539 return adap->params.fpga;
540 }
541
542 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
543 {
544 return adap->params.vpd.cclk / 1000;
545 }
546
547 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
548 unsigned int us)
549 {
550 return (us * adap->params.vpd.cclk) / 1000;
551 }
552
553 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
554 unsigned int ticks)
555 {
556 /* add Core Clock / 2 to round ticks to nearest uS */
557 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
558 adapter->params.vpd.cclk);
559 }
560
561 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
562 unsigned int ticks)
563 {
564 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
565 }
566
567 static inline u_int us_to_tcp_ticks(const struct adapter *adap, u_long us)
568 {
569
570 return (us * adap->params.vpd.cclk / 1000 >> adap->params.tp.tre);
571 }
572
573 static inline u_int tcp_ticks_to_us(const struct adapter *adap, u_int ticks)
574 {
575 return ((uint64_t)ticks << adap->params.tp.tre) /
576 core_ticks_per_usec(adap);
577 }
578
579 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val);
580
581 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
582 int size, void *rpl, bool sleep_ok, int timeout);
583 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
584 void *rpl, bool sleep_ok);
585 void t4_report_fw_error(struct adapter *adap);
586
587 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
588 const void *cmd, int size, void *rpl,
589 int timeout)
590 {
591 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
592 timeout);
593 }
594
595 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
596 int size, void *rpl)
597 {
598 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
599 }
600
601 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
602 int size, void *rpl)
603 {
604 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
605 }
606
607 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
608 unsigned int data_reg, u32 *vals, unsigned int nregs,
609 unsigned int start_idx);
610 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
611 unsigned int data_reg, const u32 *vals,
612 unsigned int nregs, unsigned int start_idx);
613
614 u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg);
615
616 struct fw_filter_wr;
617
618 void t4_intr_enable(struct adapter *adapter);
619 void t4_intr_disable(struct adapter *adapter);
620 void t4_intr_clear(struct adapter *adapter);
621 bool t4_slow_intr_handler(struct adapter *adapter, bool verbose);
622
623 int t4_hash_mac_addr(const u8 *addr);
624 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
625 struct link_config *lc);
626 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
627 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
628 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
629 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
630 int t4_seeprom_wp(struct adapter *adapter, int enable);
631 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords,
632 u32 *data, int byte_oriented);
633 int t4_write_flash(struct adapter *adapter, unsigned int addr,
634 unsigned int n, const u8 *data, int byte_oriented);
635 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
636 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
637 int t5_fw_init_extern_mem(struct adapter *adap);
638 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
639 int t4_load_boot(struct adapter *adap, u8 *boot_data,
640 unsigned int boot_addr, unsigned int size);
641 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end);
642 int t4_flash_cfg_addr(struct adapter *adapter);
643 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
644 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
645 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr);
646 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
647 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
648 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
649 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
650 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
651 int t4_get_version_info(struct adapter *adapter);
652 int t4_init_hw(struct adapter *adapter, u32 fw_params);
653 const struct chip_params *t4_get_chip_params(int chipid);
654 int t4_prep_adapter(struct adapter *adapter, u32 *buf);
655 int t4_shutdown_adapter(struct adapter *adapter);
656 int t4_init_devlog_params(struct adapter *adapter, int fw_attach);
657 int t4_init_sge_params(struct adapter *adapter);
658 int t4_init_tp_params(struct adapter *adap);
659 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
660 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id);
661 void t4_fatal_err(struct adapter *adapter, bool fw_error);
662 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
663 int filter_index, int enable);
664 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
665 int filter_index, int *enabled);
666 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
667 int start, int n, const u16 *rspq, unsigned int nrspq);
668 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
669 unsigned int flags);
670 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
671 unsigned int flags, unsigned int defq, unsigned int skeyidx,
672 unsigned int skey);
673 int t4_read_rss(struct adapter *adapter, u16 *entries);
674 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
675 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
676 bool sleep_ok);
677 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
678 u32 *valp, bool sleep_ok);
679 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
680 u32 val, bool sleep_ok);
681 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
682 u32 *vfl, u32 *vfh, bool sleep_ok);
683 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
684 u32 vfl, u32 vfh, bool sleep_ok);
685 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
686 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok);
687 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
688 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok);
689 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
690 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
691 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
692 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
693 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
694 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
695 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
696 unsigned int *valp);
697 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
698 const unsigned int *valp);
699 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
700 unsigned int *valp);
701 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
702 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
703 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr);
704 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
705 int t4_get_flash_params(struct adapter *adapter);
706
707 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach);
708 int t4_mc_read(struct adapter *adap, int idx, u32 addr,
709 __be32 *data, u64 *parity);
710 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity);
711 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size,
712 __be32 *data);
713 void t4_idma_monitor_init(struct adapter *adapter,
714 struct sge_idma_monitor_state *idma);
715 void t4_idma_monitor(struct adapter *adapter,
716 struct sge_idma_monitor_state *idma,
717 int hz, int ticks);
718 int t4_set_vf_mac(struct adapter *adapter, unsigned int pf, unsigned int vf,
719 unsigned int naddr, u8 *addr);
720
721 unsigned int t4_get_regs_len(struct adapter *adapter);
722 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size);
723
724 const char *t4_get_port_type_description(enum fw_port_type port_type);
725 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
726 void t4_get_port_stats_offset(struct adapter *adap, int idx,
727 struct port_stats *stats,
728 struct port_stats *offset);
729 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
730 void t4_clr_port_stats(struct adapter *adap, int idx);
731
732 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
733 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
734 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
735 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
736 unsigned int *ipg, bool sleep_ok);
737 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
738 unsigned int mask, unsigned int val);
739 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
740 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
741 bool sleep_ok);
742 void t4_tp_get_tnl_stats(struct adapter *adap, struct tp_tnl_stats *st,
743 bool sleep_ok);
744 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st,
745 bool sleep_ok);
746 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
747 bool sleep_ok);
748 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
749 bool sleep_ok);
750 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
751 bool sleep_ok);
752 void t4_tp_get_tid_stats(struct adapter *adap, struct tp_tid_stats *st,
753 bool sleep_ok);
754 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
755 struct tp_tcp_stats *v6, bool sleep_ok);
756 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
757 struct tp_fcoe_stats *st, bool sleep_ok);
758 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
759 const unsigned short *alpha, const unsigned short *beta);
760
761 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
762
763 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps);
764 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg);
765 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
766 unsigned int start, unsigned int n);
767 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
768 int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode);
769 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
770
771 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr);
772 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
773 u64 mask0, u64 mask1, unsigned int crc, bool enable);
774
775 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
776 enum dev_master master, enum dev_state *state);
777 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
778 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
779 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force);
780 int t4_fw_restart(struct adapter *adap, unsigned int mbox);
781 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
782 const u8 *fw_data, unsigned int size, int force);
783 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
784 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
785 unsigned int vf, unsigned int nparams, const u32 *params,
786 u32 *val);
787 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
788 unsigned int vf, unsigned int nparams, const u32 *params,
789 u32 *val, int rw);
790 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
791 unsigned int pf, unsigned int vf,
792 unsigned int nparams, const u32 *params,
793 const u32 *val, int timeout);
794 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
795 unsigned int vf, unsigned int nparams, const u32 *params,
796 const u32 *val);
797 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
798 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
799 unsigned int rxqi, unsigned int rxq, unsigned int tc,
800 unsigned int vi, unsigned int cmask, unsigned int pmask,
801 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps);
802 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
803 unsigned int port, unsigned int pf, unsigned int vf,
804 unsigned int nmac, u8 *mac, u16 *rss_size,
805 uint8_t *vfvld, uint16_t *vin,
806 unsigned int portfunc, unsigned int idstype);
807 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
808 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
809 u16 *rss_size, uint8_t *vfvld, uint16_t *vin);
810 int t4_free_vi(struct adapter *adap, unsigned int mbox,
811 unsigned int pf, unsigned int vf,
812 unsigned int viid);
813 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
814 int mtu, int promisc, int all_multi, int bcast, int vlanex,
815 bool sleep_ok);
816 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid,
817 bool free, unsigned int naddr, const u8 **addr, u16 *idx,
818 u64 *hash, bool sleep_ok);
819 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
820 unsigned int viid, unsigned int naddr,
821 const u8 **addr, bool sleep_ok);
822 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
823 int idx, bool sleep_ok);
824 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
825 const u8 *addr, const u8 *mask, unsigned int idx,
826 u8 lookup_type, u8 port_id, bool sleep_ok);
827 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
828 const u8 *addr, const u8 *mask, unsigned int idx,
829 u8 lookup_type, u8 port_id, bool sleep_ok);
830 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
831 const u8 *addr, const u8 *mask, unsigned int vni,
832 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
833 bool sleep_ok);
834 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
835 int idx, const u8 *addr, bool persist, uint16_t *smt_idx);
836 int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
837 const u8 *addr, bool smac);
838 int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
839 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac);
840 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
841 bool ucast, u64 vec, bool sleep_ok);
842 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
843 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
844 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
845 bool rx_en, bool tx_en);
846 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
847 unsigned int nblinks);
848 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
849 unsigned int mmd, unsigned int reg, unsigned int *valp);
850 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
851 unsigned int mmd, unsigned int reg, unsigned int val);
852 int t4_i2c_io(struct adapter *adap, unsigned int mbox,
853 int port, unsigned int devid,
854 unsigned int offset, unsigned int len,
855 u8 *buf, bool write);
856 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
857 int port, unsigned int devid,
858 unsigned int offset, unsigned int len,
859 u8 *buf);
860 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
861 int port, unsigned int devid,
862 unsigned int offset, unsigned int len,
863 u8 *buf);
864 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
865 unsigned int vf, unsigned int iqtype, unsigned int iqid,
866 unsigned int fl0id, unsigned int fl1id);
867 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
868 unsigned int vf, unsigned int iqtype, unsigned int iqid,
869 unsigned int fl0id, unsigned int fl1id);
870 int t4_eth_eq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
871 unsigned int vf, unsigned int eqid);
872 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
873 unsigned int vf, unsigned int eqid);
874 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
875 unsigned int vf, unsigned int eqid);
876 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
877 unsigned int vf, unsigned int eqid);
878 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
879 enum ctxt_type ctype, u32 *data);
880 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
881 u32 *data);
882 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
883 const char *t4_link_down_rc_str(unsigned char link_down_rc);
884 int t4_update_port_info(struct port_info *pi);
885 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
886 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val);
887 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
888 int sleep_ok);
889 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
890 int rateunit, int ratemode, int channel, int cl,
891 int minrate, int maxrate, int weight, int pktsize,
892 int burstsize, int sleep_ok);
893 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode,
894 unsigned int maxrate, int sleep_ok);
895 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl,
896 int weight, int sleep_ok);
897 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl,
898 int mode, unsigned int maxrate, int pktsize,
899 int sleep_ok);
900 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
901 unsigned int pf, unsigned int vf,
902 unsigned int timeout, unsigned int action);
903 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level);
904 int t4_set_devlog_level(struct adapter *adapter, unsigned int level);
905 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
906
907 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
908 u32 start_index, bool sleep_ok);
909 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs,
910 u32 start_index, bool sleep_ok);
911 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
912 u32 start_index, bool sleep_ok);
913 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
914 u32 start_index, bool sleep_ok);
915 int t4_configure_ringbb(struct adapter *adap);
916 int t4_configure_add_smac(struct adapter *adap);
917 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
918 u16 vlan);
919
920 static inline int t4vf_query_params(struct adapter *adapter,
921 unsigned int nparams, const u32 *params,
922 u32 *vals)
923 {
924 return t4_query_params(adapter, 0, 0, 0, nparams, params, vals);
925 }
926
927 static inline int t4vf_set_params(struct adapter *adapter,
928 unsigned int nparams, const u32 *params,
929 const u32 *vals)
930 {
931 return t4_set_params(adapter, 0, 0, 0, nparams, params, vals);
932 }
933
934 static inline int t4vf_wr_mbox(struct adapter *adap, const void *cmd,
935 int size, void *rpl)
936 {
937 return t4_wr_mbox(adap, adap->mbox, cmd, size, rpl);
938 }
939
940 int t4vf_wait_dev_ready(struct adapter *adapter);
941 int t4vf_fw_reset(struct adapter *adapter);
942 int t4vf_get_sge_params(struct adapter *adapter);
943 int t4vf_get_rss_glb_config(struct adapter *adapter);
944 int t4vf_get_vfres(struct adapter *adapter);
945 int t4vf_prep_adapter(struct adapter *adapter);
946 int t4vf_get_vf_mac(struct adapter *adapter, unsigned int port,
947 unsigned int *naddr, u8 *addr);
948 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
949 enum t4_bar2_qtype qtype, int user, u64 *pbar2_qoffset,
950 unsigned int *pbar2_qid);
951 unsigned int fwcap_to_speed(uint32_t caps);
952 uint32_t speed_to_fwcap(unsigned int speed);
953 uint32_t fwcap_top_speed(uint32_t caps);
954
955 static inline int
956 port_top_speed(const struct port_info *pi)
957 {
958
959 /* Mbps -> Gbps */
960 return (fwcap_to_speed(pi->link_cfg.pcaps) / 1000);
961 }
962
963 #endif /* __CHELSIO_COMMON_H */
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