1 /*-
2 * Copyright (c) 2012-2017 Chelsio Communications, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 *
28 */
29
30 #ifndef _T4FW_INTERFACE_H_
31 #define _T4FW_INTERFACE_H_
32
33 /******************************************************************************
34 * R E T U R N V A L U E S
35 ********************************/
36
37 enum fw_retval {
38 FW_SUCCESS = 0, /* completed successfully */
39 FW_EPERM = 1, /* operation not permitted */
40 FW_ENOENT = 2, /* no such file or directory */
41 FW_EIO = 5, /* input/output error; hw bad */
42 FW_ENOEXEC = 8, /* exec format error; inv microcode */
43 FW_EAGAIN = 11, /* try again */
44 FW_ENOMEM = 12, /* out of memory */
45 FW_EFAULT = 14, /* bad address; fw bad */
46 FW_EBUSY = 16, /* resource busy */
47 FW_EEXIST = 17, /* file exists */
48 FW_ENODEV = 19, /* no such device */
49 FW_EINVAL = 22, /* invalid argument */
50 FW_ENOSPC = 28, /* no space left on device */
51 FW_ENOSYS = 38, /* functionality not implemented */
52 FW_ENODATA = 61, /* no data available */
53 FW_EPROTO = 71, /* protocol error */
54 FW_EADDRINUSE = 98, /* address already in use */
55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
56 FW_ENETDOWN = 100, /* network is down */
57 FW_ENETUNREACH = 101, /* network is unreachable */
58 FW_ENOBUFS = 105, /* no buffer space available */
59 FW_ETIMEDOUT = 110, /* timeout */
60 FW_EINPROGRESS = 115, /* fw internal */
61 FW_SCSI_ABORT_REQUESTED = 128, /* */
62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */
63 FW_SCSI_ABORTED = 130, /* */
64 FW_SCSI_CLOSE_REQUESTED = 131, /* */
65 FW_ERR_LINK_DOWN = 132, /* */
66 FW_RDEV_NOT_READY = 133, /* */
67 FW_ERR_RDEV_LOST = 134, /* */
68 FW_ERR_RDEV_LOGO = 135, /* */
69 FW_FCOE_NO_XCHG = 136, /* */
70 FW_SCSI_RSP_ERR = 137, /* */
71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */
72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */
73 FW_SCSI_OVER_FLOW_ERR = 140, /* */
74 FW_SCSI_DDP_ERR = 141, /* DDP error*/
75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */
76 FW_SCSI_IO_BLOCK = 143, /* IO is going to be blocked due to resource failure */
77 };
78
79 /******************************************************************************
80 * M E M O R Y T Y P E s
81 ******************************/
82
83 enum fw_memtype {
84 FW_MEMTYPE_EDC0 = 0x0,
85 FW_MEMTYPE_EDC1 = 0x1,
86 FW_MEMTYPE_EXTMEM = 0x2,
87 FW_MEMTYPE_FLASH = 0x4,
88 FW_MEMTYPE_INTERNAL = 0x5,
89 FW_MEMTYPE_EXTMEM1 = 0x6,
90 FW_MEMTYPE_HMA = 0x7,
91 };
92
93 /******************************************************************************
94 * W O R K R E Q U E S T s
95 ********************************/
96
97 enum fw_wr_opcodes {
98 FW_FRAG_WR = 0x1d,
99 FW_FILTER_WR = 0x02,
100 FW_ULPTX_WR = 0x04,
101 FW_TP_WR = 0x05,
102 FW_ETH_TX_PKT_WR = 0x08,
103 FW_ETH_TX_PKT2_WR = 0x44,
104 FW_ETH_TX_PKTS_WR = 0x09,
105 FW_ETH_TX_PKTS2_WR = 0x78,
106 FW_ETH_TX_EO_WR = 0x1c,
107 FW_EQ_FLUSH_WR = 0x1b,
108 FW_OFLD_CONNECTION_WR = 0x2f,
109 FW_FLOWC_WR = 0x0a,
110 FW_OFLD_TX_DATA_WR = 0x0b,
111 FW_CMD_WR = 0x10,
112 FW_ETH_TX_PKT_VM_WR = 0x11,
113 FW_ETH_TX_PKTS_VM_WR = 0x12,
114 FW_RI_RES_WR = 0x0c,
115 FW_RI_RDMA_WRITE_WR = 0x14,
116 FW_RI_SEND_WR = 0x15,
117 FW_RI_RDMA_READ_WR = 0x16,
118 FW_RI_RECV_WR = 0x17,
119 FW_RI_BIND_MW_WR = 0x18,
120 FW_RI_FR_NSMR_WR = 0x19,
121 FW_RI_FR_NSMR_TPTE_WR = 0x20,
122 FW_RI_RDMA_WRITE_CMPL_WR = 0x21,
123 FW_RI_INV_LSTAG_WR = 0x1a,
124 FW_RI_SEND_IMMEDIATE_WR = 0x15,
125 FW_RI_ATOMIC_WR = 0x16,
126 FW_RI_WR = 0x0d,
127 FW_CHNET_IFCONF_WR = 0x6b,
128 FW_RDEV_WR = 0x38,
129 FW_FOISCSI_NODE_WR = 0x60,
130 FW_FOISCSI_CTRL_WR = 0x6a,
131 FW_FOISCSI_CHAP_WR = 0x6c,
132 FW_FCOE_ELS_CT_WR = 0x30,
133 FW_SCSI_WRITE_WR = 0x31,
134 FW_SCSI_READ_WR = 0x32,
135 FW_SCSI_CMD_WR = 0x33,
136 FW_SCSI_ABRT_CLS_WR = 0x34,
137 FW_SCSI_TGT_ACC_WR = 0x35,
138 FW_SCSI_TGT_XMIT_WR = 0x36,
139 FW_SCSI_TGT_RSP_WR = 0x37,
140 FW_POFCOE_TCB_WR = 0x42,
141 FW_POFCOE_ULPTX_WR = 0x43,
142 FW_ISCSI_TX_DATA_WR = 0x45,
143 FW_PTP_TX_PKT_WR = 0x46,
144 FW_TLSTX_DATA_WR = 0x68,
145 FW_TLS_TUNNEL_OFLD_WR = 0x69,
146 FW_CRYPTO_LOOKASIDE_WR = 0x6d,
147 FW_COISCSI_TGT_WR = 0x70,
148 FW_COISCSI_TGT_CONN_WR = 0x71,
149 FW_COISCSI_TGT_XMIT_WR = 0x72,
150 FW_COISCSI_STATS_WR = 0x73,
151 FW_ISNS_WR = 0x75,
152 FW_ISNS_XMIT_WR = 0x76,
153 FW_FILTER2_WR = 0x77,
154 FW_LASTC2E_WR = 0x80
155 };
156
157 /*
158 * Generic work request header flit0
159 */
160 struct fw_wr_hdr {
161 __be32 hi;
162 __be32 lo;
163 };
164
165 /* work request opcode (hi)
166 */
167 #define S_FW_WR_OP 24
168 #define M_FW_WR_OP 0xff
169 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
170 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
171
172 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
173 */
174 #define S_FW_WR_ATOMIC 23
175 #define M_FW_WR_ATOMIC 0x1
176 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC)
177 #define G_FW_WR_ATOMIC(x) \
178 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
179 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U)
180
181 /* flush flag (hi) - firmware flushes flushable work request buffered
182 * in the flow context.
183 */
184 #define S_FW_WR_FLUSH 22
185 #define M_FW_WR_FLUSH 0x1
186 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH)
187 #define G_FW_WR_FLUSH(x) \
188 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
189 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U)
190
191 /* completion flag (hi) - firmware generates a cpl_fw6_ack
192 */
193 #define S_FW_WR_COMPL 21
194 #define M_FW_WR_COMPL 0x1
195 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL)
196 #define G_FW_WR_COMPL(x) \
197 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
198 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U)
199
200
201 /* work request immediate data lengh (hi)
202 */
203 #define S_FW_WR_IMMDLEN 0
204 #define M_FW_WR_IMMDLEN 0xff
205 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
206 #define G_FW_WR_IMMDLEN(x) \
207 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
208
209 /* egress queue status update to associated ingress queue entry (lo)
210 */
211 #define S_FW_WR_EQUIQ 31
212 #define M_FW_WR_EQUIQ 0x1
213 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ)
214 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
215 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U)
216
217 /* egress queue status update to egress queue status entry (lo)
218 */
219 #define S_FW_WR_EQUEQ 30
220 #define M_FW_WR_EQUEQ 0x1
221 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
222 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
223 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
224
225 /* flow context identifier (lo)
226 */
227 #define S_FW_WR_FLOWID 8
228 #define M_FW_WR_FLOWID 0xfffff
229 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
230 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)
231
232 /* length in units of 16-bytes (lo)
233 */
234 #define S_FW_WR_LEN16 0
235 #define M_FW_WR_LEN16 0xff
236 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
237 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
238
239 struct fw_frag_wr {
240 __be32 op_to_fragoff16;
241 __be32 flowid_len16;
242 __be64 r4;
243 };
244
245 #define S_FW_FRAG_WR_EOF 15
246 #define M_FW_FRAG_WR_EOF 0x1
247 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF)
248 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)
249 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U)
250
251 #define S_FW_FRAG_WR_FRAGOFF16 8
252 #define M_FW_FRAG_WR_FRAGOFF16 0x7f
253 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16)
254 #define G_FW_FRAG_WR_FRAGOFF16(x) \
255 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)
256
257 /* valid filter configurations for compressed tuple
258 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
259 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
260 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
261 * OV - Outer VLAN/VNIC_ID,
262 */
263 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3
264 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3
265 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B
266 #define HW_TPL_FR_MT_M_OV_P_FC 0x387
267 #define HW_TPL_FR_MT_E_PR_T 0x370
268 #define HW_TPL_FR_MT_E_PR_P_FC 0X363
269 #define HW_TPL_FR_MT_E_T_P_FC 0X353
270 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
271 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327
272 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B
273 #define HW_TPL_FR_MT_T_OV_P_FC 0X317
274 #define HW_TPL_FR_M_E_PR_FC 0X2E1
275 #define HW_TPL_FR_M_E_T_FC 0X2D1
276 #define HW_TPL_FR_M_PR_IV_FC 0X2A9
277 #define HW_TPL_FR_M_PR_OV_FC 0X2A5
278 #define HW_TPL_FR_M_T_IV_FC 0X299
279 #define HW_TPL_FR_M_T_OV_FC 0X295
280 #define HW_TPL_FR_E_PR_T_P 0X272
281 #define HW_TPL_FR_E_PR_T_FC 0X271
282 #define HW_TPL_FR_E_IV_FC 0X249
283 #define HW_TPL_FR_E_OV_FC 0X245
284 #define HW_TPL_FR_PR_T_IV_FC 0X239
285 #define HW_TPL_FR_PR_T_OV_FC 0X235
286 #define HW_TPL_FR_IV_OV_FC 0X20D
287 #define HW_TPL_MT_M_E_PR 0X1E0
288 #define HW_TPL_MT_M_E_T 0X1D0
289 #define HW_TPL_MT_E_PR_T_FC 0X171
290 #define HW_TPL_MT_E_IV 0X148
291 #define HW_TPL_MT_E_OV 0X144
292 #define HW_TPL_MT_PR_T_IV 0X138
293 #define HW_TPL_MT_PR_T_OV 0X134
294 #define HW_TPL_M_E_PR_P 0X0E2
295 #define HW_TPL_M_E_T_P 0X0D2
296 #define HW_TPL_E_PR_T_P_FC 0X073
297 #define HW_TPL_E_IV_P 0X04A
298 #define HW_TPL_E_OV_P 0X046
299 #define HW_TPL_PR_T_IV_P 0X03A
300 #define HW_TPL_PR_T_OV_P 0X036
301
302 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
303 enum fw_filter_wr_cookie {
304 FW_FILTER_WR_SUCCESS,
305 FW_FILTER_WR_FLT_ADDED,
306 FW_FILTER_WR_FLT_DELETED,
307 FW_FILTER_WR_SMT_TBL_FULL,
308 FW_FILTER_WR_EINVAL,
309 };
310
311 enum fw_filter_wr_nat_mode {
312 FW_FILTER_WR_NATMODE_NONE = 0,
313 FW_FILTER_WR_NATMODE_DIP ,
314 FW_FILTER_WR_NATMODE_DIPDP,
315 FW_FILTER_WR_NATMODE_DIPDPSIP,
316 FW_FILTER_WR_NATMODE_DIPDPSP,
317 FW_FILTER_WR_NATMODE_SIPSP,
318 FW_FILTER_WR_NATMODE_DIPSIPSP,
319 FW_FILTER_WR_NATMODE_FOURTUPLE,
320 };
321
322 struct fw_filter_wr {
323 __be32 op_pkd;
324 __be32 len16_pkd;
325 __be64 r3;
326 __be32 tid_to_iq;
327 __be32 del_filter_to_l2tix;
328 __be16 ethtype;
329 __be16 ethtypem;
330 __u8 frag_to_ovlan_vldm;
331 __u8 smac_sel;
332 __be16 rx_chan_rx_rpl_iq;
333 __be32 maci_to_matchtypem;
334 __u8 ptcl;
335 __u8 ptclm;
336 __u8 ttyp;
337 __u8 ttypm;
338 __be16 ivlan;
339 __be16 ivlanm;
340 __be16 ovlan;
341 __be16 ovlanm;
342 __u8 lip[16];
343 __u8 lipm[16];
344 __u8 fip[16];
345 __u8 fipm[16];
346 __be16 lp;
347 __be16 lpm;
348 __be16 fp;
349 __be16 fpm;
350 __be16 r7;
351 __u8 sma[6];
352 };
353
354 struct fw_filter2_wr {
355 __be32 op_pkd;
356 __be32 len16_pkd;
357 __be64 r3;
358 __be32 tid_to_iq;
359 __be32 del_filter_to_l2tix;
360 __be16 ethtype;
361 __be16 ethtypem;
362 __u8 frag_to_ovlan_vldm;
363 __u8 smac_sel;
364 __be16 rx_chan_rx_rpl_iq;
365 __be32 maci_to_matchtypem;
366 __u8 ptcl;
367 __u8 ptclm;
368 __u8 ttyp;
369 __u8 ttypm;
370 __be16 ivlan;
371 __be16 ivlanm;
372 __be16 ovlan;
373 __be16 ovlanm;
374 __u8 lip[16];
375 __u8 lipm[16];
376 __u8 fip[16];
377 __u8 fipm[16];
378 __be16 lp;
379 __be16 lpm;
380 __be16 fp;
381 __be16 fpm;
382 __be16 r7;
383 __u8 sma[6];
384 __be16 r8;
385 __u8 filter_type_swapmac;
386 __u8 natmode_to_ulp_type;
387 __be16 newlport;
388 __be16 newfport;
389 __u8 newlip[16];
390 __u8 newfip[16];
391 __be32 natseqcheck;
392 __be32 r9;
393 __be64 r10;
394 __be64 r11;
395 __be64 r12;
396 __be64 r13;
397 };
398
399 #define S_FW_FILTER_WR_TID 12
400 #define M_FW_FILTER_WR_TID 0xfffff
401 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
402 #define G_FW_FILTER_WR_TID(x) \
403 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
404
405 #define S_FW_FILTER_WR_RQTYPE 11
406 #define M_FW_FILTER_WR_RQTYPE 0x1
407 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
408 #define G_FW_FILTER_WR_RQTYPE(x) \
409 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
410 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U)
411
412 #define S_FW_FILTER_WR_NOREPLY 10
413 #define M_FW_FILTER_WR_NOREPLY 0x1
414 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
415 #define G_FW_FILTER_WR_NOREPLY(x) \
416 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
417 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U)
418
419 #define S_FW_FILTER_WR_IQ 0
420 #define M_FW_FILTER_WR_IQ 0x3ff
421 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
422 #define G_FW_FILTER_WR_IQ(x) \
423 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
424
425 #define S_FW_FILTER_WR_DEL_FILTER 31
426 #define M_FW_FILTER_WR_DEL_FILTER 0x1
427 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
428 #define G_FW_FILTER_WR_DEL_FILTER(x) \
429 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
430 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
431
432 #define S_FW_FILTER2_WR_DROP_ENCAP 30
433 #define M_FW_FILTER2_WR_DROP_ENCAP 0x1
434 #define V_FW_FILTER2_WR_DROP_ENCAP(x) ((x) << S_FW_FILTER2_WR_DROP_ENCAP)
435 #define G_FW_FILTER2_WR_DROP_ENCAP(x) \
436 (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP)
437 #define F_FW_FILTER2_WR_DROP_ENCAP V_FW_FILTER2_WR_DROP_ENCAP(1U)
438
439 #define S_FW_FILTER2_WR_TX_LOOP 29
440 #define M_FW_FILTER2_WR_TX_LOOP 0x1
441 #define V_FW_FILTER2_WR_TX_LOOP(x) ((x) << S_FW_FILTER2_WR_TX_LOOP)
442 #define G_FW_FILTER2_WR_TX_LOOP(x) \
443 (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP)
444 #define F_FW_FILTER2_WR_TX_LOOP V_FW_FILTER2_WR_TX_LOOP(1U)
445
446 #define S_FW_FILTER_WR_RPTTID 25
447 #define M_FW_FILTER_WR_RPTTID 0x1
448 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
449 #define G_FW_FILTER_WR_RPTTID(x) \
450 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
451 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U)
452
453 #define S_FW_FILTER_WR_DROP 24
454 #define M_FW_FILTER_WR_DROP 0x1
455 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
456 #define G_FW_FILTER_WR_DROP(x) \
457 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
458 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U)
459
460 #define S_FW_FILTER_WR_DIRSTEER 23
461 #define M_FW_FILTER_WR_DIRSTEER 0x1
462 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
463 #define G_FW_FILTER_WR_DIRSTEER(x) \
464 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
465 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U)
466
467 #define S_FW_FILTER_WR_MASKHASH 22
468 #define M_FW_FILTER_WR_MASKHASH 0x1
469 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
470 #define G_FW_FILTER_WR_MASKHASH(x) \
471 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
472 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U)
473
474 #define S_FW_FILTER_WR_DIRSTEERHASH 21
475 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1
476 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
477 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \
478 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
479 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U)
480
481 #define S_FW_FILTER_WR_LPBK 20
482 #define M_FW_FILTER_WR_LPBK 0x1
483 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
484 #define G_FW_FILTER_WR_LPBK(x) \
485 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
486 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U)
487
488 #define S_FW_FILTER_WR_DMAC 19
489 #define M_FW_FILTER_WR_DMAC 0x1
490 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
491 #define G_FW_FILTER_WR_DMAC(x) \
492 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
493 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U)
494
495 #define S_FW_FILTER_WR_SMAC 18
496 #define M_FW_FILTER_WR_SMAC 0x1
497 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC)
498 #define G_FW_FILTER_WR_SMAC(x) \
499 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
500 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U)
501
502 #define S_FW_FILTER_WR_INSVLAN 17
503 #define M_FW_FILTER_WR_INSVLAN 0x1
504 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
505 #define G_FW_FILTER_WR_INSVLAN(x) \
506 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
507 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U)
508
509 #define S_FW_FILTER_WR_RMVLAN 16
510 #define M_FW_FILTER_WR_RMVLAN 0x1
511 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
512 #define G_FW_FILTER_WR_RMVLAN(x) \
513 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
514 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U)
515
516 #define S_FW_FILTER_WR_HITCNTS 15
517 #define M_FW_FILTER_WR_HITCNTS 0x1
518 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
519 #define G_FW_FILTER_WR_HITCNTS(x) \
520 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
521 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U)
522
523 #define S_FW_FILTER_WR_TXCHAN 13
524 #define M_FW_FILTER_WR_TXCHAN 0x3
525 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
526 #define G_FW_FILTER_WR_TXCHAN(x) \
527 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
528
529 #define S_FW_FILTER_WR_PRIO 12
530 #define M_FW_FILTER_WR_PRIO 0x1
531 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
532 #define G_FW_FILTER_WR_PRIO(x) \
533 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
534 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U)
535
536 #define S_FW_FILTER_WR_L2TIX 0
537 #define M_FW_FILTER_WR_L2TIX 0xfff
538 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
539 #define G_FW_FILTER_WR_L2TIX(x) \
540 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
541
542 #define S_FW_FILTER_WR_FRAG 7
543 #define M_FW_FILTER_WR_FRAG 0x1
544 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
545 #define G_FW_FILTER_WR_FRAG(x) \
546 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
547 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U)
548
549 #define S_FW_FILTER_WR_FRAGM 6
550 #define M_FW_FILTER_WR_FRAGM 0x1
551 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
552 #define G_FW_FILTER_WR_FRAGM(x) \
553 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
554 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U)
555
556 #define S_FW_FILTER_WR_IVLAN_VLD 5
557 #define M_FW_FILTER_WR_IVLAN_VLD 0x1
558 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
559 #define G_FW_FILTER_WR_IVLAN_VLD(x) \
560 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
561 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U)
562
563 #define S_FW_FILTER_WR_OVLAN_VLD 4
564 #define M_FW_FILTER_WR_OVLAN_VLD 0x1
565 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
566 #define G_FW_FILTER_WR_OVLAN_VLD(x) \
567 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
568 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U)
569
570 #define S_FW_FILTER_WR_IVLAN_VLDM 3
571 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1
572 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
573 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \
574 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
575 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U)
576
577 #define S_FW_FILTER_WR_OVLAN_VLDM 2
578 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1
579 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
580 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \
581 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
582 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U)
583
584 #define S_FW_FILTER_WR_RX_CHAN 15
585 #define M_FW_FILTER_WR_RX_CHAN 0x1
586 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
587 #define G_FW_FILTER_WR_RX_CHAN(x) \
588 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
589 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U)
590
591 #define S_FW_FILTER_WR_RX_RPL_IQ 0
592 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff
593 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
594 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \
595 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
596
597 #define S_FW_FILTER2_WR_FILTER_TYPE 1
598 #define M_FW_FILTER2_WR_FILTER_TYPE 0x1
599 #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE)
600 #define G_FW_FILTER2_WR_FILTER_TYPE(x) \
601 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE)
602 #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U)
603
604 #define S_FW_FILTER2_WR_SWAPMAC 0
605 #define M_FW_FILTER2_WR_SWAPMAC 0x1
606 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC)
607 #define G_FW_FILTER2_WR_SWAPMAC(x) \
608 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC)
609 #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U)
610
611 #define S_FW_FILTER2_WR_NATMODE 5
612 #define M_FW_FILTER2_WR_NATMODE 0x7
613 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE)
614 #define G_FW_FILTER2_WR_NATMODE(x) \
615 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE)
616
617 #define S_FW_FILTER2_WR_NATFLAGCHECK 4
618 #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1
619 #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK)
620 #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \
621 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK)
622 #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U)
623
624 #define S_FW_FILTER2_WR_ULP_TYPE 0
625 #define M_FW_FILTER2_WR_ULP_TYPE 0xf
626 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE)
627 #define G_FW_FILTER2_WR_ULP_TYPE(x) \
628 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE)
629
630 #define S_FW_FILTER_WR_MACI 23
631 #define M_FW_FILTER_WR_MACI 0x1ff
632 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
633 #define G_FW_FILTER_WR_MACI(x) \
634 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
635
636 #define S_FW_FILTER_WR_MACIM 14
637 #define M_FW_FILTER_WR_MACIM 0x1ff
638 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
639 #define G_FW_FILTER_WR_MACIM(x) \
640 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
641
642 #define S_FW_FILTER_WR_FCOE 13
643 #define M_FW_FILTER_WR_FCOE 0x1
644 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
645 #define G_FW_FILTER_WR_FCOE(x) \
646 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
647 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U)
648
649 #define S_FW_FILTER_WR_FCOEM 12
650 #define M_FW_FILTER_WR_FCOEM 0x1
651 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
652 #define G_FW_FILTER_WR_FCOEM(x) \
653 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
654 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U)
655
656 #define S_FW_FILTER_WR_PORT 9
657 #define M_FW_FILTER_WR_PORT 0x7
658 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
659 #define G_FW_FILTER_WR_PORT(x) \
660 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
661
662 #define S_FW_FILTER_WR_PORTM 6
663 #define M_FW_FILTER_WR_PORTM 0x7
664 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
665 #define G_FW_FILTER_WR_PORTM(x) \
666 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
667
668 #define S_FW_FILTER_WR_MATCHTYPE 3
669 #define M_FW_FILTER_WR_MATCHTYPE 0x7
670 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
671 #define G_FW_FILTER_WR_MATCHTYPE(x) \
672 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
673
674 #define S_FW_FILTER_WR_MATCHTYPEM 0
675 #define M_FW_FILTER_WR_MATCHTYPEM 0x7
676 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
677 #define G_FW_FILTER_WR_MATCHTYPEM(x) \
678 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
679
680 struct fw_ulptx_wr {
681 __be32 op_to_compl;
682 __be32 flowid_len16;
683 __u64 cookie;
684 };
685
686 /* flag for packet type - control packet (0), data packet (1)
687 */
688 #define S_FW_ULPTX_WR_DATA 28
689 #define M_FW_ULPTX_WR_DATA 0x1
690 #define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA)
691 #define G_FW_ULPTX_WR_DATA(x) \
692 (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA)
693 #define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U)
694
695 struct fw_tp_wr {
696 __be32 op_to_immdlen;
697 __be32 flowid_len16;
698 __u64 cookie;
699 };
700
701 struct fw_eth_tx_pkt_wr {
702 __be32 op_immdlen;
703 __be32 equiq_to_len16;
704 __be64 r3;
705 };
706
707 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
708 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
709 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
710 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
711 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
712
713 struct fw_eth_tx_pkt2_wr {
714 __be32 op_immdlen;
715 __be32 equiq_to_len16;
716 __be32 r3;
717 __be32 L4ChkDisable_to_IpHdrLen;
718 };
719
720 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0
721 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff
722 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
723 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \
724 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)
725
726 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31
727 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1
728 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \
729 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
730 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \
731 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
732 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
733 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \
734 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)
735
736 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30
737 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1
738 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \
739 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
740 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \
741 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
742 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
743 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \
744 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)
745
746 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28
747 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1
748 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
749 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \
750 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)
751 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U)
752
753 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12
754 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff
755 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)
756 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \
757 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)
758
759 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8
760 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf
761 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)
762 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \
763 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)
764
765 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0
766 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff
767 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)
768 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \
769 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)
770
771 struct fw_eth_tx_pkts_wr {
772 __be32 op_pkd;
773 __be32 equiq_to_len16;
774 __be32 r3;
775 __be16 plen;
776 __u8 npkt;
777 __u8 type;
778 };
779
780 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0
781 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff
782 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN)
783 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \
784 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN)
785
786 struct fw_eth_tx_pkt_ptp_wr {
787 __be32 op_immdlen;
788 __be32 equiq_to_len16;
789 __be64 r3;
790 };
791
792 enum fw_eth_tx_eo_type {
793 FW_ETH_TX_EO_TYPE_UDPSEG,
794 FW_ETH_TX_EO_TYPE_TCPSEG,
795 FW_ETH_TX_EO_TYPE_NVGRESEG,
796 FW_ETH_TX_EO_TYPE_VXLANSEG,
797 FW_ETH_TX_EO_TYPE_GENEVESEG,
798 };
799
800 struct fw_eth_tx_eo_wr {
801 __be32 op_immdlen;
802 __be32 equiq_to_len16;
803 __be64 r3;
804 union fw_eth_tx_eo {
805 struct fw_eth_tx_eo_udpseg {
806 __u8 type;
807 __u8 ethlen;
808 __be16 iplen;
809 __u8 udplen;
810 __u8 rtplen;
811 __be16 r4;
812 __be16 mss;
813 __be16 schedpktsize;
814 __be32 plen;
815 } udpseg;
816 struct fw_eth_tx_eo_tcpseg {
817 __u8 type;
818 __u8 ethlen;
819 __be16 iplen;
820 __u8 tcplen;
821 __u8 tsclk_tsoff;
822 __be16 r4;
823 __be16 mss;
824 __be16 r5;
825 __be32 plen;
826 } tcpseg;
827 struct fw_eth_tx_eo_nvgreseg {
828 __u8 type;
829 __u8 iphdroffout;
830 __be16 grehdroff;
831 __be16 iphdroffin;
832 __be16 tcphdroffin;
833 __be16 mss;
834 __be16 r4;
835 __be32 plen;
836 } nvgreseg;
837 struct fw_eth_tx_eo_vxlanseg {
838 __u8 type;
839 __u8 iphdroffout;
840 __be16 vxlanhdroff;
841 __be16 iphdroffin;
842 __be16 tcphdroffin;
843 __be16 mss;
844 __be16 r4;
845 __be32 plen;
846
847 } vxlanseg;
848 struct fw_eth_tx_eo_geneveseg {
849 __u8 type;
850 __u8 iphdroffout;
851 __be16 genevehdroff;
852 __be16 iphdroffin;
853 __be16 tcphdroffin;
854 __be16 mss;
855 __be16 r4;
856 __be32 plen;
857 } geneveseg;
858 } u;
859 };
860
861 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0
862 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff
863 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN)
864 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \
865 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN)
866
867 #define S_FW_ETH_TX_EO_WR_TSCLK 6
868 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3
869 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK)
870 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \
871 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK)
872
873 #define S_FW_ETH_TX_EO_WR_TSOFF 0
874 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f
875 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF)
876 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \
877 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF)
878
879 struct fw_eq_flush_wr {
880 __u8 opcode;
881 __u8 r1[3];
882 __be32 equiq_to_len16;
883 __be64 r3;
884 };
885
886 struct fw_ofld_connection_wr {
887 __be32 op_compl;
888 __be32 len16_pkd;
889 __u64 cookie;
890 __be64 r2;
891 __be64 r3;
892 struct fw_ofld_connection_le {
893 __be32 version_cpl;
894 __be32 filter;
895 __be32 r1;
896 __be16 lport;
897 __be16 pport;
898 union fw_ofld_connection_leip {
899 struct fw_ofld_connection_le_ipv4 {
900 __be32 pip;
901 __be32 lip;
902 __be64 r0;
903 __be64 r1;
904 __be64 r2;
905 } ipv4;
906 struct fw_ofld_connection_le_ipv6 {
907 __be64 pip_hi;
908 __be64 pip_lo;
909 __be64 lip_hi;
910 __be64 lip_lo;
911 } ipv6;
912 } u;
913 } le;
914 struct fw_ofld_connection_tcb {
915 __be32 t_state_to_astid;
916 __be16 cplrxdataack_cplpassacceptrpl;
917 __be16 rcv_adv;
918 __be32 rcv_nxt;
919 __be32 tx_max;
920 __be64 opt0;
921 __be32 opt2;
922 __be32 r1;
923 __be64 r2;
924 __be64 r3;
925 } tcb;
926 };
927
928 #define S_FW_OFLD_CONNECTION_WR_VERSION 31
929 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1
930 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \
931 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
932 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \
933 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
934 M_FW_OFLD_CONNECTION_WR_VERSION)
935 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U)
936
937 #define S_FW_OFLD_CONNECTION_WR_CPL 30
938 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1
939 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL)
940 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \
941 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
942 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U)
943
944 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28
945 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf
946 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \
947 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
948 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \
949 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
950 M_FW_OFLD_CONNECTION_WR_T_STATE)
951
952 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24
953 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf
954 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
955 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
956 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
957 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
958 M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
959
960 #define S_FW_OFLD_CONNECTION_WR_ASTID 0
961 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff
962 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \
963 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
964 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \
965 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
966
967 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15
968 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1
969 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
970 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
971 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
972 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
973 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
974 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \
975 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
976
977 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14
978 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1
979 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
980 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
981 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
982 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
983 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
984 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \
985 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
986
987 enum fw_flowc_mnem_tcpstate {
988 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */
989 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */
990 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */
991 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
992 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
993 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
994 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and
995 * will resend FIN - equiv ESTAB
996 */
997 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and
998 * will resend FIN but have
999 * received FIN
1000 */
1001 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and
1002 * will resend FIN but have
1003 * received FIN
1004 */
1005 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK,
1006 * waiting for FIN
1007 */
1008 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
1009 };
1010
1011 enum fw_flowc_mnem_eostate {
1012 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */
1013 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */
1014 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending
1015 * outstanding payload
1016 */
1017 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after
1018 * discarding outstanding payload
1019 */
1020 };
1021
1022 enum fw_flowc_mnem {
1023 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */
1024 FW_FLOWC_MNEM_CH = 1,
1025 FW_FLOWC_MNEM_PORT = 2,
1026 FW_FLOWC_MNEM_IQID = 3,
1027 FW_FLOWC_MNEM_SNDNXT = 4,
1028 FW_FLOWC_MNEM_RCVNXT = 5,
1029 FW_FLOWC_MNEM_SNDBUF = 6,
1030 FW_FLOWC_MNEM_MSS = 7,
1031 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8,
1032 FW_FLOWC_MNEM_TCPSTATE = 9,
1033 FW_FLOWC_MNEM_EOSTATE = 10,
1034 FW_FLOWC_MNEM_SCHEDCLASS = 11,
1035 FW_FLOWC_MNEM_DCBPRIO = 12,
1036 FW_FLOWC_MNEM_SND_SCALE = 13,
1037 FW_FLOWC_MNEM_RCV_SCALE = 14,
1038 FW_FLOWC_MNEM_ULP_MODE = 15,
1039 FW_FLOWC_MNEM_MAX = 16,
1040 };
1041
1042 struct fw_flowc_mnemval {
1043 __u8 mnemonic;
1044 __u8 r4[3];
1045 __be32 val;
1046 };
1047
1048 struct fw_flowc_wr {
1049 __be32 op_to_nparams;
1050 __be32 flowid_len16;
1051 #ifndef C99_NOT_SUPPORTED
1052 struct fw_flowc_mnemval mnemval[0];
1053 #endif
1054 };
1055
1056 #define S_FW_FLOWC_WR_NPARAMS 0
1057 #define M_FW_FLOWC_WR_NPARAMS 0xff
1058 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS)
1059 #define G_FW_FLOWC_WR_NPARAMS(x) \
1060 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)
1061
1062 struct fw_ofld_tx_data_wr {
1063 __be32 op_to_immdlen;
1064 __be32 flowid_len16;
1065 __be32 plen;
1066 __be32 lsodisable_to_flags;
1067 };
1068
1069 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31
1070 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1
1071 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \
1072 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE)
1073 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \
1074 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \
1075 M_FW_OFLD_TX_DATA_WR_LSODISABLE)
1076 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U)
1077
1078 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30
1079 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1
1080 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \
1081 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1082 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \
1083 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1084 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U)
1085
1086 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29
1087 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1
1088 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \
1089 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
1090 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \
1091 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \
1092 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
1093 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \
1094 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U)
1095
1096 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0
1097 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff
1098 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS)
1099 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \
1100 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS)
1101
1102
1103 /* Use fw_ofld_tx_data_wr structure */
1104 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10
1105 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff
1106 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \
1107 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1108 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \
1109 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1110
1111 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9
1112 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1
1113 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \
1114 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
1115 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \
1116 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \
1117 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
1118 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \
1119 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U)
1120
1121 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8
1122 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1
1123 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \
1124 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1125 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \
1126 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \
1127 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1128 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \
1129 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U)
1130
1131 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7
1132 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1
1133 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \
1134 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1135 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \
1136 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \
1137 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1138 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \
1139 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U)
1140
1141 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6
1142 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1
1143 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \
1144 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1145 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \
1146 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \
1147 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1148 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \
1149 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U)
1150
1151 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0
1152 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f
1153 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \
1154 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1155 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \
1156 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1157
1158 struct fw_cmd_wr {
1159 __be32 op_dma;
1160 __be32 len16_pkd;
1161 __be64 cookie_daddr;
1162 };
1163
1164 #define S_FW_CMD_WR_DMA 17
1165 #define M_FW_CMD_WR_DMA 0x1
1166 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA)
1167 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)
1168 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U)
1169
1170 struct fw_eth_tx_pkt_vm_wr {
1171 __be32 op_immdlen;
1172 __be32 equiq_to_len16;
1173 __be32 r3[2];
1174 __u8 ethmacdst[6];
1175 __u8 ethmacsrc[6];
1176 __be16 ethtype;
1177 __be16 vlantci;
1178 };
1179
1180 struct fw_eth_tx_pkts_vm_wr {
1181 __be32 op_pkd;
1182 __be32 equiq_to_len16;
1183 __be32 r3;
1184 __be16 plen;
1185 __u8 npkt;
1186 __u8 r4;
1187 __u8 ethmacdst[6];
1188 __u8 ethmacsrc[6];
1189 __be16 ethtype;
1190 __be16 vlantci;
1191 };
1192
1193 /******************************************************************************
1194 * R I W O R K R E Q U E S T s
1195 **************************************/
1196
1197 enum fw_ri_wr_opcode {
1198 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */
1199 FW_RI_READ_REQ = 0x1,
1200 FW_RI_READ_RESP = 0x2,
1201 FW_RI_SEND = 0x3,
1202 FW_RI_SEND_WITH_INV = 0x4,
1203 FW_RI_SEND_WITH_SE = 0x5,
1204 FW_RI_SEND_WITH_SE_INV = 0x6,
1205 FW_RI_TERMINATE = 0x7,
1206 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */
1207 FW_RI_BIND_MW = 0x9,
1208 FW_RI_FAST_REGISTER = 0xa,
1209 FW_RI_LOCAL_INV = 0xb,
1210 FW_RI_QP_MODIFY = 0xc,
1211 FW_RI_BYPASS = 0xd,
1212 FW_RI_RECEIVE = 0xe,
1213 #if 0
1214 FW_RI_SEND_IMMEDIATE = 0x8,
1215 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9,
1216 FW_RI_ATOMIC_REQUEST = 0xa,
1217 FW_RI_ATOMIC_RESPONSE = 0xb,
1218
1219 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */
1220 FW_RI_FAST_REGISTER = 0xd,
1221 FW_RI_LOCAL_INV = 0xe,
1222 #endif
1223 FW_RI_SGE_EC_CR_RETURN = 0xf,
1224 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT,
1225 };
1226
1227 enum fw_ri_wr_flags {
1228 FW_RI_COMPLETION_FLAG = 0x01,
1229 FW_RI_NOTIFICATION_FLAG = 0x02,
1230 FW_RI_SOLICITED_EVENT_FLAG = 0x04,
1231 FW_RI_READ_FENCE_FLAG = 0x08,
1232 FW_RI_LOCAL_FENCE_FLAG = 0x10,
1233 FW_RI_RDMA_READ_INVALIDATE = 0x20,
1234 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40
1235 };
1236
1237 enum fw_ri_mpa_attrs {
1238 FW_RI_MPA_RX_MARKER_ENABLE = 0x01,
1239 FW_RI_MPA_TX_MARKER_ENABLE = 0x02,
1240 FW_RI_MPA_CRC_ENABLE = 0x04,
1241 FW_RI_MPA_IETF_ENABLE = 0x08
1242 };
1243
1244 enum fw_ri_qp_caps {
1245 FW_RI_QP_RDMA_READ_ENABLE = 0x01,
1246 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02,
1247 FW_RI_QP_BIND_ENABLE = 0x04,
1248 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08,
1249 FW_RI_QP_STAG0_ENABLE = 0x10,
1250 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80,
1251 };
1252
1253 enum fw_ri_addr_type {
1254 FW_RI_ZERO_BASED_TO = 0x00,
1255 FW_RI_VA_BASED_TO = 0x01
1256 };
1257
1258 enum fw_ri_mem_perms {
1259 FW_RI_MEM_ACCESS_REM_WRITE = 0x01,
1260 FW_RI_MEM_ACCESS_REM_READ = 0x02,
1261 FW_RI_MEM_ACCESS_REM = 0x03,
1262 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04,
1263 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08,
1264 FW_RI_MEM_ACCESS_LOCAL = 0x0C
1265 };
1266
1267 enum fw_ri_stag_type {
1268 FW_RI_STAG_NSMR = 0x00,
1269 FW_RI_STAG_SMR = 0x01,
1270 FW_RI_STAG_MW = 0x02,
1271 FW_RI_STAG_MW_RELAXED = 0x03
1272 };
1273
1274 enum fw_ri_data_op {
1275 FW_RI_DATA_IMMD = 0x81,
1276 FW_RI_DATA_DSGL = 0x82,
1277 FW_RI_DATA_ISGL = 0x83
1278 };
1279
1280 enum fw_ri_sgl_depth {
1281 FW_RI_SGL_DEPTH_MAX_SQ = 16,
1282 FW_RI_SGL_DEPTH_MAX_RQ = 4
1283 };
1284
1285 enum fw_ri_cqe_err {
1286 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */
1287 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */
1288 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */
1289 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */
1290 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */
1291 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */
1292 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */
1293 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */
1294 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */
1295 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */
1296 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */
1297 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */
1298 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */
1299 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */
1300 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */
1301 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */
1302 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */
1303 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */
1304 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */
1305 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */
1306 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */
1307 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */
1308 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */
1309 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */
1310 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */
1311 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */
1312 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */
1313 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */
1314
1315 };
1316
1317 struct fw_ri_dsge_pair {
1318 __be32 len[2];
1319 __be64 addr[2];
1320 };
1321
1322 struct fw_ri_dsgl {
1323 __u8 op;
1324 __u8 r1;
1325 __be16 nsge;
1326 __be32 len0;
1327 __be64 addr0;
1328 #ifndef C99_NOT_SUPPORTED
1329 struct fw_ri_dsge_pair sge[0];
1330 #endif
1331 };
1332
1333 struct fw_ri_sge {
1334 __be32 stag;
1335 __be32 len;
1336 __be64 to;
1337 };
1338
1339 struct fw_ri_isgl {
1340 __u8 op;
1341 __u8 r1;
1342 __be16 nsge;
1343 __be32 r2;
1344 #ifndef C99_NOT_SUPPORTED
1345 struct fw_ri_sge sge[0];
1346 #endif
1347 };
1348
1349 struct fw_ri_immd {
1350 __u8 op;
1351 __u8 r1;
1352 __be16 r2;
1353 __be32 immdlen;
1354 #ifndef C99_NOT_SUPPORTED
1355 __u8 data[0];
1356 #endif
1357 };
1358
1359 struct fw_ri_tpte {
1360 __be32 valid_to_pdid;
1361 __be32 locread_to_qpid;
1362 __be32 nosnoop_pbladdr;
1363 __be32 len_lo;
1364 __be32 va_hi;
1365 __be32 va_lo_fbo;
1366 __be32 dca_mwbcnt_pstag;
1367 __be32 len_hi;
1368 };
1369
1370 #define S_FW_RI_TPTE_VALID 31
1371 #define M_FW_RI_TPTE_VALID 0x1
1372 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID)
1373 #define G_FW_RI_TPTE_VALID(x) \
1374 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
1375 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U)
1376
1377 #define S_FW_RI_TPTE_STAGKEY 23
1378 #define M_FW_RI_TPTE_STAGKEY 0xff
1379 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY)
1380 #define G_FW_RI_TPTE_STAGKEY(x) \
1381 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
1382
1383 #define S_FW_RI_TPTE_STAGSTATE 22
1384 #define M_FW_RI_TPTE_STAGSTATE 0x1
1385 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE)
1386 #define G_FW_RI_TPTE_STAGSTATE(x) \
1387 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
1388 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U)
1389
1390 #define S_FW_RI_TPTE_STAGTYPE 20
1391 #define M_FW_RI_TPTE_STAGTYPE 0x3
1392 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE)
1393 #define G_FW_RI_TPTE_STAGTYPE(x) \
1394 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
1395
1396 #define S_FW_RI_TPTE_PDID 0
1397 #define M_FW_RI_TPTE_PDID 0xfffff
1398 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID)
1399 #define G_FW_RI_TPTE_PDID(x) \
1400 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
1401
1402 #define S_FW_RI_TPTE_PERM 28
1403 #define M_FW_RI_TPTE_PERM 0xf
1404 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM)
1405 #define G_FW_RI_TPTE_PERM(x) \
1406 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
1407
1408 #define S_FW_RI_TPTE_REMINVDIS 27
1409 #define M_FW_RI_TPTE_REMINVDIS 0x1
1410 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS)
1411 #define G_FW_RI_TPTE_REMINVDIS(x) \
1412 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
1413 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U)
1414
1415 #define S_FW_RI_TPTE_ADDRTYPE 26
1416 #define M_FW_RI_TPTE_ADDRTYPE 1
1417 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE)
1418 #define G_FW_RI_TPTE_ADDRTYPE(x) \
1419 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
1420 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U)
1421
1422 #define S_FW_RI_TPTE_MWBINDEN 25
1423 #define M_FW_RI_TPTE_MWBINDEN 0x1
1424 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN)
1425 #define G_FW_RI_TPTE_MWBINDEN(x) \
1426 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
1427 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U)
1428
1429 #define S_FW_RI_TPTE_PS 20
1430 #define M_FW_RI_TPTE_PS 0x1f
1431 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS)
1432 #define G_FW_RI_TPTE_PS(x) \
1433 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
1434
1435 #define S_FW_RI_TPTE_QPID 0
1436 #define M_FW_RI_TPTE_QPID 0xfffff
1437 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID)
1438 #define G_FW_RI_TPTE_QPID(x) \
1439 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
1440
1441 #define S_FW_RI_TPTE_NOSNOOP 31
1442 #define M_FW_RI_TPTE_NOSNOOP 0x1
1443 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP)
1444 #define G_FW_RI_TPTE_NOSNOOP(x) \
1445 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
1446 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U)
1447
1448 #define S_FW_RI_TPTE_PBLADDR 0
1449 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff
1450 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR)
1451 #define G_FW_RI_TPTE_PBLADDR(x) \
1452 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
1453
1454 #define S_FW_RI_TPTE_DCA 24
1455 #define M_FW_RI_TPTE_DCA 0x1f
1456 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA)
1457 #define G_FW_RI_TPTE_DCA(x) \
1458 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
1459
1460 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0
1461 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff
1462 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \
1463 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
1464 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \
1465 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
1466
1467 enum fw_ri_cqe_rxtx {
1468 FW_RI_CQE_RXTX_RX = 0x0,
1469 FW_RI_CQE_RXTX_TX = 0x1,
1470 };
1471
1472 struct fw_ri_cqe {
1473 union fw_ri_rxtx {
1474 struct fw_ri_scqe {
1475 __be32 qpid_n_stat_rxtx_type;
1476 __be32 plen;
1477 __be32 stag;
1478 __be32 wrid;
1479 } scqe;
1480 struct fw_ri_rcqe {
1481 __be32 qpid_n_stat_rxtx_type;
1482 __be32 plen;
1483 __be32 stag;
1484 __be32 msn;
1485 } rcqe;
1486 struct fw_ri_rcqe_imm {
1487 __be32 qpid_n_stat_rxtx_type;
1488 __be32 plen;
1489 __be32 mo;
1490 __be32 msn;
1491 __u64 imm_data;
1492 } imm_data_rcqe;
1493 } u;
1494 };
1495
1496 #define S_FW_RI_CQE_QPID 12
1497 #define M_FW_RI_CQE_QPID 0xfffff
1498 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID)
1499 #define G_FW_RI_CQE_QPID(x) \
1500 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID)
1501
1502 #define S_FW_RI_CQE_NOTIFY 10
1503 #define M_FW_RI_CQE_NOTIFY 0x1
1504 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)
1505 #define G_FW_RI_CQE_NOTIFY(x) \
1506 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY)
1507
1508 #define S_FW_RI_CQE_STATUS 5
1509 #define M_FW_RI_CQE_STATUS 0x1f
1510 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)
1511 #define G_FW_RI_CQE_STATUS(x) \
1512 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS)
1513
1514
1515 #define S_FW_RI_CQE_RXTX 4
1516 #define M_FW_RI_CQE_RXTX 0x1
1517 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX)
1518 #define G_FW_RI_CQE_RXTX(x) \
1519 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX)
1520
1521 #define S_FW_RI_CQE_TYPE 0
1522 #define M_FW_RI_CQE_TYPE 0xf
1523 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE)
1524 #define G_FW_RI_CQE_TYPE(x) \
1525 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE)
1526
1527 enum fw_ri_res_type {
1528 FW_RI_RES_TYPE_SQ,
1529 FW_RI_RES_TYPE_RQ,
1530 FW_RI_RES_TYPE_CQ,
1531 FW_RI_RES_TYPE_SRQ,
1532 };
1533
1534 enum fw_ri_res_op {
1535 FW_RI_RES_OP_WRITE,
1536 FW_RI_RES_OP_RESET,
1537 };
1538
1539 struct fw_ri_res {
1540 union fw_ri_restype {
1541 struct fw_ri_res_sqrq {
1542 __u8 restype;
1543 __u8 op;
1544 __be16 r3;
1545 __be32 eqid;
1546 __be32 r4[2];
1547 __be32 fetchszm_to_iqid;
1548 __be32 dcaen_to_eqsize;
1549 __be64 eqaddr;
1550 } sqrq;
1551 struct fw_ri_res_cq {
1552 __u8 restype;
1553 __u8 op;
1554 __be16 r3;
1555 __be32 iqid;
1556 __be32 r4[2];
1557 __be32 iqandst_to_iqandstindex;
1558 __be16 iqdroprss_to_iqesize;
1559 __be16 iqsize;
1560 __be64 iqaddr;
1561 __be32 iqns_iqro;
1562 __be32 r6_lo;
1563 __be64 r7;
1564 } cq;
1565 struct fw_ri_res_srq {
1566 __u8 restype;
1567 __u8 op;
1568 __be16 r3;
1569 __be32 eqid;
1570 __be32 r4[2];
1571 __be32 fetchszm_to_iqid;
1572 __be32 dcaen_to_eqsize;
1573 __be64 eqaddr;
1574 __be32 srqid;
1575 __be32 pdid;
1576 __be32 hwsrqsize;
1577 __be32 hwsrqaddr;
1578 } srq;
1579 } u;
1580 };
1581
1582 struct fw_ri_res_wr {
1583 __be32 op_nres;
1584 __be32 len16_pkd;
1585 __u64 cookie;
1586 #ifndef C99_NOT_SUPPORTED
1587 struct fw_ri_res res[0];
1588 #endif
1589 };
1590
1591 #define S_FW_RI_RES_WR_VFN 8
1592 #define M_FW_RI_RES_WR_VFN 0xff
1593 #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN)
1594 #define G_FW_RI_RES_WR_VFN(x) \
1595 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN)
1596
1597 #define S_FW_RI_RES_WR_NRES 0
1598 #define M_FW_RI_RES_WR_NRES 0xff
1599 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES)
1600 #define G_FW_RI_RES_WR_NRES(x) \
1601 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
1602
1603 #define S_FW_RI_RES_WR_FETCHSZM 26
1604 #define M_FW_RI_RES_WR_FETCHSZM 0x1
1605 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM)
1606 #define G_FW_RI_RES_WR_FETCHSZM(x) \
1607 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
1608 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U)
1609
1610 #define S_FW_RI_RES_WR_STATUSPGNS 25
1611 #define M_FW_RI_RES_WR_STATUSPGNS 0x1
1612 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS)
1613 #define G_FW_RI_RES_WR_STATUSPGNS(x) \
1614 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
1615 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U)
1616
1617 #define S_FW_RI_RES_WR_STATUSPGRO 24
1618 #define M_FW_RI_RES_WR_STATUSPGRO 0x1
1619 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO)
1620 #define G_FW_RI_RES_WR_STATUSPGRO(x) \
1621 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
1622 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U)
1623
1624 #define S_FW_RI_RES_WR_FETCHNS 23
1625 #define M_FW_RI_RES_WR_FETCHNS 0x1
1626 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS)
1627 #define G_FW_RI_RES_WR_FETCHNS(x) \
1628 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
1629 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U)
1630
1631 #define S_FW_RI_RES_WR_FETCHRO 22
1632 #define M_FW_RI_RES_WR_FETCHRO 0x1
1633 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO)
1634 #define G_FW_RI_RES_WR_FETCHRO(x) \
1635 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
1636 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U)
1637
1638 #define S_FW_RI_RES_WR_HOSTFCMODE 20
1639 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3
1640 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE)
1641 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \
1642 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
1643
1644 #define S_FW_RI_RES_WR_CPRIO 19
1645 #define M_FW_RI_RES_WR_CPRIO 0x1
1646 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO)
1647 #define G_FW_RI_RES_WR_CPRIO(x) \
1648 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
1649 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U)
1650
1651 #define S_FW_RI_RES_WR_ONCHIP 18
1652 #define M_FW_RI_RES_WR_ONCHIP 0x1
1653 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP)
1654 #define G_FW_RI_RES_WR_ONCHIP(x) \
1655 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
1656 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U)
1657
1658 #define S_FW_RI_RES_WR_PCIECHN 16
1659 #define M_FW_RI_RES_WR_PCIECHN 0x3
1660 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN)
1661 #define G_FW_RI_RES_WR_PCIECHN(x) \
1662 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
1663
1664 #define S_FW_RI_RES_WR_IQID 0
1665 #define M_FW_RI_RES_WR_IQID 0xffff
1666 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID)
1667 #define G_FW_RI_RES_WR_IQID(x) \
1668 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
1669
1670 #define S_FW_RI_RES_WR_DCAEN 31
1671 #define M_FW_RI_RES_WR_DCAEN 0x1
1672 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN)
1673 #define G_FW_RI_RES_WR_DCAEN(x) \
1674 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
1675 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U)
1676
1677 #define S_FW_RI_RES_WR_DCACPU 26
1678 #define M_FW_RI_RES_WR_DCACPU 0x1f
1679 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU)
1680 #define G_FW_RI_RES_WR_DCACPU(x) \
1681 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
1682
1683 #define S_FW_RI_RES_WR_FBMIN 23
1684 #define M_FW_RI_RES_WR_FBMIN 0x7
1685 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN)
1686 #define G_FW_RI_RES_WR_FBMIN(x) \
1687 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
1688
1689 #define S_FW_RI_RES_WR_FBMAX 20
1690 #define M_FW_RI_RES_WR_FBMAX 0x7
1691 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX)
1692 #define G_FW_RI_RES_WR_FBMAX(x) \
1693 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
1694
1695 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19
1696 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1
1697 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
1698 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \
1699 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
1700 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
1701
1702 #define S_FW_RI_RES_WR_CIDXFTHRESH 16
1703 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7
1704 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
1705 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \
1706 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
1707
1708 #define S_FW_RI_RES_WR_EQSIZE 0
1709 #define M_FW_RI_RES_WR_EQSIZE 0xffff
1710 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE)
1711 #define G_FW_RI_RES_WR_EQSIZE(x) \
1712 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
1713
1714 #define S_FW_RI_RES_WR_IQANDST 15
1715 #define M_FW_RI_RES_WR_IQANDST 0x1
1716 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST)
1717 #define G_FW_RI_RES_WR_IQANDST(x) \
1718 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
1719 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U)
1720
1721 #define S_FW_RI_RES_WR_IQANUS 14
1722 #define M_FW_RI_RES_WR_IQANUS 0x1
1723 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS)
1724 #define G_FW_RI_RES_WR_IQANUS(x) \
1725 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
1726 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U)
1727
1728 #define S_FW_RI_RES_WR_IQANUD 12
1729 #define M_FW_RI_RES_WR_IQANUD 0x3
1730 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD)
1731 #define G_FW_RI_RES_WR_IQANUD(x) \
1732 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
1733
1734 #define S_FW_RI_RES_WR_IQANDSTINDEX 0
1735 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff
1736 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
1737 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \
1738 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
1739
1740 #define S_FW_RI_RES_WR_IQDROPRSS 15
1741 #define M_FW_RI_RES_WR_IQDROPRSS 0x1
1742 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS)
1743 #define G_FW_RI_RES_WR_IQDROPRSS(x) \
1744 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
1745 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U)
1746
1747 #define S_FW_RI_RES_WR_IQGTSMODE 14
1748 #define M_FW_RI_RES_WR_IQGTSMODE 0x1
1749 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE)
1750 #define G_FW_RI_RES_WR_IQGTSMODE(x) \
1751 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
1752 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U)
1753
1754 #define S_FW_RI_RES_WR_IQPCIECH 12
1755 #define M_FW_RI_RES_WR_IQPCIECH 0x3
1756 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH)
1757 #define G_FW_RI_RES_WR_IQPCIECH(x) \
1758 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
1759
1760 #define S_FW_RI_RES_WR_IQDCAEN 11
1761 #define M_FW_RI_RES_WR_IQDCAEN 0x1
1762 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN)
1763 #define G_FW_RI_RES_WR_IQDCAEN(x) \
1764 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
1765 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U)
1766
1767 #define S_FW_RI_RES_WR_IQDCACPU 6
1768 #define M_FW_RI_RES_WR_IQDCACPU 0x1f
1769 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU)
1770 #define G_FW_RI_RES_WR_IQDCACPU(x) \
1771 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
1772
1773 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4
1774 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3
1775 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
1776 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
1777 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
1778 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
1779
1780 #define S_FW_RI_RES_WR_IQO 3
1781 #define M_FW_RI_RES_WR_IQO 0x1
1782 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO)
1783 #define G_FW_RI_RES_WR_IQO(x) \
1784 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
1785 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U)
1786
1787 #define S_FW_RI_RES_WR_IQCPRIO 2
1788 #define M_FW_RI_RES_WR_IQCPRIO 0x1
1789 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO)
1790 #define G_FW_RI_RES_WR_IQCPRIO(x) \
1791 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
1792 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U)
1793
1794 #define S_FW_RI_RES_WR_IQESIZE 0
1795 #define M_FW_RI_RES_WR_IQESIZE 0x3
1796 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE)
1797 #define G_FW_RI_RES_WR_IQESIZE(x) \
1798 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
1799
1800 #define S_FW_RI_RES_WR_IQNS 31
1801 #define M_FW_RI_RES_WR_IQNS 0x1
1802 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS)
1803 #define G_FW_RI_RES_WR_IQNS(x) \
1804 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
1805 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U)
1806
1807 #define S_FW_RI_RES_WR_IQRO 30
1808 #define M_FW_RI_RES_WR_IQRO 0x1
1809 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO)
1810 #define G_FW_RI_RES_WR_IQRO(x) \
1811 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
1812 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U)
1813
1814 struct fw_ri_rdma_write_wr {
1815 __u8 opcode;
1816 __u8 flags;
1817 __u16 wrid;
1818 __u8 r1[3];
1819 __u8 len16;
1820 __u64 immd_data;
1821 __be32 plen;
1822 __be32 stag_sink;
1823 __be64 to_sink;
1824 #ifndef C99_NOT_SUPPORTED
1825 union {
1826 struct fw_ri_immd immd_src[0];
1827 struct fw_ri_isgl isgl_src[0];
1828 } u;
1829 #endif
1830 };
1831
1832 struct fw_ri_send_wr {
1833 __u8 opcode;
1834 __u8 flags;
1835 __u16 wrid;
1836 __u8 r1[3];
1837 __u8 len16;
1838 __be32 sendop_pkd;
1839 __be32 stag_inv;
1840 __be32 plen;
1841 __be32 r3;
1842 __be64 r4;
1843 #ifndef C99_NOT_SUPPORTED
1844 union {
1845 struct fw_ri_immd immd_src[0];
1846 struct fw_ri_isgl isgl_src[0];
1847 } u;
1848 #endif
1849 };
1850
1851 #define S_FW_RI_SEND_WR_SENDOP 0
1852 #define M_FW_RI_SEND_WR_SENDOP 0xf
1853 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP)
1854 #define G_FW_RI_SEND_WR_SENDOP(x) \
1855 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
1856
1857 struct fw_ri_rdma_write_cmpl_wr {
1858 __u8 opcode;
1859 __u8 flags;
1860 __u16 wrid;
1861 __u8 r1[3];
1862 __u8 len16;
1863 __u8 r2;
1864 __u8 flags_send;
1865 __u16 wrid_send;
1866 __be32 stag_inv;
1867 __be32 plen;
1868 __be32 stag_sink;
1869 __be64 to_sink;
1870 union fw_ri_cmpl {
1871 struct fw_ri_immd_cmpl {
1872 __u8 op;
1873 __u8 r1[6];
1874 __u8 immdlen;
1875 __u8 data[16];
1876 } immd_src;
1877 struct fw_ri_isgl isgl_src;
1878 } u_cmpl;
1879 __be64 r3;
1880 #ifndef C99_NOT_SUPPORTED
1881 union fw_ri_write {
1882 struct fw_ri_immd immd_src[0];
1883 struct fw_ri_isgl isgl_src[0];
1884 } u;
1885 #endif
1886 };
1887
1888 struct fw_ri_rdma_read_wr {
1889 __u8 opcode;
1890 __u8 flags;
1891 __u16 wrid;
1892 __u8 r1[3];
1893 __u8 len16;
1894 __be64 r2;
1895 __be32 stag_sink;
1896 __be32 to_sink_hi;
1897 __be32 to_sink_lo;
1898 __be32 plen;
1899 __be32 stag_src;
1900 __be32 to_src_hi;
1901 __be32 to_src_lo;
1902 __be32 r5;
1903 };
1904
1905 struct fw_ri_recv_wr {
1906 __u8 opcode;
1907 __u8 r1;
1908 __u16 wrid;
1909 __u8 r2[3];
1910 __u8 len16;
1911 struct fw_ri_isgl isgl;
1912 };
1913
1914 struct fw_ri_bind_mw_wr {
1915 __u8 opcode;
1916 __u8 flags;
1917 __u16 wrid;
1918 __u8 r1[3];
1919 __u8 len16;
1920 __u8 qpbinde_to_dcacpu;
1921 __u8 pgsz_shift;
1922 __u8 addr_type;
1923 __u8 mem_perms;
1924 __be32 stag_mr;
1925 __be32 stag_mw;
1926 __be32 r3;
1927 __be64 len_mw;
1928 __be64 va_fbo;
1929 __be64 r4;
1930 };
1931
1932 #define S_FW_RI_BIND_MW_WR_QPBINDE 6
1933 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1
1934 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
1935 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \
1936 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
1937 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U)
1938
1939 #define S_FW_RI_BIND_MW_WR_NS 5
1940 #define M_FW_RI_BIND_MW_WR_NS 0x1
1941 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS)
1942 #define G_FW_RI_BIND_MW_WR_NS(x) \
1943 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
1944 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U)
1945
1946 #define S_FW_RI_BIND_MW_WR_DCACPU 0
1947 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f
1948 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU)
1949 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \
1950 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
1951
1952 struct fw_ri_fr_nsmr_wr {
1953 __u8 opcode;
1954 __u8 flags;
1955 __u16 wrid;
1956 __u8 r1[3];
1957 __u8 len16;
1958 __u8 qpbinde_to_dcacpu;
1959 __u8 pgsz_shift;
1960 __u8 addr_type;
1961 __u8 mem_perms;
1962 __be32 stag;
1963 __be32 len_hi;
1964 __be32 len_lo;
1965 __be32 va_hi;
1966 __be32 va_lo_fbo;
1967 };
1968
1969 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6
1970 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1
1971 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
1972 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \
1973 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
1974 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
1975
1976 #define S_FW_RI_FR_NSMR_WR_NS 5
1977 #define M_FW_RI_FR_NSMR_WR_NS 0x1
1978 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS)
1979 #define G_FW_RI_FR_NSMR_WR_NS(x) \
1980 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
1981 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U)
1982
1983 #define S_FW_RI_FR_NSMR_WR_DCACPU 0
1984 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f
1985 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
1986 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \
1987 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
1988
1989 struct fw_ri_fr_nsmr_tpte_wr {
1990 __u8 opcode;
1991 __u8 flags;
1992 __u16 wrid;
1993 __u8 r1[3];
1994 __u8 len16;
1995 __be32 r2;
1996 __be32 stag;
1997 struct fw_ri_tpte tpte;
1998 __be64 pbl[2];
1999 };
2000
2001 struct fw_ri_inv_lstag_wr {
2002 __u8 opcode;
2003 __u8 flags;
2004 __u16 wrid;
2005 __u8 r1[3];
2006 __u8 len16;
2007 __be32 r2;
2008 __be32 stag_inv;
2009 };
2010
2011 struct fw_ri_send_immediate_wr {
2012 __u8 opcode;
2013 __u8 flags;
2014 __u16 wrid;
2015 __u8 r1[3];
2016 __u8 len16;
2017 __be32 sendimmop_pkd;
2018 __be32 r3;
2019 __be32 plen;
2020 __be32 r4;
2021 __be64 r5;
2022 #ifndef C99_NOT_SUPPORTED
2023 struct fw_ri_immd immd_src[0];
2024 #endif
2025 };
2026
2027 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0
2028 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf
2029 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \
2030 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
2031 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \
2032 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
2033 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
2034
2035 enum fw_ri_atomic_op {
2036 FW_RI_ATOMIC_OP_FETCHADD,
2037 FW_RI_ATOMIC_OP_SWAP,
2038 FW_RI_ATOMIC_OP_CMDSWAP,
2039 };
2040
2041 struct fw_ri_atomic_wr {
2042 __u8 opcode;
2043 __u8 flags;
2044 __u16 wrid;
2045 __u8 r1[3];
2046 __u8 len16;
2047 __be32 atomicop_pkd;
2048 __be64 r3;
2049 __be32 aopcode_pkd;
2050 __be32 reqid;
2051 __be32 stag;
2052 __be32 to_hi;
2053 __be32 to_lo;
2054 __be32 addswap_data_hi;
2055 __be32 addswap_data_lo;
2056 __be32 addswap_mask_hi;
2057 __be32 addswap_mask_lo;
2058 __be32 compare_data_hi;
2059 __be32 compare_data_lo;
2060 __be32 compare_mask_hi;
2061 __be32 compare_mask_lo;
2062 __be32 r5;
2063 };
2064
2065 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0
2066 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf
2067 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)
2068 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \
2069 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)
2070
2071 #define S_FW_RI_ATOMIC_WR_AOPCODE 0
2072 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf
2073 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE)
2074 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \
2075 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)
2076
2077 enum fw_ri_type {
2078 FW_RI_TYPE_INIT,
2079 FW_RI_TYPE_FINI,
2080 FW_RI_TYPE_TERMINATE
2081 };
2082
2083 enum fw_ri_init_p2ptype {
2084 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE,
2085 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ,
2086 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND,
2087 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV,
2088 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE,
2089 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV,
2090 FW_RI_INIT_P2PTYPE_DISABLED = 0xf,
2091 };
2092
2093 enum fw_ri_init_rqeqid_srq {
2094 FW_RI_INIT_RQEQID_SRQ = 1 << 31,
2095 };
2096
2097 struct fw_ri_wr {
2098 __be32 op_compl;
2099 __be32 flowid_len16;
2100 __u64 cookie;
2101 union fw_ri {
2102 struct fw_ri_init {
2103 __u8 type;
2104 __u8 mpareqbit_p2ptype;
2105 __u8 r4[2];
2106 __u8 mpa_attrs;
2107 __u8 qp_caps;
2108 __be16 nrqe;
2109 __be32 pdid;
2110 __be32 qpid;
2111 __be32 sq_eqid;
2112 __be32 rq_eqid;
2113 __be32 scqid;
2114 __be32 rcqid;
2115 __be32 ord_max;
2116 __be32 ird_max;
2117 __be32 iss;
2118 __be32 irs;
2119 __be32 hwrqsize;
2120 __be32 hwrqaddr;
2121 __be64 r5;
2122 union fw_ri_init_p2p {
2123 struct fw_ri_rdma_write_wr write;
2124 struct fw_ri_rdma_read_wr read;
2125 struct fw_ri_send_wr send;
2126 } u;
2127 } init;
2128 struct fw_ri_fini {
2129 __u8 type;
2130 __u8 r3[7];
2131 __be64 r4;
2132 } fini;
2133 struct fw_ri_terminate {
2134 __u8 type;
2135 __u8 r3[3];
2136 __be32 immdlen;
2137 __u8 termmsg[40];
2138 } terminate;
2139 } u;
2140 };
2141
2142 #define S_FW_RI_WR_MPAREQBIT 7
2143 #define M_FW_RI_WR_MPAREQBIT 0x1
2144 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT)
2145 #define G_FW_RI_WR_MPAREQBIT(x) \
2146 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
2147 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U)
2148
2149 #define S_FW_RI_WR_0BRRBIT 6
2150 #define M_FW_RI_WR_0BRRBIT 0x1
2151 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT)
2152 #define G_FW_RI_WR_0BRRBIT(x) \
2153 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
2154 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U)
2155
2156 #define S_FW_RI_WR_P2PTYPE 0
2157 #define M_FW_RI_WR_P2PTYPE 0xf
2158 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE)
2159 #define G_FW_RI_WR_P2PTYPE(x) \
2160 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
2161
2162 /******************************************************************************
2163 * F O i S C S I W O R K R E Q U E S T s
2164 *********************************************/
2165
2166 #define FW_FOISCSI_NAME_MAX_LEN 224
2167 #define FW_FOISCSI_ALIAS_MAX_LEN 224
2168 #define FW_FOISCSI_KEY_MAX_LEN 64
2169 #define FW_FOISCSI_VAL_MAX_LEN 256
2170 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128
2171 #define FW_FOISCSI_INIT_NODE_MAX 8
2172
2173 enum fw_chnet_ifconf_wr_subop {
2174 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0,
2175
2176 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET,
2177 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET,
2178
2179 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET,
2180 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET,
2181
2182 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET,
2183 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET,
2184
2185 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET,
2186 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET,
2187
2188 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET,
2189 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET,
2190
2191 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET,
2192 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET,
2193
2194 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET,
2195 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET,
2196
2197 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET,
2198 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET,
2199 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED,
2200
2201 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING4,
2202 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING6,
2203
2204 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING4,
2205 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING6,
2206
2207 FW_CHNET_IFCONF_WR_SUBOP_PMTU6_CLEAR,
2208
2209 FW_CHNET_IFCONF_WR_SUBOP_MAX,
2210 };
2211
2212 struct fw_chnet_ifconf_wr {
2213 __be32 op_compl;
2214 __be32 flowid_len16;
2215 __u64 cookie;
2216 __be32 if_flowid;
2217 __u8 idx;
2218 __u8 subop;
2219 __u8 retval;
2220 __u8 r2;
2221 union {
2222 __be64 r3;
2223 struct fw_chnet_ifconf_ping {
2224 __be16 ping_time;
2225 __u8 ping_rsptype;
2226 __u8 ping_param_rspcode_to_fin_bit;
2227 __u8 ping_pktsize;
2228 __u8 ping_ttl;
2229 __be16 ping_seq;
2230 } ping;
2231 struct fw_chnet_ifconf_mac {
2232 __u8 peer_mac[6];
2233 __u8 smac_idx;
2234 } mac;
2235 } u;
2236 struct fw_chnet_ifconf_params {
2237 __be16 ping_pldsize;
2238 __be16 r0;
2239 __be16 vlanid;
2240 __be16 mtu;
2241 union fw_chnet_ifconf_addr_type {
2242 struct fw_chnet_ifconf_ipv4 {
2243 __be32 addr;
2244 __be32 mask;
2245 __be32 router;
2246 __be32 r0;
2247 __be64 r1;
2248 } ipv4;
2249 struct fw_chnet_ifconf_ipv6 {
2250 __u8 prefix_len;
2251 __u8 r0;
2252 __be16 r1;
2253 __be32 r2;
2254 __be64 addr_hi;
2255 __be64 addr_lo;
2256 __be64 router_hi;
2257 __be64 router_lo;
2258 } ipv6;
2259 } in_attr;
2260 } param;
2261 };
2262
2263 #define S_FW_CHNET_IFCONF_WR_PING_MACBIT 1
2264 #define M_FW_CHNET_IFCONF_WR_PING_MACBIT 0x1
2265 #define V_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \
2266 ((x) << S_FW_CHNET_IFCONF_WR_PING_MACBIT)
2267 #define G_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \
2268 (((x) >> S_FW_CHNET_IFCONF_WR_PING_MACBIT) & \
2269 M_FW_CHNET_IFCONF_WR_PING_MACBIT)
2270 #define F_FW_CHNET_IFCONF_WR_PING_MACBIT \
2271 V_FW_CHNET_IFCONF_WR_PING_MACBIT(1U)
2272
2273 #define S_FW_CHNET_IFCONF_WR_FIN_BIT 0
2274 #define M_FW_CHNET_IFCONF_WR_FIN_BIT 0x1
2275 #define V_FW_CHNET_IFCONF_WR_FIN_BIT(x) ((x) << S_FW_CHNET_IFCONF_WR_FIN_BIT)
2276 #define G_FW_CHNET_IFCONF_WR_FIN_BIT(x) \
2277 (((x) >> S_FW_CHNET_IFCONF_WR_FIN_BIT) & M_FW_CHNET_IFCONF_WR_FIN_BIT)
2278 #define F_FW_CHNET_IFCONF_WR_FIN_BIT V_FW_CHNET_IFCONF_WR_FIN_BIT(1U)
2279
2280 enum fw_foiscsi_node_type {
2281 FW_FOISCSI_NODE_TYPE_INITIATOR = 0,
2282 FW_FOISCSI_NODE_TYPE_TARGET,
2283 };
2284
2285 enum fw_foiscsi_session_type {
2286 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0,
2287 FW_FOISCSI_SESSION_TYPE_NORMAL,
2288 };
2289
2290 enum fw_foiscsi_auth_policy {
2291 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0,
2292 FW_FOISCSI_AUTH_POLICY_MUTUAL,
2293 };
2294
2295 enum fw_foiscsi_auth_method {
2296 FW_FOISCSI_AUTH_METHOD_NONE = 0,
2297 FW_FOISCSI_AUTH_METHOD_CHAP,
2298 FW_FOISCSI_AUTH_METHOD_CHAP_FST,
2299 FW_FOISCSI_AUTH_METHOD_CHAP_SEC,
2300 };
2301
2302 enum fw_foiscsi_digest_type {
2303 FW_FOISCSI_DIGEST_TYPE_NONE = 0,
2304 FW_FOISCSI_DIGEST_TYPE_CRC32,
2305 FW_FOISCSI_DIGEST_TYPE_CRC32_FST,
2306 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC,
2307 };
2308
2309 enum fw_foiscsi_wr_subop {
2310 FW_FOISCSI_WR_SUBOP_ADD = 1,
2311 FW_FOISCSI_WR_SUBOP_DEL = 2,
2312 FW_FOISCSI_WR_SUBOP_MOD = 4,
2313 };
2314
2315 enum fw_coiscsi_stats_wr_subop {
2316 FW_COISCSI_WR_SUBOP_TOT = 1,
2317 FW_COISCSI_WR_SUBOP_MAX = 2,
2318 FW_COISCSI_WR_SUBOP_CUR = 3,
2319 FW_COISCSI_WR_SUBOP_CLR = 4,
2320 };
2321
2322 enum fw_foiscsi_ctrl_state {
2323 FW_FOISCSI_CTRL_STATE_FREE = 0,
2324 FW_FOISCSI_CTRL_STATE_ONLINE = 1,
2325 FW_FOISCSI_CTRL_STATE_FAILED,
2326 FW_FOISCSI_CTRL_STATE_IN_RECOVERY,
2327 FW_FOISCSI_CTRL_STATE_REDIRECT,
2328 };
2329
2330 struct fw_rdev_wr {
2331 __be32 op_to_immdlen;
2332 __be32 alloc_to_len16;
2333 __be64 cookie;
2334 __u8 protocol;
2335 __u8 event_cause;
2336 __u8 cur_state;
2337 __u8 prev_state;
2338 __be32 flags_to_assoc_flowid;
2339 union rdev_entry {
2340 struct fcoe_rdev_entry {
2341 __be32 flowid;
2342 __u8 protocol;
2343 __u8 event_cause;
2344 __u8 flags;
2345 __u8 rjt_reason;
2346 __u8 cur_login_st;
2347 __u8 prev_login_st;
2348 __be16 rcv_fr_sz;
2349 __u8 rd_xfer_rdy_to_rport_type;
2350 __u8 vft_to_qos;
2351 __u8 org_proc_assoc_to_acc_rsp_code;
2352 __u8 enh_disc_to_tgt;
2353 __u8 wwnn[8];
2354 __u8 wwpn[8];
2355 __be16 iqid;
2356 __u8 fc_oui[3];
2357 __u8 r_id[3];
2358 } fcoe_rdev;
2359 struct iscsi_rdev_entry {
2360 __be32 flowid;
2361 __u8 protocol;
2362 __u8 event_cause;
2363 __u8 flags;
2364 __u8 r3;
2365 __be16 iscsi_opts;
2366 __be16 tcp_opts;
2367 __be16 ip_opts;
2368 __be16 max_rcv_len;
2369 __be16 max_snd_len;
2370 __be16 first_brst_len;
2371 __be16 max_brst_len;
2372 __be16 r4;
2373 __be16 def_time2wait;
2374 __be16 def_time2ret;
2375 __be16 nop_out_intrvl;
2376 __be16 non_scsi_to;
2377 __be16 isid;
2378 __be16 tsid;
2379 __be16 port;
2380 __be16 tpgt;
2381 __u8 r5[6];
2382 __be16 iqid;
2383 } iscsi_rdev;
2384 } u;
2385 };
2386
2387 #define S_FW_RDEV_WR_IMMDLEN 0
2388 #define M_FW_RDEV_WR_IMMDLEN 0xff
2389 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN)
2390 #define G_FW_RDEV_WR_IMMDLEN(x) \
2391 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)
2392
2393 #define S_FW_RDEV_WR_ALLOC 31
2394 #define M_FW_RDEV_WR_ALLOC 0x1
2395 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC)
2396 #define G_FW_RDEV_WR_ALLOC(x) \
2397 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
2398 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U)
2399
2400 #define S_FW_RDEV_WR_FREE 30
2401 #define M_FW_RDEV_WR_FREE 0x1
2402 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE)
2403 #define G_FW_RDEV_WR_FREE(x) \
2404 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
2405 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U)
2406
2407 #define S_FW_RDEV_WR_MODIFY 29
2408 #define M_FW_RDEV_WR_MODIFY 0x1
2409 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY)
2410 #define G_FW_RDEV_WR_MODIFY(x) \
2411 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
2412 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U)
2413
2414 #define S_FW_RDEV_WR_FLOWID 8
2415 #define M_FW_RDEV_WR_FLOWID 0xfffff
2416 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID)
2417 #define G_FW_RDEV_WR_FLOWID(x) \
2418 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)
2419
2420 #define S_FW_RDEV_WR_LEN16 0
2421 #define M_FW_RDEV_WR_LEN16 0xff
2422 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16)
2423 #define G_FW_RDEV_WR_LEN16(x) \
2424 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)
2425
2426 #define S_FW_RDEV_WR_FLAGS 24
2427 #define M_FW_RDEV_WR_FLAGS 0xff
2428 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS)
2429 #define G_FW_RDEV_WR_FLAGS(x) \
2430 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)
2431
2432 #define S_FW_RDEV_WR_GET_NEXT 20
2433 #define M_FW_RDEV_WR_GET_NEXT 0xf
2434 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT)
2435 #define G_FW_RDEV_WR_GET_NEXT(x) \
2436 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)
2437
2438 #define S_FW_RDEV_WR_ASSOC_FLOWID 0
2439 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff
2440 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID)
2441 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \
2442 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)
2443
2444 #define S_FW_RDEV_WR_RJT 7
2445 #define M_FW_RDEV_WR_RJT 0x1
2446 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT)
2447 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)
2448 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U)
2449
2450 #define S_FW_RDEV_WR_REASON 0
2451 #define M_FW_RDEV_WR_REASON 0x7f
2452 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON)
2453 #define G_FW_RDEV_WR_REASON(x) \
2454 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)
2455
2456 #define S_FW_RDEV_WR_RD_XFER_RDY 7
2457 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1
2458 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY)
2459 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \
2460 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
2461 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U)
2462
2463 #define S_FW_RDEV_WR_WR_XFER_RDY 6
2464 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1
2465 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY)
2466 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \
2467 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
2468 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U)
2469
2470 #define S_FW_RDEV_WR_FC_SP 5
2471 #define M_FW_RDEV_WR_FC_SP 0x1
2472 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP)
2473 #define G_FW_RDEV_WR_FC_SP(x) \
2474 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
2475 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U)
2476
2477 #define S_FW_RDEV_WR_RPORT_TYPE 0
2478 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f
2479 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE)
2480 #define G_FW_RDEV_WR_RPORT_TYPE(x) \
2481 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)
2482
2483 #define S_FW_RDEV_WR_VFT 7
2484 #define M_FW_RDEV_WR_VFT 0x1
2485 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT)
2486 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)
2487 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U)
2488
2489 #define S_FW_RDEV_WR_NPIV 6
2490 #define M_FW_RDEV_WR_NPIV 0x1
2491 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV)
2492 #define G_FW_RDEV_WR_NPIV(x) \
2493 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
2494 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U)
2495
2496 #define S_FW_RDEV_WR_CLASS 4
2497 #define M_FW_RDEV_WR_CLASS 0x3
2498 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS)
2499 #define G_FW_RDEV_WR_CLASS(x) \
2500 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)
2501
2502 #define S_FW_RDEV_WR_SEQ_DEL 3
2503 #define M_FW_RDEV_WR_SEQ_DEL 0x1
2504 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL)
2505 #define G_FW_RDEV_WR_SEQ_DEL(x) \
2506 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
2507 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U)
2508
2509 #define S_FW_RDEV_WR_PRIO_PREEMP 2
2510 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1
2511 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP)
2512 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \
2513 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
2514 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U)
2515
2516 #define S_FW_RDEV_WR_PREF 1
2517 #define M_FW_RDEV_WR_PREF 0x1
2518 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF)
2519 #define G_FW_RDEV_WR_PREF(x) \
2520 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
2521 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U)
2522
2523 #define S_FW_RDEV_WR_QOS 0
2524 #define M_FW_RDEV_WR_QOS 0x1
2525 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS)
2526 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)
2527 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U)
2528
2529 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7
2530 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1
2531 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)
2532 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \
2533 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
2534 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)
2535
2536 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6
2537 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1
2538 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)
2539 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \
2540 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
2541 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)
2542
2543 #define S_FW_RDEV_WR_IMAGE_PAIR 5
2544 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1
2545 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR)
2546 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \
2547 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
2548 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U)
2549
2550 #define S_FW_RDEV_WR_ACC_RSP_CODE 0
2551 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f
2552 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE)
2553 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \
2554 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)
2555
2556 #define S_FW_RDEV_WR_ENH_DISC 7
2557 #define M_FW_RDEV_WR_ENH_DISC 0x1
2558 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC)
2559 #define G_FW_RDEV_WR_ENH_DISC(x) \
2560 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
2561 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U)
2562
2563 #define S_FW_RDEV_WR_REC 6
2564 #define M_FW_RDEV_WR_REC 0x1
2565 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC)
2566 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)
2567 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U)
2568
2569 #define S_FW_RDEV_WR_TASK_RETRY_ID 5
2570 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1
2571 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID)
2572 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \
2573 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
2574 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U)
2575
2576 #define S_FW_RDEV_WR_RETRY 4
2577 #define M_FW_RDEV_WR_RETRY 0x1
2578 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY)
2579 #define G_FW_RDEV_WR_RETRY(x) \
2580 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
2581 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U)
2582
2583 #define S_FW_RDEV_WR_CONF_CMPL 3
2584 #define M_FW_RDEV_WR_CONF_CMPL 0x1
2585 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL)
2586 #define G_FW_RDEV_WR_CONF_CMPL(x) \
2587 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
2588 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U)
2589
2590 #define S_FW_RDEV_WR_DATA_OVLY 2
2591 #define M_FW_RDEV_WR_DATA_OVLY 0x1
2592 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY)
2593 #define G_FW_RDEV_WR_DATA_OVLY(x) \
2594 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
2595 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U)
2596
2597 #define S_FW_RDEV_WR_INI 1
2598 #define M_FW_RDEV_WR_INI 0x1
2599 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI)
2600 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)
2601 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U)
2602
2603 #define S_FW_RDEV_WR_TGT 0
2604 #define M_FW_RDEV_WR_TGT 0x1
2605 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT)
2606 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)
2607 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U)
2608
2609 struct fw_foiscsi_node_wr {
2610 __be32 op_to_immdlen;
2611 __be32 no_sess_recv_to_len16;
2612 __u64 cookie;
2613 __u8 subop;
2614 __u8 status;
2615 __u8 alias_len;
2616 __u8 iqn_len;
2617 __be32 node_flowid;
2618 __be16 nodeid;
2619 __be16 login_retry;
2620 __be16 retry_timeout;
2621 __be16 r3;
2622 __u8 iqn[224];
2623 __u8 alias[224];
2624 __be32 isid_tval_to_isid_cval;
2625 };
2626
2627 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0
2628 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff
2629 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)
2630 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \
2631 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)
2632
2633 #define S_FW_FOISCSI_NODE_WR_NO_SESS_RECV 28
2634 #define M_FW_FOISCSI_NODE_WR_NO_SESS_RECV 0x1
2635 #define V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \
2636 ((x) << S_FW_FOISCSI_NODE_WR_NO_SESS_RECV)
2637 #define G_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \
2638 (((x) >> S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) & \
2639 M_FW_FOISCSI_NODE_WR_NO_SESS_RECV)
2640 #define F_FW_FOISCSI_NODE_WR_NO_SESS_RECV \
2641 V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(1U)
2642
2643 #define S_FW_FOISCSI_NODE_WR_ISID_TVAL 30
2644 #define M_FW_FOISCSI_NODE_WR_ISID_TVAL 0x3
2645 #define V_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \
2646 ((x) << S_FW_FOISCSI_NODE_WR_ISID_TVAL)
2647 #define G_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \
2648 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_TVAL) & M_FW_FOISCSI_NODE_WR_ISID_TVAL)
2649
2650 #define S_FW_FOISCSI_NODE_WR_ISID_AVAL 24
2651 #define M_FW_FOISCSI_NODE_WR_ISID_AVAL 0x3f
2652 #define V_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \
2653 ((x) << S_FW_FOISCSI_NODE_WR_ISID_AVAL)
2654 #define G_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \
2655 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_AVAL) & M_FW_FOISCSI_NODE_WR_ISID_AVAL)
2656
2657 #define S_FW_FOISCSI_NODE_WR_ISID_BVAL 8
2658 #define M_FW_FOISCSI_NODE_WR_ISID_BVAL 0xffff
2659 #define V_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \
2660 ((x) << S_FW_FOISCSI_NODE_WR_ISID_BVAL)
2661 #define G_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \
2662 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_BVAL) & M_FW_FOISCSI_NODE_WR_ISID_BVAL)
2663
2664 #define S_FW_FOISCSI_NODE_WR_ISID_CVAL 0
2665 #define M_FW_FOISCSI_NODE_WR_ISID_CVAL 0xff
2666 #define V_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \
2667 ((x) << S_FW_FOISCSI_NODE_WR_ISID_CVAL)
2668 #define G_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \
2669 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_CVAL) & M_FW_FOISCSI_NODE_WR_ISID_CVAL)
2670
2671 struct fw_foiscsi_ctrl_wr {
2672 __be32 op_to_no_fin;
2673 __be32 flowid_len16;
2674 __u64 cookie;
2675 __u8 subop;
2676 __u8 status;
2677 __u8 ctrl_state;
2678 __u8 io_state;
2679 __be32 node_id;
2680 __be32 ctrl_id;
2681 __be32 io_id;
2682 struct fw_foiscsi_sess_attr {
2683 __be32 sess_type_to_erl;
2684 __be16 max_conn;
2685 __be16 max_r2t;
2686 __be16 time2wait;
2687 __be16 time2retain;
2688 __be32 max_burst;
2689 __be32 first_burst;
2690 __be32 r1;
2691 } sess_attr;
2692 struct fw_foiscsi_conn_attr {
2693 __be32 hdigest_to_tcp_ws_en;
2694 __be32 max_rcv_dsl;
2695 __be32 ping_tmo;
2696 __be16 dst_port;
2697 __be16 src_port;
2698 union fw_foiscsi_conn_attr_addr {
2699 struct fw_foiscsi_conn_attr_ipv6 {
2700 __be64 dst_addr[2];
2701 __be64 src_addr[2];
2702 } ipv6_addr;
2703 struct fw_foiscsi_conn_attr_ipv4 {
2704 __be32 dst_addr;
2705 __be32 src_addr;
2706 } ipv4_addr;
2707 } u;
2708 } conn_attr;
2709 __u8 tgt_name_len;
2710 __u8 r3[7];
2711 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN];
2712 };
2713
2714 #define S_FW_FOISCSI_CTRL_WR_PORTID 1
2715 #define M_FW_FOISCSI_CTRL_WR_PORTID 0x7
2716 #define V_FW_FOISCSI_CTRL_WR_PORTID(x) ((x) << S_FW_FOISCSI_CTRL_WR_PORTID)
2717 #define G_FW_FOISCSI_CTRL_WR_PORTID(x) \
2718 (((x) >> S_FW_FOISCSI_CTRL_WR_PORTID) & M_FW_FOISCSI_CTRL_WR_PORTID)
2719
2720 #define S_FW_FOISCSI_CTRL_WR_NO_FIN 0
2721 #define M_FW_FOISCSI_CTRL_WR_NO_FIN 0x1
2722 #define V_FW_FOISCSI_CTRL_WR_NO_FIN(x) ((x) << S_FW_FOISCSI_CTRL_WR_NO_FIN)
2723 #define G_FW_FOISCSI_CTRL_WR_NO_FIN(x) \
2724 (((x) >> S_FW_FOISCSI_CTRL_WR_NO_FIN) & M_FW_FOISCSI_CTRL_WR_NO_FIN)
2725 #define F_FW_FOISCSI_CTRL_WR_NO_FIN V_FW_FOISCSI_CTRL_WR_NO_FIN(1U)
2726
2727 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30
2728 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3
2729 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \
2730 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2731 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \
2732 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2733
2734 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29
2735 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1
2736 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \
2737 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2738 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \
2739 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
2740 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2741 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \
2742 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)
2743
2744 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28
2745 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1
2746 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \
2747 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2748 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \
2749 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
2750 M_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2751 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \
2752 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)
2753
2754 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27
2755 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1
2756 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \
2757 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2758 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \
2759 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
2760 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2761 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \
2762 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)
2763
2764 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26
2765 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1
2766 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \
2767 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2768 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \
2769 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
2770 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2771 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \
2772 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)
2773
2774 #define S_FW_FOISCSI_CTRL_WR_ERL 24
2775 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3
2776 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL)
2777 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \
2778 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)
2779
2780 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30
2781 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3
2782 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)
2783 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \
2784 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)
2785
2786 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28
2787 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3
2788 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)
2789 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \
2790 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)
2791
2792 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25
2793 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7
2794 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \
2795 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2796 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \
2797 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
2798 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2799
2800 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23
2801 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3
2802 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \
2803 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2804 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \
2805 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
2806 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2807
2808 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21
2809 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3
2810 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \
2811 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2812 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \
2813 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2814
2815 #define S_FW_FOISCSI_CTRL_WR_IPV6 20
2816 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1
2817 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6)
2818 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \
2819 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6)
2820 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U)
2821
2822 #define S_FW_FOISCSI_CTRL_WR_DDP_PGIDX 16
2823 #define M_FW_FOISCSI_CTRL_WR_DDP_PGIDX 0xf
2824 #define V_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \
2825 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGIDX)
2826 #define G_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \
2827 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) & M_FW_FOISCSI_CTRL_WR_DDP_PGIDX)
2828
2829 #define S_FW_FOISCSI_CTRL_WR_TCP_WS 12
2830 #define M_FW_FOISCSI_CTRL_WR_TCP_WS 0xf
2831 #define V_FW_FOISCSI_CTRL_WR_TCP_WS(x) ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS)
2832 #define G_FW_FOISCSI_CTRL_WR_TCP_WS(x) \
2833 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS) & M_FW_FOISCSI_CTRL_WR_TCP_WS)
2834
2835 #define S_FW_FOISCSI_CTRL_WR_TCP_WS_EN 11
2836 #define M_FW_FOISCSI_CTRL_WR_TCP_WS_EN 0x1
2837 #define V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \
2838 ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS_EN)
2839 #define G_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \
2840 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) & M_FW_FOISCSI_CTRL_WR_TCP_WS_EN)
2841 #define F_FW_FOISCSI_CTRL_WR_TCP_WS_EN V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(1U)
2842
2843 struct fw_foiscsi_chap_wr {
2844 __be32 op_to_kv_flag;
2845 __be32 flowid_len16;
2846 __u64 cookie;
2847 __u8 status;
2848 union fw_foiscsi_len {
2849 struct fw_foiscsi_chap_lens {
2850 __u8 id_len;
2851 __u8 sec_len;
2852 } chapl;
2853 struct fw_foiscsi_vend_kv_lens {
2854 __u8 key_len;
2855 __u8 val_len;
2856 } vend_kvl;
2857 } lenu;
2858 __u8 node_type;
2859 __be16 node_id;
2860 __u8 r3[2];
2861 union fw_foiscsi_chap_vend {
2862 struct fw_foiscsi_chap {
2863 __u8 chap_id[224];
2864 __u8 chap_sec[128];
2865 } chap;
2866 struct fw_foiscsi_vend_kv {
2867 __u8 vend_key[64];
2868 __u8 vend_val[256];
2869 } vend_kv;
2870 } u;
2871 };
2872
2873 #define S_FW_FOISCSI_CHAP_WR_KV_FLAG 20
2874 #define M_FW_FOISCSI_CHAP_WR_KV_FLAG 0x1
2875 #define V_FW_FOISCSI_CHAP_WR_KV_FLAG(x) ((x) << S_FW_FOISCSI_CHAP_WR_KV_FLAG)
2876 #define G_FW_FOISCSI_CHAP_WR_KV_FLAG(x) \
2877 (((x) >> S_FW_FOISCSI_CHAP_WR_KV_FLAG) & M_FW_FOISCSI_CHAP_WR_KV_FLAG)
2878 #define F_FW_FOISCSI_CHAP_WR_KV_FLAG V_FW_FOISCSI_CHAP_WR_KV_FLAG(1U)
2879
2880 /******************************************************************************
2881 * C O i S C S I W O R K R E Q U E S T S
2882 ********************************************/
2883
2884 enum fw_chnet_addr_type {
2885 FW_CHNET_ADDD_TYPE_NONE = 0,
2886 FW_CHNET_ADDR_TYPE_IPV4,
2887 FW_CHNET_ADDR_TYPE_IPV6,
2888 };
2889
2890 enum fw_msg_wr_type {
2891 FW_MSG_WR_TYPE_RPL = 0,
2892 FW_MSG_WR_TYPE_ERR,
2893 FW_MSG_WR_TYPE_PLD,
2894 };
2895
2896 struct fw_coiscsi_tgt_wr {
2897 __be32 op_compl;
2898 __be32 flowid_len16;
2899 __u64 cookie;
2900 __u8 subop;
2901 __u8 status;
2902 __be16 r4;
2903 __be32 flags;
2904 struct fw_coiscsi_tgt_conn_attr {
2905 __be32 in_tid;
2906 __be16 in_port;
2907 __u8 in_type;
2908 __u8 r6;
2909 union fw_coiscsi_tgt_conn_attr_addr {
2910 struct fw_coiscsi_tgt_conn_attr_in_addr {
2911 __be32 addr;
2912 __be32 r7;
2913 __be32 r8[2];
2914 } in_addr;
2915 struct fw_coiscsi_tgt_conn_attr_in_addr6 {
2916 __be64 addr[2];
2917 } in_addr6;
2918 } u;
2919 } conn_attr;
2920 };
2921
2922 #define S_FW_COISCSI_TGT_WR_PORTID 0
2923 #define M_FW_COISCSI_TGT_WR_PORTID 0x7
2924 #define V_FW_COISCSI_TGT_WR_PORTID(x) ((x) << S_FW_COISCSI_TGT_WR_PORTID)
2925 #define G_FW_COISCSI_TGT_WR_PORTID(x) \
2926 (((x) >> S_FW_COISCSI_TGT_WR_PORTID) & M_FW_COISCSI_TGT_WR_PORTID)
2927
2928 struct fw_coiscsi_tgt_conn_wr {
2929 __be32 op_compl;
2930 __be32 flowid_len16;
2931 __u64 cookie;
2932 __u8 subop;
2933 __u8 status;
2934 __be16 iq_id;
2935 __be32 in_stid;
2936 __be32 io_id;
2937 __be32 flags_fin;
2938 union {
2939 struct fw_coiscsi_tgt_conn_tcp {
2940 __be16 in_sport;
2941 __be16 in_dport;
2942 __u8 wscale_wsen;
2943 __u8 r4[3];
2944 union fw_coiscsi_tgt_conn_tcp_addr {
2945 struct fw_coiscsi_tgt_conn_tcp_in_addr {
2946 __be32 saddr;
2947 __be32 daddr;
2948 } in_addr;
2949 struct fw_coiscsi_tgt_conn_tcp_in_addr6 {
2950 __be64 saddr[2];
2951 __be64 daddr[2];
2952 } in_addr6;
2953 } u;
2954 } conn_tcp;
2955 struct fw_coiscsi_tgt_conn_stats {
2956 __be32 ddp_reqs;
2957 __be32 ddp_cmpls;
2958 __be16 ddp_aborts;
2959 __be16 ddp_bps;
2960 } stats;
2961 } u;
2962 struct fw_coiscsi_tgt_conn_iscsi {
2963 __be32 hdigest_to_ddp_pgsz;
2964 __be32 tgt_id;
2965 __be16 max_r2t;
2966 __be16 r5;
2967 __be32 max_burst;
2968 __be32 max_rdsl;
2969 __be32 max_tdsl;
2970 __be32 cur_sn;
2971 __be32 r6;
2972 } conn_iscsi;
2973 };
2974
2975 #define S_FW_COISCSI_TGT_CONN_WR_PORTID 0
2976 #define M_FW_COISCSI_TGT_CONN_WR_PORTID 0x7
2977 #define V_FW_COISCSI_TGT_CONN_WR_PORTID(x) \
2978 ((x) << S_FW_COISCSI_TGT_CONN_WR_PORTID)
2979 #define G_FW_COISCSI_TGT_CONN_WR_PORTID(x) \
2980 (((x) >> S_FW_COISCSI_TGT_CONN_WR_PORTID) & \
2981 M_FW_COISCSI_TGT_CONN_WR_PORTID)
2982
2983 #define S_FW_COISCSI_TGT_CONN_WR_FIN 0
2984 #define M_FW_COISCSI_TGT_CONN_WR_FIN 0x1
2985 #define V_FW_COISCSI_TGT_CONN_WR_FIN(x) ((x) << S_FW_COISCSI_TGT_CONN_WR_FIN)
2986 #define G_FW_COISCSI_TGT_CONN_WR_FIN(x) \
2987 (((x) >> S_FW_COISCSI_TGT_CONN_WR_FIN) & M_FW_COISCSI_TGT_CONN_WR_FIN)
2988 #define F_FW_COISCSI_TGT_CONN_WR_FIN V_FW_COISCSI_TGT_CONN_WR_FIN(1U)
2989
2990 #define S_FW_COISCSI_TGT_CONN_WR_WSCALE 1
2991 #define M_FW_COISCSI_TGT_CONN_WR_WSCALE 0xf
2992 #define V_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \
2993 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSCALE)
2994 #define G_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \
2995 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSCALE) & \
2996 M_FW_COISCSI_TGT_CONN_WR_WSCALE)
2997
2998 #define S_FW_COISCSI_TGT_CONN_WR_WSEN 0
2999 #define M_FW_COISCSI_TGT_CONN_WR_WSEN 0x1
3000 #define V_FW_COISCSI_TGT_CONN_WR_WSEN(x) \
3001 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSEN)
3002 #define G_FW_COISCSI_TGT_CONN_WR_WSEN(x) \
3003 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSEN) & M_FW_COISCSI_TGT_CONN_WR_WSEN)
3004 #define F_FW_COISCSI_TGT_CONN_WR_WSEN V_FW_COISCSI_TGT_CONN_WR_WSEN(1U)
3005
3006 struct fw_coiscsi_tgt_xmit_wr {
3007 __be32 op_to_immdlen;
3008 union {
3009 struct cmpl_stat {
3010 __be32 cmpl_status_pkd;
3011 } cs;
3012 struct flowid_len {
3013 __be32 flowid_len16;
3014 } fllen;
3015 } u;
3016 __u64 cookie;
3017 __be16 iq_id;
3018 __be16 r3;
3019 __be32 pz_off;
3020 __be32 t_xfer_len;
3021 union {
3022 __be32 tag;
3023 __be32 datasn;
3024 __be32 ddp_status;
3025 } cu;
3026 };
3027
3028 #define S_FW_COISCSI_TGT_XMIT_WR_DDGST 23
3029 #define M_FW_COISCSI_TGT_XMIT_WR_DDGST 0x1
3030 #define V_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \
3031 ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDGST)
3032 #define G_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \
3033 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDGST) & M_FW_COISCSI_TGT_XMIT_WR_DDGST)
3034 #define F_FW_COISCSI_TGT_XMIT_WR_DDGST V_FW_COISCSI_TGT_XMIT_WR_DDGST(1U)
3035
3036 #define S_FW_COISCSI_TGT_XMIT_WR_HDGST 22
3037 #define M_FW_COISCSI_TGT_XMIT_WR_HDGST 0x1
3038 #define V_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \
3039 ((x) << S_FW_COISCSI_TGT_XMIT_WR_HDGST)
3040 #define G_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \
3041 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_HDGST) & M_FW_COISCSI_TGT_XMIT_WR_HDGST)
3042 #define F_FW_COISCSI_TGT_XMIT_WR_HDGST V_FW_COISCSI_TGT_XMIT_WR_HDGST(1U)
3043
3044 #define S_FW_COISCSI_TGT_XMIT_WR_DDP 20
3045 #define M_FW_COISCSI_TGT_XMIT_WR_DDP 0x1
3046 #define V_FW_COISCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDP)
3047 #define G_FW_COISCSI_TGT_XMIT_WR_DDP(x) \
3048 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDP) & M_FW_COISCSI_TGT_XMIT_WR_DDP)
3049 #define F_FW_COISCSI_TGT_XMIT_WR_DDP V_FW_COISCSI_TGT_XMIT_WR_DDP(1U)
3050
3051 #define S_FW_COISCSI_TGT_XMIT_WR_ABORT 19
3052 #define M_FW_COISCSI_TGT_XMIT_WR_ABORT 0x1
3053 #define V_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \
3054 ((x) << S_FW_COISCSI_TGT_XMIT_WR_ABORT)
3055 #define G_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \
3056 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_ABORT) & M_FW_COISCSI_TGT_XMIT_WR_ABORT)
3057 #define F_FW_COISCSI_TGT_XMIT_WR_ABORT V_FW_COISCSI_TGT_XMIT_WR_ABORT(1U)
3058
3059 #define S_FW_COISCSI_TGT_XMIT_WR_FINAL 18
3060 #define M_FW_COISCSI_TGT_XMIT_WR_FINAL 0x1
3061 #define V_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \
3062 ((x) << S_FW_COISCSI_TGT_XMIT_WR_FINAL)
3063 #define G_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \
3064 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_FINAL) & M_FW_COISCSI_TGT_XMIT_WR_FINAL)
3065 #define F_FW_COISCSI_TGT_XMIT_WR_FINAL V_FW_COISCSI_TGT_XMIT_WR_FINAL(1U)
3066
3067 #define S_FW_COISCSI_TGT_XMIT_WR_PADLEN 16
3068 #define M_FW_COISCSI_TGT_XMIT_WR_PADLEN 0x3
3069 #define V_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \
3070 ((x) << S_FW_COISCSI_TGT_XMIT_WR_PADLEN)
3071 #define G_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \
3072 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_PADLEN) & \
3073 M_FW_COISCSI_TGT_XMIT_WR_PADLEN)
3074
3075 #define S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 15
3076 #define M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 0x1
3077 #define V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \
3078 ((x) << S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN)
3079 #define G_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \
3080 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) & \
3081 M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN)
3082 #define F_FW_COISCSI_TGT_XMIT_WR_INCSTATSN \
3083 V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(1U)
3084
3085 #define S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0
3086 #define M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0xff
3087 #define V_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \
3088 ((x) << S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN)
3089 #define G_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \
3090 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) & \
3091 M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN)
3092
3093 #define S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 8
3094 #define M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 0xff
3095 #define V_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \
3096 ((x) << S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS)
3097 #define G_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \
3098 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) & \
3099 M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS)
3100
3101 struct fw_coiscsi_stats_wr {
3102 __be32 op_compl;
3103 __be32 flowid_len16;
3104 __u64 cookie;
3105 __u8 subop;
3106 __u8 status;
3107 union fw_coiscsi_stats {
3108 struct fw_coiscsi_resource {
3109 __u8 num_ipv4_tgt;
3110 __u8 num_ipv6_tgt;
3111 __be16 num_l2t_entries;
3112 __be16 num_csocks;
3113 __be16 num_tasks;
3114 __be16 num_ppods_zone[11];
3115 __be32 num_bufll64;
3116 __u8 r2[12];
3117 } rsrc;
3118 } u;
3119 };
3120
3121 #define S_FW_COISCSI_STATS_WR_PORTID 0
3122 #define M_FW_COISCSI_STATS_WR_PORTID 0x7
3123 #define V_FW_COISCSI_STATS_WR_PORTID(x) ((x) << S_FW_COISCSI_STATS_WR_PORTID)
3124 #define G_FW_COISCSI_STATS_WR_PORTID(x) \
3125 (((x) >> S_FW_COISCSI_STATS_WR_PORTID) & M_FW_COISCSI_STATS_WR_PORTID)
3126
3127 struct fw_isns_wr {
3128 __be32 op_compl;
3129 __be32 flowid_len16;
3130 __u64 cookie;
3131 __u8 subop;
3132 __u8 status;
3133 __be16 iq_id;
3134 __be16 vlanid;
3135 __be16 r4;
3136 struct fw_tcp_conn_attr {
3137 __be32 in_tid;
3138 __be16 in_port;
3139 __u8 in_type;
3140 __u8 r6;
3141 union fw_tcp_conn_attr_addr {
3142 struct fw_tcp_conn_attr_in_addr {
3143 __be32 addr;
3144 __be32 r7;
3145 __be32 r8[2];
3146 } in_addr;
3147 struct fw_tcp_conn_attr_in_addr6 {
3148 __be64 addr[2];
3149 } in_addr6;
3150 } u;
3151 } conn_attr;
3152 };
3153
3154 #define S_FW_ISNS_WR_PORTID 0
3155 #define M_FW_ISNS_WR_PORTID 0x7
3156 #define V_FW_ISNS_WR_PORTID(x) ((x) << S_FW_ISNS_WR_PORTID)
3157 #define G_FW_ISNS_WR_PORTID(x) \
3158 (((x) >> S_FW_ISNS_WR_PORTID) & M_FW_ISNS_WR_PORTID)
3159
3160 struct fw_isns_xmit_wr {
3161 __be32 op_to_immdlen;
3162 __be32 flowid_len16;
3163 __u64 cookie;
3164 __be16 iq_id;
3165 __be16 r4;
3166 __be32 xfer_len;
3167 __be64 r5;
3168 };
3169
3170 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0
3171 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff
3172 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN)
3173 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \
3174 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN)
3175
3176 /******************************************************************************
3177 * F O F C O E W O R K R E Q U E S T s
3178 *******************************************/
3179
3180 struct fw_fcoe_els_ct_wr {
3181 __be32 op_immdlen;
3182 __be32 flowid_len16;
3183 __be64 cookie;
3184 __be16 iqid;
3185 __u8 tmo_val;
3186 __u8 els_ct_type;
3187 __u8 ctl_pri;
3188 __u8 cp_en_class;
3189 __be16 xfer_cnt;
3190 __u8 fl_to_sp;
3191 __u8 l_id[3];
3192 __u8 r5;
3193 __u8 r_id[3];
3194 __be64 rsp_dmaaddr;
3195 __be32 rsp_dmalen;
3196 __be32 r6;
3197 };
3198
3199 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24
3200 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff
3201 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)
3202 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \
3203 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)
3204
3205 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0
3206 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff
3207 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)
3208 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \
3209 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)
3210
3211 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8
3212 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff
3213 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)
3214 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \
3215 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)
3216
3217 #define S_FW_FCOE_ELS_CT_WR_LEN16 0
3218 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff
3219 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16)
3220 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \
3221 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)
3222
3223 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6
3224 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3
3225 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)
3226 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \
3227 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)
3228
3229 #define S_FW_FCOE_ELS_CT_WR_CLASS 4
3230 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3
3231 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS)
3232 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \
3233 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)
3234
3235 #define S_FW_FCOE_ELS_CT_WR_FL 2
3236 #define M_FW_FCOE_ELS_CT_WR_FL 0x1
3237 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL)
3238 #define G_FW_FCOE_ELS_CT_WR_FL(x) \
3239 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
3240 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U)
3241
3242 #define S_FW_FCOE_ELS_CT_WR_NPIV 1
3243 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1
3244 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV)
3245 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \
3246 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
3247 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U)
3248
3249 #define S_FW_FCOE_ELS_CT_WR_SP 0
3250 #define M_FW_FCOE_ELS_CT_WR_SP 0x1
3251 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP)
3252 #define G_FW_FCOE_ELS_CT_WR_SP(x) \
3253 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
3254 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U)
3255
3256 /******************************************************************************
3257 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path)
3258 *****************************************************************************/
3259
3260 struct fw_scsi_write_wr {
3261 __be32 op_immdlen;
3262 __be32 flowid_len16;
3263 __be64 cookie;
3264 __be16 iqid;
3265 __u8 tmo_val;
3266 __u8 use_xfer_cnt;
3267 union fw_scsi_write_priv {
3268 struct fcoe_write_priv {
3269 __u8 ctl_pri;
3270 __u8 cp_en_class;
3271 __u8 r3_lo[2];
3272 } fcoe;
3273 struct iscsi_write_priv {
3274 __u8 r3[4];
3275 } iscsi;
3276 } u;
3277 __be32 xfer_cnt;
3278 __be32 ini_xfer_cnt;
3279 __be64 rsp_dmaaddr;
3280 __be32 rsp_dmalen;
3281 __be32 r4;
3282 };
3283
3284 #define S_FW_SCSI_WRITE_WR_OPCODE 24
3285 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff
3286 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE)
3287 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \
3288 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)
3289
3290 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0
3291 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff
3292 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)
3293 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \
3294 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)
3295
3296 #define S_FW_SCSI_WRITE_WR_FLOWID 8
3297 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff
3298 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID)
3299 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \
3300 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)
3301
3302 #define S_FW_SCSI_WRITE_WR_LEN16 0
3303 #define M_FW_SCSI_WRITE_WR_LEN16 0xff
3304 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16)
3305 #define G_FW_SCSI_WRITE_WR_LEN16(x) \
3306 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)
3307
3308 #define S_FW_SCSI_WRITE_WR_CP_EN 6
3309 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3
3310 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN)
3311 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \
3312 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)
3313
3314 #define S_FW_SCSI_WRITE_WR_CLASS 4
3315 #define M_FW_SCSI_WRITE_WR_CLASS 0x3
3316 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS)
3317 #define G_FW_SCSI_WRITE_WR_CLASS(x) \
3318 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)
3319
3320 struct fw_scsi_read_wr {
3321 __be32 op_immdlen;
3322 __be32 flowid_len16;
3323 __be64 cookie;
3324 __be16 iqid;
3325 __u8 tmo_val;
3326 __u8 use_xfer_cnt;
3327 union fw_scsi_read_priv {
3328 struct fcoe_read_priv {
3329 __u8 ctl_pri;
3330 __u8 cp_en_class;
3331 __u8 r3_lo[2];
3332 } fcoe;
3333 struct iscsi_read_priv {
3334 __u8 r3[4];
3335 } iscsi;
3336 } u;
3337 __be32 xfer_cnt;
3338 __be32 ini_xfer_cnt;
3339 __be64 rsp_dmaaddr;
3340 __be32 rsp_dmalen;
3341 __be32 r4;
3342 };
3343
3344 #define S_FW_SCSI_READ_WR_OPCODE 24
3345 #define M_FW_SCSI_READ_WR_OPCODE 0xff
3346 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE)
3347 #define G_FW_SCSI_READ_WR_OPCODE(x) \
3348 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)
3349
3350 #define S_FW_SCSI_READ_WR_IMMDLEN 0
3351 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff
3352 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN)
3353 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \
3354 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)
3355
3356 #define S_FW_SCSI_READ_WR_FLOWID 8
3357 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff
3358 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID)
3359 #define G_FW_SCSI_READ_WR_FLOWID(x) \
3360 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)
3361
3362 #define S_FW_SCSI_READ_WR_LEN16 0
3363 #define M_FW_SCSI_READ_WR_LEN16 0xff
3364 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16)
3365 #define G_FW_SCSI_READ_WR_LEN16(x) \
3366 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)
3367
3368 #define S_FW_SCSI_READ_WR_CP_EN 6
3369 #define M_FW_SCSI_READ_WR_CP_EN 0x3
3370 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN)
3371 #define G_FW_SCSI_READ_WR_CP_EN(x) \
3372 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)
3373
3374 #define S_FW_SCSI_READ_WR_CLASS 4
3375 #define M_FW_SCSI_READ_WR_CLASS 0x3
3376 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS)
3377 #define G_FW_SCSI_READ_WR_CLASS(x) \
3378 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)
3379
3380 struct fw_scsi_cmd_wr {
3381 __be32 op_immdlen;
3382 __be32 flowid_len16;
3383 __be64 cookie;
3384 __be16 iqid;
3385 __u8 tmo_val;
3386 __u8 r3;
3387 union fw_scsi_cmd_priv {
3388 struct fcoe_cmd_priv {
3389 __u8 ctl_pri;
3390 __u8 cp_en_class;
3391 __u8 r4_lo[2];
3392 } fcoe;
3393 struct iscsi_cmd_priv {
3394 __u8 r4[4];
3395 } iscsi;
3396 } u;
3397 __u8 r5[8];
3398 __be64 rsp_dmaaddr;
3399 __be32 rsp_dmalen;
3400 __be32 r6;
3401 };
3402
3403 #define S_FW_SCSI_CMD_WR_OPCODE 24
3404 #define M_FW_SCSI_CMD_WR_OPCODE 0xff
3405 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE)
3406 #define G_FW_SCSI_CMD_WR_OPCODE(x) \
3407 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)
3408
3409 #define S_FW_SCSI_CMD_WR_IMMDLEN 0
3410 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff
3411 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN)
3412 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \
3413 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)
3414
3415 #define S_FW_SCSI_CMD_WR_FLOWID 8
3416 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff
3417 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID)
3418 #define G_FW_SCSI_CMD_WR_FLOWID(x) \
3419 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)
3420
3421 #define S_FW_SCSI_CMD_WR_LEN16 0
3422 #define M_FW_SCSI_CMD_WR_LEN16 0xff
3423 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16)
3424 #define G_FW_SCSI_CMD_WR_LEN16(x) \
3425 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)
3426
3427 #define S_FW_SCSI_CMD_WR_CP_EN 6
3428 #define M_FW_SCSI_CMD_WR_CP_EN 0x3
3429 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN)
3430 #define G_FW_SCSI_CMD_WR_CP_EN(x) \
3431 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)
3432
3433 #define S_FW_SCSI_CMD_WR_CLASS 4
3434 #define M_FW_SCSI_CMD_WR_CLASS 0x3
3435 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS)
3436 #define G_FW_SCSI_CMD_WR_CLASS(x) \
3437 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)
3438
3439 struct fw_scsi_abrt_cls_wr {
3440 __be32 op_immdlen;
3441 __be32 flowid_len16;
3442 __be64 cookie;
3443 __be16 iqid;
3444 __u8 tmo_val;
3445 __u8 sub_opcode_to_chk_all_io;
3446 __u8 r3[4];
3447 __be64 t_cookie;
3448 };
3449
3450 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24
3451 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff
3452 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE)
3453 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \
3454 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)
3455
3456 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0
3457 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff
3458 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \
3459 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
3460 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \
3461 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
3462
3463 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8
3464 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff
3465 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID)
3466 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \
3467 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)
3468
3469 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0
3470 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff
3471 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16)
3472 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \
3473 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)
3474
3475 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2
3476 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f
3477 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \
3478 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
3479 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \
3480 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \
3481 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
3482
3483 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1
3484 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1
3485 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL)
3486 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \
3487 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)
3488 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U)
3489
3490 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0
3491 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1
3492 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \
3493 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
3494 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \
3495 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \
3496 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
3497 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \
3498 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U)
3499
3500 struct fw_scsi_tgt_acc_wr {
3501 __be32 op_immdlen;
3502 __be32 flowid_len16;
3503 __be64 cookie;
3504 __be16 iqid;
3505 __u8 r3;
3506 __u8 use_burst_len;
3507 union fw_scsi_tgt_acc_priv {
3508 struct fcoe_tgt_acc_priv {
3509 __u8 ctl_pri;
3510 __u8 cp_en_class;
3511 __u8 r4_lo[2];
3512 } fcoe;
3513 struct iscsi_tgt_acc_priv {
3514 __u8 r4[4];
3515 } iscsi;
3516 } u;
3517 __be32 burst_len;
3518 __be32 rel_off;
3519 __be64 r5;
3520 __be32 r6;
3521 __be32 tot_xfer_len;
3522 };
3523
3524 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24
3525 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff
3526 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE)
3527 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \
3528 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)
3529
3530 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0
3531 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff
3532 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN)
3533 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \
3534 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)
3535
3536 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8
3537 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff
3538 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID)
3539 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \
3540 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)
3541
3542 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0
3543 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff
3544 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16)
3545 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \
3546 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)
3547
3548 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6
3549 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3
3550 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN)
3551 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \
3552 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)
3553
3554 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4
3555 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3
3556 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS)
3557 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \
3558 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)
3559
3560 struct fw_scsi_tgt_xmit_wr {
3561 __be32 op_immdlen;
3562 __be32 flowid_len16;
3563 __be64 cookie;
3564 __be16 iqid;
3565 __u8 auto_rsp;
3566 __u8 use_xfer_cnt;
3567 union fw_scsi_tgt_xmit_priv {
3568 struct fcoe_tgt_xmit_priv {
3569 __u8 ctl_pri;
3570 __u8 cp_en_class;
3571 __u8 r3_lo[2];
3572 } fcoe;
3573 struct iscsi_tgt_xmit_priv {
3574 __u8 r3[4];
3575 } iscsi;
3576 } u;
3577 __be32 xfer_cnt;
3578 __be32 r4;
3579 __be64 r5;
3580 __be32 r6;
3581 __be32 tot_xfer_len;
3582 };
3583
3584 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24
3585 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff
3586 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE)
3587 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \
3588 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)
3589
3590 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0
3591 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff
3592 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \
3593 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
3594 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \
3595 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
3596
3597 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8
3598 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff
3599 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID)
3600 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \
3601 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)
3602
3603 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0
3604 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff
3605 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16)
3606 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \
3607 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)
3608
3609 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6
3610 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3
3611 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN)
3612 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \
3613 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)
3614
3615 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4
3616 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3
3617 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS)
3618 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \
3619 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)
3620
3621 struct fw_scsi_tgt_rsp_wr {
3622 __be32 op_immdlen;
3623 __be32 flowid_len16;
3624 __be64 cookie;
3625 __be16 iqid;
3626 __u8 r3[2];
3627 union fw_scsi_tgt_rsp_priv {
3628 struct fcoe_tgt_rsp_priv {
3629 __u8 ctl_pri;
3630 __u8 cp_en_class;
3631 __u8 r4_lo[2];
3632 } fcoe;
3633 struct iscsi_tgt_rsp_priv {
3634 __u8 r4[4];
3635 } iscsi;
3636 } u;
3637 __u8 r5[8];
3638 };
3639
3640 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24
3641 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff
3642 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE)
3643 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \
3644 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)
3645
3646 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0
3647 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff
3648 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN)
3649 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \
3650 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)
3651
3652 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8
3653 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff
3654 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID)
3655 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \
3656 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)
3657
3658 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0
3659 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff
3660 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16)
3661 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \
3662 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)
3663
3664 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6
3665 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3
3666 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN)
3667 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \
3668 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)
3669
3670 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4
3671 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3
3672 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS)
3673 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \
3674 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)
3675
3676 struct fw_pofcoe_tcb_wr {
3677 __be32 op_compl;
3678 __be32 equiq_to_len16;
3679 __be32 r4;
3680 __be32 xfer_len;
3681 __be32 tid_to_port;
3682 __be16 x_id;
3683 __be16 vlan_id;
3684 __be64 cookie;
3685 __be32 s_id;
3686 __be32 d_id;
3687 __be32 tag;
3688 __be16 r6;
3689 __be16 iqid;
3690 };
3691
3692 #define S_FW_POFCOE_TCB_WR_TID 12
3693 #define M_FW_POFCOE_TCB_WR_TID 0xfffff
3694 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID)
3695 #define G_FW_POFCOE_TCB_WR_TID(x) \
3696 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID)
3697
3698 #define S_FW_POFCOE_TCB_WR_ALLOC 4
3699 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1
3700 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC)
3701 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \
3702 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC)
3703 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U)
3704
3705 #define S_FW_POFCOE_TCB_WR_FREE 3
3706 #define M_FW_POFCOE_TCB_WR_FREE 0x1
3707 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE)
3708 #define G_FW_POFCOE_TCB_WR_FREE(x) \
3709 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE)
3710 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U)
3711
3712 #define S_FW_POFCOE_TCB_WR_PORT 0
3713 #define M_FW_POFCOE_TCB_WR_PORT 0x7
3714 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT)
3715 #define G_FW_POFCOE_TCB_WR_PORT(x) \
3716 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT)
3717
3718 struct fw_pofcoe_ulptx_wr {
3719 __be32 op_pkd;
3720 __be32 equiq_to_len16;
3721 __u64 cookie;
3722 };
3723
3724 /*******************************************************************
3725 * T10 DIF related definition
3726 *******************************************************************/
3727 struct fw_tx_pi_header {
3728 __be16 op_to_inline;
3729 __u8 pi_interval_tag_type;
3730 __u8 num_pi;
3731 __be32 pi_start4_pi_end4;
3732 __u8 tag_gen_enabled_pkd;
3733 __u8 num_pi_dsg;
3734 __be16 app_tag;
3735 __be32 ref_tag;
3736 };
3737
3738 #define S_FW_TX_PI_HEADER_OP 8
3739 #define M_FW_TX_PI_HEADER_OP 0xff
3740 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP)
3741 #define G_FW_TX_PI_HEADER_OP(x) \
3742 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP)
3743
3744 #define S_FW_TX_PI_HEADER_ULPTXMORE 7
3745 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1
3746 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE)
3747 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \
3748 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE)
3749 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U)
3750
3751 #define S_FW_TX_PI_HEADER_PI_CONTROL 4
3752 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7
3753 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL)
3754 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \
3755 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL)
3756
3757 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2
3758 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1
3759 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE)
3760 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \
3761 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE)
3762 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U)
3763
3764 #define S_FW_TX_PI_HEADER_VALIDATE 1
3765 #define M_FW_TX_PI_HEADER_VALIDATE 0x1
3766 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE)
3767 #define G_FW_TX_PI_HEADER_VALIDATE(x) \
3768 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE)
3769 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U)
3770
3771 #define S_FW_TX_PI_HEADER_INLINE 0
3772 #define M_FW_TX_PI_HEADER_INLINE 0x1
3773 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE)
3774 #define G_FW_TX_PI_HEADER_INLINE(x) \
3775 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE)
3776 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U)
3777
3778 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7
3779 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1
3780 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \
3781 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL)
3782 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \
3783 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL)
3784 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U)
3785
3786 #define S_FW_TX_PI_HEADER_TAG_TYPE 5
3787 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3
3788 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE)
3789 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \
3790 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE)
3791
3792 #define S_FW_TX_PI_HEADER_PI_START4 22
3793 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff
3794 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4)
3795 #define G_FW_TX_PI_HEADER_PI_START4(x) \
3796 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4)
3797
3798 #define S_FW_TX_PI_HEADER_PI_END4 0
3799 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff
3800 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4)
3801 #define G_FW_TX_PI_HEADER_PI_END4(x) \
3802 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4)
3803
3804 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6
3805 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3
3806 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \
3807 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED)
3808 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \
3809 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \
3810 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED)
3811
3812 enum fw_pi_error_type {
3813 FW_PI_ERROR_GUARD_CHECK_FAILED = 0,
3814 };
3815
3816 struct fw_pi_error {
3817 __be32 err_type_pkd;
3818 __be32 flowid_len16;
3819 __be16 r2;
3820 __be16 app_tag;
3821 __be32 ref_tag;
3822 __be32 pisc[4];
3823 };
3824
3825 #define S_FW_PI_ERROR_ERR_TYPE 24
3826 #define M_FW_PI_ERROR_ERR_TYPE 0xff
3827 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE)
3828 #define G_FW_PI_ERROR_ERR_TYPE(x) \
3829 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE)
3830
3831 struct fw_tlstx_data_wr {
3832 __be32 op_to_immdlen;
3833 __be32 flowid_len16;
3834 __be32 plen;
3835 __be32 lsodisable_to_flags;
3836 __be32 r5;
3837 __be32 ctxloc_to_exp;
3838 __be16 mfs;
3839 __be16 adjustedplen_pkd;
3840 __be16 expinplenmax_pkd;
3841 __u8 pdusinplenmax_pkd;
3842 __u8 r10;
3843 };
3844
3845 #define S_FW_TLSTX_DATA_WR_OPCODE 24
3846 #define M_FW_TLSTX_DATA_WR_OPCODE 0xff
3847 #define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE)
3848 #define G_FW_TLSTX_DATA_WR_OPCODE(x) \
3849 (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE)
3850
3851 #define S_FW_TLSTX_DATA_WR_COMPL 21
3852 #define M_FW_TLSTX_DATA_WR_COMPL 0x1
3853 #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL)
3854 #define G_FW_TLSTX_DATA_WR_COMPL(x) \
3855 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL)
3856 #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U)
3857
3858 #define S_FW_TLSTX_DATA_WR_IMMDLEN 0
3859 #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff
3860 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN)
3861 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \
3862 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN)
3863
3864 #define S_FW_TLSTX_DATA_WR_FLOWID 8
3865 #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff
3866 #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID)
3867 #define G_FW_TLSTX_DATA_WR_FLOWID(x) \
3868 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID)
3869
3870 #define S_FW_TLSTX_DATA_WR_LEN16 0
3871 #define M_FW_TLSTX_DATA_WR_LEN16 0xff
3872 #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16)
3873 #define G_FW_TLSTX_DATA_WR_LEN16(x) \
3874 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16)
3875
3876 #define S_FW_TLSTX_DATA_WR_LSODISABLE 31
3877 #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1
3878 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \
3879 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE)
3880 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \
3881 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE)
3882 #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U)
3883
3884 #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30
3885 #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1
3886 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD)
3887 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \
3888 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD)
3889 #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U)
3890
3891 #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29
3892 #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1
3893 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
3894 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
3895 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
3896 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \
3897 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
3898 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U)
3899
3900 #define S_FW_TLSTX_DATA_WR_FLAGS 0
3901 #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff
3902 #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS)
3903 #define G_FW_TLSTX_DATA_WR_FLAGS(x) \
3904 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS)
3905
3906 #define S_FW_TLSTX_DATA_WR_CTXLOC 30
3907 #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3
3908 #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC)
3909 #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \
3910 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC)
3911
3912 #define S_FW_TLSTX_DATA_WR_IVDSGL 29
3913 #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1
3914 #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL)
3915 #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \
3916 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL)
3917 #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U)
3918
3919 #define S_FW_TLSTX_DATA_WR_KEYSIZE 24
3920 #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f
3921 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE)
3922 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \
3923 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE)
3924
3925 #define S_FW_TLSTX_DATA_WR_NUMIVS 14
3926 #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff
3927 #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS)
3928 #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \
3929 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS)
3930
3931 #define S_FW_TLSTX_DATA_WR_EXP 0
3932 #define M_FW_TLSTX_DATA_WR_EXP 0x3fff
3933 #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP)
3934 #define G_FW_TLSTX_DATA_WR_EXP(x) \
3935 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP)
3936
3937 #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1
3938 #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff
3939 #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
3940 ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
3941 #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
3942 (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \
3943 M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
3944
3945 #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4
3946 #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff
3947 #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
3948 ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX)
3949 #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
3950 (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \
3951 M_FW_TLSTX_DATA_WR_EXPINPLENMAX)
3952
3953 #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2
3954 #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f
3955 #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
3956 ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
3957 #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
3958 (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \
3959 M_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
3960
3961 struct fw_crypto_lookaside_wr {
3962 __be32 op_to_cctx_size;
3963 __be32 len16_pkd;
3964 __be32 session_id;
3965 __be32 rx_chid_to_rx_q_id;
3966 __be32 key_addr;
3967 __be32 pld_size_hash_size;
3968 __be64 cookie;
3969 };
3970
3971 #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24
3972 #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff
3973 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
3974 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
3975 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
3976 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \
3977 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
3978
3979 #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23
3980 #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1
3981 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
3982 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL)
3983 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
3984 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \
3985 M_FW_CRYPTO_LOOKASIDE_WR_COMPL)
3986 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U)
3987
3988 #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15
3989 #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff
3990 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
3991 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
3992 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
3993 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \
3994 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
3995
3996 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5
3997 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3
3998 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
3999 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
4000 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
4001 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \
4002 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
4003
4004 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0
4005 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f
4006 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
4007 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
4008 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
4009 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \
4010 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
4011
4012 #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0
4013 #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff
4014 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
4015 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16)
4016 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
4017 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \
4018 M_FW_CRYPTO_LOOKASIDE_WR_LEN16)
4019
4020 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29
4021 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3
4022 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
4023 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
4024 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
4025 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \
4026 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
4027
4028 #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27
4029 #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3
4030 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
4031 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB)
4032 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
4033 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB)
4034
4035 #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25
4036 #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3
4037 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
4038 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH)
4039 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
4040 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \
4041 M_FW_CRYPTO_LOOKASIDE_WR_PHASH)
4042
4043 #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23
4044 #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3
4045 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
4046 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV)
4047 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
4048 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV)
4049
4050 #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15
4051 #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff
4052 #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
4053 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
4054 #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
4055 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\
4056 M_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
4057
4058 #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10
4059 #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3
4060 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
4061 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
4062 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
4063 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \
4064 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
4065
4066 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0
4067 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff
4068 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
4069 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
4070 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
4071 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \
4072 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
4073
4074 #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24
4075 #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff
4076 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
4077 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
4078 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
4079 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \
4080 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
4081
4082 #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17
4083 #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f
4084 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
4085 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
4086 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
4087 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \
4088 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
4089
4090 struct fw_tls_tunnel_ofld_wr {
4091 __be32 op_compl;
4092 __be32 flowid_len16;
4093 __be32 plen;
4094 __be32 r4;
4095 };
4096
4097 /******************************************************************************
4098 * C O M M A N D s
4099 *********************/
4100
4101 /*
4102 * The maximum length of time, in miliseconds, that we expect any firmware
4103 * command to take to execute and return a reply to the host. The RESET
4104 * and INITIALIZE commands can take a fair amount of time to execute but
4105 * most execute in far less time than this maximum. This constant is used
4106 * by host software to determine how long to wait for a firmware command
4107 * reply before declaring the firmware as dead/unreachable ...
4108 */
4109 #define FW_CMD_MAX_TIMEOUT 10000
4110
4111 /*
4112 * If a host driver does a HELLO and discovers that there's already a MASTER
4113 * selected, we may have to wait for that MASTER to finish issuing RESET,
4114 * configuration and INITIALIZE commands. Also, there's a possibility that
4115 * our own HELLO may get lost if it happens right as the MASTER is issuign a
4116 * RESET command, so we need to be willing to make a few retries of our HELLO.
4117 */
4118 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
4119 #define FW_CMD_HELLO_RETRIES 3
4120
4121 enum fw_cmd_opcodes {
4122 FW_LDST_CMD = 0x01,
4123 FW_RESET_CMD = 0x03,
4124 FW_HELLO_CMD = 0x04,
4125 FW_BYE_CMD = 0x05,
4126 FW_INITIALIZE_CMD = 0x06,
4127 FW_CAPS_CONFIG_CMD = 0x07,
4128 FW_PARAMS_CMD = 0x08,
4129 FW_PFVF_CMD = 0x09,
4130 FW_IQ_CMD = 0x10,
4131 FW_EQ_MNGT_CMD = 0x11,
4132 FW_EQ_ETH_CMD = 0x12,
4133 FW_EQ_CTRL_CMD = 0x13,
4134 FW_EQ_OFLD_CMD = 0x21,
4135 FW_VI_CMD = 0x14,
4136 FW_VI_MAC_CMD = 0x15,
4137 FW_VI_RXMODE_CMD = 0x16,
4138 FW_VI_ENABLE_CMD = 0x17,
4139 FW_VI_STATS_CMD = 0x1a,
4140 FW_ACL_MAC_CMD = 0x18,
4141 FW_ACL_VLAN_CMD = 0x19,
4142 FW_PORT_CMD = 0x1b,
4143 FW_PORT_STATS_CMD = 0x1c,
4144 FW_PORT_LB_STATS_CMD = 0x1d,
4145 FW_PORT_TRACE_CMD = 0x1e,
4146 FW_PORT_TRACE_MMAP_CMD = 0x1f,
4147 FW_RSS_IND_TBL_CMD = 0x20,
4148 FW_RSS_GLB_CONFIG_CMD = 0x22,
4149 FW_RSS_VI_CONFIG_CMD = 0x23,
4150 FW_SCHED_CMD = 0x24,
4151 FW_DEVLOG_CMD = 0x25,
4152 FW_WATCHDOG_CMD = 0x27,
4153 FW_CLIP_CMD = 0x28,
4154 FW_CLIP2_CMD = 0x29,
4155 FW_CHNET_IFACE_CMD = 0x26,
4156 FW_FCOE_RES_INFO_CMD = 0x31,
4157 FW_FCOE_LINK_CMD = 0x32,
4158 FW_FCOE_VNP_CMD = 0x33,
4159 FW_FCOE_SPARAMS_CMD = 0x35,
4160 FW_FCOE_STATS_CMD = 0x37,
4161 FW_FCOE_FCF_CMD = 0x38,
4162 FW_DCB_IEEE_CMD = 0x3a,
4163 FW_DIAG_CMD = 0x3d,
4164 FW_PTP_CMD = 0x3e,
4165 FW_HMA_CMD = 0x3f,
4166 FW_LASTC2E_CMD = 0x40,
4167 FW_ERROR_CMD = 0x80,
4168 FW_DEBUG_CMD = 0x81,
4169 };
4170
4171 enum fw_cmd_cap {
4172 FW_CMD_CAP_PF = 0x01,
4173 FW_CMD_CAP_DMAQ = 0x02,
4174 FW_CMD_CAP_PORT = 0x04,
4175 FW_CMD_CAP_PORTPROMISC = 0x08,
4176 FW_CMD_CAP_PORTSTATS = 0x10,
4177 FW_CMD_CAP_VF = 0x80,
4178 };
4179
4180 /*
4181 * Generic command header flit0
4182 */
4183 struct fw_cmd_hdr {
4184 __be32 hi;
4185 __be32 lo;
4186 };
4187
4188 #define S_FW_CMD_OP 24
4189 #define M_FW_CMD_OP 0xff
4190 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
4191 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
4192
4193 #define S_FW_CMD_REQUEST 23
4194 #define M_FW_CMD_REQUEST 0x1
4195 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
4196 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
4197 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
4198
4199 #define S_FW_CMD_READ 22
4200 #define M_FW_CMD_READ 0x1
4201 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
4202 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
4203 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
4204
4205 #define S_FW_CMD_WRITE 21
4206 #define M_FW_CMD_WRITE 0x1
4207 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
4208 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
4209 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
4210
4211 #define S_FW_CMD_EXEC 20
4212 #define M_FW_CMD_EXEC 0x1
4213 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
4214 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
4215 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
4216
4217 #define S_FW_CMD_RAMASK 20
4218 #define M_FW_CMD_RAMASK 0xf
4219 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK)
4220 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK)
4221
4222 #define S_FW_CMD_RETVAL 8
4223 #define M_FW_CMD_RETVAL 0xff
4224 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
4225 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
4226
4227 #define S_FW_CMD_LEN16 0
4228 #define M_FW_CMD_LEN16 0xff
4229 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
4230 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
4231
4232 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
4233
4234 /*
4235 * address spaces
4236 */
4237 enum fw_ldst_addrspc {
4238 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
4239 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
4240 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
4241 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
4242 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
4243 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
4244 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
4245 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
4246 FW_LDST_ADDRSPC_MDIO = 0x0018,
4247 FW_LDST_ADDRSPC_MPS = 0x0020,
4248 FW_LDST_ADDRSPC_FUNC = 0x0028,
4249 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
4250 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */
4251 FW_LDST_ADDRSPC_LE = 0x0030,
4252 FW_LDST_ADDRSPC_I2C = 0x0038,
4253 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040,
4254 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041,
4255 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042,
4256 FW_LDST_ADDRSPC_CIM_Q = 0x0048,
4257 };
4258
4259 /*
4260 * MDIO VSC8634 register access control field
4261 */
4262 enum fw_ldst_mdio_vsc8634_aid {
4263 FW_LDST_MDIO_VS_STANDARD,
4264 FW_LDST_MDIO_VS_EXTENDED,
4265 FW_LDST_MDIO_VS_GPIO
4266 };
4267
4268 enum fw_ldst_mps_fid {
4269 FW_LDST_MPS_ATRB,
4270 FW_LDST_MPS_RPLC
4271 };
4272
4273 enum fw_ldst_func_access_ctl {
4274 FW_LDST_FUNC_ACC_CTL_VIID,
4275 FW_LDST_FUNC_ACC_CTL_FID
4276 };
4277
4278 enum fw_ldst_func_mod_index {
4279 FW_LDST_FUNC_MPS
4280 };
4281
4282 struct fw_ldst_cmd {
4283 __be32 op_to_addrspace;
4284 __be32 cycles_to_len16;
4285 union fw_ldst {
4286 struct fw_ldst_addrval {
4287 __be32 addr;
4288 __be32 val;
4289 } addrval;
4290 struct fw_ldst_idctxt {
4291 __be32 physid;
4292 __be32 msg_ctxtflush;
4293 __be32 ctxt_data7;
4294 __be32 ctxt_data6;
4295 __be32 ctxt_data5;
4296 __be32 ctxt_data4;
4297 __be32 ctxt_data3;
4298 __be32 ctxt_data2;
4299 __be32 ctxt_data1;
4300 __be32 ctxt_data0;
4301 } idctxt;
4302 struct fw_ldst_mdio {
4303 __be16 paddr_mmd;
4304 __be16 raddr;
4305 __be16 vctl;
4306 __be16 rval;
4307 } mdio;
4308 struct fw_ldst_cim_rq {
4309 __u8 req_first64[8];
4310 __u8 req_second64[8];
4311 __u8 resp_first64[8];
4312 __u8 resp_second64[8];
4313 __be32 r3[2];
4314 } cim_rq;
4315 union fw_ldst_mps {
4316 struct fw_ldst_mps_rplc {
4317 __be16 fid_idx;
4318 __be16 rplcpf_pkd;
4319 __be32 rplc255_224;
4320 __be32 rplc223_192;
4321 __be32 rplc191_160;
4322 __be32 rplc159_128;
4323 __be32 rplc127_96;
4324 __be32 rplc95_64;
4325 __be32 rplc63_32;
4326 __be32 rplc31_0;
4327 } rplc;
4328 struct fw_ldst_mps_atrb {
4329 __be16 fid_mpsid;
4330 __be16 r2[3];
4331 __be32 r3[2];
4332 __be32 r4;
4333 __be32 atrb;
4334 __be16 vlan[16];
4335 } atrb;
4336 } mps;
4337 struct fw_ldst_func {
4338 __u8 access_ctl;
4339 __u8 mod_index;
4340 __be16 ctl_id;
4341 __be32 offset;
4342 __be64 data0;
4343 __be64 data1;
4344 } func;
4345 struct fw_ldst_pcie {
4346 __u8 ctrl_to_fn;
4347 __u8 bnum;
4348 __u8 r;
4349 __u8 ext_r;
4350 __u8 select_naccess;
4351 __u8 pcie_fn;
4352 __be16 nset_pkd;
4353 __be32 data[12];
4354 } pcie;
4355 struct fw_ldst_i2c_deprecated {
4356 __u8 pid_pkd;
4357 __u8 base;
4358 __u8 boffset;
4359 __u8 data;
4360 __be32 r9;
4361 } i2c_deprecated;
4362 struct fw_ldst_i2c {
4363 __u8 pid;
4364 __u8 did;
4365 __u8 boffset;
4366 __u8 blen;
4367 __be32 r9;
4368 __u8 data[48];
4369 } i2c;
4370 struct fw_ldst_le {
4371 __be32 index;
4372 __be32 r9;
4373 __u8 val[33];
4374 __u8 r11[7];
4375 } le;
4376 } u;
4377 };
4378
4379 #define S_FW_LDST_CMD_ADDRSPACE 0
4380 #define M_FW_LDST_CMD_ADDRSPACE 0xff
4381 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
4382 #define G_FW_LDST_CMD_ADDRSPACE(x) \
4383 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE)
4384
4385 #define S_FW_LDST_CMD_CYCLES 16
4386 #define M_FW_LDST_CMD_CYCLES 0xffff
4387 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES)
4388 #define G_FW_LDST_CMD_CYCLES(x) \
4389 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES)
4390
4391 #define S_FW_LDST_CMD_MSG 31
4392 #define M_FW_LDST_CMD_MSG 0x1
4393 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG)
4394 #define G_FW_LDST_CMD_MSG(x) \
4395 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG)
4396 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U)
4397
4398 #define S_FW_LDST_CMD_CTXTFLUSH 30
4399 #define M_FW_LDST_CMD_CTXTFLUSH 0x1
4400 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH)
4401 #define G_FW_LDST_CMD_CTXTFLUSH(x) \
4402 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH)
4403 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U)
4404
4405 #define S_FW_LDST_CMD_PADDR 8
4406 #define M_FW_LDST_CMD_PADDR 0x1f
4407 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR)
4408 #define G_FW_LDST_CMD_PADDR(x) \
4409 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR)
4410
4411 #define S_FW_LDST_CMD_MMD 0
4412 #define M_FW_LDST_CMD_MMD 0x1f
4413 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD)
4414 #define G_FW_LDST_CMD_MMD(x) \
4415 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD)
4416
4417 #define S_FW_LDST_CMD_FID 15
4418 #define M_FW_LDST_CMD_FID 0x1
4419 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID)
4420 #define G_FW_LDST_CMD_FID(x) \
4421 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID)
4422 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U)
4423
4424 #define S_FW_LDST_CMD_IDX 0
4425 #define M_FW_LDST_CMD_IDX 0x7fff
4426 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX)
4427 #define G_FW_LDST_CMD_IDX(x) \
4428 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX)
4429
4430 #define S_FW_LDST_CMD_RPLCPF 0
4431 #define M_FW_LDST_CMD_RPLCPF 0xff
4432 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF)
4433 #define G_FW_LDST_CMD_RPLCPF(x) \
4434 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF)
4435
4436 #define S_FW_LDST_CMD_MPSID 0
4437 #define M_FW_LDST_CMD_MPSID 0x7fff
4438 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID)
4439 #define G_FW_LDST_CMD_MPSID(x) \
4440 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID)
4441
4442 #define S_FW_LDST_CMD_CTRL 7
4443 #define M_FW_LDST_CMD_CTRL 0x1
4444 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL)
4445 #define G_FW_LDST_CMD_CTRL(x) \
4446 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL)
4447 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U)
4448
4449 #define S_FW_LDST_CMD_LC 4
4450 #define M_FW_LDST_CMD_LC 0x1
4451 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC)
4452 #define G_FW_LDST_CMD_LC(x) \
4453 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC)
4454 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U)
4455
4456 #define S_FW_LDST_CMD_AI 3
4457 #define M_FW_LDST_CMD_AI 0x1
4458 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI)
4459 #define G_FW_LDST_CMD_AI(x) \
4460 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI)
4461 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U)
4462
4463 #define S_FW_LDST_CMD_FN 0
4464 #define M_FW_LDST_CMD_FN 0x7
4465 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN)
4466 #define G_FW_LDST_CMD_FN(x) \
4467 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN)
4468
4469 #define S_FW_LDST_CMD_SELECT 4
4470 #define M_FW_LDST_CMD_SELECT 0xf
4471 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT)
4472 #define G_FW_LDST_CMD_SELECT(x) \
4473 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT)
4474
4475 #define S_FW_LDST_CMD_NACCESS 0
4476 #define M_FW_LDST_CMD_NACCESS 0xf
4477 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS)
4478 #define G_FW_LDST_CMD_NACCESS(x) \
4479 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS)
4480
4481 #define S_FW_LDST_CMD_NSET 14
4482 #define M_FW_LDST_CMD_NSET 0x3
4483 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET)
4484 #define G_FW_LDST_CMD_NSET(x) \
4485 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET)
4486
4487 #define S_FW_LDST_CMD_PID 6
4488 #define M_FW_LDST_CMD_PID 0x3
4489 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID)
4490 #define G_FW_LDST_CMD_PID(x) \
4491 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID)
4492
4493 struct fw_reset_cmd {
4494 __be32 op_to_write;
4495 __be32 retval_len16;
4496 __be32 val;
4497 __be32 halt_pkd;
4498 };
4499
4500 #define S_FW_RESET_CMD_HALT 31
4501 #define M_FW_RESET_CMD_HALT 0x1
4502 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
4503 #define G_FW_RESET_CMD_HALT(x) \
4504 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
4505 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
4506
4507 enum {
4508 FW_HELLO_CMD_STAGE_OS = 0,
4509 FW_HELLO_CMD_STAGE_PREOS0 = 1,
4510 FW_HELLO_CMD_STAGE_PREOS1 = 2,
4511 FW_HELLO_CMD_STAGE_POSTOS = 3,
4512 };
4513
4514 struct fw_hello_cmd {
4515 __be32 op_to_write;
4516 __be32 retval_len16;
4517 __be32 err_to_clearinit;
4518 __be32 fwrev;
4519 };
4520
4521 #define S_FW_HELLO_CMD_ERR 31
4522 #define M_FW_HELLO_CMD_ERR 0x1
4523 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
4524 #define G_FW_HELLO_CMD_ERR(x) \
4525 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
4526 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
4527
4528 #define S_FW_HELLO_CMD_INIT 30
4529 #define M_FW_HELLO_CMD_INIT 0x1
4530 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
4531 #define G_FW_HELLO_CMD_INIT(x) \
4532 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
4533 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
4534
4535 #define S_FW_HELLO_CMD_MASTERDIS 29
4536 #define M_FW_HELLO_CMD_MASTERDIS 0x1
4537 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
4538 #define G_FW_HELLO_CMD_MASTERDIS(x) \
4539 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
4540 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
4541
4542 #define S_FW_HELLO_CMD_MASTERFORCE 28
4543 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
4544 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
4545 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
4546 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
4547 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
4548
4549 #define S_FW_HELLO_CMD_MBMASTER 24
4550 #define M_FW_HELLO_CMD_MBMASTER 0xf
4551 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
4552 #define G_FW_HELLO_CMD_MBMASTER(x) \
4553 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
4554
4555 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23
4556 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1
4557 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT)
4558 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \
4559 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT)
4560 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U)
4561
4562 #define S_FW_HELLO_CMD_MBASYNCNOT 20
4563 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
4564 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
4565 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
4566 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
4567
4568 #define S_FW_HELLO_CMD_STAGE 17
4569 #define M_FW_HELLO_CMD_STAGE 0x7
4570 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
4571 #define G_FW_HELLO_CMD_STAGE(x) \
4572 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
4573
4574 #define S_FW_HELLO_CMD_CLEARINIT 16
4575 #define M_FW_HELLO_CMD_CLEARINIT 0x1
4576 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
4577 #define G_FW_HELLO_CMD_CLEARINIT(x) \
4578 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
4579 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
4580
4581 struct fw_bye_cmd {
4582 __be32 op_to_write;
4583 __be32 retval_len16;
4584 __be64 r3;
4585 };
4586
4587 struct fw_initialize_cmd {
4588 __be32 op_to_write;
4589 __be32 retval_len16;
4590 __be64 r3;
4591 };
4592
4593 enum fw_caps_config_hm {
4594 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
4595 FW_CAPS_CONFIG_HM_PL = 0x00000002,
4596 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
4597 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
4598 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
4599 FW_CAPS_CONFIG_HM_TP = 0x00000020,
4600 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
4601 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
4602 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
4603 FW_CAPS_CONFIG_HM_MC = 0x00000200,
4604 FW_CAPS_CONFIG_HM_LE = 0x00000400,
4605 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
4606 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
4607 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
4608 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
4609 FW_CAPS_CONFIG_HM_MI = 0x00008000,
4610 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
4611 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
4612 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
4613 FW_CAPS_CONFIG_HM_MA = 0x00080000,
4614 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
4615 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
4616 FW_CAPS_CONFIG_HM_UART = 0x00400000,
4617 FW_CAPS_CONFIG_HM_SF = 0x00800000,
4618 };
4619
4620 /*
4621 * The VF Register Map.
4622 *
4623 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local
4624 * bus module (PL) and CPU Interface Module (CIM) components are mapped via
4625 * the Slice to Module Map Table (see below) in the Physical Function Register
4626 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
4627 * and Offset registers in the PF Register Map. The MBDATA base address is
4628 * quite constrained as it determines the Mailbox Data addresses for both PFs
4629 * and VFs, and therefore must fit in both the VF and PF Register Maps without
4630 * overlapping other registers.
4631 */
4632 #define FW_T4VF_SGE_BASE_ADDR 0x0000
4633 #define FW_T4VF_MPS_BASE_ADDR 0x0100
4634 #define FW_T4VF_PL_BASE_ADDR 0x0200
4635 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
4636 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */
4637 #define FW_T4VF_CIM_BASE_ADDR 0x0300
4638
4639 #define FW_T4VF_REGMAP_START 0x0000
4640 #define FW_T4VF_REGMAP_SIZE 0x0400
4641
4642 enum fw_caps_config_nbm {
4643 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
4644 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
4645 };
4646
4647 enum fw_caps_config_link {
4648 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
4649 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
4650 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
4651 };
4652
4653 enum fw_caps_config_switch {
4654 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
4655 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
4656 };
4657
4658 enum fw_caps_config_nic {
4659 FW_CAPS_CONFIG_NIC = 0x00000001,
4660 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
4661 FW_CAPS_CONFIG_NIC_IDS = 0x00000004,
4662 FW_CAPS_CONFIG_NIC_UM = 0x00000008,
4663 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010,
4664 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
4665 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
4666 };
4667
4668 enum fw_caps_config_toe {
4669 FW_CAPS_CONFIG_TOE = 0x00000001,
4670 };
4671
4672 enum fw_caps_config_rdma {
4673 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
4674 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
4675 };
4676
4677 enum fw_caps_config_iscsi {
4678 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
4679 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
4680 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
4681 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
4682 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010,
4683 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020,
4684 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040,
4685 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080,
4686 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100,
4687 };
4688
4689 enum fw_caps_config_crypto {
4690 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
4691 FW_CAPS_CONFIG_TLSKEYS = 0x00000002,
4692 FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004,
4693 FW_CAPS_CONFIG_TLS_HW = 0x00000008,
4694 };
4695
4696 enum fw_caps_config_fcoe {
4697 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
4698 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
4699 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
4700 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008,
4701 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010,
4702 };
4703
4704 enum fw_memtype_cf {
4705 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0,
4706 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1,
4707 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM,
4708 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
4709 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL,
4710 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1,
4711 };
4712
4713 struct fw_caps_config_cmd {
4714 __be32 op_to_write;
4715 __be32 cfvalid_to_len16;
4716 __be32 r2;
4717 __be32 hwmbitmap;
4718 __be16 nbmcaps;
4719 __be16 linkcaps;
4720 __be16 switchcaps;
4721 __be16 r3;
4722 __be16 niccaps;
4723 __be16 toecaps;
4724 __be16 rdmacaps;
4725 __be16 cryptocaps;
4726 __be16 iscsicaps;
4727 __be16 fcoecaps;
4728 __be32 cfcsum;
4729 __be32 finiver;
4730 __be32 finicsum;
4731 };
4732
4733 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
4734 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
4735 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
4736 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
4737 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
4738 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
4739
4740 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
4741 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
4742 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
4743 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
4744 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
4745 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
4746 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
4747
4748 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
4749 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
4750 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
4751 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
4752 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
4753 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
4754 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
4755
4756 /*
4757 * params command mnemonics
4758 */
4759 enum fw_params_mnem {
4760 FW_PARAMS_MNEM_DEV = 1, /* device params */
4761 FW_PARAMS_MNEM_PFVF = 2, /* function params */
4762 FW_PARAMS_MNEM_REG = 3, /* limited register access */
4763 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
4764 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */
4765 FW_PARAMS_MNEM_LAST
4766 };
4767
4768 /*
4769 * device parameters
4770 */
4771 #define S_FW_PARAMS_PARAM_FILTER_MODE 16
4772 #define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff
4773 #define V_FW_PARAMS_PARAM_FILTER_MODE(x) \
4774 ((x) << S_FW_PARAMS_PARAM_FILTER_MODE)
4775 #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \
4776 (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \
4777 M_FW_PARAMS_PARAM_FILTER_MODE)
4778
4779 #define S_FW_PARAMS_PARAM_FILTER_MASK 0
4780 #define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff
4781 #define V_FW_PARAMS_PARAM_FILTER_MASK(x) \
4782 ((x) << S_FW_PARAMS_PARAM_FILTER_MASK)
4783 #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \
4784 (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \
4785 M_FW_PARAMS_PARAM_FILTER_MASK)
4786
4787 enum fw_params_param_dev {
4788 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
4789 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
4790 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
4791 * allocated by the device's
4792 * Lookup Engine
4793 */
4794 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
4795 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04,
4796 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05,
4797 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06,
4798 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07,
4799 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08,
4800 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09,
4801 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A,
4802 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
4803 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
4804 FW_PARAMS_PARAM_DEV_CF = 0x0D,
4805 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E,
4806 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
4807 FW_PARAMS_PARAM_DEV_LOAD = 0x10,
4808 FW_PARAMS_PARAM_DEV_DIAG = 0x11,
4809 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */
4810 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD
4811 */
4812 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD
4813 */
4814 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15,
4815 FW_PARAMS_PARAM_DEV_MCINIT = 0x16,
4816 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
4817 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
4818 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19,
4819 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
4820 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
4821 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C,
4822 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
4823
4824 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E,
4825 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F,
4826 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20,
4827 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
4828 FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22,
4829 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23,
4830 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24,
4831 FW_PARAMS_PARAM_DEV_ADD_SMAC = 0x25,
4832 FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26,
4833 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
4834 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28,
4835 FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29,
4836 FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A,
4837 FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B,
4838 FW_PARAMS_PARAM_DEV_VF_TRVLAN = 0x2C,
4839 FW_PARAMS_PARAM_DEV_TCB_CACHE_FLUSH = 0x2D,
4840 FW_PARAMS_PARAM_DEV_FILTER = 0x2E,
4841 FW_PARAMS_PARAM_DEV_CLIP2_CMD = 0x2F,
4842 FW_PARAMS_PARAM_DEV_DEV_512SGL_MR = 0x30,
4843 FW_PARAMS_PARAM_DEV_KTLS_HW = 0x31,
4844 FW_PARAMS_PARAM_DEV_VI_ENABLE_INGRESS_AFTER_LINKUP = 0x32,
4845 };
4846
4847 /*
4848 * dev bypass parameters; actions and modes
4849 */
4850 enum fw_params_param_dev_bypass {
4851
4852 /* actions
4853 */
4854 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00,
4855 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01,
4856
4857 /* modes
4858 */
4859 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00,
4860 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1,
4861 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,
4862 };
4863
4864 enum fw_params_param_dev_phyfw {
4865 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
4866 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
4867 };
4868
4869 enum fw_params_param_dev_diag {
4870 FW_PARAM_DEV_DIAG_TMP = 0x00,
4871 FW_PARAM_DEV_DIAG_VDD = 0x01,
4872 FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02,
4873 FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR = 0x03,
4874 };
4875
4876 enum fw_params_param_dev_filter{
4877 FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00,
4878 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01,
4879 };
4880
4881 enum fw_filter_vnic_mode {
4882 FW_VNIC_MODE_PF_VF = 0,
4883 FW_VNIC_MODE_OUTER_VLAN = 1,
4884 FW_VNIC_MODE_ENCAP_EN = 2,
4885 };
4886
4887 enum fw_params_param_dev_ktls_hw {
4888 FW_PARAMS_PARAM_DEV_KTLS_HW_DISABLE = 0x00,
4889 FW_PARAMS_PARAM_DEV_KTLS_HW_ENABLE = 0x01,
4890 FW_PARAMS_PARAM_DEV_KTLS_HW_USER_DISABLE = 0x00,
4891 FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE = 0x01,
4892 };
4893
4894 enum fw_params_param_dev_fwcache {
4895 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00,
4896 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01,
4897 };
4898
4899 /*
4900 * physical and virtual function parameters
4901 */
4902 enum fw_params_param_pfvf {
4903 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
4904 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
4905 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
4906 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
4907 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
4908 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
4909 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
4910 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
4911 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
4912 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
4913 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
4914 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
4915 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
4916 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
4917 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
4918 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
4919 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
4920 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
4921 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
4922 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
4923 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
4924 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
4925 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
4926 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
4927 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
4928 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19,
4929 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A,
4930 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
4931 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
4932 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
4933 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
4934 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
4935 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
4936 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
4937 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
4938 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
4939 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
4940 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
4941 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
4942 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
4943 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
4944 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
4945 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
4946 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
4947 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
4948 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
4949 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
4950 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
4951 FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38,
4952 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
4953 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
4954 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B,
4955 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C,
4956 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,
4957 FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E,
4958 FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F,
4959 FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40,
4960 };
4961
4962 /*
4963 * virtual link state as seen by the specified VF
4964 */
4965 enum vf_link_states {
4966 VF_LINK_STATE_AUTO = 0x00,
4967 VF_LINK_STATE_ENABLE = 0x01,
4968 VF_LINK_STATE_DISABLE = 0x02,
4969 };
4970
4971 /*
4972 * dma queue parameters
4973 */
4974 enum fw_params_param_dmaq {
4975 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
4976 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
4977 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02,
4978 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03,
4979 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
4980 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
4981 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
4982 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
4983 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14,
4984 FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15,
4985 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
4986 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30
4987 };
4988
4989 /*
4990 * chnet parameters
4991 */
4992 enum fw_params_param_chnet {
4993 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00,
4994 };
4995
4996 enum fw_params_param_chnet_flags {
4997 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1,
4998 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2,
4999 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4,
5000 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6_SLAAC = 0x8,
5001 };
5002
5003 #define S_FW_PARAMS_MNEM 24
5004 #define M_FW_PARAMS_MNEM 0xff
5005 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
5006 #define G_FW_PARAMS_MNEM(x) \
5007 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
5008
5009 #define S_FW_PARAMS_PARAM_X 16
5010 #define M_FW_PARAMS_PARAM_X 0xff
5011 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
5012 #define G_FW_PARAMS_PARAM_X(x) \
5013 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
5014
5015 #define S_FW_PARAMS_PARAM_Y 8
5016 #define M_FW_PARAMS_PARAM_Y 0xff
5017 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
5018 #define G_FW_PARAMS_PARAM_Y(x) \
5019 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
5020
5021 #define S_FW_PARAMS_PARAM_Z 0
5022 #define M_FW_PARAMS_PARAM_Z 0xff
5023 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
5024 #define G_FW_PARAMS_PARAM_Z(x) \
5025 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
5026
5027 #define S_FW_PARAMS_PARAM_XYZ 0
5028 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
5029 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
5030 #define G_FW_PARAMS_PARAM_XYZ(x) \
5031 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ)
5032
5033 #define S_FW_PARAMS_PARAM_YZ 0
5034 #define M_FW_PARAMS_PARAM_YZ 0xffff
5035 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
5036 #define G_FW_PARAMS_PARAM_YZ(x) \
5037 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
5038
5039 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31
5040 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1
5041 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
5042 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
5043 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
5044 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \
5045 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
5046
5047 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24
5048 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3
5049 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
5050 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
5051 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
5052 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \
5053 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
5054
5055 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0
5056 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff
5057 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
5058 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST)
5059 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
5060 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST)
5061
5062 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29
5063 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7
5064 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \
5065 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)
5066 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \
5067 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \
5068 M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)
5069
5070 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0
5071 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff
5072 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \
5073 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)
5074 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \
5075 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \
5076 M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)
5077
5078 struct fw_params_cmd {
5079 __be32 op_to_vfn;
5080 __be32 retval_len16;
5081 struct fw_params_param {
5082 __be32 mnem;
5083 __be32 val;
5084 } param[7];
5085 };
5086
5087 #define S_FW_PARAMS_CMD_PFN 8
5088 #define M_FW_PARAMS_CMD_PFN 0x7
5089 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
5090 #define G_FW_PARAMS_CMD_PFN(x) \
5091 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
5092
5093 #define S_FW_PARAMS_CMD_VFN 0
5094 #define M_FW_PARAMS_CMD_VFN 0xff
5095 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
5096 #define G_FW_PARAMS_CMD_VFN(x) \
5097 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
5098
5099 struct fw_pfvf_cmd {
5100 __be32 op_to_vfn;
5101 __be32 retval_len16;
5102 __be32 niqflint_niq;
5103 __be32 type_to_neq;
5104 __be32 tc_to_nexactf;
5105 __be32 r_caps_to_nethctrl;
5106 __be16 nricq;
5107 __be16 nriqp;
5108 __be32 r4;
5109 };
5110
5111 #define S_FW_PFVF_CMD_PFN 8
5112 #define M_FW_PFVF_CMD_PFN 0x7
5113 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN)
5114 #define G_FW_PFVF_CMD_PFN(x) \
5115 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN)
5116
5117 #define S_FW_PFVF_CMD_VFN 0
5118 #define M_FW_PFVF_CMD_VFN 0xff
5119 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN)
5120 #define G_FW_PFVF_CMD_VFN(x) \
5121 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN)
5122
5123 #define S_FW_PFVF_CMD_NIQFLINT 20
5124 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
5125 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT)
5126 #define G_FW_PFVF_CMD_NIQFLINT(x) \
5127 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
5128
5129 #define S_FW_PFVF_CMD_NIQ 0
5130 #define M_FW_PFVF_CMD_NIQ 0xfffff
5131 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ)
5132 #define G_FW_PFVF_CMD_NIQ(x) \
5133 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
5134
5135 #define S_FW_PFVF_CMD_TYPE 31
5136 #define M_FW_PFVF_CMD_TYPE 0x1
5137 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE)
5138 #define G_FW_PFVF_CMD_TYPE(x) \
5139 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE)
5140 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U)
5141
5142 #define S_FW_PFVF_CMD_CMASK 24
5143 #define M_FW_PFVF_CMD_CMASK 0xf
5144 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK)
5145 #define G_FW_PFVF_CMD_CMASK(x) \
5146 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK)
5147
5148 #define S_FW_PFVF_CMD_PMASK 20
5149 #define M_FW_PFVF_CMD_PMASK 0xf
5150 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK)
5151 #define G_FW_PFVF_CMD_PMASK(x) \
5152 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
5153
5154 #define S_FW_PFVF_CMD_NEQ 0
5155 #define M_FW_PFVF_CMD_NEQ 0xfffff
5156 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ)
5157 #define G_FW_PFVF_CMD_NEQ(x) \
5158 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
5159
5160 #define S_FW_PFVF_CMD_TC 24
5161 #define M_FW_PFVF_CMD_TC 0xff
5162 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC)
5163 #define G_FW_PFVF_CMD_TC(x) \
5164 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
5165
5166 #define S_FW_PFVF_CMD_NVI 16
5167 #define M_FW_PFVF_CMD_NVI 0xff
5168 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI)
5169 #define G_FW_PFVF_CMD_NVI(x) \
5170 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
5171
5172 #define S_FW_PFVF_CMD_NEXACTF 0
5173 #define M_FW_PFVF_CMD_NEXACTF 0xffff
5174 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF)
5175 #define G_FW_PFVF_CMD_NEXACTF(x) \
5176 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
5177
5178 #define S_FW_PFVF_CMD_R_CAPS 24
5179 #define M_FW_PFVF_CMD_R_CAPS 0xff
5180 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS)
5181 #define G_FW_PFVF_CMD_R_CAPS(x) \
5182 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
5183
5184 #define S_FW_PFVF_CMD_WX_CAPS 16
5185 #define M_FW_PFVF_CMD_WX_CAPS 0xff
5186 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS)
5187 #define G_FW_PFVF_CMD_WX_CAPS(x) \
5188 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
5189
5190 #define S_FW_PFVF_CMD_NETHCTRL 0
5191 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
5192 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL)
5193 #define G_FW_PFVF_CMD_NETHCTRL(x) \
5194 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
5195
5196 /*
5197 * ingress queue type; the first 1K ingress queues can have associated 0,
5198 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
5199 * capabilities
5200 */
5201 enum fw_iq_type {
5202 FW_IQ_TYPE_FL_INT_CAP,
5203 FW_IQ_TYPE_NO_FL_INT_CAP,
5204 FW_IQ_TYPE_VF_CQ
5205 };
5206
5207 enum fw_iq_iqtype {
5208 FW_IQ_IQTYPE_OTHER,
5209 FW_IQ_IQTYPE_NIC,
5210 FW_IQ_IQTYPE_OFLD,
5211 };
5212
5213 struct fw_iq_cmd {
5214 __be32 op_to_vfn;
5215 __be32 alloc_to_len16;
5216 __be16 physiqid;
5217 __be16 iqid;
5218 __be16 fl0id;
5219 __be16 fl1id;
5220 __be32 type_to_iqandstindex;
5221 __be16 iqdroprss_to_iqesize;
5222 __be16 iqsize;
5223 __be64 iqaddr;
5224 __be32 iqns_to_fl0congen;
5225 __be16 fl0dcaen_to_fl0cidxfthresh;
5226 __be16 fl0size;
5227 __be64 fl0addr;
5228 __be32 fl1cngchmap_to_fl1congen;
5229 __be16 fl1dcaen_to_fl1cidxfthresh;
5230 __be16 fl1size;
5231 __be64 fl1addr;
5232 };
5233
5234 #define S_FW_IQ_CMD_PFN 8
5235 #define M_FW_IQ_CMD_PFN 0x7
5236 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
5237 #define G_FW_IQ_CMD_PFN(x) \
5238 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
5239
5240 #define S_FW_IQ_CMD_VFN 0
5241 #define M_FW_IQ_CMD_VFN 0xff
5242 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
5243 #define G_FW_IQ_CMD_VFN(x) \
5244 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
5245
5246 #define S_FW_IQ_CMD_ALLOC 31
5247 #define M_FW_IQ_CMD_ALLOC 0x1
5248 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
5249 #define G_FW_IQ_CMD_ALLOC(x) \
5250 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
5251 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
5252
5253 #define S_FW_IQ_CMD_FREE 30
5254 #define M_FW_IQ_CMD_FREE 0x1
5255 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
5256 #define G_FW_IQ_CMD_FREE(x) \
5257 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
5258 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
5259
5260 #define S_FW_IQ_CMD_MODIFY 29
5261 #define M_FW_IQ_CMD_MODIFY 0x1
5262 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY)
5263 #define G_FW_IQ_CMD_MODIFY(x) \
5264 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY)
5265 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U)
5266
5267 #define S_FW_IQ_CMD_IQSTART 28
5268 #define M_FW_IQ_CMD_IQSTART 0x1
5269 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
5270 #define G_FW_IQ_CMD_IQSTART(x) \
5271 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
5272 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
5273
5274 #define S_FW_IQ_CMD_IQSTOP 27
5275 #define M_FW_IQ_CMD_IQSTOP 0x1
5276 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
5277 #define G_FW_IQ_CMD_IQSTOP(x) \
5278 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
5279 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
5280
5281 #define S_FW_IQ_CMD_TYPE 29
5282 #define M_FW_IQ_CMD_TYPE 0x7
5283 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
5284 #define G_FW_IQ_CMD_TYPE(x) \
5285 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
5286
5287 #define S_FW_IQ_CMD_IQASYNCH 28
5288 #define M_FW_IQ_CMD_IQASYNCH 0x1
5289 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
5290 #define G_FW_IQ_CMD_IQASYNCH(x) \
5291 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
5292 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
5293
5294 #define S_FW_IQ_CMD_VIID 16
5295 #define M_FW_IQ_CMD_VIID 0xfff
5296 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
5297 #define G_FW_IQ_CMD_VIID(x) \
5298 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
5299
5300 #define S_FW_IQ_CMD_IQANDST 15
5301 #define M_FW_IQ_CMD_IQANDST 0x1
5302 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
5303 #define G_FW_IQ_CMD_IQANDST(x) \
5304 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
5305 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
5306
5307 #define S_FW_IQ_CMD_IQANUS 14
5308 #define M_FW_IQ_CMD_IQANUS 0x1
5309 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS)
5310 #define G_FW_IQ_CMD_IQANUS(x) \
5311 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS)
5312 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U)
5313
5314 #define S_FW_IQ_CMD_IQANUD 12
5315 #define M_FW_IQ_CMD_IQANUD 0x3
5316 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
5317 #define G_FW_IQ_CMD_IQANUD(x) \
5318 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
5319
5320 #define S_FW_IQ_CMD_IQANDSTINDEX 0
5321 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
5322 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
5323 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
5324 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
5325
5326 #define S_FW_IQ_CMD_IQDROPRSS 15
5327 #define M_FW_IQ_CMD_IQDROPRSS 0x1
5328 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS)
5329 #define G_FW_IQ_CMD_IQDROPRSS(x) \
5330 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS)
5331 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U)
5332
5333 #define S_FW_IQ_CMD_IQGTSMODE 14
5334 #define M_FW_IQ_CMD_IQGTSMODE 0x1
5335 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
5336 #define G_FW_IQ_CMD_IQGTSMODE(x) \
5337 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
5338 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
5339
5340 #define S_FW_IQ_CMD_IQPCIECH 12
5341 #define M_FW_IQ_CMD_IQPCIECH 0x3
5342 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
5343 #define G_FW_IQ_CMD_IQPCIECH(x) \
5344 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
5345
5346 #define S_FW_IQ_CMD_IQDCAEN 11
5347 #define M_FW_IQ_CMD_IQDCAEN 0x1
5348 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN)
5349 #define G_FW_IQ_CMD_IQDCAEN(x) \
5350 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN)
5351 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U)
5352
5353 #define S_FW_IQ_CMD_IQDCACPU 6
5354 #define M_FW_IQ_CMD_IQDCACPU 0x1f
5355 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU)
5356 #define G_FW_IQ_CMD_IQDCACPU(x) \
5357 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU)
5358
5359 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
5360 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
5361 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
5362 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
5363 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
5364
5365 #define S_FW_IQ_CMD_IQO 3
5366 #define M_FW_IQ_CMD_IQO 0x1
5367 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO)
5368 #define G_FW_IQ_CMD_IQO(x) \
5369 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO)
5370 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U)
5371
5372 #define S_FW_IQ_CMD_IQCPRIO 2
5373 #define M_FW_IQ_CMD_IQCPRIO 0x1
5374 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO)
5375 #define G_FW_IQ_CMD_IQCPRIO(x) \
5376 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO)
5377 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U)
5378
5379 #define S_FW_IQ_CMD_IQESIZE 0
5380 #define M_FW_IQ_CMD_IQESIZE 0x3
5381 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
5382 #define G_FW_IQ_CMD_IQESIZE(x) \
5383 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
5384
5385 #define S_FW_IQ_CMD_IQNS 31
5386 #define M_FW_IQ_CMD_IQNS 0x1
5387 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS)
5388 #define G_FW_IQ_CMD_IQNS(x) \
5389 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS)
5390 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U)
5391
5392 #define S_FW_IQ_CMD_IQRO 30
5393 #define M_FW_IQ_CMD_IQRO 0x1
5394 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
5395 #define G_FW_IQ_CMD_IQRO(x) \
5396 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
5397 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
5398
5399 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28
5400 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3
5401 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN)
5402 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \
5403 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN)
5404
5405 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
5406 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
5407 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
5408 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
5409 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
5410 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
5411
5412 #define S_FW_IQ_CMD_IQFLINTISCSIC 26
5413 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1
5414 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC)
5415 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \
5416 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)
5417 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U)
5418
5419 #define S_FW_IQ_CMD_IQTYPE 24
5420 #define M_FW_IQ_CMD_IQTYPE 0x3
5421 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE)
5422 #define G_FW_IQ_CMD_IQTYPE(x) \
5423 (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE)
5424
5425 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
5426 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
5427 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
5428 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
5429 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
5430
5431 #define S_FW_IQ_CMD_FL0CONGDROP 16
5432 #define M_FW_IQ_CMD_FL0CONGDROP 0x1
5433 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP)
5434 #define G_FW_IQ_CMD_FL0CONGDROP(x) \
5435 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP)
5436 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U)
5437
5438 #define S_FW_IQ_CMD_FL0CACHELOCK 15
5439 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1
5440 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK)
5441 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \
5442 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK)
5443 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U)
5444
5445 #define S_FW_IQ_CMD_FL0DBP 14
5446 #define M_FW_IQ_CMD_FL0DBP 0x1
5447 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP)
5448 #define G_FW_IQ_CMD_FL0DBP(x) \
5449 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP)
5450 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U)
5451
5452 #define S_FW_IQ_CMD_FL0DATANS 13
5453 #define M_FW_IQ_CMD_FL0DATANS 0x1
5454 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS)
5455 #define G_FW_IQ_CMD_FL0DATANS(x) \
5456 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS)
5457 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U)
5458
5459 #define S_FW_IQ_CMD_FL0DATARO 12
5460 #define M_FW_IQ_CMD_FL0DATARO 0x1
5461 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
5462 #define G_FW_IQ_CMD_FL0DATARO(x) \
5463 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
5464 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
5465
5466 #define S_FW_IQ_CMD_FL0CONGCIF 11
5467 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
5468 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
5469 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
5470 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
5471 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
5472
5473 #define S_FW_IQ_CMD_FL0ONCHIP 10
5474 #define M_FW_IQ_CMD_FL0ONCHIP 0x1
5475 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP)
5476 #define G_FW_IQ_CMD_FL0ONCHIP(x) \
5477 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP)
5478 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U)
5479
5480 #define S_FW_IQ_CMD_FL0STATUSPGNS 9
5481 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1
5482 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS)
5483 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \
5484 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS)
5485 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U)
5486
5487 #define S_FW_IQ_CMD_FL0STATUSPGRO 8
5488 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1
5489 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO)
5490 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \
5491 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO)
5492 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U)
5493
5494 #define S_FW_IQ_CMD_FL0FETCHNS 7
5495 #define M_FW_IQ_CMD_FL0FETCHNS 0x1
5496 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS)
5497 #define G_FW_IQ_CMD_FL0FETCHNS(x) \
5498 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS)
5499 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U)
5500
5501 #define S_FW_IQ_CMD_FL0FETCHRO 6
5502 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
5503 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
5504 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
5505 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
5506 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
5507
5508 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
5509 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
5510 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
5511 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
5512 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
5513
5514 #define S_FW_IQ_CMD_FL0CPRIO 3
5515 #define M_FW_IQ_CMD_FL0CPRIO 0x1
5516 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO)
5517 #define G_FW_IQ_CMD_FL0CPRIO(x) \
5518 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO)
5519 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U)
5520
5521 #define S_FW_IQ_CMD_FL0PADEN 2
5522 #define M_FW_IQ_CMD_FL0PADEN 0x1
5523 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
5524 #define G_FW_IQ_CMD_FL0PADEN(x) \
5525 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
5526 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
5527
5528 #define S_FW_IQ_CMD_FL0PACKEN 1
5529 #define M_FW_IQ_CMD_FL0PACKEN 0x1
5530 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
5531 #define G_FW_IQ_CMD_FL0PACKEN(x) \
5532 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
5533 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
5534
5535 #define S_FW_IQ_CMD_FL0CONGEN 0
5536 #define M_FW_IQ_CMD_FL0CONGEN 0x1
5537 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
5538 #define G_FW_IQ_CMD_FL0CONGEN(x) \
5539 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
5540 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
5541
5542 #define S_FW_IQ_CMD_FL0DCAEN 15
5543 #define M_FW_IQ_CMD_FL0DCAEN 0x1
5544 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN)
5545 #define G_FW_IQ_CMD_FL0DCAEN(x) \
5546 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN)
5547 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U)
5548
5549 #define S_FW_IQ_CMD_FL0DCACPU 10
5550 #define M_FW_IQ_CMD_FL0DCACPU 0x1f
5551 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU)
5552 #define G_FW_IQ_CMD_FL0DCACPU(x) \
5553 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU)
5554
5555 #define S_FW_IQ_CMD_FL0FBMIN 7
5556 #define M_FW_IQ_CMD_FL0FBMIN 0x7
5557 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
5558 #define G_FW_IQ_CMD_FL0FBMIN(x) \
5559 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
5560
5561 #define S_FW_IQ_CMD_FL0FBMAX 4
5562 #define M_FW_IQ_CMD_FL0FBMAX 0x7
5563 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
5564 #define G_FW_IQ_CMD_FL0FBMAX(x) \
5565 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
5566
5567 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3
5568 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1
5569 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO)
5570 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \
5571 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO)
5572 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U)
5573
5574 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0
5575 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7
5576 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH)
5577 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \
5578 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH)
5579
5580 #define S_FW_IQ_CMD_FL1CNGCHMAP 20
5581 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf
5582 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP)
5583 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \
5584 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP)
5585
5586 #define S_FW_IQ_CMD_FL1CONGDROP 16
5587 #define M_FW_IQ_CMD_FL1CONGDROP 0x1
5588 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP)
5589 #define G_FW_IQ_CMD_FL1CONGDROP(x) \
5590 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP)
5591 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U)
5592
5593 #define S_FW_IQ_CMD_FL1CACHELOCK 15
5594 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1
5595 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK)
5596 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \
5597 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK)
5598 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U)
5599
5600 #define S_FW_IQ_CMD_FL1DBP 14
5601 #define M_FW_IQ_CMD_FL1DBP 0x1
5602 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP)
5603 #define G_FW_IQ_CMD_FL1DBP(x) \
5604 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP)
5605 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U)
5606
5607 #define S_FW_IQ_CMD_FL1DATANS 13
5608 #define M_FW_IQ_CMD_FL1DATANS 0x1
5609 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS)
5610 #define G_FW_IQ_CMD_FL1DATANS(x) \
5611 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS)
5612 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U)
5613
5614 #define S_FW_IQ_CMD_FL1DATARO 12
5615 #define M_FW_IQ_CMD_FL1DATARO 0x1
5616 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO)
5617 #define G_FW_IQ_CMD_FL1DATARO(x) \
5618 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO)
5619 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U)
5620
5621 #define S_FW_IQ_CMD_FL1CONGCIF 11
5622 #define M_FW_IQ_CMD_FL1CONGCIF 0x1
5623 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF)
5624 #define G_FW_IQ_CMD_FL1CONGCIF(x) \
5625 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF)
5626 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U)
5627
5628 #define S_FW_IQ_CMD_FL1ONCHIP 10
5629 #define M_FW_IQ_CMD_FL1ONCHIP 0x1
5630 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP)
5631 #define G_FW_IQ_CMD_FL1ONCHIP(x) \
5632 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP)
5633 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U)
5634
5635 #define S_FW_IQ_CMD_FL1STATUSPGNS 9
5636 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1
5637 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS)
5638 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \
5639 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS)
5640 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U)
5641
5642 #define S_FW_IQ_CMD_FL1STATUSPGRO 8
5643 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1
5644 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO)
5645 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \
5646 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO)
5647 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U)
5648
5649 #define S_FW_IQ_CMD_FL1FETCHNS 7
5650 #define M_FW_IQ_CMD_FL1FETCHNS 0x1
5651 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS)
5652 #define G_FW_IQ_CMD_FL1FETCHNS(x) \
5653 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS)
5654 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U)
5655
5656 #define S_FW_IQ_CMD_FL1FETCHRO 6
5657 #define M_FW_IQ_CMD_FL1FETCHRO 0x1
5658 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO)
5659 #define G_FW_IQ_CMD_FL1FETCHRO(x) \
5660 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO)
5661 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U)
5662
5663 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4
5664 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3
5665 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE)
5666 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \
5667 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE)
5668
5669 #define S_FW_IQ_CMD_FL1CPRIO 3
5670 #define M_FW_IQ_CMD_FL1CPRIO 0x1
5671 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO)
5672 #define G_FW_IQ_CMD_FL1CPRIO(x) \
5673 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO)
5674 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U)
5675
5676 #define S_FW_IQ_CMD_FL1PADEN 2
5677 #define M_FW_IQ_CMD_FL1PADEN 0x1
5678 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN)
5679 #define G_FW_IQ_CMD_FL1PADEN(x) \
5680 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN)
5681 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U)
5682
5683 #define S_FW_IQ_CMD_FL1PACKEN 1
5684 #define M_FW_IQ_CMD_FL1PACKEN 0x1
5685 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN)
5686 #define G_FW_IQ_CMD_FL1PACKEN(x) \
5687 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN)
5688 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U)
5689
5690 #define S_FW_IQ_CMD_FL1CONGEN 0
5691 #define M_FW_IQ_CMD_FL1CONGEN 0x1
5692 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN)
5693 #define G_FW_IQ_CMD_FL1CONGEN(x) \
5694 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN)
5695 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U)
5696
5697 #define S_FW_IQ_CMD_FL1DCAEN 15
5698 #define M_FW_IQ_CMD_FL1DCAEN 0x1
5699 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN)
5700 #define G_FW_IQ_CMD_FL1DCAEN(x) \
5701 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN)
5702 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U)
5703
5704 #define S_FW_IQ_CMD_FL1DCACPU 10
5705 #define M_FW_IQ_CMD_FL1DCACPU 0x1f
5706 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU)
5707 #define G_FW_IQ_CMD_FL1DCACPU(x) \
5708 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU)
5709
5710 #define S_FW_IQ_CMD_FL1FBMIN 7
5711 #define M_FW_IQ_CMD_FL1FBMIN 0x7
5712 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN)
5713 #define G_FW_IQ_CMD_FL1FBMIN(x) \
5714 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN)
5715
5716 #define S_FW_IQ_CMD_FL1FBMAX 4
5717 #define M_FW_IQ_CMD_FL1FBMAX 0x7
5718 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX)
5719 #define G_FW_IQ_CMD_FL1FBMAX(x) \
5720 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX)
5721
5722 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3
5723 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1
5724 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO)
5725 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \
5726 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO)
5727 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U)
5728
5729 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0
5730 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7
5731 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH)
5732 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \
5733 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH)
5734
5735 struct fw_eq_mngt_cmd {
5736 __be32 op_to_vfn;
5737 __be32 alloc_to_len16;
5738 __be32 cmpliqid_eqid;
5739 __be32 physeqid_pkd;
5740 __be32 fetchszm_to_iqid;
5741 __be32 dcaen_to_eqsize;
5742 __be64 eqaddr;
5743 };
5744
5745 #define S_FW_EQ_MNGT_CMD_PFN 8
5746 #define M_FW_EQ_MNGT_CMD_PFN 0x7
5747 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN)
5748 #define G_FW_EQ_MNGT_CMD_PFN(x) \
5749 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN)
5750
5751 #define S_FW_EQ_MNGT_CMD_VFN 0
5752 #define M_FW_EQ_MNGT_CMD_VFN 0xff
5753 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN)
5754 #define G_FW_EQ_MNGT_CMD_VFN(x) \
5755 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN)
5756
5757 #define S_FW_EQ_MNGT_CMD_ALLOC 31
5758 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1
5759 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC)
5760 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \
5761 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC)
5762 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U)
5763
5764 #define S_FW_EQ_MNGT_CMD_FREE 30
5765 #define M_FW_EQ_MNGT_CMD_FREE 0x1
5766 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE)
5767 #define G_FW_EQ_MNGT_CMD_FREE(x) \
5768 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE)
5769 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U)
5770
5771 #define S_FW_EQ_MNGT_CMD_MODIFY 29
5772 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1
5773 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY)
5774 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \
5775 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY)
5776 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U)
5777
5778 #define S_FW_EQ_MNGT_CMD_EQSTART 28
5779 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1
5780 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART)
5781 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \
5782 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART)
5783 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U)
5784
5785 #define S_FW_EQ_MNGT_CMD_EQSTOP 27
5786 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1
5787 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP)
5788 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \
5789 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP)
5790 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U)
5791
5792 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20
5793 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff
5794 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID)
5795 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \
5796 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID)
5797
5798 #define S_FW_EQ_MNGT_CMD_EQID 0
5799 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff
5800 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID)
5801 #define G_FW_EQ_MNGT_CMD_EQID(x) \
5802 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID)
5803
5804 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0
5805 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff
5806 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID)
5807 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \
5808 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID)
5809
5810 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26
5811 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1
5812 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM)
5813 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \
5814 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM)
5815 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U)
5816
5817 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25
5818 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1
5819 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS)
5820 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \
5821 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS)
5822 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U)
5823
5824 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24
5825 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1
5826 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO)
5827 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \
5828 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO)
5829 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U)
5830
5831 #define S_FW_EQ_MNGT_CMD_FETCHNS 23
5832 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1
5833 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS)
5834 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \
5835 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS)
5836 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U)
5837
5838 #define S_FW_EQ_MNGT_CMD_FETCHRO 22
5839 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1
5840 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO)
5841 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \
5842 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO)
5843 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U)
5844
5845 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20
5846 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3
5847 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE)
5848 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \
5849 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE)
5850
5851 #define S_FW_EQ_MNGT_CMD_CPRIO 19
5852 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1
5853 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO)
5854 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \
5855 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO)
5856 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U)
5857
5858 #define S_FW_EQ_MNGT_CMD_ONCHIP 18
5859 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1
5860 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP)
5861 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \
5862 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP)
5863 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U)
5864
5865 #define S_FW_EQ_MNGT_CMD_PCIECHN 16
5866 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3
5867 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN)
5868 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \
5869 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN)
5870
5871 #define S_FW_EQ_MNGT_CMD_IQID 0
5872 #define M_FW_EQ_MNGT_CMD_IQID 0xffff
5873 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID)
5874 #define G_FW_EQ_MNGT_CMD_IQID(x) \
5875 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID)
5876
5877 #define S_FW_EQ_MNGT_CMD_DCAEN 31
5878 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1
5879 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN)
5880 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \
5881 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN)
5882 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U)
5883
5884 #define S_FW_EQ_MNGT_CMD_DCACPU 26
5885 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f
5886 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU)
5887 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \
5888 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU)
5889
5890 #define S_FW_EQ_MNGT_CMD_FBMIN 23
5891 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7
5892 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN)
5893 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \
5894 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN)
5895
5896 #define S_FW_EQ_MNGT_CMD_FBMAX 20
5897 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7
5898 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX)
5899 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \
5900 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX)
5901
5902 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19
5903 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1
5904 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
5905 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
5906 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
5907 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
5908 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U)
5909
5910 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16
5911 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7
5912 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH)
5913 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \
5914 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH)
5915
5916 #define S_FW_EQ_MNGT_CMD_EQSIZE 0
5917 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff
5918 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE)
5919 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \
5920 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE)
5921
5922 struct fw_eq_eth_cmd {
5923 __be32 op_to_vfn;
5924 __be32 alloc_to_len16;
5925 __be32 eqid_pkd;
5926 __be32 physeqid_pkd;
5927 __be32 fetchszm_to_iqid;
5928 __be32 dcaen_to_eqsize;
5929 __be64 eqaddr;
5930 __be32 autoequiqe_to_viid;
5931 __be32 timeren_timerix;
5932 __be64 r9;
5933 };
5934
5935 #define S_FW_EQ_ETH_CMD_PFN 8
5936 #define M_FW_EQ_ETH_CMD_PFN 0x7
5937 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
5938 #define G_FW_EQ_ETH_CMD_PFN(x) \
5939 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
5940
5941 #define S_FW_EQ_ETH_CMD_VFN 0
5942 #define M_FW_EQ_ETH_CMD_VFN 0xff
5943 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
5944 #define G_FW_EQ_ETH_CMD_VFN(x) \
5945 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
5946
5947 #define S_FW_EQ_ETH_CMD_ALLOC 31
5948 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
5949 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
5950 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
5951 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
5952 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
5953
5954 #define S_FW_EQ_ETH_CMD_FREE 30
5955 #define M_FW_EQ_ETH_CMD_FREE 0x1
5956 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
5957 #define G_FW_EQ_ETH_CMD_FREE(x) \
5958 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
5959 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
5960
5961 #define S_FW_EQ_ETH_CMD_MODIFY 29
5962 #define M_FW_EQ_ETH_CMD_MODIFY 0x1
5963 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY)
5964 #define G_FW_EQ_ETH_CMD_MODIFY(x) \
5965 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY)
5966 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U)
5967
5968 #define S_FW_EQ_ETH_CMD_EQSTART 28
5969 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
5970 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
5971 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
5972 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
5973 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
5974
5975 #define S_FW_EQ_ETH_CMD_EQSTOP 27
5976 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1
5977 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP)
5978 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \
5979 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP)
5980 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U)
5981
5982 #define S_FW_EQ_ETH_CMD_EQID 0
5983 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
5984 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
5985 #define G_FW_EQ_ETH_CMD_EQID(x) \
5986 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
5987
5988 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
5989 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
5990 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID)
5991 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
5992 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
5993
5994 #define S_FW_EQ_ETH_CMD_FETCHSZM 26
5995 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1
5996 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM)
5997 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \
5998 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM)
5999 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U)
6000
6001 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25
6002 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1
6003 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS)
6004 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \
6005 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS)
6006 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U)
6007
6008 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24
6009 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1
6010 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO)
6011 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \
6012 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO)
6013 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U)
6014
6015 #define S_FW_EQ_ETH_CMD_FETCHNS 23
6016 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1
6017 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS)
6018 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \
6019 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS)
6020 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U)
6021
6022 #define S_FW_EQ_ETH_CMD_FETCHRO 22
6023 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
6024 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
6025 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
6026 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
6027 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
6028
6029 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
6030 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
6031 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
6032 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
6033 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
6034
6035 #define S_FW_EQ_ETH_CMD_CPRIO 19
6036 #define M_FW_EQ_ETH_CMD_CPRIO 0x1
6037 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO)
6038 #define G_FW_EQ_ETH_CMD_CPRIO(x) \
6039 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO)
6040 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U)
6041
6042 #define S_FW_EQ_ETH_CMD_ONCHIP 18
6043 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1
6044 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP)
6045 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \
6046 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP)
6047 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U)
6048
6049 #define S_FW_EQ_ETH_CMD_PCIECHN 16
6050 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
6051 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
6052 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
6053 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
6054
6055 #define S_FW_EQ_ETH_CMD_IQID 0
6056 #define M_FW_EQ_ETH_CMD_IQID 0xffff
6057 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
6058 #define G_FW_EQ_ETH_CMD_IQID(x) \
6059 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
6060
6061 #define S_FW_EQ_ETH_CMD_DCAEN 31
6062 #define M_FW_EQ_ETH_CMD_DCAEN 0x1
6063 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN)
6064 #define G_FW_EQ_ETH_CMD_DCAEN(x) \
6065 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN)
6066 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U)
6067
6068 #define S_FW_EQ_ETH_CMD_DCACPU 26
6069 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f
6070 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU)
6071 #define G_FW_EQ_ETH_CMD_DCACPU(x) \
6072 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU)
6073
6074 #define S_FW_EQ_ETH_CMD_FBMIN 23
6075 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
6076 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
6077 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
6078 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
6079
6080 #define S_FW_EQ_ETH_CMD_FBMAX 20
6081 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
6082 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
6083 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
6084 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
6085
6086 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19
6087 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1
6088 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO)
6089 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \
6090 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO)
6091 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U)
6092
6093 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
6094 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
6095 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
6096 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
6097 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
6098
6099 #define S_FW_EQ_ETH_CMD_EQSIZE 0
6100 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
6101 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
6102 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
6103 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
6104
6105 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31
6106 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1
6107 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE)
6108 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \
6109 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE)
6110 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U)
6111
6112 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
6113 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
6114 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
6115 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
6116 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
6117 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
6118
6119 #define S_FW_EQ_ETH_CMD_VIID 16
6120 #define M_FW_EQ_ETH_CMD_VIID 0xfff
6121 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
6122 #define G_FW_EQ_ETH_CMD_VIID(x) \
6123 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
6124
6125 #define S_FW_EQ_ETH_CMD_TIMEREN 3
6126 #define M_FW_EQ_ETH_CMD_TIMEREN 0x1
6127 #define V_FW_EQ_ETH_CMD_TIMEREN(x) ((x) << S_FW_EQ_ETH_CMD_TIMEREN)
6128 #define G_FW_EQ_ETH_CMD_TIMEREN(x) \
6129 (((x) >> S_FW_EQ_ETH_CMD_TIMEREN) & M_FW_EQ_ETH_CMD_TIMEREN)
6130 #define F_FW_EQ_ETH_CMD_TIMEREN V_FW_EQ_ETH_CMD_TIMEREN(1U)
6131
6132 #define S_FW_EQ_ETH_CMD_TIMERIX 0
6133 #define M_FW_EQ_ETH_CMD_TIMERIX 0x7
6134 #define V_FW_EQ_ETH_CMD_TIMERIX(x) ((x) << S_FW_EQ_ETH_CMD_TIMERIX)
6135 #define G_FW_EQ_ETH_CMD_TIMERIX(x) \
6136 (((x) >> S_FW_EQ_ETH_CMD_TIMERIX) & M_FW_EQ_ETH_CMD_TIMERIX)
6137
6138 struct fw_eq_ctrl_cmd {
6139 __be32 op_to_vfn;
6140 __be32 alloc_to_len16;
6141 __be32 cmpliqid_eqid;
6142 __be32 physeqid_pkd;
6143 __be32 fetchszm_to_iqid;
6144 __be32 dcaen_to_eqsize;
6145 __be64 eqaddr;
6146 };
6147
6148 #define S_FW_EQ_CTRL_CMD_PFN 8
6149 #define M_FW_EQ_CTRL_CMD_PFN 0x7
6150 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
6151 #define G_FW_EQ_CTRL_CMD_PFN(x) \
6152 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN)
6153
6154 #define S_FW_EQ_CTRL_CMD_VFN 0
6155 #define M_FW_EQ_CTRL_CMD_VFN 0xff
6156 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
6157 #define G_FW_EQ_CTRL_CMD_VFN(x) \
6158 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN)
6159
6160 #define S_FW_EQ_CTRL_CMD_ALLOC 31
6161 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1
6162 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
6163 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \
6164 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC)
6165 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
6166
6167 #define S_FW_EQ_CTRL_CMD_FREE 30
6168 #define M_FW_EQ_CTRL_CMD_FREE 0x1
6169 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
6170 #define G_FW_EQ_CTRL_CMD_FREE(x) \
6171 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE)
6172 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
6173
6174 #define S_FW_EQ_CTRL_CMD_MODIFY 29
6175 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1
6176 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY)
6177 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \
6178 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY)
6179 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U)
6180
6181 #define S_FW_EQ_CTRL_CMD_EQSTART 28
6182 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1
6183 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
6184 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \
6185 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART)
6186 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
6187
6188 #define S_FW_EQ_CTRL_CMD_EQSTOP 27
6189 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1
6190 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP)
6191 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \
6192 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP)
6193 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U)
6194
6195 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
6196 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff
6197 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
6198 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \
6199 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID)
6200
6201 #define S_FW_EQ_CTRL_CMD_EQID 0
6202 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
6203 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
6204 #define G_FW_EQ_CTRL_CMD_EQID(x) \
6205 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
6206
6207 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
6208 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
6209 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
6210 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
6211 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
6212
6213 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26
6214 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1
6215 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM)
6216 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \
6217 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM)
6218 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U)
6219
6220 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25
6221 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1
6222 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS)
6223 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \
6224 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS)
6225 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U)
6226
6227 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24
6228 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1
6229 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO)
6230 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \
6231 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO)
6232 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U)
6233
6234 #define S_FW_EQ_CTRL_CMD_FETCHNS 23
6235 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1
6236 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS)
6237 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \
6238 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS)
6239 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U)
6240
6241 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
6242 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1
6243 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
6244 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \
6245 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO)
6246 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
6247
6248 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
6249 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
6250 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
6251 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \
6252 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE)
6253
6254 #define S_FW_EQ_CTRL_CMD_CPRIO 19
6255 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1
6256 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO)
6257 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \
6258 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO)
6259 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U)
6260
6261 #define S_FW_EQ_CTRL_CMD_ONCHIP 18
6262 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1
6263 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP)
6264 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \
6265 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP)
6266 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U)
6267
6268 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
6269 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3
6270 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
6271 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \
6272 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN)
6273
6274 #define S_FW_EQ_CTRL_CMD_IQID 0
6275 #define M_FW_EQ_CTRL_CMD_IQID 0xffff
6276 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
6277 #define G_FW_EQ_CTRL_CMD_IQID(x) \
6278 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID)
6279
6280 #define S_FW_EQ_CTRL_CMD_DCAEN 31
6281 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1
6282 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN)
6283 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \
6284 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN)
6285 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U)
6286
6287 #define S_FW_EQ_CTRL_CMD_DCACPU 26
6288 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f
6289 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU)
6290 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \
6291 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU)
6292
6293 #define S_FW_EQ_CTRL_CMD_FBMIN 23
6294 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7
6295 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
6296 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \
6297 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN)
6298
6299 #define S_FW_EQ_CTRL_CMD_FBMAX 20
6300 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7
6301 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
6302 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \
6303 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX)
6304
6305 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19
6306 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1
6307 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
6308 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
6309 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
6310 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
6311 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U)
6312
6313 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
6314 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7
6315 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
6316 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \
6317 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH)
6318
6319 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
6320 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff
6321 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
6322 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \
6323 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE)
6324
6325 struct fw_eq_ofld_cmd {
6326 __be32 op_to_vfn;
6327 __be32 alloc_to_len16;
6328 __be32 eqid_pkd;
6329 __be32 physeqid_pkd;
6330 __be32 fetchszm_to_iqid;
6331 __be32 dcaen_to_eqsize;
6332 __be64 eqaddr;
6333 };
6334
6335 #define S_FW_EQ_OFLD_CMD_PFN 8
6336 #define M_FW_EQ_OFLD_CMD_PFN 0x7
6337 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN)
6338 #define G_FW_EQ_OFLD_CMD_PFN(x) \
6339 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN)
6340
6341 #define S_FW_EQ_OFLD_CMD_VFN 0
6342 #define M_FW_EQ_OFLD_CMD_VFN 0xff
6343 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN)
6344 #define G_FW_EQ_OFLD_CMD_VFN(x) \
6345 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN)
6346
6347 #define S_FW_EQ_OFLD_CMD_ALLOC 31
6348 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1
6349 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC)
6350 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \
6351 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC)
6352 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U)
6353
6354 #define S_FW_EQ_OFLD_CMD_FREE 30
6355 #define M_FW_EQ_OFLD_CMD_FREE 0x1
6356 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE)
6357 #define G_FW_EQ_OFLD_CMD_FREE(x) \
6358 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE)
6359 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U)
6360
6361 #define S_FW_EQ_OFLD_CMD_MODIFY 29
6362 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1
6363 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY)
6364 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \
6365 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY)
6366 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U)
6367
6368 #define S_FW_EQ_OFLD_CMD_EQSTART 28
6369 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1
6370 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART)
6371 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \
6372 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART)
6373 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U)
6374
6375 #define S_FW_EQ_OFLD_CMD_EQSTOP 27
6376 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1
6377 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP)
6378 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \
6379 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP)
6380 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U)
6381
6382 #define S_FW_EQ_OFLD_CMD_EQID 0
6383 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff
6384 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID)
6385 #define G_FW_EQ_OFLD_CMD_EQID(x) \
6386 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID)
6387
6388 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0
6389 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff
6390 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID)
6391 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \
6392 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID)
6393
6394 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26
6395 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1
6396 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM)
6397 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \
6398 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM)
6399 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U)
6400
6401 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25
6402 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1
6403 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS)
6404 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \
6405 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS)
6406 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U)
6407
6408 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24
6409 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1
6410 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO)
6411 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \
6412 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO)
6413 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U)
6414
6415 #define S_FW_EQ_OFLD_CMD_FETCHNS 23
6416 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1
6417 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS)
6418 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \
6419 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS)
6420 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U)
6421
6422 #define S_FW_EQ_OFLD_CMD_FETCHRO 22
6423 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1
6424 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO)
6425 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \
6426 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO)
6427 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U)
6428
6429 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20
6430 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3
6431 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE)
6432 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \
6433 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE)
6434
6435 #define S_FW_EQ_OFLD_CMD_CPRIO 19
6436 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1
6437 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO)
6438 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \
6439 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO)
6440 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U)
6441
6442 #define S_FW_EQ_OFLD_CMD_ONCHIP 18
6443 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1
6444 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP)
6445 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \
6446 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP)
6447 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U)
6448
6449 #define S_FW_EQ_OFLD_CMD_PCIECHN 16
6450 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3
6451 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN)
6452 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \
6453 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN)
6454
6455 #define S_FW_EQ_OFLD_CMD_IQID 0
6456 #define M_FW_EQ_OFLD_CMD_IQID 0xffff
6457 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID)
6458 #define G_FW_EQ_OFLD_CMD_IQID(x) \
6459 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID)
6460
6461 #define S_FW_EQ_OFLD_CMD_DCAEN 31
6462 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1
6463 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN)
6464 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \
6465 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN)
6466 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U)
6467
6468 #define S_FW_EQ_OFLD_CMD_DCACPU 26
6469 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f
6470 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU)
6471 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \
6472 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU)
6473
6474 #define S_FW_EQ_OFLD_CMD_FBMIN 23
6475 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7
6476 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN)
6477 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \
6478 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN)
6479
6480 #define S_FW_EQ_OFLD_CMD_FBMAX 20
6481 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7
6482 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX)
6483 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \
6484 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX)
6485
6486 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19
6487 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1
6488 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
6489 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
6490 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
6491 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
6492 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U)
6493
6494 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16
6495 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7
6496 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH)
6497 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \
6498 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH)
6499
6500 #define S_FW_EQ_OFLD_CMD_EQSIZE 0
6501 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff
6502 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE)
6503 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \
6504 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)
6505
6506 /* Following macros present here only to maintain backward
6507 * compatibiity. Driver must not use these anymore */
6508 /* Macros for VIID parsing:
6509 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */
6510 #define S_FW_VIID_PFN 8
6511 #define M_FW_VIID_PFN 0x7
6512 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN)
6513 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN)
6514
6515 #define S_FW_VIID_VIVLD 7
6516 #define M_FW_VIID_VIVLD 0x1
6517 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD)
6518 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
6519
6520 #define S_FW_VIID_VIN 0
6521 #define M_FW_VIID_VIN 0x7F
6522 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN)
6523 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
6524
6525 /* Macros for VIID parsing:
6526 VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */
6527 #define S_FW_256VIID_PFN 9
6528 #define M_FW_256VIID_PFN 0x7
6529 #define V_FW_256VIID_PFN(x) ((x) << S_FW_256VIID_PFN)
6530 #define G_FW_256VIID_PFN(x) (((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN)
6531
6532 #define S_FW_256VIID_VIVLD 8
6533 #define M_FW_256VIID_VIVLD 0x1
6534 #define V_FW_256VIID_VIVLD(x) ((x) << S_FW_256VIID_VIVLD)
6535 #define G_FW_256VIID_VIVLD(x) (((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD)
6536
6537 #define S_FW_256VIID_VIN 0
6538 #define M_FW_256VIID_VIN 0xFF
6539 #define V_FW_256VIID_VIN(x) ((x) << S_FW_256VIID_VIN)
6540 #define G_FW_256VIID_VIN(x) (((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN)
6541
6542 enum fw_vi_func {
6543 FW_VI_FUNC_ETH,
6544 FW_VI_FUNC_OFLD,
6545 FW_VI_FUNC_IWARP,
6546 FW_VI_FUNC_OPENISCSI,
6547 FW_VI_FUNC_OPENFCOE,
6548 FW_VI_FUNC_FOISCSI,
6549 FW_VI_FUNC_FOFCOE,
6550 FW_VI_FUNC_FW,
6551 };
6552
6553 struct fw_vi_cmd {
6554 __be32 op_to_vfn;
6555 __be32 alloc_to_len16;
6556 __be16 type_to_viid;
6557 __u8 mac[6];
6558 __u8 portid_pkd;
6559 __u8 nmac;
6560 __u8 nmac0[6];
6561 __be16 norss_rsssize;
6562 __u8 nmac1[6];
6563 __be16 idsiiq_pkd;
6564 __u8 nmac2[6];
6565 __be16 idseiq_pkd;
6566 __u8 nmac3[6];
6567 __be64 r9;
6568 __be64 r10;
6569 };
6570
6571 #define S_FW_VI_CMD_PFN 8
6572 #define M_FW_VI_CMD_PFN 0x7
6573 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
6574 #define G_FW_VI_CMD_PFN(x) \
6575 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
6576
6577 #define S_FW_VI_CMD_VFN 0
6578 #define M_FW_VI_CMD_VFN 0xff
6579 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
6580 #define G_FW_VI_CMD_VFN(x) \
6581 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
6582
6583 #define S_FW_VI_CMD_ALLOC 31
6584 #define M_FW_VI_CMD_ALLOC 0x1
6585 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
6586 #define G_FW_VI_CMD_ALLOC(x) \
6587 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
6588 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
6589
6590 #define S_FW_VI_CMD_FREE 30
6591 #define M_FW_VI_CMD_FREE 0x1
6592 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
6593 #define G_FW_VI_CMD_FREE(x) \
6594 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
6595 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
6596
6597 #define S_FW_VI_CMD_VFVLD 24
6598 #define M_FW_VI_CMD_VFVLD 0x1
6599 #define V_FW_VI_CMD_VFVLD(x) ((x) << S_FW_VI_CMD_VFVLD)
6600 #define G_FW_VI_CMD_VFVLD(x) \
6601 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD)
6602 #define F_FW_VI_CMD_VFVLD V_FW_VI_CMD_VFVLD(1U)
6603
6604 #define S_FW_VI_CMD_VIN 16
6605 #define M_FW_VI_CMD_VIN 0xff
6606 #define V_FW_VI_CMD_VIN(x) ((x) << S_FW_VI_CMD_VIN)
6607 #define G_FW_VI_CMD_VIN(x) \
6608 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN)
6609
6610 #define S_FW_VI_CMD_TYPE 15
6611 #define M_FW_VI_CMD_TYPE 0x1
6612 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
6613 #define G_FW_VI_CMD_TYPE(x) \
6614 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
6615 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
6616
6617 #define S_FW_VI_CMD_FUNC 12
6618 #define M_FW_VI_CMD_FUNC 0x7
6619 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
6620 #define G_FW_VI_CMD_FUNC(x) \
6621 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
6622
6623 #define S_FW_VI_CMD_VIID 0
6624 #define M_FW_VI_CMD_VIID 0xfff
6625 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
6626 #define G_FW_VI_CMD_VIID(x) \
6627 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
6628
6629 #define S_FW_VI_CMD_PORTID 4
6630 #define M_FW_VI_CMD_PORTID 0xf
6631 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
6632 #define G_FW_VI_CMD_PORTID(x) \
6633 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
6634
6635 #define S_FW_VI_CMD_NORSS 11
6636 #define M_FW_VI_CMD_NORSS 0x1
6637 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS)
6638 #define G_FW_VI_CMD_NORSS(x) \
6639 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS)
6640 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U)
6641
6642 #define S_FW_VI_CMD_RSSSIZE 0
6643 #define M_FW_VI_CMD_RSSSIZE 0x7ff
6644 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
6645 #define G_FW_VI_CMD_RSSSIZE(x) \
6646 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
6647
6648 #define S_FW_VI_CMD_IDSIIQ 0
6649 #define M_FW_VI_CMD_IDSIIQ 0x3ff
6650 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ)
6651 #define G_FW_VI_CMD_IDSIIQ(x) \
6652 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ)
6653
6654 #define S_FW_VI_CMD_IDSEIQ 0
6655 #define M_FW_VI_CMD_IDSEIQ 0x3ff
6656 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ)
6657 #define G_FW_VI_CMD_IDSEIQ(x) \
6658 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ)
6659
6660 /* Special VI_MAC command index ids */
6661 #define FW_VI_MAC_ADD_MAC 0x3FF
6662 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
6663 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
6664 #define FW_VI_MAC_ID_BASED_FREE 0x3FC
6665
6666 enum fw_vi_mac_smac {
6667 FW_VI_MAC_MPS_TCAM_ENTRY,
6668 FW_VI_MAC_MPS_TCAM_ONLY,
6669 FW_VI_MAC_SMT_ONLY,
6670 FW_VI_MAC_SMT_AND_MPSTCAM
6671 };
6672
6673 enum fw_vi_mac_result {
6674 FW_VI_MAC_R_SUCCESS,
6675 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
6676 FW_VI_MAC_R_SMAC_FAIL,
6677 FW_VI_MAC_R_F_ACL_CHECK
6678 };
6679
6680 enum fw_vi_mac_entry_types {
6681 FW_VI_MAC_TYPE_EXACTMAC,
6682 FW_VI_MAC_TYPE_HASHVEC,
6683 FW_VI_MAC_TYPE_RAW,
6684 FW_VI_MAC_TYPE_EXACTMAC_VNI,
6685 };
6686
6687 struct fw_vi_mac_cmd {
6688 __be32 op_to_viid;
6689 __be32 freemacs_to_len16;
6690 union fw_vi_mac {
6691 struct fw_vi_mac_exact {
6692 __be16 valid_to_idx;
6693 __u8 macaddr[6];
6694 } exact[7];
6695 struct fw_vi_mac_hash {
6696 __be64 hashvec;
6697 } hash;
6698 struct fw_vi_mac_raw {
6699 __be32 raw_idx_pkd;
6700 __be32 data0_pkd;
6701 __be32 data1[2];
6702 __be64 data0m_pkd;
6703 __be32 data1m[2];
6704 } raw;
6705 struct fw_vi_mac_vni {
6706 __be16 valid_to_idx;
6707 __u8 macaddr[6];
6708 __be16 r7;
6709 __u8 macaddr_mask[6];
6710 __be32 lookup_type_to_vni;
6711 __be32 vni_mask_pkd;
6712 } exact_vni[2];
6713 } u;
6714 };
6715
6716 #define S_FW_VI_MAC_CMD_SMTID 12
6717 #define M_FW_VI_MAC_CMD_SMTID 0xff
6718 #define V_FW_VI_MAC_CMD_SMTID(x) ((x) << S_FW_VI_MAC_CMD_SMTID)
6719 #define G_FW_VI_MAC_CMD_SMTID(x) \
6720 (((x) >> S_FW_VI_MAC_CMD_SMTID) & M_FW_VI_MAC_CMD_SMTID)
6721
6722 #define S_FW_VI_MAC_CMD_VIID 0
6723 #define M_FW_VI_MAC_CMD_VIID 0xfff
6724 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
6725 #define G_FW_VI_MAC_CMD_VIID(x) \
6726 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
6727
6728 #define S_FW_VI_MAC_CMD_FREEMACS 31
6729 #define M_FW_VI_MAC_CMD_FREEMACS 0x1
6730 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS)
6731 #define G_FW_VI_MAC_CMD_FREEMACS(x) \
6732 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)
6733 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U)
6734
6735 #define S_FW_VI_MAC_CMD_IS_SMAC 30
6736 #define M_FW_VI_MAC_CMD_IS_SMAC 0x1
6737 #define V_FW_VI_MAC_CMD_IS_SMAC(x) ((x) << S_FW_VI_MAC_CMD_IS_SMAC)
6738 #define G_FW_VI_MAC_CMD_IS_SMAC(x) \
6739 (((x) >> S_FW_VI_MAC_CMD_IS_SMAC) & M_FW_VI_MAC_CMD_IS_SMAC)
6740 #define F_FW_VI_MAC_CMD_IS_SMAC V_FW_VI_MAC_CMD_IS_SMAC(1U)
6741
6742 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23
6743 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7
6744 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
6745 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \
6746 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE)
6747
6748 #define S_FW_VI_MAC_CMD_HASHUNIEN 22
6749 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1
6750 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN)
6751 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \
6752 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN)
6753 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U)
6754
6755 #define S_FW_VI_MAC_CMD_VALID 15
6756 #define M_FW_VI_MAC_CMD_VALID 0x1
6757 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
6758 #define G_FW_VI_MAC_CMD_VALID(x) \
6759 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
6760 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
6761
6762 #define S_FW_VI_MAC_CMD_PRIO 12
6763 #define M_FW_VI_MAC_CMD_PRIO 0x7
6764 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO)
6765 #define G_FW_VI_MAC_CMD_PRIO(x) \
6766 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO)
6767
6768 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
6769 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
6770 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
6771 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
6772 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
6773
6774 #define S_FW_VI_MAC_CMD_IDX 0
6775 #define M_FW_VI_MAC_CMD_IDX 0x3ff
6776 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
6777 #define G_FW_VI_MAC_CMD_IDX(x) \
6778 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
6779
6780 #define S_FW_VI_MAC_CMD_RAW_IDX 16
6781 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff
6782 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
6783 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \
6784 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
6785
6786 #define S_FW_VI_MAC_CMD_DATA0 0
6787 #define M_FW_VI_MAC_CMD_DATA0 0xffff
6788 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0)
6789 #define G_FW_VI_MAC_CMD_DATA0(x) \
6790 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0)
6791
6792 #define S_FW_VI_MAC_CMD_LOOKUP_TYPE 31
6793 #define M_FW_VI_MAC_CMD_LOOKUP_TYPE 0x1
6794 #define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x) ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE)
6795 #define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \
6796 (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE)
6797 #define F_FW_VI_MAC_CMD_LOOKUP_TYPE V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U)
6798
6799 #define S_FW_VI_MAC_CMD_DIP_HIT 30
6800 #define M_FW_VI_MAC_CMD_DIP_HIT 0x1
6801 #define V_FW_VI_MAC_CMD_DIP_HIT(x) ((x) << S_FW_VI_MAC_CMD_DIP_HIT)
6802 #define G_FW_VI_MAC_CMD_DIP_HIT(x) \
6803 (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT)
6804 #define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U)
6805
6806 #define S_FW_VI_MAC_CMD_VNI 0
6807 #define M_FW_VI_MAC_CMD_VNI 0xffffff
6808 #define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI)
6809 #define G_FW_VI_MAC_CMD_VNI(x) \
6810 (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI)
6811
6812 /* Extracting loopback port number passed from driver.
6813 * as a part of fw_vi_mac_vni For non loopback entries
6814 * ignore the field and update port number from flowc.
6815 * Fw will ignore if physical port number received.
6816 * expected range (4-7).
6817 */
6818
6819 #define S_FW_VI_MAC_CMD_PORT 24
6820 #define M_FW_VI_MAC_CMD_PORT 0x7
6821 #define V_FW_VI_MAC_CMD_PORT(x) ((x) << S_FW_VI_MAC_CMD_PORT)
6822 #define G_FW_VI_MAC_CMD_PORT(x) \
6823 (((x) >> S_FW_VI_MAC_CMD_PORT) & M_FW_VI_MAC_CMD_PORT)
6824
6825 #define S_FW_VI_MAC_CMD_VNI_MASK 0
6826 #define M_FW_VI_MAC_CMD_VNI_MASK 0xffffff
6827 #define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK)
6828 #define G_FW_VI_MAC_CMD_VNI_MASK(x) \
6829 (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK)
6830
6831 /* T4 max MTU supported */
6832 #define T4_MAX_MTU_SUPPORTED 9600
6833 #define FW_RXMODE_MTU_NO_CHG 65535
6834
6835 struct fw_vi_rxmode_cmd {
6836 __be32 op_to_viid;
6837 __be32 retval_len16;
6838 __be32 mtu_to_vlanexen;
6839 __be32 r4_lo;
6840 };
6841
6842 #define S_FW_VI_RXMODE_CMD_VIID 0
6843 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
6844 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
6845 #define G_FW_VI_RXMODE_CMD_VIID(x) \
6846 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
6847
6848 #define S_FW_VI_RXMODE_CMD_MTU 16
6849 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
6850 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
6851 #define G_FW_VI_RXMODE_CMD_MTU(x) \
6852 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
6853
6854 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
6855 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
6856 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
6857 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
6858 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
6859
6860 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
6861 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
6862 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
6863 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
6864 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
6865 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
6866
6867 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
6868 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
6869 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
6870 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
6871 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
6872 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN)
6873
6874 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
6875 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
6876 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
6877 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
6878 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
6879
6880 struct fw_vi_enable_cmd {
6881 __be32 op_to_viid;
6882 __be32 ien_to_len16;
6883 __be16 blinkdur;
6884 __be16 r3;
6885 __be32 r4;
6886 };
6887
6888 #define S_FW_VI_ENABLE_CMD_VIID 0
6889 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
6890 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
6891 #define G_FW_VI_ENABLE_CMD_VIID(x) \
6892 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
6893
6894 #define S_FW_VI_ENABLE_CMD_IEN 31
6895 #define M_FW_VI_ENABLE_CMD_IEN 0x1
6896 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
6897 #define G_FW_VI_ENABLE_CMD_IEN(x) \
6898 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
6899 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
6900
6901 #define S_FW_VI_ENABLE_CMD_EEN 30
6902 #define M_FW_VI_ENABLE_CMD_EEN 0x1
6903 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
6904 #define G_FW_VI_ENABLE_CMD_EEN(x) \
6905 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
6906 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
6907
6908 #define S_FW_VI_ENABLE_CMD_LED 29
6909 #define M_FW_VI_ENABLE_CMD_LED 0x1
6910 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED)
6911 #define G_FW_VI_ENABLE_CMD_LED(x) \
6912 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED)
6913 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U)
6914
6915 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
6916 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
6917 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
6918 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
6919 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
6920 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
6921
6922 /* VI VF stats offset definitions */
6923 #define VI_VF_NUM_STATS 16
6924 enum fw_vi_stats_vf_index {
6925 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
6926 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
6927 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
6928 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
6929 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
6930 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
6931 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
6932 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
6933 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
6934 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
6935 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
6936 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
6937 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
6938 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
6939 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
6940 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
6941 };
6942
6943 /* VI PF stats offset definitions */
6944 #define VI_PF_NUM_STATS 17
6945 enum fw_vi_stats_pf_index {
6946 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
6947 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
6948 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
6949 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
6950 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
6951 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
6952 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
6953 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
6954 FW_VI_PF_STAT_RX_BYTES_IX,
6955 FW_VI_PF_STAT_RX_FRAMES_IX,
6956 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
6957 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
6958 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
6959 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
6960 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
6961 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
6962 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
6963 };
6964
6965 struct fw_vi_stats_cmd {
6966 __be32 op_to_viid;
6967 __be32 retval_len16;
6968 union fw_vi_stats {
6969 struct fw_vi_stats_ctl {
6970 __be16 nstats_ix;
6971 __be16 r6;
6972 __be32 r7;
6973 __be64 stat0;
6974 __be64 stat1;
6975 __be64 stat2;
6976 __be64 stat3;
6977 __be64 stat4;
6978 __be64 stat5;
6979 } ctl;
6980 struct fw_vi_stats_pf {
6981 __be64 tx_bcast_bytes;
6982 __be64 tx_bcast_frames;
6983 __be64 tx_mcast_bytes;
6984 __be64 tx_mcast_frames;
6985 __be64 tx_ucast_bytes;
6986 __be64 tx_ucast_frames;
6987 __be64 tx_offload_bytes;
6988 __be64 tx_offload_frames;
6989 __be64 rx_pf_bytes;
6990 __be64 rx_pf_frames;
6991 __be64 rx_bcast_bytes;
6992 __be64 rx_bcast_frames;
6993 __be64 rx_mcast_bytes;
6994 __be64 rx_mcast_frames;
6995 __be64 rx_ucast_bytes;
6996 __be64 rx_ucast_frames;
6997 __be64 rx_err_frames;
6998 } pf;
6999 struct fw_vi_stats_vf {
7000 __be64 tx_bcast_bytes;
7001 __be64 tx_bcast_frames;
7002 __be64 tx_mcast_bytes;
7003 __be64 tx_mcast_frames;
7004 __be64 tx_ucast_bytes;
7005 __be64 tx_ucast_frames;
7006 __be64 tx_drop_frames;
7007 __be64 tx_offload_bytes;
7008 __be64 tx_offload_frames;
7009 __be64 rx_bcast_bytes;
7010 __be64 rx_bcast_frames;
7011 __be64 rx_mcast_bytes;
7012 __be64 rx_mcast_frames;
7013 __be64 rx_ucast_bytes;
7014 __be64 rx_ucast_frames;
7015 __be64 rx_err_frames;
7016 } vf;
7017 } u;
7018 };
7019
7020 #define S_FW_VI_STATS_CMD_VIID 0
7021 #define M_FW_VI_STATS_CMD_VIID 0xfff
7022 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
7023 #define G_FW_VI_STATS_CMD_VIID(x) \
7024 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID)
7025
7026 #define S_FW_VI_STATS_CMD_NSTATS 12
7027 #define M_FW_VI_STATS_CMD_NSTATS 0x7
7028 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
7029 #define G_FW_VI_STATS_CMD_NSTATS(x) \
7030 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS)
7031
7032 #define S_FW_VI_STATS_CMD_IX 0
7033 #define M_FW_VI_STATS_CMD_IX 0x1f
7034 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
7035 #define G_FW_VI_STATS_CMD_IX(x) \
7036 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX)
7037
7038 struct fw_acl_mac_cmd {
7039 __be32 op_to_vfn;
7040 __be32 en_to_len16;
7041 __u8 nmac;
7042 __u8 r3[7];
7043 __be16 r4;
7044 __u8 macaddr0[6];
7045 __be16 r5;
7046 __u8 macaddr1[6];
7047 __be16 r6;
7048 __u8 macaddr2[6];
7049 __be16 r7;
7050 __u8 macaddr3[6];
7051 };
7052
7053 #define S_FW_ACL_MAC_CMD_PFN 8
7054 #define M_FW_ACL_MAC_CMD_PFN 0x7
7055 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN)
7056 #define G_FW_ACL_MAC_CMD_PFN(x) \
7057 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN)
7058
7059 #define S_FW_ACL_MAC_CMD_VFN 0
7060 #define M_FW_ACL_MAC_CMD_VFN 0xff
7061 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN)
7062 #define G_FW_ACL_MAC_CMD_VFN(x) \
7063 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN)
7064
7065 #define S_FW_ACL_MAC_CMD_EN 31
7066 #define M_FW_ACL_MAC_CMD_EN 0x1
7067 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN)
7068 #define G_FW_ACL_MAC_CMD_EN(x) \
7069 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN)
7070 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U)
7071
7072 struct fw_acl_vlan_cmd {
7073 __be32 op_to_vfn;
7074 __be32 en_to_len16;
7075 __u8 nvlan;
7076 __u8 dropnovlan_fm;
7077 __u8 r3_lo[6];
7078 __be16 vlanid[16];
7079 };
7080
7081 #define S_FW_ACL_VLAN_CMD_PFN 8
7082 #define M_FW_ACL_VLAN_CMD_PFN 0x7
7083 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN)
7084 #define G_FW_ACL_VLAN_CMD_PFN(x) \
7085 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN)
7086
7087 #define S_FW_ACL_VLAN_CMD_VFN 0
7088 #define M_FW_ACL_VLAN_CMD_VFN 0xff
7089 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN)
7090 #define G_FW_ACL_VLAN_CMD_VFN(x) \
7091 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN)
7092
7093 #define S_FW_ACL_VLAN_CMD_EN 31
7094 #define M_FW_ACL_VLAN_CMD_EN 0x1
7095 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN)
7096 #define G_FW_ACL_VLAN_CMD_EN(x) \
7097 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN)
7098 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U)
7099
7100 #define S_FW_ACL_VLAN_CMD_TRANSPARENT 30
7101 #define M_FW_ACL_VLAN_CMD_TRANSPARENT 0x1
7102 #define V_FW_ACL_VLAN_CMD_TRANSPARENT(x) \
7103 ((x) << S_FW_ACL_VLAN_CMD_TRANSPARENT)
7104 #define G_FW_ACL_VLAN_CMD_TRANSPARENT(x) \
7105 (((x) >> S_FW_ACL_VLAN_CMD_TRANSPARENT) & M_FW_ACL_VLAN_CMD_TRANSPARENT)
7106 #define F_FW_ACL_VLAN_CMD_TRANSPARENT V_FW_ACL_VLAN_CMD_TRANSPARENT(1U)
7107
7108 #define S_FW_ACL_VLAN_CMD_PMASK 16
7109 #define M_FW_ACL_VLAN_CMD_PMASK 0xf
7110 #define V_FW_ACL_VLAN_CMD_PMASK(x) ((x) << S_FW_ACL_VLAN_CMD_PMASK)
7111 #define G_FW_ACL_VLAN_CMD_PMASK(x) \
7112 (((x) >> S_FW_ACL_VLAN_CMD_PMASK) & M_FW_ACL_VLAN_CMD_PMASK)
7113
7114 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7
7115 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1
7116 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN)
7117 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \
7118 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN)
7119 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U)
7120
7121 #define S_FW_ACL_VLAN_CMD_FM 6
7122 #define M_FW_ACL_VLAN_CMD_FM 0x1
7123 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM)
7124 #define G_FW_ACL_VLAN_CMD_FM(x) \
7125 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM)
7126 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U)
7127
7128 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */
7129 enum fw_port_cap {
7130 FW_PORT_CAP_SPEED_100M = 0x0001,
7131 FW_PORT_CAP_SPEED_1G = 0x0002,
7132 FW_PORT_CAP_SPEED_25G = 0x0004,
7133 FW_PORT_CAP_SPEED_10G = 0x0008,
7134 FW_PORT_CAP_SPEED_40G = 0x0010,
7135 FW_PORT_CAP_SPEED_100G = 0x0020,
7136 FW_PORT_CAP_FC_RX = 0x0040,
7137 FW_PORT_CAP_FC_TX = 0x0080,
7138 FW_PORT_CAP_ANEG = 0x0100,
7139 FW_PORT_CAP_MDIAUTO = 0x0200,
7140 FW_PORT_CAP_MDISTRAIGHT = 0x0400,
7141 FW_PORT_CAP_FEC_RS = 0x0800,
7142 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
7143 FW_PORT_CAP_FORCE_PAUSE = 0x2000,
7144 FW_PORT_CAP_802_3_PAUSE = 0x4000,
7145 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
7146 };
7147
7148 #define S_FW_PORT_CAP_SPEED 0
7149 #define M_FW_PORT_CAP_SPEED 0x3f
7150 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
7151 #define G_FW_PORT_CAP_SPEED(x) \
7152 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
7153
7154 #define S_FW_PORT_CAP_FC 6
7155 #define M_FW_PORT_CAP_FC 0x3
7156 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC)
7157 #define G_FW_PORT_CAP_FC(x) \
7158 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC)
7159
7160 #define S_FW_PORT_CAP_ANEG 8
7161 #define M_FW_PORT_CAP_ANEG 0x1
7162 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG)
7163 #define G_FW_PORT_CAP_ANEG(x) \
7164 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)
7165
7166 #define S_FW_PORT_CAP_FEC 11
7167 #define M_FW_PORT_CAP_FEC 0x3
7168 #define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC)
7169 #define G_FW_PORT_CAP_FEC(x) \
7170 (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC)
7171
7172 #define S_FW_PORT_CAP_FORCE_PAUSE 13
7173 #define M_FW_PORT_CAP_FORCE_PAUSE 0x1
7174 #define V_FW_PORT_CAP_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP_FORCE_PAUSE)
7175 #define G_FW_PORT_CAP_FORCE_PAUSE(x) \
7176 (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE)
7177
7178 #define S_FW_PORT_CAP_802_3 14
7179 #define M_FW_PORT_CAP_802_3 0x3
7180 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3)
7181 #define G_FW_PORT_CAP_802_3(x) \
7182 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3)
7183
7184 enum fw_port_mdi {
7185 FW_PORT_CAP_MDI_UNCHANGED,
7186 FW_PORT_CAP_MDI_AUTO,
7187 FW_PORT_CAP_MDI_F_STRAIGHT,
7188 FW_PORT_CAP_MDI_F_CROSSOVER
7189 };
7190
7191 #define S_FW_PORT_CAP_MDI 9
7192 #define M_FW_PORT_CAP_MDI 3
7193 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
7194 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
7195
7196 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
7197 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
7198 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
7199 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
7200 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
7201 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
7202 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
7203 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
7204 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL
7205 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL
7206 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL
7207 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL
7208 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL
7209 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL
7210 #define FW_PORT_CAP32_FC_RX 0x00010000UL
7211 #define FW_PORT_CAP32_FC_TX 0x00020000UL
7212 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
7213 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
7214 #define FW_PORT_CAP32_ANEG 0x00100000UL
7215 #define FW_PORT_CAP32_MDIAUTO 0x00200000UL
7216 #define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL
7217 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
7218 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
7219 #define FW_PORT_CAP32_FEC_NO_FEC 0x02000000UL
7220 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL
7221 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL
7222 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL
7223 #define FW_PORT_CAP32_FORCE_FEC 0x20000000UL
7224 #define FW_PORT_CAP32_RESERVED2 0xc0000000UL
7225
7226 #define S_FW_PORT_CAP32_SPEED 0
7227 #define M_FW_PORT_CAP32_SPEED 0xfff
7228 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
7229 #define G_FW_PORT_CAP32_SPEED(x) \
7230 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
7231
7232 #define S_FW_PORT_CAP32_FC 16
7233 #define M_FW_PORT_CAP32_FC 0x3
7234 #define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC)
7235 #define G_FW_PORT_CAP32_FC(x) \
7236 (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC)
7237
7238 #define S_FW_PORT_CAP32_802_3 18
7239 #define M_FW_PORT_CAP32_802_3 0x3
7240 #define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3)
7241 #define G_FW_PORT_CAP32_802_3(x) \
7242 (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3)
7243
7244 #define S_FW_PORT_CAP32_ANEG 20
7245 #define M_FW_PORT_CAP32_ANEG 0x1
7246 #define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG)
7247 #define G_FW_PORT_CAP32_ANEG(x) \
7248 (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG)
7249
7250 #define S_FW_PORT_CAP32_FORCE_PAUSE 28
7251 #define M_FW_PORT_CAP32_FORCE_PAUSE 0x1
7252 #define V_FW_PORT_CAP32_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP32_FORCE_PAUSE)
7253 #define G_FW_PORT_CAP32_FORCE_PAUSE(x) \
7254 (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE)
7255
7256 enum fw_port_mdi32 {
7257 FW_PORT_CAP32_MDI_UNCHANGED,
7258 FW_PORT_CAP32_MDI_AUTO,
7259 FW_PORT_CAP32_MDI_F_STRAIGHT,
7260 FW_PORT_CAP32_MDI_F_CROSSOVER
7261 };
7262
7263 #define S_FW_PORT_CAP32_MDI 21
7264 #define M_FW_PORT_CAP32_MDI 3
7265 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
7266 #define G_FW_PORT_CAP32_MDI(x) \
7267 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
7268
7269 #define S_FW_PORT_CAP32_FEC 23
7270 #define M_FW_PORT_CAP32_FEC 0x1f
7271 #define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC)
7272 #define G_FW_PORT_CAP32_FEC(x) \
7273 (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC)
7274
7275 /* macros to isolate various 32-bit Port Capabilities sub-fields */
7276 #define CAP32_SPEED(__cap32) \
7277 (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32)
7278
7279 #define CAP32_FEC(__cap32) \
7280 (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32)
7281
7282 #define CAP32_FC(__cap32) \
7283 (V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32)
7284
7285 static inline bool
7286 fec_supported(uint32_t caps)
7287 {
7288
7289 return ((caps & (FW_PORT_CAP32_SPEED_25G | FW_PORT_CAP32_SPEED_50G |
7290 FW_PORT_CAP32_SPEED_100G)) != 0);
7291 }
7292
7293 enum fw_port_action {
7294 FW_PORT_ACTION_L1_CFG = 0x0001,
7295 FW_PORT_ACTION_L2_CFG = 0x0002,
7296 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
7297 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
7298 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
7299 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
7300 FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
7301 FW_PORT_ACTION_DCB_READ_DET = 0x0008,
7302 FW_PORT_ACTION_L1_CFG32 = 0x0009,
7303 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
7304 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
7305 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
7306 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
7307 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
7308 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022,
7309 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023,
7310 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025,
7311 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026,
7312 FW_PORT_ACTION_DIAGNOSTICS = 0x0027,
7313 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028,
7314 FW_PORT_ACTION_PHY_RESET = 0x0040,
7315 FW_PORT_ACTION_PMA_RESET = 0x0041,
7316 FW_PORT_ACTION_PCS_RESET = 0x0042,
7317 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
7318 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
7319 FW_PORT_ACTION_AN_RESET = 0x0045,
7320 };
7321
7322 enum fw_port_l2cfg_ctlbf {
7323 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
7324 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
7325 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
7326 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
7327 FW_PORT_L2_CTLBF_IVLAN = 0x10,
7328 FW_PORT_L2_CTLBF_TXIPG = 0x20,
7329 FW_PORT_L2_CTLBF_MTU = 0x40,
7330 FW_PORT_L2_CTLBF_OVLAN_FILT = 0x80,
7331 };
7332
7333 enum fw_dcb_app_tlv_sf {
7334 FW_DCB_APP_SF_ETHERTYPE,
7335 FW_DCB_APP_SF_SOCKET_TCP,
7336 FW_DCB_APP_SF_SOCKET_UDP,
7337 FW_DCB_APP_SF_SOCKET_ALL,
7338 };
7339
7340 enum fw_port_dcb_versions {
7341 FW_PORT_DCB_VER_UNKNOWN,
7342 FW_PORT_DCB_VER_CEE1D0,
7343 FW_PORT_DCB_VER_CEE1D01,
7344 FW_PORT_DCB_VER_IEEE,
7345 FW_PORT_DCB_VER_AUTO=7
7346 };
7347
7348 enum fw_port_dcb_cfg {
7349 FW_PORT_DCB_CFG_PG = 0x01,
7350 FW_PORT_DCB_CFG_PFC = 0x02,
7351 FW_PORT_DCB_CFG_APPL = 0x04
7352 };
7353
7354 enum fw_port_dcb_cfg_rc {
7355 FW_PORT_DCB_CFG_SUCCESS = 0x0,
7356 FW_PORT_DCB_CFG_ERROR = 0x1
7357 };
7358
7359 enum fw_port_dcb_type {
7360 FW_PORT_DCB_TYPE_PGID = 0x00,
7361 FW_PORT_DCB_TYPE_PGRATE = 0x01,
7362 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
7363 FW_PORT_DCB_TYPE_PFC = 0x03,
7364 FW_PORT_DCB_TYPE_APP_ID = 0x04,
7365 FW_PORT_DCB_TYPE_CONTROL = 0x05,
7366 };
7367
7368 enum fw_port_dcb_feature_state {
7369 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
7370 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
7371 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
7372 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
7373 };
7374
7375 enum fw_port_diag_ops {
7376 FW_PORT_DIAGS_TEMP = 0x00,
7377 FW_PORT_DIAGS_TX_POWER = 0x01,
7378 FW_PORT_DIAGS_RX_POWER = 0x02,
7379 FW_PORT_DIAGS_TX_DIS = 0x03,
7380 };
7381
7382 struct fw_port_cmd {
7383 __be32 op_to_portid;
7384 __be32 action_to_len16;
7385 union fw_port {
7386 struct fw_port_l1cfg {
7387 __be32 rcap;
7388 __be32 r;
7389 } l1cfg;
7390 struct fw_port_l2cfg {
7391 __u8 ctlbf;
7392 __u8 ovlan3_to_ivlan0;
7393 __be16 ivlantype;
7394 __be16 txipg_force_pinfo;
7395 __be16 mtu;
7396 __be16 ovlan0mask;
7397 __be16 ovlan0type;
7398 __be16 ovlan1mask;
7399 __be16 ovlan1type;
7400 __be16 ovlan2mask;
7401 __be16 ovlan2type;
7402 __be16 ovlan3mask;
7403 __be16 ovlan3type;
7404 } l2cfg;
7405 struct fw_port_info {
7406 __be32 lstatus_to_modtype;
7407 __be16 pcap;
7408 __be16 acap;
7409 __be16 mtu;
7410 __u8 cbllen;
7411 __u8 auxlinfo;
7412 __u8 dcbxdis_pkd;
7413 __u8 r8_lo;
7414 __be16 lpacap;
7415 __be64 r9;
7416 } info;
7417 struct fw_port_diags {
7418 __u8 diagop;
7419 __u8 r[3];
7420 __be32 diagval;
7421 } diags;
7422 union fw_port_dcb {
7423 struct fw_port_dcb_pgid {
7424 __u8 type;
7425 __u8 apply_pkd;
7426 __u8 r10_lo[2];
7427 __be32 pgid;
7428 __be64 r11;
7429 } pgid;
7430 struct fw_port_dcb_pgrate {
7431 __u8 type;
7432 __u8 apply_pkd;
7433 __u8 r10_lo[5];
7434 __u8 num_tcs_supported;
7435 __u8 pgrate[8];
7436 __u8 tsa[8];
7437 } pgrate;
7438 struct fw_port_dcb_priorate {
7439 __u8 type;
7440 __u8 apply_pkd;
7441 __u8 r10_lo[6];
7442 __u8 strict_priorate[8];
7443 } priorate;
7444 struct fw_port_dcb_pfc {
7445 __u8 type;
7446 __u8 pfcen;
7447 __u8 apply_pkd;
7448 __u8 r10_lo[4];
7449 __u8 max_pfc_tcs;
7450 __be64 r11;
7451 } pfc;
7452 struct fw_port_app_priority {
7453 __u8 type;
7454 __u8 apply_pkd;
7455 __u8 r10_lo;
7456 __u8 idx;
7457 __u8 user_prio_map;
7458 __u8 sel_field;
7459 __be16 protocolid;
7460 __be64 r12;
7461 } app_priority;
7462 struct fw_port_dcb_control {
7463 __u8 type;
7464 __u8 all_syncd_pkd;
7465 __be16 dcb_version_to_app_state;
7466 __be32 r11;
7467 __be64 r12;
7468 } control;
7469 } dcb;
7470 struct fw_port_l1cfg32 {
7471 __be32 rcap32;
7472 __be32 r;
7473 } l1cfg32;
7474 struct fw_port_info32 {
7475 __be32 lstatus32_to_cbllen32;
7476 __be32 auxlinfo32_mtu32;
7477 __be32 linkattr32;
7478 __be32 pcaps32;
7479 __be32 acaps32;
7480 __be32 lpacaps32;
7481 } info32;
7482 } u;
7483 };
7484
7485 #define S_FW_PORT_CMD_READ 22
7486 #define M_FW_PORT_CMD_READ 0x1
7487 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ)
7488 #define G_FW_PORT_CMD_READ(x) \
7489 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ)
7490 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U)
7491
7492 #define S_FW_PORT_CMD_PORTID 0
7493 #define M_FW_PORT_CMD_PORTID 0xf
7494 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
7495 #define G_FW_PORT_CMD_PORTID(x) \
7496 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
7497
7498 #define S_FW_PORT_CMD_ACTION 16
7499 #define M_FW_PORT_CMD_ACTION 0xffff
7500 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
7501 #define G_FW_PORT_CMD_ACTION(x) \
7502 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
7503
7504 #define S_FW_PORT_CMD_OVLAN3 7
7505 #define M_FW_PORT_CMD_OVLAN3 0x1
7506 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3)
7507 #define G_FW_PORT_CMD_OVLAN3(x) \
7508 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3)
7509 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U)
7510
7511 #define S_FW_PORT_CMD_OVLAN2 6
7512 #define M_FW_PORT_CMD_OVLAN2 0x1
7513 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2)
7514 #define G_FW_PORT_CMD_OVLAN2(x) \
7515 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2)
7516 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U)
7517
7518 #define S_FW_PORT_CMD_OVLAN1 5
7519 #define M_FW_PORT_CMD_OVLAN1 0x1
7520 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1)
7521 #define G_FW_PORT_CMD_OVLAN1(x) \
7522 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1)
7523 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U)
7524
7525 #define S_FW_PORT_CMD_OVLAN0 4
7526 #define M_FW_PORT_CMD_OVLAN0 0x1
7527 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0)
7528 #define G_FW_PORT_CMD_OVLAN0(x) \
7529 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0)
7530 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U)
7531
7532 #define S_FW_PORT_CMD_IVLAN0 3
7533 #define M_FW_PORT_CMD_IVLAN0 0x1
7534 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0)
7535 #define G_FW_PORT_CMD_IVLAN0(x) \
7536 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)
7537 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U)
7538
7539 #define S_FW_PORT_CMD_OVLAN_FILT 2
7540 #define M_FW_PORT_CMD_OVLAN_FILT 0x1
7541 #define V_FW_PORT_CMD_OVLAN_FILT(x) ((x) << S_FW_PORT_CMD_OVLAN_FILT)
7542 #define G_FW_PORT_CMD_OVLAN_FILT(x) \
7543 (((x) >> S_FW_PORT_CMD_OVLAN_FILT) & M_FW_PORT_CMD_OVLAN_FILT)
7544 #define F_FW_PORT_CMD_OVLAN_FILT V_FW_PORT_CMD_OVLAN_FILT(1U)
7545
7546 #define S_FW_PORT_CMD_TXIPG 3
7547 #define M_FW_PORT_CMD_TXIPG 0x1fff
7548 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG)
7549 #define G_FW_PORT_CMD_TXIPG(x) \
7550 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG)
7551
7552 #define S_FW_PORT_CMD_FORCE_PINFO 0
7553 #define M_FW_PORT_CMD_FORCE_PINFO 0x1
7554 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO)
7555 #define G_FW_PORT_CMD_FORCE_PINFO(x) \
7556 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO)
7557 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U)
7558
7559 #define S_FW_PORT_CMD_LSTATUS 31
7560 #define M_FW_PORT_CMD_LSTATUS 0x1
7561 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
7562 #define G_FW_PORT_CMD_LSTATUS(x) \
7563 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
7564 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
7565
7566 #define S_FW_PORT_CMD_LSPEED 24
7567 #define M_FW_PORT_CMD_LSPEED 0x3f
7568 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
7569 #define G_FW_PORT_CMD_LSPEED(x) \
7570 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
7571
7572 #define S_FW_PORT_CMD_TXPAUSE 23
7573 #define M_FW_PORT_CMD_TXPAUSE 0x1
7574 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
7575 #define G_FW_PORT_CMD_TXPAUSE(x) \
7576 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
7577 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
7578
7579 #define S_FW_PORT_CMD_RXPAUSE 22
7580 #define M_FW_PORT_CMD_RXPAUSE 0x1
7581 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
7582 #define G_FW_PORT_CMD_RXPAUSE(x) \
7583 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
7584 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
7585
7586 #define S_FW_PORT_CMD_MDIOCAP 21
7587 #define M_FW_PORT_CMD_MDIOCAP 0x1
7588 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
7589 #define G_FW_PORT_CMD_MDIOCAP(x) \
7590 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
7591 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
7592
7593 #define S_FW_PORT_CMD_MDIOADDR 16
7594 #define M_FW_PORT_CMD_MDIOADDR 0x1f
7595 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
7596 #define G_FW_PORT_CMD_MDIOADDR(x) \
7597 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
7598
7599 #define S_FW_PORT_CMD_LPTXPAUSE 15
7600 #define M_FW_PORT_CMD_LPTXPAUSE 0x1
7601 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE)
7602 #define G_FW_PORT_CMD_LPTXPAUSE(x) \
7603 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE)
7604 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U)
7605
7606 #define S_FW_PORT_CMD_LPRXPAUSE 14
7607 #define M_FW_PORT_CMD_LPRXPAUSE 0x1
7608 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE)
7609 #define G_FW_PORT_CMD_LPRXPAUSE(x) \
7610 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE)
7611 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U)
7612
7613 #define S_FW_PORT_CMD_PTYPE 8
7614 #define M_FW_PORT_CMD_PTYPE 0x1f
7615 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
7616 #define G_FW_PORT_CMD_PTYPE(x) \
7617 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
7618
7619 #define S_FW_PORT_CMD_LINKDNRC 5
7620 #define M_FW_PORT_CMD_LINKDNRC 0x7
7621 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
7622 #define G_FW_PORT_CMD_LINKDNRC(x) \
7623 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
7624
7625 #define S_FW_PORT_CMD_MODTYPE 0
7626 #define M_FW_PORT_CMD_MODTYPE 0x1f
7627 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
7628 #define G_FW_PORT_CMD_MODTYPE(x) \
7629 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
7630
7631 #define S_FW_PORT_AUXLINFO_KX4 2
7632 #define M_FW_PORT_AUXLINFO_KX4 0x1
7633 #define V_FW_PORT_AUXLINFO_KX4(x) \
7634 ((x) << S_FW_PORT_AUXLINFO_KX4)
7635 #define G_FW_PORT_AUXLINFO_KX4(x) \
7636 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)
7637 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U)
7638
7639 #define S_FW_PORT_AUXLINFO_KR 1
7640 #define M_FW_PORT_AUXLINFO_KR 0x1
7641 #define V_FW_PORT_AUXLINFO_KR(x) \
7642 ((x) << S_FW_PORT_AUXLINFO_KR)
7643 #define G_FW_PORT_AUXLINFO_KR(x) \
7644 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)
7645 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U)
7646
7647 #define S_FW_PORT_CMD_DCBXDIS 7
7648 #define M_FW_PORT_CMD_DCBXDIS 0x1
7649 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS)
7650 #define G_FW_PORT_CMD_DCBXDIS(x) \
7651 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS)
7652 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U)
7653
7654 #define S_FW_PORT_CMD_APPLY 7
7655 #define M_FW_PORT_CMD_APPLY 0x1
7656 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY)
7657 #define G_FW_PORT_CMD_APPLY(x) \
7658 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
7659 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U)
7660
7661 #define S_FW_PORT_CMD_ALL_SYNCD 7
7662 #define M_FW_PORT_CMD_ALL_SYNCD 0x1
7663 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD)
7664 #define G_FW_PORT_CMD_ALL_SYNCD(x) \
7665 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD)
7666 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U)
7667
7668 #define S_FW_PORT_CMD_DCB_VERSION 12
7669 #define M_FW_PORT_CMD_DCB_VERSION 0x7
7670 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION)
7671 #define G_FW_PORT_CMD_DCB_VERSION(x) \
7672 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION)
7673
7674 #define S_FW_PORT_CMD_PFC_STATE 8
7675 #define M_FW_PORT_CMD_PFC_STATE 0xf
7676 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE)
7677 #define G_FW_PORT_CMD_PFC_STATE(x) \
7678 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE)
7679
7680 #define S_FW_PORT_CMD_ETS_STATE 4
7681 #define M_FW_PORT_CMD_ETS_STATE 0xf
7682 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE)
7683 #define G_FW_PORT_CMD_ETS_STATE(x) \
7684 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE)
7685
7686 #define S_FW_PORT_CMD_APP_STATE 0
7687 #define M_FW_PORT_CMD_APP_STATE 0xf
7688 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE)
7689 #define G_FW_PORT_CMD_APP_STATE(x) \
7690 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE)
7691
7692 #define S_FW_PORT_CMD_LSTATUS32 31
7693 #define M_FW_PORT_CMD_LSTATUS32 0x1
7694 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
7695 #define G_FW_PORT_CMD_LSTATUS32(x) \
7696 (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32)
7697 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
7698
7699 #define S_FW_PORT_CMD_LINKDNRC32 28
7700 #define M_FW_PORT_CMD_LINKDNRC32 0x7
7701 #define V_FW_PORT_CMD_LINKDNRC32(x) ((x) << S_FW_PORT_CMD_LINKDNRC32)
7702 #define G_FW_PORT_CMD_LINKDNRC32(x) \
7703 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
7704
7705 #define S_FW_PORT_CMD_DCBXDIS32 27
7706 #define M_FW_PORT_CMD_DCBXDIS32 0x1
7707 #define V_FW_PORT_CMD_DCBXDIS32(x) ((x) << S_FW_PORT_CMD_DCBXDIS32)
7708 #define G_FW_PORT_CMD_DCBXDIS32(x) \
7709 (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32)
7710 #define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U)
7711
7712 #define S_FW_PORT_CMD_MDIOCAP32 26
7713 #define M_FW_PORT_CMD_MDIOCAP32 0x1
7714 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
7715 #define G_FW_PORT_CMD_MDIOCAP32(x) \
7716 (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32)
7717 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
7718
7719 #define S_FW_PORT_CMD_MDIOADDR32 21
7720 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
7721 #define V_FW_PORT_CMD_MDIOADDR32(x) ((x) << S_FW_PORT_CMD_MDIOADDR32)
7722 #define G_FW_PORT_CMD_MDIOADDR32(x) \
7723 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
7724
7725 #define S_FW_PORT_CMD_PORTTYPE32 13
7726 #define M_FW_PORT_CMD_PORTTYPE32 0xff
7727 #define V_FW_PORT_CMD_PORTTYPE32(x) ((x) << S_FW_PORT_CMD_PORTTYPE32)
7728 #define G_FW_PORT_CMD_PORTTYPE32(x) \
7729 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
7730
7731 #define S_FW_PORT_CMD_MODTYPE32 8
7732 #define M_FW_PORT_CMD_MODTYPE32 0x1f
7733 #define V_FW_PORT_CMD_MODTYPE32(x) ((x) << S_FW_PORT_CMD_MODTYPE32)
7734 #define G_FW_PORT_CMD_MODTYPE32(x) \
7735 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
7736
7737 #define S_FW_PORT_CMD_CBLLEN32 0
7738 #define M_FW_PORT_CMD_CBLLEN32 0xff
7739 #define V_FW_PORT_CMD_CBLLEN32(x) ((x) << S_FW_PORT_CMD_CBLLEN32)
7740 #define G_FW_PORT_CMD_CBLLEN32(x) \
7741 (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32)
7742
7743 #define S_FW_PORT_CMD_AUXLINFO32 24
7744 #define M_FW_PORT_CMD_AUXLINFO32 0xff
7745 #define V_FW_PORT_CMD_AUXLINFO32(x) ((x) << S_FW_PORT_CMD_AUXLINFO32)
7746 #define G_FW_PORT_CMD_AUXLINFO32(x) \
7747 (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32)
7748
7749 #define S_FW_PORT_AUXLINFO32_KX4 2
7750 #define M_FW_PORT_AUXLINFO32_KX4 0x1
7751 #define V_FW_PORT_AUXLINFO32_KX4(x) \
7752 ((x) << S_FW_PORT_AUXLINFO32_KX4)
7753 #define G_FW_PORT_AUXLINFO32_KX4(x) \
7754 (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4)
7755 #define F_FW_PORT_AUXLINFO32_KX4 V_FW_PORT_AUXLINFO32_KX4(1U)
7756
7757 #define S_FW_PORT_AUXLINFO32_KR 1
7758 #define M_FW_PORT_AUXLINFO32_KR 0x1
7759 #define V_FW_PORT_AUXLINFO32_KR(x) \
7760 ((x) << S_FW_PORT_AUXLINFO32_KR)
7761 #define G_FW_PORT_AUXLINFO32_KR(x) \
7762 (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR)
7763 #define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U)
7764
7765 #define S_FW_PORT_CMD_MTU32 0
7766 #define M_FW_PORT_CMD_MTU32 0xffff
7767 #define V_FW_PORT_CMD_MTU32(x) ((x) << S_FW_PORT_CMD_MTU32)
7768 #define G_FW_PORT_CMD_MTU32(x) \
7769 (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32)
7770
7771 /*
7772 * These are configured into the VPD and hence tools that generate
7773 * VPD may use this enumeration.
7774 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
7775 *
7776 * REMEMBER:
7777 * Update the Common Code t4_hw.c:t4_get_port_type_description()
7778 * with any new Firmware Port Technology Types!
7779 */
7780 enum fw_port_type {
7781 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
7782 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
7783 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
7784 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */
7785 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */
7786 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
7787 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
7788 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
7789 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
7790 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
7791 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
7792 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
7793 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
7794 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
7795 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
7796 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
7797 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
7798 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
7799 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
7800 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
7801 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
7802 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
7803 FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/
7804 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
7805 };
7806
7807 static inline bool
7808 is_bt(enum fw_port_type port_type)
7809 {
7810 return (port_type == FW_PORT_TYPE_BT_SGMII ||
7811 port_type == FW_PORT_TYPE_BT_XFI ||
7812 port_type == FW_PORT_TYPE_BT_XAUI);
7813 }
7814
7815 /* These are read from module's EEPROM and determined once the
7816 module is inserted. */
7817 enum fw_port_module_type {
7818 FW_PORT_MOD_TYPE_NA = 0x0,
7819 FW_PORT_MOD_TYPE_LR = 0x1,
7820 FW_PORT_MOD_TYPE_SR = 0x2,
7821 FW_PORT_MOD_TYPE_ER = 0x3,
7822 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
7823 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
7824 FW_PORT_MOD_TYPE_LRM = 0x6,
7825 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
7826 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
7827 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
7828 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
7829 };
7830
7831 /* used by FW and tools may use this to generate VPD */
7832 enum fw_port_mod_sub_type {
7833 FW_PORT_MOD_SUB_TYPE_NA,
7834 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1,
7835 FW_PORT_MOD_SUB_TYPE_TN8022=0x2,
7836 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3,
7837 FW_PORT_MOD_SUB_TYPE_88x3120=0x4,
7838 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5,
7839 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6,
7840 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7,
7841 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8,
7842
7843 /*
7844 * The following will never been in the VPD. They are TWINAX cable
7845 * lengths decoded from SFP+ module i2c PROMs. These should almost
7846 * certainly go somewhere else ...
7847 */
7848 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9,
7849 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA,
7850 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB,
7851 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC,
7852 };
7853
7854 /* link down reason codes (3b) */
7855 enum fw_port_link_dn_rc {
7856 FW_PORT_LINK_DN_RC_NONE,
7857 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
7858 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
7859 FW_PORT_LINK_DN_RESERVED3,
7860 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
7861 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
7862 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
7863 FW_PORT_LINK_DN_RESERVED7
7864 };
7865 enum fw_port_stats_tx_index {
7866 FW_STAT_TX_PORT_BYTES_IX = 0,
7867 FW_STAT_TX_PORT_FRAMES_IX,
7868 FW_STAT_TX_PORT_BCAST_IX,
7869 FW_STAT_TX_PORT_MCAST_IX,
7870 FW_STAT_TX_PORT_UCAST_IX,
7871 FW_STAT_TX_PORT_ERROR_IX,
7872 FW_STAT_TX_PORT_64B_IX,
7873 FW_STAT_TX_PORT_65B_127B_IX,
7874 FW_STAT_TX_PORT_128B_255B_IX,
7875 FW_STAT_TX_PORT_256B_511B_IX,
7876 FW_STAT_TX_PORT_512B_1023B_IX,
7877 FW_STAT_TX_PORT_1024B_1518B_IX,
7878 FW_STAT_TX_PORT_1519B_MAX_IX,
7879 FW_STAT_TX_PORT_DROP_IX,
7880 FW_STAT_TX_PORT_PAUSE_IX,
7881 FW_STAT_TX_PORT_PPP0_IX,
7882 FW_STAT_TX_PORT_PPP1_IX,
7883 FW_STAT_TX_PORT_PPP2_IX,
7884 FW_STAT_TX_PORT_PPP3_IX,
7885 FW_STAT_TX_PORT_PPP4_IX,
7886 FW_STAT_TX_PORT_PPP5_IX,
7887 FW_STAT_TX_PORT_PPP6_IX,
7888 FW_STAT_TX_PORT_PPP7_IX,
7889 FW_NUM_PORT_TX_STATS
7890 };
7891
7892 enum fw_port_stat_rx_index {
7893 FW_STAT_RX_PORT_BYTES_IX = 0,
7894 FW_STAT_RX_PORT_FRAMES_IX,
7895 FW_STAT_RX_PORT_BCAST_IX,
7896 FW_STAT_RX_PORT_MCAST_IX,
7897 FW_STAT_RX_PORT_UCAST_IX,
7898 FW_STAT_RX_PORT_MTU_ERROR_IX,
7899 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
7900 FW_STAT_RX_PORT_CRC_ERROR_IX,
7901 FW_STAT_RX_PORT_LEN_ERROR_IX,
7902 FW_STAT_RX_PORT_SYM_ERROR_IX,
7903 FW_STAT_RX_PORT_64B_IX,
7904 FW_STAT_RX_PORT_65B_127B_IX,
7905 FW_STAT_RX_PORT_128B_255B_IX,
7906 FW_STAT_RX_PORT_256B_511B_IX,
7907 FW_STAT_RX_PORT_512B_1023B_IX,
7908 FW_STAT_RX_PORT_1024B_1518B_IX,
7909 FW_STAT_RX_PORT_1519B_MAX_IX,
7910 FW_STAT_RX_PORT_PAUSE_IX,
7911 FW_STAT_RX_PORT_PPP0_IX,
7912 FW_STAT_RX_PORT_PPP1_IX,
7913 FW_STAT_RX_PORT_PPP2_IX,
7914 FW_STAT_RX_PORT_PPP3_IX,
7915 FW_STAT_RX_PORT_PPP4_IX,
7916 FW_STAT_RX_PORT_PPP5_IX,
7917 FW_STAT_RX_PORT_PPP6_IX,
7918 FW_STAT_RX_PORT_PPP7_IX,
7919 FW_STAT_RX_PORT_LESS_64B_IX,
7920 FW_STAT_RX_PORT_MAC_ERROR_IX,
7921 FW_NUM_PORT_RX_STATS
7922 };
7923 /* port stats */
7924 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \
7925 FW_NUM_PORT_RX_STATS)
7926
7927
7928 struct fw_port_stats_cmd {
7929 __be32 op_to_portid;
7930 __be32 retval_len16;
7931 union fw_port_stats {
7932 struct fw_port_stats_ctl {
7933 __u8 nstats_bg_bm;
7934 __u8 tx_ix;
7935 __be16 r6;
7936 __be32 r7;
7937 __be64 stat0;
7938 __be64 stat1;
7939 __be64 stat2;
7940 __be64 stat3;
7941 __be64 stat4;
7942 __be64 stat5;
7943 } ctl;
7944 struct fw_port_stats_all {
7945 __be64 tx_bytes;
7946 __be64 tx_frames;
7947 __be64 tx_bcast;
7948 __be64 tx_mcast;
7949 __be64 tx_ucast;
7950 __be64 tx_error;
7951 __be64 tx_64b;
7952 __be64 tx_65b_127b;
7953 __be64 tx_128b_255b;
7954 __be64 tx_256b_511b;
7955 __be64 tx_512b_1023b;
7956 __be64 tx_1024b_1518b;
7957 __be64 tx_1519b_max;
7958 __be64 tx_drop;
7959 __be64 tx_pause;
7960 __be64 tx_ppp0;
7961 __be64 tx_ppp1;
7962 __be64 tx_ppp2;
7963 __be64 tx_ppp3;
7964 __be64 tx_ppp4;
7965 __be64 tx_ppp5;
7966 __be64 tx_ppp6;
7967 __be64 tx_ppp7;
7968 __be64 rx_bytes;
7969 __be64 rx_frames;
7970 __be64 rx_bcast;
7971 __be64 rx_mcast;
7972 __be64 rx_ucast;
7973 __be64 rx_mtu_error;
7974 __be64 rx_mtu_crc_error;
7975 __be64 rx_crc_error;
7976 __be64 rx_len_error;
7977 __be64 rx_sym_error;
7978 __be64 rx_64b;
7979 __be64 rx_65b_127b;
7980 __be64 rx_128b_255b;
7981 __be64 rx_256b_511b;
7982 __be64 rx_512b_1023b;
7983 __be64 rx_1024b_1518b;
7984 __be64 rx_1519b_max;
7985 __be64 rx_pause;
7986 __be64 rx_ppp0;
7987 __be64 rx_ppp1;
7988 __be64 rx_ppp2;
7989 __be64 rx_ppp3;
7990 __be64 rx_ppp4;
7991 __be64 rx_ppp5;
7992 __be64 rx_ppp6;
7993 __be64 rx_ppp7;
7994 __be64 rx_less_64b;
7995 __be64 rx_bg_drop;
7996 __be64 rx_bg_trunc;
7997 } all;
7998 } u;
7999 };
8000
8001 #define S_FW_PORT_STATS_CMD_NSTATS 4
8002 #define M_FW_PORT_STATS_CMD_NSTATS 0x7
8003 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS)
8004 #define G_FW_PORT_STATS_CMD_NSTATS(x) \
8005 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS)
8006
8007 #define S_FW_PORT_STATS_CMD_BG_BM 0
8008 #define M_FW_PORT_STATS_CMD_BG_BM 0x3
8009 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM)
8010 #define G_FW_PORT_STATS_CMD_BG_BM(x) \
8011 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM)
8012
8013 #define S_FW_PORT_STATS_CMD_TX 7
8014 #define M_FW_PORT_STATS_CMD_TX 0x1
8015 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX)
8016 #define G_FW_PORT_STATS_CMD_TX(x) \
8017 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX)
8018 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U)
8019
8020 #define S_FW_PORT_STATS_CMD_IX 0
8021 #define M_FW_PORT_STATS_CMD_IX 0x3f
8022 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX)
8023 #define G_FW_PORT_STATS_CMD_IX(x) \
8024 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX)
8025
8026 /* port loopback stats */
8027 #define FW_NUM_LB_STATS 14
8028 enum fw_port_lb_stats_index {
8029 FW_STAT_LB_PORT_BYTES_IX,
8030 FW_STAT_LB_PORT_FRAMES_IX,
8031 FW_STAT_LB_PORT_BCAST_IX,
8032 FW_STAT_LB_PORT_MCAST_IX,
8033 FW_STAT_LB_PORT_UCAST_IX,
8034 FW_STAT_LB_PORT_ERROR_IX,
8035 FW_STAT_LB_PORT_64B_IX,
8036 FW_STAT_LB_PORT_65B_127B_IX,
8037 FW_STAT_LB_PORT_128B_255B_IX,
8038 FW_STAT_LB_PORT_256B_511B_IX,
8039 FW_STAT_LB_PORT_512B_1023B_IX,
8040 FW_STAT_LB_PORT_1024B_1518B_IX,
8041 FW_STAT_LB_PORT_1519B_MAX_IX,
8042 FW_STAT_LB_PORT_DROP_FRAMES_IX
8043 };
8044
8045 struct fw_port_lb_stats_cmd {
8046 __be32 op_to_lbport;
8047 __be32 retval_len16;
8048 union fw_port_lb_stats {
8049 struct fw_port_lb_stats_ctl {
8050 __u8 nstats_bg_bm;
8051 __u8 ix_pkd;
8052 __be16 r6;
8053 __be32 r7;
8054 __be64 stat0;
8055 __be64 stat1;
8056 __be64 stat2;
8057 __be64 stat3;
8058 __be64 stat4;
8059 __be64 stat5;
8060 } ctl;
8061 struct fw_port_lb_stats_all {
8062 __be64 tx_bytes;
8063 __be64 tx_frames;
8064 __be64 tx_bcast;
8065 __be64 tx_mcast;
8066 __be64 tx_ucast;
8067 __be64 tx_error;
8068 __be64 tx_64b;
8069 __be64 tx_65b_127b;
8070 __be64 tx_128b_255b;
8071 __be64 tx_256b_511b;
8072 __be64 tx_512b_1023b;
8073 __be64 tx_1024b_1518b;
8074 __be64 tx_1519b_max;
8075 __be64 rx_lb_drop;
8076 __be64 rx_lb_trunc;
8077 } all;
8078 } u;
8079 };
8080
8081 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0
8082 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf
8083 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \
8084 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT)
8085 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \
8086 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT)
8087
8088 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4
8089 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7
8090 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \
8091 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS)
8092 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \
8093 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS)
8094
8095 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0
8096 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3
8097 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM)
8098 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \
8099 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM)
8100
8101 #define S_FW_PORT_LB_STATS_CMD_IX 0
8102 #define M_FW_PORT_LB_STATS_CMD_IX 0xf
8103 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX)
8104 #define G_FW_PORT_LB_STATS_CMD_IX(x) \
8105 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX)
8106
8107 /* Trace related defines */
8108 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240
8109 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560
8110
8111 struct fw_port_trace_cmd {
8112 __be32 op_to_portid;
8113 __be32 retval_len16;
8114 __be16 traceen_to_pciech;
8115 __be16 qnum;
8116 __be32 r5;
8117 };
8118
8119 #define S_FW_PORT_TRACE_CMD_PORTID 0
8120 #define M_FW_PORT_TRACE_CMD_PORTID 0xf
8121 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID)
8122 #define G_FW_PORT_TRACE_CMD_PORTID(x) \
8123 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID)
8124
8125 #define S_FW_PORT_TRACE_CMD_TRACEEN 15
8126 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1
8127 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN)
8128 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \
8129 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN)
8130 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U)
8131
8132 #define S_FW_PORT_TRACE_CMD_FLTMODE 14
8133 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1
8134 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE)
8135 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \
8136 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE)
8137 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U)
8138
8139 #define S_FW_PORT_TRACE_CMD_DUPLEN 13
8140 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1
8141 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN)
8142 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \
8143 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN)
8144 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U)
8145
8146 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8
8147 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f
8148 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
8149 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
8150 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
8151 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \
8152 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
8153
8154 #define S_FW_PORT_TRACE_CMD_PCIECH 6
8155 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3
8156 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH)
8157 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \
8158 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH)
8159
8160 struct fw_port_trace_mmap_cmd {
8161 __be32 op_to_portid;
8162 __be32 retval_len16;
8163 __be32 fid_to_skipoffset;
8164 __be32 minpktsize_capturemax;
8165 __u8 map[224];
8166 };
8167
8168 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0
8169 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf
8170 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
8171 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID)
8172 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
8173 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \
8174 M_FW_PORT_TRACE_MMAP_CMD_PORTID)
8175
8176 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30
8177 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3
8178 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID)
8179 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \
8180 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID)
8181
8182 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29
8183 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1
8184 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
8185 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
8186 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
8187 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \
8188 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
8189 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U)
8190
8191 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28
8192 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1
8193 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
8194 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
8195 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
8196 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \
8197 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
8198 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U)
8199
8200 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8
8201 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f
8202 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
8203 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
8204 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
8205 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \
8206 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
8207
8208 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0
8209 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f
8210 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
8211 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
8212 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
8213 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \
8214 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
8215
8216 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18
8217 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff
8218 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
8219 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
8220 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
8221 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \
8222 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
8223
8224 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0
8225 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff
8226 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
8227 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
8228 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
8229 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \
8230 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
8231
8232 enum fw_ptp_subop {
8233
8234 /* none */
8235 FW_PTP_SC_INIT_TIMER = 0x00,
8236 FW_PTP_SC_TX_TYPE = 0x01,
8237
8238 /* init */
8239 FW_PTP_SC_RXTIME_STAMP = 0x08,
8240 FW_PTP_SC_RDRX_TYPE = 0x09,
8241
8242 /* ts */
8243 FW_PTP_SC_ADJ_FREQ = 0x10,
8244 FW_PTP_SC_ADJ_TIME = 0x11,
8245 FW_PTP_SC_ADJ_FTIME = 0x12,
8246 FW_PTP_SC_WALL_CLOCK = 0x13,
8247 FW_PTP_SC_GET_TIME = 0x14,
8248 FW_PTP_SC_SET_TIME = 0x15,
8249 };
8250
8251 struct fw_ptp_cmd {
8252 __be32 op_to_portid;
8253 __be32 retval_len16;
8254 union fw_ptp {
8255 struct fw_ptp_sc {
8256 __u8 sc;
8257 __u8 r3[7];
8258 } scmd;
8259 struct fw_ptp_init {
8260 __u8 sc;
8261 __u8 txchan;
8262 __be16 absid;
8263 __be16 mode;
8264 __be16 ptp_rx_ctrl_pkd;
8265 } init;
8266 struct fw_ptp_ts {
8267 __u8 sc;
8268 __u8 sign;
8269 __be16 r3;
8270 __be32 ppb;
8271 __be64 tm;
8272 } ts;
8273 } u;
8274 __be64 r3;
8275 };
8276
8277 #define S_FW_PTP_CMD_PORTID 0
8278 #define M_FW_PTP_CMD_PORTID 0xf
8279 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID)
8280 #define G_FW_PTP_CMD_PORTID(x) \
8281 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID)
8282
8283 #define S_FW_PTP_CMD_PTP_RX_CTRL 15
8284 #define M_FW_PTP_CMD_PTP_RX_CTRL 0x1
8285 #define V_FW_PTP_CMD_PTP_RX_CTRL(x) ((x) << S_FW_PTP_CMD_PTP_RX_CTRL)
8286 #define G_FW_PTP_CMD_PTP_RX_CTRL(x) \
8287 (((x) >> S_FW_PTP_CMD_PTP_RX_CTRL) & M_FW_PTP_CMD_PTP_RX_CTRL)
8288 #define F_FW_PTP_CMD_PTP_RX_CTRL V_FW_PTP_CMD_PTP_RX_CTRL(1U)
8289
8290
8291 struct fw_rss_ind_tbl_cmd {
8292 __be32 op_to_viid;
8293 __be32 retval_len16;
8294 __be16 niqid;
8295 __be16 startidx;
8296 __be32 r3;
8297 __be32 iq0_to_iq2;
8298 __be32 iq3_to_iq5;
8299 __be32 iq6_to_iq8;
8300 __be32 iq9_to_iq11;
8301 __be32 iq12_to_iq14;
8302 __be32 iq15_to_iq17;
8303 __be32 iq18_to_iq20;
8304 __be32 iq21_to_iq23;
8305 __be32 iq24_to_iq26;
8306 __be32 iq27_to_iq29;
8307 __be32 iq30_iq31;
8308 __be32 r15_lo;
8309 };
8310
8311 #define S_FW_RSS_IND_TBL_CMD_VIID 0
8312 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
8313 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
8314 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
8315 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
8316
8317 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
8318 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
8319 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
8320 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
8321 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
8322
8323 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
8324 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
8325 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
8326 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
8327 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
8328
8329 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
8330 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
8331 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
8332 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
8333 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
8334
8335 #define S_FW_RSS_IND_TBL_CMD_IQ3 20
8336 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff
8337 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3)
8338 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \
8339 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3)
8340
8341 #define S_FW_RSS_IND_TBL_CMD_IQ4 10
8342 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff
8343 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4)
8344 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \
8345 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4)
8346
8347 #define S_FW_RSS_IND_TBL_CMD_IQ5 0
8348 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff
8349 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5)
8350 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \
8351 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5)
8352
8353 #define S_FW_RSS_IND_TBL_CMD_IQ6 20
8354 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff
8355 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6)
8356 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \
8357 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6)
8358
8359 #define S_FW_RSS_IND_TBL_CMD_IQ7 10
8360 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff
8361 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7)
8362 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \
8363 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7)
8364
8365 #define S_FW_RSS_IND_TBL_CMD_IQ8 0
8366 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff
8367 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8)
8368 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \
8369 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8)
8370
8371 #define S_FW_RSS_IND_TBL_CMD_IQ9 20
8372 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff
8373 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9)
8374 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \
8375 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9)
8376
8377 #define S_FW_RSS_IND_TBL_CMD_IQ10 10
8378 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff
8379 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10)
8380 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \
8381 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10)
8382
8383 #define S_FW_RSS_IND_TBL_CMD_IQ11 0
8384 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff
8385 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11)
8386 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \
8387 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11)
8388
8389 #define S_FW_RSS_IND_TBL_CMD_IQ12 20
8390 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff
8391 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12)
8392 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \
8393 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12)
8394
8395 #define S_FW_RSS_IND_TBL_CMD_IQ13 10
8396 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff
8397 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13)
8398 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \
8399 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13)
8400
8401 #define S_FW_RSS_IND_TBL_CMD_IQ14 0
8402 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff
8403 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14)
8404 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \
8405 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14)
8406
8407 #define S_FW_RSS_IND_TBL_CMD_IQ15 20
8408 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff
8409 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15)
8410 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \
8411 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15)
8412
8413 #define S_FW_RSS_IND_TBL_CMD_IQ16 10
8414 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff
8415 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16)
8416 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \
8417 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16)
8418
8419 #define S_FW_RSS_IND_TBL_CMD_IQ17 0
8420 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff
8421 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17)
8422 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \
8423 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17)
8424
8425 #define S_FW_RSS_IND_TBL_CMD_IQ18 20
8426 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff
8427 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18)
8428 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \
8429 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18)
8430
8431 #define S_FW_RSS_IND_TBL_CMD_IQ19 10
8432 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff
8433 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19)
8434 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \
8435 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19)
8436
8437 #define S_FW_RSS_IND_TBL_CMD_IQ20 0
8438 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff
8439 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20)
8440 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \
8441 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20)
8442
8443 #define S_FW_RSS_IND_TBL_CMD_IQ21 20
8444 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff
8445 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21)
8446 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \
8447 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21)
8448
8449 #define S_FW_RSS_IND_TBL_CMD_IQ22 10
8450 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff
8451 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22)
8452 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \
8453 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22)
8454
8455 #define S_FW_RSS_IND_TBL_CMD_IQ23 0
8456 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff
8457 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23)
8458 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \
8459 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23)
8460
8461 #define S_FW_RSS_IND_TBL_CMD_IQ24 20
8462 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff
8463 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24)
8464 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \
8465 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24)
8466
8467 #define S_FW_RSS_IND_TBL_CMD_IQ25 10
8468 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff
8469 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25)
8470 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \
8471 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25)
8472
8473 #define S_FW_RSS_IND_TBL_CMD_IQ26 0
8474 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff
8475 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26)
8476 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \
8477 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26)
8478
8479 #define S_FW_RSS_IND_TBL_CMD_IQ27 20
8480 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff
8481 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27)
8482 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \
8483 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27)
8484
8485 #define S_FW_RSS_IND_TBL_CMD_IQ28 10
8486 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff
8487 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28)
8488 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \
8489 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28)
8490
8491 #define S_FW_RSS_IND_TBL_CMD_IQ29 0
8492 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff
8493 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29)
8494 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \
8495 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29)
8496
8497 #define S_FW_RSS_IND_TBL_CMD_IQ30 20
8498 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff
8499 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30)
8500 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \
8501 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30)
8502
8503 #define S_FW_RSS_IND_TBL_CMD_IQ31 10
8504 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff
8505 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31)
8506 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \
8507 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31)
8508
8509 struct fw_rss_glb_config_cmd {
8510 __be32 op_to_write;
8511 __be32 retval_len16;
8512 union fw_rss_glb_config {
8513 struct fw_rss_glb_config_manual {
8514 __be32 mode_pkd;
8515 __be32 r3;
8516 __be64 r4;
8517 __be64 r5;
8518 } manual;
8519 struct fw_rss_glb_config_basicvirtual {
8520 __be32 mode_keymode;
8521 __be32 synmapen_to_hashtoeplitz;
8522 __be64 r8;
8523 __be64 r9;
8524 } basicvirtual;
8525 } u;
8526 };
8527
8528 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
8529 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
8530 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE)
8531 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
8532 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
8533
8534 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
8535 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
8536 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1
8537
8538 #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26
8539 #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3
8540 #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
8541 ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
8542 #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
8543 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \
8544 M_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
8545
8546 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0
8547 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1
8548 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2
8549 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3
8550
8551 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
8552 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1
8553 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
8554 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
8555 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
8556 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \
8557 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
8558 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
8559
8560 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
8561 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1
8562 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
8563 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
8564 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
8565 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \
8566 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
8567 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
8568 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
8569
8570 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
8571 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1
8572 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
8573 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
8574 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
8575 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \
8576 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
8577 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
8578 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
8579
8580 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
8581 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1
8582 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
8583 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
8584 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
8585 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \
8586 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
8587 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
8588 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
8589
8590 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
8591 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1
8592 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
8593 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
8594 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
8595 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \
8596 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
8597 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
8598 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
8599
8600 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
8601 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1
8602 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
8603 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
8604 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
8605 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \
8606 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
8607 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
8608
8609 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
8610 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1
8611 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
8612 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
8613 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
8614 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \
8615 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
8616 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
8617
8618 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
8619 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1
8620 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
8621 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
8622 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
8623 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \
8624 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
8625 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
8626 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
8627
8628 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
8629 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1
8630 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
8631 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
8632 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
8633 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \
8634 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
8635 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
8636 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
8637
8638 struct fw_rss_vi_config_cmd {
8639 __be32 op_to_viid;
8640 __be32 retval_len16;
8641 union fw_rss_vi_config {
8642 struct fw_rss_vi_config_manual {
8643 __be64 r3;
8644 __be64 r4;
8645 __be64 r5;
8646 } manual;
8647 struct fw_rss_vi_config_basicvirtual {
8648 __be32 r6;
8649 __be32 defaultq_to_udpen;
8650 __be32 secretkeyidx_pkd;
8651 __be32 secretkeyxor;
8652 __be64 r10;
8653 } basicvirtual;
8654 } u;
8655 };
8656
8657 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
8658 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
8659 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
8660 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
8661 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
8662
8663 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
8664 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
8665 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
8666 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
8667 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
8668 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
8669 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
8670
8671 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
8672 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
8673 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
8674 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
8675 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
8676 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
8677 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
8678 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
8679 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
8680
8681 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
8682 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
8683 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
8684 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
8685 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
8686 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
8687 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
8688 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
8689 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
8690
8691 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
8692 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
8693 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
8694 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
8695 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
8696 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
8697 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
8698 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
8699 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
8700
8701 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
8702 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
8703 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
8704 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
8705 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
8706 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
8707 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
8708 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
8709 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
8710
8711 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
8712 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
8713 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
8714 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
8715 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
8716 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
8717
8718 #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0
8719 #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf
8720 #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
8721 ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
8722 #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
8723 (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \
8724 M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
8725
8726 enum fw_sched_sc {
8727 FW_SCHED_SC_CONFIG = 0,
8728 FW_SCHED_SC_PARAMS = 1,
8729 };
8730
8731 enum fw_sched_type {
8732 FW_SCHED_TYPE_PKTSCHED = 0,
8733 FW_SCHED_TYPE_STREAMSCHED = 1,
8734 };
8735
8736 enum fw_sched_params_level {
8737 FW_SCHED_PARAMS_LEVEL_CL_RL = 0,
8738 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1,
8739 FW_SCHED_PARAMS_LEVEL_CH_RL = 2,
8740 };
8741
8742 enum fw_sched_params_mode {
8743 FW_SCHED_PARAMS_MODE_CLASS = 0,
8744 FW_SCHED_PARAMS_MODE_FLOW = 1,
8745 };
8746
8747 enum fw_sched_params_unit {
8748 FW_SCHED_PARAMS_UNIT_BITRATE = 0,
8749 FW_SCHED_PARAMS_UNIT_PKTRATE = 1,
8750 };
8751
8752 enum fw_sched_params_rate {
8753 FW_SCHED_PARAMS_RATE_REL = 0,
8754 FW_SCHED_PARAMS_RATE_ABS = 1,
8755 };
8756
8757 struct fw_sched_cmd {
8758 __be32 op_to_write;
8759 __be32 retval_len16;
8760 union fw_sched {
8761 struct fw_sched_config {
8762 __u8 sc;
8763 __u8 type;
8764 __u8 minmaxen;
8765 __u8 r3[5];
8766 __u8 nclasses[4];
8767 __be32 r4;
8768 } config;
8769 struct fw_sched_params {
8770 __u8 sc;
8771 __u8 type;
8772 __u8 level;
8773 __u8 mode;
8774 __u8 unit;
8775 __u8 rate;
8776 __u8 ch;
8777 __u8 cl;
8778 __be32 min;
8779 __be32 max;
8780 __be16 weight;
8781 __be16 pktsize;
8782 __be16 burstsize;
8783 __be16 r4;
8784 } params;
8785 } u;
8786 };
8787
8788 /*
8789 * length of the formatting string
8790 */
8791 #define FW_DEVLOG_FMT_LEN 192
8792
8793 /*
8794 * maximum number of the formatting string parameters
8795 */
8796 #define FW_DEVLOG_FMT_PARAMS_NUM 8
8797
8798 /*
8799 * priority levels
8800 */
8801 enum fw_devlog_level {
8802 FW_DEVLOG_LEVEL_EMERG = 0x0,
8803 FW_DEVLOG_LEVEL_CRIT = 0x1,
8804 FW_DEVLOG_LEVEL_ERR = 0x2,
8805 FW_DEVLOG_LEVEL_NOTICE = 0x3,
8806 FW_DEVLOG_LEVEL_INFO = 0x4,
8807 FW_DEVLOG_LEVEL_DEBUG = 0x5,
8808 FW_DEVLOG_LEVEL_MAX = 0x5,
8809 };
8810
8811 /*
8812 * facilities that may send a log message
8813 */
8814 enum fw_devlog_facility {
8815 FW_DEVLOG_FACILITY_CORE = 0x00,
8816 FW_DEVLOG_FACILITY_CF = 0x01,
8817 FW_DEVLOG_FACILITY_SCHED = 0x02,
8818 FW_DEVLOG_FACILITY_TIMER = 0x04,
8819 FW_DEVLOG_FACILITY_RES = 0x06,
8820 FW_DEVLOG_FACILITY_HW = 0x08,
8821 FW_DEVLOG_FACILITY_FLR = 0x10,
8822 FW_DEVLOG_FACILITY_DMAQ = 0x12,
8823 FW_DEVLOG_FACILITY_PHY = 0x14,
8824 FW_DEVLOG_FACILITY_MAC = 0x16,
8825 FW_DEVLOG_FACILITY_PORT = 0x18,
8826 FW_DEVLOG_FACILITY_VI = 0x1A,
8827 FW_DEVLOG_FACILITY_FILTER = 0x1C,
8828 FW_DEVLOG_FACILITY_ACL = 0x1E,
8829 FW_DEVLOG_FACILITY_TM = 0x20,
8830 FW_DEVLOG_FACILITY_QFC = 0x22,
8831 FW_DEVLOG_FACILITY_DCB = 0x24,
8832 FW_DEVLOG_FACILITY_ETH = 0x26,
8833 FW_DEVLOG_FACILITY_OFLD = 0x28,
8834 FW_DEVLOG_FACILITY_RI = 0x2A,
8835 FW_DEVLOG_FACILITY_ISCSI = 0x2C,
8836 FW_DEVLOG_FACILITY_FCOE = 0x2E,
8837 FW_DEVLOG_FACILITY_FOISCSI = 0x30,
8838 FW_DEVLOG_FACILITY_FOFCOE = 0x32,
8839 FW_DEVLOG_FACILITY_CHNET = 0x34,
8840 FW_DEVLOG_FACILITY_COISCSI = 0x36,
8841 FW_DEVLOG_FACILITY_MAX = 0x38,
8842 };
8843
8844 /*
8845 * log message format
8846 */
8847 struct fw_devlog_e {
8848 __be64 timestamp;
8849 __be32 seqno;
8850 __be16 reserved1;
8851 __u8 level;
8852 __u8 facility;
8853 __u8 fmt[FW_DEVLOG_FMT_LEN];
8854 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM];
8855 __be32 reserved3[4];
8856 };
8857
8858 struct fw_devlog_cmd {
8859 __be32 op_to_write;
8860 __be32 retval_len16;
8861 __u8 level;
8862 __u8 r2[7];
8863 __be32 memtype_devlog_memaddr16_devlog;
8864 __be32 memsize_devlog;
8865 __be32 r3[2];
8866 };
8867
8868 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28
8869 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf
8870 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
8871 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
8872 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
8873 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
8874
8875 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0
8876 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff
8877 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
8878 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
8879 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
8880 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \
8881 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
8882
8883 enum fw_watchdog_actions {
8884 FW_WATCHDOG_ACTION_SHUTDOWN = 0,
8885 FW_WATCHDOG_ACTION_FLR = 1,
8886 FW_WATCHDOG_ACTION_BYPASS = 2,
8887 FW_WATCHDOG_ACTION_TMPCHK = 3,
8888 FW_WATCHDOG_ACTION_PAUSEOFF = 4,
8889
8890 FW_WATCHDOG_ACTION_MAX = 5,
8891 };
8892
8893 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60
8894
8895 struct fw_watchdog_cmd {
8896 __be32 op_to_vfn;
8897 __be32 retval_len16;
8898 __be32 timeout;
8899 __be32 action;
8900 };
8901
8902 #define S_FW_WATCHDOG_CMD_PFN 8
8903 #define M_FW_WATCHDOG_CMD_PFN 0x7
8904 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN)
8905 #define G_FW_WATCHDOG_CMD_PFN(x) \
8906 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN)
8907
8908 #define S_FW_WATCHDOG_CMD_VFN 0
8909 #define M_FW_WATCHDOG_CMD_VFN 0xff
8910 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN)
8911 #define G_FW_WATCHDOG_CMD_VFN(x) \
8912 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN)
8913
8914 struct fw_clip_cmd {
8915 __be32 op_to_write;
8916 __be32 alloc_to_len16;
8917 __be64 ip_hi;
8918 __be64 ip_lo;
8919 __be32 r4[2];
8920 };
8921
8922 #define S_FW_CLIP_CMD_ALLOC 31
8923 #define M_FW_CLIP_CMD_ALLOC 0x1
8924 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
8925 #define G_FW_CLIP_CMD_ALLOC(x) \
8926 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
8927 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
8928
8929 #define S_FW_CLIP_CMD_FREE 30
8930 #define M_FW_CLIP_CMD_FREE 0x1
8931 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
8932 #define G_FW_CLIP_CMD_FREE(x) \
8933 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
8934 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
8935
8936 #define S_FW_CLIP_CMD_INDEX 16
8937 #define M_FW_CLIP_CMD_INDEX 0x1fff
8938 #define V_FW_CLIP_CMD_INDEX(x) ((x) << S_FW_CLIP_CMD_INDEX)
8939 #define G_FW_CLIP_CMD_INDEX(x) \
8940 (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX)
8941
8942 struct fw_clip2_cmd {
8943 __be32 op_to_write;
8944 __be32 alloc_to_len16;
8945 __be64 ip_hi;
8946 __be64 ip_lo;
8947 __be64 ipm_hi;
8948 __be64 ipm_lo;
8949 __be32 r4[2];
8950 };
8951
8952 /******************************************************************************
8953 * F O i S C S I C O M M A N D s
8954 **************************************/
8955
8956 #define FW_CHNET_IFACE_ADDR_MAX 3
8957
8958 enum fw_chnet_iface_cmd_subop {
8959 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0,
8960
8961 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP,
8962 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN,
8963
8964 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET,
8965 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET,
8966
8967 FW_CHNET_IFACE_CMD_SUBOP_MAX,
8968 };
8969
8970 struct fw_chnet_iface_cmd {
8971 __be32 op_to_portid;
8972 __be32 retval_len16;
8973 __u8 subop;
8974 __u8 r2[2];
8975 __u8 flags;
8976 __be32 ifid_ifstate;
8977 __be16 mtu;
8978 __be16 vlanid;
8979 __be32 r3;
8980 __be16 r4;
8981 __u8 mac[6];
8982 };
8983
8984 #define S_FW_CHNET_IFACE_CMD_PORTID 0
8985 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf
8986 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID)
8987 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \
8988 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID)
8989
8990 #define S_FW_CHNET_IFACE_CMD_RSS_IQID 16
8991 #define M_FW_CHNET_IFACE_CMD_RSS_IQID 0xffff
8992 #define V_FW_CHNET_IFACE_CMD_RSS_IQID(x) \
8993 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID)
8994 #define G_FW_CHNET_IFACE_CMD_RSS_IQID(x) \
8995 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID) & M_FW_CHNET_IFACE_CMD_RSS_IQID)
8996
8997 #define S_FW_CHNET_IFACE_CMD_RSS_IQID_F 0
8998 #define M_FW_CHNET_IFACE_CMD_RSS_IQID_F 0x1
8999 #define V_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \
9000 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID_F)
9001 #define G_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \
9002 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID_F) & \
9003 M_FW_CHNET_IFACE_CMD_RSS_IQID_F)
9004 #define F_FW_CHNET_IFACE_CMD_RSS_IQID_F V_FW_CHNET_IFACE_CMD_RSS_IQID_F(1U)
9005
9006 #define S_FW_CHNET_IFACE_CMD_IFID 8
9007 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff
9008 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID)
9009 #define G_FW_CHNET_IFACE_CMD_IFID(x) \
9010 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID)
9011
9012 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0
9013 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff
9014 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE)
9015 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \
9016 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE)
9017
9018 struct fw_fcoe_res_info_cmd {
9019 __be32 op_to_read;
9020 __be32 retval_len16;
9021 __be16 e_d_tov;
9022 __be16 r_a_tov_seq;
9023 __be16 r_a_tov_els;
9024 __be16 r_r_tov;
9025 __be32 max_xchgs;
9026 __be32 max_ssns;
9027 __be32 used_xchgs;
9028 __be32 used_ssns;
9029 __be32 max_fcfs;
9030 __be32 max_vnps;
9031 __be32 used_fcfs;
9032 __be32 used_vnps;
9033 };
9034
9035 struct fw_fcoe_link_cmd {
9036 __be32 op_to_portid;
9037 __be32 retval_len16;
9038 __be32 sub_opcode_fcfi;
9039 __u8 r3;
9040 __u8 lstatus;
9041 __be16 flags;
9042 __u8 r4;
9043 __u8 set_vlan;
9044 __be16 vlan_id;
9045 __be32 vnpi_pkd;
9046 __be16 r6;
9047 __u8 phy_mac[6];
9048 __u8 vnport_wwnn[8];
9049 __u8 vnport_wwpn[8];
9050 };
9051
9052 #define S_FW_FCOE_LINK_CMD_PORTID 0
9053 #define M_FW_FCOE_LINK_CMD_PORTID 0xf
9054 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID)
9055 #define G_FW_FCOE_LINK_CMD_PORTID(x) \
9056 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID)
9057
9058 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24
9059 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff
9060 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
9061 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE)
9062 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
9063 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE)
9064
9065 #define S_FW_FCOE_LINK_CMD_FCFI 0
9066 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff
9067 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI)
9068 #define G_FW_FCOE_LINK_CMD_FCFI(x) \
9069 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI)
9070
9071 #define S_FW_FCOE_LINK_CMD_VNPI 0
9072 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff
9073 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI)
9074 #define G_FW_FCOE_LINK_CMD_VNPI(x) \
9075 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI)
9076
9077 struct fw_fcoe_vnp_cmd {
9078 __be32 op_to_fcfi;
9079 __be32 alloc_to_len16;
9080 __be32 gen_wwn_to_vnpi;
9081 __be32 vf_id;
9082 __be16 iqid;
9083 __u8 vnport_mac[6];
9084 __u8 vnport_wwnn[8];
9085 __u8 vnport_wwpn[8];
9086 __u8 cmn_srv_parms[16];
9087 __u8 clsp_word_0_1[8];
9088 };
9089
9090 #define S_FW_FCOE_VNP_CMD_FCFI 0
9091 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff
9092 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI)
9093 #define G_FW_FCOE_VNP_CMD_FCFI(x) \
9094 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI)
9095
9096 #define S_FW_FCOE_VNP_CMD_ALLOC 31
9097 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1
9098 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC)
9099 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \
9100 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC)
9101 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U)
9102
9103 #define S_FW_FCOE_VNP_CMD_FREE 30
9104 #define M_FW_FCOE_VNP_CMD_FREE 0x1
9105 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE)
9106 #define G_FW_FCOE_VNP_CMD_FREE(x) \
9107 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE)
9108 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U)
9109
9110 #define S_FW_FCOE_VNP_CMD_MODIFY 29
9111 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1
9112 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY)
9113 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \
9114 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY)
9115 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U)
9116
9117 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22
9118 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1
9119 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN)
9120 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \
9121 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN)
9122 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U)
9123
9124 #define S_FW_FCOE_VNP_CMD_PERSIST 21
9125 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1
9126 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST)
9127 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \
9128 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST)
9129 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U)
9130
9131 #define S_FW_FCOE_VNP_CMD_VFID_EN 20
9132 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1
9133 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN)
9134 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \
9135 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN)
9136 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U)
9137
9138 #define S_FW_FCOE_VNP_CMD_VNPI 0
9139 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff
9140 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI)
9141 #define G_FW_FCOE_VNP_CMD_VNPI(x) \
9142 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI)
9143
9144 struct fw_fcoe_sparams_cmd {
9145 __be32 op_to_portid;
9146 __be32 retval_len16;
9147 __u8 r3[7];
9148 __u8 cos;
9149 __u8 lport_wwnn[8];
9150 __u8 lport_wwpn[8];
9151 __u8 cmn_srv_parms[16];
9152 __u8 cls_srv_parms[16];
9153 };
9154
9155 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0
9156 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf
9157 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID)
9158 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \
9159 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID)
9160
9161 struct fw_fcoe_stats_cmd {
9162 __be32 op_to_flowid;
9163 __be32 free_to_len16;
9164 union fw_fcoe_stats {
9165 struct fw_fcoe_stats_ctl {
9166 __u8 nstats_port;
9167 __u8 port_valid_ix;
9168 __be16 r6;
9169 __be32 r7;
9170 __be64 stat0;
9171 __be64 stat1;
9172 __be64 stat2;
9173 __be64 stat3;
9174 __be64 stat4;
9175 __be64 stat5;
9176 } ctl;
9177 struct fw_fcoe_port_stats {
9178 __be64 tx_bcast_bytes;
9179 __be64 tx_bcast_frames;
9180 __be64 tx_mcast_bytes;
9181 __be64 tx_mcast_frames;
9182 __be64 tx_ucast_bytes;
9183 __be64 tx_ucast_frames;
9184 __be64 tx_drop_frames;
9185 __be64 tx_offload_bytes;
9186 __be64 tx_offload_frames;
9187 __be64 rx_bcast_bytes;
9188 __be64 rx_bcast_frames;
9189 __be64 rx_mcast_bytes;
9190 __be64 rx_mcast_frames;
9191 __be64 rx_ucast_bytes;
9192 __be64 rx_ucast_frames;
9193 __be64 rx_err_frames;
9194 } port_stats;
9195 struct fw_fcoe_fcf_stats {
9196 __be32 fip_tx_bytes;
9197 __be32 fip_tx_fr;
9198 __be64 fcf_ka;
9199 __be64 mcast_adv_rcvd;
9200 __be16 ucast_adv_rcvd;
9201 __be16 sol_sent;
9202 __be16 vlan_req;
9203 __be16 vlan_rpl;
9204 __be16 clr_vlink;
9205 __be16 link_down;
9206 __be16 link_up;
9207 __be16 logo;
9208 __be16 flogi_req;
9209 __be16 flogi_rpl;
9210 __be16 fdisc_req;
9211 __be16 fdisc_rpl;
9212 __be16 fka_prd_chg;
9213 __be16 fc_map_chg;
9214 __be16 vfid_chg;
9215 __u8 no_fka_req;
9216 __u8 no_vnp;
9217 } fcf_stats;
9218 struct fw_fcoe_pcb_stats {
9219 __be64 tx_bytes;
9220 __be64 tx_frames;
9221 __be64 rx_bytes;
9222 __be64 rx_frames;
9223 __be32 vnp_ka;
9224 __be32 unsol_els_rcvd;
9225 __be64 unsol_cmd_rcvd;
9226 __be16 implicit_logo;
9227 __be16 flogi_inv_sparm;
9228 __be16 fdisc_inv_sparm;
9229 __be16 flogi_rjt;
9230 __be16 fdisc_rjt;
9231 __be16 no_ssn;
9232 __be16 mac_flt_fail;
9233 __be16 inv_fr_rcvd;
9234 } pcb_stats;
9235 struct fw_fcoe_scb_stats {
9236 __be64 tx_bytes;
9237 __be64 tx_frames;
9238 __be64 rx_bytes;
9239 __be64 rx_frames;
9240 __be32 host_abrt_req;
9241 __be32 adap_auto_abrt;
9242 __be32 adap_abrt_rsp;
9243 __be32 host_ios_req;
9244 __be16 ssn_offl_ios;
9245 __be16 ssn_not_rdy_ios;
9246 __u8 rx_data_ddp_err;
9247 __u8 ddp_flt_set_err;
9248 __be16 rx_data_fr_err;
9249 __u8 bad_st_abrt_req;
9250 __u8 no_io_abrt_req;
9251 __u8 abort_tmo;
9252 __u8 abort_tmo_2;
9253 __be32 abort_req;
9254 __u8 no_ppod_res_tmo;
9255 __u8 bp_tmo;
9256 __u8 adap_auto_cls;
9257 __u8 no_io_cls_req;
9258 __be32 host_cls_req;
9259 __be64 unsol_cmd_rcvd;
9260 __be32 plogi_req_rcvd;
9261 __be32 prli_req_rcvd;
9262 __be16 logo_req_rcvd;
9263 __be16 prlo_req_rcvd;
9264 __be16 plogi_rjt_rcvd;
9265 __be16 prli_rjt_rcvd;
9266 __be32 adisc_req_rcvd;
9267 __be32 rscn_rcvd;
9268 __be32 rrq_req_rcvd;
9269 __be32 unsol_els_rcvd;
9270 __u8 adisc_rjt_rcvd;
9271 __u8 scr_rjt;
9272 __u8 ct_rjt;
9273 __u8 inval_bls_rcvd;
9274 __be32 ba_rjt_rcvd;
9275 } scb_stats;
9276 } u;
9277 };
9278
9279 #define S_FW_FCOE_STATS_CMD_FLOWID 0
9280 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff
9281 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID)
9282 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \
9283 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID)
9284
9285 #define S_FW_FCOE_STATS_CMD_FREE 30
9286 #define M_FW_FCOE_STATS_CMD_FREE 0x1
9287 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE)
9288 #define G_FW_FCOE_STATS_CMD_FREE(x) \
9289 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE)
9290 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U)
9291
9292 #define S_FW_FCOE_STATS_CMD_NSTATS 4
9293 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7
9294 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS)
9295 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \
9296 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS)
9297
9298 #define S_FW_FCOE_STATS_CMD_PORT 0
9299 #define M_FW_FCOE_STATS_CMD_PORT 0x3
9300 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT)
9301 #define G_FW_FCOE_STATS_CMD_PORT(x) \
9302 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT)
9303
9304 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7
9305 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1
9306 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \
9307 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID)
9308 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \
9309 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID)
9310 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U)
9311
9312 #define S_FW_FCOE_STATS_CMD_IX 0
9313 #define M_FW_FCOE_STATS_CMD_IX 0x3f
9314 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX)
9315 #define G_FW_FCOE_STATS_CMD_IX(x) \
9316 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX)
9317
9318 struct fw_fcoe_fcf_cmd {
9319 __be32 op_to_fcfi;
9320 __be32 retval_len16;
9321 __be16 priority_pkd;
9322 __u8 mac[6];
9323 __u8 name_id[8];
9324 __u8 fabric[8];
9325 __be16 vf_id;
9326 __be16 max_fcoe_size;
9327 __u8 vlan_id;
9328 __u8 fc_map[3];
9329 __be32 fka_adv;
9330 __be32 r6;
9331 __u8 r7_hi;
9332 __u8 fpma_to_portid;
9333 __u8 spma_mac[6];
9334 __be64 r8;
9335 };
9336
9337 #define S_FW_FCOE_FCF_CMD_FCFI 0
9338 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff
9339 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI)
9340 #define G_FW_FCOE_FCF_CMD_FCFI(x) \
9341 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI)
9342
9343 #define S_FW_FCOE_FCF_CMD_PRIORITY 0
9344 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff
9345 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY)
9346 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \
9347 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY)
9348
9349 #define S_FW_FCOE_FCF_CMD_FPMA 6
9350 #define M_FW_FCOE_FCF_CMD_FPMA 0x1
9351 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA)
9352 #define G_FW_FCOE_FCF_CMD_FPMA(x) \
9353 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA)
9354 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U)
9355
9356 #define S_FW_FCOE_FCF_CMD_SPMA 5
9357 #define M_FW_FCOE_FCF_CMD_SPMA 0x1
9358 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA)
9359 #define G_FW_FCOE_FCF_CMD_SPMA(x) \
9360 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA)
9361 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U)
9362
9363 #define S_FW_FCOE_FCF_CMD_LOGIN 4
9364 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1
9365 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN)
9366 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \
9367 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN)
9368 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U)
9369
9370 #define S_FW_FCOE_FCF_CMD_PORTID 0
9371 #define M_FW_FCOE_FCF_CMD_PORTID 0xf
9372 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID)
9373 #define G_FW_FCOE_FCF_CMD_PORTID(x) \
9374 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID)
9375
9376 /******************************************************************************
9377 * E R R O R a n d D E B U G C O M M A N D s
9378 ******************************************************/
9379
9380 enum fw_error_type {
9381 FW_ERROR_TYPE_EXCEPTION = 0x0,
9382 FW_ERROR_TYPE_HWMODULE = 0x1,
9383 FW_ERROR_TYPE_WR = 0x2,
9384 FW_ERROR_TYPE_ACL = 0x3,
9385 };
9386
9387 enum fw_dcb_ieee_locations {
9388 FW_IEEE_LOC_LOCAL,
9389 FW_IEEE_LOC_PEER,
9390 FW_IEEE_LOC_OPERATIONAL,
9391 };
9392
9393 struct fw_dcb_ieee_cmd {
9394 __be32 op_to_location;
9395 __be32 changed_to_len16;
9396 union fw_dcbx_stats {
9397 struct fw_dcbx_pfc_stats_ieee {
9398 __be32 pfc_mbc_pkd;
9399 __be32 pfc_willing_to_pfc_en;
9400 } dcbx_pfc_stats;
9401 struct fw_dcbx_ets_stats_ieee {
9402 __be32 cbs_to_ets_max_tc;
9403 __be32 pg_table;
9404 __u8 pg_percent[8];
9405 __u8 tsa[8];
9406 } dcbx_ets_stats;
9407 struct fw_dcbx_app_stats_ieee {
9408 __be32 num_apps_pkd;
9409 __be32 r6;
9410 __be32 app[4];
9411 } dcbx_app_stats;
9412 struct fw_dcbx_control {
9413 __be32 multi_peer_invalidated;
9414 __u8 version;
9415 __u8 r6[3];
9416 } dcbx_control;
9417 } u;
9418 };
9419
9420 #define S_FW_DCB_IEEE_CMD_PORT 8
9421 #define M_FW_DCB_IEEE_CMD_PORT 0x7
9422 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT)
9423 #define G_FW_DCB_IEEE_CMD_PORT(x) \
9424 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT)
9425
9426 #define S_FW_DCB_IEEE_CMD_FEATURE 2
9427 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7
9428 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE)
9429 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \
9430 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE)
9431
9432 #define S_FW_DCB_IEEE_CMD_LOCATION 0
9433 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3
9434 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION)
9435 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \
9436 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION)
9437
9438 #define S_FW_DCB_IEEE_CMD_CHANGED 20
9439 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1
9440 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED)
9441 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \
9442 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED)
9443 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U)
9444
9445 #define S_FW_DCB_IEEE_CMD_RECEIVED 19
9446 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1
9447 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED)
9448 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \
9449 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED)
9450 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U)
9451
9452 #define S_FW_DCB_IEEE_CMD_APPLY 18
9453 #define M_FW_DCB_IEEE_CMD_APPLY 0x1
9454 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY)
9455 #define G_FW_DCB_IEEE_CMD_APPLY(x) \
9456 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY)
9457 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U)
9458
9459 #define S_FW_DCB_IEEE_CMD_DISABLED 17
9460 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1
9461 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED)
9462 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \
9463 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED)
9464 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U)
9465
9466 #define S_FW_DCB_IEEE_CMD_MORE 16
9467 #define M_FW_DCB_IEEE_CMD_MORE 0x1
9468 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE)
9469 #define G_FW_DCB_IEEE_CMD_MORE(x) \
9470 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE)
9471 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U)
9472
9473 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0
9474 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1
9475 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC)
9476 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \
9477 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC)
9478 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U)
9479
9480 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16
9481 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1
9482 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \
9483 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING)
9484 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \
9485 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING)
9486 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U)
9487
9488 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8
9489 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff
9490 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC)
9491 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \
9492 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC)
9493
9494 #define S_FW_DCB_IEEE_CMD_PFC_EN 0
9495 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff
9496 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN)
9497 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \
9498 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN)
9499
9500 #define S_FW_DCB_IEEE_CMD_CBS 16
9501 #define M_FW_DCB_IEEE_CMD_CBS 0x1
9502 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS)
9503 #define G_FW_DCB_IEEE_CMD_CBS(x) \
9504 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS)
9505 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U)
9506
9507 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8
9508 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1
9509 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \
9510 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING)
9511 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \
9512 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING)
9513 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U)
9514
9515 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0
9516 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff
9517 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC)
9518 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \
9519 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC)
9520
9521 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0
9522 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7
9523 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS)
9524 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \
9525 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS)
9526
9527 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31
9528 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1
9529 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER)
9530 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \
9531 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER)
9532 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U)
9533
9534 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30
9535 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1
9536 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \
9537 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED)
9538 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \
9539 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED)
9540 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U)
9541
9542 /* Hand-written */
9543 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16
9544 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff
9545 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL)
9546 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \
9547 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL)
9548
9549 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3
9550 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7
9551 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT)
9552 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \
9553 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT)
9554
9555 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0
9556 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7
9557 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY)
9558 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \
9559 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY)
9560
9561
9562 struct fw_error_cmd {
9563 __be32 op_to_type;
9564 __be32 len16_pkd;
9565 union fw_error {
9566 struct fw_error_exception {
9567 __be32 info[6];
9568 } exception;
9569 struct fw_error_hwmodule {
9570 __be32 regaddr;
9571 __be32 regval;
9572 } hwmodule;
9573 struct fw_error_wr {
9574 __be16 cidx;
9575 __be16 pfn_vfn;
9576 __be32 eqid;
9577 __u8 wrhdr[16];
9578 } wr;
9579 struct fw_error_acl {
9580 __be16 cidx;
9581 __be16 pfn_vfn;
9582 __be32 eqid;
9583 __be16 mv_pkd;
9584 __u8 val[6];
9585 __be64 r4;
9586 } acl;
9587 } u;
9588 };
9589
9590 #define S_FW_ERROR_CMD_FATAL 4
9591 #define M_FW_ERROR_CMD_FATAL 0x1
9592 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL)
9593 #define G_FW_ERROR_CMD_FATAL(x) \
9594 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL)
9595 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U)
9596
9597 #define S_FW_ERROR_CMD_TYPE 0
9598 #define M_FW_ERROR_CMD_TYPE 0xf
9599 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE)
9600 #define G_FW_ERROR_CMD_TYPE(x) \
9601 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE)
9602
9603 #define S_FW_ERROR_CMD_PFN 8
9604 #define M_FW_ERROR_CMD_PFN 0x7
9605 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN)
9606 #define G_FW_ERROR_CMD_PFN(x) \
9607 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
9608
9609 #define S_FW_ERROR_CMD_VFN 0
9610 #define M_FW_ERROR_CMD_VFN 0xff
9611 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN)
9612 #define G_FW_ERROR_CMD_VFN(x) \
9613 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
9614
9615 #define S_FW_ERROR_CMD_PFN 8
9616 #define M_FW_ERROR_CMD_PFN 0x7
9617 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN)
9618 #define G_FW_ERROR_CMD_PFN(x) \
9619 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
9620
9621 #define S_FW_ERROR_CMD_VFN 0
9622 #define M_FW_ERROR_CMD_VFN 0xff
9623 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN)
9624 #define G_FW_ERROR_CMD_VFN(x) \
9625 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
9626
9627 #define S_FW_ERROR_CMD_MV 15
9628 #define M_FW_ERROR_CMD_MV 0x1
9629 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV)
9630 #define G_FW_ERROR_CMD_MV(x) \
9631 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV)
9632 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U)
9633
9634 struct fw_debug_cmd {
9635 __be32 op_type;
9636 __be32 len16_pkd;
9637 union fw_debug {
9638 struct fw_debug_assert {
9639 __be32 fcid;
9640 __be32 line;
9641 __be32 x;
9642 __be32 y;
9643 __u8 filename_0_7[8];
9644 __u8 filename_8_15[8];
9645 __be64 r3;
9646 } assert;
9647 struct fw_debug_prt {
9648 __be16 dprtstridx;
9649 __be16 r3[3];
9650 __be32 dprtstrparam0;
9651 __be32 dprtstrparam1;
9652 __be32 dprtstrparam2;
9653 __be32 dprtstrparam3;
9654 } prt;
9655 } u;
9656 };
9657
9658 #define S_FW_DEBUG_CMD_TYPE 0
9659 #define M_FW_DEBUG_CMD_TYPE 0xff
9660 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
9661 #define G_FW_DEBUG_CMD_TYPE(x) \
9662 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
9663
9664 enum fw_diag_cmd_type {
9665 FW_DIAG_CMD_TYPE_OFLDIAG = 0,
9666 FW_DIAG_CMD_TYPE_MEM_TEST_DIAG,
9667 };
9668
9669 enum fw_diag_cmd_ofldiag_op {
9670 FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0,
9671 FW_DIAG_CMD_OFLDIAG_TEST_START,
9672 FW_DIAG_CMD_OFLDIAG_TEST_STOP,
9673 FW_DIAG_CMD_OFLDIAG_TEST_STATUS,
9674 };
9675
9676 enum fw_diag_cmd_ofldiag_status {
9677 FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0,
9678 FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING,
9679 FW_DIAG_CMD_OFLDIAG_STATUS_FAILED,
9680 FW_DIAG_CMD_OFLDIAG_STATUS_PASSED,
9681 };
9682
9683 enum fw_diag_cmd_memdiag_op {
9684 FW_DIAG_CMD_MEMDIAG_TEST_START=1,
9685 FW_DIAG_CMD_MEMDIAG_TEST_STOP,
9686 FW_DIAG_CMD_MEMDIAG_TEST_STATUS,
9687 FW_DIAG_CMD_MEMDIAG_TEST_INIT,
9688 };
9689
9690
9691 enum fw_diag_cmd_memdiag_status {
9692 FW_DIAG_CMD_MEMDIAG_STATUS_NONE,
9693 FW_DIAG_CMD_MEMDIAG_STATUS_RUNNING,
9694 FW_DIAG_CMD_MEMDIAG_STATUS_FAILED,
9695 FW_DIAG_CMD_MEMDIAG_STATUS_PASSED
9696 };
9697
9698
9699 struct fw_diag_cmd {
9700 __be32 op_type;
9701 __be32 len16_pkd;
9702 union fw_diag_test {
9703 struct fw_diag_test_ofldiag {
9704 __u8 test_op;
9705 __u8 r3;
9706 __be16 test_status;
9707 __be32 duration;
9708 } ofldiag;
9709 struct fw_diag_test_memtest_diag {
9710 __u8 test_op;
9711 __u8 test_status;
9712 __be16 size; /* in KB */
9713 __be32 duration; /* in seconds */
9714 } memdiag;
9715 } u;
9716 };
9717
9718 #define S_FW_DIAG_CMD_OPCODE 24
9719 #define M_FW_DIAG_CMD_OPCODE 0xff
9720 #define V_FW_DIAG_CMD_OPCODE(x) ((x) << S_FW_DIAG_CMD_OPCODE)
9721 #define G_FW_DIAG_CMD_OPCODE(x) \
9722 (((x) >> S_FW_DIAG_CMD_OPCODE) & M_FW_DIAG_CMD_OPCODE)
9723
9724 #define S_FW_DIAG_CMD_TYPE 0
9725 #define M_FW_DIAG_CMD_TYPE 0xff
9726 #define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE)
9727 #define G_FW_DIAG_CMD_TYPE(x) \
9728 (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE)
9729
9730 #define S_FW_DIAG_CMD_LEN16 0
9731 #define M_FW_DIAG_CMD_LEN16 0xff
9732 #define V_FW_DIAG_CMD_LEN16(x) ((x) << S_FW_DIAG_CMD_LEN16)
9733 #define G_FW_DIAG_CMD_LEN16(x) \
9734 (((x) >> S_FW_DIAG_CMD_LEN16) & M_FW_DIAG_CMD_LEN16)
9735
9736 struct fw_hma_cmd {
9737 __be32 op_pkd;
9738 __be32 retval_len16;
9739 __be32 mode_to_pcie_params;
9740 __be32 naddr_size;
9741 __be32 addr_size_pkd;
9742 __be32 r6;
9743 __be64 phy_address[5];
9744 };
9745
9746 #define S_FW_HMA_CMD_MODE 31
9747 #define M_FW_HMA_CMD_MODE 0x1
9748 #define V_FW_HMA_CMD_MODE(x) ((x) << S_FW_HMA_CMD_MODE)
9749 #define G_FW_HMA_CMD_MODE(x) \
9750 (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE)
9751 #define F_FW_HMA_CMD_MODE V_FW_HMA_CMD_MODE(1U)
9752
9753 #define S_FW_HMA_CMD_SOC 30
9754 #define M_FW_HMA_CMD_SOC 0x1
9755 #define V_FW_HMA_CMD_SOC(x) ((x) << S_FW_HMA_CMD_SOC)
9756 #define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC)
9757 #define F_FW_HMA_CMD_SOC V_FW_HMA_CMD_SOC(1U)
9758
9759 #define S_FW_HMA_CMD_EOC 29
9760 #define M_FW_HMA_CMD_EOC 0x1
9761 #define V_FW_HMA_CMD_EOC(x) ((x) << S_FW_HMA_CMD_EOC)
9762 #define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC)
9763 #define F_FW_HMA_CMD_EOC V_FW_HMA_CMD_EOC(1U)
9764
9765 #define S_FW_HMA_CMD_PCIE_PARAMS 0
9766 #define M_FW_HMA_CMD_PCIE_PARAMS 0x7ffffff
9767 #define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS)
9768 #define G_FW_HMA_CMD_PCIE_PARAMS(x) \
9769 (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS)
9770
9771 #define S_FW_HMA_CMD_NADDR 12
9772 #define M_FW_HMA_CMD_NADDR 0x3f
9773 #define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR)
9774 #define G_FW_HMA_CMD_NADDR(x) \
9775 (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR)
9776
9777 #define S_FW_HMA_CMD_SIZE 0
9778 #define M_FW_HMA_CMD_SIZE 0xfff
9779 #define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE)
9780 #define G_FW_HMA_CMD_SIZE(x) \
9781 (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE)
9782
9783 #define S_FW_HMA_CMD_ADDR_SIZE 11
9784 #define M_FW_HMA_CMD_ADDR_SIZE 0x1fffff
9785 #define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE)
9786 #define G_FW_HMA_CMD_ADDR_SIZE(x) \
9787 (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE)
9788
9789 /******************************************************************************
9790 * P C I E F W R E G I S T E R
9791 **************************************/
9792
9793 enum pcie_fw_eval {
9794 PCIE_FW_EVAL_CRASH = 0,
9795 PCIE_FW_EVAL_PREP = 1,
9796 PCIE_FW_EVAL_CONF = 2,
9797 PCIE_FW_EVAL_INIT = 3,
9798 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4,
9799 PCIE_FW_EVAL_OVERHEAT = 5,
9800 PCIE_FW_EVAL_DEVICESHUTDOWN = 6,
9801 };
9802
9803 /**
9804 * Register definitions for the PCIE_FW register which the firmware uses
9805 * to retain status across RESETs. This register should be considered
9806 * as a READ-ONLY register for Host Software and only to be used to
9807 * track firmware initialization/error state, etc.
9808 */
9809 #define S_PCIE_FW_ERR 31
9810 #define M_PCIE_FW_ERR 0x1
9811 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
9812 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
9813 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
9814
9815 #define S_PCIE_FW_INIT 30
9816 #define M_PCIE_FW_INIT 0x1
9817 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
9818 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
9819 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
9820
9821 #define S_PCIE_FW_HALT 29
9822 #define M_PCIE_FW_HALT 0x1
9823 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
9824 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
9825 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
9826
9827 #define S_PCIE_FW_EVAL 24
9828 #define M_PCIE_FW_EVAL 0x7
9829 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
9830 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
9831
9832 #define S_PCIE_FW_STAGE 21
9833 #define M_PCIE_FW_STAGE 0x7
9834 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE)
9835 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE)
9836
9837 #define S_PCIE_FW_ASYNCNOT_VLD 20
9838 #define M_PCIE_FW_ASYNCNOT_VLD 0x1
9839 #define V_PCIE_FW_ASYNCNOT_VLD(x) \
9840 ((x) << S_PCIE_FW_ASYNCNOT_VLD)
9841 #define G_PCIE_FW_ASYNCNOT_VLD(x) \
9842 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD)
9843 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U)
9844
9845 #define S_PCIE_FW_ASYNCNOTINT 19
9846 #define M_PCIE_FW_ASYNCNOTINT 0x1
9847 #define V_PCIE_FW_ASYNCNOTINT(x) \
9848 ((x) << S_PCIE_FW_ASYNCNOTINT)
9849 #define G_PCIE_FW_ASYNCNOTINT(x) \
9850 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT)
9851 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U)
9852
9853 #define S_PCIE_FW_ASYNCNOT 16
9854 #define M_PCIE_FW_ASYNCNOT 0x7
9855 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT)
9856 #define G_PCIE_FW_ASYNCNOT(x) \
9857 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT)
9858
9859 #define S_PCIE_FW_MASTER_VLD 15
9860 #define M_PCIE_FW_MASTER_VLD 0x1
9861 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
9862 #define G_PCIE_FW_MASTER_VLD(x) \
9863 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
9864 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
9865
9866 #define S_PCIE_FW_MASTER 12
9867 #define M_PCIE_FW_MASTER 0x7
9868 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
9869 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
9870
9871 #define S_PCIE_FW_RESET_VLD 11
9872 #define M_PCIE_FW_RESET_VLD 0x1
9873 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD)
9874 #define G_PCIE_FW_RESET_VLD(x) \
9875 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD)
9876 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U)
9877
9878 #define S_PCIE_FW_RESET 8
9879 #define M_PCIE_FW_RESET 0x7
9880 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET)
9881 #define G_PCIE_FW_RESET(x) \
9882 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET)
9883
9884 #define S_PCIE_FW_REGISTERED 0
9885 #define M_PCIE_FW_REGISTERED 0xff
9886 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED)
9887 #define G_PCIE_FW_REGISTERED(x) \
9888 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
9889
9890
9891 /******************************************************************************
9892 * P C I E F W P F 0 R E G I S T E R
9893 **********************************************/
9894
9895 /*
9896 * this register is available as 32-bit of persistent storage (across
9897 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver
9898 * will not write it)
9899 */
9900
9901
9902 /******************************************************************************
9903 * P C I E F W P F 7 R E G I S T E R
9904 **********************************************/
9905
9906 /*
9907 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to
9908 * access the "devlog" which needing to contact firmware. The encoding is
9909 * mostly the same as that returned by the DEVLOG command except for the size
9910 * which is encoded as the number of entries in multiples-1 of 128 here rather
9911 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128
9912 * and 15 means 2048. This of course in turn constrains the allowed values
9913 * for the devlog size ...
9914 */
9915 #define PCIE_FW_PF_DEVLOG 7
9916
9917 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28
9918 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf
9919 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
9920 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128)
9921 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
9922 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \
9923 M_PCIE_FW_PF_DEVLOG_NENTRIES128)
9924
9925 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4
9926 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff
9927 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16)
9928 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \
9929 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16)
9930
9931 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0
9932 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf
9933 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE)
9934 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \
9935 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE)
9936
9937
9938 /******************************************************************************
9939 * B I N A R Y H E A D E R F O R M A T
9940 **********************************************/
9941
9942 /*
9943 * firmware binary header format
9944 */
9945 struct fw_hdr {
9946 __u8 ver;
9947 __u8 chip; /* terminator chip family */
9948 __be16 len512; /* bin length in units of 512-bytes */
9949 __be32 fw_ver; /* firmware version */
9950 __be32 tp_microcode_ver; /* tcp processor microcode version */
9951 __u8 intfver_nic;
9952 __u8 intfver_vnic;
9953 __u8 intfver_ofld;
9954 __u8 intfver_ri;
9955 __u8 intfver_iscsipdu;
9956 __u8 intfver_iscsi;
9957 __u8 intfver_fcoepdu;
9958 __u8 intfver_fcoe;
9959 __u32 reserved2;
9960 __u32 reserved3;
9961 __be32 magic; /* runtime or bootstrap fw */
9962 __be32 flags;
9963 __be32 reserved6[4];
9964 __u8 reserved7[3];
9965 __u8 dsign_len;
9966 __u8 dsign[72]; /* fw binary digital signature */
9967 };
9968
9969 enum fw_hdr_chip {
9970 FW_HDR_CHIP_T4,
9971 FW_HDR_CHIP_T5,
9972 FW_HDR_CHIP_T6
9973 };
9974
9975 #define S_FW_HDR_FW_VER_MAJOR 24
9976 #define M_FW_HDR_FW_VER_MAJOR 0xff
9977 #define V_FW_HDR_FW_VER_MAJOR(x) \
9978 ((x) << S_FW_HDR_FW_VER_MAJOR)
9979 #define G_FW_HDR_FW_VER_MAJOR(x) \
9980 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
9981
9982 #define S_FW_HDR_FW_VER_MINOR 16
9983 #define M_FW_HDR_FW_VER_MINOR 0xff
9984 #define V_FW_HDR_FW_VER_MINOR(x) \
9985 ((x) << S_FW_HDR_FW_VER_MINOR)
9986 #define G_FW_HDR_FW_VER_MINOR(x) \
9987 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
9988
9989 #define S_FW_HDR_FW_VER_MICRO 8
9990 #define M_FW_HDR_FW_VER_MICRO 0xff
9991 #define V_FW_HDR_FW_VER_MICRO(x) \
9992 ((x) << S_FW_HDR_FW_VER_MICRO)
9993 #define G_FW_HDR_FW_VER_MICRO(x) \
9994 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
9995
9996 #define S_FW_HDR_FW_VER_BUILD 0
9997 #define M_FW_HDR_FW_VER_BUILD 0xff
9998 #define V_FW_HDR_FW_VER_BUILD(x) \
9999 ((x) << S_FW_HDR_FW_VER_BUILD)
10000 #define G_FW_HDR_FW_VER_BUILD(x) \
10001 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
10002
10003 enum {
10004 T4FW_VERSION_MAJOR = 1,
10005 T4FW_VERSION_MINOR = 27,
10006 T4FW_VERSION_MICRO = 0,
10007 T4FW_VERSION_BUILD = 0,
10008
10009 T5FW_VERSION_MAJOR = 1,
10010 T5FW_VERSION_MINOR = 27,
10011 T5FW_VERSION_MICRO = 0,
10012 T5FW_VERSION_BUILD = 0,
10013
10014 T6FW_VERSION_MAJOR = 1,
10015 T6FW_VERSION_MINOR = 27,
10016 T6FW_VERSION_MICRO = 0,
10017 T6FW_VERSION_BUILD = 0,
10018 };
10019
10020 enum {
10021 /* T4
10022 */
10023 T4FW_HDR_INTFVER_NIC = 0x00,
10024 T4FW_HDR_INTFVER_VNIC = 0x00,
10025 T4FW_HDR_INTFVER_OFLD = 0x00,
10026 T4FW_HDR_INTFVER_RI = 0x00,
10027 T4FW_HDR_INTFVER_ISCSIPDU= 0x00,
10028 T4FW_HDR_INTFVER_ISCSI = 0x00,
10029 T4FW_HDR_INTFVER_FCOEPDU = 0x00,
10030 T4FW_HDR_INTFVER_FCOE = 0x00,
10031
10032 /* T5
10033 */
10034 T5FW_HDR_INTFVER_NIC = 0x00,
10035 T5FW_HDR_INTFVER_VNIC = 0x00,
10036 T5FW_HDR_INTFVER_OFLD = 0x00,
10037 T5FW_HDR_INTFVER_RI = 0x00,
10038 T5FW_HDR_INTFVER_ISCSIPDU= 0x00,
10039 T5FW_HDR_INTFVER_ISCSI = 0x00,
10040 T5FW_HDR_INTFVER_FCOEPDU= 0x00,
10041 T5FW_HDR_INTFVER_FCOE = 0x00,
10042
10043 /* T6
10044 */
10045 T6FW_HDR_INTFVER_NIC = 0x00,
10046 T6FW_HDR_INTFVER_VNIC = 0x00,
10047 T6FW_HDR_INTFVER_OFLD = 0x00,
10048 T6FW_HDR_INTFVER_RI = 0x00,
10049 T6FW_HDR_INTFVER_ISCSIPDU= 0x00,
10050 T6FW_HDR_INTFVER_ISCSI = 0x00,
10051 T6FW_HDR_INTFVER_FCOEPDU= 0x00,
10052 T6FW_HDR_INTFVER_FCOE = 0x00,
10053 };
10054
10055 #define FW_VERSION32(MAJOR, MINOR, MICRO, BUILD) ( \
10056 V_FW_HDR_FW_VER_MAJOR(MAJOR) | V_FW_HDR_FW_VER_MINOR(MINOR) | \
10057 V_FW_HDR_FW_VER_MICRO(MICRO) | V_FW_HDR_FW_VER_BUILD(BUILD))
10058
10059 enum {
10060 FW_HDR_MAGIC_RUNTIME = 0x00000000,
10061 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74,
10062 };
10063
10064 enum fw_hdr_flags {
10065 FW_HDR_FLAGS_RESET_HALT = 0x00000001,
10066 FW_HDR_FLAGS_SIGNED_FW = 0x00000002,
10067 };
10068
10069 /*
10070 * External PHY firmware binary header format
10071 */
10072 struct fw_ephy_hdr {
10073 __u8 ver;
10074 __u8 reserved;
10075 __be16 len512; /* bin length in units of 512-bytes */
10076 __be32 magic;
10077
10078 __be16 vendor_id;
10079 __be16 device_id;
10080 __be32 version;
10081
10082 __be32 reserved1[4];
10083 };
10084
10085 enum {
10086 FW_EPHY_HDR_MAGIC = 0x65706879,
10087 };
10088
10089 struct fw_ifconf_dhcp_info {
10090 __be32 addr;
10091 __be32 mask;
10092 __be16 vlanid;
10093 __be16 mtu;
10094 __be32 gw;
10095 __u8 op;
10096 __u8 len;
10097 __u8 data[270];
10098 };
10099
10100 struct fw_ifconf_ping_info {
10101 __be16 ping_pldsize;
10102 };
10103
10104 #endif /* _T4FW_INTERFACE_H_ */
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