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sys/dev/cxgbe/iw_cxgbe/qp.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include "opt_inet.h" 38 39 #ifdef TCP_OFFLOAD 40 #include <sys/types.h> 41 #include <sys/malloc.h> 42 #include <sys/socket.h> 43 #include <sys/socketvar.h> 44 #include <sys/sockio.h> 45 #include <sys/taskqueue.h> 46 #include <netinet/in.h> 47 #include <net/route.h> 48 49 #include <netinet/in_systm.h> 50 #include <netinet/in_pcb.h> 51 #include <netinet/ip.h> 52 #include <netinet/ip_var.h> 53 #include <netinet/tcp_var.h> 54 #include <netinet/tcp.h> 55 #include <netinet/tcpip.h> 56 57 #include <netinet/toecore.h> 58 59 struct sge_iq; 60 struct rss_header; 61 struct cpl_set_tcb_rpl; 62 #include <linux/types.h> 63 #include "offload.h" 64 #include "tom/t4_tom.h" 65 66 #include "iw_cxgbe.h" 67 #include "user.h" 68 69 static int creds(struct toepcb *toep, struct inpcb *inp, size_t wrsize); 70 static int max_fr_immd = T4_MAX_FR_IMMD;//SYSCTL parameter later... 71 72 static int alloc_ird(struct c4iw_dev *dev, u32 ird) 73 { 74 int ret = 0; 75 76 spin_lock_irq(&dev->lock); 77 if (ird <= dev->avail_ird) 78 dev->avail_ird -= ird; 79 else 80 ret = -ENOMEM; 81 spin_unlock_irq(&dev->lock); 82 83 if (ret) 84 log(LOG_WARNING, "%s: device IRD resources exhausted\n", 85 device_get_nameunit(dev->rdev.adap->dev)); 86 87 return ret; 88 } 89 90 static void free_ird(struct c4iw_dev *dev, int ird) 91 { 92 spin_lock_irq(&dev->lock); 93 dev->avail_ird += ird; 94 spin_unlock_irq(&dev->lock); 95 } 96 97 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) 98 { 99 unsigned long flag; 100 spin_lock_irqsave(&qhp->lock, flag); 101 qhp->attr.state = state; 102 spin_unlock_irqrestore(&qhp->lock, flag); 103 } 104 105 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 106 struct c4iw_dev_ucontext *uctx) 107 { 108 struct c4iw_dev *rhp = rdev_to_c4iw_dev(rdev); 109 /* 110 * uP clears EQ contexts when the connection exits rdma mode, 111 * so no need to post a RESET WR for these EQs. 112 */ 113 dma_free_coherent(rhp->ibdev.dma_device, 114 wq->rq.memsize, wq->rq.queue, 115 dma_unmap_addr(&wq->rq, mapping)); 116 dma_free_coherent(rhp->ibdev.dma_device, 117 wq->sq.memsize, wq->sq.queue, 118 dma_unmap_addr(&wq->sq, mapping)); 119 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 120 kfree(wq->rq.sw_rq); 121 kfree(wq->sq.sw_sq); 122 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 123 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 124 return 0; 125 } 126 127 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 128 struct t4_cq *rcq, struct t4_cq *scq, 129 struct c4iw_dev_ucontext *uctx) 130 { 131 struct adapter *sc = rdev->adap; 132 struct c4iw_dev *rhp = rdev_to_c4iw_dev(rdev); 133 int user = (uctx != &rdev->uctx); 134 struct fw_ri_res_wr *res_wr; 135 struct fw_ri_res *res; 136 int wr_len; 137 struct c4iw_wr_wait wr_wait; 138 int ret = 0; 139 int eqsize; 140 struct wrqe *wr; 141 u64 sq_bar2_qoffset = 0, rq_bar2_qoffset = 0; 142 143 wq->sq.qid = c4iw_get_qpid(rdev, uctx); 144 if (!wq->sq.qid) 145 return -ENOMEM; 146 147 wq->rq.qid = c4iw_get_qpid(rdev, uctx); 148 if (!wq->rq.qid) { 149 ret = -ENOMEM; 150 goto free_sq_qid; 151 } 152 153 if (!user) { 154 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq, 155 GFP_KERNEL); 156 if (!wq->sq.sw_sq) { 157 ret = -ENOMEM; 158 goto free_rq_qid; 159 } 160 161 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq, 162 GFP_KERNEL); 163 if (!wq->rq.sw_rq) { 164 ret = -ENOMEM; 165 goto free_sw_sq; 166 } 167 } 168 169 /* 170 * RQT must be a power of 2 and at least 16 deep. 171 */ 172 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16)); 173 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size); 174 if (!wq->rq.rqt_hwaddr) { 175 ret = -ENOMEM; 176 goto free_sw_rq; 177 } 178 179 /*QP memory, allocate DMAable memory for Send & Receive Queues */ 180 wq->sq.queue = dma_alloc_coherent(rhp->ibdev.dma_device, wq->sq.memsize, 181 &(wq->sq.dma_addr), GFP_KERNEL); 182 if (!wq->sq.queue) { 183 ret = -ENOMEM; 184 goto free_hwaddr; 185 } 186 wq->sq.phys_addr = vtophys(wq->sq.queue); 187 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); 188 memset(wq->sq.queue, 0, wq->sq.memsize); 189 190 wq->rq.queue = dma_alloc_coherent(rhp->ibdev.dma_device, 191 wq->rq.memsize, &(wq->rq.dma_addr), GFP_KERNEL); 192 if (!wq->rq.queue) { 193 ret = -ENOMEM; 194 goto free_sq_dma; 195 } 196 wq->rq.phys_addr = vtophys(wq->rq.queue); 197 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr); 198 memset(wq->rq.queue, 0, wq->rq.memsize); 199 200 CTR5(KTR_IW_CXGBE, 201 "%s QP sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx", 202 __func__, 203 wq->sq.queue, (unsigned long long)wq->sq.phys_addr, 204 wq->rq.queue, (unsigned long long)wq->rq.phys_addr); 205 206 /* Doorbell/WC regions, determine the BAR2 queue offset and qid. */ 207 t4_bar2_sge_qregs(rdev->adap, wq->sq.qid, T4_BAR2_QTYPE_EGRESS, user, 208 &sq_bar2_qoffset, &wq->sq.bar2_qid); 209 t4_bar2_sge_qregs(rdev->adap, wq->rq.qid, T4_BAR2_QTYPE_EGRESS, user, 210 &rq_bar2_qoffset, &wq->rq.bar2_qid); 211 212 if (user) { 213 /* Compute BAR2 DB/WC physical address(page-aligned) for 214 * Userspace mapping. 215 */ 216 wq->sq.bar2_pa = (rdev->bar2_pa + sq_bar2_qoffset) & PAGE_MASK; 217 wq->rq.bar2_pa = (rdev->bar2_pa + rq_bar2_qoffset) & PAGE_MASK; 218 CTR3(KTR_IW_CXGBE, 219 "%s BAR2 DB/WC sq base pa 0x%llx rq base pa 0x%llx", 220 __func__, (unsigned long long)wq->sq.bar2_pa, 221 (unsigned long long)wq->rq.bar2_pa); 222 } else { 223 /* Compute BAR2 DB/WC virtual address to access in kernel. */ 224 wq->sq.bar2_va = (void __iomem *)((u64)rdev->bar2_kva + 225 sq_bar2_qoffset); 226 wq->rq.bar2_va = (void __iomem *)((u64)rdev->bar2_kva + 227 rq_bar2_qoffset); 228 CTR3(KTR_IW_CXGBE, "%s BAR2 DB/WC sq base va %p rq base va %p", 229 __func__, (unsigned long long)wq->sq.bar2_va, 230 (unsigned long long)wq->rq.bar2_va); 231 } 232 233 wq->rdev = rdev; 234 wq->rq.msn = 1; 235 236 /* build fw_ri_res_wr */ 237 wr_len = sizeof *res_wr + 2 * sizeof *res; 238 239 wr = alloc_wrqe(wr_len, &sc->sge.ctrlq[0]); 240 if (wr == NULL) { 241 ret = -ENOMEM; 242 goto free_rq_dma; 243 } 244 res_wr = wrtod(wr); 245 246 memset(res_wr, 0, wr_len); 247 res_wr->op_nres = cpu_to_be32( 248 V_FW_WR_OP(FW_RI_RES_WR) | 249 V_FW_RI_RES_WR_NRES(2) | 250 F_FW_WR_COMPL); 251 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 252 res_wr->cookie = (unsigned long) &wr_wait; 253 res = res_wr->res; 254 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 255 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 256 257 /* eqsize is the number of 64B entries plus the status page size. */ 258 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + 259 rdev->hw_queue.t4_eq_status_entries; 260 261 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 262 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 263 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 264 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 265 V_FW_RI_RES_WR_IQID(scq->cqid)); 266 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 267 V_FW_RI_RES_WR_DCAEN(0) | 268 V_FW_RI_RES_WR_DCACPU(0) | 269 V_FW_RI_RES_WR_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 270 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 271 V_FW_RI_RES_WR_FBMAX(3) | 272 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 273 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 274 V_FW_RI_RES_WR_EQSIZE(eqsize)); 275 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid); 276 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr); 277 res++; 278 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ; 279 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 280 281 /* eqsize is the number of 64B entries plus the status page size. */ 282 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + 283 rdev->hw_queue.t4_eq_status_entries; 284 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 285 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 286 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 287 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 288 V_FW_RI_RES_WR_IQID(rcq->cqid)); 289 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 290 V_FW_RI_RES_WR_DCAEN(0) | 291 V_FW_RI_RES_WR_DCACPU(0) | 292 V_FW_RI_RES_WR_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 293 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 294 V_FW_RI_RES_WR_FBMAX(3) | 295 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 296 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 297 V_FW_RI_RES_WR_EQSIZE(eqsize)); 298 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); 299 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); 300 301 c4iw_init_wr_wait(&wr_wait); 302 303 t4_wrq_tx(sc, wr); 304 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, 305 NULL, __func__); 306 if (ret) 307 goto free_rq_dma; 308 309 CTR5(KTR_IW_CXGBE, 310 "%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx", 311 __func__, wq->sq.qid, wq->rq.qid, 312 (unsigned long long)wq->sq.bar2_va, 313 (unsigned long long)wq->rq.bar2_va); 314 315 return 0; 316 free_rq_dma: 317 dma_free_coherent(rhp->ibdev.dma_device, 318 wq->rq.memsize, wq->rq.queue, 319 dma_unmap_addr(&wq->rq, mapping)); 320 free_sq_dma: 321 dma_free_coherent(rhp->ibdev.dma_device, 322 wq->sq.memsize, wq->sq.queue, 323 dma_unmap_addr(&wq->sq, mapping)); 324 free_hwaddr: 325 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 326 free_sw_rq: 327 kfree(wq->rq.sw_rq); 328 free_sw_sq: 329 kfree(wq->sq.sw_sq); 330 free_rq_qid: 331 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 332 free_sq_qid: 333 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 334 return ret; 335 } 336 337 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp, 338 const struct ib_send_wr *wr, int max, u32 *plenp) 339 { 340 u8 *dstp, *srcp; 341 u32 plen = 0; 342 int i; 343 int rem, len; 344 345 dstp = (u8 *)immdp->data; 346 for (i = 0; i < wr->num_sge; i++) { 347 if ((plen + wr->sg_list[i].length) > max) 348 return -EMSGSIZE; 349 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr; 350 plen += wr->sg_list[i].length; 351 rem = wr->sg_list[i].length; 352 while (rem) { 353 if (dstp == (u8 *)&sq->queue[sq->size]) 354 dstp = (u8 *)sq->queue; 355 if (rem <= (u8 *)&sq->queue[sq->size] - dstp) 356 len = rem; 357 else 358 len = (u8 *)&sq->queue[sq->size] - dstp; 359 memcpy(dstp, srcp, len); 360 dstp += len; 361 srcp += len; 362 rem -= len; 363 } 364 } 365 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp); 366 if (len) 367 memset(dstp, 0, len); 368 immdp->op = FW_RI_DATA_IMMD; 369 immdp->r1 = 0; 370 immdp->r2 = 0; 371 immdp->immdlen = cpu_to_be32(plen); 372 *plenp = plen; 373 return 0; 374 } 375 376 static int build_isgl(__be64 *queue_start, __be64 *queue_end, 377 struct fw_ri_isgl *isglp, struct ib_sge *sg_list, 378 int num_sge, u32 *plenp) 379 380 { 381 int i; 382 u32 plen = 0; 383 __be64 *flitp = (__be64 *)isglp->sge; 384 385 for (i = 0; i < num_sge; i++) { 386 if ((plen + sg_list[i].length) < plen) 387 return -EMSGSIZE; 388 plen += sg_list[i].length; 389 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) | 390 sg_list[i].length); 391 if (++flitp == queue_end) 392 flitp = queue_start; 393 *flitp = cpu_to_be64(sg_list[i].addr); 394 if (++flitp == queue_end) 395 flitp = queue_start; 396 } 397 *flitp = (__force __be64)0; 398 isglp->op = FW_RI_DATA_ISGL; 399 isglp->r1 = 0; 400 isglp->nsge = cpu_to_be16(num_sge); 401 isglp->r2 = 0; 402 if (plenp) 403 *plenp = plen; 404 return 0; 405 } 406 407 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, 408 const struct ib_send_wr *wr, u8 *len16) 409 { 410 u32 plen; 411 int size; 412 int ret; 413 414 if (wr->num_sge > T4_MAX_SEND_SGE) 415 return -EINVAL; 416 switch (wr->opcode) { 417 case IB_WR_SEND: 418 if (wr->send_flags & IB_SEND_SOLICITED) 419 wqe->send.sendop_pkd = cpu_to_be32( 420 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE)); 421 else 422 wqe->send.sendop_pkd = cpu_to_be32( 423 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND)); 424 wqe->send.stag_inv = 0; 425 break; 426 case IB_WR_SEND_WITH_INV: 427 if (wr->send_flags & IB_SEND_SOLICITED) 428 wqe->send.sendop_pkd = cpu_to_be32( 429 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV)); 430 else 431 wqe->send.sendop_pkd = cpu_to_be32( 432 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV)); 433 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 434 break; 435 436 default: 437 return -EINVAL; 438 } 439 wqe->send.r3 = 0; 440 wqe->send.r4 = 0; 441 442 plen = 0; 443 if (wr->num_sge) { 444 if (wr->send_flags & IB_SEND_INLINE) { 445 ret = build_immd(sq, wqe->send.u.immd_src, wr, 446 T4_MAX_SEND_INLINE, &plen); 447 if (ret) 448 return ret; 449 size = sizeof wqe->send + sizeof(struct fw_ri_immd) + 450 plen; 451 } else { 452 ret = build_isgl((__be64 *)sq->queue, 453 (__be64 *)&sq->queue[sq->size], 454 wqe->send.u.isgl_src, 455 wr->sg_list, wr->num_sge, &plen); 456 if (ret) 457 return ret; 458 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) + 459 wr->num_sge * sizeof(struct fw_ri_sge); 460 } 461 } else { 462 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD; 463 wqe->send.u.immd_src[0].r1 = 0; 464 wqe->send.u.immd_src[0].r2 = 0; 465 wqe->send.u.immd_src[0].immdlen = 0; 466 size = sizeof wqe->send + sizeof(struct fw_ri_immd); 467 plen = 0; 468 } 469 *len16 = DIV_ROUND_UP(size, 16); 470 wqe->send.plen = cpu_to_be32(plen); 471 return 0; 472 } 473 474 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, 475 const struct ib_send_wr *wr, u8 *len16) 476 { 477 u32 plen; 478 int size; 479 int ret; 480 481 if (wr->num_sge > T4_MAX_SEND_SGE) 482 return -EINVAL; 483 wqe->write.immd_data = 0; 484 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey); 485 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr); 486 if (wr->num_sge) { 487 if (wr->send_flags & IB_SEND_INLINE) { 488 ret = build_immd(sq, wqe->write.u.immd_src, wr, 489 T4_MAX_WRITE_INLINE, &plen); 490 if (ret) 491 return ret; 492 size = sizeof wqe->write + sizeof(struct fw_ri_immd) + 493 plen; 494 } else { 495 ret = build_isgl((__be64 *)sq->queue, 496 (__be64 *)&sq->queue[sq->size], 497 wqe->write.u.isgl_src, 498 wr->sg_list, wr->num_sge, &plen); 499 if (ret) 500 return ret; 501 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) + 502 wr->num_sge * sizeof(struct fw_ri_sge); 503 } 504 } else { 505 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD; 506 wqe->write.u.immd_src[0].r1 = 0; 507 wqe->write.u.immd_src[0].r2 = 0; 508 wqe->write.u.immd_src[0].immdlen = 0; 509 size = sizeof wqe->write + sizeof(struct fw_ri_immd); 510 plen = 0; 511 } 512 *len16 = DIV_ROUND_UP(size, 16); 513 wqe->write.plen = cpu_to_be32(plen); 514 return 0; 515 } 516 517 static int build_rdma_read(union t4_wr *wqe, const struct ib_send_wr *wr, u8 *len16) 518 { 519 if (wr->num_sge > 1) 520 return -EINVAL; 521 if (wr->num_sge && wr->sg_list[0].length) { 522 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey); 523 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr 524 >> 32)); 525 wqe->read.to_src_lo = 526 cpu_to_be32((u32)rdma_wr(wr)->remote_addr); 527 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey); 528 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length); 529 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr 530 >> 32)); 531 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr)); 532 } else { 533 wqe->read.stag_src = cpu_to_be32(2); 534 wqe->read.to_src_hi = 0; 535 wqe->read.to_src_lo = 0; 536 wqe->read.stag_sink = cpu_to_be32(2); 537 wqe->read.plen = 0; 538 wqe->read.to_sink_hi = 0; 539 wqe->read.to_sink_lo = 0; 540 } 541 wqe->read.r2 = 0; 542 wqe->read.r5 = 0; 543 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 544 return 0; 545 } 546 547 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, 548 const struct ib_recv_wr *wr, u8 *len16) 549 { 550 int ret; 551 552 ret = build_isgl((__be64 *)qhp->wq.rq.queue, 553 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size], 554 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL); 555 if (ret) 556 return ret; 557 *len16 = DIV_ROUND_UP(sizeof wqe->recv + 558 wr->num_sge * sizeof(struct fw_ri_sge), 16); 559 return 0; 560 } 561 562 static int build_inv_stag(union t4_wr *wqe, const struct ib_send_wr *wr, 563 u8 *len16) 564 { 565 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 566 wqe->inv.r2 = 0; 567 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); 568 return 0; 569 } 570 571 static void free_qp_work(struct work_struct *work) 572 { 573 struct c4iw_ucontext *ucontext; 574 struct c4iw_qp *qhp; 575 struct c4iw_dev *rhp; 576 577 qhp = container_of(work, struct c4iw_qp, free_work); 578 ucontext = qhp->ucontext; 579 rhp = qhp->rhp; 580 581 CTR3(KTR_IW_CXGBE, "%s qhp %p ucontext %p", __func__, 582 qhp, ucontext); 583 destroy_qp(&rhp->rdev, &qhp->wq, 584 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 585 586 kfree(qhp); 587 } 588 589 static void queue_qp_free(struct kref *kref) 590 { 591 struct c4iw_qp *qhp; 592 593 qhp = container_of(kref, struct c4iw_qp, kref); 594 CTR2(KTR_IW_CXGBE, "%s qhp %p", __func__, qhp); 595 queue_work(qhp->rhp->rdev.free_workq, &qhp->free_work); 596 } 597 598 void c4iw_qp_add_ref(struct ib_qp *qp) 599 { 600 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 601 kref_get(&to_c4iw_qp(qp)->kref); 602 } 603 604 void c4iw_qp_rem_ref(struct ib_qp *qp) 605 { 606 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 607 kref_put(&to_c4iw_qp(qp)->kref, queue_qp_free); 608 } 609 610 static void complete_sq_drain_wr(struct c4iw_qp *qhp, const struct ib_send_wr *wr) 611 { 612 struct t4_cqe cqe = {}; 613 struct c4iw_cq *schp; 614 unsigned long flag; 615 struct t4_cq *cq; 616 617 schp = to_c4iw_cq(qhp->ibqp.send_cq); 618 cq = &schp->cq; 619 620 PDBG("%s drain sq id %u\n", __func__, qhp->wq.sq.qid); 621 cqe.u.drain_cookie = wr->wr_id; 622 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) | 623 V_CQE_OPCODE(C4IW_DRAIN_OPCODE) | 624 V_CQE_TYPE(1) | 625 V_CQE_SWCQE(1) | 626 V_CQE_QPID(qhp->wq.sq.qid)); 627 628 spin_lock_irqsave(&schp->lock, flag); 629 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen)); 630 cq->sw_queue[cq->sw_pidx] = cqe; 631 t4_swcq_produce(cq); 632 spin_unlock_irqrestore(&schp->lock, flag); 633 634 spin_lock_irqsave(&schp->comp_handler_lock, flag); 635 (*schp->ibcq.comp_handler)(&schp->ibcq, 636 schp->ibcq.cq_context); 637 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 638 } 639 640 static void complete_rq_drain_wr(struct c4iw_qp *qhp, const struct ib_recv_wr *wr) 641 { 642 struct t4_cqe cqe = {}; 643 struct c4iw_cq *rchp; 644 unsigned long flag; 645 struct t4_cq *cq; 646 647 rchp = to_c4iw_cq(qhp->ibqp.recv_cq); 648 cq = &rchp->cq; 649 650 PDBG("%s drain rq id %u\n", __func__, qhp->wq.sq.qid); 651 cqe.u.drain_cookie = wr->wr_id; 652 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) | 653 V_CQE_OPCODE(C4IW_DRAIN_OPCODE) | 654 V_CQE_TYPE(0) | 655 V_CQE_SWCQE(1) | 656 V_CQE_QPID(qhp->wq.sq.qid)); 657 658 spin_lock_irqsave(&rchp->lock, flag); 659 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen)); 660 cq->sw_queue[cq->sw_pidx] = cqe; 661 t4_swcq_produce(cq); 662 spin_unlock_irqrestore(&rchp->lock, flag); 663 664 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 665 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 666 rchp->ibcq.cq_context); 667 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 668 } 669 670 static int build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr, 671 const struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16) 672 { 673 __be64 *p = (__be64 *)fr->pbl; 674 675 if (wr->mr->page_size > C4IW_MAX_PAGE_SIZE) 676 return -EINVAL; 677 678 fr->r2 = cpu_to_be32(0); 679 fr->stag = cpu_to_be32(mhp->ibmr.rkey); 680 681 fr->tpte.valid_to_pdid = cpu_to_be32(F_FW_RI_TPTE_VALID | 682 V_FW_RI_TPTE_STAGKEY((mhp->ibmr.rkey & M_FW_RI_TPTE_STAGKEY)) | 683 V_FW_RI_TPTE_STAGSTATE(1) | 684 V_FW_RI_TPTE_STAGTYPE(FW_RI_STAG_NSMR) | 685 V_FW_RI_TPTE_PDID(mhp->attr.pdid)); 686 fr->tpte.locread_to_qpid = cpu_to_be32( 687 V_FW_RI_TPTE_PERM(c4iw_ib_to_tpt_access(wr->access)) | 688 V_FW_RI_TPTE_ADDRTYPE(FW_RI_VA_BASED_TO) | 689 V_FW_RI_TPTE_PS(ilog2(wr->mr->page_size) - 12)); 690 fr->tpte.nosnoop_pbladdr = cpu_to_be32(V_FW_RI_TPTE_PBLADDR( 691 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3)); 692 fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0); 693 fr->tpte.len_hi = cpu_to_be32(mhp->ibmr.length >> 32); 694 fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length & 0xffffffff); 695 fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32); 696 fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff); 697 698 p[0] = cpu_to_be64((u64)mhp->mpl[0]); 699 p[1] = cpu_to_be64((u64)mhp->mpl[1]); 700 701 *len16 = DIV_ROUND_UP(sizeof(*fr), 16); 702 return 0; 703 } 704 705 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe, 706 const struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16, 707 bool dsgl_supported) 708 { 709 struct fw_ri_immd *imdp; 710 __be64 *p; 711 int i; 712 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32); 713 int rem; 714 715 if (mhp->mpl_len > t4_max_fr_depth(&mhp->rhp->rdev, use_dsgl)) 716 return -EINVAL; 717 if (wr->mr->page_size > C4IW_MAX_PAGE_SIZE) 718 return -EINVAL; 719 720 wqe->fr.qpbinde_to_dcacpu = 0; 721 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12; 722 wqe->fr.addr_type = FW_RI_VA_BASED_TO; 723 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access); 724 wqe->fr.len_hi = cpu_to_be32(mhp->ibmr.length >> 32); 725 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length & 0xffffffff); 726 wqe->fr.stag = cpu_to_be32(wr->key); 727 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32); 728 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff); 729 730 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) { 731 struct fw_ri_dsgl *sglp; 732 733 for (i = 0; i < mhp->mpl_len; i++) 734 mhp->mpl[i] = 735 (__force u64)cpu_to_be64((u64)mhp->mpl[i]); 736 737 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1); 738 sglp->op = FW_RI_DATA_DSGL; 739 sglp->r1 = 0; 740 sglp->nsge = cpu_to_be16(1); 741 sglp->addr0 = cpu_to_be64(mhp->mpl_addr); 742 sglp->len0 = cpu_to_be32(pbllen); 743 744 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16); 745 } else { 746 imdp = (struct fw_ri_immd *)(&wqe->fr + 1); 747 imdp->op = FW_RI_DATA_IMMD; 748 imdp->r1 = 0; 749 imdp->r2 = 0; 750 imdp->immdlen = cpu_to_be32(pbllen); 751 p = (__be64 *)(imdp + 1); 752 rem = pbllen; 753 for (i = 0; i < mhp->mpl_len; i++) { 754 *p = cpu_to_be64((u64)mhp->mpl[i]); 755 rem -= sizeof(*p); 756 if (++p == (__be64 *)&sq->queue[sq->size]) 757 p = (__be64 *)sq->queue; 758 } 759 BUG_ON(rem < 0); 760 while (rem) { 761 *p = 0; 762 rem -= sizeof(*p); 763 if (++p == (__be64 *)&sq->queue[sq->size]) 764 p = (__be64 *)sq->queue; 765 } 766 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp) 767 + pbllen, 16); 768 } 769 770 return 0; 771 } 772 773 int c4iw_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 774 const struct ib_send_wr **bad_wr) 775 { 776 int err = 0; 777 u8 len16 = 0; 778 enum fw_wr_opcodes fw_opcode = 0; 779 enum fw_ri_wr_flags fw_flags; 780 struct c4iw_qp *qhp; 781 union t4_wr *wqe = NULL; 782 u32 num_wrs; 783 struct t4_swsqe *swsqe; 784 unsigned long flag; 785 u16 idx = 0; 786 struct c4iw_rdev *rdev; 787 788 qhp = to_c4iw_qp(ibqp); 789 rdev = &qhp->rhp->rdev; 790 spin_lock_irqsave(&qhp->lock, flag); 791 if (t4_wq_in_error(&qhp->wq)) { 792 spin_unlock_irqrestore(&qhp->lock, flag); 793 complete_sq_drain_wr(qhp, wr); 794 return err; 795 } 796 num_wrs = t4_sq_avail(&qhp->wq); 797 if (num_wrs == 0) { 798 spin_unlock_irqrestore(&qhp->lock, flag); 799 *bad_wr = wr; 800 return -ENOMEM; 801 } 802 while (wr) { 803 if (num_wrs == 0) { 804 err = -ENOMEM; 805 *bad_wr = wr; 806 break; 807 } 808 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue + 809 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE); 810 811 fw_flags = 0; 812 if (wr->send_flags & IB_SEND_SOLICITED) 813 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG; 814 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all) 815 fw_flags |= FW_RI_COMPLETION_FLAG; 816 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx]; 817 switch (wr->opcode) { 818 case IB_WR_SEND_WITH_INV: 819 case IB_WR_SEND: 820 if (wr->send_flags & IB_SEND_FENCE) 821 fw_flags |= FW_RI_READ_FENCE_FLAG; 822 fw_opcode = FW_RI_SEND_WR; 823 if (wr->opcode == IB_WR_SEND) 824 swsqe->opcode = FW_RI_SEND; 825 else 826 swsqe->opcode = FW_RI_SEND_WITH_INV; 827 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16); 828 break; 829 case IB_WR_RDMA_WRITE: 830 fw_opcode = FW_RI_RDMA_WRITE_WR; 831 swsqe->opcode = FW_RI_RDMA_WRITE; 832 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16); 833 break; 834 case IB_WR_RDMA_READ: 835 case IB_WR_RDMA_READ_WITH_INV: 836 fw_opcode = FW_RI_RDMA_READ_WR; 837 swsqe->opcode = FW_RI_READ_REQ; 838 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) { 839 c4iw_invalidate_mr(qhp->rhp, 840 wr->sg_list[0].lkey); 841 fw_flags = FW_RI_RDMA_READ_INVALIDATE; 842 } else { 843 fw_flags = 0; 844 } 845 err = build_rdma_read(wqe, wr, &len16); 846 if (err) 847 break; 848 swsqe->read_len = wr->sg_list[0].length; 849 if (!qhp->wq.sq.oldest_read) 850 qhp->wq.sq.oldest_read = swsqe; 851 break; 852 case IB_WR_REG_MR: { 853 struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr); 854 855 swsqe->opcode = FW_RI_FAST_REGISTER; 856 if (rdev->adap->params.fr_nsmr_tpte_wr_support && 857 !mhp->attr.state && mhp->mpl_len <= 2) { 858 fw_opcode = FW_RI_FR_NSMR_TPTE_WR; 859 err = build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr), 860 mhp, &len16); 861 } else { 862 fw_opcode = FW_RI_FR_NSMR_WR; 863 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr), 864 mhp, &len16, 865 rdev->adap->params.ulptx_memwrite_dsgl); 866 } 867 if (err) 868 break; 869 mhp->attr.state = 1; 870 break; 871 } 872 case IB_WR_LOCAL_INV: 873 if (wr->send_flags & IB_SEND_FENCE) 874 fw_flags |= FW_RI_LOCAL_FENCE_FLAG; 875 fw_opcode = FW_RI_INV_LSTAG_WR; 876 swsqe->opcode = FW_RI_LOCAL_INV; 877 err = build_inv_stag(wqe, wr, &len16); 878 c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey); 879 break; 880 default: 881 CTR2(KTR_IW_CXGBE, "%s post of type =%d TBD!", __func__, 882 wr->opcode); 883 err = -EINVAL; 884 } 885 if (err) { 886 *bad_wr = wr; 887 break; 888 } 889 swsqe->idx = qhp->wq.sq.pidx; 890 swsqe->complete = 0; 891 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) || 892 qhp->sq_sig_all; 893 swsqe->flushed = 0; 894 swsqe->wr_id = wr->wr_id; 895 896 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); 897 898 CTR5(KTR_IW_CXGBE, 899 "%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u", 900 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, 901 swsqe->opcode, swsqe->read_len); 902 wr = wr->next; 903 num_wrs--; 904 t4_sq_produce(&qhp->wq, len16); 905 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 906 } 907 908 t4_ring_sq_db(&qhp->wq, idx, wqe, rdev->adap->iwt.wc_en); 909 spin_unlock_irqrestore(&qhp->lock, flag); 910 return err; 911 } 912 913 int c4iw_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 914 const struct ib_recv_wr **bad_wr) 915 { 916 int err = 0; 917 struct c4iw_qp *qhp; 918 union t4_recv_wr *wqe = NULL; 919 u32 num_wrs; 920 u8 len16 = 0; 921 unsigned long flag; 922 u16 idx = 0; 923 924 qhp = to_c4iw_qp(ibqp); 925 spin_lock_irqsave(&qhp->lock, flag); 926 if (t4_wq_in_error(&qhp->wq)) { 927 spin_unlock_irqrestore(&qhp->lock, flag); 928 complete_rq_drain_wr(qhp, wr); 929 return err; 930 } 931 num_wrs = t4_rq_avail(&qhp->wq); 932 if (num_wrs == 0) { 933 spin_unlock_irqrestore(&qhp->lock, flag); 934 *bad_wr = wr; 935 return -ENOMEM; 936 } 937 while (wr) { 938 if (wr->num_sge > T4_MAX_RECV_SGE) { 939 err = -EINVAL; 940 *bad_wr = wr; 941 break; 942 } 943 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue + 944 qhp->wq.rq.wq_pidx * 945 T4_EQ_ENTRY_SIZE); 946 if (num_wrs) 947 err = build_rdma_recv(qhp, wqe, wr, &len16); 948 else 949 err = -ENOMEM; 950 if (err) { 951 *bad_wr = wr; 952 break; 953 } 954 955 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id; 956 957 wqe->recv.opcode = FW_RI_RECV_WR; 958 wqe->recv.r1 = 0; 959 wqe->recv.wrid = qhp->wq.rq.pidx; 960 wqe->recv.r2[0] = 0; 961 wqe->recv.r2[1] = 0; 962 wqe->recv.r2[2] = 0; 963 wqe->recv.len16 = len16; 964 CTR3(KTR_IW_CXGBE, "%s cookie 0x%llx pidx %u", __func__, 965 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx); 966 t4_rq_produce(&qhp->wq, len16); 967 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 968 wr = wr->next; 969 num_wrs--; 970 } 971 972 t4_ring_rq_db(&qhp->wq, idx, wqe, qhp->rhp->rdev.adap->iwt.wc_en); 973 spin_unlock_irqrestore(&qhp->lock, flag); 974 return err; 975 } 976 977 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type, 978 u8 *ecode) 979 { 980 int status; 981 int tagged; 982 int opcode; 983 int rqtype; 984 int send_inv; 985 986 if (!err_cqe) { 987 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 988 *ecode = 0; 989 return; 990 } 991 992 status = CQE_STATUS(err_cqe); 993 opcode = CQE_OPCODE(err_cqe); 994 rqtype = RQ_TYPE(err_cqe); 995 send_inv = (opcode == FW_RI_SEND_WITH_INV) || 996 (opcode == FW_RI_SEND_WITH_SE_INV); 997 tagged = (opcode == FW_RI_RDMA_WRITE) || 998 (rqtype && (opcode == FW_RI_READ_RESP)); 999 1000 switch (status) { 1001 case T4_ERR_STAG: 1002 if (send_inv) { 1003 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1004 *ecode = RDMAP_CANT_INV_STAG; 1005 } else { 1006 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1007 *ecode = RDMAP_INV_STAG; 1008 } 1009 break; 1010 case T4_ERR_PDID: 1011 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1012 if ((opcode == FW_RI_SEND_WITH_INV) || 1013 (opcode == FW_RI_SEND_WITH_SE_INV)) 1014 *ecode = RDMAP_CANT_INV_STAG; 1015 else 1016 *ecode = RDMAP_STAG_NOT_ASSOC; 1017 break; 1018 case T4_ERR_QPID: 1019 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1020 *ecode = RDMAP_STAG_NOT_ASSOC; 1021 break; 1022 case T4_ERR_ACCESS: 1023 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1024 *ecode = RDMAP_ACC_VIOL; 1025 break; 1026 case T4_ERR_WRAP: 1027 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1028 *ecode = RDMAP_TO_WRAP; 1029 break; 1030 case T4_ERR_BOUND: 1031 if (tagged) { 1032 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1033 *ecode = DDPT_BASE_BOUNDS; 1034 } else { 1035 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 1036 *ecode = RDMAP_BASE_BOUNDS; 1037 } 1038 break; 1039 case T4_ERR_INVALIDATE_SHARED_MR: 1040 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 1041 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1042 *ecode = RDMAP_CANT_INV_STAG; 1043 break; 1044 case T4_ERR_ECC: 1045 case T4_ERR_ECC_PSTAG: 1046 case T4_ERR_INTERNAL_ERR: 1047 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA; 1048 *ecode = 0; 1049 break; 1050 case T4_ERR_OUT_OF_RQE: 1051 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1052 *ecode = DDPU_INV_MSN_NOBUF; 1053 break; 1054 case T4_ERR_PBL_ADDR_BOUND: 1055 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1056 *ecode = DDPT_BASE_BOUNDS; 1057 break; 1058 case T4_ERR_CRC: 1059 *layer_type = LAYER_MPA|DDP_LLP; 1060 *ecode = MPA_CRC_ERR; 1061 break; 1062 case T4_ERR_MARKER: 1063 *layer_type = LAYER_MPA|DDP_LLP; 1064 *ecode = MPA_MARKER_ERR; 1065 break; 1066 case T4_ERR_PDU_LEN_ERR: 1067 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1068 *ecode = DDPU_MSG_TOOBIG; 1069 break; 1070 case T4_ERR_DDP_VERSION: 1071 if (tagged) { 1072 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 1073 *ecode = DDPT_INV_VERS; 1074 } else { 1075 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1076 *ecode = DDPU_INV_VERS; 1077 } 1078 break; 1079 case T4_ERR_RDMA_VERSION: 1080 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1081 *ecode = RDMAP_INV_VERS; 1082 break; 1083 case T4_ERR_OPCODE: 1084 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 1085 *ecode = RDMAP_INV_OPCODE; 1086 break; 1087 case T4_ERR_DDP_QUEUE_NUM: 1088 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1089 *ecode = DDPU_INV_QN; 1090 break; 1091 case T4_ERR_MSN: 1092 case T4_ERR_MSN_GAP: 1093 case T4_ERR_MSN_RANGE: 1094 case T4_ERR_IRD_OVERFLOW: 1095 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1096 *ecode = DDPU_INV_MSN_RANGE; 1097 break; 1098 case T4_ERR_TBIT: 1099 *layer_type = LAYER_DDP|DDP_LOCAL_CATA; 1100 *ecode = 0; 1101 break; 1102 case T4_ERR_MO: 1103 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 1104 *ecode = DDPU_INV_MO; 1105 break; 1106 default: 1107 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 1108 *ecode = 0; 1109 break; 1110 } 1111 } 1112 1113 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 1114 gfp_t gfp) 1115 { 1116 int ret; 1117 struct fw_ri_wr *wqe; 1118 struct terminate_message *term; 1119 struct wrqe *wr; 1120 struct socket *so = qhp->ep->com.so; 1121 struct inpcb *inp = sotoinpcb(so); 1122 struct tcpcb *tp = intotcpcb(inp); 1123 struct toepcb *toep = tp->t_toe; 1124 1125 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 1126 qhp->wq.sq.qid, qhp->ep->hwtid); 1127 1128 wr = alloc_wrqe(sizeof(*wqe), &toep->ofld_txq->wrq); 1129 if (wr == NULL) 1130 return; 1131 wqe = wrtod(wr); 1132 1133 memset(wqe, 0, sizeof *wqe); 1134 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR)); 1135 wqe->flowid_len16 = cpu_to_be32( 1136 V_FW_WR_FLOWID(qhp->ep->hwtid) | 1137 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1138 1139 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; 1140 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); 1141 term = (struct terminate_message *)wqe->u.terminate.termmsg; 1142 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) { 1143 term->layer_etype = qhp->attr.layer_etype; 1144 term->ecode = qhp->attr.ecode; 1145 } else 1146 build_term_codes(err_cqe, &term->layer_etype, &term->ecode); 1147 ret = creds(toep, inp, sizeof(*wqe)); 1148 if (ret) { 1149 free_wrqe(wr); 1150 return; 1151 } 1152 t4_wrq_tx(qhp->rhp->rdev.adap, wr); 1153 } 1154 1155 /* Assumes qhp lock is held. */ 1156 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, 1157 struct c4iw_cq *schp) 1158 { 1159 int count; 1160 int rq_flushed, sq_flushed; 1161 unsigned long flag; 1162 1163 CTR4(KTR_IW_CXGBE, "%s qhp %p rchp %p schp %p", __func__, qhp, rchp, 1164 schp); 1165 1166 /* locking hierarchy: cq lock first, then qp lock. */ 1167 spin_lock_irqsave(&rchp->lock, flag); 1168 spin_lock(&qhp->lock); 1169 1170 if (qhp->wq.flushed) { 1171 spin_unlock(&qhp->lock); 1172 spin_unlock_irqrestore(&rchp->lock, flag); 1173 return; 1174 } 1175 qhp->wq.flushed = 1; 1176 1177 c4iw_flush_hw_cq(rchp); 1178 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 1179 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 1180 spin_unlock(&qhp->lock); 1181 spin_unlock_irqrestore(&rchp->lock, flag); 1182 1183 /* locking hierarchy: cq lock first, then qp lock. */ 1184 spin_lock_irqsave(&schp->lock, flag); 1185 spin_lock(&qhp->lock); 1186 if (schp != rchp) 1187 c4iw_flush_hw_cq(schp); 1188 sq_flushed = c4iw_flush_sq(qhp); 1189 spin_unlock(&qhp->lock); 1190 spin_unlock_irqrestore(&schp->lock, flag); 1191 1192 if (schp == rchp) { 1193 if (t4_clear_cq_armed(&rchp->cq) && 1194 (rq_flushed || sq_flushed)) { 1195 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1196 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 1197 rchp->ibcq.cq_context); 1198 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1199 } 1200 } else { 1201 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) { 1202 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1203 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 1204 rchp->ibcq.cq_context); 1205 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1206 } 1207 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) { 1208 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1209 (*schp->ibcq.comp_handler)(&schp->ibcq, 1210 schp->ibcq.cq_context); 1211 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1212 } 1213 } 1214 } 1215 1216 static void flush_qp(struct c4iw_qp *qhp) 1217 { 1218 struct c4iw_cq *rchp, *schp; 1219 unsigned long flag; 1220 1221 rchp = to_c4iw_cq(qhp->ibqp.recv_cq); 1222 schp = to_c4iw_cq(qhp->ibqp.send_cq); 1223 1224 t4_set_wq_in_error(&qhp->wq); 1225 if (qhp->ibqp.uobject) { 1226 t4_set_cq_in_error(&rchp->cq); 1227 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1228 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 1229 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 1230 if (schp != rchp) { 1231 t4_set_cq_in_error(&schp->cq); 1232 spin_lock_irqsave(&schp->comp_handler_lock, flag); 1233 (*schp->ibcq.comp_handler)(&schp->ibcq, 1234 schp->ibcq.cq_context); 1235 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 1236 } 1237 return; 1238 } 1239 __flush_qp(qhp, rchp, schp); 1240 } 1241 1242 static int 1243 rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, struct c4iw_ep *ep) 1244 { 1245 struct c4iw_rdev *rdev = &rhp->rdev; 1246 struct adapter *sc = rdev->adap; 1247 struct fw_ri_wr *wqe; 1248 int ret; 1249 struct wrqe *wr; 1250 struct socket *so = ep->com.so; 1251 struct inpcb *inp = sotoinpcb(so); 1252 struct tcpcb *tp = intotcpcb(inp); 1253 struct toepcb *toep = tp->t_toe; 1254 1255 KASSERT(rhp == qhp->rhp && ep == qhp->ep, ("%s: EDOOFUS", __func__)); 1256 1257 CTR5(KTR_IW_CXGBE, "%s qhp %p qid 0x%x ep %p tid %u", __func__, qhp, 1258 qhp->wq.sq.qid, ep, ep->hwtid); 1259 1260 wr = alloc_wrqe(sizeof(*wqe), &toep->ofld_txq->wrq); 1261 if (wr == NULL) 1262 return (0); 1263 wqe = wrtod(wr); 1264 1265 memset(wqe, 0, sizeof *wqe); 1266 1267 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR) | F_FW_WR_COMPL); 1268 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1269 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1270 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1271 wqe->u.fini.type = FW_RI_TYPE_FINI; 1272 1273 c4iw_init_wr_wait(&ep->com.wr_wait); 1274 1275 ret = creds(toep, inp, sizeof(*wqe)); 1276 if (ret) { 1277 free_wrqe(wr); 1278 return ret; 1279 } 1280 t4_wrq_tx(sc, wr); 1281 1282 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1283 qhp->wq.sq.qid, ep->com.so, __func__); 1284 return ret; 1285 } 1286 1287 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) 1288 { 1289 CTR2(KTR_IW_CXGBE, "%s p2p_type = %d", __func__, p2p_type); 1290 memset(&init->u, 0, sizeof init->u); 1291 switch (p2p_type) { 1292 case FW_RI_INIT_P2PTYPE_RDMA_WRITE: 1293 init->u.write.opcode = FW_RI_RDMA_WRITE_WR; 1294 init->u.write.stag_sink = cpu_to_be32(1); 1295 init->u.write.to_sink = cpu_to_be64(1); 1296 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD; 1297 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write + 1298 sizeof(struct fw_ri_immd), 1299 16); 1300 break; 1301 case FW_RI_INIT_P2PTYPE_READ_REQ: 1302 init->u.write.opcode = FW_RI_RDMA_READ_WR; 1303 init->u.read.stag_src = cpu_to_be32(1); 1304 init->u.read.to_src_lo = cpu_to_be32(1); 1305 init->u.read.stag_sink = cpu_to_be32(1); 1306 init->u.read.to_sink_lo = cpu_to_be32(1); 1307 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16); 1308 break; 1309 } 1310 } 1311 1312 static int 1313 creds(struct toepcb *toep, struct inpcb *inp, size_t wrsize) 1314 { 1315 struct ofld_tx_sdesc *txsd; 1316 1317 CTR3(KTR_IW_CXGBE, "%s:creB %p %u", __func__, toep , wrsize); 1318 INP_WLOCK(inp); 1319 if ((inp->inp_flags & INP_DROPPED) != 0) { 1320 INP_WUNLOCK(inp); 1321 return (EINVAL); 1322 } 1323 txsd = &toep->txsd[toep->txsd_pidx]; 1324 txsd->tx_credits = howmany(wrsize, 16); 1325 txsd->plen = 0; 1326 KASSERT(toep->tx_credits >= txsd->tx_credits && toep->txsd_avail > 0, 1327 ("%s: not enough credits (%d)", __func__, toep->tx_credits)); 1328 toep->tx_credits -= txsd->tx_credits; 1329 if (__predict_false(++toep->txsd_pidx == toep->txsd_total)) 1330 toep->txsd_pidx = 0; 1331 toep->txsd_avail--; 1332 INP_WUNLOCK(inp); 1333 CTR5(KTR_IW_CXGBE, "%s:creE %p %u %u %u", __func__, toep , 1334 txsd->tx_credits, toep->tx_credits, toep->txsd_pidx); 1335 return (0); 1336 } 1337 1338 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) 1339 { 1340 struct fw_ri_wr *wqe; 1341 int ret; 1342 struct wrqe *wr; 1343 struct c4iw_ep *ep = qhp->ep; 1344 struct c4iw_rdev *rdev = &qhp->rhp->rdev; 1345 struct adapter *sc = rdev->adap; 1346 struct socket *so = ep->com.so; 1347 struct inpcb *inp = sotoinpcb(so); 1348 struct tcpcb *tp = intotcpcb(inp); 1349 struct toepcb *toep = tp->t_toe; 1350 1351 CTR5(KTR_IW_CXGBE, "%s qhp %p qid 0x%x ep %p tid %u", __func__, qhp, 1352 qhp->wq.sq.qid, ep, ep->hwtid); 1353 1354 wr = alloc_wrqe(sizeof(*wqe), &toep->ofld_txq->wrq); 1355 if (wr == NULL) 1356 return (0); 1357 wqe = wrtod(wr); 1358 ret = alloc_ird(rhp, qhp->attr.max_ird); 1359 if (ret) { 1360 qhp->attr.max_ird = 0; 1361 free_wrqe(wr); 1362 return ret; 1363 } 1364 1365 memset(wqe, 0, sizeof *wqe); 1366 1367 wqe->op_compl = cpu_to_be32( 1368 V_FW_WR_OP(FW_RI_WR) | 1369 F_FW_WR_COMPL); 1370 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1371 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1372 1373 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1374 1375 wqe->u.init.type = FW_RI_TYPE_INIT; 1376 wqe->u.init.mpareqbit_p2ptype = 1377 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) | 1378 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type); 1379 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE; 1380 if (qhp->attr.mpa_attr.recv_marker_enabled) 1381 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE; 1382 if (qhp->attr.mpa_attr.xmit_marker_enabled) 1383 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE; 1384 if (qhp->attr.mpa_attr.crc_enabled) 1385 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE; 1386 1387 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE | 1388 FW_RI_QP_RDMA_WRITE_ENABLE | 1389 FW_RI_QP_BIND_ENABLE; 1390 if (!qhp->ibqp.uobject) 1391 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE | 1392 FW_RI_QP_STAG0_ENABLE; 1393 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq)); 1394 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd); 1395 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid); 1396 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid); 1397 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid); 1398 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq); 1399 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq); 1400 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord); 1401 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird); 1402 wqe->u.init.iss = cpu_to_be32(ep->snd_seq); 1403 wqe->u.init.irs = cpu_to_be32(ep->rcv_seq); 1404 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size); 1405 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr - 1406 sc->vres.rq.start); 1407 if (qhp->attr.mpa_attr.initiator) 1408 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1409 1410 c4iw_init_wr_wait(&ep->com.wr_wait); 1411 1412 ret = creds(toep, inp, sizeof(*wqe)); 1413 if (ret) { 1414 free_wrqe(wr); 1415 free_ird(rhp, qhp->attr.max_ird); 1416 return ret; 1417 } 1418 t4_wrq_tx(sc, wr); 1419 1420 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1421 qhp->wq.sq.qid, ep->com.so, __func__); 1422 1423 toep->params.ulp_mode = ULP_MODE_RDMA; 1424 free_ird(rhp, qhp->attr.max_ird); 1425 1426 return ret; 1427 } 1428 1429 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1430 enum c4iw_qp_attr_mask mask, 1431 struct c4iw_qp_attributes *attrs, 1432 int internal) 1433 { 1434 int ret = 0; 1435 struct c4iw_qp_attributes newattr = qhp->attr; 1436 int disconnect = 0; 1437 int terminate = 0; 1438 int abort = 0; 1439 int free = 0; 1440 struct c4iw_ep *ep = NULL; 1441 1442 CTR5(KTR_IW_CXGBE, "%s qhp %p sqid 0x%x rqid 0x%x ep %p", __func__, qhp, 1443 qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep); 1444 CTR3(KTR_IW_CXGBE, "%s state %d -> %d", __func__, qhp->attr.state, 1445 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1446 1447 mutex_lock(&qhp->mutex); 1448 1449 /* Process attr changes if in IDLE */ 1450 if (mask & C4IW_QP_ATTR_VALID_MODIFY) { 1451 if (qhp->attr.state != C4IW_QP_STATE_IDLE) { 1452 ret = -EIO; 1453 goto out; 1454 } 1455 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) 1456 newattr.enable_rdma_read = attrs->enable_rdma_read; 1457 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) 1458 newattr.enable_rdma_write = attrs->enable_rdma_write; 1459 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) 1460 newattr.enable_bind = attrs->enable_bind; 1461 if (mask & C4IW_QP_ATTR_MAX_ORD) { 1462 if (attrs->max_ord > c4iw_max_read_depth) { 1463 ret = -EINVAL; 1464 goto out; 1465 } 1466 newattr.max_ord = attrs->max_ord; 1467 } 1468 if (mask & C4IW_QP_ATTR_MAX_IRD) { 1469 if (attrs->max_ird > cur_max_read_depth(rhp)) { 1470 ret = -EINVAL; 1471 goto out; 1472 } 1473 newattr.max_ird = attrs->max_ird; 1474 } 1475 qhp->attr = newattr; 1476 } 1477 1478 if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) 1479 goto out; 1480 if (qhp->attr.state == attrs->next_state) 1481 goto out; 1482 1483 /* Return EINPROGRESS if QP is already in transition state. 1484 * Eg: CLOSING->IDLE transition or *->ERROR transition. 1485 * This can happen while connection is switching(due to rdma_fini) 1486 * from iWARP/RDDP to TOE mode and any inflight RDMA RX data will 1487 * reach TOE driver -> TCP stack -> iWARP driver. In this way 1488 * iWARP driver keep receiving inflight RDMA RX data until socket 1489 * is closed or aborted. And if iWARP CM is in FPDU sate, then 1490 * it tries to put QP in TERM state and disconnects endpoint. 1491 * But as QP is already in transition state, this event is ignored. 1492 */ 1493 if ((qhp->attr.state >= C4IW_QP_STATE_ERROR) && 1494 (attrs->next_state == C4IW_QP_STATE_TERMINATE)) { 1495 ret = -EINPROGRESS; 1496 goto out; 1497 } 1498 1499 switch (qhp->attr.state) { 1500 case C4IW_QP_STATE_IDLE: 1501 switch (attrs->next_state) { 1502 case C4IW_QP_STATE_RTS: 1503 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { 1504 ret = -EINVAL; 1505 goto out; 1506 } 1507 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { 1508 ret = -EINVAL; 1509 goto out; 1510 } 1511 qhp->attr.mpa_attr = attrs->mpa_attr; 1512 qhp->attr.llp_stream_handle = attrs->llp_stream_handle; 1513 qhp->ep = qhp->attr.llp_stream_handle; 1514 set_state(qhp, C4IW_QP_STATE_RTS); 1515 1516 /* 1517 * Ref the endpoint here and deref when we 1518 * disassociate the endpoint from the QP. This 1519 * happens in CLOSING->IDLE transition or *->ERROR 1520 * transition. 1521 */ 1522 c4iw_get_ep(&qhp->ep->com); 1523 ret = rdma_init(rhp, qhp); 1524 if (ret) 1525 goto err; 1526 break; 1527 case C4IW_QP_STATE_ERROR: 1528 set_state(qhp, C4IW_QP_STATE_ERROR); 1529 flush_qp(qhp); 1530 break; 1531 default: 1532 ret = -EINVAL; 1533 goto out; 1534 } 1535 break; 1536 case C4IW_QP_STATE_RTS: 1537 switch (attrs->next_state) { 1538 case C4IW_QP_STATE_CLOSING: 1539 BUG_ON(kref_read(&qhp->ep->com.kref) < 2); 1540 t4_set_wq_in_error(&qhp->wq); 1541 set_state(qhp, C4IW_QP_STATE_CLOSING); 1542 ep = qhp->ep; 1543 if (!internal) { 1544 abort = 0; 1545 disconnect = 1; 1546 c4iw_get_ep(&qhp->ep->com); 1547 } 1548 ret = rdma_fini(rhp, qhp, ep); 1549 if (ret) 1550 goto err; 1551 break; 1552 case C4IW_QP_STATE_TERMINATE: 1553 t4_set_wq_in_error(&qhp->wq); 1554 set_state(qhp, C4IW_QP_STATE_TERMINATE); 1555 qhp->attr.layer_etype = attrs->layer_etype; 1556 qhp->attr.ecode = attrs->ecode; 1557 ep = qhp->ep; 1558 if (!internal) { 1559 c4iw_get_ep(&qhp->ep->com); 1560 terminate = 1; 1561 disconnect = 1; 1562 } else { 1563 terminate = qhp->attr.send_term; 1564 ret = rdma_fini(rhp, qhp, ep); 1565 if (ret) 1566 goto err; 1567 } 1568 break; 1569 case C4IW_QP_STATE_ERROR: 1570 t4_set_wq_in_error(&qhp->wq); 1571 set_state(qhp, C4IW_QP_STATE_ERROR); 1572 if (!internal) { 1573 abort = 1; 1574 disconnect = 1; 1575 ep = qhp->ep; 1576 c4iw_get_ep(&qhp->ep->com); 1577 } 1578 goto err; 1579 break; 1580 default: 1581 ret = -EINVAL; 1582 goto out; 1583 } 1584 break; 1585 case C4IW_QP_STATE_CLOSING: 1586 1587 /* 1588 * Allow kernel users to move to ERROR for qp draining. 1589 */ 1590 if (!internal && (qhp->ibqp.uobject || attrs->next_state != 1591 C4IW_QP_STATE_ERROR)) { 1592 ret = -EINVAL; 1593 goto out; 1594 } 1595 switch (attrs->next_state) { 1596 case C4IW_QP_STATE_IDLE: 1597 flush_qp(qhp); 1598 set_state(qhp, C4IW_QP_STATE_IDLE); 1599 qhp->attr.llp_stream_handle = NULL; 1600 c4iw_put_ep(&qhp->ep->com); 1601 qhp->ep = NULL; 1602 wake_up(&qhp->wait); 1603 break; 1604 case C4IW_QP_STATE_ERROR: 1605 goto err; 1606 default: 1607 ret = -EINVAL; 1608 goto err; 1609 } 1610 break; 1611 case C4IW_QP_STATE_ERROR: 1612 if (attrs->next_state != C4IW_QP_STATE_IDLE) { 1613 ret = -EINVAL; 1614 goto out; 1615 } 1616 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) { 1617 ret = -EINVAL; 1618 goto out; 1619 } 1620 set_state(qhp, C4IW_QP_STATE_IDLE); 1621 break; 1622 case C4IW_QP_STATE_TERMINATE: 1623 if (!internal) { 1624 ret = -EINVAL; 1625 goto out; 1626 } 1627 goto err; 1628 break; 1629 default: 1630 printf("%s in a bad state %d\n", 1631 __func__, qhp->attr.state); 1632 ret = -EINVAL; 1633 goto err; 1634 break; 1635 } 1636 goto out; 1637 err: 1638 CTR3(KTR_IW_CXGBE, "%s disassociating ep %p qpid 0x%x", __func__, 1639 qhp->ep, qhp->wq.sq.qid); 1640 1641 /* disassociate the LLP connection */ 1642 qhp->attr.llp_stream_handle = NULL; 1643 if (!ep) 1644 ep = qhp->ep; 1645 qhp->ep = NULL; 1646 set_state(qhp, C4IW_QP_STATE_ERROR); 1647 free = 1; 1648 abort = 1; 1649 BUG_ON(!ep); 1650 flush_qp(qhp); 1651 wake_up(&qhp->wait); 1652 out: 1653 mutex_unlock(&qhp->mutex); 1654 1655 if (terminate) 1656 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); 1657 1658 /* 1659 * If disconnect is 1, then we need to initiate a disconnect 1660 * on the EP. This can be a normal close (RTS->CLOSING) or 1661 * an abnormal close (RTS/CLOSING->ERROR). 1662 */ 1663 if (disconnect) { 1664 __c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC : 1665 GFP_KERNEL); 1666 c4iw_put_ep(&ep->com); 1667 } 1668 1669 /* 1670 * If free is 1, then we've disassociated the EP from the QP 1671 * and we need to dereference the EP. 1672 */ 1673 if (free) 1674 c4iw_put_ep(&ep->com); 1675 CTR2(KTR_IW_CXGBE, "%s exit state %d", __func__, qhp->attr.state); 1676 return ret; 1677 } 1678 1679 int c4iw_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 1680 { 1681 struct c4iw_dev *rhp; 1682 struct c4iw_qp *qhp; 1683 struct c4iw_qp_attributes attrs; 1684 1685 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ib_qp); 1686 qhp = to_c4iw_qp(ib_qp); 1687 rhp = qhp->rhp; 1688 1689 attrs.next_state = C4IW_QP_STATE_ERROR; 1690 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE) 1691 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1692 else 1693 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0); 1694 wait_event(qhp->wait, !qhp->ep); 1695 1696 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1697 1698 free_ird(rhp, qhp->attr.max_ird); 1699 c4iw_qp_rem_ref(ib_qp); 1700 1701 CTR3(KTR_IW_CXGBE, "%s ib_qp %p qpid 0x%0x", __func__, ib_qp, 1702 qhp->wq.sq.qid); 1703 return 0; 1704 } 1705 1706 struct ib_qp * 1707 c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, 1708 struct ib_udata *udata) 1709 { 1710 struct c4iw_dev *rhp; 1711 struct c4iw_qp *qhp; 1712 struct c4iw_pd *php; 1713 struct c4iw_cq *schp; 1714 struct c4iw_cq *rchp; 1715 struct c4iw_create_qp_resp uresp; 1716 unsigned int sqsize, rqsize; 1717 struct c4iw_ucontext *ucontext; 1718 int ret; 1719 struct c4iw_mm_entry *sq_key_mm = NULL, *rq_key_mm = NULL; 1720 struct c4iw_mm_entry *sq_db_key_mm = NULL, *rq_db_key_mm = NULL; 1721 1722 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd); 1723 1724 if (attrs->qp_type != IB_QPT_RC) 1725 return ERR_PTR(-EINVAL); 1726 1727 php = to_c4iw_pd(pd); 1728 rhp = php->rhp; 1729 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid); 1730 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid); 1731 if (!schp || !rchp) 1732 return ERR_PTR(-EINVAL); 1733 1734 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) 1735 return ERR_PTR(-EINVAL); 1736 1737 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size) 1738 return ERR_PTR(-E2BIG); 1739 rqsize = attrs->cap.max_recv_wr + 1; 1740 if (rqsize < 8) 1741 rqsize = 8; 1742 1743 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size) 1744 return ERR_PTR(-E2BIG); 1745 sqsize = attrs->cap.max_send_wr + 1; 1746 if (sqsize < 8) 1747 sqsize = 8; 1748 1749 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; 1750 1751 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); 1752 if (!qhp) 1753 return ERR_PTR(-ENOMEM); 1754 qhp->wq.sq.size = sqsize; 1755 qhp->wq.sq.memsize = 1756 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) * 1757 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64); 1758 qhp->wq.sq.flush_cidx = -1; 1759 qhp->wq.rq.size = rqsize; 1760 qhp->wq.rq.memsize = 1761 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) * 1762 sizeof(*qhp->wq.rq.queue); 1763 1764 if (ucontext) { 1765 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); 1766 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE); 1767 } 1768 1769 CTR5(KTR_IW_CXGBE, "%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu", 1770 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize); 1771 1772 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, 1773 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1774 if (ret) 1775 goto err1; 1776 1777 attrs->cap.max_recv_wr = rqsize - 1; 1778 attrs->cap.max_send_wr = sqsize - 1; 1779 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE; 1780 1781 qhp->rhp = rhp; 1782 qhp->attr.pd = php->pdid; 1783 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid; 1784 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid; 1785 qhp->attr.sq_num_entries = attrs->cap.max_send_wr; 1786 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr; 1787 qhp->attr.sq_max_sges = attrs->cap.max_send_sge; 1788 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge; 1789 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge; 1790 qhp->attr.state = C4IW_QP_STATE_IDLE; 1791 qhp->attr.next_state = C4IW_QP_STATE_IDLE; 1792 qhp->attr.enable_rdma_read = 1; 1793 qhp->attr.enable_rdma_write = 1; 1794 qhp->attr.enable_bind = 1; 1795 qhp->attr.max_ord = 0; 1796 qhp->attr.max_ird = 0; 1797 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR; 1798 spin_lock_init(&qhp->lock); 1799 mutex_init(&qhp->mutex); 1800 init_waitqueue_head(&qhp->wait); 1801 kref_init(&qhp->kref); 1802 INIT_WORK(&qhp->free_work, free_qp_work); 1803 1804 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); 1805 if (ret) 1806 goto err2; 1807 1808 if (udata) { 1809 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL); 1810 if (!sq_key_mm) { 1811 ret = -ENOMEM; 1812 goto err3; 1813 } 1814 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL); 1815 if (!rq_key_mm) { 1816 ret = -ENOMEM; 1817 goto err4; 1818 } 1819 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL); 1820 if (!sq_db_key_mm) { 1821 ret = -ENOMEM; 1822 goto err5; 1823 } 1824 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL); 1825 if (!rq_db_key_mm) { 1826 ret = -ENOMEM; 1827 goto err6; 1828 } 1829 uresp.flags = 0; 1830 uresp.qid_mask = rhp->rdev.qpmask; 1831 uresp.sqid = qhp->wq.sq.qid; 1832 uresp.sq_size = qhp->wq.sq.size; 1833 uresp.sq_memsize = qhp->wq.sq.memsize; 1834 uresp.rqid = qhp->wq.rq.qid; 1835 uresp.rq_size = qhp->wq.rq.size; 1836 uresp.rq_memsize = qhp->wq.rq.memsize; 1837 spin_lock(&ucontext->mmap_lock); 1838 uresp.ma_sync_key = 0; 1839 uresp.sq_key = ucontext->key; 1840 ucontext->key += PAGE_SIZE; 1841 uresp.rq_key = ucontext->key; 1842 ucontext->key += PAGE_SIZE; 1843 uresp.sq_db_gts_key = ucontext->key; 1844 ucontext->key += PAGE_SIZE; 1845 uresp.rq_db_gts_key = ucontext->key; 1846 ucontext->key += PAGE_SIZE; 1847 spin_unlock(&ucontext->mmap_lock); 1848 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1849 if (ret) 1850 goto err7; 1851 sq_key_mm->key = uresp.sq_key; 1852 sq_key_mm->addr = qhp->wq.sq.phys_addr; 1853 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1854 CTR4(KTR_IW_CXGBE, "%s sq_key_mm %x, %x, %d", __func__, 1855 sq_key_mm->key, sq_key_mm->addr, 1856 sq_key_mm->len); 1857 insert_mmap(ucontext, sq_key_mm); 1858 rq_key_mm->key = uresp.rq_key; 1859 rq_key_mm->addr = qhp->wq.rq.phys_addr; 1860 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize); 1861 CTR4(KTR_IW_CXGBE, "%s rq_key_mm %x, %x, %d", __func__, 1862 rq_key_mm->key, rq_key_mm->addr, 1863 rq_key_mm->len); 1864 insert_mmap(ucontext, rq_key_mm); 1865 sq_db_key_mm->key = uresp.sq_db_gts_key; 1866 sq_db_key_mm->addr = (u64)qhp->wq.sq.bar2_pa; 1867 sq_db_key_mm->len = PAGE_SIZE; 1868 CTR4(KTR_IW_CXGBE, "%s sq_db_key_mm %x, %x, %d", __func__, 1869 sq_db_key_mm->key, sq_db_key_mm->addr, 1870 sq_db_key_mm->len); 1871 insert_mmap(ucontext, sq_db_key_mm); 1872 rq_db_key_mm->key = uresp.rq_db_gts_key; 1873 rq_db_key_mm->addr = (u64)qhp->wq.rq.bar2_pa; 1874 rq_db_key_mm->len = PAGE_SIZE; 1875 CTR4(KTR_IW_CXGBE, "%s rq_db_key_mm %x, %x, %d", __func__, 1876 rq_db_key_mm->key, rq_db_key_mm->addr, 1877 rq_db_key_mm->len); 1878 insert_mmap(ucontext, rq_db_key_mm); 1879 1880 qhp->ucontext = ucontext; 1881 } 1882 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1883 init_timer(&(qhp->timer)); 1884 1885 CTR5(KTR_IW_CXGBE, "%s sq id %u size %u memsize %zu num_entries %u", 1886 __func__, qhp->wq.sq.qid, 1887 qhp->wq.sq.size, qhp->wq.sq.memsize, attrs->cap.max_send_wr); 1888 CTR5(KTR_IW_CXGBE, "%s rq id %u size %u memsize %zu num_entries %u", 1889 __func__, qhp->wq.rq.qid, 1890 qhp->wq.rq.size, qhp->wq.rq.memsize, attrs->cap.max_recv_wr); 1891 return &qhp->ibqp; 1892 err7: 1893 kfree(rq_db_key_mm); 1894 err6: 1895 kfree(sq_db_key_mm); 1896 err5: 1897 kfree(rq_key_mm); 1898 err4: 1899 kfree(sq_key_mm); 1900 err3: 1901 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1902 err2: 1903 destroy_qp(&rhp->rdev, &qhp->wq, 1904 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1905 err1: 1906 kfree(qhp); 1907 return ERR_PTR(ret); 1908 } 1909 1910 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1911 int attr_mask, struct ib_udata *udata) 1912 { 1913 struct c4iw_dev *rhp; 1914 struct c4iw_qp *qhp; 1915 enum c4iw_qp_attr_mask mask = 0; 1916 struct c4iw_qp_attributes attrs; 1917 1918 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ibqp); 1919 1920 /* iwarp does not support the RTR state */ 1921 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) 1922 attr_mask &= ~IB_QP_STATE; 1923 1924 /* Make sure we still have something left to do */ 1925 if (!attr_mask) 1926 return 0; 1927 1928 memset(&attrs, 0, sizeof attrs); 1929 qhp = to_c4iw_qp(ibqp); 1930 rhp = qhp->rhp; 1931 1932 attrs.next_state = c4iw_convert_state(attr->qp_state); 1933 attrs.enable_rdma_read = (attr->qp_access_flags & 1934 IB_ACCESS_REMOTE_READ) ? 1 : 0; 1935 attrs.enable_rdma_write = (attr->qp_access_flags & 1936 IB_ACCESS_REMOTE_WRITE) ? 1 : 0; 1937 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0; 1938 1939 1940 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; 1941 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? 1942 (C4IW_QP_ATTR_ENABLE_RDMA_READ | 1943 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 1944 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0; 1945 1946 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); 1947 } 1948 1949 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) 1950 { 1951 CTR3(KTR_IW_CXGBE, "%s ib_dev %p qpn 0x%x", __func__, dev, qpn); 1952 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); 1953 } 1954 1955 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1956 int attr_mask, struct ib_qp_init_attr *init_attr) 1957 { 1958 struct c4iw_qp *qhp = to_c4iw_qp(ibqp); 1959 1960 memset(attr, 0, sizeof *attr); 1961 memset(init_attr, 0, sizeof *init_attr); 1962 attr->qp_state = to_ib_qp_state(qhp->attr.state); 1963 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries; 1964 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries; 1965 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges; 1966 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges; 1967 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE; 1968 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0; 1969 return 0; 1970 } 1971 #endif
Cache object: e8610160ebe22c30aad5bca5f2e35d9c
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