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sys/dev/cxgbe/t4_main.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_kern_tls.h" 37 #include "opt_ratelimit.h" 38 #include "opt_rss.h" 39 40 #include <sys/param.h> 41 #include <sys/conf.h> 42 #include <sys/priv.h> 43 #include <sys/kernel.h> 44 #include <sys/bus.h> 45 #include <sys/eventhandler.h> 46 #include <sys/module.h> 47 #include <sys/malloc.h> 48 #include <sys/queue.h> 49 #include <sys/taskqueue.h> 50 #include <sys/pciio.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pci_private.h> 54 #include <sys/firmware.h> 55 #include <sys/sbuf.h> 56 #include <sys/smp.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/sysctl.h> 60 #include <net/ethernet.h> 61 #include <net/if.h> 62 #include <net/if_types.h> 63 #include <net/if_dl.h> 64 #include <net/if_vlan_var.h> 65 #ifdef RSS 66 #include <net/rss_config.h> 67 #endif 68 #include <netinet/in.h> 69 #include <netinet/ip.h> 70 #ifdef KERN_TLS 71 #include <netinet/tcp_seq.h> 72 #endif 73 #if defined(__i386__) || defined(__amd64__) 74 #include <machine/md_var.h> 75 #include <machine/cputypes.h> 76 #include <vm/vm.h> 77 #include <vm/pmap.h> 78 #endif 79 #ifdef DDB 80 #include <ddb/ddb.h> 81 #include <ddb/db_lex.h> 82 #endif 83 84 #include "common/common.h" 85 #include "common/t4_msg.h" 86 #include "common/t4_regs.h" 87 #include "common/t4_regs_values.h" 88 #include "cudbg/cudbg.h" 89 #include "t4_clip.h" 90 #include "t4_ioctl.h" 91 #include "t4_l2t.h" 92 #include "t4_mp_ring.h" 93 #include "t4_if.h" 94 #include "t4_smt.h" 95 96 /* T4 bus driver interface */ 97 static int t4_probe(device_t); 98 static int t4_attach(device_t); 99 static int t4_detach(device_t); 100 static int t4_child_location(device_t, device_t, struct sbuf *); 101 static int t4_ready(device_t); 102 static int t4_read_port_device(device_t, int, device_t *); 103 static int t4_suspend(device_t); 104 static int t4_resume(device_t); 105 static int t4_reset_prepare(device_t, device_t); 106 static int t4_reset_post(device_t, device_t); 107 static device_method_t t4_methods[] = { 108 DEVMETHOD(device_probe, t4_probe), 109 DEVMETHOD(device_attach, t4_attach), 110 DEVMETHOD(device_detach, t4_detach), 111 DEVMETHOD(device_suspend, t4_suspend), 112 DEVMETHOD(device_resume, t4_resume), 113 114 DEVMETHOD(bus_child_location, t4_child_location), 115 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 116 DEVMETHOD(bus_reset_post, t4_reset_post), 117 118 DEVMETHOD(t4_is_main_ready, t4_ready), 119 DEVMETHOD(t4_read_port_device, t4_read_port_device), 120 121 DEVMETHOD_END 122 }; 123 static driver_t t4_driver = { 124 "t4nex", 125 t4_methods, 126 sizeof(struct adapter) 127 }; 128 129 130 /* T4 port (cxgbe) interface */ 131 static int cxgbe_probe(device_t); 132 static int cxgbe_attach(device_t); 133 static int cxgbe_detach(device_t); 134 device_method_t cxgbe_methods[] = { 135 DEVMETHOD(device_probe, cxgbe_probe), 136 DEVMETHOD(device_attach, cxgbe_attach), 137 DEVMETHOD(device_detach, cxgbe_detach), 138 { 0, 0 } 139 }; 140 static driver_t cxgbe_driver = { 141 "cxgbe", 142 cxgbe_methods, 143 sizeof(struct port_info) 144 }; 145 146 /* T4 VI (vcxgbe) interface */ 147 static int vcxgbe_probe(device_t); 148 static int vcxgbe_attach(device_t); 149 static int vcxgbe_detach(device_t); 150 static device_method_t vcxgbe_methods[] = { 151 DEVMETHOD(device_probe, vcxgbe_probe), 152 DEVMETHOD(device_attach, vcxgbe_attach), 153 DEVMETHOD(device_detach, vcxgbe_detach), 154 { 0, 0 } 155 }; 156 static driver_t vcxgbe_driver = { 157 "vcxgbe", 158 vcxgbe_methods, 159 sizeof(struct vi_info) 160 }; 161 162 static d_ioctl_t t4_ioctl; 163 164 static struct cdevsw t4_cdevsw = { 165 .d_version = D_VERSION, 166 .d_ioctl = t4_ioctl, 167 .d_name = "t4nex", 168 }; 169 170 /* T5 bus driver interface */ 171 static int t5_probe(device_t); 172 static device_method_t t5_methods[] = { 173 DEVMETHOD(device_probe, t5_probe), 174 DEVMETHOD(device_attach, t4_attach), 175 DEVMETHOD(device_detach, t4_detach), 176 DEVMETHOD(device_suspend, t4_suspend), 177 DEVMETHOD(device_resume, t4_resume), 178 179 DEVMETHOD(bus_child_location, t4_child_location), 180 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 181 DEVMETHOD(bus_reset_post, t4_reset_post), 182 183 DEVMETHOD(t4_is_main_ready, t4_ready), 184 DEVMETHOD(t4_read_port_device, t4_read_port_device), 185 186 DEVMETHOD_END 187 }; 188 static driver_t t5_driver = { 189 "t5nex", 190 t5_methods, 191 sizeof(struct adapter) 192 }; 193 194 195 /* T5 port (cxl) interface */ 196 static driver_t cxl_driver = { 197 "cxl", 198 cxgbe_methods, 199 sizeof(struct port_info) 200 }; 201 202 /* T5 VI (vcxl) interface */ 203 static driver_t vcxl_driver = { 204 "vcxl", 205 vcxgbe_methods, 206 sizeof(struct vi_info) 207 }; 208 209 /* T6 bus driver interface */ 210 static int t6_probe(device_t); 211 static device_method_t t6_methods[] = { 212 DEVMETHOD(device_probe, t6_probe), 213 DEVMETHOD(device_attach, t4_attach), 214 DEVMETHOD(device_detach, t4_detach), 215 DEVMETHOD(device_suspend, t4_suspend), 216 DEVMETHOD(device_resume, t4_resume), 217 218 DEVMETHOD(bus_child_location, t4_child_location), 219 DEVMETHOD(bus_reset_prepare, t4_reset_prepare), 220 DEVMETHOD(bus_reset_post, t4_reset_post), 221 222 DEVMETHOD(t4_is_main_ready, t4_ready), 223 DEVMETHOD(t4_read_port_device, t4_read_port_device), 224 225 DEVMETHOD_END 226 }; 227 static driver_t t6_driver = { 228 "t6nex", 229 t6_methods, 230 sizeof(struct adapter) 231 }; 232 233 234 /* T6 port (cc) interface */ 235 static driver_t cc_driver = { 236 "cc", 237 cxgbe_methods, 238 sizeof(struct port_info) 239 }; 240 241 /* T6 VI (vcc) interface */ 242 static driver_t vcc_driver = { 243 "vcc", 244 vcxgbe_methods, 245 sizeof(struct vi_info) 246 }; 247 248 /* ifnet interface */ 249 static void cxgbe_init(void *); 250 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 251 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 252 static void cxgbe_qflush(struct ifnet *); 253 #if defined(KERN_TLS) || defined(RATELIMIT) 254 static int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 255 struct m_snd_tag **); 256 #endif 257 258 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 259 260 /* 261 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 262 * then ADAPTER_LOCK, then t4_uld_list_lock. 263 */ 264 static struct sx t4_list_lock; 265 SLIST_HEAD(, adapter) t4_list; 266 #ifdef TCP_OFFLOAD 267 static struct sx t4_uld_list_lock; 268 SLIST_HEAD(, uld_info) t4_uld_list; 269 #endif 270 271 /* 272 * Tunables. See tweak_tunables() too. 273 * 274 * Each tunable is set to a default value here if it's known at compile-time. 275 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 276 * provide a reasonable default (upto n) when the driver is loaded. 277 * 278 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 279 * T5 are under hw.cxl. 280 */ 281 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 282 "cxgbe(4) parameters"); 283 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 284 "cxgbe(4) T5+ parameters"); 285 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 286 "cxgbe(4) TOE parameters"); 287 288 /* 289 * Number of queues for tx and rx, NIC and offload. 290 */ 291 #define NTXQ 16 292 int t4_ntxq = -NTXQ; 293 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 294 "Number of TX queues per port"); 295 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 296 297 #define NRXQ 8 298 int t4_nrxq = -NRXQ; 299 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 300 "Number of RX queues per port"); 301 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 302 303 #define NTXQ_VI 1 304 static int t4_ntxq_vi = -NTXQ_VI; 305 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 306 "Number of TX queues per VI"); 307 308 #define NRXQ_VI 1 309 static int t4_nrxq_vi = -NRXQ_VI; 310 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 311 "Number of RX queues per VI"); 312 313 static int t4_rsrv_noflowq = 0; 314 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 315 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 316 317 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 318 #define NOFLDTXQ 8 319 static int t4_nofldtxq = -NOFLDTXQ; 320 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 321 "Number of offload TX queues per port"); 322 323 #define NOFLDRXQ 2 324 static int t4_nofldrxq = -NOFLDRXQ; 325 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 326 "Number of offload RX queues per port"); 327 328 #define NOFLDTXQ_VI 1 329 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 330 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 331 "Number of offload TX queues per VI"); 332 333 #define NOFLDRXQ_VI 1 334 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 335 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 336 "Number of offload RX queues per VI"); 337 338 #define TMR_IDX_OFLD 1 339 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 340 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 341 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 342 343 #define PKTC_IDX_OFLD (-1) 344 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 345 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 346 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 347 348 /* 0 means chip/fw default, non-zero number is value in microseconds */ 349 static u_long t4_toe_keepalive_idle = 0; 350 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 351 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 352 353 /* 0 means chip/fw default, non-zero number is value in microseconds */ 354 static u_long t4_toe_keepalive_interval = 0; 355 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 356 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 357 358 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 359 static int t4_toe_keepalive_count = 0; 360 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 361 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 362 363 /* 0 means chip/fw default, non-zero number is value in microseconds */ 364 static u_long t4_toe_rexmt_min = 0; 365 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 366 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 367 368 /* 0 means chip/fw default, non-zero number is value in microseconds */ 369 static u_long t4_toe_rexmt_max = 0; 370 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 371 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 372 373 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 374 static int t4_toe_rexmt_count = 0; 375 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 376 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 377 378 /* -1 means chip/fw default, other values are raw backoff values to use */ 379 static int t4_toe_rexmt_backoff[16] = { 380 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 381 }; 382 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, 383 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 384 "cxgbe(4) TOE retransmit backoff values"); 385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 386 &t4_toe_rexmt_backoff[0], 0, ""); 387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 388 &t4_toe_rexmt_backoff[1], 0, ""); 389 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 390 &t4_toe_rexmt_backoff[2], 0, ""); 391 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 392 &t4_toe_rexmt_backoff[3], 0, ""); 393 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 394 &t4_toe_rexmt_backoff[4], 0, ""); 395 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 396 &t4_toe_rexmt_backoff[5], 0, ""); 397 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 398 &t4_toe_rexmt_backoff[6], 0, ""); 399 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 400 &t4_toe_rexmt_backoff[7], 0, ""); 401 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 402 &t4_toe_rexmt_backoff[8], 0, ""); 403 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 404 &t4_toe_rexmt_backoff[9], 0, ""); 405 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 406 &t4_toe_rexmt_backoff[10], 0, ""); 407 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 408 &t4_toe_rexmt_backoff[11], 0, ""); 409 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 410 &t4_toe_rexmt_backoff[12], 0, ""); 411 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 412 &t4_toe_rexmt_backoff[13], 0, ""); 413 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 414 &t4_toe_rexmt_backoff[14], 0, ""); 415 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 416 &t4_toe_rexmt_backoff[15], 0, ""); 417 #endif 418 419 #ifdef DEV_NETMAP 420 #define NN_MAIN_VI (1 << 0) /* Native netmap on the main VI */ 421 #define NN_EXTRA_VI (1 << 1) /* Native netmap on the extra VI(s) */ 422 static int t4_native_netmap = NN_EXTRA_VI; 423 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap, 424 0, "Native netmap support. bit 0 = main VI, bit 1 = extra VIs"); 425 426 #define NNMTXQ 8 427 static int t4_nnmtxq = -NNMTXQ; 428 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0, 429 "Number of netmap TX queues"); 430 431 #define NNMRXQ 8 432 static int t4_nnmrxq = -NNMRXQ; 433 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0, 434 "Number of netmap RX queues"); 435 436 #define NNMTXQ_VI 2 437 static int t4_nnmtxq_vi = -NNMTXQ_VI; 438 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 439 "Number of netmap TX queues per VI"); 440 441 #define NNMRXQ_VI 2 442 static int t4_nnmrxq_vi = -NNMRXQ_VI; 443 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 444 "Number of netmap RX queues per VI"); 445 #endif 446 447 /* 448 * Holdoff parameters for ports. 449 */ 450 #define TMR_IDX 1 451 int t4_tmr_idx = TMR_IDX; 452 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 453 0, "Holdoff timer index"); 454 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 455 456 #define PKTC_IDX (-1) 457 int t4_pktc_idx = PKTC_IDX; 458 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 459 0, "Holdoff packet counter index"); 460 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 461 462 /* 463 * Size (# of entries) of each tx and rx queue. 464 */ 465 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 466 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 467 "Number of descriptors in each TX queue"); 468 469 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 470 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 471 "Number of descriptors in each RX queue"); 472 473 /* 474 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 475 */ 476 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 477 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 478 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 479 480 /* 481 * Configuration file. All the _CF names here are special. 482 */ 483 #define DEFAULT_CF "default" 484 #define BUILTIN_CF "built-in" 485 #define FLASH_CF "flash" 486 #define UWIRE_CF "uwire" 487 #define FPGA_CF "fpga" 488 static char t4_cfg_file[32] = DEFAULT_CF; 489 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 490 sizeof(t4_cfg_file), "Firmware configuration file"); 491 492 /* 493 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 494 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 495 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 496 * mark or when signalled to do so, 0 to never emit PAUSE. 497 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 498 * negotiated settings will override rx_pause/tx_pause. 499 * Otherwise rx_pause/tx_pause are applied forcibly. 500 */ 501 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 502 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 503 &t4_pause_settings, 0, 504 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 505 506 /* 507 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 508 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 509 * 0 to disable FEC. 510 */ 511 static int t4_fec = -1; 512 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 513 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 514 515 /* 516 * Controls when the driver sets the FORCE_FEC bit in the L1_CFG32 that it 517 * issues to the firmware. If the firmware doesn't support FORCE_FEC then the 518 * driver runs as if this is set to 0. 519 * -1 to set FORCE_FEC iff requested_fec != AUTO. Multiple FEC bits are okay. 520 * 0 to never set FORCE_FEC. requested_fec = AUTO means use the hint from the 521 * transceiver. Multiple FEC bits may not be okay but will be passed on to 522 * the firmware anyway (may result in l1cfg errors with old firmwares). 523 * 1 to always set FORCE_FEC. Multiple FEC bits are okay. requested_fec = AUTO 524 * means set all FEC bits that are valid for the speed. 525 */ 526 static int t4_force_fec = -1; 527 SYSCTL_INT(_hw_cxgbe, OID_AUTO, force_fec, CTLFLAG_RDTUN, &t4_force_fec, 0, 528 "Controls the use of FORCE_FEC bit in L1 configuration."); 529 530 /* 531 * Link autonegotiation. 532 * -1 to run with the firmware default. 533 * 0 to disable. 534 * 1 to enable. 535 */ 536 static int t4_autoneg = -1; 537 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 538 "Link autonegotiation"); 539 540 /* 541 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 542 * encouraged respectively). '-n' is the same as 'n' except the firmware 543 * version used in the checks is read from the firmware bundled with the driver. 544 */ 545 static int t4_fw_install = 1; 546 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 547 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 548 549 /* 550 * ASIC features that will be used. Disable the ones you don't want so that the 551 * chip resources aren't wasted on features that will not be used. 552 */ 553 static int t4_nbmcaps_allowed = 0; 554 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 555 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 556 557 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 558 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 559 &t4_linkcaps_allowed, 0, "Default link capabilities"); 560 561 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 562 FW_CAPS_CONFIG_SWITCH_EGRESS; 563 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 564 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 565 566 #ifdef RATELIMIT 567 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 568 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 569 #else 570 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 571 FW_CAPS_CONFIG_NIC_HASHFILTER; 572 #endif 573 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 574 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 575 576 static int t4_toecaps_allowed = -1; 577 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 578 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 579 580 static int t4_rdmacaps_allowed = -1; 581 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 582 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 583 584 static int t4_cryptocaps_allowed = -1; 585 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 586 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 587 588 static int t4_iscsicaps_allowed = -1; 589 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 590 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 591 592 static int t4_fcoecaps_allowed = 0; 593 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 594 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 595 596 static int t5_write_combine = 0; 597 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 598 0, "Use WC instead of UC for BAR2"); 599 600 static int t4_num_vis = 1; 601 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 602 "Number of VIs per port"); 603 604 /* 605 * PCIe Relaxed Ordering. 606 * -1: driver should figure out a good value. 607 * 0: disable RO. 608 * 1: enable RO. 609 * 2: leave RO alone. 610 */ 611 static int pcie_relaxed_ordering = -1; 612 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 613 &pcie_relaxed_ordering, 0, 614 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 615 616 static int t4_panic_on_fatal_err = 0; 617 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RWTUN, 618 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 619 620 static int t4_reset_on_fatal_err = 0; 621 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_on_fatal_err, CTLFLAG_RWTUN, 622 &t4_reset_on_fatal_err, 0, "reset adapter on fatal errors"); 623 624 static int t4_clock_gate_on_suspend = 0; 625 SYSCTL_INT(_hw_cxgbe, OID_AUTO, clock_gate_on_suspend, CTLFLAG_RWTUN, 626 &t4_clock_gate_on_suspend, 0, "gate the clock on suspend"); 627 628 static int t4_tx_vm_wr = 0; 629 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_vm_wr, CTLFLAG_RWTUN, &t4_tx_vm_wr, 0, 630 "Use VM work requests to transmit packets."); 631 632 /* 633 * Set to non-zero to enable the attack filter. A packet that matches any of 634 * these conditions will get dropped on ingress: 635 * 1) IP && source address == destination address. 636 * 2) TCP/IP && source address is not a unicast address. 637 * 3) TCP/IP && destination address is not a unicast address. 638 * 4) IP && source address is loopback (127.x.y.z). 639 * 5) IP && destination address is loopback (127.x.y.z). 640 * 6) IPv6 && source address == destination address. 641 * 7) IPv6 && source address is not a unicast address. 642 * 8) IPv6 && source address is loopback (::1/128). 643 * 9) IPv6 && destination address is loopback (::1/128). 644 * 10) IPv6 && source address is unspecified (::/128). 645 * 11) IPv6 && destination address is unspecified (::/128). 646 * 12) TCP/IPv6 && source address is multicast (ff00::/8). 647 * 13) TCP/IPv6 && destination address is multicast (ff00::/8). 648 */ 649 static int t4_attack_filter = 0; 650 SYSCTL_INT(_hw_cxgbe, OID_AUTO, attack_filter, CTLFLAG_RDTUN, 651 &t4_attack_filter, 0, "Drop suspicious traffic"); 652 653 static int t4_drop_ip_fragments = 0; 654 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_ip_fragments, CTLFLAG_RDTUN, 655 &t4_drop_ip_fragments, 0, "Drop IP fragments"); 656 657 static int t4_drop_pkts_with_l2_errors = 1; 658 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l2_errors, CTLFLAG_RDTUN, 659 &t4_drop_pkts_with_l2_errors, 0, 660 "Drop all frames with Layer 2 length or checksum errors"); 661 662 static int t4_drop_pkts_with_l3_errors = 0; 663 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l3_errors, CTLFLAG_RDTUN, 664 &t4_drop_pkts_with_l3_errors, 0, 665 "Drop all frames with IP version, length, or checksum errors"); 666 667 static int t4_drop_pkts_with_l4_errors = 0; 668 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l4_errors, CTLFLAG_RDTUN, 669 &t4_drop_pkts_with_l4_errors, 0, 670 "Drop all frames with Layer 4 length, checksum, or other errors"); 671 672 #ifdef TCP_OFFLOAD 673 /* 674 * TOE tunables. 675 */ 676 static int t4_cop_managed_offloading = 0; 677 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 678 &t4_cop_managed_offloading, 0, 679 "COP (Connection Offload Policy) controls all TOE offload"); 680 #endif 681 682 #ifdef KERN_TLS 683 /* 684 * This enables KERN_TLS for all adapters if set. 685 */ 686 static int t4_kern_tls = 0; 687 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0, 688 "Enable KERN_TLS mode for T6 adapters"); 689 690 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 691 "cxgbe(4) KERN_TLS parameters"); 692 693 static int t4_tls_inline_keys = 0; 694 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN, 695 &t4_tls_inline_keys, 0, 696 "Always pass TLS keys in work requests (1) or attempt to store TLS keys " 697 "in card memory."); 698 699 static int t4_tls_combo_wrs = 0; 700 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs, 701 0, "Attempt to combine TCB field updates with TLS record work requests."); 702 #endif 703 704 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 705 static int vi_mac_funcs[] = { 706 FW_VI_FUNC_ETH, 707 FW_VI_FUNC_OFLD, 708 FW_VI_FUNC_IWARP, 709 FW_VI_FUNC_OPENISCSI, 710 FW_VI_FUNC_OPENFCOE, 711 FW_VI_FUNC_FOISCSI, 712 FW_VI_FUNC_FOFCOE, 713 }; 714 715 struct intrs_and_queues { 716 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 717 uint16_t num_vis; /* number of VIs for each port */ 718 uint16_t nirq; /* Total # of vectors */ 719 uint16_t ntxq; /* # of NIC txq's for each port */ 720 uint16_t nrxq; /* # of NIC rxq's for each port */ 721 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 722 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 723 uint16_t nnmtxq; /* # of netmap txq's */ 724 uint16_t nnmrxq; /* # of netmap rxq's */ 725 726 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 727 uint16_t ntxq_vi; /* # of NIC txq's */ 728 uint16_t nrxq_vi; /* # of NIC rxq's */ 729 uint16_t nofldtxq_vi; /* # of TOE txq's */ 730 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 731 uint16_t nnmtxq_vi; /* # of netmap txq's */ 732 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 733 }; 734 735 static void setup_memwin(struct adapter *); 736 static void position_memwin(struct adapter *, int, uint32_t); 737 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 738 static int fwmtype_to_hwmtype(int); 739 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 740 uint32_t *); 741 static int fixup_devlog_params(struct adapter *); 742 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 743 static int contact_firmware(struct adapter *); 744 static int partition_resources(struct adapter *); 745 static int get_params__pre_init(struct adapter *); 746 static int set_params__pre_init(struct adapter *); 747 static int get_params__post_init(struct adapter *); 748 static int set_params__post_init(struct adapter *); 749 static void t4_set_desc(struct adapter *); 750 static bool fixed_ifmedia(struct port_info *); 751 static void build_medialist(struct port_info *); 752 static void init_link_config(struct port_info *); 753 static int fixup_link_config(struct port_info *); 754 static int apply_link_config(struct port_info *); 755 static int cxgbe_init_synchronized(struct vi_info *); 756 static int cxgbe_uninit_synchronized(struct vi_info *); 757 static int adapter_full_init(struct adapter *); 758 static void adapter_full_uninit(struct adapter *); 759 static int vi_full_init(struct vi_info *); 760 static void vi_full_uninit(struct vi_info *); 761 static int alloc_extra_vi(struct adapter *, struct port_info *, struct vi_info *); 762 static void quiesce_txq(struct sge_txq *); 763 static void quiesce_wrq(struct sge_wrq *); 764 static void quiesce_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 765 static void quiesce_vi(struct vi_info *); 766 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 767 driver_intr_t *, void *, char *); 768 static int t4_free_irq(struct adapter *, struct irq *); 769 static void t4_init_atid_table(struct adapter *); 770 static void t4_free_atid_table(struct adapter *); 771 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 772 static void vi_refresh_stats(struct vi_info *); 773 static void cxgbe_refresh_stats(struct vi_info *); 774 static void cxgbe_tick(void *); 775 static void vi_tick(void *); 776 static void cxgbe_sysctls(struct port_info *); 777 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 778 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 779 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 780 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 781 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 782 static int sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS); 783 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 784 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 785 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 786 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 787 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 788 static int sysctl_link_fec(SYSCTL_HANDLER_ARGS); 789 static int sysctl_requested_fec(SYSCTL_HANDLER_ARGS); 790 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS); 791 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 792 static int sysctl_force_fec(SYSCTL_HANDLER_ARGS); 793 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 794 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 795 static int sysctl_vdd(SYSCTL_HANDLER_ARGS); 796 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS); 797 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 798 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 799 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 800 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 801 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 802 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 803 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 804 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 805 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 806 static int sysctl_tid_stats(SYSCTL_HANDLER_ARGS); 807 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 808 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 809 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 810 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 811 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 812 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 813 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 814 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 815 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 816 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 817 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 818 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 819 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 820 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 821 static int sysctl_tnl_stats(SYSCTL_HANDLER_ARGS); 822 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 823 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 824 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 825 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 826 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 827 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 828 static int sysctl_reset(SYSCTL_HANDLER_ARGS); 829 #ifdef TCP_OFFLOAD 830 static int sysctl_tls(SYSCTL_HANDLER_ARGS); 831 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 832 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 833 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 834 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 835 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 836 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 837 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 838 #endif 839 static int get_sge_context(struct adapter *, struct t4_sge_context *); 840 static int load_fw(struct adapter *, struct t4_data *); 841 static int load_cfg(struct adapter *, struct t4_data *); 842 static int load_boot(struct adapter *, struct t4_bootrom *); 843 static int load_bootcfg(struct adapter *, struct t4_data *); 844 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 845 static void free_offload_policy(struct t4_offload_policy *); 846 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 847 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 848 static int read_i2c(struct adapter *, struct t4_i2c_data *); 849 static int clear_stats(struct adapter *, u_int); 850 static int hold_clip_addr(struct adapter *, struct t4_clip_addr *); 851 static int release_clip_addr(struct adapter *, struct t4_clip_addr *); 852 #ifdef TCP_OFFLOAD 853 static int toe_capability(struct vi_info *, bool); 854 static int t4_deactivate_all_uld(struct adapter *); 855 static void t4_async_event(struct adapter *); 856 #endif 857 #ifdef KERN_TLS 858 static int ktls_capability(struct adapter *, bool); 859 #endif 860 static int mod_event(module_t, int, void *); 861 static int notify_siblings(device_t, int); 862 static uint64_t vi_get_counter(struct ifnet *, ift_counter); 863 static uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 864 static void enable_vxlan_rx(struct adapter *); 865 static void reset_adapter_task(void *, int); 866 static void fatal_error_task(void *, int); 867 static void dump_devlog(struct adapter *); 868 static void dump_cim_regs(struct adapter *); 869 static void dump_cimla(struct adapter *); 870 871 struct { 872 uint16_t device; 873 char *desc; 874 } t4_pciids[] = { 875 {0xa000, "Chelsio Terminator 4 FPGA"}, 876 {0x4400, "Chelsio T440-dbg"}, 877 {0x4401, "Chelsio T420-CR"}, 878 {0x4402, "Chelsio T422-CR"}, 879 {0x4403, "Chelsio T440-CR"}, 880 {0x4404, "Chelsio T420-BCH"}, 881 {0x4405, "Chelsio T440-BCH"}, 882 {0x4406, "Chelsio T440-CH"}, 883 {0x4407, "Chelsio T420-SO"}, 884 {0x4408, "Chelsio T420-CX"}, 885 {0x4409, "Chelsio T420-BT"}, 886 {0x440a, "Chelsio T404-BT"}, 887 {0x440e, "Chelsio T440-LP-CR"}, 888 }, t5_pciids[] = { 889 {0xb000, "Chelsio Terminator 5 FPGA"}, 890 {0x5400, "Chelsio T580-dbg"}, 891 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 892 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 893 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 894 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 895 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 896 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 897 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 898 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 899 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 900 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 901 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 902 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 903 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 904 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 905 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 906 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 907 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 908 909 /* Custom */ 910 {0x5483, "Custom T540-CR"}, 911 {0x5484, "Custom T540-BT"}, 912 }, t6_pciids[] = { 913 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 914 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 915 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 916 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 917 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 918 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 919 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 920 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 921 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 922 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 923 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 924 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 925 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 926 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 927 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 928 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 929 930 /* Custom */ 931 {0x6480, "Custom T6225-CR"}, 932 {0x6481, "Custom T62100-CR"}, 933 {0x6482, "Custom T6225-CR"}, 934 {0x6483, "Custom T62100-CR"}, 935 {0x6484, "Custom T64100-CR"}, 936 {0x6485, "Custom T6240-SO"}, 937 {0x6486, "Custom T6225-SO-CR"}, 938 {0x6487, "Custom T6225-CR"}, 939 }; 940 941 #ifdef TCP_OFFLOAD 942 /* 943 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 944 * be exactly the same for both rxq and ofld_rxq. 945 */ 946 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 947 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 948 #endif 949 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 950 951 static int 952 t4_probe(device_t dev) 953 { 954 int i; 955 uint16_t v = pci_get_vendor(dev); 956 uint16_t d = pci_get_device(dev); 957 uint8_t f = pci_get_function(dev); 958 959 if (v != PCI_VENDOR_ID_CHELSIO) 960 return (ENXIO); 961 962 /* Attach only to PF0 of the FPGA */ 963 if (d == 0xa000 && f != 0) 964 return (ENXIO); 965 966 for (i = 0; i < nitems(t4_pciids); i++) { 967 if (d == t4_pciids[i].device) { 968 device_set_desc(dev, t4_pciids[i].desc); 969 return (BUS_PROBE_DEFAULT); 970 } 971 } 972 973 return (ENXIO); 974 } 975 976 static int 977 t5_probe(device_t dev) 978 { 979 int i; 980 uint16_t v = pci_get_vendor(dev); 981 uint16_t d = pci_get_device(dev); 982 uint8_t f = pci_get_function(dev); 983 984 if (v != PCI_VENDOR_ID_CHELSIO) 985 return (ENXIO); 986 987 /* Attach only to PF0 of the FPGA */ 988 if (d == 0xb000 && f != 0) 989 return (ENXIO); 990 991 for (i = 0; i < nitems(t5_pciids); i++) { 992 if (d == t5_pciids[i].device) { 993 device_set_desc(dev, t5_pciids[i].desc); 994 return (BUS_PROBE_DEFAULT); 995 } 996 } 997 998 return (ENXIO); 999 } 1000 1001 static int 1002 t6_probe(device_t dev) 1003 { 1004 int i; 1005 uint16_t v = pci_get_vendor(dev); 1006 uint16_t d = pci_get_device(dev); 1007 1008 if (v != PCI_VENDOR_ID_CHELSIO) 1009 return (ENXIO); 1010 1011 for (i = 0; i < nitems(t6_pciids); i++) { 1012 if (d == t6_pciids[i].device) { 1013 device_set_desc(dev, t6_pciids[i].desc); 1014 return (BUS_PROBE_DEFAULT); 1015 } 1016 } 1017 1018 return (ENXIO); 1019 } 1020 1021 static void 1022 t5_attribute_workaround(device_t dev) 1023 { 1024 device_t root_port; 1025 uint32_t v; 1026 1027 /* 1028 * The T5 chips do not properly echo the No Snoop and Relaxed 1029 * Ordering attributes when replying to a TLP from a Root 1030 * Port. As a workaround, find the parent Root Port and 1031 * disable No Snoop and Relaxed Ordering. Note that this 1032 * affects all devices under this root port. 1033 */ 1034 root_port = pci_find_pcie_root_port(dev); 1035 if (root_port == NULL) { 1036 device_printf(dev, "Unable to find parent root port\n"); 1037 return; 1038 } 1039 1040 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 1041 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 1042 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 1043 0) 1044 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 1045 device_get_nameunit(root_port)); 1046 } 1047 1048 static const struct devnames devnames[] = { 1049 { 1050 .nexus_name = "t4nex", 1051 .ifnet_name = "cxgbe", 1052 .vi_ifnet_name = "vcxgbe", 1053 .pf03_drv_name = "t4iov", 1054 .vf_nexus_name = "t4vf", 1055 .vf_ifnet_name = "cxgbev" 1056 }, { 1057 .nexus_name = "t5nex", 1058 .ifnet_name = "cxl", 1059 .vi_ifnet_name = "vcxl", 1060 .pf03_drv_name = "t5iov", 1061 .vf_nexus_name = "t5vf", 1062 .vf_ifnet_name = "cxlv" 1063 }, { 1064 .nexus_name = "t6nex", 1065 .ifnet_name = "cc", 1066 .vi_ifnet_name = "vcc", 1067 .pf03_drv_name = "t6iov", 1068 .vf_nexus_name = "t6vf", 1069 .vf_ifnet_name = "ccv" 1070 } 1071 }; 1072 1073 void 1074 t4_init_devnames(struct adapter *sc) 1075 { 1076 int id; 1077 1078 id = chip_id(sc); 1079 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 1080 sc->names = &devnames[id - CHELSIO_T4]; 1081 else { 1082 device_printf(sc->dev, "chip id %d is not supported.\n", id); 1083 sc->names = NULL; 1084 } 1085 } 1086 1087 static int 1088 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 1089 { 1090 const char *parent, *name; 1091 long value; 1092 int line, unit; 1093 1094 line = 0; 1095 parent = device_get_nameunit(sc->dev); 1096 name = sc->names->ifnet_name; 1097 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 1098 if (resource_long_value(name, unit, "port", &value) == 0 && 1099 value == pi->port_id) 1100 return (unit); 1101 } 1102 return (-1); 1103 } 1104 1105 static void 1106 t4_calibration(void *arg) 1107 { 1108 struct adapter *sc; 1109 struct clock_sync *cur, *nex; 1110 uint64_t hw; 1111 sbintime_t sbt; 1112 int next_up; 1113 1114 sc = (struct adapter *)arg; 1115 1116 KASSERT((hw_off_limits(sc) == 0), ("hw_off_limits at t4_calibration")); 1117 hw = t4_read_reg64(sc, A_SGE_TIMESTAMP_LO); 1118 sbt = sbinuptime(); 1119 1120 cur = &sc->cal_info[sc->cal_current]; 1121 next_up = (sc->cal_current + 1) % CNT_CAL_INFO; 1122 nex = &sc->cal_info[next_up]; 1123 if (__predict_false(sc->cal_count == 0)) { 1124 /* First time in, just get the values in */ 1125 cur->hw_cur = hw; 1126 cur->sbt_cur = sbt; 1127 sc->cal_count++; 1128 goto done; 1129 } 1130 1131 if (cur->hw_cur == hw) { 1132 /* The clock is not advancing? */ 1133 sc->cal_count = 0; 1134 atomic_store_rel_int(&cur->gen, 0); 1135 goto done; 1136 } 1137 1138 seqc_write_begin(&nex->gen); 1139 nex->hw_prev = cur->hw_cur; 1140 nex->sbt_prev = cur->sbt_cur; 1141 nex->hw_cur = hw; 1142 nex->sbt_cur = sbt; 1143 seqc_write_end(&nex->gen); 1144 sc->cal_current = next_up; 1145 done: 1146 callout_reset_sbt_curcpu(&sc->cal_callout, SBT_1S, 0, t4_calibration, 1147 sc, C_DIRECT_EXEC); 1148 } 1149 1150 static void 1151 t4_calibration_start(struct adapter *sc) 1152 { 1153 /* 1154 * Here if we have not done a calibration 1155 * then do so otherwise start the appropriate 1156 * timer. 1157 */ 1158 int i; 1159 1160 for (i = 0; i < CNT_CAL_INFO; i++) { 1161 sc->cal_info[i].gen = 0; 1162 } 1163 sc->cal_current = 0; 1164 sc->cal_count = 0; 1165 sc->cal_gen = 0; 1166 t4_calibration(sc); 1167 } 1168 1169 static int 1170 t4_attach(device_t dev) 1171 { 1172 struct adapter *sc; 1173 int rc = 0, i, j, rqidx, tqidx, nports; 1174 struct make_dev_args mda; 1175 struct intrs_and_queues iaq; 1176 struct sge *s; 1177 uint32_t *buf; 1178 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1179 int ofld_tqidx; 1180 #endif 1181 #ifdef TCP_OFFLOAD 1182 int ofld_rqidx; 1183 #endif 1184 #ifdef DEV_NETMAP 1185 int nm_rqidx, nm_tqidx; 1186 #endif 1187 int num_vis; 1188 1189 sc = device_get_softc(dev); 1190 sc->dev = dev; 1191 sysctl_ctx_init(&sc->ctx); 1192 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 1193 1194 if ((pci_get_device(dev) & 0xff00) == 0x5400) 1195 t5_attribute_workaround(dev); 1196 pci_enable_busmaster(dev); 1197 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 1198 uint32_t v; 1199 1200 pci_set_max_read_req(dev, 4096); 1201 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 1202 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 1203 if (pcie_relaxed_ordering == 0 && 1204 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 1205 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 1206 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1207 } else if (pcie_relaxed_ordering == 1 && 1208 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 1209 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 1210 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 1211 } 1212 } 1213 1214 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 1215 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 1216 sc->traceq = -1; 1217 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 1218 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 1219 device_get_nameunit(dev)); 1220 1221 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 1222 device_get_nameunit(dev)); 1223 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 1224 t4_add_adapter(sc); 1225 1226 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 1227 TAILQ_INIT(&sc->sfl); 1228 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 1229 1230 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 1231 1232 sc->policy = NULL; 1233 rw_init(&sc->policy_lock, "connection offload policy"); 1234 1235 callout_init(&sc->ktls_tick, 1); 1236 1237 callout_init(&sc->cal_callout, 1); 1238 1239 refcount_init(&sc->vxlan_refcount, 0); 1240 1241 TASK_INIT(&sc->reset_task, 0, reset_adapter_task, sc); 1242 TASK_INIT(&sc->fatal_error_task, 0, fatal_error_task, sc); 1243 1244 sc->ctrlq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1245 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "ctrlq", 1246 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues"); 1247 sc->fwq_oid = SYSCTL_ADD_NODE(&sc->ctx, 1248 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "fwq", 1249 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue"); 1250 1251 rc = t4_map_bars_0_and_4(sc); 1252 if (rc != 0) 1253 goto done; /* error message displayed already */ 1254 1255 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1256 1257 /* Prepare the adapter for operation. */ 1258 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1259 rc = -t4_prep_adapter(sc, buf); 1260 free(buf, M_CXGBE); 1261 if (rc != 0) { 1262 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1263 goto done; 1264 } 1265 1266 /* 1267 * This is the real PF# to which we're attaching. Works from within PCI 1268 * passthrough environments too, where pci_get_function() could return a 1269 * different PF# depending on the passthrough configuration. We need to 1270 * use the real PF# in all our communication with the firmware. 1271 */ 1272 j = t4_read_reg(sc, A_PL_WHOAMI); 1273 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1274 sc->mbox = sc->pf; 1275 1276 t4_init_devnames(sc); 1277 if (sc->names == NULL) { 1278 rc = ENOTSUP; 1279 goto done; /* error message displayed already */ 1280 } 1281 1282 /* 1283 * Do this really early, with the memory windows set up even before the 1284 * character device. The userland tool's register i/o and mem read 1285 * will work even in "recovery mode". 1286 */ 1287 setup_memwin(sc); 1288 if (t4_init_devlog_params(sc, 0) == 0) 1289 fixup_devlog_params(sc); 1290 make_dev_args_init(&mda); 1291 mda.mda_devsw = &t4_cdevsw; 1292 mda.mda_uid = UID_ROOT; 1293 mda.mda_gid = GID_WHEEL; 1294 mda.mda_mode = 0600; 1295 mda.mda_si_drv1 = sc; 1296 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1297 if (rc != 0) 1298 device_printf(dev, "failed to create nexus char device: %d.\n", 1299 rc); 1300 1301 /* Go no further if recovery mode has been requested. */ 1302 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1303 device_printf(dev, "recovery mode.\n"); 1304 goto done; 1305 } 1306 1307 #if defined(__i386__) 1308 if ((cpu_feature & CPUID_CX8) == 0) { 1309 device_printf(dev, "64 bit atomics not available.\n"); 1310 rc = ENOTSUP; 1311 goto done; 1312 } 1313 #endif 1314 1315 /* Contact the firmware and try to become the master driver. */ 1316 rc = contact_firmware(sc); 1317 if (rc != 0) 1318 goto done; /* error message displayed already */ 1319 MPASS(sc->flags & FW_OK); 1320 1321 rc = get_params__pre_init(sc); 1322 if (rc != 0) 1323 goto done; /* error message displayed already */ 1324 1325 if (sc->flags & MASTER_PF) { 1326 rc = partition_resources(sc); 1327 if (rc != 0) 1328 goto done; /* error message displayed already */ 1329 t4_intr_clear(sc); 1330 } 1331 1332 rc = get_params__post_init(sc); 1333 if (rc != 0) 1334 goto done; /* error message displayed already */ 1335 1336 rc = set_params__post_init(sc); 1337 if (rc != 0) 1338 goto done; /* error message displayed already */ 1339 1340 rc = t4_map_bar_2(sc); 1341 if (rc != 0) 1342 goto done; /* error message displayed already */ 1343 1344 rc = t4_create_dma_tag(sc); 1345 if (rc != 0) 1346 goto done; /* error message displayed already */ 1347 1348 /* 1349 * First pass over all the ports - allocate VIs and initialize some 1350 * basic parameters like mac address, port type, etc. 1351 */ 1352 for_each_port(sc, i) { 1353 struct port_info *pi; 1354 1355 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1356 sc->port[i] = pi; 1357 1358 /* These must be set before t4_port_init */ 1359 pi->adapter = sc; 1360 pi->port_id = i; 1361 /* 1362 * XXX: vi[0] is special so we can't delay this allocation until 1363 * pi->nvi's final value is known. 1364 */ 1365 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1366 M_ZERO | M_WAITOK); 1367 1368 /* 1369 * Allocate the "main" VI and initialize parameters 1370 * like mac addr. 1371 */ 1372 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1373 if (rc != 0) { 1374 device_printf(dev, "unable to initialize port %d: %d\n", 1375 i, rc); 1376 free(pi->vi, M_CXGBE); 1377 free(pi, M_CXGBE); 1378 sc->port[i] = NULL; 1379 goto done; 1380 } 1381 1382 if (is_bt(pi->port_type)) 1383 setbit(&sc->bt_map, pi->tx_chan); 1384 else 1385 MPASS(!isset(&sc->bt_map, pi->tx_chan)); 1386 1387 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1388 device_get_nameunit(dev), i); 1389 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1390 sc->chan_map[pi->tx_chan] = i; 1391 1392 /* 1393 * The MPS counter for FCS errors doesn't work correctly on the 1394 * T6 so we use the MAC counter here. Which MAC is in use 1395 * depends on the link settings which will be known when the 1396 * link comes up. 1397 */ 1398 if (is_t6(sc)) { 1399 pi->fcs_reg = -1; 1400 } else if (is_t4(sc)) { 1401 pi->fcs_reg = PORT_REG(pi->tx_chan, 1402 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L); 1403 } else { 1404 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 1405 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L); 1406 } 1407 pi->fcs_base = 0; 1408 1409 /* All VIs on this port share this media. */ 1410 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1411 cxgbe_media_status); 1412 1413 PORT_LOCK(pi); 1414 init_link_config(pi); 1415 fixup_link_config(pi); 1416 build_medialist(pi); 1417 if (fixed_ifmedia(pi)) 1418 pi->flags |= FIXED_IFMEDIA; 1419 PORT_UNLOCK(pi); 1420 1421 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1422 t4_ifnet_unit(sc, pi)); 1423 if (pi->dev == NULL) { 1424 device_printf(dev, 1425 "failed to add device for port %d.\n", i); 1426 rc = ENXIO; 1427 goto done; 1428 } 1429 pi->vi[0].dev = pi->dev; 1430 device_set_softc(pi->dev, pi); 1431 } 1432 1433 /* 1434 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1435 */ 1436 nports = sc->params.nports; 1437 rc = cfg_itype_and_nqueues(sc, &iaq); 1438 if (rc != 0) 1439 goto done; /* error message displayed already */ 1440 1441 num_vis = iaq.num_vis; 1442 sc->intr_type = iaq.intr_type; 1443 sc->intr_count = iaq.nirq; 1444 1445 s = &sc->sge; 1446 s->nrxq = nports * iaq.nrxq; 1447 s->ntxq = nports * iaq.ntxq; 1448 if (num_vis > 1) { 1449 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1450 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1451 } 1452 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1453 s->neq += nports; /* ctrl queues: 1 per port */ 1454 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1455 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1456 if (is_offload(sc) || is_ethoffload(sc)) { 1457 s->nofldtxq = nports * iaq.nofldtxq; 1458 if (num_vis > 1) 1459 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1460 s->neq += s->nofldtxq; 1461 1462 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_ofld_txq), 1463 M_CXGBE, M_ZERO | M_WAITOK); 1464 } 1465 #endif 1466 #ifdef TCP_OFFLOAD 1467 if (is_offload(sc)) { 1468 s->nofldrxq = nports * iaq.nofldrxq; 1469 if (num_vis > 1) 1470 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1471 s->neq += s->nofldrxq; /* free list */ 1472 s->niq += s->nofldrxq; 1473 1474 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1475 M_CXGBE, M_ZERO | M_WAITOK); 1476 } 1477 #endif 1478 #ifdef DEV_NETMAP 1479 s->nnmrxq = 0; 1480 s->nnmtxq = 0; 1481 if (t4_native_netmap & NN_MAIN_VI) { 1482 s->nnmrxq += nports * iaq.nnmrxq; 1483 s->nnmtxq += nports * iaq.nnmtxq; 1484 } 1485 if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) { 1486 s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi; 1487 s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi; 1488 } 1489 s->neq += s->nnmtxq + s->nnmrxq; 1490 s->niq += s->nnmrxq; 1491 1492 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1493 M_CXGBE, M_ZERO | M_WAITOK); 1494 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1495 M_CXGBE, M_ZERO | M_WAITOK); 1496 #endif 1497 MPASS(s->niq <= s->iqmap_sz); 1498 MPASS(s->neq <= s->eqmap_sz); 1499 1500 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1501 M_ZERO | M_WAITOK); 1502 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1503 M_ZERO | M_WAITOK); 1504 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1505 M_ZERO | M_WAITOK); 1506 s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE, 1507 M_ZERO | M_WAITOK); 1508 s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE, 1509 M_ZERO | M_WAITOK); 1510 1511 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1512 M_ZERO | M_WAITOK); 1513 1514 t4_init_l2t(sc, M_WAITOK); 1515 t4_init_smt(sc, M_WAITOK); 1516 t4_init_tx_sched(sc); 1517 t4_init_atid_table(sc); 1518 #ifdef RATELIMIT 1519 t4_init_etid_table(sc); 1520 #endif 1521 #ifdef INET6 1522 t4_init_clip_table(sc); 1523 #endif 1524 if (sc->vres.key.size != 0) 1525 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1526 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1527 1528 /* 1529 * Second pass over the ports. This time we know the number of rx and 1530 * tx queues that each port should get. 1531 */ 1532 rqidx = tqidx = 0; 1533 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1534 ofld_tqidx = 0; 1535 #endif 1536 #ifdef TCP_OFFLOAD 1537 ofld_rqidx = 0; 1538 #endif 1539 #ifdef DEV_NETMAP 1540 nm_rqidx = nm_tqidx = 0; 1541 #endif 1542 for_each_port(sc, i) { 1543 struct port_info *pi = sc->port[i]; 1544 struct vi_info *vi; 1545 1546 if (pi == NULL) 1547 continue; 1548 1549 pi->nvi = num_vis; 1550 for_each_vi(pi, j, vi) { 1551 vi->pi = pi; 1552 vi->adapter = sc; 1553 vi->first_intr = -1; 1554 vi->qsize_rxq = t4_qsize_rxq; 1555 vi->qsize_txq = t4_qsize_txq; 1556 1557 vi->first_rxq = rqidx; 1558 vi->first_txq = tqidx; 1559 vi->tmr_idx = t4_tmr_idx; 1560 vi->pktc_idx = t4_pktc_idx; 1561 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1562 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1563 1564 rqidx += vi->nrxq; 1565 tqidx += vi->ntxq; 1566 1567 if (j == 0 && vi->ntxq > 1) 1568 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1569 else 1570 vi->rsrv_noflowq = 0; 1571 1572 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1573 vi->first_ofld_txq = ofld_tqidx; 1574 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1575 ofld_tqidx += vi->nofldtxq; 1576 #endif 1577 #ifdef TCP_OFFLOAD 1578 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1579 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1580 vi->first_ofld_rxq = ofld_rqidx; 1581 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1582 1583 ofld_rqidx += vi->nofldrxq; 1584 #endif 1585 #ifdef DEV_NETMAP 1586 vi->first_nm_rxq = nm_rqidx; 1587 vi->first_nm_txq = nm_tqidx; 1588 if (j == 0) { 1589 vi->nnmrxq = iaq.nnmrxq; 1590 vi->nnmtxq = iaq.nnmtxq; 1591 } else { 1592 vi->nnmrxq = iaq.nnmrxq_vi; 1593 vi->nnmtxq = iaq.nnmtxq_vi; 1594 } 1595 nm_rqidx += vi->nnmrxq; 1596 nm_tqidx += vi->nnmtxq; 1597 #endif 1598 } 1599 } 1600 1601 rc = t4_setup_intr_handlers(sc); 1602 if (rc != 0) { 1603 device_printf(dev, 1604 "failed to setup interrupt handlers: %d\n", rc); 1605 goto done; 1606 } 1607 1608 rc = bus_generic_probe(dev); 1609 if (rc != 0) { 1610 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1611 goto done; 1612 } 1613 1614 /* 1615 * Ensure thread-safe mailbox access (in debug builds). 1616 * 1617 * So far this was the only thread accessing the mailbox but various 1618 * ifnets and sysctls are about to be created and their handlers/ioctls 1619 * will access the mailbox from different threads. 1620 */ 1621 sc->flags |= CHK_MBOX_ACCESS; 1622 1623 rc = bus_generic_attach(dev); 1624 if (rc != 0) { 1625 device_printf(dev, 1626 "failed to attach all child ports: %d\n", rc); 1627 goto done; 1628 } 1629 t4_calibration_start(sc); 1630 1631 device_printf(dev, 1632 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1633 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1634 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1635 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1636 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1637 1638 t4_set_desc(sc); 1639 1640 notify_siblings(dev, 0); 1641 1642 done: 1643 if (rc != 0 && sc->cdev) { 1644 /* cdev was created and so cxgbetool works; recover that way. */ 1645 device_printf(dev, 1646 "error during attach, adapter is now in recovery mode.\n"); 1647 rc = 0; 1648 } 1649 1650 if (rc != 0) 1651 t4_detach_common(dev); 1652 else 1653 t4_sysctls(sc); 1654 1655 return (rc); 1656 } 1657 1658 static int 1659 t4_child_location(device_t bus, device_t dev, struct sbuf *sb) 1660 { 1661 struct adapter *sc; 1662 struct port_info *pi; 1663 int i; 1664 1665 sc = device_get_softc(bus); 1666 for_each_port(sc, i) { 1667 pi = sc->port[i]; 1668 if (pi != NULL && pi->dev == dev) { 1669 sbuf_printf(sb, "port=%d", pi->port_id); 1670 break; 1671 } 1672 } 1673 return (0); 1674 } 1675 1676 static int 1677 t4_ready(device_t dev) 1678 { 1679 struct adapter *sc; 1680 1681 sc = device_get_softc(dev); 1682 if (sc->flags & FW_OK) 1683 return (0); 1684 return (ENXIO); 1685 } 1686 1687 static int 1688 t4_read_port_device(device_t dev, int port, device_t *child) 1689 { 1690 struct adapter *sc; 1691 struct port_info *pi; 1692 1693 sc = device_get_softc(dev); 1694 if (port < 0 || port >= MAX_NPORTS) 1695 return (EINVAL); 1696 pi = sc->port[port]; 1697 if (pi == NULL || pi->dev == NULL) 1698 return (ENXIO); 1699 *child = pi->dev; 1700 return (0); 1701 } 1702 1703 static int 1704 notify_siblings(device_t dev, int detaching) 1705 { 1706 device_t sibling; 1707 int error, i; 1708 1709 error = 0; 1710 for (i = 0; i < PCI_FUNCMAX; i++) { 1711 if (i == pci_get_function(dev)) 1712 continue; 1713 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1714 pci_get_slot(dev), i); 1715 if (sibling == NULL || !device_is_attached(sibling)) 1716 continue; 1717 if (detaching) 1718 error = T4_DETACH_CHILD(sibling); 1719 else 1720 (void)T4_ATTACH_CHILD(sibling); 1721 if (error) 1722 break; 1723 } 1724 return (error); 1725 } 1726 1727 /* 1728 * Idempotent 1729 */ 1730 static int 1731 t4_detach(device_t dev) 1732 { 1733 int rc; 1734 1735 rc = notify_siblings(dev, 1); 1736 if (rc) { 1737 device_printf(dev, 1738 "failed to detach sibling devices: %d\n", rc); 1739 return (rc); 1740 } 1741 1742 return (t4_detach_common(dev)); 1743 } 1744 1745 int 1746 t4_detach_common(device_t dev) 1747 { 1748 struct adapter *sc; 1749 struct port_info *pi; 1750 int i, rc; 1751 1752 sc = device_get_softc(dev); 1753 1754 #ifdef TCP_OFFLOAD 1755 rc = t4_deactivate_all_uld(sc); 1756 if (rc) { 1757 device_printf(dev, 1758 "failed to detach upper layer drivers: %d\n", rc); 1759 return (rc); 1760 } 1761 #endif 1762 1763 if (sc->cdev) { 1764 destroy_dev(sc->cdev); 1765 sc->cdev = NULL; 1766 } 1767 1768 sx_xlock(&t4_list_lock); 1769 SLIST_REMOVE(&t4_list, sc, adapter, link); 1770 sx_xunlock(&t4_list_lock); 1771 1772 sc->flags &= ~CHK_MBOX_ACCESS; 1773 if (sc->flags & FULL_INIT_DONE) { 1774 if (!(sc->flags & IS_VF)) 1775 t4_intr_disable(sc); 1776 } 1777 1778 if (device_is_attached(dev)) { 1779 rc = bus_generic_detach(dev); 1780 if (rc) { 1781 device_printf(dev, 1782 "failed to detach child devices: %d\n", rc); 1783 return (rc); 1784 } 1785 } 1786 1787 for (i = 0; i < sc->intr_count; i++) 1788 t4_free_irq(sc, &sc->irq[i]); 1789 1790 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1791 t4_free_tx_sched(sc); 1792 1793 for (i = 0; i < MAX_NPORTS; i++) { 1794 pi = sc->port[i]; 1795 if (pi) { 1796 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1797 if (pi->dev) 1798 device_delete_child(dev, pi->dev); 1799 1800 mtx_destroy(&pi->pi_lock); 1801 free(pi->vi, M_CXGBE); 1802 free(pi, M_CXGBE); 1803 } 1804 } 1805 callout_stop(&sc->cal_callout); 1806 callout_drain(&sc->cal_callout); 1807 device_delete_children(dev); 1808 sysctl_ctx_free(&sc->ctx); 1809 adapter_full_uninit(sc); 1810 1811 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1812 t4_fw_bye(sc, sc->mbox); 1813 1814 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1815 pci_release_msi(dev); 1816 1817 if (sc->regs_res) 1818 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1819 sc->regs_res); 1820 1821 if (sc->udbs_res) 1822 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1823 sc->udbs_res); 1824 1825 if (sc->msix_res) 1826 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1827 sc->msix_res); 1828 1829 if (sc->l2t) 1830 t4_free_l2t(sc->l2t); 1831 if (sc->smt) 1832 t4_free_smt(sc->smt); 1833 t4_free_atid_table(sc); 1834 #ifdef RATELIMIT 1835 t4_free_etid_table(sc); 1836 #endif 1837 if (sc->key_map) 1838 vmem_destroy(sc->key_map); 1839 #ifdef INET6 1840 t4_destroy_clip_table(sc); 1841 #endif 1842 1843 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1844 free(sc->sge.ofld_txq, M_CXGBE); 1845 #endif 1846 #ifdef TCP_OFFLOAD 1847 free(sc->sge.ofld_rxq, M_CXGBE); 1848 #endif 1849 #ifdef DEV_NETMAP 1850 free(sc->sge.nm_rxq, M_CXGBE); 1851 free(sc->sge.nm_txq, M_CXGBE); 1852 #endif 1853 free(sc->irq, M_CXGBE); 1854 free(sc->sge.rxq, M_CXGBE); 1855 free(sc->sge.txq, M_CXGBE); 1856 free(sc->sge.ctrlq, M_CXGBE); 1857 free(sc->sge.iqmap, M_CXGBE); 1858 free(sc->sge.eqmap, M_CXGBE); 1859 free(sc->tids.ftid_tab, M_CXGBE); 1860 free(sc->tids.hpftid_tab, M_CXGBE); 1861 free_hftid_hash(&sc->tids); 1862 free(sc->tids.tid_tab, M_CXGBE); 1863 t4_destroy_dma_tag(sc); 1864 1865 callout_drain(&sc->ktls_tick); 1866 callout_drain(&sc->sfl_callout); 1867 if (mtx_initialized(&sc->tids.ftid_lock)) { 1868 mtx_destroy(&sc->tids.ftid_lock); 1869 cv_destroy(&sc->tids.ftid_cv); 1870 } 1871 if (mtx_initialized(&sc->tids.atid_lock)) 1872 mtx_destroy(&sc->tids.atid_lock); 1873 if (mtx_initialized(&sc->ifp_lock)) 1874 mtx_destroy(&sc->ifp_lock); 1875 1876 if (rw_initialized(&sc->policy_lock)) { 1877 rw_destroy(&sc->policy_lock); 1878 #ifdef TCP_OFFLOAD 1879 if (sc->policy != NULL) 1880 free_offload_policy(sc->policy); 1881 #endif 1882 } 1883 1884 for (i = 0; i < NUM_MEMWIN; i++) { 1885 struct memwin *mw = &sc->memwin[i]; 1886 1887 if (rw_initialized(&mw->mw_lock)) 1888 rw_destroy(&mw->mw_lock); 1889 } 1890 1891 mtx_destroy(&sc->sfl_lock); 1892 mtx_destroy(&sc->reg_lock); 1893 mtx_destroy(&sc->sc_lock); 1894 1895 bzero(sc, sizeof(*sc)); 1896 1897 return (0); 1898 } 1899 1900 static inline bool 1901 ok_to_reset(struct adapter *sc) 1902 { 1903 struct tid_info *t = &sc->tids; 1904 struct port_info *pi; 1905 struct vi_info *vi; 1906 int i, j; 1907 int caps = IFCAP_TOE | IFCAP_NETMAP | IFCAP_TXRTLMT; 1908 1909 if (is_t6(sc)) 1910 caps |= IFCAP_TXTLS; 1911 1912 ASSERT_SYNCHRONIZED_OP(sc); 1913 MPASS(!(sc->flags & IS_VF)); 1914 1915 for_each_port(sc, i) { 1916 pi = sc->port[i]; 1917 for_each_vi(pi, j, vi) { 1918 if (vi->ifp->if_capenable & caps) 1919 return (false); 1920 } 1921 } 1922 1923 if (atomic_load_int(&t->tids_in_use) > 0) 1924 return (false); 1925 if (atomic_load_int(&t->stids_in_use) > 0) 1926 return (false); 1927 if (atomic_load_int(&t->atids_in_use) > 0) 1928 return (false); 1929 if (atomic_load_int(&t->ftids_in_use) > 0) 1930 return (false); 1931 if (atomic_load_int(&t->hpftids_in_use) > 0) 1932 return (false); 1933 if (atomic_load_int(&t->etids_in_use) > 0) 1934 return (false); 1935 1936 return (true); 1937 } 1938 1939 static inline int 1940 stop_adapter(struct adapter *sc) 1941 { 1942 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_STOPPED))) 1943 return (1); /* Already stopped. */ 1944 return (t4_shutdown_adapter(sc)); 1945 } 1946 1947 static int 1948 t4_suspend(device_t dev) 1949 { 1950 struct adapter *sc = device_get_softc(dev); 1951 struct port_info *pi; 1952 struct vi_info *vi; 1953 struct ifnet *ifp; 1954 struct sge_rxq *rxq; 1955 struct sge_txq *txq; 1956 struct sge_wrq *wrq; 1957 #ifdef TCP_OFFLOAD 1958 struct sge_ofld_rxq *ofld_rxq; 1959 #endif 1960 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1961 struct sge_ofld_txq *ofld_txq; 1962 #endif 1963 int rc, i, j, k; 1964 1965 CH_ALERT(sc, "suspend requested\n"); 1966 1967 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4sus"); 1968 if (rc != 0) 1969 return (ENXIO); 1970 1971 /* XXX: Can the kernel call suspend repeatedly without resume? */ 1972 MPASS(!hw_off_limits(sc)); 1973 1974 if (!ok_to_reset(sc)) { 1975 /* XXX: should list what resource is preventing suspend. */ 1976 CH_ERR(sc, "not safe to suspend.\n"); 1977 rc = EBUSY; 1978 goto done; 1979 } 1980 1981 /* No more DMA or interrupts. */ 1982 stop_adapter(sc); 1983 1984 /* Quiesce all activity. */ 1985 for_each_port(sc, i) { 1986 pi = sc->port[i]; 1987 pi->vxlan_tcam_entry = false; 1988 1989 PORT_LOCK(pi); 1990 if (pi->up_vis > 0) { 1991 /* 1992 * t4_shutdown_adapter has already shut down all the 1993 * PHYs but it also disables interrupts and DMA so there 1994 * won't be a link interrupt. So we update the state 1995 * manually and inform the kernel. 1996 */ 1997 pi->link_cfg.link_ok = false; 1998 t4_os_link_changed(pi); 1999 } 2000 PORT_UNLOCK(pi); 2001 2002 for_each_vi(pi, j, vi) { 2003 vi->xact_addr_filt = -1; 2004 mtx_lock(&vi->tick_mtx); 2005 vi->flags |= VI_SKIP_STATS; 2006 mtx_unlock(&vi->tick_mtx); 2007 if (!(vi->flags & VI_INIT_DONE)) 2008 continue; 2009 2010 ifp = vi->ifp; 2011 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2012 mtx_lock(&vi->tick_mtx); 2013 callout_stop(&vi->tick); 2014 mtx_unlock(&vi->tick_mtx); 2015 callout_drain(&vi->tick); 2016 } 2017 2018 /* 2019 * Note that the HW is not available. 2020 */ 2021 for_each_txq(vi, k, txq) { 2022 TXQ_LOCK(txq); 2023 txq->eq.flags &= ~(EQ_ENABLED | EQ_HW_ALLOCATED); 2024 TXQ_UNLOCK(txq); 2025 } 2026 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2027 for_each_ofld_txq(vi, k, ofld_txq) { 2028 ofld_txq->wrq.eq.flags &= ~EQ_HW_ALLOCATED; 2029 } 2030 #endif 2031 for_each_rxq(vi, k, rxq) { 2032 rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2033 } 2034 #if defined(TCP_OFFLOAD) 2035 for_each_ofld_rxq(vi, k, ofld_rxq) { 2036 ofld_rxq->iq.flags &= ~IQ_HW_ALLOCATED; 2037 } 2038 #endif 2039 2040 quiesce_vi(vi); 2041 } 2042 2043 if (sc->flags & FULL_INIT_DONE) { 2044 /* Control queue */ 2045 wrq = &sc->sge.ctrlq[i]; 2046 wrq->eq.flags &= ~EQ_HW_ALLOCATED; 2047 quiesce_wrq(wrq); 2048 } 2049 } 2050 if (sc->flags & FULL_INIT_DONE) { 2051 /* Firmware event queue */ 2052 sc->sge.fwq.flags &= ~IQ_HW_ALLOCATED; 2053 quiesce_iq_fl(sc, &sc->sge.fwq, NULL); 2054 } 2055 2056 /* Stop calibration */ 2057 callout_stop(&sc->cal_callout); 2058 callout_drain(&sc->cal_callout); 2059 2060 /* Mark the adapter totally off limits. */ 2061 mtx_lock(&sc->reg_lock); 2062 atomic_set_int(&sc->error_flags, HW_OFF_LIMITS); 2063 sc->flags &= ~(FW_OK | MASTER_PF); 2064 sc->reset_thread = NULL; 2065 mtx_unlock(&sc->reg_lock); 2066 2067 if (t4_clock_gate_on_suspend) { 2068 t4_set_reg_field(sc, A_PMU_PART_CG_PWRMODE, F_MA_PART_CGEN | 2069 F_LE_PART_CGEN | F_EDC1_PART_CGEN | F_EDC0_PART_CGEN | 2070 F_TP_PART_CGEN | F_PDP_PART_CGEN | F_SGE_PART_CGEN, 0); 2071 } 2072 2073 CH_ALERT(sc, "suspend completed.\n"); 2074 done: 2075 end_synchronized_op(sc, 0); 2076 return (rc); 2077 } 2078 2079 struct adapter_pre_reset_state { 2080 u_int flags; 2081 uint16_t nbmcaps; 2082 uint16_t linkcaps; 2083 uint16_t switchcaps; 2084 uint16_t niccaps; 2085 uint16_t toecaps; 2086 uint16_t rdmacaps; 2087 uint16_t cryptocaps; 2088 uint16_t iscsicaps; 2089 uint16_t fcoecaps; 2090 2091 u_int cfcsum; 2092 char cfg_file[32]; 2093 2094 struct adapter_params params; 2095 struct t4_virt_res vres; 2096 struct tid_info tids; 2097 struct sge sge; 2098 2099 int rawf_base; 2100 int nrawf; 2101 2102 }; 2103 2104 static void 2105 save_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2106 { 2107 2108 ASSERT_SYNCHRONIZED_OP(sc); 2109 2110 o->flags = sc->flags; 2111 2112 o->nbmcaps = sc->nbmcaps; 2113 o->linkcaps = sc->linkcaps; 2114 o->switchcaps = sc->switchcaps; 2115 o->niccaps = sc->niccaps; 2116 o->toecaps = sc->toecaps; 2117 o->rdmacaps = sc->rdmacaps; 2118 o->cryptocaps = sc->cryptocaps; 2119 o->iscsicaps = sc->iscsicaps; 2120 o->fcoecaps = sc->fcoecaps; 2121 2122 o->cfcsum = sc->cfcsum; 2123 MPASS(sizeof(o->cfg_file) == sizeof(sc->cfg_file)); 2124 memcpy(o->cfg_file, sc->cfg_file, sizeof(o->cfg_file)); 2125 2126 o->params = sc->params; 2127 o->vres = sc->vres; 2128 o->tids = sc->tids; 2129 o->sge = sc->sge; 2130 2131 o->rawf_base = sc->rawf_base; 2132 o->nrawf = sc->nrawf; 2133 } 2134 2135 static int 2136 compare_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o) 2137 { 2138 int rc = 0; 2139 2140 ASSERT_SYNCHRONIZED_OP(sc); 2141 2142 /* Capabilities */ 2143 #define COMPARE_CAPS(c) do { \ 2144 if (o->c##caps != sc->c##caps) { \ 2145 CH_ERR(sc, "%scaps 0x%04x -> 0x%04x.\n", #c, o->c##caps, \ 2146 sc->c##caps); \ 2147 rc = EINVAL; \ 2148 } \ 2149 } while (0) 2150 COMPARE_CAPS(nbm); 2151 COMPARE_CAPS(link); 2152 COMPARE_CAPS(switch); 2153 COMPARE_CAPS(nic); 2154 COMPARE_CAPS(toe); 2155 COMPARE_CAPS(rdma); 2156 COMPARE_CAPS(crypto); 2157 COMPARE_CAPS(iscsi); 2158 COMPARE_CAPS(fcoe); 2159 #undef COMPARE_CAPS 2160 2161 /* Firmware config file */ 2162 if (o->cfcsum != sc->cfcsum) { 2163 CH_ERR(sc, "config file %s (0x%x) -> %s (0x%x)\n", o->cfg_file, 2164 o->cfcsum, sc->cfg_file, sc->cfcsum); 2165 rc = EINVAL; 2166 } 2167 2168 #define COMPARE_PARAM(p, name) do { \ 2169 if (o->p != sc->p) { \ 2170 CH_ERR(sc, #name " %d -> %d\n", o->p, sc->p); \ 2171 rc = EINVAL; \ 2172 } \ 2173 } while (0) 2174 COMPARE_PARAM(sge.iq_start, iq_start); 2175 COMPARE_PARAM(sge.eq_start, eq_start); 2176 COMPARE_PARAM(tids.ftid_base, ftid_base); 2177 COMPARE_PARAM(tids.ftid_end, ftid_end); 2178 COMPARE_PARAM(tids.nftids, nftids); 2179 COMPARE_PARAM(vres.l2t.start, l2t_start); 2180 COMPARE_PARAM(vres.l2t.size, l2t_size); 2181 COMPARE_PARAM(sge.iqmap_sz, iqmap_sz); 2182 COMPARE_PARAM(sge.eqmap_sz, eqmap_sz); 2183 COMPARE_PARAM(tids.tid_base, tid_base); 2184 COMPARE_PARAM(tids.hpftid_base, hpftid_base); 2185 COMPARE_PARAM(tids.hpftid_end, hpftid_end); 2186 COMPARE_PARAM(tids.nhpftids, nhpftids); 2187 COMPARE_PARAM(rawf_base, rawf_base); 2188 COMPARE_PARAM(nrawf, nrawf); 2189 COMPARE_PARAM(params.mps_bg_map, mps_bg_map); 2190 COMPARE_PARAM(params.filter2_wr_support, filter2_wr_support); 2191 COMPARE_PARAM(params.ulptx_memwrite_dsgl, ulptx_memwrite_dsgl); 2192 COMPARE_PARAM(params.fr_nsmr_tpte_wr_support, fr_nsmr_tpte_wr_support); 2193 COMPARE_PARAM(params.max_pkts_per_eth_tx_pkts_wr, max_pkts_per_eth_tx_pkts_wr); 2194 COMPARE_PARAM(tids.ntids, ntids); 2195 COMPARE_PARAM(tids.etid_base, etid_base); 2196 COMPARE_PARAM(tids.etid_end, etid_end); 2197 COMPARE_PARAM(tids.netids, netids); 2198 COMPARE_PARAM(params.eo_wr_cred, eo_wr_cred); 2199 COMPARE_PARAM(params.ethoffload, ethoffload); 2200 COMPARE_PARAM(tids.natids, natids); 2201 COMPARE_PARAM(tids.stid_base, stid_base); 2202 COMPARE_PARAM(vres.ddp.start, ddp_start); 2203 COMPARE_PARAM(vres.ddp.size, ddp_size); 2204 COMPARE_PARAM(params.ofldq_wr_cred, ofldq_wr_cred); 2205 COMPARE_PARAM(vres.stag.start, stag_start); 2206 COMPARE_PARAM(vres.stag.size, stag_size); 2207 COMPARE_PARAM(vres.rq.start, rq_start); 2208 COMPARE_PARAM(vres.rq.size, rq_size); 2209 COMPARE_PARAM(vres.pbl.start, pbl_start); 2210 COMPARE_PARAM(vres.pbl.size, pbl_size); 2211 COMPARE_PARAM(vres.qp.start, qp_start); 2212 COMPARE_PARAM(vres.qp.size, qp_size); 2213 COMPARE_PARAM(vres.cq.start, cq_start); 2214 COMPARE_PARAM(vres.cq.size, cq_size); 2215 COMPARE_PARAM(vres.ocq.start, ocq_start); 2216 COMPARE_PARAM(vres.ocq.size, ocq_size); 2217 COMPARE_PARAM(vres.srq.start, srq_start); 2218 COMPARE_PARAM(vres.srq.size, srq_size); 2219 COMPARE_PARAM(params.max_ordird_qp, max_ordird_qp); 2220 COMPARE_PARAM(params.max_ird_adapter, max_ird_adapter); 2221 COMPARE_PARAM(vres.iscsi.start, iscsi_start); 2222 COMPARE_PARAM(vres.iscsi.size, iscsi_size); 2223 COMPARE_PARAM(vres.key.start, key_start); 2224 COMPARE_PARAM(vres.key.size, key_size); 2225 #undef COMPARE_PARAM 2226 2227 return (rc); 2228 } 2229 2230 static int 2231 t4_resume(device_t dev) 2232 { 2233 struct adapter *sc = device_get_softc(dev); 2234 struct adapter_pre_reset_state *old_state = NULL; 2235 struct port_info *pi; 2236 struct vi_info *vi; 2237 struct ifnet *ifp; 2238 struct sge_txq *txq; 2239 int rc, i, j, k; 2240 2241 CH_ALERT(sc, "resume requested.\n"); 2242 2243 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4res"); 2244 if (rc != 0) 2245 return (ENXIO); 2246 MPASS(hw_off_limits(sc)); 2247 MPASS((sc->flags & FW_OK) == 0); 2248 MPASS((sc->flags & MASTER_PF) == 0); 2249 MPASS(sc->reset_thread == NULL); 2250 sc->reset_thread = curthread; 2251 2252 /* Register access is expected to work by the time we're here. */ 2253 if (t4_read_reg(sc, A_PL_WHOAMI) == 0xffffffff) { 2254 CH_ERR(sc, "%s: can't read device registers\n", __func__); 2255 rc = ENXIO; 2256 goto done; 2257 } 2258 2259 /* Note that HW_OFF_LIMITS is cleared a bit later. */ 2260 atomic_clear_int(&sc->error_flags, ADAP_FATAL_ERR | ADAP_STOPPED); 2261 2262 /* Restore memory window. */ 2263 setup_memwin(sc); 2264 2265 /* Go no further if recovery mode has been requested. */ 2266 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 2267 CH_ALERT(sc, "recovery mode on resume.\n"); 2268 rc = 0; 2269 mtx_lock(&sc->reg_lock); 2270 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS); 2271 mtx_unlock(&sc->reg_lock); 2272 goto done; 2273 } 2274 2275 old_state = malloc(sizeof(*old_state), M_CXGBE, M_ZERO | M_WAITOK); 2276 save_caps_and_params(sc, old_state); 2277 2278 /* Reestablish contact with firmware and become the primary PF. */ 2279 rc = contact_firmware(sc); 2280 if (rc != 0) 2281 goto done; /* error message displayed already */ 2282 MPASS(sc->flags & FW_OK); 2283 2284 if (sc->flags & MASTER_PF) { 2285 rc = partition_resources(sc); 2286 if (rc != 0) 2287 goto done; /* error message displayed already */ 2288 t4_intr_clear(sc); 2289 } 2290 2291 rc = get_params__post_init(sc); 2292 if (rc != 0) 2293 goto done; /* error message displayed already */ 2294 2295 rc = set_params__post_init(sc); 2296 if (rc != 0) 2297 goto done; /* error message displayed already */ 2298 2299 rc = compare_caps_and_params(sc, old_state); 2300 if (rc != 0) 2301 goto done; /* error message displayed already */ 2302 2303 for_each_port(sc, i) { 2304 pi = sc->port[i]; 2305 MPASS(pi != NULL); 2306 MPASS(pi->vi != NULL); 2307 MPASS(pi->vi[0].dev == pi->dev); 2308 2309 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 2310 if (rc != 0) { 2311 CH_ERR(sc, 2312 "failed to re-initialize port %d: %d\n", i, rc); 2313 goto done; 2314 } 2315 MPASS(sc->chan_map[pi->tx_chan] == i); 2316 2317 PORT_LOCK(pi); 2318 fixup_link_config(pi); 2319 build_medialist(pi); 2320 PORT_UNLOCK(pi); 2321 for_each_vi(pi, j, vi) { 2322 if (IS_MAIN_VI(vi)) 2323 continue; 2324 rc = alloc_extra_vi(sc, pi, vi); 2325 if (rc != 0) { 2326 CH_ERR(vi, 2327 "failed to re-allocate extra VI: %d\n", rc); 2328 goto done; 2329 } 2330 } 2331 } 2332 2333 /* 2334 * Interrupts and queues are about to be enabled and other threads will 2335 * want to access the hardware too. It is safe to do so. Note that 2336 * this thread is still in the middle of a synchronized_op. 2337 */ 2338 mtx_lock(&sc->reg_lock); 2339 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS); 2340 mtx_unlock(&sc->reg_lock); 2341 2342 if (sc->flags & FULL_INIT_DONE) { 2343 rc = adapter_full_init(sc); 2344 if (rc != 0) { 2345 CH_ERR(sc, "failed to re-initialize adapter: %d\n", rc); 2346 goto done; 2347 } 2348 2349 if (sc->vxlan_refcount > 0) 2350 enable_vxlan_rx(sc); 2351 2352 for_each_port(sc, i) { 2353 pi = sc->port[i]; 2354 for_each_vi(pi, j, vi) { 2355 mtx_lock(&vi->tick_mtx); 2356 vi->flags &= ~VI_SKIP_STATS; 2357 mtx_unlock(&vi->tick_mtx); 2358 if (!(vi->flags & VI_INIT_DONE)) 2359 continue; 2360 rc = vi_full_init(vi); 2361 if (rc != 0) { 2362 CH_ERR(vi, "failed to re-initialize " 2363 "interface: %d\n", rc); 2364 goto done; 2365 } 2366 2367 ifp = vi->ifp; 2368 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 2369 continue; 2370 /* 2371 * Note that we do not setup multicast addresses 2372 * in the first pass. This ensures that the 2373 * unicast DMACs for all VIs on all ports get an 2374 * MPS TCAM entry. 2375 */ 2376 rc = update_mac_settings(ifp, XGMAC_ALL & 2377 ~XGMAC_MCADDRS); 2378 if (rc != 0) { 2379 CH_ERR(vi, "failed to re-configure MAC: %d\n", rc); 2380 goto done; 2381 } 2382 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, 2383 true); 2384 if (rc != 0) { 2385 CH_ERR(vi, "failed to re-enable VI: %d\n", rc); 2386 goto done; 2387 } 2388 for_each_txq(vi, k, txq) { 2389 TXQ_LOCK(txq); 2390 txq->eq.flags |= EQ_ENABLED; 2391 TXQ_UNLOCK(txq); 2392 } 2393 mtx_lock(&vi->tick_mtx); 2394 callout_schedule(&vi->tick, hz); 2395 mtx_unlock(&vi->tick_mtx); 2396 } 2397 PORT_LOCK(pi); 2398 if (pi->up_vis > 0) { 2399 t4_update_port_info(pi); 2400 fixup_link_config(pi); 2401 build_medialist(pi); 2402 apply_link_config(pi); 2403 if (pi->link_cfg.link_ok) 2404 t4_os_link_changed(pi); 2405 } 2406 PORT_UNLOCK(pi); 2407 } 2408 2409 /* Now reprogram the L2 multicast addresses. */ 2410 for_each_port(sc, i) { 2411 pi = sc->port[i]; 2412 for_each_vi(pi, j, vi) { 2413 if (!(vi->flags & VI_INIT_DONE)) 2414 continue; 2415 ifp = vi->ifp; 2416 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 2417 continue; 2418 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2419 if (rc != 0) { 2420 CH_ERR(vi, "failed to re-configure MCAST MACs: %d\n", rc); 2421 rc = 0; /* carry on */ 2422 } 2423 } 2424 } 2425 } 2426 2427 /* Reset all calibration */ 2428 t4_calibration_start(sc); 2429 2430 done: 2431 if (rc == 0) { 2432 sc->incarnation++; 2433 CH_ALERT(sc, "resume completed.\n"); 2434 } 2435 end_synchronized_op(sc, 0); 2436 free(old_state, M_CXGBE); 2437 return (rc); 2438 } 2439 2440 static int 2441 t4_reset_prepare(device_t dev, device_t child) 2442 { 2443 struct adapter *sc = device_get_softc(dev); 2444 2445 CH_ALERT(sc, "reset_prepare.\n"); 2446 return (0); 2447 } 2448 2449 static int 2450 t4_reset_post(device_t dev, device_t child) 2451 { 2452 struct adapter *sc = device_get_softc(dev); 2453 2454 CH_ALERT(sc, "reset_post.\n"); 2455 return (0); 2456 } 2457 2458 static int 2459 reset_adapter(struct adapter *sc) 2460 { 2461 int rc, oldinc, error_flags; 2462 2463 CH_ALERT(sc, "reset requested.\n"); 2464 2465 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rst1"); 2466 if (rc != 0) 2467 return (EBUSY); 2468 2469 if (hw_off_limits(sc)) { 2470 CH_ERR(sc, "adapter is suspended, use resume (not reset).\n"); 2471 rc = ENXIO; 2472 goto done; 2473 } 2474 2475 if (!ok_to_reset(sc)) { 2476 /* XXX: should list what resource is preventing reset. */ 2477 CH_ERR(sc, "not safe to reset.\n"); 2478 rc = EBUSY; 2479 goto done; 2480 } 2481 2482 done: 2483 oldinc = sc->incarnation; 2484 end_synchronized_op(sc, 0); 2485 if (rc != 0) 2486 return (rc); /* Error logged already. */ 2487 2488 atomic_add_int(&sc->num_resets, 1); 2489 mtx_lock(&Giant); 2490 rc = BUS_RESET_CHILD(device_get_parent(sc->dev), sc->dev, 0); 2491 mtx_unlock(&Giant); 2492 if (rc != 0) 2493 CH_ERR(sc, "bus_reset_child failed: %d.\n", rc); 2494 else { 2495 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rst2"); 2496 if (rc != 0) 2497 return (EBUSY); 2498 error_flags = atomic_load_int(&sc->error_flags); 2499 if (sc->incarnation > oldinc && error_flags == 0) { 2500 CH_ALERT(sc, "bus_reset_child succeeded.\n"); 2501 } else { 2502 CH_ERR(sc, "adapter did not reset properly, flags " 2503 "0x%08x, error_flags 0x%08x.\n", sc->flags, 2504 error_flags); 2505 rc = ENXIO; 2506 } 2507 end_synchronized_op(sc, 0); 2508 } 2509 2510 return (rc); 2511 } 2512 2513 static void 2514 reset_adapter_task(void *arg, int pending) 2515 { 2516 /* XXX: t4_async_event here? */ 2517 reset_adapter(arg); 2518 } 2519 2520 static int 2521 cxgbe_probe(device_t dev) 2522 { 2523 char buf[128]; 2524 struct port_info *pi = device_get_softc(dev); 2525 2526 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 2527 device_set_desc_copy(dev, buf); 2528 2529 return (BUS_PROBE_DEFAULT); 2530 } 2531 2532 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 2533 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 2534 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 2535 IFCAP_HWRXTSTMP | IFCAP_MEXTPG) 2536 #define T4_CAP_ENABLE (T4_CAP) 2537 2538 static int 2539 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 2540 { 2541 struct ifnet *ifp; 2542 struct sbuf *sb; 2543 struct sysctl_ctx_list *ctx = &vi->ctx; 2544 struct sysctl_oid_list *children; 2545 struct pfil_head_args pa; 2546 struct adapter *sc = vi->adapter; 2547 2548 sysctl_ctx_init(ctx); 2549 children = SYSCTL_CHILDREN(device_get_sysctl_tree(vi->dev)); 2550 vi->rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rxq", 2551 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC rx queues"); 2552 vi->txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "txq", 2553 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC tx queues"); 2554 #ifdef DEV_NETMAP 2555 vi->nm_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_rxq", 2556 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap rx queues"); 2557 vi->nm_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_txq", 2558 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queues"); 2559 #endif 2560 #ifdef TCP_OFFLOAD 2561 vi->ofld_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_rxq", 2562 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE rx queues"); 2563 #endif 2564 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2565 vi->ofld_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_txq", 2566 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE/ETHOFLD tx queues"); 2567 #endif 2568 2569 vi->xact_addr_filt = -1; 2570 mtx_init(&vi->tick_mtx, "vi tick", NULL, MTX_DEF); 2571 callout_init_mtx(&vi->tick, &vi->tick_mtx, 0); 2572 if (sc->flags & IS_VF || t4_tx_vm_wr != 0) 2573 vi->flags |= TX_USES_VM_WR; 2574 2575 /* Allocate an ifnet and set it up */ 2576 ifp = if_alloc_dev(IFT_ETHER, dev); 2577 if (ifp == NULL) { 2578 device_printf(dev, "Cannot allocate ifnet\n"); 2579 return (ENOMEM); 2580 } 2581 vi->ifp = ifp; 2582 ifp->if_softc = vi; 2583 2584 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2585 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2586 2587 ifp->if_init = cxgbe_init; 2588 ifp->if_ioctl = cxgbe_ioctl; 2589 ifp->if_transmit = cxgbe_transmit; 2590 ifp->if_qflush = cxgbe_qflush; 2591 if (vi->pi->nvi > 1 || sc->flags & IS_VF) 2592 ifp->if_get_counter = vi_get_counter; 2593 else 2594 ifp->if_get_counter = cxgbe_get_counter; 2595 #if defined(KERN_TLS) || defined(RATELIMIT) 2596 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc; 2597 #endif 2598 #ifdef RATELIMIT 2599 ifp->if_ratelimit_query = cxgbe_ratelimit_query; 2600 #endif 2601 2602 ifp->if_capabilities = T4_CAP; 2603 ifp->if_capenable = T4_CAP_ENABLE; 2604 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 2605 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 2606 if (chip_id(sc) >= CHELSIO_T6) { 2607 ifp->if_capabilities |= IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO; 2608 ifp->if_capenable |= IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO; 2609 ifp->if_hwassist |= CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 2610 CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2611 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN; 2612 } 2613 2614 #ifdef TCP_OFFLOAD 2615 if (vi->nofldrxq != 0) 2616 ifp->if_capabilities |= IFCAP_TOE; 2617 #endif 2618 #ifdef RATELIMIT 2619 if (is_ethoffload(sc) && vi->nofldtxq != 0) { 2620 ifp->if_capabilities |= IFCAP_TXRTLMT; 2621 ifp->if_capenable |= IFCAP_TXRTLMT; 2622 } 2623 #endif 2624 2625 ifp->if_hw_tsomax = IP_MAXPACKET; 2626 if (vi->flags & TX_USES_VM_WR) 2627 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_VM_TSO; 2628 else 2629 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO; 2630 #ifdef RATELIMIT 2631 if (is_ethoffload(sc) && vi->nofldtxq != 0) 2632 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO; 2633 #endif 2634 ifp->if_hw_tsomaxsegsize = 65536; 2635 #ifdef KERN_TLS 2636 if (is_ktls(sc)) { 2637 ifp->if_capabilities |= IFCAP_TXTLS; 2638 if (sc->flags & KERN_TLS_ON || !is_t6(sc)) 2639 ifp->if_capenable |= IFCAP_TXTLS; 2640 } 2641 #endif 2642 2643 ether_ifattach(ifp, vi->hw_addr); 2644 #ifdef DEV_NETMAP 2645 if (vi->nnmrxq != 0) 2646 cxgbe_nm_attach(vi); 2647 #endif 2648 sb = sbuf_new_auto(); 2649 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 2650 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 2651 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) { 2652 case IFCAP_TOE: 2653 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 2654 break; 2655 case IFCAP_TOE | IFCAP_TXRTLMT: 2656 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 2657 break; 2658 case IFCAP_TXRTLMT: 2659 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 2660 break; 2661 } 2662 #endif 2663 #ifdef TCP_OFFLOAD 2664 if (ifp->if_capabilities & IFCAP_TOE) 2665 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 2666 #endif 2667 #ifdef DEV_NETMAP 2668 if (ifp->if_capabilities & IFCAP_NETMAP) 2669 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 2670 vi->nnmtxq, vi->nnmrxq); 2671 #endif 2672 sbuf_finish(sb); 2673 device_printf(dev, "%s\n", sbuf_data(sb)); 2674 sbuf_delete(sb); 2675 2676 vi_sysctls(vi); 2677 2678 pa.pa_version = PFIL_VERSION; 2679 pa.pa_flags = PFIL_IN; 2680 pa.pa_type = PFIL_TYPE_ETHERNET; 2681 pa.pa_headname = ifp->if_xname; 2682 vi->pfil = pfil_head_register(&pa); 2683 2684 return (0); 2685 } 2686 2687 static int 2688 cxgbe_attach(device_t dev) 2689 { 2690 struct port_info *pi = device_get_softc(dev); 2691 struct adapter *sc = pi->adapter; 2692 struct vi_info *vi; 2693 int i, rc; 2694 2695 sysctl_ctx_init(&pi->ctx); 2696 2697 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 2698 if (rc) 2699 return (rc); 2700 2701 for_each_vi(pi, i, vi) { 2702 if (i == 0) 2703 continue; 2704 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 2705 if (vi->dev == NULL) { 2706 device_printf(dev, "failed to add VI %d\n", i); 2707 continue; 2708 } 2709 device_set_softc(vi->dev, vi); 2710 } 2711 2712 cxgbe_sysctls(pi); 2713 2714 bus_generic_attach(dev); 2715 2716 return (0); 2717 } 2718 2719 static void 2720 cxgbe_vi_detach(struct vi_info *vi) 2721 { 2722 struct ifnet *ifp = vi->ifp; 2723 2724 if (vi->pfil != NULL) { 2725 pfil_head_unregister(vi->pfil); 2726 vi->pfil = NULL; 2727 } 2728 2729 ether_ifdetach(ifp); 2730 2731 /* Let detach proceed even if these fail. */ 2732 #ifdef DEV_NETMAP 2733 if (ifp->if_capabilities & IFCAP_NETMAP) 2734 cxgbe_nm_detach(vi); 2735 #endif 2736 cxgbe_uninit_synchronized(vi); 2737 callout_drain(&vi->tick); 2738 sysctl_ctx_free(&vi->ctx); 2739 vi_full_uninit(vi); 2740 2741 if_free(vi->ifp); 2742 vi->ifp = NULL; 2743 } 2744 2745 static int 2746 cxgbe_detach(device_t dev) 2747 { 2748 struct port_info *pi = device_get_softc(dev); 2749 struct adapter *sc = pi->adapter; 2750 int rc; 2751 2752 /* Detach the extra VIs first. */ 2753 rc = bus_generic_detach(dev); 2754 if (rc) 2755 return (rc); 2756 device_delete_children(dev); 2757 2758 sysctl_ctx_free(&pi->ctx); 2759 doom_vi(sc, &pi->vi[0]); 2760 2761 if (pi->flags & HAS_TRACEQ) { 2762 sc->traceq = -1; /* cloner should not create ifnet */ 2763 t4_tracer_port_detach(sc); 2764 } 2765 2766 cxgbe_vi_detach(&pi->vi[0]); 2767 ifmedia_removeall(&pi->media); 2768 2769 end_synchronized_op(sc, 0); 2770 2771 return (0); 2772 } 2773 2774 static void 2775 cxgbe_init(void *arg) 2776 { 2777 struct vi_info *vi = arg; 2778 struct adapter *sc = vi->adapter; 2779 2780 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 2781 return; 2782 cxgbe_init_synchronized(vi); 2783 end_synchronized_op(sc, 0); 2784 } 2785 2786 static int 2787 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 2788 { 2789 int rc = 0, mtu, flags; 2790 struct vi_info *vi = ifp->if_softc; 2791 struct port_info *pi = vi->pi; 2792 struct adapter *sc = pi->adapter; 2793 struct ifreq *ifr = (struct ifreq *)data; 2794 uint32_t mask; 2795 2796 switch (cmd) { 2797 case SIOCSIFMTU: 2798 mtu = ifr->ifr_mtu; 2799 if (mtu < ETHERMIN || mtu > MAX_MTU) 2800 return (EINVAL); 2801 2802 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 2803 if (rc) 2804 return (rc); 2805 ifp->if_mtu = mtu; 2806 if (vi->flags & VI_INIT_DONE) { 2807 t4_update_fl_bufsize(ifp); 2808 if (!hw_off_limits(sc) && 2809 ifp->if_drv_flags & IFF_DRV_RUNNING) 2810 rc = update_mac_settings(ifp, XGMAC_MTU); 2811 } 2812 end_synchronized_op(sc, 0); 2813 break; 2814 2815 case SIOCSIFFLAGS: 2816 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 2817 if (rc) 2818 return (rc); 2819 2820 if (hw_off_limits(sc)) { 2821 rc = ENXIO; 2822 goto fail; 2823 } 2824 2825 if (ifp->if_flags & IFF_UP) { 2826 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2827 flags = vi->if_flags; 2828 if ((ifp->if_flags ^ flags) & 2829 (IFF_PROMISC | IFF_ALLMULTI)) { 2830 rc = update_mac_settings(ifp, 2831 XGMAC_PROMISC | XGMAC_ALLMULTI); 2832 } 2833 } else { 2834 rc = cxgbe_init_synchronized(vi); 2835 } 2836 vi->if_flags = ifp->if_flags; 2837 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2838 rc = cxgbe_uninit_synchronized(vi); 2839 } 2840 end_synchronized_op(sc, 0); 2841 break; 2842 2843 case SIOCADDMULTI: 2844 case SIOCDELMULTI: 2845 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 2846 if (rc) 2847 return (rc); 2848 if (!hw_off_limits(sc) && ifp->if_drv_flags & IFF_DRV_RUNNING) 2849 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 2850 end_synchronized_op(sc, 0); 2851 break; 2852 2853 case SIOCSIFCAP: 2854 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 2855 if (rc) 2856 return (rc); 2857 2858 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2859 if (mask & IFCAP_TXCSUM) { 2860 ifp->if_capenable ^= IFCAP_TXCSUM; 2861 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 2862 2863 if (IFCAP_TSO4 & ifp->if_capenable && 2864 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2865 mask &= ~IFCAP_TSO4; 2866 ifp->if_capenable &= ~IFCAP_TSO4; 2867 if_printf(ifp, 2868 "tso4 disabled due to -txcsum.\n"); 2869 } 2870 } 2871 if (mask & IFCAP_TXCSUM_IPV6) { 2872 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 2873 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2874 2875 if (IFCAP_TSO6 & ifp->if_capenable && 2876 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2877 mask &= ~IFCAP_TSO6; 2878 ifp->if_capenable &= ~IFCAP_TSO6; 2879 if_printf(ifp, 2880 "tso6 disabled due to -txcsum6.\n"); 2881 } 2882 } 2883 if (mask & IFCAP_RXCSUM) 2884 ifp->if_capenable ^= IFCAP_RXCSUM; 2885 if (mask & IFCAP_RXCSUM_IPV6) 2886 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 2887 2888 /* 2889 * Note that we leave CSUM_TSO alone (it is always set). The 2890 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 2891 * sending a TSO request our way, so it's sufficient to toggle 2892 * IFCAP_TSOx only. 2893 */ 2894 if (mask & IFCAP_TSO4) { 2895 if (!(IFCAP_TSO4 & ifp->if_capenable) && 2896 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2897 if_printf(ifp, "enable txcsum first.\n"); 2898 rc = EAGAIN; 2899 goto fail; 2900 } 2901 ifp->if_capenable ^= IFCAP_TSO4; 2902 } 2903 if (mask & IFCAP_TSO6) { 2904 if (!(IFCAP_TSO6 & ifp->if_capenable) && 2905 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2906 if_printf(ifp, "enable txcsum6 first.\n"); 2907 rc = EAGAIN; 2908 goto fail; 2909 } 2910 ifp->if_capenable ^= IFCAP_TSO6; 2911 } 2912 if (mask & IFCAP_LRO) { 2913 #if defined(INET) || defined(INET6) 2914 int i; 2915 struct sge_rxq *rxq; 2916 2917 ifp->if_capenable ^= IFCAP_LRO; 2918 for_each_rxq(vi, i, rxq) { 2919 if (ifp->if_capenable & IFCAP_LRO) 2920 rxq->iq.flags |= IQ_LRO_ENABLED; 2921 else 2922 rxq->iq.flags &= ~IQ_LRO_ENABLED; 2923 } 2924 #endif 2925 } 2926 #ifdef TCP_OFFLOAD 2927 if (mask & IFCAP_TOE) { 2928 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 2929 2930 rc = toe_capability(vi, enable); 2931 if (rc != 0) 2932 goto fail; 2933 2934 ifp->if_capenable ^= mask; 2935 } 2936 #endif 2937 if (mask & IFCAP_VLAN_HWTAGGING) { 2938 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2939 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2940 rc = update_mac_settings(ifp, XGMAC_VLANEX); 2941 } 2942 if (mask & IFCAP_VLAN_MTU) { 2943 ifp->if_capenable ^= IFCAP_VLAN_MTU; 2944 2945 /* Need to find out how to disable auto-mtu-inflation */ 2946 } 2947 if (mask & IFCAP_VLAN_HWTSO) 2948 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2949 if (mask & IFCAP_VLAN_HWCSUM) 2950 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2951 #ifdef RATELIMIT 2952 if (mask & IFCAP_TXRTLMT) 2953 ifp->if_capenable ^= IFCAP_TXRTLMT; 2954 #endif 2955 if (mask & IFCAP_HWRXTSTMP) { 2956 int i; 2957 struct sge_rxq *rxq; 2958 2959 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 2960 for_each_rxq(vi, i, rxq) { 2961 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 2962 rxq->iq.flags |= IQ_RX_TIMESTAMP; 2963 else 2964 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 2965 } 2966 } 2967 if (mask & IFCAP_MEXTPG) 2968 ifp->if_capenable ^= IFCAP_MEXTPG; 2969 2970 #ifdef KERN_TLS 2971 if (mask & IFCAP_TXTLS) { 2972 int enable = (ifp->if_capenable ^ mask) & IFCAP_TXTLS; 2973 2974 rc = ktls_capability(sc, enable); 2975 if (rc != 0) 2976 goto fail; 2977 2978 ifp->if_capenable ^= (mask & IFCAP_TXTLS); 2979 } 2980 #endif 2981 if (mask & IFCAP_VXLAN_HWCSUM) { 2982 ifp->if_capenable ^= IFCAP_VXLAN_HWCSUM; 2983 ifp->if_hwassist ^= CSUM_INNER_IP6_UDP | 2984 CSUM_INNER_IP6_TCP | CSUM_INNER_IP | 2985 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP; 2986 } 2987 if (mask & IFCAP_VXLAN_HWTSO) { 2988 ifp->if_capenable ^= IFCAP_VXLAN_HWTSO; 2989 ifp->if_hwassist ^= CSUM_INNER_IP6_TSO | 2990 CSUM_INNER_IP_TSO; 2991 } 2992 2993 #ifdef VLAN_CAPABILITIES 2994 VLAN_CAPABILITIES(ifp); 2995 #endif 2996 fail: 2997 end_synchronized_op(sc, 0); 2998 break; 2999 3000 case SIOCSIFMEDIA: 3001 case SIOCGIFMEDIA: 3002 case SIOCGIFXMEDIA: 3003 rc = ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 3004 break; 3005 3006 case SIOCGI2C: { 3007 struct ifi2creq i2c; 3008 3009 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3010 if (rc != 0) 3011 break; 3012 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3013 rc = EPERM; 3014 break; 3015 } 3016 if (i2c.len > sizeof(i2c.data)) { 3017 rc = EINVAL; 3018 break; 3019 } 3020 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 3021 if (rc) 3022 return (rc); 3023 if (hw_off_limits(sc)) 3024 rc = ENXIO; 3025 else 3026 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 3027 i2c.offset, i2c.len, &i2c.data[0]); 3028 end_synchronized_op(sc, 0); 3029 if (rc == 0) 3030 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3031 break; 3032 } 3033 3034 default: 3035 rc = ether_ioctl(ifp, cmd, data); 3036 } 3037 3038 return (rc); 3039 } 3040 3041 static int 3042 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 3043 { 3044 struct vi_info *vi = ifp->if_softc; 3045 struct port_info *pi = vi->pi; 3046 struct adapter *sc; 3047 struct sge_txq *txq; 3048 void *items[1]; 3049 int rc; 3050 3051 M_ASSERTPKTHDR(m); 3052 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 3053 #if defined(KERN_TLS) || defined(RATELIMIT) 3054 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) 3055 MPASS(m->m_pkthdr.snd_tag->ifp == ifp); 3056 #endif 3057 3058 if (__predict_false(pi->link_cfg.link_ok == false)) { 3059 m_freem(m); 3060 return (ENETDOWN); 3061 } 3062 3063 rc = parse_pkt(&m, vi->flags & TX_USES_VM_WR); 3064 if (__predict_false(rc != 0)) { 3065 MPASS(m == NULL); /* was freed already */ 3066 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 3067 return (rc); 3068 } 3069 #ifdef RATELIMIT 3070 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) { 3071 if (m->m_pkthdr.snd_tag->sw->type == IF_SND_TAG_TYPE_RATE_LIMIT) 3072 return (ethofld_transmit(ifp, m)); 3073 } 3074 #endif 3075 3076 /* Select a txq. */ 3077 sc = vi->adapter; 3078 txq = &sc->sge.txq[vi->first_txq]; 3079 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 3080 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 3081 vi->rsrv_noflowq); 3082 3083 items[0] = m; 3084 rc = mp_ring_enqueue(txq->r, items, 1, 256); 3085 if (__predict_false(rc != 0)) 3086 m_freem(m); 3087 3088 return (rc); 3089 } 3090 3091 static void 3092 cxgbe_qflush(struct ifnet *ifp) 3093 { 3094 struct vi_info *vi = ifp->if_softc; 3095 struct sge_txq *txq; 3096 int i; 3097 3098 /* queues do not exist if !VI_INIT_DONE. */ 3099 if (vi->flags & VI_INIT_DONE) { 3100 for_each_txq(vi, i, txq) { 3101 TXQ_LOCK(txq); 3102 txq->eq.flags |= EQ_QFLUSH; 3103 TXQ_UNLOCK(txq); 3104 while (!mp_ring_is_idle(txq->r)) { 3105 mp_ring_check_drainage(txq->r, 4096); 3106 pause("qflush", 1); 3107 } 3108 TXQ_LOCK(txq); 3109 txq->eq.flags &= ~EQ_QFLUSH; 3110 TXQ_UNLOCK(txq); 3111 } 3112 } 3113 if_qflush(ifp); 3114 } 3115 3116 static uint64_t 3117 vi_get_counter(struct ifnet *ifp, ift_counter c) 3118 { 3119 struct vi_info *vi = ifp->if_softc; 3120 struct fw_vi_stats_vf *s = &vi->stats; 3121 3122 mtx_lock(&vi->tick_mtx); 3123 vi_refresh_stats(vi); 3124 mtx_unlock(&vi->tick_mtx); 3125 3126 switch (c) { 3127 case IFCOUNTER_IPACKETS: 3128 return (s->rx_bcast_frames + s->rx_mcast_frames + 3129 s->rx_ucast_frames); 3130 case IFCOUNTER_IERRORS: 3131 return (s->rx_err_frames); 3132 case IFCOUNTER_OPACKETS: 3133 return (s->tx_bcast_frames + s->tx_mcast_frames + 3134 s->tx_ucast_frames + s->tx_offload_frames); 3135 case IFCOUNTER_OERRORS: 3136 return (s->tx_drop_frames); 3137 case IFCOUNTER_IBYTES: 3138 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 3139 s->rx_ucast_bytes); 3140 case IFCOUNTER_OBYTES: 3141 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 3142 s->tx_ucast_bytes + s->tx_offload_bytes); 3143 case IFCOUNTER_IMCASTS: 3144 return (s->rx_mcast_frames); 3145 case IFCOUNTER_OMCASTS: 3146 return (s->tx_mcast_frames); 3147 case IFCOUNTER_OQDROPS: { 3148 uint64_t drops; 3149 3150 drops = 0; 3151 if (vi->flags & VI_INIT_DONE) { 3152 int i; 3153 struct sge_txq *txq; 3154 3155 for_each_txq(vi, i, txq) 3156 drops += counter_u64_fetch(txq->r->dropped); 3157 } 3158 3159 return (drops); 3160 3161 } 3162 3163 default: 3164 return (if_get_counter_default(ifp, c)); 3165 } 3166 } 3167 3168 static uint64_t 3169 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 3170 { 3171 struct vi_info *vi = ifp->if_softc; 3172 struct port_info *pi = vi->pi; 3173 struct port_stats *s = &pi->stats; 3174 3175 mtx_lock(&vi->tick_mtx); 3176 cxgbe_refresh_stats(vi); 3177 mtx_unlock(&vi->tick_mtx); 3178 3179 switch (c) { 3180 case IFCOUNTER_IPACKETS: 3181 return (s->rx_frames); 3182 3183 case IFCOUNTER_IERRORS: 3184 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 3185 s->rx_fcs_err + s->rx_len_err); 3186 3187 case IFCOUNTER_OPACKETS: 3188 return (s->tx_frames); 3189 3190 case IFCOUNTER_OERRORS: 3191 return (s->tx_error_frames); 3192 3193 case IFCOUNTER_IBYTES: 3194 return (s->rx_octets); 3195 3196 case IFCOUNTER_OBYTES: 3197 return (s->tx_octets); 3198 3199 case IFCOUNTER_IMCASTS: 3200 return (s->rx_mcast_frames); 3201 3202 case IFCOUNTER_OMCASTS: 3203 return (s->tx_mcast_frames); 3204 3205 case IFCOUNTER_IQDROPS: 3206 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 3207 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 3208 s->rx_trunc3 + pi->tnl_cong_drops); 3209 3210 case IFCOUNTER_OQDROPS: { 3211 uint64_t drops; 3212 3213 drops = s->tx_drop; 3214 if (vi->flags & VI_INIT_DONE) { 3215 int i; 3216 struct sge_txq *txq; 3217 3218 for_each_txq(vi, i, txq) 3219 drops += counter_u64_fetch(txq->r->dropped); 3220 } 3221 3222 return (drops); 3223 3224 } 3225 3226 default: 3227 return (if_get_counter_default(ifp, c)); 3228 } 3229 } 3230 3231 #if defined(KERN_TLS) || defined(RATELIMIT) 3232 static int 3233 cxgbe_snd_tag_alloc(struct ifnet *ifp, union if_snd_tag_alloc_params *params, 3234 struct m_snd_tag **pt) 3235 { 3236 int error; 3237 3238 switch (params->hdr.type) { 3239 #ifdef RATELIMIT 3240 case IF_SND_TAG_TYPE_RATE_LIMIT: 3241 error = cxgbe_rate_tag_alloc(ifp, params, pt); 3242 break; 3243 #endif 3244 #ifdef KERN_TLS 3245 case IF_SND_TAG_TYPE_TLS: 3246 { 3247 struct vi_info *vi = ifp->if_softc; 3248 3249 if (is_t6(vi->pi->adapter)) 3250 error = t6_tls_tag_alloc(ifp, params, pt); 3251 else 3252 error = EOPNOTSUPP; 3253 break; 3254 } 3255 #endif 3256 default: 3257 error = EOPNOTSUPP; 3258 } 3259 return (error); 3260 } 3261 #endif 3262 3263 /* 3264 * The kernel picks a media from the list we had provided but we still validate 3265 * the requeste. 3266 */ 3267 int 3268 cxgbe_media_change(struct ifnet *ifp) 3269 { 3270 struct vi_info *vi = ifp->if_softc; 3271 struct port_info *pi = vi->pi; 3272 struct ifmedia *ifm = &pi->media; 3273 struct link_config *lc = &pi->link_cfg; 3274 struct adapter *sc = pi->adapter; 3275 int rc; 3276 3277 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 3278 if (rc != 0) 3279 return (rc); 3280 PORT_LOCK(pi); 3281 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 3282 /* ifconfig .. media autoselect */ 3283 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) { 3284 rc = ENOTSUP; /* AN not supported by transceiver */ 3285 goto done; 3286 } 3287 lc->requested_aneg = AUTONEG_ENABLE; 3288 lc->requested_speed = 0; 3289 lc->requested_fc |= PAUSE_AUTONEG; 3290 } else { 3291 lc->requested_aneg = AUTONEG_DISABLE; 3292 lc->requested_speed = 3293 ifmedia_baudrate(ifm->ifm_media) / 1000000; 3294 lc->requested_fc = 0; 3295 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 3296 lc->requested_fc |= PAUSE_RX; 3297 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 3298 lc->requested_fc |= PAUSE_TX; 3299 } 3300 if (pi->up_vis > 0 && !hw_off_limits(sc)) { 3301 fixup_link_config(pi); 3302 rc = apply_link_config(pi); 3303 } 3304 done: 3305 PORT_UNLOCK(pi); 3306 end_synchronized_op(sc, 0); 3307 return (rc); 3308 } 3309 3310 /* 3311 * Base media word (without ETHER, pause, link active, etc.) for the port at the 3312 * given speed. 3313 */ 3314 static int 3315 port_mword(struct port_info *pi, uint32_t speed) 3316 { 3317 3318 MPASS(speed & M_FW_PORT_CAP32_SPEED); 3319 MPASS(powerof2(speed)); 3320 3321 switch(pi->port_type) { 3322 case FW_PORT_TYPE_BT_SGMII: 3323 case FW_PORT_TYPE_BT_XFI: 3324 case FW_PORT_TYPE_BT_XAUI: 3325 /* BaseT */ 3326 switch (speed) { 3327 case FW_PORT_CAP32_SPEED_100M: 3328 return (IFM_100_T); 3329 case FW_PORT_CAP32_SPEED_1G: 3330 return (IFM_1000_T); 3331 case FW_PORT_CAP32_SPEED_10G: 3332 return (IFM_10G_T); 3333 } 3334 break; 3335 case FW_PORT_TYPE_KX4: 3336 if (speed == FW_PORT_CAP32_SPEED_10G) 3337 return (IFM_10G_KX4); 3338 break; 3339 case FW_PORT_TYPE_CX4: 3340 if (speed == FW_PORT_CAP32_SPEED_10G) 3341 return (IFM_10G_CX4); 3342 break; 3343 case FW_PORT_TYPE_KX: 3344 if (speed == FW_PORT_CAP32_SPEED_1G) 3345 return (IFM_1000_KX); 3346 break; 3347 case FW_PORT_TYPE_KR: 3348 case FW_PORT_TYPE_BP_AP: 3349 case FW_PORT_TYPE_BP4_AP: 3350 case FW_PORT_TYPE_BP40_BA: 3351 case FW_PORT_TYPE_KR4_100G: 3352 case FW_PORT_TYPE_KR_SFP28: 3353 case FW_PORT_TYPE_KR_XLAUI: 3354 switch (speed) { 3355 case FW_PORT_CAP32_SPEED_1G: 3356 return (IFM_1000_KX); 3357 case FW_PORT_CAP32_SPEED_10G: 3358 return (IFM_10G_KR); 3359 case FW_PORT_CAP32_SPEED_25G: 3360 return (IFM_25G_KR); 3361 case FW_PORT_CAP32_SPEED_40G: 3362 return (IFM_40G_KR4); 3363 case FW_PORT_CAP32_SPEED_50G: 3364 return (IFM_50G_KR2); 3365 case FW_PORT_CAP32_SPEED_100G: 3366 return (IFM_100G_KR4); 3367 } 3368 break; 3369 case FW_PORT_TYPE_FIBER_XFI: 3370 case FW_PORT_TYPE_FIBER_XAUI: 3371 case FW_PORT_TYPE_SFP: 3372 case FW_PORT_TYPE_QSFP_10G: 3373 case FW_PORT_TYPE_QSA: 3374 case FW_PORT_TYPE_QSFP: 3375 case FW_PORT_TYPE_CR4_QSFP: 3376 case FW_PORT_TYPE_CR_QSFP: 3377 case FW_PORT_TYPE_CR2_QSFP: 3378 case FW_PORT_TYPE_SFP28: 3379 /* Pluggable transceiver */ 3380 switch (pi->mod_type) { 3381 case FW_PORT_MOD_TYPE_LR: 3382 switch (speed) { 3383 case FW_PORT_CAP32_SPEED_1G: 3384 return (IFM_1000_LX); 3385 case FW_PORT_CAP32_SPEED_10G: 3386 return (IFM_10G_LR); 3387 case FW_PORT_CAP32_SPEED_25G: 3388 return (IFM_25G_LR); 3389 case FW_PORT_CAP32_SPEED_40G: 3390 return (IFM_40G_LR4); 3391 case FW_PORT_CAP32_SPEED_50G: 3392 return (IFM_50G_LR2); 3393 case FW_PORT_CAP32_SPEED_100G: 3394 return (IFM_100G_LR4); 3395 } 3396 break; 3397 case FW_PORT_MOD_TYPE_SR: 3398 switch (speed) { 3399 case FW_PORT_CAP32_SPEED_1G: 3400 return (IFM_1000_SX); 3401 case FW_PORT_CAP32_SPEED_10G: 3402 return (IFM_10G_SR); 3403 case FW_PORT_CAP32_SPEED_25G: 3404 return (IFM_25G_SR); 3405 case FW_PORT_CAP32_SPEED_40G: 3406 return (IFM_40G_SR4); 3407 case FW_PORT_CAP32_SPEED_50G: 3408 return (IFM_50G_SR2); 3409 case FW_PORT_CAP32_SPEED_100G: 3410 return (IFM_100G_SR4); 3411 } 3412 break; 3413 case FW_PORT_MOD_TYPE_ER: 3414 if (speed == FW_PORT_CAP32_SPEED_10G) 3415 return (IFM_10G_ER); 3416 break; 3417 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3418 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3419 switch (speed) { 3420 case FW_PORT_CAP32_SPEED_1G: 3421 return (IFM_1000_CX); 3422 case FW_PORT_CAP32_SPEED_10G: 3423 return (IFM_10G_TWINAX); 3424 case FW_PORT_CAP32_SPEED_25G: 3425 return (IFM_25G_CR); 3426 case FW_PORT_CAP32_SPEED_40G: 3427 return (IFM_40G_CR4); 3428 case FW_PORT_CAP32_SPEED_50G: 3429 return (IFM_50G_CR2); 3430 case FW_PORT_CAP32_SPEED_100G: 3431 return (IFM_100G_CR4); 3432 } 3433 break; 3434 case FW_PORT_MOD_TYPE_LRM: 3435 if (speed == FW_PORT_CAP32_SPEED_10G) 3436 return (IFM_10G_LRM); 3437 break; 3438 case FW_PORT_MOD_TYPE_NA: 3439 MPASS(0); /* Not pluggable? */ 3440 /* fall throough */ 3441 case FW_PORT_MOD_TYPE_ERROR: 3442 case FW_PORT_MOD_TYPE_UNKNOWN: 3443 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 3444 break; 3445 case FW_PORT_MOD_TYPE_NONE: 3446 return (IFM_NONE); 3447 } 3448 break; 3449 case FW_PORT_TYPE_NONE: 3450 return (IFM_NONE); 3451 } 3452 3453 return (IFM_UNKNOWN); 3454 } 3455 3456 void 3457 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 3458 { 3459 struct vi_info *vi = ifp->if_softc; 3460 struct port_info *pi = vi->pi; 3461 struct adapter *sc = pi->adapter; 3462 struct link_config *lc = &pi->link_cfg; 3463 3464 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0) 3465 return; 3466 PORT_LOCK(pi); 3467 3468 if (pi->up_vis == 0 && !hw_off_limits(sc)) { 3469 /* 3470 * If all the interfaces are administratively down the firmware 3471 * does not report transceiver changes. Refresh port info here 3472 * so that ifconfig displays accurate ifmedia at all times. 3473 * This is the only reason we have a synchronized op in this 3474 * function. Just PORT_LOCK would have been enough otherwise. 3475 */ 3476 t4_update_port_info(pi); 3477 build_medialist(pi); 3478 } 3479 3480 /* ifm_status */ 3481 ifmr->ifm_status = IFM_AVALID; 3482 if (lc->link_ok == false) 3483 goto done; 3484 ifmr->ifm_status |= IFM_ACTIVE; 3485 3486 /* ifm_active */ 3487 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 3488 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 3489 if (lc->fc & PAUSE_RX) 3490 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 3491 if (lc->fc & PAUSE_TX) 3492 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 3493 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 3494 done: 3495 PORT_UNLOCK(pi); 3496 end_synchronized_op(sc, 0); 3497 } 3498 3499 static int 3500 vcxgbe_probe(device_t dev) 3501 { 3502 char buf[128]; 3503 struct vi_info *vi = device_get_softc(dev); 3504 3505 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 3506 vi - vi->pi->vi); 3507 device_set_desc_copy(dev, buf); 3508 3509 return (BUS_PROBE_DEFAULT); 3510 } 3511 3512 static int 3513 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 3514 { 3515 int func, index, rc; 3516 uint32_t param, val; 3517 3518 ASSERT_SYNCHRONIZED_OP(sc); 3519 3520 index = vi - pi->vi; 3521 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 3522 KASSERT(index < nitems(vi_mac_funcs), 3523 ("%s: VI %s doesn't have a MAC func", __func__, 3524 device_get_nameunit(vi->dev))); 3525 func = vi_mac_funcs[index]; 3526 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 3527 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 3528 if (rc < 0) { 3529 CH_ERR(vi, "failed to allocate virtual interface %d" 3530 "for port %d: %d\n", index, pi->port_id, -rc); 3531 return (-rc); 3532 } 3533 vi->viid = rc; 3534 3535 if (vi->rss_size == 1) { 3536 /* 3537 * This VI didn't get a slice of the RSS table. Reduce the 3538 * number of VIs being created (hw.cxgbe.num_vis) or modify the 3539 * configuration file (nvi, rssnvi for this PF) if this is a 3540 * problem. 3541 */ 3542 device_printf(vi->dev, "RSS table not available.\n"); 3543 vi->rss_base = 0xffff; 3544 3545 return (0); 3546 } 3547 3548 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3549 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 3550 V_FW_PARAMS_PARAM_YZ(vi->viid); 3551 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3552 if (rc) 3553 vi->rss_base = 0xffff; 3554 else { 3555 MPASS((val >> 16) == vi->rss_size); 3556 vi->rss_base = val & 0xffff; 3557 } 3558 3559 return (0); 3560 } 3561 3562 static int 3563 vcxgbe_attach(device_t dev) 3564 { 3565 struct vi_info *vi; 3566 struct port_info *pi; 3567 struct adapter *sc; 3568 int rc; 3569 3570 vi = device_get_softc(dev); 3571 pi = vi->pi; 3572 sc = pi->adapter; 3573 3574 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 3575 if (rc) 3576 return (rc); 3577 rc = alloc_extra_vi(sc, pi, vi); 3578 end_synchronized_op(sc, 0); 3579 if (rc) 3580 return (rc); 3581 3582 rc = cxgbe_vi_attach(dev, vi); 3583 if (rc) { 3584 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 3585 return (rc); 3586 } 3587 return (0); 3588 } 3589 3590 static int 3591 vcxgbe_detach(device_t dev) 3592 { 3593 struct vi_info *vi; 3594 struct adapter *sc; 3595 3596 vi = device_get_softc(dev); 3597 sc = vi->adapter; 3598 3599 doom_vi(sc, vi); 3600 3601 cxgbe_vi_detach(vi); 3602 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 3603 3604 end_synchronized_op(sc, 0); 3605 3606 return (0); 3607 } 3608 3609 static struct callout fatal_callout; 3610 static struct taskqueue *reset_tq; 3611 3612 static void 3613 delayed_panic(void *arg) 3614 { 3615 struct adapter *sc = arg; 3616 3617 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 3618 } 3619 3620 static void 3621 fatal_error_task(void *arg, int pending) 3622 { 3623 struct adapter *sc = arg; 3624 int rc; 3625 3626 #ifdef TCP_OFFLOAD 3627 t4_async_event(sc); 3628 #endif 3629 if (atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_CIM_ERR))) { 3630 dump_cim_regs(sc); 3631 dump_cimla(sc); 3632 dump_devlog(sc); 3633 } 3634 3635 if (t4_reset_on_fatal_err) { 3636 CH_ALERT(sc, "resetting on fatal error.\n"); 3637 rc = reset_adapter(sc); 3638 if (rc == 0 && t4_panic_on_fatal_err) { 3639 CH_ALERT(sc, "reset was successful, " 3640 "system will NOT panic.\n"); 3641 return; 3642 } 3643 } 3644 3645 if (t4_panic_on_fatal_err) { 3646 CH_ALERT(sc, "panicking on fatal error (after 30s).\n"); 3647 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 3648 } 3649 } 3650 3651 void 3652 t4_fatal_err(struct adapter *sc, bool fw_error) 3653 { 3654 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 3655 3656 stop_adapter(sc); 3657 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_FATAL_ERR))) 3658 return; 3659 if (fw_error) { 3660 /* 3661 * We are here because of a firmware error/timeout and not 3662 * because of a hardware interrupt. It is possible (although 3663 * not very likely) that an error interrupt was also raised but 3664 * this thread ran first and inhibited t4_intr_err. We walk the 3665 * main INT_CAUSE registers here to make sure we haven't missed 3666 * anything interesting. 3667 */ 3668 t4_slow_intr_handler(sc, verbose); 3669 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 3670 } 3671 t4_report_fw_error(sc); 3672 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped (%d).\n", 3673 device_get_nameunit(sc->dev), fw_error); 3674 taskqueue_enqueue(reset_tq, &sc->fatal_error_task); 3675 } 3676 3677 void 3678 t4_add_adapter(struct adapter *sc) 3679 { 3680 sx_xlock(&t4_list_lock); 3681 SLIST_INSERT_HEAD(&t4_list, sc, link); 3682 sx_xunlock(&t4_list_lock); 3683 } 3684 3685 int 3686 t4_map_bars_0_and_4(struct adapter *sc) 3687 { 3688 sc->regs_rid = PCIR_BAR(0); 3689 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3690 &sc->regs_rid, RF_ACTIVE); 3691 if (sc->regs_res == NULL) { 3692 device_printf(sc->dev, "cannot map registers.\n"); 3693 return (ENXIO); 3694 } 3695 sc->bt = rman_get_bustag(sc->regs_res); 3696 sc->bh = rman_get_bushandle(sc->regs_res); 3697 sc->mmio_len = rman_get_size(sc->regs_res); 3698 setbit(&sc->doorbells, DOORBELL_KDB); 3699 3700 sc->msix_rid = PCIR_BAR(4); 3701 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3702 &sc->msix_rid, RF_ACTIVE); 3703 if (sc->msix_res == NULL) { 3704 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 3705 return (ENXIO); 3706 } 3707 3708 return (0); 3709 } 3710 3711 int 3712 t4_map_bar_2(struct adapter *sc) 3713 { 3714 3715 /* 3716 * T4: only iWARP driver uses the userspace doorbells. There is no need 3717 * to map it if RDMA is disabled. 3718 */ 3719 if (is_t4(sc) && sc->rdmacaps == 0) 3720 return (0); 3721 3722 sc->udbs_rid = PCIR_BAR(2); 3723 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 3724 &sc->udbs_rid, RF_ACTIVE); 3725 if (sc->udbs_res == NULL) { 3726 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 3727 return (ENXIO); 3728 } 3729 sc->udbs_base = rman_get_virtual(sc->udbs_res); 3730 3731 if (chip_id(sc) >= CHELSIO_T5) { 3732 setbit(&sc->doorbells, DOORBELL_UDB); 3733 #if defined(__i386__) || defined(__amd64__) 3734 if (t5_write_combine) { 3735 int rc, mode; 3736 3737 /* 3738 * Enable write combining on BAR2. This is the 3739 * userspace doorbell BAR and is split into 128B 3740 * (UDBS_SEG_SIZE) doorbell regions, each associated 3741 * with an egress queue. The first 64B has the doorbell 3742 * and the second 64B can be used to submit a tx work 3743 * request with an implicit doorbell. 3744 */ 3745 3746 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 3747 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 3748 if (rc == 0) { 3749 clrbit(&sc->doorbells, DOORBELL_UDB); 3750 setbit(&sc->doorbells, DOORBELL_WCWR); 3751 setbit(&sc->doorbells, DOORBELL_UDBWC); 3752 } else { 3753 device_printf(sc->dev, 3754 "couldn't enable write combining: %d\n", 3755 rc); 3756 } 3757 3758 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 3759 t4_write_reg(sc, A_SGE_STAT_CFG, 3760 V_STATSOURCE_T5(7) | mode); 3761 } 3762 #endif 3763 } 3764 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 3765 3766 return (0); 3767 } 3768 3769 struct memwin_init { 3770 uint32_t base; 3771 uint32_t aperture; 3772 }; 3773 3774 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 3775 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3776 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3777 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 3778 }; 3779 3780 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 3781 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 3782 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 3783 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 3784 }; 3785 3786 static void 3787 setup_memwin(struct adapter *sc) 3788 { 3789 const struct memwin_init *mw_init; 3790 struct memwin *mw; 3791 int i; 3792 uint32_t bar0; 3793 3794 if (is_t4(sc)) { 3795 /* 3796 * Read low 32b of bar0 indirectly via the hardware backdoor 3797 * mechanism. Works from within PCI passthrough environments 3798 * too, where rman_get_start() can return a different value. We 3799 * need to program the T4 memory window decoders with the actual 3800 * addresses that will be coming across the PCIe link. 3801 */ 3802 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 3803 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 3804 3805 mw_init = &t4_memwin[0]; 3806 } else { 3807 /* T5+ use the relative offset inside the PCIe BAR */ 3808 bar0 = 0; 3809 3810 mw_init = &t5_memwin[0]; 3811 } 3812 3813 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 3814 if (!rw_initialized(&mw->mw_lock)) { 3815 rw_init(&mw->mw_lock, "memory window access"); 3816 mw->mw_base = mw_init->base; 3817 mw->mw_aperture = mw_init->aperture; 3818 mw->mw_curpos = 0; 3819 } 3820 t4_write_reg(sc, 3821 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 3822 (mw->mw_base + bar0) | V_BIR(0) | 3823 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 3824 rw_wlock(&mw->mw_lock); 3825 position_memwin(sc, i, mw->mw_curpos); 3826 rw_wunlock(&mw->mw_lock); 3827 } 3828 3829 /* flush */ 3830 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 3831 } 3832 3833 /* 3834 * Positions the memory window at the given address in the card's address space. 3835 * There are some alignment requirements and the actual position may be at an 3836 * address prior to the requested address. mw->mw_curpos always has the actual 3837 * position of the window. 3838 */ 3839 static void 3840 position_memwin(struct adapter *sc, int idx, uint32_t addr) 3841 { 3842 struct memwin *mw; 3843 uint32_t pf; 3844 uint32_t reg; 3845 3846 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3847 mw = &sc->memwin[idx]; 3848 rw_assert(&mw->mw_lock, RA_WLOCKED); 3849 3850 if (is_t4(sc)) { 3851 pf = 0; 3852 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 3853 } else { 3854 pf = V_PFNUM(sc->pf); 3855 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 3856 } 3857 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 3858 t4_write_reg(sc, reg, mw->mw_curpos | pf); 3859 t4_read_reg(sc, reg); /* flush */ 3860 } 3861 3862 int 3863 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 3864 int len, int rw) 3865 { 3866 struct memwin *mw; 3867 uint32_t mw_end, v; 3868 3869 MPASS(idx >= 0 && idx < NUM_MEMWIN); 3870 3871 /* Memory can only be accessed in naturally aligned 4 byte units */ 3872 if (addr & 3 || len & 3 || len <= 0) 3873 return (EINVAL); 3874 3875 mw = &sc->memwin[idx]; 3876 while (len > 0) { 3877 rw_rlock(&mw->mw_lock); 3878 mw_end = mw->mw_curpos + mw->mw_aperture; 3879 if (addr >= mw_end || addr < mw->mw_curpos) { 3880 /* Will need to reposition the window */ 3881 if (!rw_try_upgrade(&mw->mw_lock)) { 3882 rw_runlock(&mw->mw_lock); 3883 rw_wlock(&mw->mw_lock); 3884 } 3885 rw_assert(&mw->mw_lock, RA_WLOCKED); 3886 position_memwin(sc, idx, addr); 3887 rw_downgrade(&mw->mw_lock); 3888 mw_end = mw->mw_curpos + mw->mw_aperture; 3889 } 3890 rw_assert(&mw->mw_lock, RA_RLOCKED); 3891 while (addr < mw_end && len > 0) { 3892 if (rw == 0) { 3893 v = t4_read_reg(sc, mw->mw_base + addr - 3894 mw->mw_curpos); 3895 *val++ = le32toh(v); 3896 } else { 3897 v = *val++; 3898 t4_write_reg(sc, mw->mw_base + addr - 3899 mw->mw_curpos, htole32(v)); 3900 } 3901 addr += 4; 3902 len -= 4; 3903 } 3904 rw_runlock(&mw->mw_lock); 3905 } 3906 3907 return (0); 3908 } 3909 3910 static void 3911 t4_init_atid_table(struct adapter *sc) 3912 { 3913 struct tid_info *t; 3914 int i; 3915 3916 t = &sc->tids; 3917 if (t->natids == 0) 3918 return; 3919 3920 MPASS(t->atid_tab == NULL); 3921 3922 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 3923 M_ZERO | M_WAITOK); 3924 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 3925 t->afree = t->atid_tab; 3926 t->atids_in_use = 0; 3927 for (i = 1; i < t->natids; i++) 3928 t->atid_tab[i - 1].next = &t->atid_tab[i]; 3929 t->atid_tab[t->natids - 1].next = NULL; 3930 } 3931 3932 static void 3933 t4_free_atid_table(struct adapter *sc) 3934 { 3935 struct tid_info *t; 3936 3937 t = &sc->tids; 3938 3939 KASSERT(t->atids_in_use == 0, 3940 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 3941 3942 if (mtx_initialized(&t->atid_lock)) 3943 mtx_destroy(&t->atid_lock); 3944 free(t->atid_tab, M_CXGBE); 3945 t->atid_tab = NULL; 3946 } 3947 3948 int 3949 alloc_atid(struct adapter *sc, void *ctx) 3950 { 3951 struct tid_info *t = &sc->tids; 3952 int atid = -1; 3953 3954 mtx_lock(&t->atid_lock); 3955 if (t->afree) { 3956 union aopen_entry *p = t->afree; 3957 3958 atid = p - t->atid_tab; 3959 MPASS(atid <= M_TID_TID); 3960 t->afree = p->next; 3961 p->data = ctx; 3962 t->atids_in_use++; 3963 } 3964 mtx_unlock(&t->atid_lock); 3965 return (atid); 3966 } 3967 3968 void * 3969 lookup_atid(struct adapter *sc, int atid) 3970 { 3971 struct tid_info *t = &sc->tids; 3972 3973 return (t->atid_tab[atid].data); 3974 } 3975 3976 void 3977 free_atid(struct adapter *sc, int atid) 3978 { 3979 struct tid_info *t = &sc->tids; 3980 union aopen_entry *p = &t->atid_tab[atid]; 3981 3982 mtx_lock(&t->atid_lock); 3983 p->next = t->afree; 3984 t->afree = p; 3985 t->atids_in_use--; 3986 mtx_unlock(&t->atid_lock); 3987 } 3988 3989 static void 3990 queue_tid_release(struct adapter *sc, int tid) 3991 { 3992 3993 CXGBE_UNIMPLEMENTED("deferred tid release"); 3994 } 3995 3996 void 3997 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 3998 { 3999 struct wrqe *wr; 4000 struct cpl_tid_release *req; 4001 4002 wr = alloc_wrqe(sizeof(*req), ctrlq); 4003 if (wr == NULL) { 4004 queue_tid_release(sc, tid); /* defer */ 4005 return; 4006 } 4007 req = wrtod(wr); 4008 4009 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 4010 4011 t4_wrq_tx(sc, wr); 4012 } 4013 4014 static int 4015 t4_range_cmp(const void *a, const void *b) 4016 { 4017 return ((const struct t4_range *)a)->start - 4018 ((const struct t4_range *)b)->start; 4019 } 4020 4021 /* 4022 * Verify that the memory range specified by the addr/len pair is valid within 4023 * the card's address space. 4024 */ 4025 static int 4026 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 4027 { 4028 struct t4_range mem_ranges[4], *r, *next; 4029 uint32_t em, addr_len; 4030 int i, n, remaining; 4031 4032 /* Memory can only be accessed in naturally aligned 4 byte units */ 4033 if (addr & 3 || len & 3 || len == 0) 4034 return (EINVAL); 4035 4036 /* Enabled memories */ 4037 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4038 4039 r = &mem_ranges[0]; 4040 n = 0; 4041 bzero(r, sizeof(mem_ranges)); 4042 if (em & F_EDRAM0_ENABLE) { 4043 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4044 r->size = G_EDRAM0_SIZE(addr_len) << 20; 4045 if (r->size > 0) { 4046 r->start = G_EDRAM0_BASE(addr_len) << 20; 4047 if (addr >= r->start && 4048 addr + len <= r->start + r->size) 4049 return (0); 4050 r++; 4051 n++; 4052 } 4053 } 4054 if (em & F_EDRAM1_ENABLE) { 4055 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4056 r->size = G_EDRAM1_SIZE(addr_len) << 20; 4057 if (r->size > 0) { 4058 r->start = G_EDRAM1_BASE(addr_len) << 20; 4059 if (addr >= r->start && 4060 addr + len <= r->start + r->size) 4061 return (0); 4062 r++; 4063 n++; 4064 } 4065 } 4066 if (em & F_EXT_MEM_ENABLE) { 4067 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4068 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 4069 if (r->size > 0) { 4070 r->start = G_EXT_MEM_BASE(addr_len) << 20; 4071 if (addr >= r->start && 4072 addr + len <= r->start + r->size) 4073 return (0); 4074 r++; 4075 n++; 4076 } 4077 } 4078 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 4079 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4080 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 4081 if (r->size > 0) { 4082 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 4083 if (addr >= r->start && 4084 addr + len <= r->start + r->size) 4085 return (0); 4086 r++; 4087 n++; 4088 } 4089 } 4090 MPASS(n <= nitems(mem_ranges)); 4091 4092 if (n > 1) { 4093 /* Sort and merge the ranges. */ 4094 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 4095 4096 /* Start from index 0 and examine the next n - 1 entries. */ 4097 r = &mem_ranges[0]; 4098 for (remaining = n - 1; remaining > 0; remaining--, r++) { 4099 4100 MPASS(r->size > 0); /* r is a valid entry. */ 4101 next = r + 1; 4102 MPASS(next->size > 0); /* and so is the next one. */ 4103 4104 while (r->start + r->size >= next->start) { 4105 /* Merge the next one into the current entry. */ 4106 r->size = max(r->start + r->size, 4107 next->start + next->size) - r->start; 4108 n--; /* One fewer entry in total. */ 4109 if (--remaining == 0) 4110 goto done; /* short circuit */ 4111 next++; 4112 } 4113 if (next != r + 1) { 4114 /* 4115 * Some entries were merged into r and next 4116 * points to the first valid entry that couldn't 4117 * be merged. 4118 */ 4119 MPASS(next->size > 0); /* must be valid */ 4120 memcpy(r + 1, next, remaining * sizeof(*r)); 4121 #ifdef INVARIANTS 4122 /* 4123 * This so that the foo->size assertion in the 4124 * next iteration of the loop do the right 4125 * thing for entries that were pulled up and are 4126 * no longer valid. 4127 */ 4128 MPASS(n < nitems(mem_ranges)); 4129 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 4130 sizeof(struct t4_range)); 4131 #endif 4132 } 4133 } 4134 done: 4135 /* Done merging the ranges. */ 4136 MPASS(n > 0); 4137 r = &mem_ranges[0]; 4138 for (i = 0; i < n; i++, r++) { 4139 if (addr >= r->start && 4140 addr + len <= r->start + r->size) 4141 return (0); 4142 } 4143 } 4144 4145 return (EFAULT); 4146 } 4147 4148 static int 4149 fwmtype_to_hwmtype(int mtype) 4150 { 4151 4152 switch (mtype) { 4153 case FW_MEMTYPE_EDC0: 4154 return (MEM_EDC0); 4155 case FW_MEMTYPE_EDC1: 4156 return (MEM_EDC1); 4157 case FW_MEMTYPE_EXTMEM: 4158 return (MEM_MC0); 4159 case FW_MEMTYPE_EXTMEM1: 4160 return (MEM_MC1); 4161 default: 4162 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 4163 } 4164 } 4165 4166 /* 4167 * Verify that the memory range specified by the memtype/offset/len pair is 4168 * valid and lies entirely within the memtype specified. The global address of 4169 * the start of the range is returned in addr. 4170 */ 4171 static int 4172 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 4173 uint32_t *addr) 4174 { 4175 uint32_t em, addr_len, maddr; 4176 4177 /* Memory can only be accessed in naturally aligned 4 byte units */ 4178 if (off & 3 || len & 3 || len == 0) 4179 return (EINVAL); 4180 4181 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 4182 switch (fwmtype_to_hwmtype(mtype)) { 4183 case MEM_EDC0: 4184 if (!(em & F_EDRAM0_ENABLE)) 4185 return (EINVAL); 4186 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 4187 maddr = G_EDRAM0_BASE(addr_len) << 20; 4188 break; 4189 case MEM_EDC1: 4190 if (!(em & F_EDRAM1_ENABLE)) 4191 return (EINVAL); 4192 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 4193 maddr = G_EDRAM1_BASE(addr_len) << 20; 4194 break; 4195 case MEM_MC: 4196 if (!(em & F_EXT_MEM_ENABLE)) 4197 return (EINVAL); 4198 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 4199 maddr = G_EXT_MEM_BASE(addr_len) << 20; 4200 break; 4201 case MEM_MC1: 4202 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 4203 return (EINVAL); 4204 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 4205 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 4206 break; 4207 default: 4208 return (EINVAL); 4209 } 4210 4211 *addr = maddr + off; /* global address */ 4212 return (validate_mem_range(sc, *addr, len)); 4213 } 4214 4215 static int 4216 fixup_devlog_params(struct adapter *sc) 4217 { 4218 struct devlog_params *dparams = &sc->params.devlog; 4219 int rc; 4220 4221 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 4222 dparams->size, &dparams->addr); 4223 4224 return (rc); 4225 } 4226 4227 static void 4228 update_nirq(struct intrs_and_queues *iaq, int nports) 4229 { 4230 4231 iaq->nirq = T4_EXTRA_INTR; 4232 iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq); 4233 iaq->nirq += nports * iaq->nofldrxq; 4234 iaq->nirq += nports * (iaq->num_vis - 1) * 4235 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 4236 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 4237 } 4238 4239 /* 4240 * Adjust requirements to fit the number of interrupts available. 4241 */ 4242 static void 4243 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 4244 int navail) 4245 { 4246 int old_nirq; 4247 const int nports = sc->params.nports; 4248 4249 MPASS(nports > 0); 4250 MPASS(navail > 0); 4251 4252 bzero(iaq, sizeof(*iaq)); 4253 iaq->intr_type = itype; 4254 iaq->num_vis = t4_num_vis; 4255 iaq->ntxq = t4_ntxq; 4256 iaq->ntxq_vi = t4_ntxq_vi; 4257 iaq->nrxq = t4_nrxq; 4258 iaq->nrxq_vi = t4_nrxq_vi; 4259 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4260 if (is_offload(sc) || is_ethoffload(sc)) { 4261 iaq->nofldtxq = t4_nofldtxq; 4262 iaq->nofldtxq_vi = t4_nofldtxq_vi; 4263 } 4264 #endif 4265 #ifdef TCP_OFFLOAD 4266 if (is_offload(sc)) { 4267 iaq->nofldrxq = t4_nofldrxq; 4268 iaq->nofldrxq_vi = t4_nofldrxq_vi; 4269 } 4270 #endif 4271 #ifdef DEV_NETMAP 4272 if (t4_native_netmap & NN_MAIN_VI) { 4273 iaq->nnmtxq = t4_nnmtxq; 4274 iaq->nnmrxq = t4_nnmrxq; 4275 } 4276 if (t4_native_netmap & NN_EXTRA_VI) { 4277 iaq->nnmtxq_vi = t4_nnmtxq_vi; 4278 iaq->nnmrxq_vi = t4_nnmrxq_vi; 4279 } 4280 #endif 4281 4282 update_nirq(iaq, nports); 4283 if (iaq->nirq <= navail && 4284 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4285 /* 4286 * This is the normal case -- there are enough interrupts for 4287 * everything. 4288 */ 4289 goto done; 4290 } 4291 4292 /* 4293 * If extra VIs have been configured try reducing their count and see if 4294 * that works. 4295 */ 4296 while (iaq->num_vis > 1) { 4297 iaq->num_vis--; 4298 update_nirq(iaq, nports); 4299 if (iaq->nirq <= navail && 4300 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4301 device_printf(sc->dev, "virtual interfaces per port " 4302 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 4303 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 4304 "itype %d, navail %u, nirq %d.\n", 4305 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 4306 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 4307 itype, navail, iaq->nirq); 4308 goto done; 4309 } 4310 } 4311 4312 /* 4313 * Extra VIs will not be created. Log a message if they were requested. 4314 */ 4315 MPASS(iaq->num_vis == 1); 4316 iaq->ntxq_vi = iaq->nrxq_vi = 0; 4317 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 4318 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 4319 if (iaq->num_vis != t4_num_vis) { 4320 device_printf(sc->dev, "extra virtual interfaces disabled. " 4321 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 4322 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 4323 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 4324 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 4325 } 4326 4327 /* 4328 * Keep reducing the number of NIC rx queues to the next lower power of 4329 * 2 (for even RSS distribution) and halving the TOE rx queues and see 4330 * if that works. 4331 */ 4332 do { 4333 if (iaq->nrxq > 1) { 4334 do { 4335 iaq->nrxq--; 4336 } while (!powerof2(iaq->nrxq)); 4337 if (iaq->nnmrxq > iaq->nrxq) 4338 iaq->nnmrxq = iaq->nrxq; 4339 } 4340 if (iaq->nofldrxq > 1) 4341 iaq->nofldrxq >>= 1; 4342 4343 old_nirq = iaq->nirq; 4344 update_nirq(iaq, nports); 4345 if (iaq->nirq <= navail && 4346 (itype != INTR_MSI || powerof2(iaq->nirq))) { 4347 device_printf(sc->dev, "running with reduced number of " 4348 "rx queues because of shortage of interrupts. " 4349 "nrxq=%u, nofldrxq=%u. " 4350 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 4351 iaq->nofldrxq, itype, navail, iaq->nirq); 4352 goto done; 4353 } 4354 } while (old_nirq != iaq->nirq); 4355 4356 /* One interrupt for everything. Ugh. */ 4357 device_printf(sc->dev, "running with minimal number of queues. " 4358 "itype %d, navail %u.\n", itype, navail); 4359 iaq->nirq = 1; 4360 iaq->nrxq = 1; 4361 iaq->ntxq = 1; 4362 if (iaq->nofldrxq > 0) { 4363 iaq->nofldrxq = 1; 4364 iaq->nofldtxq = 1; 4365 } 4366 iaq->nnmtxq = 0; 4367 iaq->nnmrxq = 0; 4368 done: 4369 MPASS(iaq->num_vis > 0); 4370 if (iaq->num_vis > 1) { 4371 MPASS(iaq->nrxq_vi > 0); 4372 MPASS(iaq->ntxq_vi > 0); 4373 } 4374 MPASS(iaq->nirq > 0); 4375 MPASS(iaq->nrxq > 0); 4376 MPASS(iaq->ntxq > 0); 4377 if (itype == INTR_MSI) { 4378 MPASS(powerof2(iaq->nirq)); 4379 } 4380 } 4381 4382 static int 4383 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 4384 { 4385 int rc, itype, navail, nalloc; 4386 4387 for (itype = INTR_MSIX; itype; itype >>= 1) { 4388 4389 if ((itype & t4_intr_types) == 0) 4390 continue; /* not allowed */ 4391 4392 if (itype == INTR_MSIX) 4393 navail = pci_msix_count(sc->dev); 4394 else if (itype == INTR_MSI) 4395 navail = pci_msi_count(sc->dev); 4396 else 4397 navail = 1; 4398 restart: 4399 if (navail == 0) 4400 continue; 4401 4402 calculate_iaq(sc, iaq, itype, navail); 4403 nalloc = iaq->nirq; 4404 rc = 0; 4405 if (itype == INTR_MSIX) 4406 rc = pci_alloc_msix(sc->dev, &nalloc); 4407 else if (itype == INTR_MSI) 4408 rc = pci_alloc_msi(sc->dev, &nalloc); 4409 4410 if (rc == 0 && nalloc > 0) { 4411 if (nalloc == iaq->nirq) 4412 return (0); 4413 4414 /* 4415 * Didn't get the number requested. Use whatever number 4416 * the kernel is willing to allocate. 4417 */ 4418 device_printf(sc->dev, "fewer vectors than requested, " 4419 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 4420 itype, iaq->nirq, nalloc); 4421 pci_release_msi(sc->dev); 4422 navail = nalloc; 4423 goto restart; 4424 } 4425 4426 device_printf(sc->dev, 4427 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 4428 itype, rc, iaq->nirq, nalloc); 4429 } 4430 4431 device_printf(sc->dev, 4432 "failed to find a usable interrupt type. " 4433 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 4434 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 4435 4436 return (ENXIO); 4437 } 4438 4439 #define FW_VERSION(chip) ( \ 4440 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 4441 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 4442 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 4443 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 4444 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 4445 4446 /* Just enough of fw_hdr to cover all version info. */ 4447 struct fw_h { 4448 __u8 ver; 4449 __u8 chip; 4450 __be16 len512; 4451 __be32 fw_ver; 4452 __be32 tp_microcode_ver; 4453 __u8 intfver_nic; 4454 __u8 intfver_vnic; 4455 __u8 intfver_ofld; 4456 __u8 intfver_ri; 4457 __u8 intfver_iscsipdu; 4458 __u8 intfver_iscsi; 4459 __u8 intfver_fcoepdu; 4460 __u8 intfver_fcoe; 4461 }; 4462 /* Spot check a couple of fields. */ 4463 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 4464 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 4465 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 4466 4467 struct fw_info { 4468 uint8_t chip; 4469 char *kld_name; 4470 char *fw_mod_name; 4471 struct fw_h fw_h; 4472 } fw_info[] = { 4473 { 4474 .chip = CHELSIO_T4, 4475 .kld_name = "t4fw_cfg", 4476 .fw_mod_name = "t4fw", 4477 .fw_h = { 4478 .chip = FW_HDR_CHIP_T4, 4479 .fw_ver = htobe32(FW_VERSION(T4)), 4480 .intfver_nic = FW_INTFVER(T4, NIC), 4481 .intfver_vnic = FW_INTFVER(T4, VNIC), 4482 .intfver_ofld = FW_INTFVER(T4, OFLD), 4483 .intfver_ri = FW_INTFVER(T4, RI), 4484 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 4485 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 4486 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 4487 .intfver_fcoe = FW_INTFVER(T4, FCOE), 4488 }, 4489 }, { 4490 .chip = CHELSIO_T5, 4491 .kld_name = "t5fw_cfg", 4492 .fw_mod_name = "t5fw", 4493 .fw_h = { 4494 .chip = FW_HDR_CHIP_T5, 4495 .fw_ver = htobe32(FW_VERSION(T5)), 4496 .intfver_nic = FW_INTFVER(T5, NIC), 4497 .intfver_vnic = FW_INTFVER(T5, VNIC), 4498 .intfver_ofld = FW_INTFVER(T5, OFLD), 4499 .intfver_ri = FW_INTFVER(T5, RI), 4500 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 4501 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 4502 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 4503 .intfver_fcoe = FW_INTFVER(T5, FCOE), 4504 }, 4505 }, { 4506 .chip = CHELSIO_T6, 4507 .kld_name = "t6fw_cfg", 4508 .fw_mod_name = "t6fw", 4509 .fw_h = { 4510 .chip = FW_HDR_CHIP_T6, 4511 .fw_ver = htobe32(FW_VERSION(T6)), 4512 .intfver_nic = FW_INTFVER(T6, NIC), 4513 .intfver_vnic = FW_INTFVER(T6, VNIC), 4514 .intfver_ofld = FW_INTFVER(T6, OFLD), 4515 .intfver_ri = FW_INTFVER(T6, RI), 4516 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 4517 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 4518 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 4519 .intfver_fcoe = FW_INTFVER(T6, FCOE), 4520 }, 4521 } 4522 }; 4523 4524 static struct fw_info * 4525 find_fw_info(int chip) 4526 { 4527 int i; 4528 4529 for (i = 0; i < nitems(fw_info); i++) { 4530 if (fw_info[i].chip == chip) 4531 return (&fw_info[i]); 4532 } 4533 return (NULL); 4534 } 4535 4536 /* 4537 * Is the given firmware API compatible with the one the driver was compiled 4538 * with? 4539 */ 4540 static int 4541 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 4542 { 4543 4544 /* short circuit if it's the exact same firmware version */ 4545 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 4546 return (1); 4547 4548 /* 4549 * XXX: Is this too conservative? Perhaps I should limit this to the 4550 * features that are supported in the driver. 4551 */ 4552 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 4553 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 4554 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 4555 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 4556 return (1); 4557 #undef SAME_INTF 4558 4559 return (0); 4560 } 4561 4562 static int 4563 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 4564 const struct firmware **fw) 4565 { 4566 struct fw_info *fw_info; 4567 4568 *dcfg = NULL; 4569 if (fw != NULL) 4570 *fw = NULL; 4571 4572 fw_info = find_fw_info(chip_id(sc)); 4573 if (fw_info == NULL) { 4574 device_printf(sc->dev, 4575 "unable to look up firmware information for chip %d.\n", 4576 chip_id(sc)); 4577 return (EINVAL); 4578 } 4579 4580 *dcfg = firmware_get(fw_info->kld_name); 4581 if (*dcfg != NULL) { 4582 if (fw != NULL) 4583 *fw = firmware_get(fw_info->fw_mod_name); 4584 return (0); 4585 } 4586 4587 return (ENOENT); 4588 } 4589 4590 static void 4591 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 4592 const struct firmware *fw) 4593 { 4594 4595 if (fw != NULL) 4596 firmware_put(fw, FIRMWARE_UNLOAD); 4597 if (dcfg != NULL) 4598 firmware_put(dcfg, FIRMWARE_UNLOAD); 4599 } 4600 4601 /* 4602 * Return values: 4603 * 0 means no firmware install attempted. 4604 * ERESTART means a firmware install was attempted and was successful. 4605 * +ve errno means a firmware install was attempted but failed. 4606 */ 4607 static int 4608 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 4609 const struct fw_h *drv_fw, const char *reason, int *already) 4610 { 4611 const struct firmware *cfg, *fw; 4612 const uint32_t c = be32toh(card_fw->fw_ver); 4613 uint32_t d, k; 4614 int rc, fw_install; 4615 struct fw_h bundled_fw; 4616 bool load_attempted; 4617 4618 cfg = fw = NULL; 4619 load_attempted = false; 4620 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 4621 4622 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 4623 if (t4_fw_install < 0) { 4624 rc = load_fw_module(sc, &cfg, &fw); 4625 if (rc != 0 || fw == NULL) { 4626 device_printf(sc->dev, 4627 "failed to load firmware module: %d. cfg %p, fw %p;" 4628 " will use compiled-in firmware version for" 4629 "hw.cxgbe.fw_install checks.\n", 4630 rc, cfg, fw); 4631 } else { 4632 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 4633 } 4634 load_attempted = true; 4635 } 4636 d = be32toh(bundled_fw.fw_ver); 4637 4638 if (reason != NULL) 4639 goto install; 4640 4641 if ((sc->flags & FW_OK) == 0) { 4642 4643 if (c == 0xffffffff) { 4644 reason = "missing"; 4645 goto install; 4646 } 4647 4648 rc = 0; 4649 goto done; 4650 } 4651 4652 if (!fw_compatible(card_fw, &bundled_fw)) { 4653 reason = "incompatible or unusable"; 4654 goto install; 4655 } 4656 4657 if (d > c) { 4658 reason = "older than the version bundled with this driver"; 4659 goto install; 4660 } 4661 4662 if (fw_install == 2 && d != c) { 4663 reason = "different than the version bundled with this driver"; 4664 goto install; 4665 } 4666 4667 /* No reason to do anything to the firmware already on the card. */ 4668 rc = 0; 4669 goto done; 4670 4671 install: 4672 rc = 0; 4673 if ((*already)++) 4674 goto done; 4675 4676 if (fw_install == 0) { 4677 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4678 "but the driver is prohibited from installing a firmware " 4679 "on the card.\n", 4680 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4681 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4682 4683 goto done; 4684 } 4685 4686 /* 4687 * We'll attempt to install a firmware. Load the module first (if it 4688 * hasn't been loaded already). 4689 */ 4690 if (!load_attempted) { 4691 rc = load_fw_module(sc, &cfg, &fw); 4692 if (rc != 0 || fw == NULL) { 4693 device_printf(sc->dev, 4694 "failed to load firmware module: %d. cfg %p, fw %p\n", 4695 rc, cfg, fw); 4696 /* carry on */ 4697 } 4698 } 4699 if (fw == NULL) { 4700 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4701 "but the driver cannot take corrective action because it " 4702 "is unable to load the firmware module.\n", 4703 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4704 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 4705 rc = sc->flags & FW_OK ? 0 : ENOENT; 4706 goto done; 4707 } 4708 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 4709 if (k != d) { 4710 MPASS(t4_fw_install > 0); 4711 device_printf(sc->dev, 4712 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 4713 "expecting (%u.%u.%u.%u) and will not be used.\n", 4714 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 4715 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 4716 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4717 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4718 rc = sc->flags & FW_OK ? 0 : EINVAL; 4719 goto done; 4720 } 4721 4722 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 4723 "installing firmware %u.%u.%u.%u on card.\n", 4724 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 4725 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 4726 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 4727 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 4728 4729 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 4730 if (rc != 0) { 4731 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 4732 } else { 4733 /* Installed successfully, update the cached header too. */ 4734 rc = ERESTART; 4735 memcpy(card_fw, fw->data, sizeof(*card_fw)); 4736 } 4737 done: 4738 unload_fw_module(sc, cfg, fw); 4739 4740 return (rc); 4741 } 4742 4743 /* 4744 * Establish contact with the firmware and attempt to become the master driver. 4745 * 4746 * A firmware will be installed to the card if needed (if the driver is allowed 4747 * to do so). 4748 */ 4749 static int 4750 contact_firmware(struct adapter *sc) 4751 { 4752 int rc, already = 0; 4753 enum dev_state state; 4754 struct fw_info *fw_info; 4755 struct fw_hdr *card_fw; /* fw on the card */ 4756 const struct fw_h *drv_fw; 4757 4758 fw_info = find_fw_info(chip_id(sc)); 4759 if (fw_info == NULL) { 4760 device_printf(sc->dev, 4761 "unable to look up firmware information for chip %d.\n", 4762 chip_id(sc)); 4763 return (EINVAL); 4764 } 4765 drv_fw = &fw_info->fw_h; 4766 4767 /* Read the header of the firmware on the card */ 4768 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 4769 restart: 4770 rc = -t4_get_fw_hdr(sc, card_fw); 4771 if (rc != 0) { 4772 device_printf(sc->dev, 4773 "unable to read firmware header from card's flash: %d\n", 4774 rc); 4775 goto done; 4776 } 4777 4778 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 4779 &already); 4780 if (rc == ERESTART) 4781 goto restart; 4782 if (rc != 0) 4783 goto done; 4784 4785 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 4786 if (rc < 0 || state == DEV_STATE_ERR) { 4787 rc = -rc; 4788 device_printf(sc->dev, 4789 "failed to connect to the firmware: %d, %d. " 4790 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4791 #if 0 4792 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4793 "not responding properly to HELLO", &already) == ERESTART) 4794 goto restart; 4795 #endif 4796 goto done; 4797 } 4798 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 4799 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 4800 4801 if (rc == sc->pf) { 4802 sc->flags |= MASTER_PF; 4803 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 4804 NULL, &already); 4805 if (rc == ERESTART) 4806 rc = 0; 4807 else if (rc != 0) 4808 goto done; 4809 } else if (state == DEV_STATE_UNINIT) { 4810 /* 4811 * We didn't get to be the master so we definitely won't be 4812 * configuring the chip. It's a bug if someone else hasn't 4813 * configured it already. 4814 */ 4815 device_printf(sc->dev, "couldn't be master(%d), " 4816 "device not already initialized either(%d). " 4817 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4818 rc = EPROTO; 4819 goto done; 4820 } else { 4821 /* 4822 * Some other PF is the master and has configured the chip. 4823 * This is allowed but untested. 4824 */ 4825 device_printf(sc->dev, "PF%d is master, device state %d. " 4826 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 4827 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 4828 sc->cfcsum = 0; 4829 rc = 0; 4830 } 4831 done: 4832 if (rc != 0 && sc->flags & FW_OK) { 4833 t4_fw_bye(sc, sc->mbox); 4834 sc->flags &= ~FW_OK; 4835 } 4836 free(card_fw, M_CXGBE); 4837 return (rc); 4838 } 4839 4840 static int 4841 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 4842 uint32_t mtype, uint32_t moff) 4843 { 4844 struct fw_info *fw_info; 4845 const struct firmware *dcfg, *rcfg = NULL; 4846 const uint32_t *cfdata; 4847 uint32_t cflen, addr; 4848 int rc; 4849 4850 load_fw_module(sc, &dcfg, NULL); 4851 4852 /* Card specific interpretation of "default". */ 4853 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4854 if (pci_get_device(sc->dev) == 0x440a) 4855 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 4856 if (is_fpga(sc)) 4857 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 4858 } 4859 4860 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 4861 if (dcfg == NULL) { 4862 device_printf(sc->dev, 4863 "KLD with default config is not available.\n"); 4864 rc = ENOENT; 4865 goto done; 4866 } 4867 cfdata = dcfg->data; 4868 cflen = dcfg->datasize & ~3; 4869 } else { 4870 char s[32]; 4871 4872 fw_info = find_fw_info(chip_id(sc)); 4873 if (fw_info == NULL) { 4874 device_printf(sc->dev, 4875 "unable to look up firmware information for chip %d.\n", 4876 chip_id(sc)); 4877 rc = EINVAL; 4878 goto done; 4879 } 4880 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 4881 4882 rcfg = firmware_get(s); 4883 if (rcfg == NULL) { 4884 device_printf(sc->dev, 4885 "unable to load module \"%s\" for configuration " 4886 "profile \"%s\".\n", s, cfg_file); 4887 rc = ENOENT; 4888 goto done; 4889 } 4890 cfdata = rcfg->data; 4891 cflen = rcfg->datasize & ~3; 4892 } 4893 4894 if (cflen > FLASH_CFG_MAX_SIZE) { 4895 device_printf(sc->dev, 4896 "config file too long (%d, max allowed is %d).\n", 4897 cflen, FLASH_CFG_MAX_SIZE); 4898 rc = EINVAL; 4899 goto done; 4900 } 4901 4902 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 4903 if (rc != 0) { 4904 device_printf(sc->dev, 4905 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 4906 __func__, mtype, moff, cflen, rc); 4907 rc = EINVAL; 4908 goto done; 4909 } 4910 write_via_memwin(sc, 2, addr, cfdata, cflen); 4911 done: 4912 if (rcfg != NULL) 4913 firmware_put(rcfg, FIRMWARE_UNLOAD); 4914 unload_fw_module(sc, dcfg, NULL); 4915 return (rc); 4916 } 4917 4918 struct caps_allowed { 4919 uint16_t nbmcaps; 4920 uint16_t linkcaps; 4921 uint16_t switchcaps; 4922 uint16_t niccaps; 4923 uint16_t toecaps; 4924 uint16_t rdmacaps; 4925 uint16_t cryptocaps; 4926 uint16_t iscsicaps; 4927 uint16_t fcoecaps; 4928 }; 4929 4930 #define FW_PARAM_DEV(param) \ 4931 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 4932 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 4933 #define FW_PARAM_PFVF(param) \ 4934 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 4935 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 4936 4937 /* 4938 * Provide a configuration profile to the firmware and have it initialize the 4939 * chip accordingly. This may involve uploading a configuration file to the 4940 * card. 4941 */ 4942 static int 4943 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 4944 const struct caps_allowed *caps_allowed) 4945 { 4946 int rc; 4947 struct fw_caps_config_cmd caps; 4948 uint32_t mtype, moff, finicsum, cfcsum, param, val; 4949 4950 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 4951 if (rc != 0) { 4952 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 4953 return (rc); 4954 } 4955 4956 bzero(&caps, sizeof(caps)); 4957 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4958 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4959 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 4960 mtype = 0; 4961 moff = 0; 4962 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4963 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 4964 mtype = FW_MEMTYPE_FLASH; 4965 moff = t4_flash_cfg_addr(sc); 4966 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 4967 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 4968 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 4969 FW_LEN16(caps)); 4970 } else { 4971 /* 4972 * Ask the firmware where it wants us to upload the config file. 4973 */ 4974 param = FW_PARAM_DEV(CF); 4975 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4976 if (rc != 0) { 4977 /* No support for config file? Shouldn't happen. */ 4978 device_printf(sc->dev, 4979 "failed to query config file location: %d.\n", rc); 4980 goto done; 4981 } 4982 mtype = G_FW_PARAMS_PARAM_Y(val); 4983 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 4984 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 4985 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 4986 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 4987 FW_LEN16(caps)); 4988 4989 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 4990 if (rc != 0) { 4991 device_printf(sc->dev, 4992 "failed to upload config file to card: %d.\n", rc); 4993 goto done; 4994 } 4995 } 4996 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 4997 if (rc != 0) { 4998 device_printf(sc->dev, "failed to pre-process config file: %d " 4999 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 5000 goto done; 5001 } 5002 5003 finicsum = be32toh(caps.finicsum); 5004 cfcsum = be32toh(caps.cfcsum); /* actual */ 5005 if (finicsum != cfcsum) { 5006 device_printf(sc->dev, 5007 "WARNING: config file checksum mismatch: %08x %08x\n", 5008 finicsum, cfcsum); 5009 } 5010 sc->cfcsum = cfcsum; 5011 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 5012 5013 /* 5014 * Let the firmware know what features will (not) be used so it can tune 5015 * things accordingly. 5016 */ 5017 #define LIMIT_CAPS(x) do { \ 5018 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 5019 } while (0) 5020 LIMIT_CAPS(nbm); 5021 LIMIT_CAPS(link); 5022 LIMIT_CAPS(switch); 5023 LIMIT_CAPS(nic); 5024 LIMIT_CAPS(toe); 5025 LIMIT_CAPS(rdma); 5026 LIMIT_CAPS(crypto); 5027 LIMIT_CAPS(iscsi); 5028 LIMIT_CAPS(fcoe); 5029 #undef LIMIT_CAPS 5030 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 5031 /* 5032 * TOE and hashfilters are mutually exclusive. It is a config 5033 * file or firmware bug if both are reported as available. Try 5034 * to cope with the situation in non-debug builds by disabling 5035 * TOE. 5036 */ 5037 MPASS(caps.toecaps == 0); 5038 5039 caps.toecaps = 0; 5040 caps.rdmacaps = 0; 5041 caps.iscsicaps = 0; 5042 } 5043 5044 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5045 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5046 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5047 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 5048 if (rc != 0) { 5049 device_printf(sc->dev, 5050 "failed to process config file: %d.\n", rc); 5051 goto done; 5052 } 5053 5054 t4_tweak_chip_settings(sc); 5055 set_params__pre_init(sc); 5056 5057 /* get basic stuff going */ 5058 rc = -t4_fw_initialize(sc, sc->mbox); 5059 if (rc != 0) { 5060 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 5061 goto done; 5062 } 5063 done: 5064 return (rc); 5065 } 5066 5067 /* 5068 * Partition chip resources for use between various PFs, VFs, etc. 5069 */ 5070 static int 5071 partition_resources(struct adapter *sc) 5072 { 5073 char cfg_file[sizeof(t4_cfg_file)]; 5074 struct caps_allowed caps_allowed; 5075 int rc; 5076 bool fallback; 5077 5078 /* Only the master driver gets to configure the chip resources. */ 5079 MPASS(sc->flags & MASTER_PF); 5080 5081 #define COPY_CAPS(x) do { \ 5082 caps_allowed.x##caps = t4_##x##caps_allowed; \ 5083 } while (0) 5084 bzero(&caps_allowed, sizeof(caps_allowed)); 5085 COPY_CAPS(nbm); 5086 COPY_CAPS(link); 5087 COPY_CAPS(switch); 5088 COPY_CAPS(nic); 5089 COPY_CAPS(toe); 5090 COPY_CAPS(rdma); 5091 COPY_CAPS(crypto); 5092 COPY_CAPS(iscsi); 5093 COPY_CAPS(fcoe); 5094 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 5095 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 5096 retry: 5097 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 5098 if (rc != 0 && fallback) { 5099 device_printf(sc->dev, 5100 "failed (%d) to configure card with \"%s\" profile, " 5101 "will fall back to a basic configuration and retry.\n", 5102 rc, cfg_file); 5103 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 5104 bzero(&caps_allowed, sizeof(caps_allowed)); 5105 COPY_CAPS(switch); 5106 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC; 5107 fallback = false; 5108 goto retry; 5109 } 5110 #undef COPY_CAPS 5111 return (rc); 5112 } 5113 5114 /* 5115 * Retrieve parameters that are needed (or nice to have) very early. 5116 */ 5117 static int 5118 get_params__pre_init(struct adapter *sc) 5119 { 5120 int rc; 5121 uint32_t param[2], val[2]; 5122 5123 t4_get_version_info(sc); 5124 5125 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 5126 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 5127 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 5128 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 5129 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 5130 5131 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 5132 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 5133 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 5134 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 5135 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 5136 5137 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 5138 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 5139 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 5140 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 5141 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 5142 5143 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 5144 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 5145 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 5146 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 5147 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 5148 5149 param[0] = FW_PARAM_DEV(PORTVEC); 5150 param[1] = FW_PARAM_DEV(CCLK); 5151 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5152 if (rc != 0) { 5153 device_printf(sc->dev, 5154 "failed to query parameters (pre_init): %d.\n", rc); 5155 return (rc); 5156 } 5157 5158 sc->params.portvec = val[0]; 5159 sc->params.nports = bitcount32(val[0]); 5160 sc->params.vpd.cclk = val[1]; 5161 5162 /* Read device log parameters. */ 5163 rc = -t4_init_devlog_params(sc, 1); 5164 if (rc == 0) 5165 fixup_devlog_params(sc); 5166 else { 5167 device_printf(sc->dev, 5168 "failed to get devlog parameters: %d.\n", rc); 5169 rc = 0; /* devlog isn't critical for device operation */ 5170 } 5171 5172 return (rc); 5173 } 5174 5175 /* 5176 * Any params that need to be set before FW_INITIALIZE. 5177 */ 5178 static int 5179 set_params__pre_init(struct adapter *sc) 5180 { 5181 int rc = 0; 5182 uint32_t param, val; 5183 5184 if (chip_id(sc) >= CHELSIO_T6) { 5185 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 5186 val = 1; 5187 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5188 /* firmwares < 1.20.1.0 do not have this param. */ 5189 if (rc == FW_EINVAL && 5190 sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) { 5191 rc = 0; 5192 } 5193 if (rc != 0) { 5194 device_printf(sc->dev, 5195 "failed to enable high priority filters :%d.\n", 5196 rc); 5197 } 5198 5199 param = FW_PARAM_DEV(PPOD_EDRAM); 5200 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5201 if (rc == 0 && val == 1) { 5202 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, 5203 &val); 5204 if (rc != 0) { 5205 device_printf(sc->dev, 5206 "failed to set PPOD_EDRAM: %d.\n", rc); 5207 } 5208 } 5209 } 5210 5211 /* Enable opaque VIIDs with firmwares that support it. */ 5212 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 5213 val = 1; 5214 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5215 if (rc == 0 && val == 1) 5216 sc->params.viid_smt_extn_support = true; 5217 else 5218 sc->params.viid_smt_extn_support = false; 5219 5220 return (rc); 5221 } 5222 5223 /* 5224 * Retrieve various parameters that are of interest to the driver. The device 5225 * has been initialized by the firmware at this point. 5226 */ 5227 static int 5228 get_params__post_init(struct adapter *sc) 5229 { 5230 int rc; 5231 uint32_t param[7], val[7]; 5232 struct fw_caps_config_cmd caps; 5233 5234 param[0] = FW_PARAM_PFVF(IQFLINT_START); 5235 param[1] = FW_PARAM_PFVF(EQ_START); 5236 param[2] = FW_PARAM_PFVF(FILTER_START); 5237 param[3] = FW_PARAM_PFVF(FILTER_END); 5238 param[4] = FW_PARAM_PFVF(L2T_START); 5239 param[5] = FW_PARAM_PFVF(L2T_END); 5240 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5241 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 5242 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 5243 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 5244 if (rc != 0) { 5245 device_printf(sc->dev, 5246 "failed to query parameters (post_init): %d.\n", rc); 5247 return (rc); 5248 } 5249 5250 sc->sge.iq_start = val[0]; 5251 sc->sge.eq_start = val[1]; 5252 if ((int)val[3] > (int)val[2]) { 5253 sc->tids.ftid_base = val[2]; 5254 sc->tids.ftid_end = val[3]; 5255 sc->tids.nftids = val[3] - val[2] + 1; 5256 } 5257 sc->vres.l2t.start = val[4]; 5258 sc->vres.l2t.size = val[5] - val[4] + 1; 5259 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 5260 ("%s: L2 table size (%u) larger than expected (%u)", 5261 __func__, sc->vres.l2t.size, L2T_SIZE)); 5262 sc->params.core_vdd = val[6]; 5263 5264 param[0] = FW_PARAM_PFVF(IQFLINT_END); 5265 param[1] = FW_PARAM_PFVF(EQ_END); 5266 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5267 if (rc != 0) { 5268 device_printf(sc->dev, 5269 "failed to query parameters (post_init2): %d.\n", rc); 5270 return (rc); 5271 } 5272 MPASS((int)val[0] >= sc->sge.iq_start); 5273 sc->sge.iqmap_sz = val[0] - sc->sge.iq_start + 1; 5274 MPASS((int)val[1] >= sc->sge.eq_start); 5275 sc->sge.eqmap_sz = val[1] - sc->sge.eq_start + 1; 5276 5277 if (chip_id(sc) >= CHELSIO_T6) { 5278 5279 sc->tids.tid_base = t4_read_reg(sc, 5280 A_LE_DB_ACTIVE_TABLE_START_INDEX); 5281 5282 param[0] = FW_PARAM_PFVF(HPFILTER_START); 5283 param[1] = FW_PARAM_PFVF(HPFILTER_END); 5284 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5285 if (rc != 0) { 5286 device_printf(sc->dev, 5287 "failed to query hpfilter parameters: %d.\n", rc); 5288 return (rc); 5289 } 5290 if ((int)val[1] > (int)val[0]) { 5291 sc->tids.hpftid_base = val[0]; 5292 sc->tids.hpftid_end = val[1]; 5293 sc->tids.nhpftids = val[1] - val[0] + 1; 5294 5295 /* 5296 * These should go off if the layout changes and the 5297 * driver needs to catch up. 5298 */ 5299 MPASS(sc->tids.hpftid_base == 0); 5300 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 5301 } 5302 5303 param[0] = FW_PARAM_PFVF(RAWF_START); 5304 param[1] = FW_PARAM_PFVF(RAWF_END); 5305 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5306 if (rc != 0) { 5307 device_printf(sc->dev, 5308 "failed to query rawf parameters: %d.\n", rc); 5309 return (rc); 5310 } 5311 if ((int)val[1] > (int)val[0]) { 5312 sc->rawf_base = val[0]; 5313 sc->nrawf = val[1] - val[0] + 1; 5314 } 5315 } 5316 5317 /* 5318 * MPSBGMAP is queried separately because only recent firmwares support 5319 * it as a parameter and we don't want the compound query above to fail 5320 * on older firmwares. 5321 */ 5322 param[0] = FW_PARAM_DEV(MPSBGMAP); 5323 val[0] = 0; 5324 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5325 if (rc == 0) 5326 sc->params.mps_bg_map = val[0]; 5327 else 5328 sc->params.mps_bg_map = 0; 5329 5330 /* 5331 * Determine whether the firmware supports the filter2 work request. 5332 * This is queried separately for the same reason as MPSBGMAP above. 5333 */ 5334 param[0] = FW_PARAM_DEV(FILTER2_WR); 5335 val[0] = 0; 5336 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5337 if (rc == 0) 5338 sc->params.filter2_wr_support = val[0] != 0; 5339 else 5340 sc->params.filter2_wr_support = 0; 5341 5342 /* 5343 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 5344 * This is queried separately for the same reason as other params above. 5345 */ 5346 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 5347 val[0] = 0; 5348 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5349 if (rc == 0) 5350 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 5351 else 5352 sc->params.ulptx_memwrite_dsgl = false; 5353 5354 /* FW_RI_FR_NSMR_TPTE_WR support */ 5355 param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 5356 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5357 if (rc == 0) 5358 sc->params.fr_nsmr_tpte_wr_support = val[0] != 0; 5359 else 5360 sc->params.fr_nsmr_tpte_wr_support = false; 5361 5362 /* Support for 512 SGL entries per FR MR. */ 5363 param[0] = FW_PARAM_DEV(DEV_512SGL_MR); 5364 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5365 if (rc == 0) 5366 sc->params.dev_512sgl_mr = val[0] != 0; 5367 else 5368 sc->params.dev_512sgl_mr = false; 5369 5370 param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); 5371 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5372 if (rc == 0) 5373 sc->params.max_pkts_per_eth_tx_pkts_wr = val[0]; 5374 else 5375 sc->params.max_pkts_per_eth_tx_pkts_wr = 15; 5376 5377 param[0] = FW_PARAM_DEV(NUM_TM_CLASS); 5378 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5379 if (rc == 0) { 5380 MPASS(val[0] > 0 && val[0] < 256); /* nsched_cls is 8b */ 5381 sc->params.nsched_cls = val[0]; 5382 } else 5383 sc->params.nsched_cls = sc->chip_params->nsched_cls; 5384 5385 /* get capabilites */ 5386 bzero(&caps, sizeof(caps)); 5387 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 5388 F_FW_CMD_REQUEST | F_FW_CMD_READ); 5389 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 5390 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 5391 if (rc != 0) { 5392 device_printf(sc->dev, 5393 "failed to get card capabilities: %d.\n", rc); 5394 return (rc); 5395 } 5396 5397 #define READ_CAPS(x) do { \ 5398 sc->x = htobe16(caps.x); \ 5399 } while (0) 5400 READ_CAPS(nbmcaps); 5401 READ_CAPS(linkcaps); 5402 READ_CAPS(switchcaps); 5403 READ_CAPS(niccaps); 5404 READ_CAPS(toecaps); 5405 READ_CAPS(rdmacaps); 5406 READ_CAPS(cryptocaps); 5407 READ_CAPS(iscsicaps); 5408 READ_CAPS(fcoecaps); 5409 5410 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 5411 MPASS(chip_id(sc) > CHELSIO_T4); 5412 MPASS(sc->toecaps == 0); 5413 sc->toecaps = 0; 5414 5415 param[0] = FW_PARAM_DEV(NTID); 5416 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 5417 if (rc != 0) { 5418 device_printf(sc->dev, 5419 "failed to query HASHFILTER parameters: %d.\n", rc); 5420 return (rc); 5421 } 5422 sc->tids.ntids = val[0]; 5423 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5424 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5425 sc->tids.ntids -= sc->tids.nhpftids; 5426 } 5427 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5428 sc->params.hash_filter = 1; 5429 } 5430 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 5431 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 5432 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 5433 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5434 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 5435 if (rc != 0) { 5436 device_printf(sc->dev, 5437 "failed to query NIC parameters: %d.\n", rc); 5438 return (rc); 5439 } 5440 if ((int)val[1] > (int)val[0]) { 5441 sc->tids.etid_base = val[0]; 5442 sc->tids.etid_end = val[1]; 5443 sc->tids.netids = val[1] - val[0] + 1; 5444 sc->params.eo_wr_cred = val[2]; 5445 sc->params.ethoffload = 1; 5446 } 5447 } 5448 if (sc->toecaps) { 5449 /* query offload-related parameters */ 5450 param[0] = FW_PARAM_DEV(NTID); 5451 param[1] = FW_PARAM_PFVF(SERVER_START); 5452 param[2] = FW_PARAM_PFVF(SERVER_END); 5453 param[3] = FW_PARAM_PFVF(TDDP_START); 5454 param[4] = FW_PARAM_PFVF(TDDP_END); 5455 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 5456 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5457 if (rc != 0) { 5458 device_printf(sc->dev, 5459 "failed to query TOE parameters: %d.\n", rc); 5460 return (rc); 5461 } 5462 sc->tids.ntids = val[0]; 5463 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) { 5464 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 5465 sc->tids.ntids -= sc->tids.nhpftids; 5466 } 5467 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 5468 if ((int)val[2] > (int)val[1]) { 5469 sc->tids.stid_base = val[1]; 5470 sc->tids.nstids = val[2] - val[1] + 1; 5471 } 5472 sc->vres.ddp.start = val[3]; 5473 sc->vres.ddp.size = val[4] - val[3] + 1; 5474 sc->params.ofldq_wr_cred = val[5]; 5475 sc->params.offload = 1; 5476 } else { 5477 /* 5478 * The firmware attempts memfree TOE configuration for -SO cards 5479 * and will report toecaps=0 if it runs out of resources (this 5480 * depends on the config file). It may not report 0 for other 5481 * capabilities dependent on the TOE in this case. Set them to 5482 * 0 here so that the driver doesn't bother tracking resources 5483 * that will never be used. 5484 */ 5485 sc->iscsicaps = 0; 5486 sc->rdmacaps = 0; 5487 } 5488 if (sc->rdmacaps) { 5489 param[0] = FW_PARAM_PFVF(STAG_START); 5490 param[1] = FW_PARAM_PFVF(STAG_END); 5491 param[2] = FW_PARAM_PFVF(RQ_START); 5492 param[3] = FW_PARAM_PFVF(RQ_END); 5493 param[4] = FW_PARAM_PFVF(PBL_START); 5494 param[5] = FW_PARAM_PFVF(PBL_END); 5495 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5496 if (rc != 0) { 5497 device_printf(sc->dev, 5498 "failed to query RDMA parameters(1): %d.\n", rc); 5499 return (rc); 5500 } 5501 sc->vres.stag.start = val[0]; 5502 sc->vres.stag.size = val[1] - val[0] + 1; 5503 sc->vres.rq.start = val[2]; 5504 sc->vres.rq.size = val[3] - val[2] + 1; 5505 sc->vres.pbl.start = val[4]; 5506 sc->vres.pbl.size = val[5] - val[4] + 1; 5507 5508 param[0] = FW_PARAM_PFVF(SQRQ_START); 5509 param[1] = FW_PARAM_PFVF(SQRQ_END); 5510 param[2] = FW_PARAM_PFVF(CQ_START); 5511 param[3] = FW_PARAM_PFVF(CQ_END); 5512 param[4] = FW_PARAM_PFVF(OCQ_START); 5513 param[5] = FW_PARAM_PFVF(OCQ_END); 5514 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 5515 if (rc != 0) { 5516 device_printf(sc->dev, 5517 "failed to query RDMA parameters(2): %d.\n", rc); 5518 return (rc); 5519 } 5520 sc->vres.qp.start = val[0]; 5521 sc->vres.qp.size = val[1] - val[0] + 1; 5522 sc->vres.cq.start = val[2]; 5523 sc->vres.cq.size = val[3] - val[2] + 1; 5524 sc->vres.ocq.start = val[4]; 5525 sc->vres.ocq.size = val[5] - val[4] + 1; 5526 5527 param[0] = FW_PARAM_PFVF(SRQ_START); 5528 param[1] = FW_PARAM_PFVF(SRQ_END); 5529 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 5530 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 5531 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 5532 if (rc != 0) { 5533 device_printf(sc->dev, 5534 "failed to query RDMA parameters(3): %d.\n", rc); 5535 return (rc); 5536 } 5537 sc->vres.srq.start = val[0]; 5538 sc->vres.srq.size = val[1] - val[0] + 1; 5539 sc->params.max_ordird_qp = val[2]; 5540 sc->params.max_ird_adapter = val[3]; 5541 } 5542 if (sc->iscsicaps) { 5543 param[0] = FW_PARAM_PFVF(ISCSI_START); 5544 param[1] = FW_PARAM_PFVF(ISCSI_END); 5545 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5546 if (rc != 0) { 5547 device_printf(sc->dev, 5548 "failed to query iSCSI parameters: %d.\n", rc); 5549 return (rc); 5550 } 5551 sc->vres.iscsi.start = val[0]; 5552 sc->vres.iscsi.size = val[1] - val[0] + 1; 5553 } 5554 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 5555 param[0] = FW_PARAM_PFVF(TLS_START); 5556 param[1] = FW_PARAM_PFVF(TLS_END); 5557 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 5558 if (rc != 0) { 5559 device_printf(sc->dev, 5560 "failed to query TLS parameters: %d.\n", rc); 5561 return (rc); 5562 } 5563 sc->vres.key.start = val[0]; 5564 sc->vres.key.size = val[1] - val[0] + 1; 5565 } 5566 5567 /* 5568 * We've got the params we wanted to query directly from the firmware. 5569 * Grab some others via other means. 5570 */ 5571 t4_init_sge_params(sc); 5572 t4_init_tp_params(sc); 5573 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 5574 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 5575 5576 rc = t4_verify_chip_settings(sc); 5577 if (rc != 0) 5578 return (rc); 5579 t4_init_rx_buf_info(sc); 5580 5581 return (rc); 5582 } 5583 5584 #ifdef KERN_TLS 5585 static void 5586 ktls_tick(void *arg) 5587 { 5588 struct adapter *sc; 5589 uint32_t tstamp; 5590 5591 sc = arg; 5592 tstamp = tcp_ts_getticks(); 5593 t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1); 5594 t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31); 5595 callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK); 5596 } 5597 5598 static int 5599 t6_config_kern_tls(struct adapter *sc, bool enable) 5600 { 5601 int rc; 5602 uint32_t param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5603 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_KTLS_HW) | 5604 V_FW_PARAMS_PARAM_Y(enable ? 1 : 0) | 5605 V_FW_PARAMS_PARAM_Z(FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE); 5606 5607 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, ¶m); 5608 if (rc != 0) { 5609 CH_ERR(sc, "failed to %s NIC TLS: %d\n", 5610 enable ? "enable" : "disable", rc); 5611 return (rc); 5612 } 5613 5614 if (enable) { 5615 sc->flags |= KERN_TLS_ON; 5616 callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc, 5617 C_HARDCLOCK); 5618 } else { 5619 sc->flags &= ~KERN_TLS_ON; 5620 callout_stop(&sc->ktls_tick); 5621 } 5622 5623 return (rc); 5624 } 5625 #endif 5626 5627 static int 5628 set_params__post_init(struct adapter *sc) 5629 { 5630 uint32_t mask, param, val; 5631 #ifdef TCP_OFFLOAD 5632 int i, v, shift; 5633 #endif 5634 5635 /* ask for encapsulated CPLs */ 5636 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 5637 val = 1; 5638 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5639 5640 /* Enable 32b port caps if the firmware supports it. */ 5641 param = FW_PARAM_PFVF(PORT_CAPS32); 5642 val = 1; 5643 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 5644 sc->params.port_caps32 = 1; 5645 5646 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 5647 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 5648 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 5649 V_MASKFILTER(val - 1)); 5650 5651 mask = F_DROPERRORANY | F_DROPERRORMAC | F_DROPERRORIPVER | 5652 F_DROPERRORFRAG | F_DROPERRORATTACK | F_DROPERRORETHHDRLEN | 5653 F_DROPERRORIPHDRLEN | F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5654 F_DROPERRORTCPOPT | F_DROPERRORCSUMIP | F_DROPERRORCSUM; 5655 val = 0; 5656 if (chip_id(sc) < CHELSIO_T6 && t4_attack_filter != 0) { 5657 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE, 5658 F_ATTACKFILTERENABLE); 5659 val |= F_DROPERRORATTACK; 5660 } 5661 if (t4_drop_ip_fragments != 0) { 5662 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP, 5663 F_FRAGMENTDROP); 5664 val |= F_DROPERRORFRAG; 5665 } 5666 if (t4_drop_pkts_with_l2_errors != 0) 5667 val |= F_DROPERRORMAC | F_DROPERRORETHHDRLEN; 5668 if (t4_drop_pkts_with_l3_errors != 0) { 5669 val |= F_DROPERRORIPVER | F_DROPERRORIPHDRLEN | 5670 F_DROPERRORCSUMIP; 5671 } 5672 if (t4_drop_pkts_with_l4_errors != 0) { 5673 val |= F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN | 5674 F_DROPERRORTCPOPT | F_DROPERRORCSUM; 5675 } 5676 t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val); 5677 5678 #ifdef TCP_OFFLOAD 5679 /* 5680 * Override the TOE timers with user provided tunables. This is not the 5681 * recommended way to change the timers (the firmware config file is) so 5682 * these tunables are not documented. 5683 * 5684 * All the timer tunables are in microseconds. 5685 */ 5686 if (t4_toe_keepalive_idle != 0) { 5687 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 5688 v &= M_KEEPALIVEIDLE; 5689 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 5690 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 5691 } 5692 if (t4_toe_keepalive_interval != 0) { 5693 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 5694 v &= M_KEEPALIVEINTVL; 5695 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 5696 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 5697 } 5698 if (t4_toe_keepalive_count != 0) { 5699 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 5700 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5701 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 5702 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 5703 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 5704 } 5705 if (t4_toe_rexmt_min != 0) { 5706 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 5707 v &= M_RXTMIN; 5708 t4_set_reg_field(sc, A_TP_RXT_MIN, 5709 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 5710 } 5711 if (t4_toe_rexmt_max != 0) { 5712 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 5713 v &= M_RXTMAX; 5714 t4_set_reg_field(sc, A_TP_RXT_MAX, 5715 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 5716 } 5717 if (t4_toe_rexmt_count != 0) { 5718 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 5719 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 5720 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 5721 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 5722 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 5723 } 5724 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 5725 if (t4_toe_rexmt_backoff[i] != -1) { 5726 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 5727 shift = (i & 3) << 3; 5728 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 5729 M_TIMERBACKOFFINDEX0 << shift, v << shift); 5730 } 5731 } 5732 #endif 5733 5734 #ifdef KERN_TLS 5735 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 5736 sc->toecaps & FW_CAPS_CONFIG_TOE) { 5737 /* 5738 * Limit TOE connections to 2 reassembly "islands". 5739 * This is required to permit migrating TOE 5740 * connections to UPL_MODE_TLS. 5741 */ 5742 t4_tp_wr_bits_indirect(sc, A_TP_FRAG_CONFIG, 5743 V_PASSMODE(M_PASSMODE), V_PASSMODE(2)); 5744 } 5745 5746 if (is_ktls(sc)) { 5747 sc->tlst.inline_keys = t4_tls_inline_keys; 5748 sc->tlst.combo_wrs = t4_tls_combo_wrs; 5749 if (t4_kern_tls != 0 && is_t6(sc)) 5750 t6_config_kern_tls(sc, true); 5751 } 5752 #endif 5753 return (0); 5754 } 5755 5756 #undef FW_PARAM_PFVF 5757 #undef FW_PARAM_DEV 5758 5759 static void 5760 t4_set_desc(struct adapter *sc) 5761 { 5762 char buf[128]; 5763 struct adapter_params *p = &sc->params; 5764 5765 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 5766 5767 device_set_desc_copy(sc->dev, buf); 5768 } 5769 5770 static inline void 5771 ifmedia_add4(struct ifmedia *ifm, int m) 5772 { 5773 5774 ifmedia_add(ifm, m, 0, NULL); 5775 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 5776 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 5777 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 5778 } 5779 5780 /* 5781 * This is the selected media, which is not quite the same as the active media. 5782 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 5783 * and active are not the same, and "media: Ethernet selected" otherwise. 5784 */ 5785 static void 5786 set_current_media(struct port_info *pi) 5787 { 5788 struct link_config *lc; 5789 struct ifmedia *ifm; 5790 int mword; 5791 u_int speed; 5792 5793 PORT_LOCK_ASSERT_OWNED(pi); 5794 5795 /* Leave current media alone if it's already set to IFM_NONE. */ 5796 ifm = &pi->media; 5797 if (ifm->ifm_cur != NULL && 5798 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 5799 return; 5800 5801 lc = &pi->link_cfg; 5802 if (lc->requested_aneg != AUTONEG_DISABLE && 5803 lc->pcaps & FW_PORT_CAP32_ANEG) { 5804 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 5805 return; 5806 } 5807 mword = IFM_ETHER | IFM_FDX; 5808 if (lc->requested_fc & PAUSE_TX) 5809 mword |= IFM_ETH_TXPAUSE; 5810 if (lc->requested_fc & PAUSE_RX) 5811 mword |= IFM_ETH_RXPAUSE; 5812 if (lc->requested_speed == 0) 5813 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 5814 else 5815 speed = lc->requested_speed; 5816 mword |= port_mword(pi, speed_to_fwcap(speed)); 5817 ifmedia_set(ifm, mword); 5818 } 5819 5820 /* 5821 * Returns true if the ifmedia list for the port cannot change. 5822 */ 5823 static bool 5824 fixed_ifmedia(struct port_info *pi) 5825 { 5826 5827 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 5828 pi->port_type == FW_PORT_TYPE_BT_XFI || 5829 pi->port_type == FW_PORT_TYPE_BT_XAUI || 5830 pi->port_type == FW_PORT_TYPE_KX4 || 5831 pi->port_type == FW_PORT_TYPE_KX || 5832 pi->port_type == FW_PORT_TYPE_KR || 5833 pi->port_type == FW_PORT_TYPE_BP_AP || 5834 pi->port_type == FW_PORT_TYPE_BP4_AP || 5835 pi->port_type == FW_PORT_TYPE_BP40_BA || 5836 pi->port_type == FW_PORT_TYPE_KR4_100G || 5837 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 5838 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 5839 } 5840 5841 static void 5842 build_medialist(struct port_info *pi) 5843 { 5844 uint32_t ss, speed; 5845 int unknown, mword, bit; 5846 struct link_config *lc; 5847 struct ifmedia *ifm; 5848 5849 PORT_LOCK_ASSERT_OWNED(pi); 5850 5851 if (pi->flags & FIXED_IFMEDIA) 5852 return; 5853 5854 /* 5855 * Rebuild the ifmedia list. 5856 */ 5857 ifm = &pi->media; 5858 ifmedia_removeall(ifm); 5859 lc = &pi->link_cfg; 5860 ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */ 5861 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 5862 MPASS(ss != 0); 5863 no_media: 5864 MPASS(LIST_EMPTY(&ifm->ifm_list)); 5865 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 5866 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 5867 return; 5868 } 5869 5870 unknown = 0; 5871 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 5872 speed = 1 << bit; 5873 MPASS(speed & M_FW_PORT_CAP32_SPEED); 5874 if (ss & speed) { 5875 mword = port_mword(pi, speed); 5876 if (mword == IFM_NONE) { 5877 goto no_media; 5878 } else if (mword == IFM_UNKNOWN) 5879 unknown++; 5880 else 5881 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 5882 } 5883 } 5884 if (unknown > 0) /* Add one unknown for all unknown media types. */ 5885 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 5886 if (lc->pcaps & FW_PORT_CAP32_ANEG) 5887 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 5888 5889 set_current_media(pi); 5890 } 5891 5892 /* 5893 * Initialize the requested fields in the link config based on driver tunables. 5894 */ 5895 static void 5896 init_link_config(struct port_info *pi) 5897 { 5898 struct link_config *lc = &pi->link_cfg; 5899 5900 PORT_LOCK_ASSERT_OWNED(pi); 5901 5902 lc->requested_caps = 0; 5903 lc->requested_speed = 0; 5904 5905 if (t4_autoneg == 0) 5906 lc->requested_aneg = AUTONEG_DISABLE; 5907 else if (t4_autoneg == 1) 5908 lc->requested_aneg = AUTONEG_ENABLE; 5909 else 5910 lc->requested_aneg = AUTONEG_AUTO; 5911 5912 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 5913 PAUSE_AUTONEG); 5914 5915 if (t4_fec & FEC_AUTO) 5916 lc->requested_fec = FEC_AUTO; 5917 else if (t4_fec == 0) 5918 lc->requested_fec = FEC_NONE; 5919 else { 5920 /* -1 is handled by the FEC_AUTO block above and not here. */ 5921 lc->requested_fec = t4_fec & 5922 (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE); 5923 if (lc->requested_fec == 0) 5924 lc->requested_fec = FEC_AUTO; 5925 } 5926 if (t4_force_fec < 0) 5927 lc->force_fec = -1; 5928 else if (t4_force_fec > 0) 5929 lc->force_fec = 1; 5930 else 5931 lc->force_fec = 0; 5932 } 5933 5934 /* 5935 * Makes sure that all requested settings comply with what's supported by the 5936 * port. Returns the number of settings that were invalid and had to be fixed. 5937 */ 5938 static int 5939 fixup_link_config(struct port_info *pi) 5940 { 5941 int n = 0; 5942 struct link_config *lc = &pi->link_cfg; 5943 uint32_t fwspeed; 5944 5945 PORT_LOCK_ASSERT_OWNED(pi); 5946 5947 /* Speed (when not autonegotiating) */ 5948 if (lc->requested_speed != 0) { 5949 fwspeed = speed_to_fwcap(lc->requested_speed); 5950 if ((fwspeed & lc->pcaps) == 0) { 5951 n++; 5952 lc->requested_speed = 0; 5953 } 5954 } 5955 5956 /* Link autonegotiation */ 5957 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 5958 lc->requested_aneg == AUTONEG_DISABLE || 5959 lc->requested_aneg == AUTONEG_AUTO); 5960 if (lc->requested_aneg == AUTONEG_ENABLE && 5961 !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 5962 n++; 5963 lc->requested_aneg = AUTONEG_AUTO; 5964 } 5965 5966 /* Flow control */ 5967 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 5968 if (lc->requested_fc & PAUSE_TX && 5969 !(lc->pcaps & FW_PORT_CAP32_FC_TX)) { 5970 n++; 5971 lc->requested_fc &= ~PAUSE_TX; 5972 } 5973 if (lc->requested_fc & PAUSE_RX && 5974 !(lc->pcaps & FW_PORT_CAP32_FC_RX)) { 5975 n++; 5976 lc->requested_fc &= ~PAUSE_RX; 5977 } 5978 if (!(lc->requested_fc & PAUSE_AUTONEG) && 5979 !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) { 5980 n++; 5981 lc->requested_fc |= PAUSE_AUTONEG; 5982 } 5983 5984 /* FEC */ 5985 if ((lc->requested_fec & FEC_RS && 5986 !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) || 5987 (lc->requested_fec & FEC_BASER_RS && 5988 !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) { 5989 n++; 5990 lc->requested_fec = FEC_AUTO; 5991 } 5992 5993 return (n); 5994 } 5995 5996 /* 5997 * Apply the requested L1 settings, which are expected to be valid, to the 5998 * hardware. 5999 */ 6000 static int 6001 apply_link_config(struct port_info *pi) 6002 { 6003 struct adapter *sc = pi->adapter; 6004 struct link_config *lc = &pi->link_cfg; 6005 int rc; 6006 6007 #ifdef INVARIANTS 6008 ASSERT_SYNCHRONIZED_OP(sc); 6009 PORT_LOCK_ASSERT_OWNED(pi); 6010 6011 if (lc->requested_aneg == AUTONEG_ENABLE) 6012 MPASS(lc->pcaps & FW_PORT_CAP32_ANEG); 6013 if (!(lc->requested_fc & PAUSE_AUTONEG)) 6014 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE); 6015 if (lc->requested_fc & PAUSE_TX) 6016 MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX); 6017 if (lc->requested_fc & PAUSE_RX) 6018 MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX); 6019 if (lc->requested_fec & FEC_RS) 6020 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS); 6021 if (lc->requested_fec & FEC_BASER_RS) 6022 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS); 6023 #endif 6024 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 6025 if (rc != 0) { 6026 /* Don't complain if the VF driver gets back an EPERM. */ 6027 if (!(sc->flags & IS_VF) || rc != FW_EPERM) 6028 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 6029 } else { 6030 /* 6031 * An L1_CFG will almost always result in a link-change event if 6032 * the link is up, and the driver will refresh the actual 6033 * fec/fc/etc. when the notification is processed. If the link 6034 * is down then the actual settings are meaningless. 6035 * 6036 * This takes care of the case where a change in the L1 settings 6037 * may not result in a notification. 6038 */ 6039 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 6040 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 6041 } 6042 return (rc); 6043 } 6044 6045 #define FW_MAC_EXACT_CHUNK 7 6046 struct mcaddr_ctx { 6047 struct ifnet *ifp; 6048 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 6049 uint64_t hash; 6050 int i; 6051 int del; 6052 int rc; 6053 }; 6054 6055 static u_int 6056 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 6057 { 6058 struct mcaddr_ctx *ctx = arg; 6059 struct vi_info *vi = ctx->ifp->if_softc; 6060 struct port_info *pi = vi->pi; 6061 struct adapter *sc = pi->adapter; 6062 6063 if (ctx->rc < 0) 6064 return (0); 6065 6066 ctx->mcaddr[ctx->i] = LLADDR(sdl); 6067 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i])); 6068 ctx->i++; 6069 6070 if (ctx->i == FW_MAC_EXACT_CHUNK) { 6071 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del, 6072 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0); 6073 if (ctx->rc < 0) { 6074 int j; 6075 6076 for (j = 0; j < ctx->i; j++) { 6077 if_printf(ctx->ifp, 6078 "failed to add mc address" 6079 " %02x:%02x:%02x:" 6080 "%02x:%02x:%02x rc=%d\n", 6081 ctx->mcaddr[j][0], ctx->mcaddr[j][1], 6082 ctx->mcaddr[j][2], ctx->mcaddr[j][3], 6083 ctx->mcaddr[j][4], ctx->mcaddr[j][5], 6084 -ctx->rc); 6085 } 6086 return (0); 6087 } 6088 ctx->del = 0; 6089 ctx->i = 0; 6090 } 6091 6092 return (1); 6093 } 6094 6095 /* 6096 * Program the port's XGMAC based on parameters in ifnet. The caller also 6097 * indicates which parameters should be programmed (the rest are left alone). 6098 */ 6099 int 6100 update_mac_settings(struct ifnet *ifp, int flags) 6101 { 6102 int rc = 0; 6103 struct vi_info *vi = ifp->if_softc; 6104 struct port_info *pi = vi->pi; 6105 struct adapter *sc = pi->adapter; 6106 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 6107 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 6108 6109 ASSERT_SYNCHRONIZED_OP(sc); 6110 KASSERT(flags, ("%s: not told what to update.", __func__)); 6111 6112 if (flags & XGMAC_MTU) 6113 mtu = ifp->if_mtu; 6114 6115 if (flags & XGMAC_PROMISC) 6116 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 6117 6118 if (flags & XGMAC_ALLMULTI) 6119 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 6120 6121 if (flags & XGMAC_VLANEX) 6122 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 6123 6124 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 6125 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 6126 allmulti, 1, vlanex, false); 6127 if (rc) { 6128 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 6129 rc); 6130 return (rc); 6131 } 6132 } 6133 6134 if (flags & XGMAC_UCADDR) { 6135 uint8_t ucaddr[ETHER_ADDR_LEN]; 6136 6137 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 6138 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 6139 ucaddr, true, &vi->smt_idx); 6140 if (rc < 0) { 6141 rc = -rc; 6142 if_printf(ifp, "change_mac failed: %d\n", rc); 6143 return (rc); 6144 } else { 6145 vi->xact_addr_filt = rc; 6146 rc = 0; 6147 } 6148 } 6149 6150 if (flags & XGMAC_MCADDRS) { 6151 struct epoch_tracker et; 6152 struct mcaddr_ctx ctx; 6153 int j; 6154 6155 ctx.ifp = ifp; 6156 ctx.hash = 0; 6157 ctx.i = 0; 6158 ctx.del = 1; 6159 ctx.rc = 0; 6160 /* 6161 * Unlike other drivers, we accumulate list of pointers into 6162 * interface address lists and we need to keep it safe even 6163 * after if_foreach_llmaddr() returns, thus we must enter the 6164 * network epoch. 6165 */ 6166 NET_EPOCH_ENTER(et); 6167 if_foreach_llmaddr(ifp, add_maddr, &ctx); 6168 if (ctx.rc < 0) { 6169 NET_EPOCH_EXIT(et); 6170 rc = -ctx.rc; 6171 return (rc); 6172 } 6173 if (ctx.i > 0) { 6174 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 6175 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0); 6176 NET_EPOCH_EXIT(et); 6177 if (rc < 0) { 6178 rc = -rc; 6179 for (j = 0; j < ctx.i; j++) { 6180 if_printf(ifp, 6181 "failed to add mcast address" 6182 " %02x:%02x:%02x:" 6183 "%02x:%02x:%02x rc=%d\n", 6184 ctx.mcaddr[j][0], ctx.mcaddr[j][1], 6185 ctx.mcaddr[j][2], ctx.mcaddr[j][3], 6186 ctx.mcaddr[j][4], ctx.mcaddr[j][5], 6187 rc); 6188 } 6189 return (rc); 6190 } 6191 ctx.del = 0; 6192 } else 6193 NET_EPOCH_EXIT(et); 6194 6195 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0); 6196 if (rc != 0) 6197 if_printf(ifp, "failed to set mcast address hash: %d\n", 6198 rc); 6199 if (ctx.del == 0) { 6200 /* We clobbered the VXLAN entry if there was one. */ 6201 pi->vxlan_tcam_entry = false; 6202 } 6203 } 6204 6205 if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 && 6206 pi->vxlan_tcam_entry == false) { 6207 rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac, 6208 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 6209 true); 6210 if (rc < 0) { 6211 rc = -rc; 6212 if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n", 6213 rc); 6214 } else { 6215 MPASS(rc == sc->rawf_base + pi->port_id); 6216 rc = 0; 6217 pi->vxlan_tcam_entry = true; 6218 } 6219 } 6220 6221 return (rc); 6222 } 6223 6224 /* 6225 * {begin|end}_synchronized_op must be called from the same thread. 6226 */ 6227 int 6228 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 6229 char *wmesg) 6230 { 6231 int rc, pri; 6232 6233 #ifdef WITNESS 6234 /* the caller thinks it's ok to sleep, but is it really? */ 6235 if (flags & SLEEP_OK) 6236 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 6237 "begin_synchronized_op"); 6238 #endif 6239 6240 if (INTR_OK) 6241 pri = PCATCH; 6242 else 6243 pri = 0; 6244 6245 ADAPTER_LOCK(sc); 6246 for (;;) { 6247 6248 if (vi && IS_DOOMED(vi)) { 6249 rc = ENXIO; 6250 goto done; 6251 } 6252 6253 if (!IS_BUSY(sc)) { 6254 rc = 0; 6255 break; 6256 } 6257 6258 if (!(flags & SLEEP_OK)) { 6259 rc = EBUSY; 6260 goto done; 6261 } 6262 6263 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 6264 rc = EINTR; 6265 goto done; 6266 } 6267 } 6268 6269 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 6270 SET_BUSY(sc); 6271 #ifdef INVARIANTS 6272 sc->last_op = wmesg; 6273 sc->last_op_thr = curthread; 6274 sc->last_op_flags = flags; 6275 #endif 6276 6277 done: 6278 if (!(flags & HOLD_LOCK) || rc) 6279 ADAPTER_UNLOCK(sc); 6280 6281 return (rc); 6282 } 6283 6284 /* 6285 * Tell if_ioctl and if_init that the VI is going away. This is 6286 * special variant of begin_synchronized_op and must be paired with a 6287 * call to end_synchronized_op. 6288 */ 6289 void 6290 doom_vi(struct adapter *sc, struct vi_info *vi) 6291 { 6292 6293 ADAPTER_LOCK(sc); 6294 SET_DOOMED(vi); 6295 wakeup(&sc->flags); 6296 while (IS_BUSY(sc)) 6297 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 6298 SET_BUSY(sc); 6299 #ifdef INVARIANTS 6300 sc->last_op = "t4detach"; 6301 sc->last_op_thr = curthread; 6302 sc->last_op_flags = 0; 6303 #endif 6304 ADAPTER_UNLOCK(sc); 6305 } 6306 6307 /* 6308 * {begin|end}_synchronized_op must be called from the same thread. 6309 */ 6310 void 6311 end_synchronized_op(struct adapter *sc, int flags) 6312 { 6313 6314 if (flags & LOCK_HELD) 6315 ADAPTER_LOCK_ASSERT_OWNED(sc); 6316 else 6317 ADAPTER_LOCK(sc); 6318 6319 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 6320 CLR_BUSY(sc); 6321 wakeup(&sc->flags); 6322 ADAPTER_UNLOCK(sc); 6323 } 6324 6325 static int 6326 cxgbe_init_synchronized(struct vi_info *vi) 6327 { 6328 struct port_info *pi = vi->pi; 6329 struct adapter *sc = pi->adapter; 6330 struct ifnet *ifp = vi->ifp; 6331 int rc = 0, i; 6332 struct sge_txq *txq; 6333 6334 ASSERT_SYNCHRONIZED_OP(sc); 6335 6336 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6337 return (0); /* already running */ 6338 6339 if (!(sc->flags & FULL_INIT_DONE) && ((rc = adapter_init(sc)) != 0)) 6340 return (rc); /* error message displayed already */ 6341 6342 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 6343 return (rc); /* error message displayed already */ 6344 6345 rc = update_mac_settings(ifp, XGMAC_ALL); 6346 if (rc) 6347 goto done; /* error message displayed already */ 6348 6349 PORT_LOCK(pi); 6350 if (pi->up_vis == 0) { 6351 t4_update_port_info(pi); 6352 fixup_link_config(pi); 6353 build_medialist(pi); 6354 apply_link_config(pi); 6355 } 6356 6357 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 6358 if (rc != 0) { 6359 if_printf(ifp, "enable_vi failed: %d\n", rc); 6360 PORT_UNLOCK(pi); 6361 goto done; 6362 } 6363 6364 /* 6365 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 6366 * if this changes. 6367 */ 6368 6369 for_each_txq(vi, i, txq) { 6370 TXQ_LOCK(txq); 6371 txq->eq.flags |= EQ_ENABLED; 6372 TXQ_UNLOCK(txq); 6373 } 6374 6375 /* 6376 * The first iq of the first port to come up is used for tracing. 6377 */ 6378 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 6379 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 6380 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 6381 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 6382 V_QUEUENUMBER(sc->traceq)); 6383 pi->flags |= HAS_TRACEQ; 6384 } 6385 6386 /* all ok */ 6387 pi->up_vis++; 6388 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6389 if (pi->link_cfg.link_ok) 6390 t4_os_link_changed(pi); 6391 PORT_UNLOCK(pi); 6392 6393 mtx_lock(&vi->tick_mtx); 6394 if (ifp->if_get_counter == vi_get_counter) 6395 callout_reset(&vi->tick, hz, vi_tick, vi); 6396 else 6397 callout_reset(&vi->tick, hz, cxgbe_tick, vi); 6398 mtx_unlock(&vi->tick_mtx); 6399 done: 6400 if (rc != 0) 6401 cxgbe_uninit_synchronized(vi); 6402 6403 return (rc); 6404 } 6405 6406 /* 6407 * Idempotent. 6408 */ 6409 static int 6410 cxgbe_uninit_synchronized(struct vi_info *vi) 6411 { 6412 struct port_info *pi = vi->pi; 6413 struct adapter *sc = pi->adapter; 6414 struct ifnet *ifp = vi->ifp; 6415 int rc, i; 6416 struct sge_txq *txq; 6417 6418 ASSERT_SYNCHRONIZED_OP(sc); 6419 6420 if (!(vi->flags & VI_INIT_DONE)) { 6421 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 6422 KASSERT(0, ("uninited VI is running")); 6423 if_printf(ifp, "uninited VI with running ifnet. " 6424 "vi->flags 0x%016lx, if_flags 0x%08x, " 6425 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 6426 ifp->if_drv_flags); 6427 } 6428 return (0); 6429 } 6430 6431 /* 6432 * Disable the VI so that all its data in either direction is discarded 6433 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 6434 * tick) intact as the TP can deliver negative advice or data that it's 6435 * holding in its RAM (for an offloaded connection) even after the VI is 6436 * disabled. 6437 */ 6438 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 6439 if (rc) { 6440 if_printf(ifp, "disable_vi failed: %d\n", rc); 6441 return (rc); 6442 } 6443 6444 for_each_txq(vi, i, txq) { 6445 TXQ_LOCK(txq); 6446 txq->eq.flags &= ~EQ_ENABLED; 6447 TXQ_UNLOCK(txq); 6448 } 6449 6450 mtx_lock(&vi->tick_mtx); 6451 callout_stop(&vi->tick); 6452 mtx_unlock(&vi->tick_mtx); 6453 6454 PORT_LOCK(pi); 6455 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 6456 PORT_UNLOCK(pi); 6457 return (0); 6458 } 6459 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 6460 pi->up_vis--; 6461 if (pi->up_vis > 0) { 6462 PORT_UNLOCK(pi); 6463 return (0); 6464 } 6465 6466 pi->link_cfg.link_ok = false; 6467 pi->link_cfg.speed = 0; 6468 pi->link_cfg.link_down_rc = 255; 6469 t4_os_link_changed(pi); 6470 PORT_UNLOCK(pi); 6471 6472 return (0); 6473 } 6474 6475 /* 6476 * It is ok for this function to fail midway and return right away. t4_detach 6477 * will walk the entire sc->irq list and clean up whatever is valid. 6478 */ 6479 int 6480 t4_setup_intr_handlers(struct adapter *sc) 6481 { 6482 int rc, rid, p, q, v; 6483 char s[8]; 6484 struct irq *irq; 6485 struct port_info *pi; 6486 struct vi_info *vi; 6487 struct sge *sge = &sc->sge; 6488 struct sge_rxq *rxq; 6489 #ifdef TCP_OFFLOAD 6490 struct sge_ofld_rxq *ofld_rxq; 6491 #endif 6492 #ifdef DEV_NETMAP 6493 struct sge_nm_rxq *nm_rxq; 6494 #endif 6495 #ifdef RSS 6496 int nbuckets = rss_getnumbuckets(); 6497 #endif 6498 6499 /* 6500 * Setup interrupts. 6501 */ 6502 irq = &sc->irq[0]; 6503 rid = sc->intr_type == INTR_INTX ? 0 : 1; 6504 if (forwarding_intr_to_fwq(sc)) 6505 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 6506 6507 /* Multiple interrupts. */ 6508 if (sc->flags & IS_VF) 6509 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 6510 ("%s: too few intr.", __func__)); 6511 else 6512 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 6513 ("%s: too few intr.", __func__)); 6514 6515 /* The first one is always error intr on PFs */ 6516 if (!(sc->flags & IS_VF)) { 6517 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 6518 if (rc != 0) 6519 return (rc); 6520 irq++; 6521 rid++; 6522 } 6523 6524 /* The second one is always the firmware event queue (first on VFs) */ 6525 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 6526 if (rc != 0) 6527 return (rc); 6528 irq++; 6529 rid++; 6530 6531 for_each_port(sc, p) { 6532 pi = sc->port[p]; 6533 for_each_vi(pi, v, vi) { 6534 vi->first_intr = rid - 1; 6535 6536 if (vi->nnmrxq > 0) { 6537 int n = max(vi->nrxq, vi->nnmrxq); 6538 6539 rxq = &sge->rxq[vi->first_rxq]; 6540 #ifdef DEV_NETMAP 6541 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 6542 #endif 6543 for (q = 0; q < n; q++) { 6544 snprintf(s, sizeof(s), "%x%c%x", p, 6545 'a' + v, q); 6546 if (q < vi->nrxq) 6547 irq->rxq = rxq++; 6548 #ifdef DEV_NETMAP 6549 if (q < vi->nnmrxq) 6550 irq->nm_rxq = nm_rxq++; 6551 6552 if (irq->nm_rxq != NULL && 6553 irq->rxq == NULL) { 6554 /* Netmap rx only */ 6555 rc = t4_alloc_irq(sc, irq, rid, 6556 t4_nm_intr, irq->nm_rxq, s); 6557 } 6558 if (irq->nm_rxq != NULL && 6559 irq->rxq != NULL) { 6560 /* NIC and Netmap rx */ 6561 rc = t4_alloc_irq(sc, irq, rid, 6562 t4_vi_intr, irq, s); 6563 } 6564 #endif 6565 if (irq->rxq != NULL && 6566 irq->nm_rxq == NULL) { 6567 /* NIC rx only */ 6568 rc = t4_alloc_irq(sc, irq, rid, 6569 t4_intr, irq->rxq, s); 6570 } 6571 if (rc != 0) 6572 return (rc); 6573 #ifdef RSS 6574 if (q < vi->nrxq) { 6575 bus_bind_intr(sc->dev, irq->res, 6576 rss_getcpu(q % nbuckets)); 6577 } 6578 #endif 6579 irq++; 6580 rid++; 6581 vi->nintr++; 6582 } 6583 } else { 6584 for_each_rxq(vi, q, rxq) { 6585 snprintf(s, sizeof(s), "%x%c%x", p, 6586 'a' + v, q); 6587 rc = t4_alloc_irq(sc, irq, rid, 6588 t4_intr, rxq, s); 6589 if (rc != 0) 6590 return (rc); 6591 #ifdef RSS 6592 bus_bind_intr(sc->dev, irq->res, 6593 rss_getcpu(q % nbuckets)); 6594 #endif 6595 irq++; 6596 rid++; 6597 vi->nintr++; 6598 } 6599 } 6600 #ifdef TCP_OFFLOAD 6601 for_each_ofld_rxq(vi, q, ofld_rxq) { 6602 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 6603 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 6604 ofld_rxq, s); 6605 if (rc != 0) 6606 return (rc); 6607 irq++; 6608 rid++; 6609 vi->nintr++; 6610 } 6611 #endif 6612 } 6613 } 6614 MPASS(irq == &sc->irq[sc->intr_count]); 6615 6616 return (0); 6617 } 6618 6619 static void 6620 write_global_rss_key(struct adapter *sc) 6621 { 6622 #ifdef RSS 6623 int i; 6624 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6625 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 6626 6627 CTASSERT(RSS_KEYSIZE == 40); 6628 6629 rss_getkey((void *)&raw_rss_key[0]); 6630 for (i = 0; i < nitems(rss_key); i++) { 6631 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 6632 } 6633 t4_write_rss_key(sc, &rss_key[0], -1, 1); 6634 #endif 6635 } 6636 6637 /* 6638 * Idempotent. 6639 */ 6640 static int 6641 adapter_full_init(struct adapter *sc) 6642 { 6643 int rc, i; 6644 6645 ASSERT_SYNCHRONIZED_OP(sc); 6646 6647 /* 6648 * queues that belong to the adapter (not any particular port). 6649 */ 6650 rc = t4_setup_adapter_queues(sc); 6651 if (rc != 0) 6652 return (rc); 6653 6654 for (i = 0; i < nitems(sc->tq); i++) { 6655 if (sc->tq[i] != NULL) 6656 continue; 6657 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 6658 taskqueue_thread_enqueue, &sc->tq[i]); 6659 if (sc->tq[i] == NULL) { 6660 CH_ERR(sc, "failed to allocate task queue %d\n", i); 6661 return (ENOMEM); 6662 } 6663 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 6664 device_get_nameunit(sc->dev), i); 6665 } 6666 6667 if (!(sc->flags & IS_VF)) { 6668 write_global_rss_key(sc); 6669 t4_intr_enable(sc); 6670 } 6671 return (0); 6672 } 6673 6674 int 6675 adapter_init(struct adapter *sc) 6676 { 6677 int rc; 6678 6679 ASSERT_SYNCHRONIZED_OP(sc); 6680 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 6681 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 6682 ("%s: FULL_INIT_DONE already", __func__)); 6683 6684 rc = adapter_full_init(sc); 6685 if (rc != 0) 6686 adapter_full_uninit(sc); 6687 else 6688 sc->flags |= FULL_INIT_DONE; 6689 6690 return (rc); 6691 } 6692 6693 /* 6694 * Idempotent. 6695 */ 6696 static void 6697 adapter_full_uninit(struct adapter *sc) 6698 { 6699 int i; 6700 6701 t4_teardown_adapter_queues(sc); 6702 6703 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 6704 taskqueue_free(sc->tq[i]); 6705 sc->tq[i] = NULL; 6706 } 6707 6708 sc->flags &= ~FULL_INIT_DONE; 6709 } 6710 6711 #ifdef RSS 6712 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 6713 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 6714 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 6715 RSS_HASHTYPE_RSS_UDP_IPV6) 6716 6717 /* Translates kernel hash types to hardware. */ 6718 static int 6719 hashconfig_to_hashen(int hashconfig) 6720 { 6721 int hashen = 0; 6722 6723 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 6724 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 6725 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 6726 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 6727 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 6728 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6729 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6730 } 6731 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 6732 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 6733 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6734 } 6735 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 6736 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 6737 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 6738 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 6739 6740 return (hashen); 6741 } 6742 6743 /* Translates hardware hash types to kernel. */ 6744 static int 6745 hashen_to_hashconfig(int hashen) 6746 { 6747 int hashconfig = 0; 6748 6749 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 6750 /* 6751 * If UDP hashing was enabled it must have been enabled for 6752 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 6753 * enabling any 4-tuple hash is nonsense configuration. 6754 */ 6755 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6756 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 6757 6758 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6759 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 6760 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6761 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 6762 } 6763 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6764 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 6765 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6766 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 6767 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6768 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 6769 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6770 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 6771 6772 return (hashconfig); 6773 } 6774 #endif 6775 6776 /* 6777 * Idempotent. 6778 */ 6779 static int 6780 vi_full_init(struct vi_info *vi) 6781 { 6782 struct adapter *sc = vi->adapter; 6783 struct sge_rxq *rxq; 6784 int rc, i, j; 6785 #ifdef RSS 6786 int nbuckets = rss_getnumbuckets(); 6787 int hashconfig = rss_gethashconfig(); 6788 int extra; 6789 #endif 6790 6791 ASSERT_SYNCHRONIZED_OP(sc); 6792 6793 /* 6794 * Allocate tx/rx/fl queues for this VI. 6795 */ 6796 rc = t4_setup_vi_queues(vi); 6797 if (rc != 0) 6798 return (rc); 6799 6800 /* 6801 * Setup RSS for this VI. Save a copy of the RSS table for later use. 6802 */ 6803 if (vi->nrxq > vi->rss_size) { 6804 CH_ALERT(vi, "nrxq (%d) > hw RSS table size (%d); " 6805 "some queues will never receive traffic.\n", vi->nrxq, 6806 vi->rss_size); 6807 } else if (vi->rss_size % vi->nrxq) { 6808 CH_ALERT(vi, "nrxq (%d), hw RSS table size (%d); " 6809 "expect uneven traffic distribution.\n", vi->nrxq, 6810 vi->rss_size); 6811 } 6812 #ifdef RSS 6813 if (vi->nrxq != nbuckets) { 6814 CH_ALERT(vi, "nrxq (%d) != kernel RSS buckets (%d);" 6815 "performance will be impacted.\n", vi->nrxq, nbuckets); 6816 } 6817 #endif 6818 if (vi->rss == NULL) 6819 vi->rss = malloc(vi->rss_size * sizeof (*vi->rss), M_CXGBE, 6820 M_ZERO | M_WAITOK); 6821 for (i = 0; i < vi->rss_size;) { 6822 #ifdef RSS 6823 j = rss_get_indirection_to_bucket(i); 6824 j %= vi->nrxq; 6825 rxq = &sc->sge.rxq[vi->first_rxq + j]; 6826 vi->rss[i++] = rxq->iq.abs_id; 6827 #else 6828 for_each_rxq(vi, j, rxq) { 6829 vi->rss[i++] = rxq->iq.abs_id; 6830 if (i == vi->rss_size) 6831 break; 6832 } 6833 #endif 6834 } 6835 6836 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 6837 vi->rss, vi->rss_size); 6838 if (rc != 0) { 6839 CH_ERR(vi, "rss_config failed: %d\n", rc); 6840 return (rc); 6841 } 6842 6843 #ifdef RSS 6844 vi->hashen = hashconfig_to_hashen(hashconfig); 6845 6846 /* 6847 * We may have had to enable some hashes even though the global config 6848 * wants them disabled. This is a potential problem that must be 6849 * reported to the user. 6850 */ 6851 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 6852 6853 /* 6854 * If we consider only the supported hash types, then the enabled hashes 6855 * are a superset of the requested hashes. In other words, there cannot 6856 * be any supported hash that was requested but not enabled, but there 6857 * can be hashes that were not requested but had to be enabled. 6858 */ 6859 extra &= SUPPORTED_RSS_HASHTYPES; 6860 MPASS((extra & hashconfig) == 0); 6861 6862 if (extra) { 6863 CH_ALERT(vi, 6864 "global RSS config (0x%x) cannot be accommodated.\n", 6865 hashconfig); 6866 } 6867 if (extra & RSS_HASHTYPE_RSS_IPV4) 6868 CH_ALERT(vi, "IPv4 2-tuple hashing forced on.\n"); 6869 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 6870 CH_ALERT(vi, "TCP/IPv4 4-tuple hashing forced on.\n"); 6871 if (extra & RSS_HASHTYPE_RSS_IPV6) 6872 CH_ALERT(vi, "IPv6 2-tuple hashing forced on.\n"); 6873 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 6874 CH_ALERT(vi, "TCP/IPv6 4-tuple hashing forced on.\n"); 6875 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 6876 CH_ALERT(vi, "UDP/IPv4 4-tuple hashing forced on.\n"); 6877 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 6878 CH_ALERT(vi, "UDP/IPv6 4-tuple hashing forced on.\n"); 6879 #else 6880 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 6881 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 6882 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 6883 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 6884 #endif 6885 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 6886 0, 0); 6887 if (rc != 0) { 6888 CH_ERR(vi, "rss hash/defaultq config failed: %d\n", rc); 6889 return (rc); 6890 } 6891 6892 return (0); 6893 } 6894 6895 int 6896 vi_init(struct vi_info *vi) 6897 { 6898 int rc; 6899 6900 ASSERT_SYNCHRONIZED_OP(vi->adapter); 6901 KASSERT((vi->flags & VI_INIT_DONE) == 0, 6902 ("%s: VI_INIT_DONE already", __func__)); 6903 6904 rc = vi_full_init(vi); 6905 if (rc != 0) 6906 vi_full_uninit(vi); 6907 else 6908 vi->flags |= VI_INIT_DONE; 6909 6910 return (rc); 6911 } 6912 6913 /* 6914 * Idempotent. 6915 */ 6916 static void 6917 vi_full_uninit(struct vi_info *vi) 6918 { 6919 6920 if (vi->flags & VI_INIT_DONE) { 6921 quiesce_vi(vi); 6922 free(vi->rss, M_CXGBE); 6923 free(vi->nm_rss, M_CXGBE); 6924 } 6925 6926 t4_teardown_vi_queues(vi); 6927 vi->flags &= ~VI_INIT_DONE; 6928 } 6929 6930 static void 6931 quiesce_txq(struct sge_txq *txq) 6932 { 6933 struct sge_eq *eq = &txq->eq; 6934 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 6935 6936 MPASS(eq->flags & EQ_SW_ALLOCATED); 6937 MPASS(!(eq->flags & EQ_ENABLED)); 6938 6939 /* Wait for the mp_ring to empty. */ 6940 while (!mp_ring_is_idle(txq->r)) { 6941 mp_ring_check_drainage(txq->r, 4096); 6942 pause("rquiesce", 1); 6943 } 6944 MPASS(txq->txp.npkt == 0); 6945 6946 if (eq->flags & EQ_HW_ALLOCATED) { 6947 /* 6948 * Hardware is alive and working normally. Wait for it to 6949 * finish and then wait for the driver to catch up and reclaim 6950 * all descriptors. 6951 */ 6952 while (spg->cidx != htobe16(eq->pidx)) 6953 pause("equiesce", 1); 6954 while (eq->cidx != eq->pidx) 6955 pause("dquiesce", 1); 6956 } else { 6957 /* 6958 * Hardware is unavailable. Discard all pending tx and reclaim 6959 * descriptors directly. 6960 */ 6961 TXQ_LOCK(txq); 6962 while (eq->cidx != eq->pidx) { 6963 struct mbuf *m, *nextpkt; 6964 struct tx_sdesc *txsd; 6965 6966 txsd = &txq->sdesc[eq->cidx]; 6967 for (m = txsd->m; m != NULL; m = nextpkt) { 6968 nextpkt = m->m_nextpkt; 6969 m->m_nextpkt = NULL; 6970 m_freem(m); 6971 } 6972 IDXINCR(eq->cidx, txsd->desc_used, eq->sidx); 6973 } 6974 spg->pidx = spg->cidx = htobe16(eq->cidx); 6975 TXQ_UNLOCK(txq); 6976 } 6977 } 6978 6979 static void 6980 quiesce_wrq(struct sge_wrq *wrq) 6981 { 6982 6983 /* XXXTX */ 6984 } 6985 6986 static void 6987 quiesce_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 6988 { 6989 /* Synchronize with the interrupt handler */ 6990 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 6991 pause("iqfree", 1); 6992 6993 if (fl != NULL) { 6994 MPASS(iq->flags & IQ_HAS_FL); 6995 6996 mtx_lock(&sc->sfl_lock); 6997 FL_LOCK(fl); 6998 fl->flags |= FL_DOOMED; 6999 FL_UNLOCK(fl); 7000 callout_stop(&sc->sfl_callout); 7001 mtx_unlock(&sc->sfl_lock); 7002 7003 KASSERT((fl->flags & FL_STARVING) == 0, 7004 ("%s: still starving", __func__)); 7005 7006 /* Release all buffers if hardware is no longer available. */ 7007 if (!(iq->flags & IQ_HW_ALLOCATED)) 7008 free_fl_buffers(sc, fl); 7009 } 7010 } 7011 7012 /* 7013 * Wait for all activity on all the queues of the VI to complete. It is assumed 7014 * that no new work is being enqueued by the hardware or the driver. That part 7015 * should be arranged before calling this function. 7016 */ 7017 static void 7018 quiesce_vi(struct vi_info *vi) 7019 { 7020 int i; 7021 struct adapter *sc = vi->adapter; 7022 struct sge_rxq *rxq; 7023 struct sge_txq *txq; 7024 #ifdef TCP_OFFLOAD 7025 struct sge_ofld_rxq *ofld_rxq; 7026 #endif 7027 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7028 struct sge_ofld_txq *ofld_txq; 7029 #endif 7030 7031 if (!(vi->flags & VI_INIT_DONE)) 7032 return; 7033 7034 for_each_txq(vi, i, txq) { 7035 quiesce_txq(txq); 7036 } 7037 7038 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7039 for_each_ofld_txq(vi, i, ofld_txq) { 7040 quiesce_wrq(&ofld_txq->wrq); 7041 } 7042 #endif 7043 7044 for_each_rxq(vi, i, rxq) { 7045 quiesce_iq_fl(sc, &rxq->iq, &rxq->fl); 7046 } 7047 7048 #ifdef TCP_OFFLOAD 7049 for_each_ofld_rxq(vi, i, ofld_rxq) { 7050 quiesce_iq_fl(sc, &ofld_rxq->iq, &ofld_rxq->fl); 7051 } 7052 #endif 7053 } 7054 7055 static int 7056 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 7057 driver_intr_t *handler, void *arg, char *name) 7058 { 7059 int rc; 7060 7061 irq->rid = rid; 7062 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 7063 RF_SHAREABLE | RF_ACTIVE); 7064 if (irq->res == NULL) { 7065 device_printf(sc->dev, 7066 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 7067 return (ENOMEM); 7068 } 7069 7070 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 7071 NULL, handler, arg, &irq->tag); 7072 if (rc != 0) { 7073 device_printf(sc->dev, 7074 "failed to setup interrupt for rid %d, name %s: %d\n", 7075 rid, name, rc); 7076 } else if (name) 7077 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 7078 7079 return (rc); 7080 } 7081 7082 static int 7083 t4_free_irq(struct adapter *sc, struct irq *irq) 7084 { 7085 if (irq->tag) 7086 bus_teardown_intr(sc->dev, irq->res, irq->tag); 7087 if (irq->res) 7088 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 7089 7090 bzero(irq, sizeof(*irq)); 7091 7092 return (0); 7093 } 7094 7095 static void 7096 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 7097 { 7098 7099 regs->version = chip_id(sc) | chip_rev(sc) << 10; 7100 t4_get_regs(sc, buf, regs->len); 7101 } 7102 7103 #define A_PL_INDIR_CMD 0x1f8 7104 7105 #define S_PL_AUTOINC 31 7106 #define M_PL_AUTOINC 0x1U 7107 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 7108 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 7109 7110 #define S_PL_VFID 20 7111 #define M_PL_VFID 0xffU 7112 #define V_PL_VFID(x) ((x) << S_PL_VFID) 7113 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 7114 7115 #define S_PL_ADDR 0 7116 #define M_PL_ADDR 0xfffffU 7117 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 7118 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 7119 7120 #define A_PL_INDIR_DATA 0x1fc 7121 7122 static uint64_t 7123 read_vf_stat(struct adapter *sc, u_int vin, int reg) 7124 { 7125 u32 stats[2]; 7126 7127 if (sc->flags & IS_VF) { 7128 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 7129 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 7130 } else { 7131 mtx_assert(&sc->reg_lock, MA_OWNED); 7132 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 7133 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 7134 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 7135 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 7136 } 7137 return (((uint64_t)stats[1]) << 32 | stats[0]); 7138 } 7139 7140 static void 7141 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 7142 { 7143 7144 #define GET_STAT(name) \ 7145 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 7146 7147 if (!(sc->flags & IS_VF)) 7148 mtx_lock(&sc->reg_lock); 7149 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 7150 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 7151 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 7152 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 7153 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 7154 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 7155 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 7156 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 7157 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 7158 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 7159 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 7160 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 7161 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 7162 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 7163 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 7164 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 7165 if (!(sc->flags & IS_VF)) 7166 mtx_unlock(&sc->reg_lock); 7167 7168 #undef GET_STAT 7169 } 7170 7171 static void 7172 t4_clr_vi_stats(struct adapter *sc, u_int vin) 7173 { 7174 int reg; 7175 7176 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 7177 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 7178 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 7179 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 7180 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 7181 } 7182 7183 static void 7184 vi_refresh_stats(struct vi_info *vi) 7185 { 7186 struct timeval tv; 7187 const struct timeval interval = {0, 250000}; /* 250ms */ 7188 7189 mtx_assert(&vi->tick_mtx, MA_OWNED); 7190 7191 if (vi->flags & VI_SKIP_STATS) 7192 return; 7193 7194 getmicrotime(&tv); 7195 timevalsub(&tv, &interval); 7196 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7197 return; 7198 7199 t4_get_vi_stats(vi->adapter, vi->vin, &vi->stats); 7200 getmicrotime(&vi->last_refreshed); 7201 } 7202 7203 static void 7204 cxgbe_refresh_stats(struct vi_info *vi) 7205 { 7206 u_int i, v, tnl_cong_drops, chan_map; 7207 struct timeval tv; 7208 const struct timeval interval = {0, 250000}; /* 250ms */ 7209 struct port_info *pi; 7210 struct adapter *sc; 7211 7212 mtx_assert(&vi->tick_mtx, MA_OWNED); 7213 7214 if (vi->flags & VI_SKIP_STATS) 7215 return; 7216 7217 getmicrotime(&tv); 7218 timevalsub(&tv, &interval); 7219 if (timevalcmp(&tv, &vi->last_refreshed, <)) 7220 return; 7221 7222 pi = vi->pi; 7223 sc = vi->adapter; 7224 tnl_cong_drops = 0; 7225 t4_get_port_stats(sc, pi->port_id, &pi->stats); 7226 chan_map = pi->rx_e_chan_map; 7227 while (chan_map) { 7228 i = ffs(chan_map) - 1; 7229 mtx_lock(&sc->reg_lock); 7230 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 7231 A_TP_MIB_TNL_CNG_DROP_0 + i); 7232 mtx_unlock(&sc->reg_lock); 7233 tnl_cong_drops += v; 7234 chan_map &= ~(1 << i); 7235 } 7236 pi->tnl_cong_drops = tnl_cong_drops; 7237 getmicrotime(&vi->last_refreshed); 7238 } 7239 7240 static void 7241 cxgbe_tick(void *arg) 7242 { 7243 struct vi_info *vi = arg; 7244 7245 MPASS(IS_MAIN_VI(vi)); 7246 mtx_assert(&vi->tick_mtx, MA_OWNED); 7247 7248 cxgbe_refresh_stats(vi); 7249 callout_schedule(&vi->tick, hz); 7250 } 7251 7252 static void 7253 vi_tick(void *arg) 7254 { 7255 struct vi_info *vi = arg; 7256 7257 mtx_assert(&vi->tick_mtx, MA_OWNED); 7258 7259 vi_refresh_stats(vi); 7260 callout_schedule(&vi->tick, hz); 7261 } 7262 7263 /* 7264 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 7265 */ 7266 static char *caps_decoder[] = { 7267 "\2\001IPMI\002NCSI", /* 0: NBM */ 7268 "\2\001PPP\002QFC\003DCBX", /* 1: link */ 7269 "\2\001INGRESS\002EGRESS", /* 2: switch */ 7270 "\2\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 7271 "\006HASHFILTER\007ETHOFLD", 7272 "\2\001TOE", /* 4: TOE */ 7273 "\2\001RDDP\002RDMAC", /* 5: RDMA */ 7274 "\2\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 7275 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 7276 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 7277 "\007T10DIF" 7278 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 7279 "\2\001LOOKASIDE\002TLSKEYS\003IPSEC_INLINE" /* 7: Crypto */ 7280 "\004TLS_HW", 7281 "\2\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 7282 "\004PO_INITIATOR\005PO_TARGET", 7283 }; 7284 7285 void 7286 t4_sysctls(struct adapter *sc) 7287 { 7288 struct sysctl_ctx_list *ctx = &sc->ctx; 7289 struct sysctl_oid *oid; 7290 struct sysctl_oid_list *children, *c0; 7291 static char *doorbells = {"\2\1UDB\2WCWR\3UDBWC\4KDB"}; 7292 7293 /* 7294 * dev.t4nex.X. 7295 */ 7296 oid = device_get_sysctl_tree(sc->dev); 7297 c0 = children = SYSCTL_CHILDREN(oid); 7298 7299 sc->sc_do_rxcopy = 1; 7300 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 7301 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 7302 7303 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 7304 sc->params.nports, "# of ports"); 7305 7306 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 7307 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, doorbells, 7308 (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A", 7309 "available doorbells"); 7310 7311 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 7312 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 7313 7314 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 7315 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7316 sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val), 7317 sysctl_int_array, "A", "interrupt holdoff timer values (us)"); 7318 7319 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 7320 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 7321 sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val), 7322 sysctl_int_array, "A", "interrupt holdoff packet counter values"); 7323 7324 t4_sge_sysctls(sc, ctx, children); 7325 7326 sc->lro_timeout = 100; 7327 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 7328 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 7329 7330 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 7331 &sc->debug_flags, 0, "flags to enable runtime debugging"); 7332 7333 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 7334 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 7335 7336 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 7337 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 7338 7339 if (sc->flags & IS_VF) 7340 return; 7341 7342 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 7343 NULL, chip_rev(sc), "chip hardware revision"); 7344 7345 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 7346 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 7347 7348 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 7349 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 7350 7351 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 7352 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 7353 7354 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 7355 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 7356 7357 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 7358 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 7359 7360 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 7361 sc->er_version, 0, "expansion ROM version"); 7362 7363 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 7364 sc->bs_version, 0, "bootstrap firmware version"); 7365 7366 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 7367 NULL, sc->params.scfg_vers, "serial config version"); 7368 7369 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 7370 NULL, sc->params.vpd_vers, "VPD version"); 7371 7372 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 7373 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 7374 7375 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 7376 sc->cfcsum, "config file checksum"); 7377 7378 #define SYSCTL_CAP(name, n, text) \ 7379 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 7380 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, caps_decoder[n], \ 7381 (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \ 7382 "available " text " capabilities") 7383 7384 SYSCTL_CAP(nbmcaps, 0, "NBM"); 7385 SYSCTL_CAP(linkcaps, 1, "link"); 7386 SYSCTL_CAP(switchcaps, 2, "switch"); 7387 SYSCTL_CAP(niccaps, 3, "NIC"); 7388 SYSCTL_CAP(toecaps, 4, "TCP offload"); 7389 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 7390 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 7391 SYSCTL_CAP(cryptocaps, 7, "crypto"); 7392 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 7393 #undef SYSCTL_CAP 7394 7395 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 7396 NULL, sc->tids.nftids, "number of filters"); 7397 7398 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 7399 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7400 sysctl_temperature, "I", "chip temperature (in Celsius)"); 7401 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor", 7402 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7403 sysctl_reset_sensor, "I", "reset the chip's temperature sensor."); 7404 7405 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", 7406 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7407 sysctl_loadavg, "A", 7408 "microprocessor load averages (debug firmwares only)"); 7409 7410 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd", 7411 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd, 7412 "I", "core Vdd (in mV)"); 7413 7414 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 7415 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, LOCAL_CPUS, 7416 sysctl_cpus, "A", "local CPUs"); 7417 7418 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 7419 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, INTR_CPUS, 7420 sysctl_cpus, "A", "preferred CPUs for interrupts"); 7421 7422 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW, 7423 &sc->swintr, 0, "software triggered interrupts"); 7424 7425 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset", 7426 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_reset, "I", 7427 "1 = reset adapter, 0 = zero reset counter"); 7428 7429 /* 7430 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 7431 */ 7432 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 7433 CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL, 7434 "logs and miscellaneous information"); 7435 children = SYSCTL_CHILDREN(oid); 7436 7437 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 7438 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7439 sysctl_cctrl, "A", "congestion control"); 7440 7441 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 7442 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7443 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 7444 7445 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 7446 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7447 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 7448 7449 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 7450 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7451 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 7452 7453 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 7454 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 3, 7455 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 7456 7457 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 7458 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 4, 7459 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 7460 7461 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 7462 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 5, 7463 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 7464 7465 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 7466 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7467 sysctl_cim_la, "A", "CIM logic analyzer"); 7468 7469 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 7470 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7471 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 7472 7473 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 7474 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7475 0 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 7476 7477 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 7478 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7479 1 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 7480 7481 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 7482 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7483 2 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 7484 7485 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 7486 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7487 3 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 7488 7489 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 7490 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7491 4 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 7492 7493 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 7494 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7495 5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 7496 7497 if (chip_id(sc) > CHELSIO_T4) { 7498 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 7499 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7500 6 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7501 "CIM OBQ 6 (SGE0-RX)"); 7502 7503 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 7504 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7505 7 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", 7506 "CIM OBQ 7 (SGE1-RX)"); 7507 } 7508 7509 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 7510 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7511 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 7512 7513 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 7514 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7515 sysctl_cim_qcfg, "A", "CIM queue configuration"); 7516 7517 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 7518 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7519 sysctl_cpl_stats, "A", "CPL statistics"); 7520 7521 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 7522 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7523 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 7524 7525 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tid_stats", 7526 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7527 sysctl_tid_stats, "A", "tid stats"); 7528 7529 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 7530 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7531 sysctl_devlog, "A", "firmware's device log"); 7532 7533 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 7534 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7535 sysctl_fcoe_stats, "A", "FCoE statistics"); 7536 7537 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 7538 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7539 sysctl_hw_sched, "A", "hardware scheduler "); 7540 7541 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 7542 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7543 sysctl_l2t, "A", "hardware L2 table"); 7544 7545 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 7546 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7547 sysctl_smt, "A", "hardware source MAC table"); 7548 7549 #ifdef INET6 7550 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 7551 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7552 sysctl_clip, "A", "active CLIP table entries"); 7553 #endif 7554 7555 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 7556 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7557 sysctl_lb_stats, "A", "loopback statistics"); 7558 7559 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 7560 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7561 sysctl_meminfo, "A", "memory regions"); 7562 7563 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 7564 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7565 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 7566 "A", "MPS TCAM entries"); 7567 7568 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 7569 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7570 sysctl_path_mtus, "A", "path MTUs"); 7571 7572 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 7573 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7574 sysctl_pm_stats, "A", "PM statistics"); 7575 7576 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 7577 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7578 sysctl_rdma_stats, "A", "RDMA statistics"); 7579 7580 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 7581 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7582 sysctl_tcp_stats, "A", "TCP statistics"); 7583 7584 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 7585 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7586 sysctl_tids, "A", "TID information"); 7587 7588 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 7589 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7590 sysctl_tp_err_stats, "A", "TP error statistics"); 7591 7592 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tnl_stats", 7593 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7594 sysctl_tnl_stats, "A", "TP tunnel statistics"); 7595 7596 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 7597 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, 7598 sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask"); 7599 7600 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 7601 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7602 sysctl_tp_la, "A", "TP logic analyzer"); 7603 7604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 7605 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7606 sysctl_tx_rate, "A", "Tx rate"); 7607 7608 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 7609 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7610 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 7611 7612 if (chip_id(sc) >= CHELSIO_T5) { 7613 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 7614 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7615 sysctl_wcwr_stats, "A", "write combined work requests"); 7616 } 7617 7618 #ifdef KERN_TLS 7619 if (is_ktls(sc)) { 7620 /* 7621 * dev.t4nex.0.tls. 7622 */ 7623 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls", 7624 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters"); 7625 children = SYSCTL_CHILDREN(oid); 7626 7627 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys", 7628 CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS " 7629 "keys in work requests (1) or attempt to store TLS keys " 7630 "in card memory."); 7631 7632 if (is_t6(sc)) 7633 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs", 7634 CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to " 7635 "combine TCB field updates with TLS record work " 7636 "requests."); 7637 } 7638 #endif 7639 7640 #ifdef TCP_OFFLOAD 7641 if (is_offload(sc)) { 7642 int i; 7643 char s[4]; 7644 7645 /* 7646 * dev.t4nex.X.toe. 7647 */ 7648 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", 7649 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters"); 7650 children = SYSCTL_CHILDREN(oid); 7651 7652 sc->tt.cong_algorithm = -1; 7653 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 7654 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 7655 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 7656 "3 = highspeed)"); 7657 7658 sc->tt.sndbuf = -1; 7659 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 7660 &sc->tt.sndbuf, 0, "hardware send buffer"); 7661 7662 sc->tt.ddp = 0; 7663 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", 7664 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, ""); 7665 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW, 7666 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)"); 7667 7668 sc->tt.rx_coalesce = -1; 7669 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 7670 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 7671 7672 sc->tt.tls = 0; 7673 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT | 7674 CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, sysctl_tls, "I", 7675 "Inline TLS allowed"); 7676 7677 sc->tt.tx_align = -1; 7678 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 7679 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 7680 7681 sc->tt.tx_zcopy = 0; 7682 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 7683 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 7684 "Enable zero-copy aio_write(2)"); 7685 7686 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 7687 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7688 "cop_managed_offloading", CTLFLAG_RW, 7689 &sc->tt.cop_managed_offloading, 0, 7690 "COP (Connection Offload Policy) controls all TOE offload"); 7691 7692 sc->tt.autorcvbuf_inc = 16 * 1024; 7693 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc", 7694 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0, 7695 "autorcvbuf increment"); 7696 7697 sc->tt.update_hc_on_pmtu_change = 1; 7698 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7699 "update_hc_on_pmtu_change", CTLFLAG_RW, 7700 &sc->tt.update_hc_on_pmtu_change, 0, 7701 "Update hostcache entry if the PMTU changes"); 7702 7703 sc->tt.iso = 1; 7704 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iso", CTLFLAG_RW, 7705 &sc->tt.iso, 0, "Enable iSCSI segmentation offload"); 7706 7707 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 7708 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7709 sysctl_tp_tick, "A", "TP timer tick (us)"); 7710 7711 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 7712 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1, 7713 sysctl_tp_tick, "A", "TCP timestamp tick (us)"); 7714 7715 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 7716 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2, 7717 sysctl_tp_tick, "A", "DACK tick (us)"); 7718 7719 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 7720 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 7721 sysctl_tp_dack_timer, "IU", "DACK timer (us)"); 7722 7723 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 7724 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7725 A_TP_RXT_MIN, sysctl_tp_timer, "LU", 7726 "Minimum retransmit interval (us)"); 7727 7728 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 7729 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7730 A_TP_RXT_MAX, sysctl_tp_timer, "LU", 7731 "Maximum retransmit interval (us)"); 7732 7733 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 7734 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7735 A_TP_PERS_MIN, sysctl_tp_timer, "LU", 7736 "Persist timer min (us)"); 7737 7738 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 7739 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7740 A_TP_PERS_MAX, sysctl_tp_timer, "LU", 7741 "Persist timer max (us)"); 7742 7743 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 7744 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7745 A_TP_KEEP_IDLE, sysctl_tp_timer, "LU", 7746 "Keepalive idle timer (us)"); 7747 7748 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 7749 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7750 A_TP_KEEP_INTVL, sysctl_tp_timer, "LU", 7751 "Keepalive interval timer (us)"); 7752 7753 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 7754 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7755 A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)"); 7756 7757 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 7758 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7759 A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU", 7760 "FINWAIT2 timer (us)"); 7761 7762 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 7763 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7764 S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU", 7765 "Number of SYN retransmissions before abort"); 7766 7767 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 7768 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7769 S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU", 7770 "Number of retransmissions before abort"); 7771 7772 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 7773 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7774 S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU", 7775 "Number of keepalive probes before abort"); 7776 7777 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 7778 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7779 "TOE retransmit backoffs"); 7780 children = SYSCTL_CHILDREN(oid); 7781 for (i = 0; i < 16; i++) { 7782 snprintf(s, sizeof(s), "%u", i); 7783 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 7784 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7785 i, sysctl_tp_backoff, "IU", 7786 "TOE retransmit backoff"); 7787 } 7788 } 7789 #endif 7790 } 7791 7792 void 7793 vi_sysctls(struct vi_info *vi) 7794 { 7795 struct sysctl_ctx_list *ctx = &vi->ctx; 7796 struct sysctl_oid *oid; 7797 struct sysctl_oid_list *children; 7798 7799 /* 7800 * dev.v?(cxgbe|cxl).X. 7801 */ 7802 oid = device_get_sysctl_tree(vi->dev); 7803 children = SYSCTL_CHILDREN(oid); 7804 7805 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 7806 vi->viid, "VI identifer"); 7807 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 7808 &vi->nrxq, 0, "# of rx queues"); 7809 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 7810 &vi->ntxq, 0, "# of tx queues"); 7811 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 7812 &vi->first_rxq, 0, "index of first rx queue"); 7813 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 7814 &vi->first_txq, 0, "index of first tx queue"); 7815 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 7816 vi->rss_base, "start of RSS indirection table"); 7817 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 7818 vi->rss_size, "size of RSS indirection table"); 7819 7820 if (IS_MAIN_VI(vi)) { 7821 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 7822 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7823 sysctl_noflowq, "IU", 7824 "Reserve queue 0 for non-flowid packets"); 7825 } 7826 7827 if (vi->adapter->flags & IS_VF) { 7828 MPASS(vi->flags & TX_USES_VM_WR); 7829 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_vm_wr", CTLFLAG_RD, 7830 NULL, 1, "use VM work requests for transmit"); 7831 } else { 7832 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_vm_wr", 7833 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7834 sysctl_tx_vm_wr, "I", "use VM work requestes for transmit"); 7835 } 7836 7837 #ifdef TCP_OFFLOAD 7838 if (vi->nofldrxq != 0) { 7839 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 7840 &vi->nofldrxq, 0, 7841 "# of rx queues for offloaded TCP connections"); 7842 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 7843 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 7844 "index of first TOE rx queue"); 7845 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 7846 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7847 sysctl_holdoff_tmr_idx_ofld, "I", 7848 "holdoff timer index for TOE queues"); 7849 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 7850 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7851 sysctl_holdoff_pktc_idx_ofld, "I", 7852 "holdoff packet counter index for TOE queues"); 7853 } 7854 #endif 7855 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 7856 if (vi->nofldtxq != 0) { 7857 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 7858 &vi->nofldtxq, 0, 7859 "# of tx queues for TOE/ETHOFLD"); 7860 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 7861 CTLFLAG_RD, &vi->first_ofld_txq, 0, 7862 "index of first TOE/ETHOFLD tx queue"); 7863 } 7864 #endif 7865 #ifdef DEV_NETMAP 7866 if (vi->nnmrxq != 0) { 7867 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 7868 &vi->nnmrxq, 0, "# of netmap rx queues"); 7869 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 7870 &vi->nnmtxq, 0, "# of netmap tx queues"); 7871 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 7872 CTLFLAG_RD, &vi->first_nm_rxq, 0, 7873 "index of first netmap rx queue"); 7874 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 7875 CTLFLAG_RD, &vi->first_nm_txq, 0, 7876 "index of first netmap tx queue"); 7877 } 7878 #endif 7879 7880 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 7881 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7882 sysctl_holdoff_tmr_idx, "I", "holdoff timer index"); 7883 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 7884 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7885 sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index"); 7886 7887 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 7888 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7889 sysctl_qsize_rxq, "I", "rx queue size"); 7890 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 7891 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0, 7892 sysctl_qsize_txq, "I", "tx queue size"); 7893 } 7894 7895 static void 7896 cxgbe_sysctls(struct port_info *pi) 7897 { 7898 struct sysctl_ctx_list *ctx = &pi->ctx; 7899 struct sysctl_oid *oid; 7900 struct sysctl_oid_list *children, *children2; 7901 struct adapter *sc = pi->adapter; 7902 int i; 7903 char name[16]; 7904 static char *tc_flags = {"\2\1USER"}; 7905 7906 /* 7907 * dev.cxgbe.X. 7908 */ 7909 oid = device_get_sysctl_tree(pi->dev); 7910 children = SYSCTL_CHILDREN(oid); 7911 7912 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", 7913 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 7914 sysctl_linkdnrc, "A", "reason why link is down"); 7915 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 7916 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 7917 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0, 7918 sysctl_btphy, "I", "PHY temperature (in Celsius)"); 7919 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 7920 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 1, 7921 sysctl_btphy, "I", "PHY firmware version"); 7922 } 7923 7924 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 7925 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7926 sysctl_pause_settings, "A", 7927 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 7928 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "link_fec", 7929 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_link_fec, "A", 7930 "FEC in use on the link"); 7931 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "requested_fec", 7932 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7933 sysctl_requested_fec, "A", 7934 "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)"); 7935 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec", 7936 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_module_fec, "A", 7937 "FEC recommended by the cable/transceiver"); 7938 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 7939 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7940 sysctl_autoneg, "I", 7941 "autonegotiation (-1 = not supported)"); 7942 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "force_fec", 7943 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0, 7944 sysctl_force_fec, "I", "when to use FORCE_FEC bit for link config"); 7945 7946 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rcaps", CTLFLAG_RD, 7947 &pi->link_cfg.requested_caps, 0, "L1 config requested by driver"); 7948 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD, 7949 &pi->link_cfg.pcaps, 0, "port capabilities"); 7950 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD, 7951 &pi->link_cfg.acaps, 0, "advertised capabilities"); 7952 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD, 7953 &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities"); 7954 7955 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 7956 port_top_speed(pi), "max speed (in Gbps)"); 7957 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 7958 pi->mps_bg_map, "MPS buffer group map"); 7959 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 7960 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 7961 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_c_chan", CTLFLAG_RD, NULL, 7962 pi->rx_c_chan, "TP rx c-channel"); 7963 7964 if (sc->flags & IS_VF) 7965 return; 7966 7967 /* 7968 * dev.(cxgbe|cxl).X.tc. 7969 */ 7970 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", 7971 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7972 "Tx scheduler traffic classes (cl_rl)"); 7973 children2 = SYSCTL_CHILDREN(oid); 7974 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 7975 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 7976 "pktsize for per-flow cl-rl (0 means up to the driver )"); 7977 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 7978 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 7979 "burstsize for per-flow cl-rl (0 means up to the driver)"); 7980 for (i = 0; i < sc->params.nsched_cls; i++) { 7981 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 7982 7983 snprintf(name, sizeof(name), "%d", i); 7984 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 7985 SYSCTL_CHILDREN(oid), OID_AUTO, name, 7986 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class")); 7987 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "state", 7988 CTLFLAG_RD, &tc->state, 0, "current state"); 7989 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 7990 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, tc_flags, 7991 (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags"); 7992 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 7993 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 7994 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 7995 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 7996 (pi->port_id << 16) | i, sysctl_tc_params, "A", 7997 "traffic class parameters"); 7998 } 7999 8000 /* 8001 * dev.cxgbe.X.stats. 8002 */ 8003 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 8004 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics"); 8005 children = SYSCTL_CHILDREN(oid); 8006 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 8007 &pi->tx_parse_error, 0, 8008 "# of tx packets with invalid length or # of segments"); 8009 8010 #define T4_REGSTAT(name, stat, desc) \ 8011 SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \ 8012 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \ 8013 (is_t4(sc) ? PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##stat##_L) : \ 8014 T5_PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##stat##_L)), \ 8015 sysctl_handle_t4_reg64, "QU", desc) 8016 8017 /* We get these from port_stats and they may be stale by up to 1s */ 8018 #define T4_PORTSTAT(name, desc) \ 8019 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 8020 &pi->stats.name, desc) 8021 8022 T4_REGSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames"); 8023 T4_REGSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames"); 8024 T4_REGSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames"); 8025 T4_REGSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames"); 8026 T4_REGSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames"); 8027 T4_REGSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames"); 8028 T4_REGSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range"); 8029 T4_REGSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range"); 8030 T4_REGSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range"); 8031 T4_REGSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range"); 8032 T4_REGSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range"); 8033 T4_REGSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range"); 8034 T4_REGSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range"); 8035 T4_REGSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames"); 8036 T4_REGSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted"); 8037 T4_REGSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted"); 8038 T4_REGSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted"); 8039 T4_REGSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted"); 8040 T4_REGSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted"); 8041 T4_REGSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted"); 8042 T4_REGSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted"); 8043 T4_REGSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted"); 8044 T4_REGSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted"); 8045 8046 T4_REGSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames"); 8047 T4_REGSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames"); 8048 T4_REGSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames"); 8049 T4_REGSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames"); 8050 T4_REGSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames"); 8051 T4_REGSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU"); 8052 T4_REGSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames"); 8053 if (is_t6(sc)) { 8054 T4_PORTSTAT(rx_fcs_err, 8055 "# of frames received with bad FCS since last link up"); 8056 } else { 8057 T4_REGSTAT(rx_fcs_err, RX_PORT_CRC_ERROR, 8058 "# of frames received with bad FCS"); 8059 } 8060 T4_REGSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error"); 8061 T4_REGSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors"); 8062 T4_REGSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received"); 8063 T4_REGSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range"); 8064 T4_REGSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range"); 8065 T4_REGSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range"); 8066 T4_REGSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range"); 8067 T4_REGSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range"); 8068 T4_REGSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range"); 8069 T4_REGSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range"); 8070 T4_REGSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received"); 8071 T4_REGSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received"); 8072 T4_REGSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received"); 8073 T4_REGSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received"); 8074 T4_REGSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received"); 8075 T4_REGSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received"); 8076 T4_REGSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received"); 8077 T4_REGSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received"); 8078 T4_REGSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received"); 8079 8080 T4_PORTSTAT(rx_ovflow0, "# drops due to buffer-group 0 overflows"); 8081 T4_PORTSTAT(rx_ovflow1, "# drops due to buffer-group 1 overflows"); 8082 T4_PORTSTAT(rx_ovflow2, "# drops due to buffer-group 2 overflows"); 8083 T4_PORTSTAT(rx_ovflow3, "# drops due to buffer-group 3 overflows"); 8084 T4_PORTSTAT(rx_trunc0, "# of buffer-group 0 truncated packets"); 8085 T4_PORTSTAT(rx_trunc1, "# of buffer-group 1 truncated packets"); 8086 T4_PORTSTAT(rx_trunc2, "# of buffer-group 2 truncated packets"); 8087 T4_PORTSTAT(rx_trunc3, "# of buffer-group 3 truncated packets"); 8088 8089 #undef T4_REGSTAT 8090 #undef T4_PORTSTAT 8091 } 8092 8093 static int 8094 sysctl_int_array(SYSCTL_HANDLER_ARGS) 8095 { 8096 int rc, *i, space = 0; 8097 struct sbuf sb; 8098 8099 sbuf_new_for_sysctl(&sb, NULL, 64, req); 8100 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 8101 if (space) 8102 sbuf_printf(&sb, " "); 8103 sbuf_printf(&sb, "%d", *i); 8104 space = 1; 8105 } 8106 rc = sbuf_finish(&sb); 8107 sbuf_delete(&sb); 8108 return (rc); 8109 } 8110 8111 static int 8112 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 8113 { 8114 int rc; 8115 struct sbuf *sb; 8116 8117 rc = sysctl_wire_old_buffer(req, 0); 8118 if (rc != 0) 8119 return(rc); 8120 8121 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8122 if (sb == NULL) 8123 return (ENOMEM); 8124 8125 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 8126 rc = sbuf_finish(sb); 8127 sbuf_delete(sb); 8128 8129 return (rc); 8130 } 8131 8132 static int 8133 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 8134 { 8135 int rc; 8136 struct sbuf *sb; 8137 8138 rc = sysctl_wire_old_buffer(req, 0); 8139 if (rc != 0) 8140 return(rc); 8141 8142 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8143 if (sb == NULL) 8144 return (ENOMEM); 8145 8146 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 8147 rc = sbuf_finish(sb); 8148 sbuf_delete(sb); 8149 8150 return (rc); 8151 } 8152 8153 static int 8154 sysctl_btphy(SYSCTL_HANDLER_ARGS) 8155 { 8156 struct port_info *pi = arg1; 8157 int op = arg2; 8158 struct adapter *sc = pi->adapter; 8159 u_int v; 8160 int rc; 8161 8162 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 8163 if (rc) 8164 return (rc); 8165 if (hw_off_limits(sc)) 8166 rc = ENXIO; 8167 else { 8168 /* XXX: magic numbers */ 8169 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, 8170 op ? 0x20 : 0xc820, &v); 8171 } 8172 end_synchronized_op(sc, 0); 8173 if (rc) 8174 return (rc); 8175 if (op == 0) 8176 v /= 256; 8177 8178 rc = sysctl_handle_int(oidp, &v, 0, req); 8179 return (rc); 8180 } 8181 8182 static int 8183 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 8184 { 8185 struct vi_info *vi = arg1; 8186 int rc, val; 8187 8188 val = vi->rsrv_noflowq; 8189 rc = sysctl_handle_int(oidp, &val, 0, req); 8190 if (rc != 0 || req->newptr == NULL) 8191 return (rc); 8192 8193 if ((val >= 1) && (vi->ntxq > 1)) 8194 vi->rsrv_noflowq = 1; 8195 else 8196 vi->rsrv_noflowq = 0; 8197 8198 return (rc); 8199 } 8200 8201 static int 8202 sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS) 8203 { 8204 struct vi_info *vi = arg1; 8205 struct adapter *sc = vi->adapter; 8206 int rc, val, i; 8207 8208 MPASS(!(sc->flags & IS_VF)); 8209 8210 val = vi->flags & TX_USES_VM_WR ? 1 : 0; 8211 rc = sysctl_handle_int(oidp, &val, 0, req); 8212 if (rc != 0 || req->newptr == NULL) 8213 return (rc); 8214 8215 if (val != 0 && val != 1) 8216 return (EINVAL); 8217 8218 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8219 "t4txvm"); 8220 if (rc) 8221 return (rc); 8222 if (hw_off_limits(sc)) 8223 rc = ENXIO; 8224 else if (vi->ifp->if_drv_flags & IFF_DRV_RUNNING) { 8225 /* 8226 * We don't want parse_pkt to run with one setting (VF or PF) 8227 * and then eth_tx to see a different setting but still use 8228 * stale information calculated by parse_pkt. 8229 */ 8230 rc = EBUSY; 8231 } else { 8232 struct port_info *pi = vi->pi; 8233 struct sge_txq *txq; 8234 uint32_t ctrl0; 8235 uint8_t npkt = sc->params.max_pkts_per_eth_tx_pkts_wr; 8236 8237 if (val) { 8238 vi->flags |= TX_USES_VM_WR; 8239 vi->ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_VM_TSO; 8240 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8241 V_TXPKT_INTF(pi->tx_chan)); 8242 if (!(sc->flags & IS_VF)) 8243 npkt--; 8244 } else { 8245 vi->flags &= ~TX_USES_VM_WR; 8246 vi->ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO; 8247 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 8248 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 8249 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 8250 } 8251 for_each_txq(vi, i, txq) { 8252 txq->cpl_ctrl0 = ctrl0; 8253 txq->txp.max_npkt = npkt; 8254 } 8255 } 8256 end_synchronized_op(sc, LOCK_HELD); 8257 return (rc); 8258 } 8259 8260 static int 8261 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 8262 { 8263 struct vi_info *vi = arg1; 8264 struct adapter *sc = vi->adapter; 8265 int idx, rc, i; 8266 struct sge_rxq *rxq; 8267 uint8_t v; 8268 8269 idx = vi->tmr_idx; 8270 8271 rc = sysctl_handle_int(oidp, &idx, 0, req); 8272 if (rc != 0 || req->newptr == NULL) 8273 return (rc); 8274 8275 if (idx < 0 || idx >= SGE_NTIMERS) 8276 return (EINVAL); 8277 8278 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8279 "t4tmr"); 8280 if (rc) 8281 return (rc); 8282 8283 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 8284 for_each_rxq(vi, i, rxq) { 8285 #ifdef atomic_store_rel_8 8286 atomic_store_rel_8(&rxq->iq.intr_params, v); 8287 #else 8288 rxq->iq.intr_params = v; 8289 #endif 8290 } 8291 vi->tmr_idx = idx; 8292 8293 end_synchronized_op(sc, LOCK_HELD); 8294 return (0); 8295 } 8296 8297 static int 8298 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 8299 { 8300 struct vi_info *vi = arg1; 8301 struct adapter *sc = vi->adapter; 8302 int idx, rc; 8303 8304 idx = vi->pktc_idx; 8305 8306 rc = sysctl_handle_int(oidp, &idx, 0, req); 8307 if (rc != 0 || req->newptr == NULL) 8308 return (rc); 8309 8310 if (idx < -1 || idx >= SGE_NCOUNTERS) 8311 return (EINVAL); 8312 8313 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8314 "t4pktc"); 8315 if (rc) 8316 return (rc); 8317 8318 if (vi->flags & VI_INIT_DONE) 8319 rc = EBUSY; /* cannot be changed once the queues are created */ 8320 else 8321 vi->pktc_idx = idx; 8322 8323 end_synchronized_op(sc, LOCK_HELD); 8324 return (rc); 8325 } 8326 8327 static int 8328 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 8329 { 8330 struct vi_info *vi = arg1; 8331 struct adapter *sc = vi->adapter; 8332 int qsize, rc; 8333 8334 qsize = vi->qsize_rxq; 8335 8336 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8337 if (rc != 0 || req->newptr == NULL) 8338 return (rc); 8339 8340 if (qsize < 128 || (qsize & 7)) 8341 return (EINVAL); 8342 8343 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8344 "t4rxqs"); 8345 if (rc) 8346 return (rc); 8347 8348 if (vi->flags & VI_INIT_DONE) 8349 rc = EBUSY; /* cannot be changed once the queues are created */ 8350 else 8351 vi->qsize_rxq = qsize; 8352 8353 end_synchronized_op(sc, LOCK_HELD); 8354 return (rc); 8355 } 8356 8357 static int 8358 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 8359 { 8360 struct vi_info *vi = arg1; 8361 struct adapter *sc = vi->adapter; 8362 int qsize, rc; 8363 8364 qsize = vi->qsize_txq; 8365 8366 rc = sysctl_handle_int(oidp, &qsize, 0, req); 8367 if (rc != 0 || req->newptr == NULL) 8368 return (rc); 8369 8370 if (qsize < 128 || qsize > 65536) 8371 return (EINVAL); 8372 8373 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 8374 "t4txqs"); 8375 if (rc) 8376 return (rc); 8377 8378 if (vi->flags & VI_INIT_DONE) 8379 rc = EBUSY; /* cannot be changed once the queues are created */ 8380 else 8381 vi->qsize_txq = qsize; 8382 8383 end_synchronized_op(sc, LOCK_HELD); 8384 return (rc); 8385 } 8386 8387 static int 8388 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 8389 { 8390 struct port_info *pi = arg1; 8391 struct adapter *sc = pi->adapter; 8392 struct link_config *lc = &pi->link_cfg; 8393 int rc; 8394 8395 if (req->newptr == NULL) { 8396 struct sbuf *sb; 8397 static char *bits = "\2\1RX\2TX\3AUTO"; 8398 8399 rc = sysctl_wire_old_buffer(req, 0); 8400 if (rc != 0) 8401 return(rc); 8402 8403 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8404 if (sb == NULL) 8405 return (ENOMEM); 8406 8407 if (lc->link_ok) { 8408 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 8409 (lc->requested_fc & PAUSE_AUTONEG), bits); 8410 } else { 8411 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 8412 PAUSE_RX | PAUSE_AUTONEG), bits); 8413 } 8414 rc = sbuf_finish(sb); 8415 sbuf_delete(sb); 8416 } else { 8417 char s[2]; 8418 int n; 8419 8420 s[0] = '' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 8421 PAUSE_AUTONEG)); 8422 s[1] = 0; 8423 8424 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8425 if (rc != 0) 8426 return(rc); 8427 8428 if (s[1] != 0) 8429 return (EINVAL); 8430 if (s[0] < '' || s[0] > '9') 8431 return (EINVAL); /* not a number */ 8432 n = s[0] - ''; 8433 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 8434 return (EINVAL); /* some other bit is set too */ 8435 8436 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8437 "t4PAUSE"); 8438 if (rc) 8439 return (rc); 8440 if (!hw_off_limits(sc)) { 8441 PORT_LOCK(pi); 8442 lc->requested_fc = n; 8443 fixup_link_config(pi); 8444 if (pi->up_vis > 0) 8445 rc = apply_link_config(pi); 8446 set_current_media(pi); 8447 PORT_UNLOCK(pi); 8448 } 8449 end_synchronized_op(sc, 0); 8450 } 8451 8452 return (rc); 8453 } 8454 8455 static int 8456 sysctl_link_fec(SYSCTL_HANDLER_ARGS) 8457 { 8458 struct port_info *pi = arg1; 8459 struct link_config *lc = &pi->link_cfg; 8460 int rc; 8461 struct sbuf *sb; 8462 static char *bits = "\2\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2"; 8463 8464 rc = sysctl_wire_old_buffer(req, 0); 8465 if (rc != 0) 8466 return(rc); 8467 8468 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8469 if (sb == NULL) 8470 return (ENOMEM); 8471 if (lc->link_ok) 8472 sbuf_printf(sb, "%b", lc->fec, bits); 8473 else 8474 sbuf_printf(sb, "no link"); 8475 rc = sbuf_finish(sb); 8476 sbuf_delete(sb); 8477 8478 return (rc); 8479 } 8480 8481 static int 8482 sysctl_requested_fec(SYSCTL_HANDLER_ARGS) 8483 { 8484 struct port_info *pi = arg1; 8485 struct adapter *sc = pi->adapter; 8486 struct link_config *lc = &pi->link_cfg; 8487 int rc; 8488 int8_t old; 8489 8490 if (req->newptr == NULL) { 8491 struct sbuf *sb; 8492 static char *bits = "\2\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2" 8493 "\5RSVD3\6auto\7module"; 8494 8495 rc = sysctl_wire_old_buffer(req, 0); 8496 if (rc != 0) 8497 return(rc); 8498 8499 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8500 if (sb == NULL) 8501 return (ENOMEM); 8502 8503 sbuf_printf(sb, "%b", lc->requested_fec, bits); 8504 rc = sbuf_finish(sb); 8505 sbuf_delete(sb); 8506 } else { 8507 char s[8]; 8508 int n; 8509 8510 snprintf(s, sizeof(s), "%d", 8511 lc->requested_fec == FEC_AUTO ? -1 : 8512 lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE)); 8513 8514 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 8515 if (rc != 0) 8516 return(rc); 8517 8518 n = strtol(&s[0], NULL, 0); 8519 if (n < 0 || n & FEC_AUTO) 8520 n = FEC_AUTO; 8521 else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE)) 8522 return (EINVAL);/* some other bit is set too */ 8523 8524 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8525 "t4reqf"); 8526 if (rc) 8527 return (rc); 8528 PORT_LOCK(pi); 8529 old = lc->requested_fec; 8530 if (n == FEC_AUTO) 8531 lc->requested_fec = FEC_AUTO; 8532 else if (n == 0 || n == FEC_NONE) 8533 lc->requested_fec = FEC_NONE; 8534 else { 8535 if ((lc->pcaps | 8536 V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) != 8537 lc->pcaps) { 8538 rc = ENOTSUP; 8539 goto done; 8540 } 8541 lc->requested_fec = n & (M_FW_PORT_CAP32_FEC | 8542 FEC_MODULE); 8543 } 8544 if (!hw_off_limits(sc)) { 8545 fixup_link_config(pi); 8546 if (pi->up_vis > 0) { 8547 rc = apply_link_config(pi); 8548 if (rc != 0) { 8549 lc->requested_fec = old; 8550 if (rc == FW_EPROTO) 8551 rc = ENOTSUP; 8552 } 8553 } 8554 } 8555 done: 8556 PORT_UNLOCK(pi); 8557 end_synchronized_op(sc, 0); 8558 } 8559 8560 return (rc); 8561 } 8562 8563 static int 8564 sysctl_module_fec(SYSCTL_HANDLER_ARGS) 8565 { 8566 struct port_info *pi = arg1; 8567 struct adapter *sc = pi->adapter; 8568 struct link_config *lc = &pi->link_cfg; 8569 int rc; 8570 int8_t fec; 8571 struct sbuf *sb; 8572 static char *bits = "\2\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3"; 8573 8574 rc = sysctl_wire_old_buffer(req, 0); 8575 if (rc != 0) 8576 return (rc); 8577 8578 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 8579 if (sb == NULL) 8580 return (ENOMEM); 8581 8582 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) { 8583 rc = EBUSY; 8584 goto done; 8585 } 8586 if (hw_off_limits(sc)) { 8587 rc = ENXIO; 8588 goto done; 8589 } 8590 PORT_LOCK(pi); 8591 if (pi->up_vis == 0) { 8592 /* 8593 * If all the interfaces are administratively down the firmware 8594 * does not report transceiver changes. Refresh port info here. 8595 * This is the only reason we have a synchronized op in this 8596 * function. Just PORT_LOCK would have been enough otherwise. 8597 */ 8598 t4_update_port_info(pi); 8599 } 8600 8601 fec = lc->fec_hint; 8602 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE || 8603 !fec_supported(lc->pcaps)) { 8604 sbuf_printf(sb, "n/a"); 8605 } else { 8606 if (fec == 0) 8607 fec = FEC_NONE; 8608 sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits); 8609 } 8610 rc = sbuf_finish(sb); 8611 PORT_UNLOCK(pi); 8612 done: 8613 sbuf_delete(sb); 8614 end_synchronized_op(sc, 0); 8615 8616 return (rc); 8617 } 8618 8619 static int 8620 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 8621 { 8622 struct port_info *pi = arg1; 8623 struct adapter *sc = pi->adapter; 8624 struct link_config *lc = &pi->link_cfg; 8625 int rc, val; 8626 8627 if (lc->pcaps & FW_PORT_CAP32_ANEG) 8628 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 8629 else 8630 val = -1; 8631 rc = sysctl_handle_int(oidp, &val, 0, req); 8632 if (rc != 0 || req->newptr == NULL) 8633 return (rc); 8634 if (val == 0) 8635 val = AUTONEG_DISABLE; 8636 else if (val == 1) 8637 val = AUTONEG_ENABLE; 8638 else 8639 val = AUTONEG_AUTO; 8640 8641 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 8642 "t4aneg"); 8643 if (rc) 8644 return (rc); 8645 PORT_LOCK(pi); 8646 if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) { 8647 rc = ENOTSUP; 8648 goto done; 8649 } 8650 lc->requested_aneg = val; 8651 if (!hw_off_limits(sc)) { 8652 fixup_link_config(pi); 8653 if (pi->up_vis > 0) 8654 rc = apply_link_config(pi); 8655 set_current_media(pi); 8656 } 8657 done: 8658 PORT_UNLOCK(pi); 8659 end_synchronized_op(sc, 0); 8660 return (rc); 8661 } 8662 8663 static int 8664 sysctl_force_fec(SYSCTL_HANDLER_ARGS) 8665 { 8666 struct port_info *pi = arg1; 8667 struct adapter *sc = pi->adapter; 8668 struct link_config *lc = &pi->link_cfg; 8669 int rc, val; 8670 8671 val = lc->force_fec; 8672 MPASS(val >= -1 && val <= 1); 8673 rc = sysctl_handle_int(oidp, &val, 0, req); 8674 if (rc != 0 || req->newptr == NULL) 8675 return (rc); 8676 if (!(lc->pcaps & FW_PORT_CAP32_FORCE_FEC)) 8677 return (ENOTSUP); 8678 if (val < -1 || val > 1) 8679 return (EINVAL); 8680 8681 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4ff"); 8682 if (rc) 8683 return (rc); 8684 PORT_LOCK(pi); 8685 lc->force_fec = val; 8686 if (!hw_off_limits(sc)) { 8687 fixup_link_config(pi); 8688 if (pi->up_vis > 0) 8689 rc = apply_link_config(pi); 8690 } 8691 PORT_UNLOCK(pi); 8692 end_synchronized_op(sc, 0); 8693 return (rc); 8694 } 8695 8696 static int 8697 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 8698 { 8699 struct adapter *sc = arg1; 8700 int rc, reg = arg2; 8701 uint64_t val; 8702 8703 mtx_lock(&sc->reg_lock); 8704 if (hw_off_limits(sc)) 8705 rc = ENXIO; 8706 else { 8707 rc = 0; 8708 val = t4_read_reg64(sc, reg); 8709 } 8710 mtx_unlock(&sc->reg_lock); 8711 if (rc == 0) 8712 rc = sysctl_handle_64(oidp, &val, 0, req); 8713 return (rc); 8714 } 8715 8716 static int 8717 sysctl_temperature(SYSCTL_HANDLER_ARGS) 8718 { 8719 struct adapter *sc = arg1; 8720 int rc, t; 8721 uint32_t param, val; 8722 8723 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 8724 if (rc) 8725 return (rc); 8726 if (hw_off_limits(sc)) 8727 rc = ENXIO; 8728 else { 8729 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8730 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8731 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 8732 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8733 } 8734 end_synchronized_op(sc, 0); 8735 if (rc) 8736 return (rc); 8737 8738 /* unknown is returned as 0 but we display -1 in that case */ 8739 t = val == 0 ? -1 : val; 8740 8741 rc = sysctl_handle_int(oidp, &t, 0, req); 8742 return (rc); 8743 } 8744 8745 static int 8746 sysctl_vdd(SYSCTL_HANDLER_ARGS) 8747 { 8748 struct adapter *sc = arg1; 8749 int rc; 8750 uint32_t param, val; 8751 8752 if (sc->params.core_vdd == 0) { 8753 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8754 "t4vdd"); 8755 if (rc) 8756 return (rc); 8757 if (hw_off_limits(sc)) 8758 rc = ENXIO; 8759 else { 8760 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8761 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8762 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 8763 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, 8764 ¶m, &val); 8765 } 8766 end_synchronized_op(sc, 0); 8767 if (rc) 8768 return (rc); 8769 sc->params.core_vdd = val; 8770 } 8771 8772 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req)); 8773 } 8774 8775 static int 8776 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS) 8777 { 8778 struct adapter *sc = arg1; 8779 int rc, v; 8780 uint32_t param, val; 8781 8782 v = sc->sensor_resets; 8783 rc = sysctl_handle_int(oidp, &v, 0, req); 8784 if (rc != 0 || req->newptr == NULL || v <= 0) 8785 return (rc); 8786 8787 if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) || 8788 chip_id(sc) < CHELSIO_T5) 8789 return (ENOTSUP); 8790 8791 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst"); 8792 if (rc) 8793 return (rc); 8794 if (hw_off_limits(sc)) 8795 rc = ENXIO; 8796 else { 8797 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8798 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 8799 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR)); 8800 val = 1; 8801 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8802 } 8803 end_synchronized_op(sc, 0); 8804 if (rc == 0) 8805 sc->sensor_resets++; 8806 return (rc); 8807 } 8808 8809 static int 8810 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 8811 { 8812 struct adapter *sc = arg1; 8813 struct sbuf *sb; 8814 int rc; 8815 uint32_t param, val; 8816 8817 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 8818 if (rc) 8819 return (rc); 8820 if (hw_off_limits(sc)) 8821 rc = ENXIO; 8822 else { 8823 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8824 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 8825 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 8826 } 8827 end_synchronized_op(sc, 0); 8828 if (rc) 8829 return (rc); 8830 8831 rc = sysctl_wire_old_buffer(req, 0); 8832 if (rc != 0) 8833 return (rc); 8834 8835 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8836 if (sb == NULL) 8837 return (ENOMEM); 8838 8839 if (val == 0xffffffff) { 8840 /* Only debug and custom firmwares report load averages. */ 8841 sbuf_printf(sb, "not available"); 8842 } else { 8843 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 8844 (val >> 16) & 0xff); 8845 } 8846 rc = sbuf_finish(sb); 8847 sbuf_delete(sb); 8848 8849 return (rc); 8850 } 8851 8852 static int 8853 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 8854 { 8855 struct adapter *sc = arg1; 8856 struct sbuf *sb; 8857 int rc, i; 8858 uint16_t incr[NMTUS][NCCTRL_WIN]; 8859 static const char *dec_fac[] = { 8860 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 8861 "0.9375" 8862 }; 8863 8864 rc = sysctl_wire_old_buffer(req, 0); 8865 if (rc != 0) 8866 return (rc); 8867 8868 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8869 if (sb == NULL) 8870 return (ENOMEM); 8871 8872 mtx_lock(&sc->reg_lock); 8873 if (hw_off_limits(sc)) 8874 rc = ENXIO; 8875 else 8876 t4_read_cong_tbl(sc, incr); 8877 mtx_unlock(&sc->reg_lock); 8878 if (rc) 8879 goto done; 8880 8881 for (i = 0; i < NCCTRL_WIN; ++i) { 8882 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 8883 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 8884 incr[5][i], incr[6][i], incr[7][i]); 8885 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 8886 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 8887 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 8888 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 8889 } 8890 8891 rc = sbuf_finish(sb); 8892 done: 8893 sbuf_delete(sb); 8894 return (rc); 8895 } 8896 8897 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 8898 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 8899 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 8900 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 8901 }; 8902 8903 static int 8904 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 8905 { 8906 struct adapter *sc = arg1; 8907 struct sbuf *sb; 8908 int rc, i, n, qid = arg2; 8909 uint32_t *buf, *p; 8910 char *qtype; 8911 u_int cim_num_obq = sc->chip_params->cim_num_obq; 8912 8913 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 8914 ("%s: bad qid %d\n", __func__, qid)); 8915 8916 if (qid < CIM_NUM_IBQ) { 8917 /* inbound queue */ 8918 qtype = "IBQ"; 8919 n = 4 * CIM_IBQ_SIZE; 8920 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 8921 mtx_lock(&sc->reg_lock); 8922 if (hw_off_limits(sc)) 8923 rc = -ENXIO; 8924 else 8925 rc = t4_read_cim_ibq(sc, qid, buf, n); 8926 mtx_unlock(&sc->reg_lock); 8927 } else { 8928 /* outbound queue */ 8929 qtype = "OBQ"; 8930 qid -= CIM_NUM_IBQ; 8931 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 8932 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 8933 mtx_lock(&sc->reg_lock); 8934 if (hw_off_limits(sc)) 8935 rc = -ENXIO; 8936 else 8937 rc = t4_read_cim_obq(sc, qid, buf, n); 8938 mtx_unlock(&sc->reg_lock); 8939 } 8940 8941 if (rc < 0) { 8942 rc = -rc; 8943 goto done; 8944 } 8945 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 8946 8947 rc = sysctl_wire_old_buffer(req, 0); 8948 if (rc != 0) 8949 goto done; 8950 8951 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 8952 if (sb == NULL) { 8953 rc = ENOMEM; 8954 goto done; 8955 } 8956 8957 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 8958 for (i = 0, p = buf; i < n; i += 16, p += 4) 8959 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 8960 p[2], p[3]); 8961 8962 rc = sbuf_finish(sb); 8963 sbuf_delete(sb); 8964 done: 8965 free(buf, M_CXGBE); 8966 return (rc); 8967 } 8968 8969 static void 8970 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 8971 { 8972 uint32_t *p; 8973 8974 sbuf_printf(sb, "Status Data PC%s", 8975 cfg & F_UPDBGLACAPTPCONLY ? "" : 8976 " LS0Stat LS0Addr LS0Data"); 8977 8978 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 8979 if (cfg & F_UPDBGLACAPTPCONLY) { 8980 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 8981 p[6], p[7]); 8982 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 8983 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 8984 p[4] & 0xff, p[5] >> 8); 8985 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 8986 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 8987 p[1] & 0xf, p[2] >> 4); 8988 } else { 8989 sbuf_printf(sb, 8990 "\n %02x %x%07x %x%07x %08x %08x " 8991 "%08x%08x%08x%08x", 8992 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 8993 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 8994 p[6], p[7]); 8995 } 8996 } 8997 } 8998 8999 static void 9000 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 9001 { 9002 uint32_t *p; 9003 9004 sbuf_printf(sb, "Status Inst Data PC%s", 9005 cfg & F_UPDBGLACAPTPCONLY ? "" : 9006 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 9007 9008 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 9009 if (cfg & F_UPDBGLACAPTPCONLY) { 9010 sbuf_printf(sb, "\n %02x %08x %08x %08x", 9011 p[3] & 0xff, p[2], p[1], p[0]); 9012 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 9013 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 9014 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 9015 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 9016 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 9017 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 9018 p[6] >> 16); 9019 } else { 9020 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 9021 "%08x %08x %08x %08x %08x %08x", 9022 (p[9] >> 16) & 0xff, 9023 p[9] & 0xffff, p[8] >> 16, 9024 p[8] & 0xffff, p[7] >> 16, 9025 p[7] & 0xffff, p[6] >> 16, 9026 p[2], p[1], p[0], p[5], p[4], p[3]); 9027 } 9028 } 9029 } 9030 9031 static int 9032 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 9033 { 9034 uint32_t cfg, *buf; 9035 int rc; 9036 9037 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9038 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 9039 M_ZERO | flags); 9040 if (buf == NULL) 9041 return (ENOMEM); 9042 9043 mtx_lock(&sc->reg_lock); 9044 if (hw_off_limits(sc)) 9045 rc = ENXIO; 9046 else { 9047 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 9048 if (rc == 0) 9049 rc = -t4_cim_read_la(sc, buf, NULL); 9050 } 9051 mtx_unlock(&sc->reg_lock); 9052 if (rc == 0) { 9053 if (chip_id(sc) < CHELSIO_T6) 9054 sbuf_cim_la4(sc, sb, buf, cfg); 9055 else 9056 sbuf_cim_la6(sc, sb, buf, cfg); 9057 } 9058 free(buf, M_CXGBE); 9059 return (rc); 9060 } 9061 9062 static int 9063 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 9064 { 9065 struct adapter *sc = arg1; 9066 struct sbuf *sb; 9067 int rc; 9068 9069 rc = sysctl_wire_old_buffer(req, 0); 9070 if (rc != 0) 9071 return (rc); 9072 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9073 if (sb == NULL) 9074 return (ENOMEM); 9075 9076 rc = sbuf_cim_la(sc, sb, M_WAITOK); 9077 if (rc == 0) 9078 rc = sbuf_finish(sb); 9079 sbuf_delete(sb); 9080 return (rc); 9081 } 9082 9083 static void 9084 dump_cim_regs(struct adapter *sc) 9085 { 9086 log(LOG_DEBUG, "%s: CIM debug regs1 %08x %08x %08x %08x %08x\n", 9087 device_get_nameunit(sc->dev), 9088 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9089 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9090 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA2), 9091 t4_read_reg(sc, A_EDC_H_BIST_DATA_PATTERN), 9092 t4_read_reg(sc, A_EDC_H_BIST_STATUS_RDATA)); 9093 log(LOG_DEBUG, "%s: CIM debug regs2 %08x %08x %08x %08x %08x\n", 9094 device_get_nameunit(sc->dev), 9095 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0), 9096 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1), 9097 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0 + 0x800), 9098 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1 + 0x800), 9099 t4_read_reg(sc, A_EDC_H_BIST_CMD_LEN)); 9100 } 9101 9102 static void 9103 dump_cimla(struct adapter *sc) 9104 { 9105 struct sbuf sb; 9106 int rc; 9107 9108 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9109 log(LOG_DEBUG, "%s: failed to generate CIM LA dump.\n", 9110 device_get_nameunit(sc->dev)); 9111 return; 9112 } 9113 rc = sbuf_cim_la(sc, &sb, M_WAITOK); 9114 if (rc == 0) { 9115 rc = sbuf_finish(&sb); 9116 if (rc == 0) { 9117 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s\n", 9118 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9119 } 9120 } 9121 sbuf_delete(&sb); 9122 } 9123 9124 void 9125 t4_os_cim_err(struct adapter *sc) 9126 { 9127 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR); 9128 } 9129 9130 static int 9131 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 9132 { 9133 struct adapter *sc = arg1; 9134 u_int i; 9135 struct sbuf *sb; 9136 uint32_t *buf, *p; 9137 int rc; 9138 9139 rc = sysctl_wire_old_buffer(req, 0); 9140 if (rc != 0) 9141 return (rc); 9142 9143 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9144 if (sb == NULL) 9145 return (ENOMEM); 9146 9147 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 9148 M_ZERO | M_WAITOK); 9149 9150 mtx_lock(&sc->reg_lock); 9151 if (hw_off_limits(sc)) 9152 rc = ENXIO; 9153 else 9154 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 9155 mtx_unlock(&sc->reg_lock); 9156 if (rc) 9157 goto done; 9158 9159 p = buf; 9160 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9161 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 9162 p[1], p[0]); 9163 } 9164 9165 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 9166 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 9167 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 9168 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 9169 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 9170 (p[1] >> 2) | ((p[2] & 3) << 30), 9171 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 9172 p[0] & 1); 9173 } 9174 rc = sbuf_finish(sb); 9175 done: 9176 sbuf_delete(sb); 9177 free(buf, M_CXGBE); 9178 return (rc); 9179 } 9180 9181 static int 9182 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 9183 { 9184 struct adapter *sc = arg1; 9185 u_int i; 9186 struct sbuf *sb; 9187 uint32_t *buf, *p; 9188 int rc; 9189 9190 rc = sysctl_wire_old_buffer(req, 0); 9191 if (rc != 0) 9192 return (rc); 9193 9194 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9195 if (sb == NULL) 9196 return (ENOMEM); 9197 9198 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 9199 M_ZERO | M_WAITOK); 9200 9201 mtx_lock(&sc->reg_lock); 9202 if (hw_off_limits(sc)) 9203 rc = ENXIO; 9204 else 9205 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 9206 mtx_unlock(&sc->reg_lock); 9207 if (rc) 9208 goto done; 9209 9210 p = buf; 9211 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 9212 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9213 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 9214 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 9215 p[4], p[3], p[2], p[1], p[0]); 9216 } 9217 9218 sbuf_printf(sb, "\n\nCntl ID Data"); 9219 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 9220 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 9221 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 9222 } 9223 9224 rc = sbuf_finish(sb); 9225 done: 9226 sbuf_delete(sb); 9227 free(buf, M_CXGBE); 9228 return (rc); 9229 } 9230 9231 static int 9232 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 9233 { 9234 struct adapter *sc = arg1; 9235 struct sbuf *sb; 9236 int rc, i; 9237 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9238 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 9239 uint16_t thres[CIM_NUM_IBQ]; 9240 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 9241 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 9242 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 9243 9244 cim_num_obq = sc->chip_params->cim_num_obq; 9245 if (is_t4(sc)) { 9246 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 9247 obq_rdaddr = A_UP_OBQ_0_REALADDR; 9248 } else { 9249 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 9250 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 9251 } 9252 nq = CIM_NUM_IBQ + cim_num_obq; 9253 9254 mtx_lock(&sc->reg_lock); 9255 if (hw_off_limits(sc)) 9256 rc = ENXIO; 9257 else { 9258 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 9259 if (rc == 0) { 9260 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, 9261 obq_wr); 9262 if (rc == 0) 9263 t4_read_cimq_cfg(sc, base, size, thres); 9264 } 9265 } 9266 mtx_unlock(&sc->reg_lock); 9267 if (rc) 9268 return (rc); 9269 9270 rc = sysctl_wire_old_buffer(req, 0); 9271 if (rc != 0) 9272 return (rc); 9273 9274 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 9275 if (sb == NULL) 9276 return (ENOMEM); 9277 9278 sbuf_printf(sb, 9279 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 9280 9281 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 9282 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 9283 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 9284 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9285 G_QUEREMFLITS(p[2]) * 16); 9286 for ( ; i < nq; i++, p += 4, wr += 2) 9287 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 9288 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 9289 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 9290 G_QUEREMFLITS(p[2]) * 16); 9291 9292 rc = sbuf_finish(sb); 9293 sbuf_delete(sb); 9294 9295 return (rc); 9296 } 9297 9298 static int 9299 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 9300 { 9301 struct adapter *sc = arg1; 9302 struct sbuf *sb; 9303 int rc; 9304 struct tp_cpl_stats stats; 9305 9306 rc = sysctl_wire_old_buffer(req, 0); 9307 if (rc != 0) 9308 return (rc); 9309 9310 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9311 if (sb == NULL) 9312 return (ENOMEM); 9313 9314 mtx_lock(&sc->reg_lock); 9315 if (hw_off_limits(sc)) 9316 rc = ENXIO; 9317 else 9318 t4_tp_get_cpl_stats(sc, &stats, 0); 9319 mtx_unlock(&sc->reg_lock); 9320 if (rc) 9321 goto done; 9322 9323 if (sc->chip_params->nchan > 2) { 9324 sbuf_printf(sb, " channel 0 channel 1" 9325 " channel 2 channel 3"); 9326 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 9327 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 9328 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 9329 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 9330 } else { 9331 sbuf_printf(sb, " channel 0 channel 1"); 9332 sbuf_printf(sb, "\nCPL requests: %10u %10u", 9333 stats.req[0], stats.req[1]); 9334 sbuf_printf(sb, "\nCPL responses: %10u %10u", 9335 stats.rsp[0], stats.rsp[1]); 9336 } 9337 9338 rc = sbuf_finish(sb); 9339 done: 9340 sbuf_delete(sb); 9341 return (rc); 9342 } 9343 9344 static int 9345 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 9346 { 9347 struct adapter *sc = arg1; 9348 struct sbuf *sb; 9349 int rc; 9350 struct tp_usm_stats stats; 9351 9352 rc = sysctl_wire_old_buffer(req, 0); 9353 if (rc != 0) 9354 return(rc); 9355 9356 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9357 if (sb == NULL) 9358 return (ENOMEM); 9359 9360 mtx_lock(&sc->reg_lock); 9361 if (hw_off_limits(sc)) 9362 rc = ENXIO; 9363 else 9364 t4_get_usm_stats(sc, &stats, 1); 9365 mtx_unlock(&sc->reg_lock); 9366 if (rc == 0) { 9367 sbuf_printf(sb, "Frames: %u\n", stats.frames); 9368 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 9369 sbuf_printf(sb, "Drops: %u", stats.drops); 9370 rc = sbuf_finish(sb); 9371 } 9372 sbuf_delete(sb); 9373 9374 return (rc); 9375 } 9376 9377 static int 9378 sysctl_tid_stats(SYSCTL_HANDLER_ARGS) 9379 { 9380 struct adapter *sc = arg1; 9381 struct sbuf *sb; 9382 int rc; 9383 struct tp_tid_stats stats; 9384 9385 rc = sysctl_wire_old_buffer(req, 0); 9386 if (rc != 0) 9387 return(rc); 9388 9389 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9390 if (sb == NULL) 9391 return (ENOMEM); 9392 9393 mtx_lock(&sc->reg_lock); 9394 if (hw_off_limits(sc)) 9395 rc = ENXIO; 9396 else 9397 t4_tp_get_tid_stats(sc, &stats, 1); 9398 mtx_unlock(&sc->reg_lock); 9399 if (rc == 0) { 9400 sbuf_printf(sb, "Delete: %u\n", stats.del); 9401 sbuf_printf(sb, "Invalidate: %u\n", stats.inv); 9402 sbuf_printf(sb, "Active: %u\n", stats.act); 9403 sbuf_printf(sb, "Passive: %u", stats.pas); 9404 rc = sbuf_finish(sb); 9405 } 9406 sbuf_delete(sb); 9407 9408 return (rc); 9409 } 9410 9411 static const char * const devlog_level_strings[] = { 9412 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 9413 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 9414 [FW_DEVLOG_LEVEL_ERR] = "ERR", 9415 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 9416 [FW_DEVLOG_LEVEL_INFO] = "INFO", 9417 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 9418 }; 9419 9420 static const char * const devlog_facility_strings[] = { 9421 [FW_DEVLOG_FACILITY_CORE] = "CORE", 9422 [FW_DEVLOG_FACILITY_CF] = "CF", 9423 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 9424 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 9425 [FW_DEVLOG_FACILITY_RES] = "RES", 9426 [FW_DEVLOG_FACILITY_HW] = "HW", 9427 [FW_DEVLOG_FACILITY_FLR] = "FLR", 9428 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 9429 [FW_DEVLOG_FACILITY_PHY] = "PHY", 9430 [FW_DEVLOG_FACILITY_MAC] = "MAC", 9431 [FW_DEVLOG_FACILITY_PORT] = "PORT", 9432 [FW_DEVLOG_FACILITY_VI] = "VI", 9433 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 9434 [FW_DEVLOG_FACILITY_ACL] = "ACL", 9435 [FW_DEVLOG_FACILITY_TM] = "TM", 9436 [FW_DEVLOG_FACILITY_QFC] = "QFC", 9437 [FW_DEVLOG_FACILITY_DCB] = "DCB", 9438 [FW_DEVLOG_FACILITY_ETH] = "ETH", 9439 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 9440 [FW_DEVLOG_FACILITY_RI] = "RI", 9441 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 9442 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 9443 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 9444 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 9445 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 9446 }; 9447 9448 static int 9449 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 9450 { 9451 int i, j, rc, nentries, first = 0; 9452 struct devlog_params *dparams = &sc->params.devlog; 9453 struct fw_devlog_e *buf, *e; 9454 uint64_t ftstamp = UINT64_MAX; 9455 9456 if (dparams->addr == 0) 9457 return (ENXIO); 9458 9459 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 9460 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 9461 if (buf == NULL) 9462 return (ENOMEM); 9463 9464 mtx_lock(&sc->reg_lock); 9465 if (hw_off_limits(sc)) 9466 rc = ENXIO; 9467 else 9468 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, 9469 dparams->size); 9470 mtx_unlock(&sc->reg_lock); 9471 if (rc != 0) 9472 goto done; 9473 9474 nentries = dparams->size / sizeof(struct fw_devlog_e); 9475 for (i = 0; i < nentries; i++) { 9476 e = &buf[i]; 9477 9478 if (e->timestamp == 0) 9479 break; /* end */ 9480 9481 e->timestamp = be64toh(e->timestamp); 9482 e->seqno = be32toh(e->seqno); 9483 for (j = 0; j < 8; j++) 9484 e->params[j] = be32toh(e->params[j]); 9485 9486 if (e->timestamp < ftstamp) { 9487 ftstamp = e->timestamp; 9488 first = i; 9489 } 9490 } 9491 9492 if (buf[first].timestamp == 0) 9493 goto done; /* nothing in the log */ 9494 9495 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 9496 "Seq#", "Tstamp", "Level", "Facility", "Message"); 9497 9498 i = first; 9499 do { 9500 e = &buf[i]; 9501 if (e->timestamp == 0) 9502 break; /* end */ 9503 9504 sbuf_printf(sb, "%10d %15ju %8s %8s ", 9505 e->seqno, e->timestamp, 9506 (e->level < nitems(devlog_level_strings) ? 9507 devlog_level_strings[e->level] : "UNKNOWN"), 9508 (e->facility < nitems(devlog_facility_strings) ? 9509 devlog_facility_strings[e->facility] : "UNKNOWN")); 9510 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 9511 e->params[2], e->params[3], e->params[4], 9512 e->params[5], e->params[6], e->params[7]); 9513 9514 if (++i == nentries) 9515 i = 0; 9516 } while (i != first); 9517 done: 9518 free(buf, M_CXGBE); 9519 return (rc); 9520 } 9521 9522 static int 9523 sysctl_devlog(SYSCTL_HANDLER_ARGS) 9524 { 9525 struct adapter *sc = arg1; 9526 int rc; 9527 struct sbuf *sb; 9528 9529 rc = sysctl_wire_old_buffer(req, 0); 9530 if (rc != 0) 9531 return (rc); 9532 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9533 if (sb == NULL) 9534 return (ENOMEM); 9535 9536 rc = sbuf_devlog(sc, sb, M_WAITOK); 9537 if (rc == 0) 9538 rc = sbuf_finish(sb); 9539 sbuf_delete(sb); 9540 return (rc); 9541 } 9542 9543 static void 9544 dump_devlog(struct adapter *sc) 9545 { 9546 int rc; 9547 struct sbuf sb; 9548 9549 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) { 9550 log(LOG_DEBUG, "%s: failed to generate devlog dump.\n", 9551 device_get_nameunit(sc->dev)); 9552 return; 9553 } 9554 rc = sbuf_devlog(sc, &sb, M_WAITOK); 9555 if (rc == 0) { 9556 rc = sbuf_finish(&sb); 9557 if (rc == 0) { 9558 log(LOG_DEBUG, "%s: device log follows.\n%s", 9559 device_get_nameunit(sc->dev), sbuf_data(&sb)); 9560 } 9561 } 9562 sbuf_delete(&sb); 9563 } 9564 9565 static int 9566 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 9567 { 9568 struct adapter *sc = arg1; 9569 struct sbuf *sb; 9570 int rc; 9571 struct tp_fcoe_stats stats[MAX_NCHAN]; 9572 int i, nchan = sc->chip_params->nchan; 9573 9574 rc = sysctl_wire_old_buffer(req, 0); 9575 if (rc != 0) 9576 return (rc); 9577 9578 mtx_lock(&sc->reg_lock); 9579 if (hw_off_limits(sc)) 9580 rc = ENXIO; 9581 else { 9582 for (i = 0; i < nchan; i++) 9583 t4_get_fcoe_stats(sc, i, &stats[i], 1); 9584 } 9585 mtx_unlock(&sc->reg_lock); 9586 if (rc != 0) 9587 return (rc); 9588 9589 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9590 if (sb == NULL) 9591 return (ENOMEM); 9592 9593 if (nchan > 2) { 9594 sbuf_printf(sb, " channel 0 channel 1" 9595 " channel 2 channel 3"); 9596 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 9597 stats[0].octets_ddp, stats[1].octets_ddp, 9598 stats[2].octets_ddp, stats[3].octets_ddp); 9599 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 9600 stats[0].frames_ddp, stats[1].frames_ddp, 9601 stats[2].frames_ddp, stats[3].frames_ddp); 9602 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 9603 stats[0].frames_drop, stats[1].frames_drop, 9604 stats[2].frames_drop, stats[3].frames_drop); 9605 } else { 9606 sbuf_printf(sb, " channel 0 channel 1"); 9607 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 9608 stats[0].octets_ddp, stats[1].octets_ddp); 9609 sbuf_printf(sb, "\nframesDDP: %16u %16u", 9610 stats[0].frames_ddp, stats[1].frames_ddp); 9611 sbuf_printf(sb, "\nframesDrop: %16u %16u", 9612 stats[0].frames_drop, stats[1].frames_drop); 9613 } 9614 9615 rc = sbuf_finish(sb); 9616 sbuf_delete(sb); 9617 9618 return (rc); 9619 } 9620 9621 static int 9622 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 9623 { 9624 struct adapter *sc = arg1; 9625 struct sbuf *sb; 9626 int rc, i; 9627 unsigned int map, kbps, ipg, mode; 9628 unsigned int pace_tab[NTX_SCHED]; 9629 9630 rc = sysctl_wire_old_buffer(req, 0); 9631 if (rc != 0) 9632 return (rc); 9633 9634 sb = sbuf_new_for_sysctl(NULL, NULL, 512, req); 9635 if (sb == NULL) 9636 return (ENOMEM); 9637 9638 mtx_lock(&sc->reg_lock); 9639 if (hw_off_limits(sc)) { 9640 rc = ENXIO; 9641 goto done; 9642 } 9643 9644 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 9645 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 9646 t4_read_pace_tbl(sc, pace_tab); 9647 9648 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 9649 "Class IPG (0.1 ns) Flow IPG (us)"); 9650 9651 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 9652 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 9653 sbuf_printf(sb, "\n %u %-5s %u ", i, 9654 (mode & (1 << i)) ? "flow" : "class", map & 3); 9655 if (kbps) 9656 sbuf_printf(sb, "%9u ", kbps); 9657 else 9658 sbuf_printf(sb, " disabled "); 9659 9660 if (ipg) 9661 sbuf_printf(sb, "%13u ", ipg); 9662 else 9663 sbuf_printf(sb, " disabled "); 9664 9665 if (pace_tab[i]) 9666 sbuf_printf(sb, "%10u", pace_tab[i]); 9667 else 9668 sbuf_printf(sb, " disabled"); 9669 } 9670 rc = sbuf_finish(sb); 9671 done: 9672 mtx_unlock(&sc->reg_lock); 9673 sbuf_delete(sb); 9674 return (rc); 9675 } 9676 9677 static int 9678 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 9679 { 9680 struct adapter *sc = arg1; 9681 struct sbuf *sb; 9682 int rc, i, j; 9683 uint64_t *p0, *p1; 9684 struct lb_port_stats s[2]; 9685 static const char *stat_name[] = { 9686 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 9687 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 9688 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 9689 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 9690 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 9691 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 9692 "BG2FramesTrunc:", "BG3FramesTrunc:" 9693 }; 9694 9695 rc = sysctl_wire_old_buffer(req, 0); 9696 if (rc != 0) 9697 return (rc); 9698 9699 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9700 if (sb == NULL) 9701 return (ENOMEM); 9702 9703 memset(s, 0, sizeof(s)); 9704 9705 for (i = 0; i < sc->chip_params->nchan; i += 2) { 9706 mtx_lock(&sc->reg_lock); 9707 if (hw_off_limits(sc)) 9708 rc = ENXIO; 9709 else { 9710 t4_get_lb_stats(sc, i, &s[0]); 9711 t4_get_lb_stats(sc, i + 1, &s[1]); 9712 } 9713 mtx_unlock(&sc->reg_lock); 9714 if (rc != 0) 9715 break; 9716 9717 p0 = &s[0].octets; 9718 p1 = &s[1].octets; 9719 sbuf_printf(sb, "%s Loopback %u" 9720 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 9721 9722 for (j = 0; j < nitems(stat_name); j++) 9723 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 9724 *p0++, *p1++); 9725 } 9726 9727 rc = sbuf_finish(sb); 9728 sbuf_delete(sb); 9729 9730 return (rc); 9731 } 9732 9733 static int 9734 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 9735 { 9736 int rc = 0; 9737 struct port_info *pi = arg1; 9738 struct link_config *lc = &pi->link_cfg; 9739 struct sbuf *sb; 9740 9741 rc = sysctl_wire_old_buffer(req, 0); 9742 if (rc != 0) 9743 return(rc); 9744 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 9745 if (sb == NULL) 9746 return (ENOMEM); 9747 9748 if (lc->link_ok || lc->link_down_rc == 255) 9749 sbuf_printf(sb, "n/a"); 9750 else 9751 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 9752 9753 rc = sbuf_finish(sb); 9754 sbuf_delete(sb); 9755 9756 return (rc); 9757 } 9758 9759 struct mem_desc { 9760 u_int base; 9761 u_int limit; 9762 u_int idx; 9763 }; 9764 9765 static int 9766 mem_desc_cmp(const void *a, const void *b) 9767 { 9768 const u_int v1 = ((const struct mem_desc *)a)->base; 9769 const u_int v2 = ((const struct mem_desc *)b)->base; 9770 9771 if (v1 < v2) 9772 return (-1); 9773 else if (v1 > v2) 9774 return (1); 9775 9776 return (0); 9777 } 9778 9779 static void 9780 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 9781 unsigned int to) 9782 { 9783 unsigned int size; 9784 9785 if (from == to) 9786 return; 9787 9788 size = to - from + 1; 9789 if (size == 0) 9790 return; 9791 9792 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 9793 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 9794 } 9795 9796 static int 9797 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 9798 { 9799 struct adapter *sc = arg1; 9800 struct sbuf *sb; 9801 int rc, i, n; 9802 uint32_t lo, hi, used, free, alloc; 9803 static const char *memory[] = { 9804 "EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:" 9805 }; 9806 static const char *region[] = { 9807 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 9808 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 9809 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 9810 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 9811 "RQUDP region:", "PBL region:", "TXPBL region:", 9812 "TLSKey region:", "DBVFIFO region:", "ULPRX state:", 9813 "ULPTX state:", "On-chip queues:", 9814 }; 9815 struct mem_desc avail[4]; 9816 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 9817 struct mem_desc *md = mem; 9818 9819 rc = sysctl_wire_old_buffer(req, 0); 9820 if (rc != 0) 9821 return (rc); 9822 9823 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9824 if (sb == NULL) 9825 return (ENOMEM); 9826 9827 for (i = 0; i < nitems(mem); i++) { 9828 mem[i].limit = 0; 9829 mem[i].idx = i; 9830 } 9831 9832 mtx_lock(&sc->reg_lock); 9833 if (hw_off_limits(sc)) { 9834 rc = ENXIO; 9835 goto done; 9836 } 9837 9838 /* Find and sort the populated memory ranges */ 9839 i = 0; 9840 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 9841 if (lo & F_EDRAM0_ENABLE) { 9842 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 9843 avail[i].base = G_EDRAM0_BASE(hi) << 20; 9844 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 9845 avail[i].idx = 0; 9846 i++; 9847 } 9848 if (lo & F_EDRAM1_ENABLE) { 9849 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 9850 avail[i].base = G_EDRAM1_BASE(hi) << 20; 9851 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 9852 avail[i].idx = 1; 9853 i++; 9854 } 9855 if (lo & F_EXT_MEM_ENABLE) { 9856 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 9857 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 9858 avail[i].limit = avail[i].base + (G_EXT_MEM_SIZE(hi) << 20); 9859 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 9860 i++; 9861 } 9862 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 9863 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9864 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9865 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9866 avail[i].idx = 4; 9867 i++; 9868 } 9869 if (is_t6(sc) && lo & F_HMA_MUX) { 9870 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 9871 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 9872 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); 9873 avail[i].idx = 5; 9874 i++; 9875 } 9876 MPASS(i <= nitems(avail)); 9877 if (!i) /* no memory available */ 9878 goto done; 9879 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 9880 9881 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 9882 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 9883 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 9884 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9885 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 9886 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 9887 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 9888 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 9889 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 9890 9891 /* the next few have explicit upper bounds */ 9892 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 9893 md->limit = md->base - 1 + 9894 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 9895 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 9896 md++; 9897 9898 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 9899 md->limit = md->base - 1 + 9900 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 9901 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 9902 md++; 9903 9904 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 9905 if (chip_id(sc) <= CHELSIO_T5) 9906 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 9907 else 9908 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 9909 md->limit = 0; 9910 } else { 9911 md->base = 0; 9912 md->idx = nitems(region); /* hide it */ 9913 } 9914 md++; 9915 9916 #define ulp_region(reg) \ 9917 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 9918 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 9919 9920 ulp_region(RX_ISCSI); 9921 ulp_region(RX_TDDP); 9922 ulp_region(TX_TPT); 9923 ulp_region(RX_STAG); 9924 ulp_region(RX_RQ); 9925 ulp_region(RX_RQUDP); 9926 ulp_region(RX_PBL); 9927 ulp_region(TX_PBL); 9928 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 9929 ulp_region(RX_TLS_KEY); 9930 } 9931 #undef ulp_region 9932 9933 md->base = 0; 9934 if (is_t4(sc)) 9935 md->idx = nitems(region); 9936 else { 9937 uint32_t size = 0; 9938 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 9939 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 9940 9941 if (is_t5(sc)) { 9942 if (sge_ctrl & F_VFIFO_ENABLE) 9943 size = fifo_size << 2; 9944 } else 9945 size = G_T6_DBVFIFO_SIZE(fifo_size) << 6; 9946 9947 if (size) { 9948 md->base = t4_read_reg(sc, A_SGE_DBVFIFO_BADDR); 9949 md->limit = md->base + size - 1; 9950 } else 9951 md->idx = nitems(region); 9952 } 9953 md++; 9954 9955 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 9956 md->limit = 0; 9957 md++; 9958 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 9959 md->limit = 0; 9960 md++; 9961 9962 md->base = sc->vres.ocq.start; 9963 if (sc->vres.ocq.size) 9964 md->limit = md->base + sc->vres.ocq.size - 1; 9965 else 9966 md->idx = nitems(region); /* hide it */ 9967 md++; 9968 9969 /* add any address-space holes, there can be up to 3 */ 9970 for (n = 0; n < i - 1; n++) 9971 if (avail[n].limit < avail[n + 1].base) 9972 (md++)->base = avail[n].limit; 9973 if (avail[n].limit) 9974 (md++)->base = avail[n].limit; 9975 9976 n = md - mem; 9977 MPASS(n <= nitems(mem)); 9978 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 9979 9980 for (lo = 0; lo < i; lo++) 9981 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 9982 avail[lo].limit - 1); 9983 9984 sbuf_printf(sb, "\n"); 9985 for (i = 0; i < n; i++) { 9986 if (mem[i].idx >= nitems(region)) 9987 continue; /* skip holes */ 9988 if (!mem[i].limit) 9989 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 9990 mem_region_show(sb, region[mem[i].idx], mem[i].base, 9991 mem[i].limit); 9992 } 9993 9994 sbuf_printf(sb, "\n"); 9995 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 9996 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 9997 mem_region_show(sb, "uP RAM:", lo, hi); 9998 9999 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 10000 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 10001 mem_region_show(sb, "uP Extmem2:", lo, hi); 10002 10003 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 10004 for (i = 0, free = 0; i < 2; i++) 10005 free += G_FREERXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_RX_CNT)); 10006 sbuf_printf(sb, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n", 10007 G_PMRXMAXPAGE(lo), free, 10008 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 10009 (lo & F_PMRXNUMCHN) ? 2 : 1); 10010 10011 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 10012 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 10013 for (i = 0, free = 0; i < 4; i++) 10014 free += G_FREETXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_TX_CNT)); 10015 sbuf_printf(sb, "%u Tx pages (%u free) of size %u%ciB for %u channels\n", 10016 G_PMTXMAXPAGE(lo), free, 10017 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 10018 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 10019 sbuf_printf(sb, "%u p-structs (%u free)\n", 10020 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT), 10021 G_FREEPSTRUCTCOUNT(t4_read_reg(sc, A_TP_FLM_FREE_PS_CNT))); 10022 10023 for (i = 0; i < 4; i++) { 10024 if (chip_id(sc) > CHELSIO_T5) 10025 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 10026 else 10027 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 10028 if (is_t5(sc)) { 10029 used = G_T5_USED(lo); 10030 alloc = G_T5_ALLOC(lo); 10031 } else { 10032 used = G_USED(lo); 10033 alloc = G_ALLOC(lo); 10034 } 10035 /* For T6 these are MAC buffer groups */ 10036 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 10037 i, used, alloc); 10038 } 10039 for (i = 0; i < sc->chip_params->nchan; i++) { 10040 if (chip_id(sc) > CHELSIO_T5) 10041 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 10042 else 10043 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 10044 if (is_t5(sc)) { 10045 used = G_T5_USED(lo); 10046 alloc = G_T5_ALLOC(lo); 10047 } else { 10048 used = G_USED(lo); 10049 alloc = G_ALLOC(lo); 10050 } 10051 /* For T6 these are MAC buffer groups */ 10052 sbuf_printf(sb, 10053 "\nLoopback %d using %u pages out of %u allocated", 10054 i, used, alloc); 10055 } 10056 done: 10057 mtx_unlock(&sc->reg_lock); 10058 if (rc == 0) 10059 rc = sbuf_finish(sb); 10060 sbuf_delete(sb); 10061 return (rc); 10062 } 10063 10064 static inline void 10065 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 10066 { 10067 *mask = x | y; 10068 y = htobe64(y); 10069 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 10070 } 10071 10072 static int 10073 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 10074 { 10075 struct adapter *sc = arg1; 10076 struct sbuf *sb; 10077 int rc, i; 10078 10079 MPASS(chip_id(sc) <= CHELSIO_T5); 10080 10081 rc = sysctl_wire_old_buffer(req, 0); 10082 if (rc != 0) 10083 return (rc); 10084 10085 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10086 if (sb == NULL) 10087 return (ENOMEM); 10088 10089 sbuf_printf(sb, 10090 "Idx Ethernet address Mask Vld Ports PF" 10091 " VF Replication P0 P1 P2 P3 ML"); 10092 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10093 uint64_t tcamx, tcamy, mask; 10094 uint32_t cls_lo, cls_hi; 10095 uint8_t addr[ETHER_ADDR_LEN]; 10096 10097 mtx_lock(&sc->reg_lock); 10098 if (hw_off_limits(sc)) 10099 rc = ENXIO; 10100 else { 10101 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 10102 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 10103 } 10104 mtx_unlock(&sc->reg_lock); 10105 if (rc != 0) 10106 break; 10107 if (tcamx & tcamy) 10108 continue; 10109 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10110 mtx_lock(&sc->reg_lock); 10111 if (hw_off_limits(sc)) 10112 rc = ENXIO; 10113 else { 10114 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10115 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10116 } 10117 mtx_unlock(&sc->reg_lock); 10118 if (rc != 0) 10119 break; 10120 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 10121 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 10122 addr[3], addr[4], addr[5], (uintmax_t)mask, 10123 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 10124 G_PORTMAP(cls_hi), G_PF(cls_lo), 10125 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 10126 10127 if (cls_lo & F_REPLICATE) { 10128 struct fw_ldst_cmd ldst_cmd; 10129 10130 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10131 ldst_cmd.op_to_addrspace = 10132 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10133 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10134 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10135 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10136 ldst_cmd.u.mps.rplc.fid_idx = 10137 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10138 V_FW_LDST_CMD_IDX(i)); 10139 10140 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10141 "t4mps"); 10142 if (rc) 10143 break; 10144 if (hw_off_limits(sc)) 10145 rc = ENXIO; 10146 else 10147 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10148 sizeof(ldst_cmd), &ldst_cmd); 10149 end_synchronized_op(sc, 0); 10150 if (rc != 0) 10151 break; 10152 else { 10153 sbuf_printf(sb, " %08x %08x %08x %08x", 10154 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10155 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10156 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10157 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10158 } 10159 } else 10160 sbuf_printf(sb, "%36s", ""); 10161 10162 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 10163 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 10164 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 10165 } 10166 10167 if (rc) 10168 (void) sbuf_finish(sb); 10169 else 10170 rc = sbuf_finish(sb); 10171 sbuf_delete(sb); 10172 10173 return (rc); 10174 } 10175 10176 static int 10177 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 10178 { 10179 struct adapter *sc = arg1; 10180 struct sbuf *sb; 10181 int rc, i; 10182 10183 MPASS(chip_id(sc) > CHELSIO_T5); 10184 10185 rc = sysctl_wire_old_buffer(req, 0); 10186 if (rc != 0) 10187 return (rc); 10188 10189 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 10190 if (sb == NULL) 10191 return (ENOMEM); 10192 10193 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 10194 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 10195 " Replication" 10196 " P0 P1 P2 P3 ML\n"); 10197 10198 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 10199 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 10200 uint16_t ivlan; 10201 uint64_t tcamx, tcamy, val, mask; 10202 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 10203 uint8_t addr[ETHER_ADDR_LEN]; 10204 10205 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 10206 if (i < 256) 10207 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 10208 else 10209 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 10210 mtx_lock(&sc->reg_lock); 10211 if (hw_off_limits(sc)) 10212 rc = ENXIO; 10213 else { 10214 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10215 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10216 tcamy = G_DMACH(val) << 32; 10217 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10218 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10219 } 10220 mtx_unlock(&sc->reg_lock); 10221 if (rc != 0) 10222 break; 10223 10224 lookup_type = G_DATALKPTYPE(data2); 10225 port_num = G_DATAPORTNUM(data2); 10226 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10227 /* Inner header VNI */ 10228 vniy = ((data2 & F_DATAVIDH2) << 23) | 10229 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10230 dip_hit = data2 & F_DATADIPHIT; 10231 vlan_vld = 0; 10232 } else { 10233 vniy = 0; 10234 dip_hit = 0; 10235 vlan_vld = data2 & F_DATAVIDH2; 10236 ivlan = G_VIDL(val); 10237 } 10238 10239 ctl |= V_CTLXYBITSEL(1); 10240 mtx_lock(&sc->reg_lock); 10241 if (hw_off_limits(sc)) 10242 rc = ENXIO; 10243 else { 10244 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 10245 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 10246 tcamx = G_DMACH(val) << 32; 10247 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 10248 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 10249 } 10250 mtx_unlock(&sc->reg_lock); 10251 if (rc != 0) 10252 break; 10253 10254 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10255 /* Inner header VNI mask */ 10256 vnix = ((data2 & F_DATAVIDH2) << 23) | 10257 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 10258 } else 10259 vnix = 0; 10260 10261 if (tcamx & tcamy) 10262 continue; 10263 tcamxy2valmask(tcamx, tcamy, addr, &mask); 10264 10265 mtx_lock(&sc->reg_lock); 10266 if (hw_off_limits(sc)) 10267 rc = ENXIO; 10268 else { 10269 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 10270 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 10271 } 10272 mtx_unlock(&sc->reg_lock); 10273 if (rc != 0) 10274 break; 10275 10276 if (lookup_type && lookup_type != M_DATALKPTYPE) { 10277 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10278 "%012jx %06x %06x - - %3c" 10279 " I %4x %3c %#x%4u%4d", i, addr[0], 10280 addr[1], addr[2], addr[3], addr[4], addr[5], 10281 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 10282 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10283 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10284 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10285 } else { 10286 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 10287 "%012jx - - ", i, addr[0], addr[1], 10288 addr[2], addr[3], addr[4], addr[5], 10289 (uintmax_t)mask); 10290 10291 if (vlan_vld) 10292 sbuf_printf(sb, "%4u Y ", ivlan); 10293 else 10294 sbuf_printf(sb, " - N "); 10295 10296 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 10297 lookup_type ? 'I' : 'O', port_num, 10298 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 10299 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 10300 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 10301 } 10302 10303 10304 if (cls_lo & F_T6_REPLICATE) { 10305 struct fw_ldst_cmd ldst_cmd; 10306 10307 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 10308 ldst_cmd.op_to_addrspace = 10309 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 10310 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10311 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 10312 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 10313 ldst_cmd.u.mps.rplc.fid_idx = 10314 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 10315 V_FW_LDST_CMD_IDX(i)); 10316 10317 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 10318 "t6mps"); 10319 if (rc) 10320 break; 10321 if (hw_off_limits(sc)) 10322 rc = ENXIO; 10323 else 10324 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 10325 sizeof(ldst_cmd), &ldst_cmd); 10326 end_synchronized_op(sc, 0); 10327 if (rc != 0) 10328 break; 10329 else { 10330 sbuf_printf(sb, " %08x %08x %08x %08x" 10331 " %08x %08x %08x %08x", 10332 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 10333 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 10334 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 10335 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 10336 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 10337 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 10338 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 10339 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 10340 } 10341 } else 10342 sbuf_printf(sb, "%72s", ""); 10343 10344 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 10345 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 10346 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 10347 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 10348 } 10349 10350 if (rc) 10351 (void) sbuf_finish(sb); 10352 else 10353 rc = sbuf_finish(sb); 10354 sbuf_delete(sb); 10355 10356 return (rc); 10357 } 10358 10359 static int 10360 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 10361 { 10362 struct adapter *sc = arg1; 10363 struct sbuf *sb; 10364 int rc; 10365 uint16_t mtus[NMTUS]; 10366 10367 rc = sysctl_wire_old_buffer(req, 0); 10368 if (rc != 0) 10369 return (rc); 10370 10371 mtx_lock(&sc->reg_lock); 10372 if (hw_off_limits(sc)) 10373 rc = ENXIO; 10374 else 10375 t4_read_mtu_tbl(sc, mtus, NULL); 10376 mtx_unlock(&sc->reg_lock); 10377 if (rc != 0) 10378 return (rc); 10379 10380 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10381 if (sb == NULL) 10382 return (ENOMEM); 10383 10384 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 10385 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 10386 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 10387 mtus[14], mtus[15]); 10388 10389 rc = sbuf_finish(sb); 10390 sbuf_delete(sb); 10391 10392 return (rc); 10393 } 10394 10395 static int 10396 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 10397 { 10398 struct adapter *sc = arg1; 10399 struct sbuf *sb; 10400 int rc, i; 10401 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 10402 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 10403 static const char *tx_stats[MAX_PM_NSTATS] = { 10404 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 10405 "Tx FIFO wait", NULL, "Tx latency" 10406 }; 10407 static const char *rx_stats[MAX_PM_NSTATS] = { 10408 "Read:", "Write bypass:", "Write mem:", "Flush:", 10409 "Rx FIFO wait", NULL, "Rx latency" 10410 }; 10411 10412 rc = sysctl_wire_old_buffer(req, 0); 10413 if (rc != 0) 10414 return (rc); 10415 10416 mtx_lock(&sc->reg_lock); 10417 if (hw_off_limits(sc)) 10418 rc = ENXIO; 10419 else { 10420 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 10421 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 10422 } 10423 mtx_unlock(&sc->reg_lock); 10424 if (rc != 0) 10425 return (rc); 10426 10427 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10428 if (sb == NULL) 10429 return (ENOMEM); 10430 10431 sbuf_printf(sb, " Tx pcmds Tx bytes"); 10432 for (i = 0; i < 4; i++) { 10433 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10434 tx_cyc[i]); 10435 } 10436 10437 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 10438 for (i = 0; i < 4; i++) { 10439 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10440 rx_cyc[i]); 10441 } 10442 10443 if (chip_id(sc) > CHELSIO_T5) { 10444 sbuf_printf(sb, 10445 "\n Total wait Total occupancy"); 10446 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10447 tx_cyc[i]); 10448 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10449 rx_cyc[i]); 10450 10451 i += 2; 10452 MPASS(i < nitems(tx_stats)); 10453 10454 sbuf_printf(sb, 10455 "\n Reads Total wait"); 10456 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 10457 tx_cyc[i]); 10458 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 10459 rx_cyc[i]); 10460 } 10461 10462 rc = sbuf_finish(sb); 10463 sbuf_delete(sb); 10464 10465 return (rc); 10466 } 10467 10468 static int 10469 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 10470 { 10471 struct adapter *sc = arg1; 10472 struct sbuf *sb; 10473 int rc; 10474 struct tp_rdma_stats stats; 10475 10476 rc = sysctl_wire_old_buffer(req, 0); 10477 if (rc != 0) 10478 return (rc); 10479 10480 mtx_lock(&sc->reg_lock); 10481 if (hw_off_limits(sc)) 10482 rc = ENXIO; 10483 else 10484 t4_tp_get_rdma_stats(sc, &stats, 0); 10485 mtx_unlock(&sc->reg_lock); 10486 if (rc != 0) 10487 return (rc); 10488 10489 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10490 if (sb == NULL) 10491 return (ENOMEM); 10492 10493 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 10494 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 10495 10496 rc = sbuf_finish(sb); 10497 sbuf_delete(sb); 10498 10499 return (rc); 10500 } 10501 10502 static int 10503 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 10504 { 10505 struct adapter *sc = arg1; 10506 struct sbuf *sb; 10507 int rc; 10508 struct tp_tcp_stats v4, v6; 10509 10510 rc = sysctl_wire_old_buffer(req, 0); 10511 if (rc != 0) 10512 return (rc); 10513 10514 mtx_lock(&sc->reg_lock); 10515 if (hw_off_limits(sc)) 10516 rc = ENXIO; 10517 else 10518 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 10519 mtx_unlock(&sc->reg_lock); 10520 if (rc != 0) 10521 return (rc); 10522 10523 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10524 if (sb == NULL) 10525 return (ENOMEM); 10526 10527 sbuf_printf(sb, 10528 " IP IPv6\n"); 10529 sbuf_printf(sb, "OutRsts: %20u %20u\n", 10530 v4.tcp_out_rsts, v6.tcp_out_rsts); 10531 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 10532 v4.tcp_in_segs, v6.tcp_in_segs); 10533 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 10534 v4.tcp_out_segs, v6.tcp_out_segs); 10535 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 10536 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 10537 10538 rc = sbuf_finish(sb); 10539 sbuf_delete(sb); 10540 10541 return (rc); 10542 } 10543 10544 static int 10545 sysctl_tids(SYSCTL_HANDLER_ARGS) 10546 { 10547 struct adapter *sc = arg1; 10548 struct sbuf *sb; 10549 int rc; 10550 uint32_t x, y; 10551 struct tid_info *t = &sc->tids; 10552 10553 rc = sysctl_wire_old_buffer(req, 0); 10554 if (rc != 0) 10555 return (rc); 10556 10557 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10558 if (sb == NULL) 10559 return (ENOMEM); 10560 10561 if (t->natids) { 10562 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 10563 t->atids_in_use); 10564 } 10565 10566 if (t->nhpftids) { 10567 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 10568 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 10569 } 10570 10571 if (t->ntids) { 10572 bool hashen = false; 10573 10574 mtx_lock(&sc->reg_lock); 10575 if (hw_off_limits(sc)) 10576 rc = ENXIO; 10577 else if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 10578 hashen = true; 10579 if (chip_id(sc) <= CHELSIO_T5) { 10580 x = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 10581 y = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 10582 } else { 10583 x = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 10584 y = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 10585 } 10586 } 10587 mtx_unlock(&sc->reg_lock); 10588 if (rc != 0) 10589 goto done; 10590 10591 sbuf_printf(sb, "TID range: "); 10592 if (hashen) { 10593 if (x) 10594 sbuf_printf(sb, "%u-%u, ", t->tid_base, x - 1); 10595 sbuf_printf(sb, "%u-%u", y, t->ntids - 1); 10596 } else { 10597 sbuf_printf(sb, "%u-%u", t->tid_base, t->tid_base + 10598 t->ntids - 1); 10599 } 10600 sbuf_printf(sb, ", in use: %u\n", 10601 atomic_load_acq_int(&t->tids_in_use)); 10602 } 10603 10604 if (t->nstids) { 10605 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 10606 t->stid_base + t->nstids - 1, t->stids_in_use); 10607 } 10608 10609 if (t->nftids) { 10610 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 10611 t->ftid_end, t->ftids_in_use); 10612 } 10613 10614 if (t->netids) { 10615 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 10616 t->etid_base + t->netids - 1, t->etids_in_use); 10617 } 10618 10619 mtx_lock(&sc->reg_lock); 10620 if (hw_off_limits(sc)) 10621 rc = ENXIO; 10622 else { 10623 x = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4); 10624 y = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6); 10625 } 10626 mtx_unlock(&sc->reg_lock); 10627 if (rc != 0) 10628 goto done; 10629 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", x, y); 10630 done: 10631 if (rc == 0) 10632 rc = sbuf_finish(sb); 10633 else 10634 (void)sbuf_finish(sb); 10635 sbuf_delete(sb); 10636 10637 return (rc); 10638 } 10639 10640 static int 10641 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 10642 { 10643 struct adapter *sc = arg1; 10644 struct sbuf *sb; 10645 int rc; 10646 struct tp_err_stats stats; 10647 10648 rc = sysctl_wire_old_buffer(req, 0); 10649 if (rc != 0) 10650 return (rc); 10651 10652 mtx_lock(&sc->reg_lock); 10653 if (hw_off_limits(sc)) 10654 rc = ENXIO; 10655 else 10656 t4_tp_get_err_stats(sc, &stats, 0); 10657 mtx_unlock(&sc->reg_lock); 10658 if (rc != 0) 10659 return (rc); 10660 10661 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10662 if (sb == NULL) 10663 return (ENOMEM); 10664 10665 if (sc->chip_params->nchan > 2) { 10666 sbuf_printf(sb, " channel 0 channel 1" 10667 " channel 2 channel 3\n"); 10668 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 10669 stats.mac_in_errs[0], stats.mac_in_errs[1], 10670 stats.mac_in_errs[2], stats.mac_in_errs[3]); 10671 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 10672 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 10673 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 10674 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 10675 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 10676 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 10677 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 10678 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 10679 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 10680 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 10681 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 10682 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 10683 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 10684 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 10685 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 10686 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 10687 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 10688 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 10689 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 10690 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 10691 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 10692 } else { 10693 sbuf_printf(sb, " channel 0 channel 1\n"); 10694 sbuf_printf(sb, "macInErrs: %10u %10u\n", 10695 stats.mac_in_errs[0], stats.mac_in_errs[1]); 10696 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 10697 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 10698 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 10699 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 10700 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 10701 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 10702 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 10703 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 10704 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 10705 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 10706 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 10707 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 10708 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 10709 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 10710 } 10711 10712 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 10713 stats.ofld_no_neigh, stats.ofld_cong_defer); 10714 10715 rc = sbuf_finish(sb); 10716 sbuf_delete(sb); 10717 10718 return (rc); 10719 } 10720 10721 static int 10722 sysctl_tnl_stats(SYSCTL_HANDLER_ARGS) 10723 { 10724 struct adapter *sc = arg1; 10725 struct sbuf *sb; 10726 int rc; 10727 struct tp_tnl_stats stats; 10728 10729 rc = sysctl_wire_old_buffer(req, 0); 10730 if (rc != 0) 10731 return(rc); 10732 10733 mtx_lock(&sc->reg_lock); 10734 if (hw_off_limits(sc)) 10735 rc = ENXIO; 10736 else 10737 t4_tp_get_tnl_stats(sc, &stats, 1); 10738 mtx_unlock(&sc->reg_lock); 10739 if (rc != 0) 10740 return (rc); 10741 10742 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 10743 if (sb == NULL) 10744 return (ENOMEM); 10745 10746 if (sc->chip_params->nchan > 2) { 10747 sbuf_printf(sb, " channel 0 channel 1" 10748 " channel 2 channel 3\n"); 10749 sbuf_printf(sb, "OutPkts: %10u %10u %10u %10u\n", 10750 stats.out_pkt[0], stats.out_pkt[1], 10751 stats.out_pkt[2], stats.out_pkt[3]); 10752 sbuf_printf(sb, "InPkts: %10u %10u %10u %10u", 10753 stats.in_pkt[0], stats.in_pkt[1], 10754 stats.in_pkt[2], stats.in_pkt[3]); 10755 } else { 10756 sbuf_printf(sb, " channel 0 channel 1\n"); 10757 sbuf_printf(sb, "OutPkts: %10u %10u\n", 10758 stats.out_pkt[0], stats.out_pkt[1]); 10759 sbuf_printf(sb, "InPkts: %10u %10u", 10760 stats.in_pkt[0], stats.in_pkt[1]); 10761 } 10762 10763 rc = sbuf_finish(sb); 10764 sbuf_delete(sb); 10765 10766 return (rc); 10767 } 10768 10769 static int 10770 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 10771 { 10772 struct adapter *sc = arg1; 10773 struct tp_params *tpp = &sc->params.tp; 10774 u_int mask; 10775 int rc; 10776 10777 mask = tpp->la_mask >> 16; 10778 rc = sysctl_handle_int(oidp, &mask, 0, req); 10779 if (rc != 0 || req->newptr == NULL) 10780 return (rc); 10781 if (mask > 0xffff) 10782 return (EINVAL); 10783 mtx_lock(&sc->reg_lock); 10784 if (hw_off_limits(sc)) 10785 rc = ENXIO; 10786 else { 10787 tpp->la_mask = mask << 16; 10788 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, 10789 tpp->la_mask); 10790 } 10791 mtx_unlock(&sc->reg_lock); 10792 10793 return (rc); 10794 } 10795 10796 struct field_desc { 10797 const char *name; 10798 u_int start; 10799 u_int width; 10800 }; 10801 10802 static void 10803 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 10804 { 10805 char buf[32]; 10806 int line_size = 0; 10807 10808 while (f->name) { 10809 uint64_t mask = (1ULL << f->width) - 1; 10810 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 10811 ((uintmax_t)v >> f->start) & mask); 10812 10813 if (line_size + len >= 79) { 10814 line_size = 8; 10815 sbuf_printf(sb, "\n "); 10816 } 10817 sbuf_printf(sb, "%s ", buf); 10818 line_size += len + 1; 10819 f++; 10820 } 10821 sbuf_printf(sb, "\n"); 10822 } 10823 10824 static const struct field_desc tp_la0[] = { 10825 { "RcfOpCodeOut", 60, 4 }, 10826 { "State", 56, 4 }, 10827 { "WcfState", 52, 4 }, 10828 { "RcfOpcSrcOut", 50, 2 }, 10829 { "CRxError", 49, 1 }, 10830 { "ERxError", 48, 1 }, 10831 { "SanityFailed", 47, 1 }, 10832 { "SpuriousMsg", 46, 1 }, 10833 { "FlushInputMsg", 45, 1 }, 10834 { "FlushInputCpl", 44, 1 }, 10835 { "RssUpBit", 43, 1 }, 10836 { "RssFilterHit", 42, 1 }, 10837 { "Tid", 32, 10 }, 10838 { "InitTcb", 31, 1 }, 10839 { "LineNumber", 24, 7 }, 10840 { "Emsg", 23, 1 }, 10841 { "EdataOut", 22, 1 }, 10842 { "Cmsg", 21, 1 }, 10843 { "CdataOut", 20, 1 }, 10844 { "EreadPdu", 19, 1 }, 10845 { "CreadPdu", 18, 1 }, 10846 { "TunnelPkt", 17, 1 }, 10847 { "RcfPeerFin", 16, 1 }, 10848 { "RcfReasonOut", 12, 4 }, 10849 { "TxCchannel", 10, 2 }, 10850 { "RcfTxChannel", 8, 2 }, 10851 { "RxEchannel", 6, 2 }, 10852 { "RcfRxChannel", 5, 1 }, 10853 { "RcfDataOutSrdy", 4, 1 }, 10854 { "RxDvld", 3, 1 }, 10855 { "RxOoDvld", 2, 1 }, 10856 { "RxCongestion", 1, 1 }, 10857 { "TxCongestion", 0, 1 }, 10858 { NULL } 10859 }; 10860 10861 static const struct field_desc tp_la1[] = { 10862 { "CplCmdIn", 56, 8 }, 10863 { "CplCmdOut", 48, 8 }, 10864 { "ESynOut", 47, 1 }, 10865 { "EAckOut", 46, 1 }, 10866 { "EFinOut", 45, 1 }, 10867 { "ERstOut", 44, 1 }, 10868 { "SynIn", 43, 1 }, 10869 { "AckIn", 42, 1 }, 10870 { "FinIn", 41, 1 }, 10871 { "RstIn", 40, 1 }, 10872 { "DataIn", 39, 1 }, 10873 { "DataInVld", 38, 1 }, 10874 { "PadIn", 37, 1 }, 10875 { "RxBufEmpty", 36, 1 }, 10876 { "RxDdp", 35, 1 }, 10877 { "RxFbCongestion", 34, 1 }, 10878 { "TxFbCongestion", 33, 1 }, 10879 { "TxPktSumSrdy", 32, 1 }, 10880 { "RcfUlpType", 28, 4 }, 10881 { "Eread", 27, 1 }, 10882 { "Ebypass", 26, 1 }, 10883 { "Esave", 25, 1 }, 10884 { "Static0", 24, 1 }, 10885 { "Cread", 23, 1 }, 10886 { "Cbypass", 22, 1 }, 10887 { "Csave", 21, 1 }, 10888 { "CPktOut", 20, 1 }, 10889 { "RxPagePoolFull", 18, 2 }, 10890 { "RxLpbkPkt", 17, 1 }, 10891 { "TxLpbkPkt", 16, 1 }, 10892 { "RxVfValid", 15, 1 }, 10893 { "SynLearned", 14, 1 }, 10894 { "SetDelEntry", 13, 1 }, 10895 { "SetInvEntry", 12, 1 }, 10896 { "CpcmdDvld", 11, 1 }, 10897 { "CpcmdSave", 10, 1 }, 10898 { "RxPstructsFull", 8, 2 }, 10899 { "EpcmdDvld", 7, 1 }, 10900 { "EpcmdFlush", 6, 1 }, 10901 { "EpcmdTrimPrefix", 5, 1 }, 10902 { "EpcmdTrimPostfix", 4, 1 }, 10903 { "ERssIp4Pkt", 3, 1 }, 10904 { "ERssIp6Pkt", 2, 1 }, 10905 { "ERssTcpUdpPkt", 1, 1 }, 10906 { "ERssFceFipPkt", 0, 1 }, 10907 { NULL } 10908 }; 10909 10910 static const struct field_desc tp_la2[] = { 10911 { "CplCmdIn", 56, 8 }, 10912 { "MpsVfVld", 55, 1 }, 10913 { "MpsPf", 52, 3 }, 10914 { "MpsVf", 44, 8 }, 10915 { "SynIn", 43, 1 }, 10916 { "AckIn", 42, 1 }, 10917 { "FinIn", 41, 1 }, 10918 { "RstIn", 40, 1 }, 10919 { "DataIn", 39, 1 }, 10920 { "DataInVld", 38, 1 }, 10921 { "PadIn", 37, 1 }, 10922 { "RxBufEmpty", 36, 1 }, 10923 { "RxDdp", 35, 1 }, 10924 { "RxFbCongestion", 34, 1 }, 10925 { "TxFbCongestion", 33, 1 }, 10926 { "TxPktSumSrdy", 32, 1 }, 10927 { "RcfUlpType", 28, 4 }, 10928 { "Eread", 27, 1 }, 10929 { "Ebypass", 26, 1 }, 10930 { "Esave", 25, 1 }, 10931 { "Static0", 24, 1 }, 10932 { "Cread", 23, 1 }, 10933 { "Cbypass", 22, 1 }, 10934 { "Csave", 21, 1 }, 10935 { "CPktOut", 20, 1 }, 10936 { "RxPagePoolFull", 18, 2 }, 10937 { "RxLpbkPkt", 17, 1 }, 10938 { "TxLpbkPkt", 16, 1 }, 10939 { "RxVfValid", 15, 1 }, 10940 { "SynLearned", 14, 1 }, 10941 { "SetDelEntry", 13, 1 }, 10942 { "SetInvEntry", 12, 1 }, 10943 { "CpcmdDvld", 11, 1 }, 10944 { "CpcmdSave", 10, 1 }, 10945 { "RxPstructsFull", 8, 2 }, 10946 { "EpcmdDvld", 7, 1 }, 10947 { "EpcmdFlush", 6, 1 }, 10948 { "EpcmdTrimPrefix", 5, 1 }, 10949 { "EpcmdTrimPostfix", 4, 1 }, 10950 { "ERssIp4Pkt", 3, 1 }, 10951 { "ERssIp6Pkt", 2, 1 }, 10952 { "ERssTcpUdpPkt", 1, 1 }, 10953 { "ERssFceFipPkt", 0, 1 }, 10954 { NULL } 10955 }; 10956 10957 static void 10958 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 10959 { 10960 10961 field_desc_show(sb, *p, tp_la0); 10962 } 10963 10964 static void 10965 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 10966 { 10967 10968 if (idx) 10969 sbuf_printf(sb, "\n"); 10970 field_desc_show(sb, p[0], tp_la0); 10971 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 10972 field_desc_show(sb, p[1], tp_la0); 10973 } 10974 10975 static void 10976 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 10977 { 10978 10979 if (idx) 10980 sbuf_printf(sb, "\n"); 10981 field_desc_show(sb, p[0], tp_la0); 10982 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 10983 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 10984 } 10985 10986 static int 10987 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 10988 { 10989 struct adapter *sc = arg1; 10990 struct sbuf *sb; 10991 uint64_t *buf, *p; 10992 int rc; 10993 u_int i, inc; 10994 void (*show_func)(struct sbuf *, uint64_t *, int); 10995 10996 rc = sysctl_wire_old_buffer(req, 0); 10997 if (rc != 0) 10998 return (rc); 10999 11000 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11001 if (sb == NULL) 11002 return (ENOMEM); 11003 11004 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 11005 11006 mtx_lock(&sc->reg_lock); 11007 if (hw_off_limits(sc)) 11008 rc = ENXIO; 11009 else { 11010 t4_tp_read_la(sc, buf, NULL); 11011 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 11012 case 2: 11013 inc = 2; 11014 show_func = tp_la_show2; 11015 break; 11016 case 3: 11017 inc = 2; 11018 show_func = tp_la_show3; 11019 break; 11020 default: 11021 inc = 1; 11022 show_func = tp_la_show; 11023 } 11024 } 11025 mtx_unlock(&sc->reg_lock); 11026 if (rc != 0) 11027 goto done; 11028 11029 p = buf; 11030 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 11031 (*show_func)(sb, p, i); 11032 rc = sbuf_finish(sb); 11033 done: 11034 sbuf_delete(sb); 11035 free(buf, M_CXGBE); 11036 return (rc); 11037 } 11038 11039 static int 11040 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 11041 { 11042 struct adapter *sc = arg1; 11043 struct sbuf *sb; 11044 int rc; 11045 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 11046 11047 rc = sysctl_wire_old_buffer(req, 0); 11048 if (rc != 0) 11049 return (rc); 11050 11051 mtx_lock(&sc->reg_lock); 11052 if (hw_off_limits(sc)) 11053 rc = ENXIO; 11054 else 11055 t4_get_chan_txrate(sc, nrate, orate); 11056 mtx_unlock(&sc->reg_lock); 11057 if (rc != 0) 11058 return (rc); 11059 11060 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 11061 if (sb == NULL) 11062 return (ENOMEM); 11063 11064 if (sc->chip_params->nchan > 2) { 11065 sbuf_printf(sb, " channel 0 channel 1" 11066 " channel 2 channel 3\n"); 11067 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 11068 nrate[0], nrate[1], nrate[2], nrate[3]); 11069 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 11070 orate[0], orate[1], orate[2], orate[3]); 11071 } else { 11072 sbuf_printf(sb, " channel 0 channel 1\n"); 11073 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 11074 nrate[0], nrate[1]); 11075 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 11076 orate[0], orate[1]); 11077 } 11078 11079 rc = sbuf_finish(sb); 11080 sbuf_delete(sb); 11081 11082 return (rc); 11083 } 11084 11085 static int 11086 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 11087 { 11088 struct adapter *sc = arg1; 11089 struct sbuf *sb; 11090 uint32_t *buf, *p; 11091 int rc, i; 11092 11093 rc = sysctl_wire_old_buffer(req, 0); 11094 if (rc != 0) 11095 return (rc); 11096 11097 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11098 if (sb == NULL) 11099 return (ENOMEM); 11100 11101 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 11102 M_ZERO | M_WAITOK); 11103 11104 mtx_lock(&sc->reg_lock); 11105 if (hw_off_limits(sc)) 11106 rc = ENXIO; 11107 else 11108 t4_ulprx_read_la(sc, buf); 11109 mtx_unlock(&sc->reg_lock); 11110 if (rc != 0) 11111 goto done; 11112 11113 p = buf; 11114 sbuf_printf(sb, " Pcmd Type Message" 11115 " Data"); 11116 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 11117 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 11118 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 11119 } 11120 rc = sbuf_finish(sb); 11121 done: 11122 sbuf_delete(sb); 11123 free(buf, M_CXGBE); 11124 return (rc); 11125 } 11126 11127 static int 11128 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 11129 { 11130 struct adapter *sc = arg1; 11131 struct sbuf *sb; 11132 int rc; 11133 uint32_t cfg, s1, s2; 11134 11135 MPASS(chip_id(sc) >= CHELSIO_T5); 11136 11137 rc = sysctl_wire_old_buffer(req, 0); 11138 if (rc != 0) 11139 return (rc); 11140 11141 mtx_lock(&sc->reg_lock); 11142 if (hw_off_limits(sc)) 11143 rc = ENXIO; 11144 else { 11145 cfg = t4_read_reg(sc, A_SGE_STAT_CFG); 11146 s1 = t4_read_reg(sc, A_SGE_STAT_TOTAL); 11147 s2 = t4_read_reg(sc, A_SGE_STAT_MATCH); 11148 } 11149 mtx_unlock(&sc->reg_lock); 11150 if (rc != 0) 11151 return (rc); 11152 11153 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11154 if (sb == NULL) 11155 return (ENOMEM); 11156 11157 if (G_STATSOURCE_T5(cfg) == 7) { 11158 int mode; 11159 11160 mode = is_t5(sc) ? G_STATMODE(cfg) : G_T6_STATMODE(cfg); 11161 if (mode == 0) 11162 sbuf_printf(sb, "total %d, incomplete %d", s1, s2); 11163 else if (mode == 1) 11164 sbuf_printf(sb, "total %d, data overflow %d", s1, s2); 11165 else 11166 sbuf_printf(sb, "unknown mode %d", mode); 11167 } 11168 rc = sbuf_finish(sb); 11169 sbuf_delete(sb); 11170 11171 return (rc); 11172 } 11173 11174 static int 11175 sysctl_cpus(SYSCTL_HANDLER_ARGS) 11176 { 11177 struct adapter *sc = arg1; 11178 enum cpu_sets op = arg2; 11179 cpuset_t cpuset; 11180 struct sbuf *sb; 11181 int i, rc; 11182 11183 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 11184 11185 CPU_ZERO(&cpuset); 11186 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 11187 if (rc != 0) 11188 return (rc); 11189 11190 rc = sysctl_wire_old_buffer(req, 0); 11191 if (rc != 0) 11192 return (rc); 11193 11194 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 11195 if (sb == NULL) 11196 return (ENOMEM); 11197 11198 CPU_FOREACH(i) 11199 sbuf_printf(sb, "%d ", i); 11200 rc = sbuf_finish(sb); 11201 sbuf_delete(sb); 11202 11203 return (rc); 11204 } 11205 11206 static int 11207 sysctl_reset(SYSCTL_HANDLER_ARGS) 11208 { 11209 struct adapter *sc = arg1; 11210 u_int val; 11211 int rc; 11212 11213 val = atomic_load_int(&sc->num_resets); 11214 rc = sysctl_handle_int(oidp, &val, 0, req); 11215 if (rc != 0 || req->newptr == NULL) 11216 return (rc); 11217 11218 if (val == 0) { 11219 /* Zero out the counter that tracks reset. */ 11220 atomic_store_int(&sc->num_resets, 0); 11221 return (0); 11222 } 11223 11224 if (val != 1) 11225 return (EINVAL); /* 0 or 1 are the only legal values */ 11226 11227 if (hw_off_limits(sc)) /* harmless race */ 11228 return (EALREADY); 11229 11230 taskqueue_enqueue(reset_tq, &sc->reset_task); 11231 return (0); 11232 } 11233 11234 #ifdef TCP_OFFLOAD 11235 static int 11236 sysctl_tls(SYSCTL_HANDLER_ARGS) 11237 { 11238 struct adapter *sc = arg1; 11239 int i, j, v, rc; 11240 struct vi_info *vi; 11241 11242 v = sc->tt.tls; 11243 rc = sysctl_handle_int(oidp, &v, 0, req); 11244 if (rc != 0 || req->newptr == NULL) 11245 return (rc); 11246 11247 if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS)) 11248 return (ENOTSUP); 11249 11250 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls"); 11251 if (rc) 11252 return (rc); 11253 if (hw_off_limits(sc)) 11254 rc = ENXIO; 11255 else { 11256 sc->tt.tls = !!v; 11257 for_each_port(sc, i) { 11258 for_each_vi(sc->port[i], j, vi) { 11259 if (vi->flags & VI_INIT_DONE) 11260 t4_update_fl_bufsize(vi->ifp); 11261 } 11262 } 11263 } 11264 end_synchronized_op(sc, 0); 11265 11266 return (rc); 11267 11268 } 11269 11270 static void 11271 unit_conv(char *buf, size_t len, u_int val, u_int factor) 11272 { 11273 u_int rem = val % factor; 11274 11275 if (rem == 0) 11276 snprintf(buf, len, "%u", val / factor); 11277 else { 11278 while (rem % 10 == 0) 11279 rem /= 10; 11280 snprintf(buf, len, "%u.%u", val / factor, rem); 11281 } 11282 } 11283 11284 static int 11285 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 11286 { 11287 struct adapter *sc = arg1; 11288 char buf[16]; 11289 u_int res, re; 11290 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11291 11292 mtx_lock(&sc->reg_lock); 11293 if (hw_off_limits(sc)) 11294 res = (u_int)-1; 11295 else 11296 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 11297 mtx_unlock(&sc->reg_lock); 11298 if (res == (u_int)-1) 11299 return (ENXIO); 11300 11301 switch (arg2) { 11302 case 0: 11303 /* timer_tick */ 11304 re = G_TIMERRESOLUTION(res); 11305 break; 11306 case 1: 11307 /* TCP timestamp tick */ 11308 re = G_TIMESTAMPRESOLUTION(res); 11309 break; 11310 case 2: 11311 /* DACK tick */ 11312 re = G_DELAYEDACKRESOLUTION(res); 11313 break; 11314 default: 11315 return (EDOOFUS); 11316 } 11317 11318 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 11319 11320 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 11321 } 11322 11323 static int 11324 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 11325 { 11326 struct adapter *sc = arg1; 11327 int rc; 11328 u_int dack_tmr, dack_re, v; 11329 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11330 11331 mtx_lock(&sc->reg_lock); 11332 if (hw_off_limits(sc)) 11333 rc = ENXIO; 11334 else { 11335 rc = 0; 11336 dack_re = G_DELAYEDACKRESOLUTION(t4_read_reg(sc, 11337 A_TP_TIMER_RESOLUTION)); 11338 dack_tmr = t4_read_reg(sc, A_TP_DACK_TIMER); 11339 } 11340 mtx_unlock(&sc->reg_lock); 11341 if (rc != 0) 11342 return (rc); 11343 11344 v = ((cclk_ps << dack_re) / 1000000) * dack_tmr; 11345 11346 return (sysctl_handle_int(oidp, &v, 0, req)); 11347 } 11348 11349 static int 11350 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 11351 { 11352 struct adapter *sc = arg1; 11353 int rc, reg = arg2; 11354 u_int tre; 11355 u_long tp_tick_us, v; 11356 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 11357 11358 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 11359 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 11360 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 11361 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 11362 11363 mtx_lock(&sc->reg_lock); 11364 if (hw_off_limits(sc)) 11365 rc = ENXIO; 11366 else { 11367 rc = 0; 11368 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 11369 tp_tick_us = (cclk_ps << tre) / 1000000; 11370 if (reg == A_TP_INIT_SRTT) 11371 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 11372 else 11373 v = tp_tick_us * t4_read_reg(sc, reg); 11374 } 11375 mtx_unlock(&sc->reg_lock); 11376 if (rc != 0) 11377 return (rc); 11378 else 11379 return (sysctl_handle_long(oidp, &v, 0, req)); 11380 } 11381 11382 /* 11383 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 11384 * passed to this function. 11385 */ 11386 static int 11387 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 11388 { 11389 struct adapter *sc = arg1; 11390 int rc, idx = arg2; 11391 u_int v; 11392 11393 MPASS(idx >= 0 && idx <= 24); 11394 11395 mtx_lock(&sc->reg_lock); 11396 if (hw_off_limits(sc)) 11397 rc = ENXIO; 11398 else { 11399 rc = 0; 11400 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 11401 } 11402 mtx_unlock(&sc->reg_lock); 11403 if (rc != 0) 11404 return (rc); 11405 else 11406 return (sysctl_handle_int(oidp, &v, 0, req)); 11407 } 11408 11409 static int 11410 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 11411 { 11412 struct adapter *sc = arg1; 11413 int rc, idx = arg2; 11414 u_int shift, v, r; 11415 11416 MPASS(idx >= 0 && idx < 16); 11417 11418 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 11419 shift = (idx & 3) << 3; 11420 mtx_lock(&sc->reg_lock); 11421 if (hw_off_limits(sc)) 11422 rc = ENXIO; 11423 else { 11424 rc = 0; 11425 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 11426 } 11427 mtx_unlock(&sc->reg_lock); 11428 if (rc != 0) 11429 return (rc); 11430 else 11431 return (sysctl_handle_int(oidp, &v, 0, req)); 11432 } 11433 11434 static int 11435 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 11436 { 11437 struct vi_info *vi = arg1; 11438 struct adapter *sc = vi->adapter; 11439 int idx, rc, i; 11440 struct sge_ofld_rxq *ofld_rxq; 11441 uint8_t v; 11442 11443 idx = vi->ofld_tmr_idx; 11444 11445 rc = sysctl_handle_int(oidp, &idx, 0, req); 11446 if (rc != 0 || req->newptr == NULL) 11447 return (rc); 11448 11449 if (idx < 0 || idx >= SGE_NTIMERS) 11450 return (EINVAL); 11451 11452 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11453 "t4otmr"); 11454 if (rc) 11455 return (rc); 11456 11457 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 11458 for_each_ofld_rxq(vi, i, ofld_rxq) { 11459 #ifdef atomic_store_rel_8 11460 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 11461 #else 11462 ofld_rxq->iq.intr_params = v; 11463 #endif 11464 } 11465 vi->ofld_tmr_idx = idx; 11466 11467 end_synchronized_op(sc, LOCK_HELD); 11468 return (0); 11469 } 11470 11471 static int 11472 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 11473 { 11474 struct vi_info *vi = arg1; 11475 struct adapter *sc = vi->adapter; 11476 int idx, rc; 11477 11478 idx = vi->ofld_pktc_idx; 11479 11480 rc = sysctl_handle_int(oidp, &idx, 0, req); 11481 if (rc != 0 || req->newptr == NULL) 11482 return (rc); 11483 11484 if (idx < -1 || idx >= SGE_NCOUNTERS) 11485 return (EINVAL); 11486 11487 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 11488 "t4opktc"); 11489 if (rc) 11490 return (rc); 11491 11492 if (vi->flags & VI_INIT_DONE) 11493 rc = EBUSY; /* cannot be changed once the queues are created */ 11494 else 11495 vi->ofld_pktc_idx = idx; 11496 11497 end_synchronized_op(sc, LOCK_HELD); 11498 return (rc); 11499 } 11500 #endif 11501 11502 static int 11503 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 11504 { 11505 int rc; 11506 11507 if (cntxt->cid > M_CTXTQID) 11508 return (EINVAL); 11509 11510 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 11511 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 11512 return (EINVAL); 11513 11514 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 11515 if (rc) 11516 return (rc); 11517 11518 if (hw_off_limits(sc)) { 11519 rc = ENXIO; 11520 goto done; 11521 } 11522 11523 if (sc->flags & FW_OK) { 11524 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 11525 &cntxt->data[0]); 11526 if (rc == 0) 11527 goto done; 11528 } 11529 11530 /* 11531 * Read via firmware failed or wasn't even attempted. Read directly via 11532 * the backdoor. 11533 */ 11534 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 11535 done: 11536 end_synchronized_op(sc, 0); 11537 return (rc); 11538 } 11539 11540 static int 11541 load_fw(struct adapter *sc, struct t4_data *fw) 11542 { 11543 int rc; 11544 uint8_t *fw_data; 11545 11546 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 11547 if (rc) 11548 return (rc); 11549 11550 if (hw_off_limits(sc)) { 11551 rc = ENXIO; 11552 goto done; 11553 } 11554 11555 /* 11556 * The firmware, with the sole exception of the memory parity error 11557 * handler, runs from memory and not flash. It is almost always safe to 11558 * install a new firmware on a running system. Just set bit 1 in 11559 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 11560 */ 11561 if (sc->flags & FULL_INIT_DONE && 11562 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 11563 rc = EBUSY; 11564 goto done; 11565 } 11566 11567 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 11568 11569 rc = copyin(fw->data, fw_data, fw->len); 11570 if (rc == 0) 11571 rc = -t4_load_fw(sc, fw_data, fw->len); 11572 11573 free(fw_data, M_CXGBE); 11574 done: 11575 end_synchronized_op(sc, 0); 11576 return (rc); 11577 } 11578 11579 static int 11580 load_cfg(struct adapter *sc, struct t4_data *cfg) 11581 { 11582 int rc; 11583 uint8_t *cfg_data = NULL; 11584 11585 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11586 if (rc) 11587 return (rc); 11588 11589 if (hw_off_limits(sc)) { 11590 rc = ENXIO; 11591 goto done; 11592 } 11593 11594 if (cfg->len == 0) { 11595 /* clear */ 11596 rc = -t4_load_cfg(sc, NULL, 0); 11597 goto done; 11598 } 11599 11600 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 11601 11602 rc = copyin(cfg->data, cfg_data, cfg->len); 11603 if (rc == 0) 11604 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 11605 11606 free(cfg_data, M_CXGBE); 11607 done: 11608 end_synchronized_op(sc, 0); 11609 return (rc); 11610 } 11611 11612 static int 11613 load_boot(struct adapter *sc, struct t4_bootrom *br) 11614 { 11615 int rc; 11616 uint8_t *br_data = NULL; 11617 u_int offset; 11618 11619 if (br->len > 1024 * 1024) 11620 return (EFBIG); 11621 11622 if (br->pf_offset == 0) { 11623 /* pfidx */ 11624 if (br->pfidx_addr > 7) 11625 return (EINVAL); 11626 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 11627 A_PCIE_PF_EXPROM_OFST))); 11628 } else if (br->pf_offset == 1) { 11629 /* offset */ 11630 offset = G_OFFSET(br->pfidx_addr); 11631 } else { 11632 return (EINVAL); 11633 } 11634 11635 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 11636 if (rc) 11637 return (rc); 11638 11639 if (hw_off_limits(sc)) { 11640 rc = ENXIO; 11641 goto done; 11642 } 11643 11644 if (br->len == 0) { 11645 /* clear */ 11646 rc = -t4_load_boot(sc, NULL, offset, 0); 11647 goto done; 11648 } 11649 11650 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 11651 11652 rc = copyin(br->data, br_data, br->len); 11653 if (rc == 0) 11654 rc = -t4_load_boot(sc, br_data, offset, br->len); 11655 11656 free(br_data, M_CXGBE); 11657 done: 11658 end_synchronized_op(sc, 0); 11659 return (rc); 11660 } 11661 11662 static int 11663 load_bootcfg(struct adapter *sc, struct t4_data *bc) 11664 { 11665 int rc; 11666 uint8_t *bc_data = NULL; 11667 11668 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 11669 if (rc) 11670 return (rc); 11671 11672 if (hw_off_limits(sc)) { 11673 rc = ENXIO; 11674 goto done; 11675 } 11676 11677 if (bc->len == 0) { 11678 /* clear */ 11679 rc = -t4_load_bootcfg(sc, NULL, 0); 11680 goto done; 11681 } 11682 11683 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 11684 11685 rc = copyin(bc->data, bc_data, bc->len); 11686 if (rc == 0) 11687 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 11688 11689 free(bc_data, M_CXGBE); 11690 done: 11691 end_synchronized_op(sc, 0); 11692 return (rc); 11693 } 11694 11695 static int 11696 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 11697 { 11698 int rc; 11699 struct cudbg_init *cudbg; 11700 void *handle, *buf; 11701 11702 /* buf is large, don't block if no memory is available */ 11703 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 11704 if (buf == NULL) 11705 return (ENOMEM); 11706 11707 handle = cudbg_alloc_handle(); 11708 if (handle == NULL) { 11709 rc = ENOMEM; 11710 goto done; 11711 } 11712 11713 cudbg = cudbg_get_init(handle); 11714 cudbg->adap = sc; 11715 cudbg->print = (cudbg_print_cb)printf; 11716 11717 #ifndef notyet 11718 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 11719 __func__, dump->wr_flash, dump->len, dump->data); 11720 #endif 11721 11722 if (dump->wr_flash) 11723 cudbg->use_flash = 1; 11724 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 11725 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 11726 11727 rc = cudbg_collect(handle, buf, &dump->len); 11728 if (rc != 0) 11729 goto done; 11730 11731 rc = copyout(buf, dump->data, dump->len); 11732 done: 11733 cudbg_free_handle(handle); 11734 free(buf, M_CXGBE); 11735 return (rc); 11736 } 11737 11738 static void 11739 free_offload_policy(struct t4_offload_policy *op) 11740 { 11741 struct offload_rule *r; 11742 int i; 11743 11744 if (op == NULL) 11745 return; 11746 11747 r = &op->rule[0]; 11748 for (i = 0; i < op->nrules; i++, r++) { 11749 free(r->bpf_prog.bf_insns, M_CXGBE); 11750 } 11751 free(op->rule, M_CXGBE); 11752 free(op, M_CXGBE); 11753 } 11754 11755 static int 11756 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 11757 { 11758 int i, rc, len; 11759 struct t4_offload_policy *op, *old; 11760 struct bpf_program *bf; 11761 const struct offload_settings *s; 11762 struct offload_rule *r; 11763 void *u; 11764 11765 if (!is_offload(sc)) 11766 return (ENODEV); 11767 11768 if (uop->nrules == 0) { 11769 /* Delete installed policies. */ 11770 op = NULL; 11771 goto set_policy; 11772 } else if (uop->nrules > 256) { /* arbitrary */ 11773 return (E2BIG); 11774 } 11775 11776 /* Copy userspace offload policy to kernel */ 11777 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 11778 op->nrules = uop->nrules; 11779 len = op->nrules * sizeof(struct offload_rule); 11780 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11781 rc = copyin(uop->rule, op->rule, len); 11782 if (rc) { 11783 free(op->rule, M_CXGBE); 11784 free(op, M_CXGBE); 11785 return (rc); 11786 } 11787 11788 r = &op->rule[0]; 11789 for (i = 0; i < op->nrules; i++, r++) { 11790 11791 /* Validate open_type */ 11792 if (r->open_type != OPEN_TYPE_LISTEN && 11793 r->open_type != OPEN_TYPE_ACTIVE && 11794 r->open_type != OPEN_TYPE_PASSIVE && 11795 r->open_type != OPEN_TYPE_DONTCARE) { 11796 error: 11797 /* 11798 * Rules 0 to i have malloc'd filters that need to be 11799 * freed. Rules i+1 to nrules have userspace pointers 11800 * and should be left alone. 11801 */ 11802 op->nrules = i; 11803 free_offload_policy(op); 11804 return (rc); 11805 } 11806 11807 /* Validate settings */ 11808 s = &r->settings; 11809 if ((s->offload != 0 && s->offload != 1) || 11810 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 11811 s->sched_class < -1 || 11812 s->sched_class >= sc->params.nsched_cls) { 11813 rc = EINVAL; 11814 goto error; 11815 } 11816 11817 bf = &r->bpf_prog; 11818 u = bf->bf_insns; /* userspace ptr */ 11819 bf->bf_insns = NULL; 11820 if (bf->bf_len == 0) { 11821 /* legal, matches everything */ 11822 continue; 11823 } 11824 len = bf->bf_len * sizeof(*bf->bf_insns); 11825 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 11826 rc = copyin(u, bf->bf_insns, len); 11827 if (rc != 0) 11828 goto error; 11829 11830 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 11831 rc = EINVAL; 11832 goto error; 11833 } 11834 } 11835 set_policy: 11836 rw_wlock(&sc->policy_lock); 11837 old = sc->policy; 11838 sc->policy = op; 11839 rw_wunlock(&sc->policy_lock); 11840 free_offload_policy(old); 11841 11842 return (0); 11843 } 11844 11845 #define MAX_READ_BUF_SIZE (128 * 1024) 11846 static int 11847 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 11848 { 11849 uint32_t addr, remaining, n; 11850 uint32_t *buf; 11851 int rc; 11852 uint8_t *dst; 11853 11854 mtx_lock(&sc->reg_lock); 11855 if (hw_off_limits(sc)) 11856 rc = ENXIO; 11857 else 11858 rc = validate_mem_range(sc, mr->addr, mr->len); 11859 mtx_unlock(&sc->reg_lock); 11860 if (rc != 0) 11861 return (rc); 11862 11863 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 11864 addr = mr->addr; 11865 remaining = mr->len; 11866 dst = (void *)mr->data; 11867 11868 while (remaining) { 11869 n = min(remaining, MAX_READ_BUF_SIZE); 11870 mtx_lock(&sc->reg_lock); 11871 if (hw_off_limits(sc)) 11872 rc = ENXIO; 11873 else 11874 read_via_memwin(sc, 2, addr, buf, n); 11875 mtx_unlock(&sc->reg_lock); 11876 if (rc != 0) 11877 break; 11878 11879 rc = copyout(buf, dst, n); 11880 if (rc != 0) 11881 break; 11882 11883 dst += n; 11884 remaining -= n; 11885 addr += n; 11886 } 11887 11888 free(buf, M_CXGBE); 11889 return (rc); 11890 } 11891 #undef MAX_READ_BUF_SIZE 11892 11893 static int 11894 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 11895 { 11896 int rc; 11897 11898 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 11899 return (EINVAL); 11900 11901 if (i2cd->len > sizeof(i2cd->data)) 11902 return (EFBIG); 11903 11904 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 11905 if (rc) 11906 return (rc); 11907 if (hw_off_limits(sc)) 11908 rc = ENXIO; 11909 else 11910 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 11911 i2cd->offset, i2cd->len, &i2cd->data[0]); 11912 end_synchronized_op(sc, 0); 11913 11914 return (rc); 11915 } 11916 11917 static int 11918 clear_stats(struct adapter *sc, u_int port_id) 11919 { 11920 int i, v, chan_map; 11921 struct port_info *pi; 11922 struct vi_info *vi; 11923 struct sge_rxq *rxq; 11924 struct sge_txq *txq; 11925 struct sge_wrq *wrq; 11926 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 11927 struct sge_ofld_txq *ofld_txq; 11928 #endif 11929 #ifdef TCP_OFFLOAD 11930 struct sge_ofld_rxq *ofld_rxq; 11931 #endif 11932 11933 if (port_id >= sc->params.nports) 11934 return (EINVAL); 11935 pi = sc->port[port_id]; 11936 if (pi == NULL) 11937 return (EIO); 11938 11939 mtx_lock(&sc->reg_lock); 11940 if (!hw_off_limits(sc)) { 11941 /* MAC stats */ 11942 t4_clr_port_stats(sc, pi->tx_chan); 11943 if (is_t6(sc)) { 11944 if (pi->fcs_reg != -1) 11945 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 11946 else 11947 pi->stats.rx_fcs_err = 0; 11948 } 11949 for_each_vi(pi, v, vi) { 11950 if (vi->flags & VI_INIT_DONE) 11951 t4_clr_vi_stats(sc, vi->vin); 11952 } 11953 chan_map = pi->rx_e_chan_map; 11954 v = 0; /* reuse */ 11955 while (chan_map) { 11956 i = ffs(chan_map) - 1; 11957 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 11958 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 11959 chan_map &= ~(1 << i); 11960 } 11961 } 11962 mtx_unlock(&sc->reg_lock); 11963 pi->tx_parse_error = 0; 11964 pi->tnl_cong_drops = 0; 11965 11966 /* 11967 * Since this command accepts a port, clear stats for 11968 * all VIs on this port. 11969 */ 11970 for_each_vi(pi, v, vi) { 11971 if (vi->flags & VI_INIT_DONE) { 11972 11973 for_each_rxq(vi, i, rxq) { 11974 #if defined(INET) || defined(INET6) 11975 rxq->lro.lro_queued = 0; 11976 rxq->lro.lro_flushed = 0; 11977 #endif 11978 rxq->rxcsum = 0; 11979 rxq->vlan_extraction = 0; 11980 rxq->vxlan_rxcsum = 0; 11981 11982 rxq->fl.cl_allocated = 0; 11983 rxq->fl.cl_recycled = 0; 11984 rxq->fl.cl_fast_recycled = 0; 11985 } 11986 11987 for_each_txq(vi, i, txq) { 11988 txq->txcsum = 0; 11989 txq->tso_wrs = 0; 11990 txq->vlan_insertion = 0; 11991 txq->imm_wrs = 0; 11992 txq->sgl_wrs = 0; 11993 txq->txpkt_wrs = 0; 11994 txq->txpkts0_wrs = 0; 11995 txq->txpkts1_wrs = 0; 11996 txq->txpkts0_pkts = 0; 11997 txq->txpkts1_pkts = 0; 11998 txq->txpkts_flush = 0; 11999 txq->raw_wrs = 0; 12000 txq->vxlan_tso_wrs = 0; 12001 txq->vxlan_txcsum = 0; 12002 txq->kern_tls_records = 0; 12003 txq->kern_tls_short = 0; 12004 txq->kern_tls_partial = 0; 12005 txq->kern_tls_full = 0; 12006 txq->kern_tls_octets = 0; 12007 txq->kern_tls_waste = 0; 12008 txq->kern_tls_options = 0; 12009 txq->kern_tls_header = 0; 12010 txq->kern_tls_fin = 0; 12011 txq->kern_tls_fin_short = 0; 12012 txq->kern_tls_cbc = 0; 12013 txq->kern_tls_gcm = 0; 12014 mp_ring_reset_stats(txq->r); 12015 } 12016 12017 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12018 for_each_ofld_txq(vi, i, ofld_txq) { 12019 ofld_txq->wrq.tx_wrs_direct = 0; 12020 ofld_txq->wrq.tx_wrs_copied = 0; 12021 counter_u64_zero(ofld_txq->tx_iscsi_pdus); 12022 counter_u64_zero(ofld_txq->tx_iscsi_octets); 12023 counter_u64_zero(ofld_txq->tx_iscsi_iso_wrs); 12024 counter_u64_zero(ofld_txq->tx_toe_tls_records); 12025 counter_u64_zero(ofld_txq->tx_toe_tls_octets); 12026 } 12027 #endif 12028 #ifdef TCP_OFFLOAD 12029 for_each_ofld_rxq(vi, i, ofld_rxq) { 12030 ofld_rxq->fl.cl_allocated = 0; 12031 ofld_rxq->fl.cl_recycled = 0; 12032 ofld_rxq->fl.cl_fast_recycled = 0; 12033 counter_u64_zero( 12034 ofld_rxq->rx_iscsi_ddp_setup_ok); 12035 counter_u64_zero( 12036 ofld_rxq->rx_iscsi_ddp_setup_error); 12037 ofld_rxq->rx_iscsi_ddp_pdus = 0; 12038 ofld_rxq->rx_iscsi_ddp_octets = 0; 12039 ofld_rxq->rx_iscsi_fl_pdus = 0; 12040 ofld_rxq->rx_iscsi_fl_octets = 0; 12041 ofld_rxq->rx_toe_tls_records = 0; 12042 ofld_rxq->rx_toe_tls_octets = 0; 12043 } 12044 #endif 12045 12046 if (IS_MAIN_VI(vi)) { 12047 wrq = &sc->sge.ctrlq[pi->port_id]; 12048 wrq->tx_wrs_direct = 0; 12049 wrq->tx_wrs_copied = 0; 12050 } 12051 } 12052 } 12053 12054 return (0); 12055 } 12056 12057 static int 12058 hold_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12059 { 12060 #ifdef INET6 12061 struct in6_addr in6; 12062 12063 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12064 if (t4_get_clip_entry(sc, &in6, true) != NULL) 12065 return (0); 12066 else 12067 return (EIO); 12068 #else 12069 return (ENOTSUP); 12070 #endif 12071 } 12072 12073 static int 12074 release_clip_addr(struct adapter *sc, struct t4_clip_addr *ca) 12075 { 12076 #ifdef INET6 12077 struct in6_addr in6; 12078 12079 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr)); 12080 return (t4_release_clip_addr(sc, &in6)); 12081 #else 12082 return (ENOTSUP); 12083 #endif 12084 } 12085 12086 int 12087 t4_os_find_pci_capability(struct adapter *sc, int cap) 12088 { 12089 int i; 12090 12091 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 12092 } 12093 12094 int 12095 t4_os_pci_save_state(struct adapter *sc) 12096 { 12097 device_t dev; 12098 struct pci_devinfo *dinfo; 12099 12100 dev = sc->dev; 12101 dinfo = device_get_ivars(dev); 12102 12103 pci_cfg_save(dev, dinfo, 0); 12104 return (0); 12105 } 12106 12107 int 12108 t4_os_pci_restore_state(struct adapter *sc) 12109 { 12110 device_t dev; 12111 struct pci_devinfo *dinfo; 12112 12113 dev = sc->dev; 12114 dinfo = device_get_ivars(dev); 12115 12116 pci_cfg_restore(dev, dinfo); 12117 return (0); 12118 } 12119 12120 void 12121 t4_os_portmod_changed(struct port_info *pi) 12122 { 12123 struct adapter *sc = pi->adapter; 12124 struct vi_info *vi; 12125 struct ifnet *ifp; 12126 static const char *mod_str[] = { 12127 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 12128 }; 12129 12130 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 12131 ("%s: port_type %u", __func__, pi->port_type)); 12132 12133 vi = &pi->vi[0]; 12134 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 12135 PORT_LOCK(pi); 12136 build_medialist(pi); 12137 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 12138 fixup_link_config(pi); 12139 apply_link_config(pi); 12140 } 12141 PORT_UNLOCK(pi); 12142 end_synchronized_op(sc, LOCK_HELD); 12143 } 12144 12145 ifp = vi->ifp; 12146 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 12147 if_printf(ifp, "transceiver unplugged.\n"); 12148 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 12149 if_printf(ifp, "unknown transceiver inserted.\n"); 12150 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 12151 if_printf(ifp, "unsupported transceiver inserted.\n"); 12152 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 12153 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 12154 port_top_speed(pi), mod_str[pi->mod_type]); 12155 } else { 12156 if_printf(ifp, "transceiver (type %d) inserted.\n", 12157 pi->mod_type); 12158 } 12159 } 12160 12161 void 12162 t4_os_link_changed(struct port_info *pi) 12163 { 12164 struct vi_info *vi; 12165 struct ifnet *ifp; 12166 struct link_config *lc = &pi->link_cfg; 12167 struct adapter *sc = pi->adapter; 12168 int v; 12169 12170 PORT_LOCK_ASSERT_OWNED(pi); 12171 12172 if (is_t6(sc)) { 12173 if (lc->link_ok) { 12174 if (lc->speed > 25000 || 12175 (lc->speed == 25000 && lc->fec == FEC_RS)) { 12176 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12177 A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS); 12178 } else { 12179 pi->fcs_reg = T5_PORT_REG(pi->tx_chan, 12180 A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS); 12181 } 12182 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg); 12183 pi->stats.rx_fcs_err = 0; 12184 } else { 12185 pi->fcs_reg = -1; 12186 } 12187 } else { 12188 MPASS(pi->fcs_reg != -1); 12189 MPASS(pi->fcs_base == 0); 12190 } 12191 12192 for_each_vi(pi, v, vi) { 12193 ifp = vi->ifp; 12194 if (ifp == NULL) 12195 continue; 12196 12197 if (lc->link_ok) { 12198 ifp->if_baudrate = IF_Mbps(lc->speed); 12199 if_link_state_change(ifp, LINK_STATE_UP); 12200 } else { 12201 if_link_state_change(ifp, LINK_STATE_DOWN); 12202 } 12203 } 12204 } 12205 12206 void 12207 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 12208 { 12209 struct adapter *sc; 12210 12211 sx_slock(&t4_list_lock); 12212 SLIST_FOREACH(sc, &t4_list, link) { 12213 /* 12214 * func should not make any assumptions about what state sc is 12215 * in - the only guarantee is that sc->sc_lock is a valid lock. 12216 */ 12217 func(sc, arg); 12218 } 12219 sx_sunlock(&t4_list_lock); 12220 } 12221 12222 static int 12223 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 12224 struct thread *td) 12225 { 12226 int rc; 12227 struct adapter *sc = dev->si_drv1; 12228 12229 rc = priv_check(td, PRIV_DRIVER); 12230 if (rc != 0) 12231 return (rc); 12232 12233 switch (cmd) { 12234 case CHELSIO_T4_GETREG: { 12235 struct t4_reg *edata = (struct t4_reg *)data; 12236 12237 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12238 return (EFAULT); 12239 12240 mtx_lock(&sc->reg_lock); 12241 if (hw_off_limits(sc)) 12242 rc = ENXIO; 12243 else if (edata->size == 4) 12244 edata->val = t4_read_reg(sc, edata->addr); 12245 else if (edata->size == 8) 12246 edata->val = t4_read_reg64(sc, edata->addr); 12247 else 12248 rc = EINVAL; 12249 mtx_unlock(&sc->reg_lock); 12250 12251 break; 12252 } 12253 case CHELSIO_T4_SETREG: { 12254 struct t4_reg *edata = (struct t4_reg *)data; 12255 12256 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 12257 return (EFAULT); 12258 12259 mtx_lock(&sc->reg_lock); 12260 if (hw_off_limits(sc)) 12261 rc = ENXIO; 12262 else if (edata->size == 4) { 12263 if (edata->val & 0xffffffff00000000) 12264 rc = EINVAL; 12265 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 12266 } else if (edata->size == 8) 12267 t4_write_reg64(sc, edata->addr, edata->val); 12268 else 12269 rc = EINVAL; 12270 mtx_unlock(&sc->reg_lock); 12271 12272 break; 12273 } 12274 case CHELSIO_T4_REGDUMP: { 12275 struct t4_regdump *regs = (struct t4_regdump *)data; 12276 int reglen = t4_get_regs_len(sc); 12277 uint8_t *buf; 12278 12279 if (regs->len < reglen) { 12280 regs->len = reglen; /* hint to the caller */ 12281 return (ENOBUFS); 12282 } 12283 12284 regs->len = reglen; 12285 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 12286 mtx_lock(&sc->reg_lock); 12287 if (hw_off_limits(sc)) 12288 rc = ENXIO; 12289 else 12290 get_regs(sc, regs, buf); 12291 mtx_unlock(&sc->reg_lock); 12292 if (rc == 0) 12293 rc = copyout(buf, regs->data, reglen); 12294 free(buf, M_CXGBE); 12295 break; 12296 } 12297 case CHELSIO_T4_GET_FILTER_MODE: 12298 rc = get_filter_mode(sc, (uint32_t *)data); 12299 break; 12300 case CHELSIO_T4_SET_FILTER_MODE: 12301 rc = set_filter_mode(sc, *(uint32_t *)data); 12302 break; 12303 case CHELSIO_T4_SET_FILTER_MASK: 12304 rc = set_filter_mask(sc, *(uint32_t *)data); 12305 break; 12306 case CHELSIO_T4_GET_FILTER: 12307 rc = get_filter(sc, (struct t4_filter *)data); 12308 break; 12309 case CHELSIO_T4_SET_FILTER: 12310 rc = set_filter(sc, (struct t4_filter *)data); 12311 break; 12312 case CHELSIO_T4_DEL_FILTER: 12313 rc = del_filter(sc, (struct t4_filter *)data); 12314 break; 12315 case CHELSIO_T4_GET_SGE_CONTEXT: 12316 rc = get_sge_context(sc, (struct t4_sge_context *)data); 12317 break; 12318 case CHELSIO_T4_LOAD_FW: 12319 rc = load_fw(sc, (struct t4_data *)data); 12320 break; 12321 case CHELSIO_T4_GET_MEM: 12322 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 12323 break; 12324 case CHELSIO_T4_GET_I2C: 12325 rc = read_i2c(sc, (struct t4_i2c_data *)data); 12326 break; 12327 case CHELSIO_T4_CLEAR_STATS: 12328 rc = clear_stats(sc, *(uint32_t *)data); 12329 break; 12330 case CHELSIO_T4_SCHED_CLASS: 12331 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 12332 break; 12333 case CHELSIO_T4_SCHED_QUEUE: 12334 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 12335 break; 12336 case CHELSIO_T4_GET_TRACER: 12337 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 12338 break; 12339 case CHELSIO_T4_SET_TRACER: 12340 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 12341 break; 12342 case CHELSIO_T4_LOAD_CFG: 12343 rc = load_cfg(sc, (struct t4_data *)data); 12344 break; 12345 case CHELSIO_T4_LOAD_BOOT: 12346 rc = load_boot(sc, (struct t4_bootrom *)data); 12347 break; 12348 case CHELSIO_T4_LOAD_BOOTCFG: 12349 rc = load_bootcfg(sc, (struct t4_data *)data); 12350 break; 12351 case CHELSIO_T4_CUDBG_DUMP: 12352 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 12353 break; 12354 case CHELSIO_T4_SET_OFLD_POLICY: 12355 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 12356 break; 12357 case CHELSIO_T4_HOLD_CLIP_ADDR: 12358 rc = hold_clip_addr(sc, (struct t4_clip_addr *)data); 12359 break; 12360 case CHELSIO_T4_RELEASE_CLIP_ADDR: 12361 rc = release_clip_addr(sc, (struct t4_clip_addr *)data); 12362 break; 12363 default: 12364 rc = ENOTTY; 12365 } 12366 12367 return (rc); 12368 } 12369 12370 #ifdef TCP_OFFLOAD 12371 static int 12372 toe_capability(struct vi_info *vi, bool enable) 12373 { 12374 int rc; 12375 struct port_info *pi = vi->pi; 12376 struct adapter *sc = pi->adapter; 12377 12378 ASSERT_SYNCHRONIZED_OP(sc); 12379 12380 if (!is_offload(sc)) 12381 return (ENODEV); 12382 if (hw_off_limits(sc)) 12383 return (ENXIO); 12384 12385 if (enable) { 12386 #ifdef KERN_TLS 12387 if (sc->flags & KERN_TLS_ON && is_t6(sc)) { 12388 int i, j, n; 12389 struct port_info *p; 12390 struct vi_info *v; 12391 12392 /* 12393 * Reconfigure hardware for TOE if TXTLS is not enabled 12394 * on any ifnet. 12395 */ 12396 n = 0; 12397 for_each_port(sc, i) { 12398 p = sc->port[i]; 12399 for_each_vi(p, j, v) { 12400 if (v->ifp->if_capenable & IFCAP_TXTLS) { 12401 CH_WARN(sc, 12402 "%s has NIC TLS enabled.\n", 12403 device_get_nameunit(v->dev)); 12404 n++; 12405 } 12406 } 12407 } 12408 if (n > 0) { 12409 CH_WARN(sc, "Disable NIC TLS on all interfaces " 12410 "associated with this adapter before " 12411 "trying to enable TOE.\n"); 12412 return (EAGAIN); 12413 } 12414 rc = t6_config_kern_tls(sc, false); 12415 if (rc) 12416 return (rc); 12417 } 12418 #endif 12419 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 12420 /* TOE is already enabled. */ 12421 return (0); 12422 } 12423 12424 /* 12425 * We need the port's queues around so that we're able to send 12426 * and receive CPLs to/from the TOE even if the ifnet for this 12427 * port has never been UP'd administratively. 12428 */ 12429 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0)) 12430 return (rc); 12431 if (!(pi->vi[0].flags & VI_INIT_DONE) && 12432 ((rc = vi_init(&pi->vi[0])) != 0)) 12433 return (rc); 12434 12435 if (isset(&sc->offload_map, pi->port_id)) { 12436 /* TOE is enabled on another VI of this port. */ 12437 pi->uld_vis++; 12438 return (0); 12439 } 12440 12441 if (!uld_active(sc, ULD_TOM)) { 12442 rc = t4_activate_uld(sc, ULD_TOM); 12443 if (rc == EAGAIN) { 12444 log(LOG_WARNING, 12445 "You must kldload t4_tom.ko before trying " 12446 "to enable TOE on a cxgbe interface.\n"); 12447 } 12448 if (rc != 0) 12449 return (rc); 12450 KASSERT(sc->tom_softc != NULL, 12451 ("%s: TOM activated but softc NULL", __func__)); 12452 KASSERT(uld_active(sc, ULD_TOM), 12453 ("%s: TOM activated but flag not set", __func__)); 12454 } 12455 12456 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 12457 if (!uld_active(sc, ULD_IWARP)) 12458 (void) t4_activate_uld(sc, ULD_IWARP); 12459 if (!uld_active(sc, ULD_ISCSI)) 12460 (void) t4_activate_uld(sc, ULD_ISCSI); 12461 12462 pi->uld_vis++; 12463 setbit(&sc->offload_map, pi->port_id); 12464 } else { 12465 pi->uld_vis--; 12466 12467 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 12468 return (0); 12469 12470 KASSERT(uld_active(sc, ULD_TOM), 12471 ("%s: TOM never initialized?", __func__)); 12472 clrbit(&sc->offload_map, pi->port_id); 12473 } 12474 12475 return (0); 12476 } 12477 12478 /* 12479 * Add an upper layer driver to the global list. 12480 */ 12481 int 12482 t4_register_uld(struct uld_info *ui) 12483 { 12484 int rc = 0; 12485 struct uld_info *u; 12486 12487 sx_xlock(&t4_uld_list_lock); 12488 SLIST_FOREACH(u, &t4_uld_list, link) { 12489 if (u->uld_id == ui->uld_id) { 12490 rc = EEXIST; 12491 goto done; 12492 } 12493 } 12494 12495 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 12496 ui->refcount = 0; 12497 done: 12498 sx_xunlock(&t4_uld_list_lock); 12499 return (rc); 12500 } 12501 12502 int 12503 t4_unregister_uld(struct uld_info *ui) 12504 { 12505 int rc = EINVAL; 12506 struct uld_info *u; 12507 12508 sx_xlock(&t4_uld_list_lock); 12509 12510 SLIST_FOREACH(u, &t4_uld_list, link) { 12511 if (u == ui) { 12512 if (ui->refcount > 0) { 12513 rc = EBUSY; 12514 goto done; 12515 } 12516 12517 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 12518 rc = 0; 12519 goto done; 12520 } 12521 } 12522 done: 12523 sx_xunlock(&t4_uld_list_lock); 12524 return (rc); 12525 } 12526 12527 int 12528 t4_activate_uld(struct adapter *sc, int id) 12529 { 12530 int rc; 12531 struct uld_info *ui; 12532 12533 ASSERT_SYNCHRONIZED_OP(sc); 12534 12535 if (id < 0 || id > ULD_MAX) 12536 return (EINVAL); 12537 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 12538 12539 sx_slock(&t4_uld_list_lock); 12540 12541 SLIST_FOREACH(ui, &t4_uld_list, link) { 12542 if (ui->uld_id == id) { 12543 if (!(sc->flags & FULL_INIT_DONE)) { 12544 rc = adapter_init(sc); 12545 if (rc != 0) 12546 break; 12547 } 12548 12549 rc = ui->activate(sc); 12550 if (rc == 0) { 12551 setbit(&sc->active_ulds, id); 12552 ui->refcount++; 12553 } 12554 break; 12555 } 12556 } 12557 12558 sx_sunlock(&t4_uld_list_lock); 12559 12560 return (rc); 12561 } 12562 12563 int 12564 t4_deactivate_uld(struct adapter *sc, int id) 12565 { 12566 int rc; 12567 struct uld_info *ui; 12568 12569 ASSERT_SYNCHRONIZED_OP(sc); 12570 12571 if (id < 0 || id > ULD_MAX) 12572 return (EINVAL); 12573 rc = ENXIO; 12574 12575 sx_slock(&t4_uld_list_lock); 12576 12577 SLIST_FOREACH(ui, &t4_uld_list, link) { 12578 if (ui->uld_id == id) { 12579 rc = ui->deactivate(sc); 12580 if (rc == 0) { 12581 clrbit(&sc->active_ulds, id); 12582 ui->refcount--; 12583 } 12584 break; 12585 } 12586 } 12587 12588 sx_sunlock(&t4_uld_list_lock); 12589 12590 return (rc); 12591 } 12592 12593 static int 12594 t4_deactivate_all_uld(struct adapter *sc) 12595 { 12596 int rc; 12597 struct uld_info *ui; 12598 12599 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4detuld"); 12600 if (rc != 0) 12601 return (ENXIO); 12602 12603 sx_slock(&t4_uld_list_lock); 12604 12605 SLIST_FOREACH(ui, &t4_uld_list, link) { 12606 if (isset(&sc->active_ulds, ui->uld_id)) { 12607 rc = ui->deactivate(sc); 12608 if (rc != 0) 12609 break; 12610 clrbit(&sc->active_ulds, ui->uld_id); 12611 ui->refcount--; 12612 } 12613 } 12614 12615 sx_sunlock(&t4_uld_list_lock); 12616 end_synchronized_op(sc, 0); 12617 12618 return (rc); 12619 } 12620 12621 static void 12622 t4_async_event(struct adapter *sc) 12623 { 12624 struct uld_info *ui; 12625 12626 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4async") != 0) 12627 return; 12628 sx_slock(&t4_uld_list_lock); 12629 SLIST_FOREACH(ui, &t4_uld_list, link) { 12630 if (ui->uld_id == ULD_IWARP) { 12631 ui->async_event(sc); 12632 break; 12633 } 12634 } 12635 sx_sunlock(&t4_uld_list_lock); 12636 end_synchronized_op(sc, 0); 12637 } 12638 12639 int 12640 uld_active(struct adapter *sc, int uld_id) 12641 { 12642 12643 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 12644 12645 return (isset(&sc->active_ulds, uld_id)); 12646 } 12647 #endif 12648 12649 #ifdef KERN_TLS 12650 static int 12651 ktls_capability(struct adapter *sc, bool enable) 12652 { 12653 ASSERT_SYNCHRONIZED_OP(sc); 12654 12655 if (!is_ktls(sc)) 12656 return (ENODEV); 12657 if (!is_t6(sc)) 12658 return (0); 12659 if (hw_off_limits(sc)) 12660 return (ENXIO); 12661 12662 if (enable) { 12663 if (sc->flags & KERN_TLS_ON) 12664 return (0); /* already on */ 12665 if (sc->offload_map != 0) { 12666 CH_WARN(sc, 12667 "Disable TOE on all interfaces associated with " 12668 "this adapter before trying to enable NIC TLS.\n"); 12669 return (EAGAIN); 12670 } 12671 return (t6_config_kern_tls(sc, true)); 12672 } else { 12673 /* 12674 * Nothing to do for disable. If TOE is enabled sometime later 12675 * then toe_capability will reconfigure the hardware. 12676 */ 12677 return (0); 12678 } 12679 } 12680 #endif 12681 12682 /* 12683 * t = ptr to tunable. 12684 * nc = number of CPUs. 12685 * c = compiled in default for that tunable. 12686 */ 12687 static void 12688 calculate_nqueues(int *t, int nc, const int c) 12689 { 12690 int nq; 12691 12692 if (*t > 0) 12693 return; 12694 nq = *t < 0 ? -*t : c; 12695 *t = min(nc, nq); 12696 } 12697 12698 /* 12699 * Come up with reasonable defaults for some of the tunables, provided they're 12700 * not set by the user (in which case we'll use the values as is). 12701 */ 12702 static void 12703 tweak_tunables(void) 12704 { 12705 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 12706 12707 if (t4_ntxq < 1) { 12708 #ifdef RSS 12709 t4_ntxq = rss_getnumbuckets(); 12710 #else 12711 calculate_nqueues(&t4_ntxq, nc, NTXQ); 12712 #endif 12713 } 12714 12715 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 12716 12717 if (t4_nrxq < 1) { 12718 #ifdef RSS 12719 t4_nrxq = rss_getnumbuckets(); 12720 #else 12721 calculate_nqueues(&t4_nrxq, nc, NRXQ); 12722 #endif 12723 } 12724 12725 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 12726 12727 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 12728 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 12729 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 12730 #endif 12731 #ifdef TCP_OFFLOAD 12732 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 12733 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 12734 #endif 12735 12736 #if defined(TCP_OFFLOAD) || defined(KERN_TLS) 12737 if (t4_toecaps_allowed == -1) 12738 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 12739 #else 12740 if (t4_toecaps_allowed == -1) 12741 t4_toecaps_allowed = 0; 12742 #endif 12743 12744 #ifdef TCP_OFFLOAD 12745 if (t4_rdmacaps_allowed == -1) { 12746 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 12747 FW_CAPS_CONFIG_RDMA_RDMAC; 12748 } 12749 12750 if (t4_iscsicaps_allowed == -1) { 12751 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 12752 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 12753 FW_CAPS_CONFIG_ISCSI_T10DIF; 12754 } 12755 12756 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 12757 t4_tmr_idx_ofld = TMR_IDX_OFLD; 12758 12759 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 12760 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 12761 #else 12762 if (t4_rdmacaps_allowed == -1) 12763 t4_rdmacaps_allowed = 0; 12764 12765 if (t4_iscsicaps_allowed == -1) 12766 t4_iscsicaps_allowed = 0; 12767 #endif 12768 12769 #ifdef DEV_NETMAP 12770 calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ); 12771 calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ); 12772 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 12773 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 12774 #endif 12775 12776 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 12777 t4_tmr_idx = TMR_IDX; 12778 12779 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 12780 t4_pktc_idx = PKTC_IDX; 12781 12782 if (t4_qsize_txq < 128) 12783 t4_qsize_txq = 128; 12784 12785 if (t4_qsize_rxq < 128) 12786 t4_qsize_rxq = 128; 12787 while (t4_qsize_rxq & 7) 12788 t4_qsize_rxq++; 12789 12790 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 12791 12792 /* 12793 * Number of VIs to create per-port. The first VI is the "main" regular 12794 * VI for the port. The rest are additional virtual interfaces on the 12795 * same physical port. Note that the main VI does not have native 12796 * netmap support but the extra VIs do. 12797 * 12798 * Limit the number of VIs per port to the number of available 12799 * MAC addresses per port. 12800 */ 12801 if (t4_num_vis < 1) 12802 t4_num_vis = 1; 12803 if (t4_num_vis > nitems(vi_mac_funcs)) { 12804 t4_num_vis = nitems(vi_mac_funcs); 12805 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 12806 } 12807 12808 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 12809 pcie_relaxed_ordering = 1; 12810 #if defined(__i386__) || defined(__amd64__) 12811 if (cpu_vendor_id == CPU_VENDOR_INTEL) 12812 pcie_relaxed_ordering = 0; 12813 #endif 12814 } 12815 } 12816 12817 #ifdef DDB 12818 static void 12819 t4_dump_tcb(struct adapter *sc, int tid) 12820 { 12821 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 12822 12823 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 12824 save = t4_read_reg(sc, reg); 12825 base = sc->memwin[2].mw_base; 12826 12827 /* Dump TCB for the tid */ 12828 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 12829 tcb_addr += tid * TCB_SIZE; 12830 12831 if (is_t4(sc)) { 12832 pf = 0; 12833 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 12834 } else { 12835 pf = V_PFNUM(sc->pf); 12836 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 12837 } 12838 t4_write_reg(sc, reg, win_pos | pf); 12839 t4_read_reg(sc, reg); 12840 12841 off = tcb_addr - win_pos; 12842 for (i = 0; i < 4; i++) { 12843 uint32_t buf[8]; 12844 for (j = 0; j < 8; j++, off += 4) 12845 buf[j] = htonl(t4_read_reg(sc, base + off)); 12846 12847 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 12848 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 12849 buf[7]); 12850 } 12851 12852 t4_write_reg(sc, reg, save); 12853 t4_read_reg(sc, reg); 12854 } 12855 12856 static void 12857 t4_dump_devlog(struct adapter *sc) 12858 { 12859 struct devlog_params *dparams = &sc->params.devlog; 12860 struct fw_devlog_e e; 12861 int i, first, j, m, nentries, rc; 12862 uint64_t ftstamp = UINT64_MAX; 12863 12864 if (dparams->start == 0) { 12865 db_printf("devlog params not valid\n"); 12866 return; 12867 } 12868 12869 nentries = dparams->size / sizeof(struct fw_devlog_e); 12870 m = fwmtype_to_hwmtype(dparams->memtype); 12871 12872 /* Find the first entry. */ 12873 first = -1; 12874 for (i = 0; i < nentries && !db_pager_quit; i++) { 12875 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 12876 sizeof(e), (void *)&e); 12877 if (rc != 0) 12878 break; 12879 12880 if (e.timestamp == 0) 12881 break; 12882 12883 e.timestamp = be64toh(e.timestamp); 12884 if (e.timestamp < ftstamp) { 12885 ftstamp = e.timestamp; 12886 first = i; 12887 } 12888 } 12889 12890 if (first == -1) 12891 return; 12892 12893 i = first; 12894 do { 12895 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 12896 sizeof(e), (void *)&e); 12897 if (rc != 0) 12898 return; 12899 12900 if (e.timestamp == 0) 12901 return; 12902 12903 e.timestamp = be64toh(e.timestamp); 12904 e.seqno = be32toh(e.seqno); 12905 for (j = 0; j < 8; j++) 12906 e.params[j] = be32toh(e.params[j]); 12907 12908 db_printf("%10d %15ju %8s %8s ", 12909 e.seqno, e.timestamp, 12910 (e.level < nitems(devlog_level_strings) ? 12911 devlog_level_strings[e.level] : "UNKNOWN"), 12912 (e.facility < nitems(devlog_facility_strings) ? 12913 devlog_facility_strings[e.facility] : "UNKNOWN")); 12914 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 12915 e.params[3], e.params[4], e.params[5], e.params[6], 12916 e.params[7]); 12917 12918 if (++i == nentries) 12919 i = 0; 12920 } while (i != first && !db_pager_quit); 12921 } 12922 12923 static struct db_command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 12924 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 12925 12926 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 12927 { 12928 device_t dev; 12929 int t; 12930 bool valid; 12931 12932 valid = false; 12933 t = db_read_token(); 12934 if (t == tIDENT) { 12935 dev = device_lookup_by_name(db_tok_string); 12936 valid = true; 12937 } 12938 db_skip_to_eol(); 12939 if (!valid) { 12940 db_printf("usage: show t4 devlog <nexus>\n"); 12941 return; 12942 } 12943 12944 if (dev == NULL) { 12945 db_printf("device not found\n"); 12946 return; 12947 } 12948 12949 t4_dump_devlog(device_get_softc(dev)); 12950 } 12951 12952 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 12953 { 12954 device_t dev; 12955 int radix, tid, t; 12956 bool valid; 12957 12958 valid = false; 12959 radix = db_radix; 12960 db_radix = 10; 12961 t = db_read_token(); 12962 if (t == tIDENT) { 12963 dev = device_lookup_by_name(db_tok_string); 12964 t = db_read_token(); 12965 if (t == tNUMBER) { 12966 tid = db_tok_number; 12967 valid = true; 12968 } 12969 } 12970 db_radix = radix; 12971 db_skip_to_eol(); 12972 if (!valid) { 12973 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 12974 return; 12975 } 12976 12977 if (dev == NULL) { 12978 db_printf("device not found\n"); 12979 return; 12980 } 12981 if (tid < 0) { 12982 db_printf("invalid tid\n"); 12983 return; 12984 } 12985 12986 t4_dump_tcb(device_get_softc(dev), tid); 12987 } 12988 #endif 12989 12990 static eventhandler_tag vxlan_start_evtag; 12991 static eventhandler_tag vxlan_stop_evtag; 12992 12993 struct vxlan_evargs { 12994 struct ifnet *ifp; 12995 uint16_t port; 12996 }; 12997 12998 static void 12999 enable_vxlan_rx(struct adapter *sc) 13000 { 13001 int i, rc; 13002 struct port_info *pi; 13003 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0}; 13004 13005 ASSERT_SYNCHRONIZED_OP(sc); 13006 13007 t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, V_VXLAN(sc->vxlan_port) | 13008 F_VXLAN_EN); 13009 for_each_port(sc, i) { 13010 pi = sc->port[i]; 13011 if (pi->vxlan_tcam_entry == true) 13012 continue; 13013 rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, match_all_mac, 13014 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id, 13015 true); 13016 if (rc < 0) { 13017 rc = -rc; 13018 CH_ERR(&pi->vi[0], 13019 "failed to add VXLAN TCAM entry: %d.\n", rc); 13020 } else { 13021 MPASS(rc == sc->rawf_base + pi->port_id); 13022 pi->vxlan_tcam_entry = true; 13023 } 13024 } 13025 } 13026 13027 static void 13028 t4_vxlan_start(struct adapter *sc, void *arg) 13029 { 13030 struct vxlan_evargs *v = arg; 13031 13032 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13033 return; 13034 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0) 13035 return; 13036 13037 if (sc->vxlan_refcount == 0) { 13038 sc->vxlan_port = v->port; 13039 sc->vxlan_refcount = 1; 13040 if (!hw_off_limits(sc)) 13041 enable_vxlan_rx(sc); 13042 } else if (sc->vxlan_port == v->port) { 13043 sc->vxlan_refcount++; 13044 } else { 13045 CH_ERR(sc, "VXLAN already configured on port %d; " 13046 "ignoring attempt to configure it on port %d\n", 13047 sc->vxlan_port, v->port); 13048 } 13049 end_synchronized_op(sc, 0); 13050 } 13051 13052 static void 13053 t4_vxlan_stop(struct adapter *sc, void *arg) 13054 { 13055 struct vxlan_evargs *v = arg; 13056 13057 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5) 13058 return; 13059 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0) 13060 return; 13061 13062 /* 13063 * VXLANs may have been configured before the driver was loaded so we 13064 * may see more stops than starts. This is not handled cleanly but at 13065 * least we keep the refcount sane. 13066 */ 13067 if (sc->vxlan_port != v->port) 13068 goto done; 13069 if (sc->vxlan_refcount == 0) { 13070 CH_ERR(sc, "VXLAN operation on port %d was stopped earlier; " 13071 "ignoring attempt to stop it again.\n", sc->vxlan_port); 13072 } else if (--sc->vxlan_refcount == 0 && !hw_off_limits(sc)) 13073 t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0); 13074 done: 13075 end_synchronized_op(sc, 0); 13076 } 13077 13078 static void 13079 t4_vxlan_start_handler(void *arg __unused, struct ifnet *ifp, 13080 sa_family_t family, u_int port) 13081 { 13082 struct vxlan_evargs v; 13083 13084 MPASS(family == AF_INET || family == AF_INET6); 13085 v.ifp = ifp; 13086 v.port = port; 13087 13088 t4_iterate(t4_vxlan_start, &v); 13089 } 13090 13091 static void 13092 t4_vxlan_stop_handler(void *arg __unused, struct ifnet *ifp, sa_family_t family, 13093 u_int port) 13094 { 13095 struct vxlan_evargs v; 13096 13097 MPASS(family == AF_INET || family == AF_INET6); 13098 v.ifp = ifp; 13099 v.port = port; 13100 13101 t4_iterate(t4_vxlan_stop, &v); 13102 } 13103 13104 13105 static struct sx mlu; /* mod load unload */ 13106 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 13107 13108 static int 13109 mod_event(module_t mod, int cmd, void *arg) 13110 { 13111 int rc = 0; 13112 static int loaded = 0; 13113 13114 switch (cmd) { 13115 case MOD_LOAD: 13116 sx_xlock(&mlu); 13117 if (loaded++ == 0) { 13118 t4_sge_modload(); 13119 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13120 t4_filter_rpl, CPL_COOKIE_FILTER); 13121 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 13122 do_l2t_write_rpl, CPL_COOKIE_FILTER); 13123 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 13124 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 13125 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 13126 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 13127 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 13128 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 13129 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 13130 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 13131 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 13132 do_smt_write_rpl); 13133 sx_init(&t4_list_lock, "T4/T5 adapters"); 13134 SLIST_INIT(&t4_list); 13135 callout_init(&fatal_callout, 1); 13136 #ifdef TCP_OFFLOAD 13137 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 13138 SLIST_INIT(&t4_uld_list); 13139 #endif 13140 #ifdef INET6 13141 t4_clip_modload(); 13142 #endif 13143 #ifdef KERN_TLS 13144 t6_ktls_modload(); 13145 #endif 13146 t4_tracer_modload(); 13147 tweak_tunables(); 13148 vxlan_start_evtag = 13149 EVENTHANDLER_REGISTER(vxlan_start, 13150 t4_vxlan_start_handler, NULL, 13151 EVENTHANDLER_PRI_ANY); 13152 vxlan_stop_evtag = 13153 EVENTHANDLER_REGISTER(vxlan_stop, 13154 t4_vxlan_stop_handler, NULL, 13155 EVENTHANDLER_PRI_ANY); 13156 reset_tq = taskqueue_create("t4_rst_tq", M_WAITOK, 13157 taskqueue_thread_enqueue, &reset_tq); 13158 taskqueue_start_threads(&reset_tq, 1, PI_SOFT, 13159 "t4_rst_thr"); 13160 } 13161 sx_xunlock(&mlu); 13162 break; 13163 13164 case MOD_UNLOAD: 13165 sx_xlock(&mlu); 13166 if (--loaded == 0) { 13167 int tries; 13168 13169 taskqueue_free(reset_tq); 13170 sx_slock(&t4_list_lock); 13171 if (!SLIST_EMPTY(&t4_list)) { 13172 rc = EBUSY; 13173 sx_sunlock(&t4_list_lock); 13174 goto done_unload; 13175 } 13176 #ifdef TCP_OFFLOAD 13177 sx_slock(&t4_uld_list_lock); 13178 if (!SLIST_EMPTY(&t4_uld_list)) { 13179 rc = EBUSY; 13180 sx_sunlock(&t4_uld_list_lock); 13181 sx_sunlock(&t4_list_lock); 13182 goto done_unload; 13183 } 13184 #endif 13185 tries = 0; 13186 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 13187 uprintf("%ju clusters with custom free routine " 13188 "still is use.\n", t4_sge_extfree_refs()); 13189 pause("t4unload", 2 * hz); 13190 } 13191 #ifdef TCP_OFFLOAD 13192 sx_sunlock(&t4_uld_list_lock); 13193 #endif 13194 sx_sunlock(&t4_list_lock); 13195 13196 if (t4_sge_extfree_refs() == 0) { 13197 EVENTHANDLER_DEREGISTER(vxlan_start, 13198 vxlan_start_evtag); 13199 EVENTHANDLER_DEREGISTER(vxlan_stop, 13200 vxlan_stop_evtag); 13201 t4_tracer_modunload(); 13202 #ifdef KERN_TLS 13203 t6_ktls_modunload(); 13204 #endif 13205 #ifdef INET6 13206 t4_clip_modunload(); 13207 #endif 13208 #ifdef TCP_OFFLOAD 13209 sx_destroy(&t4_uld_list_lock); 13210 #endif 13211 sx_destroy(&t4_list_lock); 13212 t4_sge_modunload(); 13213 loaded = 0; 13214 } else { 13215 rc = EBUSY; 13216 loaded++; /* undo earlier decrement */ 13217 } 13218 } 13219 done_unload: 13220 sx_xunlock(&mlu); 13221 break; 13222 } 13223 13224 return (rc); 13225 } 13226 13227 DRIVER_MODULE(t4nex, pci, t4_driver, mod_event, 0); 13228 MODULE_VERSION(t4nex, 1); 13229 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 13230 #ifdef DEV_NETMAP 13231 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 13232 #endif /* DEV_NETMAP */ 13233 13234 DRIVER_MODULE(t5nex, pci, t5_driver, mod_event, 0); 13235 MODULE_VERSION(t5nex, 1); 13236 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 13237 #ifdef DEV_NETMAP 13238 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 13239 #endif /* DEV_NETMAP */ 13240 13241 DRIVER_MODULE(t6nex, pci, t6_driver, mod_event, 0); 13242 MODULE_VERSION(t6nex, 1); 13243 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 13244 #ifdef DEV_NETMAP 13245 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 13246 #endif /* DEV_NETMAP */ 13247 13248 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, 0, 0); 13249 MODULE_VERSION(cxgbe, 1); 13250 13251 DRIVER_MODULE(cxl, t5nex, cxl_driver, 0, 0); 13252 MODULE_VERSION(cxl, 1); 13253 13254 DRIVER_MODULE(cc, t6nex, cc_driver, 0, 0); 13255 MODULE_VERSION(cc, 1); 13256 13257 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, 0, 0); 13258 MODULE_VERSION(vcxgbe, 1); 13259 13260 DRIVER_MODULE(vcxl, cxl, vcxl_driver, 0, 0); 13261 MODULE_VERSION(vcxl, 1); 13262 13263 DRIVER_MODULE(vcc, cc, vcc_driver, 0, 0); 13264 MODULE_VERSION(vcc, 1);
Cache object: 8976a320b4e3494a0c6b9e8a4b86ba2c
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