Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/cxgbe/t4_netmap.c
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1 /*- 2 * Copyright (c) 2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #ifdef DEV_NETMAP 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/lock.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/selinfo.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <machine/bus.h> 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/if_media.h> 48 #include <net/if_var.h> 49 #include <net/if_clone.h> 50 #include <net/if_types.h> 51 #include <net/netmap.h> 52 #include <dev/netmap/netmap_kern.h> 53 54 #include "common/common.h" 55 #include "common/t4_regs.h" 56 #include "common/t4_regs_values.h" 57 58 extern int fl_pad; /* XXXNM */ 59 60 /* 61 * 0 = normal netmap rx 62 * 1 = black hole 63 * 2 = supermassive black hole (buffer packing enabled) 64 */ 65 int black_hole = 0; 66 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RWTUN, &black_hole, 0, 67 "Sink incoming packets."); 68 69 int rx_ndesc = 256; 70 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN, 71 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated."); 72 73 int rx_nframes = 64; 74 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_nframes, CTLFLAG_RWTUN, 75 &rx_nframes, 0, "max # of frames received before waking up netmap rx."); 76 77 int holdoff_tmr_idx = 2; 78 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN, 79 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues."); 80 81 /* 82 * Congestion drops. 83 * -1: no congestion feedback (not recommended). 84 * 0: backpressure the channel instead of dropping packets right away. 85 * 1: no backpressure, drop packets for the congested queue immediately. 86 */ 87 static int nm_cong_drop = 1; 88 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_cong_drop, CTLFLAG_RWTUN, 89 &nm_cong_drop, 0, 90 "Congestion control for netmap rx queues (0 = backpressure, 1 = drop"); 91 92 int starve_fl = 0; 93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, starve_fl, CTLFLAG_RWTUN, 94 &starve_fl, 0, "Don't ring fl db for netmap rx queues."); 95 96 /* 97 * Try to process tx credits in bulk. This may cause a delay in the return of 98 * tx credits and is suitable for bursty or non-stop tx only. 99 */ 100 int lazy_tx_credit_flush = 1; 101 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lazy_tx_credit_flush, CTLFLAG_RWTUN, 102 &lazy_tx_credit_flush, 0, "lazy credit flush for netmap tx queues."); 103 104 /* 105 * Split the netmap rx queues into two groups that populate separate halves of 106 * the RSS indirection table. This allows filters with hashmask to steer to a 107 * particular group of queues. 108 */ 109 static int nm_split_rss = 0; 110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_split_rss, CTLFLAG_RWTUN, 111 &nm_split_rss, 0, "Split the netmap rx queues into two groups."); 112 113 /* 114 * netmap(4) says "netmap does not use features such as checksum offloading, TCP 115 * segmentation offloading, encryption, VLAN encapsulation/decapsulation, etc." 116 * but this knob can be used to get the hardware to checksum all tx traffic 117 * anyway. 118 */ 119 static int nm_txcsum = 0; 120 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_txcsum, CTLFLAG_RWTUN, 121 &nm_txcsum, 0, "Enable transmit checksum offloading."); 122 123 static int free_nm_rxq_hwq(struct vi_info *, struct sge_nm_rxq *); 124 static int free_nm_txq_hwq(struct vi_info *, struct sge_nm_txq *); 125 126 int 127 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 128 int idx) 129 { 130 int rc; 131 struct sysctl_oid *oid; 132 struct sysctl_oid_list *children; 133 struct sysctl_ctx_list *ctx; 134 char name[16]; 135 size_t len; 136 struct adapter *sc = vi->adapter; 137 struct netmap_adapter *na = NA(vi->ifp); 138 139 MPASS(na != NULL); 140 141 len = vi->qsize_rxq * IQ_ESIZE; 142 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 143 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 144 if (rc != 0) 145 return (rc); 146 147 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 148 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 149 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 150 if (rc != 0) 151 return (rc); 152 153 nm_rxq->vi = vi; 154 nm_rxq->nid = idx; 155 nm_rxq->iq_cidx = 0; 156 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 157 nm_rxq->iq_gen = F_RSPD_GEN; 158 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 159 nm_rxq->fl_sidx = na->num_rx_desc; 160 nm_rxq->fl_sidx2 = nm_rxq->fl_sidx; /* copy for rxsync cacheline */ 161 nm_rxq->intr_idx = intr_idx; 162 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 163 164 ctx = &vi->ctx; 165 children = SYSCTL_CHILDREN(vi->nm_rxq_oid); 166 167 snprintf(name, sizeof(name), "%d", idx); 168 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, 169 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue"); 170 children = SYSCTL_CHILDREN(oid); 171 172 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 173 &nm_rxq->iq_abs_id, 0, "absolute id of the queue"); 174 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 175 &nm_rxq->iq_cntxt_id, 0, "SGE context id of the queue"); 176 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 177 &nm_rxq->iq_cidx, 0, "consumer index"); 178 179 children = SYSCTL_CHILDREN(oid); 180 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 181 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 182 children = SYSCTL_CHILDREN(oid); 183 184 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 185 &nm_rxq->fl_cntxt_id, 0, "SGE context id of the freelist"); 186 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 187 &nm_rxq->fl_cidx, 0, "consumer index"); 188 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 189 &nm_rxq->fl_pidx, 0, "producer index"); 190 191 return (rc); 192 } 193 194 int 195 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 196 { 197 struct adapter *sc = vi->adapter; 198 199 if (!(vi->flags & VI_INIT_DONE)) 200 return (0); 201 202 if (nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID) 203 free_nm_rxq_hwq(vi, nm_rxq); 204 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 205 206 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 207 nm_rxq->iq_desc); 208 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 209 nm_rxq->fl_desc); 210 211 return (0); 212 } 213 214 int 215 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx) 216 { 217 int rc; 218 size_t len; 219 struct port_info *pi = vi->pi; 220 struct adapter *sc = pi->adapter; 221 struct netmap_adapter *na = NA(vi->ifp); 222 char name[16]; 223 struct sysctl_oid *oid; 224 struct sysctl_oid_list *children = SYSCTL_CHILDREN(vi->nm_txq_oid); 225 226 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 227 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 228 &nm_txq->ba, (void **)&nm_txq->desc); 229 if (rc) 230 return (rc); 231 232 nm_txq->pidx = nm_txq->cidx = 0; 233 nm_txq->sidx = na->num_tx_desc; 234 nm_txq->nid = idx; 235 nm_txq->iqidx = iqidx; 236 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 237 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 238 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 239 if (sc->params.fw_vers >= FW_VERSION32(1, 24, 11, 0)) 240 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR)); 241 else 242 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 243 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 244 245 snprintf(name, sizeof(name), "%d", idx); 246 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, 247 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queue"); 248 children = SYSCTL_CHILDREN(oid); 249 250 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 251 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 252 SYSCTL_ADD_U16(&vi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 253 &nm_txq->cidx, 0, "consumer index"); 254 SYSCTL_ADD_U16(&vi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 255 &nm_txq->pidx, 0, "producer index"); 256 257 return (rc); 258 } 259 260 int 261 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 262 { 263 struct adapter *sc = vi->adapter; 264 265 if (!(vi->flags & VI_INIT_DONE)) 266 return (0); 267 268 if (nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID) 269 free_nm_txq_hwq(vi, nm_txq); 270 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 271 272 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 273 nm_txq->desc); 274 275 return (0); 276 } 277 278 static int 279 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 280 { 281 int rc, cntxt_id; 282 __be32 v; 283 struct adapter *sc = vi->adapter; 284 struct port_info *pi = vi->pi; 285 struct sge_params *sp = &sc->params.sge; 286 struct netmap_adapter *na = NA(vi->ifp); 287 struct fw_iq_cmd c; 288 const int cong_drop = nm_cong_drop; 289 const int cong_map = pi->rx_e_chan_map; 290 291 MPASS(na != NULL); 292 MPASS(nm_rxq->iq_desc != NULL); 293 MPASS(nm_rxq->fl_desc != NULL); 294 295 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE); 296 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len); 297 298 bzero(&c, sizeof(c)); 299 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 300 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 301 V_FW_IQ_CMD_VFN(0)); 302 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_IQSTART | FW_LEN16(c)); 303 if (nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID) 304 c.alloc_to_len16 |= htobe32(F_FW_IQ_CMD_ALLOC); 305 else { 306 c.iqid = htobe16(nm_rxq->iq_cntxt_id); 307 c.fl0id = htobe16(nm_rxq->fl_cntxt_id); 308 c.fl1id = htobe16(0xffff); 309 c.physiqid = htobe16(nm_rxq->iq_abs_id); 310 } 311 MPASS(!forwarding_intr_to_fwq(sc)); 312 KASSERT(nm_rxq->intr_idx < sc->intr_count, 313 ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx)); 314 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx); 315 c.type_to_iqandstindex = htobe32(v | 316 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 317 V_FW_IQ_CMD_VIID(vi->viid) | 318 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 319 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 320 F_FW_IQ_CMD_IQGTSMODE | 321 V_FW_IQ_CMD_IQINTCNTTHRESH(0) | 322 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 323 c.iqsize = htobe16(vi->qsize_rxq); 324 c.iqaddr = htobe64(nm_rxq->iq_ba); 325 if (cong_drop != -1) { 326 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN | 327 V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) | F_FW_IQ_CMD_FL0CONGCIF | 328 F_FW_IQ_CMD_FL0CONGEN); 329 } 330 c.iqns_to_fl0congen |= 331 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 332 V_FW_IQ_CMD_IQTYPE(FW_IQ_IQTYPE_NIC) | 333 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 334 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 335 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0)); 336 c.fl0dcaen_to_fl0cidxfthresh = 337 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 338 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 339 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 340 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 341 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE); 342 c.fl0addr = htobe64(nm_rxq->fl_ba); 343 344 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 345 if (rc != 0) { 346 device_printf(sc->dev, 347 "failed to create netmap ingress queue: %d\n", rc); 348 return (rc); 349 } 350 351 nm_rxq->iq_cidx = 0; 352 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE); 353 nm_rxq->iq_gen = F_RSPD_GEN; 354 nm_rxq->iq_cntxt_id = be16toh(c.iqid); 355 nm_rxq->iq_abs_id = be16toh(c.physiqid); 356 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start; 357 if (cntxt_id >= sc->sge.iqmap_sz) { 358 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)", 359 __func__, cntxt_id, sc->sge.iqmap_sz - 1); 360 } 361 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq; 362 363 nm_rxq->fl_cntxt_id = be16toh(c.fl0id); 364 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 365 nm_rxq->fl_db_saved = 0; 366 /* matches the X_FETCHBURSTMAX_512B or X_FETCHBURSTMAX_256B above. */ 367 nm_rxq->fl_db_threshold = chip_id(sc) <= CHELSIO_T5 ? 8 : 4; 368 MPASS(nm_rxq->fl_sidx == na->num_rx_desc); 369 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start; 370 if (cntxt_id >= sc->sge.eqmap_sz) { 371 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)", 372 __func__, cntxt_id, sc->sge.eqmap_sz - 1); 373 } 374 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq; 375 376 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) | 377 sc->chip_params->sge_fl_db; 378 379 if (chip_id(sc) >= CHELSIO_T5 && cong_drop != -1) { 380 t4_sge_set_conm_context(sc, nm_rxq->iq_cntxt_id, cong_drop, 381 cong_map); 382 } 383 384 t4_write_reg(sc, sc->sge_gts_reg, 385 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 386 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 387 388 return (rc); 389 } 390 391 static int 392 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 393 { 394 struct adapter *sc = vi->adapter; 395 int rc; 396 397 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 398 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff); 399 if (rc != 0) 400 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n", 401 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc); 402 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 403 return (rc); 404 } 405 406 static int 407 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 408 { 409 int rc, cntxt_id; 410 size_t len; 411 struct adapter *sc = vi->adapter; 412 struct netmap_adapter *na = NA(vi->ifp); 413 struct fw_eq_eth_cmd c; 414 415 MPASS(na != NULL); 416 MPASS(nm_txq->desc != NULL); 417 418 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 419 bzero(nm_txq->desc, len); 420 421 bzero(&c, sizeof(c)); 422 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 423 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 424 V_FW_EQ_ETH_CMD_VFN(0)); 425 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 426 if (nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID) 427 c.alloc_to_len16 |= htobe32(F_FW_EQ_ETH_CMD_ALLOC); 428 else 429 c.eqid_pkd = htobe32(V_FW_EQ_ETH_CMD_EQID(nm_txq->cntxt_id)); 430 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 431 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 432 c.fetchszm_to_iqid = 433 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 434 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 435 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id)); 436 c.dcaen_to_eqsize = 437 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 438 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 439 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 440 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE)); 441 c.eqaddr = htobe64(nm_txq->ba); 442 443 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 444 if (rc != 0) { 445 device_printf(vi->dev, 446 "failed to create netmap egress queue: %d\n", rc); 447 return (rc); 448 } 449 450 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 451 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start; 452 if (cntxt_id >= sc->sge.eqmap_sz) 453 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__, 454 cntxt_id, sc->sge.eqmap_sz - 1); 455 sc->sge.eqmap[cntxt_id] = (void *)nm_txq; 456 457 nm_txq->pidx = nm_txq->cidx = 0; 458 MPASS(nm_txq->sidx == na->num_tx_desc); 459 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0; 460 461 nm_txq->doorbells = sc->doorbells; 462 if (isset(&nm_txq->doorbells, DOORBELL_UDB) || 463 isset(&nm_txq->doorbells, DOORBELL_UDBWC) || 464 isset(&nm_txq->doorbells, DOORBELL_WCWR)) { 465 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 466 uint32_t mask = (1 << s_qpp) - 1; 467 volatile uint8_t *udb; 468 469 udb = sc->udbs_base + UDBS_DB_OFFSET; 470 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT; 471 nm_txq->udb_qid = nm_txq->cntxt_id & mask; 472 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 473 clrbit(&nm_txq->doorbells, DOORBELL_WCWR); 474 else { 475 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT; 476 nm_txq->udb_qid = 0; 477 } 478 nm_txq->udb = (volatile void *)udb; 479 } 480 481 if (sc->params.fw_vers < FW_VERSION32(1, 25, 1, 0)) { 482 uint32_t param, val; 483 484 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 485 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) | 486 V_FW_PARAMS_PARAM_YZ(nm_txq->cntxt_id); 487 val = 0xff; 488 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 489 if (rc != 0) { 490 device_printf(vi->dev, 491 "failed to bind netmap txq %d to class 0xff: %d\n", 492 nm_txq->cntxt_id, rc); 493 rc = 0; 494 } 495 } 496 497 return (rc); 498 } 499 500 static int 501 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 502 { 503 struct adapter *sc = vi->adapter; 504 int rc; 505 506 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id); 507 if (rc != 0) 508 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__, 509 nm_txq->cntxt_id, rc); 510 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 511 return (rc); 512 } 513 514 static int 515 cxgbe_netmap_simple_rss(struct adapter *sc, struct vi_info *vi, 516 struct ifnet *ifp, struct netmap_adapter *na) 517 { 518 struct netmap_kring *kring; 519 struct sge_nm_rxq *nm_rxq; 520 int rc, i, j, nm_state, defq; 521 uint16_t *rss; 522 523 /* 524 * Check if there's at least one active (or about to go active) netmap 525 * rx queue. 526 */ 527 defq = -1; 528 for_each_nm_rxq(vi, j, nm_rxq) { 529 nm_state = atomic_load_int(&nm_rxq->nm_state); 530 kring = na->rx_rings[nm_rxq->nid]; 531 if ((nm_state != NM_OFF && !nm_kring_pending_off(kring)) || 532 (nm_state == NM_OFF && nm_kring_pending_on(kring))) { 533 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 534 if (defq == -1) { 535 defq = nm_rxq->iq_abs_id; 536 break; 537 } 538 } 539 } 540 541 if (defq == -1) { 542 /* No active netmap queues. Switch back to NIC queues. */ 543 rss = vi->rss; 544 defq = vi->rss[0]; 545 } else { 546 for (i = 0; i < vi->rss_size;) { 547 for_each_nm_rxq(vi, j, nm_rxq) { 548 nm_state = atomic_load_int(&nm_rxq->nm_state); 549 kring = na->rx_rings[nm_rxq->nid]; 550 if ((nm_state != NM_OFF && 551 !nm_kring_pending_off(kring)) || 552 (nm_state == NM_OFF && 553 nm_kring_pending_on(kring))) { 554 MPASS(nm_rxq->iq_cntxt_id != 555 INVALID_NM_RXQ_CNTXT_ID); 556 vi->nm_rss[i++] = nm_rxq->iq_abs_id; 557 if (i == vi->rss_size) 558 break; 559 } 560 } 561 } 562 rss = vi->nm_rss; 563 } 564 565 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 566 vi->rss_size); 567 if (rc != 0) 568 if_printf(ifp, "netmap rss_config failed: %d\n", rc); 569 570 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0); 571 if (rc != 0) { 572 if_printf(ifp, "netmap defaultq config failed: %d\n", rc); 573 } 574 575 return (rc); 576 } 577 578 /* 579 * Odd number of rx queues work best for split RSS mode as the first queue can 580 * be dedicated for non-RSS traffic and the rest divided into two equal halves. 581 */ 582 static int 583 cxgbe_netmap_split_rss(struct adapter *sc, struct vi_info *vi, 584 struct ifnet *ifp, struct netmap_adapter *na) 585 { 586 struct netmap_kring *kring; 587 struct sge_nm_rxq *nm_rxq; 588 int rc, i, j, nm_state, defq; 589 int nactive[2] = {0, 0}; 590 int dq[2] = {-1, -1}; 591 bool dq_norss; /* default queue should not be in RSS table. */ 592 593 MPASS(nm_split_rss != 0); 594 MPASS(vi->nnmrxq > 1); 595 596 for_each_nm_rxq(vi, i, nm_rxq) { 597 j = i / ((vi->nnmrxq + 1) / 2); 598 nm_state = atomic_load_int(&nm_rxq->nm_state); 599 kring = na->rx_rings[nm_rxq->nid]; 600 if ((nm_state != NM_OFF && !nm_kring_pending_off(kring)) || 601 (nm_state == NM_OFF && nm_kring_pending_on(kring))) { 602 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 603 nactive[j]++; 604 if (dq[j] == -1) { 605 dq[j] = nm_rxq->iq_abs_id; 606 break; 607 } 608 } 609 } 610 611 if (nactive[0] == 0 || nactive[1] == 0) 612 return (cxgbe_netmap_simple_rss(sc, vi, ifp, na)); 613 614 MPASS(dq[0] != -1 && dq[1] != -1); 615 if (nactive[0] > nactive[1]) { 616 defq = dq[0]; 617 dq_norss = true; 618 } else if (nactive[0] < nactive[1]) { 619 defq = dq[1]; 620 dq_norss = true; 621 } else { 622 defq = dq[0]; 623 dq_norss = false; 624 } 625 626 i = 0; 627 nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq]; 628 while (i < vi->rss_size / 2) { 629 for (j = 0; j < (vi->nnmrxq + 1) / 2; j++) { 630 nm_state = atomic_load_int(&nm_rxq[j].nm_state); 631 kring = na->rx_rings[nm_rxq[j].nid]; 632 if ((nm_state == NM_OFF && 633 !nm_kring_pending_on(kring)) || 634 (nm_state == NM_ON && 635 nm_kring_pending_off(kring))) { 636 continue; 637 } 638 MPASS(nm_rxq[j].iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 639 if (dq_norss && defq == nm_rxq[j].iq_abs_id) 640 continue; 641 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 642 if (i == vi->rss_size / 2) 643 break; 644 } 645 } 646 while (i < vi->rss_size) { 647 for (j = (vi->nnmrxq + 1) / 2; j < vi->nnmrxq; j++) { 648 nm_state = atomic_load_int(&nm_rxq[j].nm_state); 649 kring = na->rx_rings[nm_rxq[j].nid]; 650 if ((nm_state == NM_OFF && 651 !nm_kring_pending_on(kring)) || 652 (nm_state == NM_ON && 653 nm_kring_pending_off(kring))) { 654 continue; 655 } 656 MPASS(nm_rxq[j].iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 657 if (dq_norss && defq == nm_rxq[j].iq_abs_id) 658 continue; 659 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 660 if (i == vi->rss_size) 661 break; 662 } 663 } 664 665 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 666 vi->nm_rss, vi->rss_size); 667 if (rc != 0) 668 if_printf(ifp, "netmap split_rss_config failed: %d\n", rc); 669 670 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0); 671 if (rc != 0) 672 if_printf(ifp, "netmap defaultq config failed: %d\n", rc); 673 674 return (rc); 675 } 676 677 static inline int 678 cxgbe_netmap_rss(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 679 struct netmap_adapter *na) 680 { 681 682 if (nm_split_rss == 0 || vi->nnmrxq == 1) 683 return (cxgbe_netmap_simple_rss(sc, vi, ifp, na)); 684 else 685 return (cxgbe_netmap_split_rss(sc, vi, ifp, na)); 686 } 687 688 static int 689 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 690 struct netmap_adapter *na) 691 { 692 struct netmap_slot *slot; 693 struct netmap_kring *kring; 694 struct sge_nm_rxq *nm_rxq; 695 struct sge_nm_txq *nm_txq; 696 int i, j, hwidx; 697 struct rx_buf_info *rxb; 698 699 ASSERT_SYNCHRONIZED_OP(sc); 700 MPASS(vi->nnmrxq > 0); 701 MPASS(vi->nnmtxq > 0); 702 703 if ((vi->flags & VI_INIT_DONE) == 0 || 704 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 705 if_printf(ifp, "cannot enable netmap operation because " 706 "interface is not UP.\n"); 707 return (EAGAIN); 708 } 709 710 rxb = &sc->sge.rx_buf_info[0]; 711 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 712 if (rxb->size1 == NETMAP_BUF_SIZE(na)) { 713 hwidx = rxb->hwidx1; 714 break; 715 } 716 if (rxb->size2 == NETMAP_BUF_SIZE(na)) { 717 hwidx = rxb->hwidx2; 718 break; 719 } 720 } 721 if (i >= SW_ZONE_SIZES) { 722 if_printf(ifp, "no hwidx for netmap buffer size %d.\n", 723 NETMAP_BUF_SIZE(na)); 724 return (ENXIO); 725 } 726 727 /* Must set caps before calling netmap_reset */ 728 nm_set_native_flags(na); 729 730 for_each_nm_rxq(vi, i, nm_rxq) { 731 kring = na->rx_rings[nm_rxq->nid]; 732 if (!nm_kring_pending_on(kring)) 733 continue; 734 735 alloc_nm_rxq_hwq(vi, nm_rxq); 736 nm_rxq->fl_hwidx = hwidx; 737 slot = netmap_reset(na, NR_RX, i, 0); 738 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 739 740 /* We deal with 8 bufs at a time */ 741 MPASS((na->num_rx_desc & 7) == 0); 742 MPASS(na->num_rx_desc == nm_rxq->fl_sidx); 743 for (j = 0; j < nm_rxq->fl_sidx; j++) { 744 uint64_t ba; 745 746 PNMB(na, &slot[j], &ba); 747 MPASS(ba != 0); 748 nm_rxq->fl_desc[j] = htobe64(ba | hwidx); 749 } 750 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8; 751 MPASS((j & 7) == 0); 752 j /= 8; /* driver pidx to hardware pidx */ 753 wmb(); 754 t4_write_reg(sc, sc->sge_kdoorbell_reg, 755 nm_rxq->fl_db_val | V_PIDX(j)); 756 757 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON); 758 } 759 760 for_each_nm_txq(vi, i, nm_txq) { 761 kring = na->tx_rings[nm_txq->nid]; 762 if (!nm_kring_pending_on(kring)) 763 continue; 764 765 alloc_nm_txq_hwq(vi, nm_txq); 766 slot = netmap_reset(na, NR_TX, i, 0); 767 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 768 } 769 770 if (vi->nm_rss == NULL) { 771 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE, 772 M_ZERO | M_WAITOK); 773 } 774 775 return (cxgbe_netmap_rss(sc, vi, ifp, na)); 776 } 777 778 static int 779 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 780 struct netmap_adapter *na) 781 { 782 struct netmap_kring *kring; 783 int rc, i, nm_state, nactive; 784 struct sge_nm_txq *nm_txq; 785 struct sge_nm_rxq *nm_rxq; 786 787 ASSERT_SYNCHRONIZED_OP(sc); 788 MPASS(vi->nnmrxq > 0); 789 MPASS(vi->nnmtxq > 0); 790 791 if (!nm_netmap_on(na)) 792 return (0); 793 794 if ((vi->flags & VI_INIT_DONE) == 0) 795 return (0); 796 797 /* First remove the queues that are stopping from the RSS table. */ 798 rc = cxgbe_netmap_rss(sc, vi, ifp, na); 799 if (rc != 0) 800 return (rc); /* error message logged already. */ 801 802 for_each_nm_txq(vi, i, nm_txq) { 803 kring = na->tx_rings[nm_txq->nid]; 804 if (!nm_kring_pending_off(kring)) 805 continue; 806 MPASS(nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID); 807 808 rc = -t4_eth_eq_stop(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id); 809 if (rc != 0) { 810 device_printf(vi->dev, 811 "failed to stop nm_txq[%d]: %d.\n", i, rc); 812 return (rc); 813 } 814 815 /* XXX: netmap, not the driver, should do this. */ 816 kring->rhead = kring->rcur = kring->nr_hwcur = 0; 817 kring->rtail = kring->nr_hwtail = kring->nkr_num_slots - 1; 818 } 819 nactive = 0; 820 for_each_nm_rxq(vi, i, nm_rxq) { 821 nm_state = atomic_load_int(&nm_rxq->nm_state); 822 kring = na->rx_rings[nm_rxq->nid]; 823 if (nm_state != NM_OFF && !nm_kring_pending_off(kring)) 824 nactive++; 825 if (!nm_kring_pending_off(kring)) 826 continue; 827 MPASS(nm_state != NM_OFF); 828 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 829 830 rc = -t4_iq_stop(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 831 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff); 832 if (rc != 0) { 833 device_printf(vi->dev, 834 "failed to stop nm_rxq[%d]: %d.\n", i, rc); 835 return (rc); 836 } 837 838 while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF)) 839 pause("nmst", 1); 840 841 /* XXX: netmap, not the driver, should do this. */ 842 kring->rhead = kring->rcur = kring->nr_hwcur = 0; 843 kring->rtail = kring->nr_hwtail = 0; 844 } 845 netmap_krings_mode_commit(na, 0); 846 if (nactive == 0) 847 nm_clear_native_flags(na); 848 849 return (rc); 850 } 851 852 static int 853 cxgbe_netmap_reg(struct netmap_adapter *na, int on) 854 { 855 struct ifnet *ifp = na->ifp; 856 struct vi_info *vi = ifp->if_softc; 857 struct adapter *sc = vi->adapter; 858 int rc; 859 860 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg"); 861 if (rc != 0) 862 return (rc); 863 if (on) 864 rc = cxgbe_netmap_on(sc, vi, ifp, na); 865 else 866 rc = cxgbe_netmap_off(sc, vi, ifp, na); 867 end_synchronized_op(sc, 0); 868 869 return (rc); 870 } 871 872 /* How many packets can a single type1 WR carry in n descriptors */ 873 static inline int 874 ndesc_to_npkt(const int n) 875 { 876 877 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC); 878 879 return (n * 2 - 1); 880 } 881 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC)) 882 883 /* 884 * Space (in descriptors) needed for a type1 WR (TX_PKTS or TX_PKTS2) that 885 * carries n packets 886 */ 887 static inline int 888 npkt_to_ndesc(const int n) 889 { 890 891 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 892 893 return ((n + 2) / 2); 894 } 895 896 /* 897 * Space (in 16B units) needed for a type1 WR (TX_PKTS or TX_PKTS2) that 898 * carries n packets 899 */ 900 static inline int 901 npkt_to_len16(const int n) 902 { 903 904 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 905 906 return (n * 2 + 1); 907 } 908 909 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx) 910 911 static void 912 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq) 913 { 914 int n; 915 u_int db = nm_txq->doorbells; 916 917 MPASS(nm_txq->pidx != nm_txq->dbidx); 918 919 n = NMIDXDIFF(nm_txq, dbidx); 920 if (n > 1) 921 clrbit(&db, DOORBELL_WCWR); 922 wmb(); 923 924 switch (ffs(db) - 1) { 925 case DOORBELL_UDB: 926 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 927 break; 928 929 case DOORBELL_WCWR: { 930 volatile uint64_t *dst, *src; 931 932 /* 933 * Queues whose 128B doorbell segment fits in the page do not 934 * use relative qid (udb_qid is always 0). Only queues with 935 * doorbell segments can do WCWR. 936 */ 937 KASSERT(nm_txq->udb_qid == 0 && n == 1, 938 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p", 939 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq)); 940 941 dst = (volatile void *)((uintptr_t)nm_txq->udb + 942 UDBS_WR_OFFSET - UDBS_DB_OFFSET); 943 src = (void *)&nm_txq->desc[nm_txq->dbidx]; 944 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1]) 945 *dst++ = *src++; 946 wmb(); 947 break; 948 } 949 950 case DOORBELL_UDBWC: 951 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 952 wmb(); 953 break; 954 955 case DOORBELL_KDB: 956 t4_write_reg(sc, sc->sge_kdoorbell_reg, 957 V_QID(nm_txq->cntxt_id) | V_PIDX(n)); 958 break; 959 } 960 nm_txq->dbidx = nm_txq->pidx; 961 } 962 963 /* 964 * Write work requests to send 'npkt' frames and ring the doorbell to send them 965 * on their way. No need to check for wraparound. 966 */ 967 static void 968 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq, 969 struct netmap_kring *kring, int npkt, int npkt_remaining) 970 { 971 struct netmap_ring *ring = kring->ring; 972 struct netmap_slot *slot; 973 const u_int lim = kring->nkr_num_slots - 1; 974 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx]; 975 uint16_t len; 976 uint64_t ba; 977 struct cpl_tx_pkt_core *cpl; 978 struct ulptx_sgl *usgl; 979 int i, n; 980 981 while (npkt) { 982 n = min(npkt, MAX_NPKT_IN_TYPE1_WR); 983 len = 0; 984 985 wr = (void *)&nm_txq->desc[nm_txq->pidx]; 986 wr->op_pkd = nm_txq->op_pkd; 987 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n))); 988 wr->npkt = n; 989 wr->r3 = 0; 990 wr->type = 1; 991 cpl = (void *)(wr + 1); 992 993 for (i = 0; i < n; i++) { 994 slot = &ring->slot[kring->nr_hwcur]; 995 PNMB(kring->na, slot, &ba); 996 MPASS(ba != 0); 997 998 cpl->ctrl0 = nm_txq->cpl_ctrl0; 999 cpl->pack = 0; 1000 cpl->len = htobe16(slot->len); 1001 cpl->ctrl1 = nm_txcsum ? 0 : 1002 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 1003 1004 usgl = (void *)(cpl + 1); 1005 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 1006 V_ULPTX_NSGE(1)); 1007 usgl->len0 = htobe32(slot->len); 1008 usgl->addr0 = htobe64(ba); 1009 1010 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1011 cpl = (void *)(usgl + 1); 1012 MPASS(slot->len + len <= UINT16_MAX); 1013 len += slot->len; 1014 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim); 1015 } 1016 wr->plen = htobe16(len); 1017 1018 npkt -= n; 1019 nm_txq->pidx += npkt_to_ndesc(n); 1020 MPASS(nm_txq->pidx <= nm_txq->sidx); 1021 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) { 1022 /* 1023 * This routine doesn't know how to write WRs that wrap 1024 * around. Make sure it wasn't asked to. 1025 */ 1026 MPASS(npkt == 0); 1027 nm_txq->pidx = 0; 1028 } 1029 1030 if (npkt == 0 && npkt_remaining == 0) { 1031 /* All done. */ 1032 if (lazy_tx_credit_flush == 0) { 1033 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 1034 F_FW_WR_EQUIQ); 1035 nm_txq->equeqidx = nm_txq->pidx; 1036 nm_txq->equiqidx = nm_txq->pidx; 1037 } 1038 ring_nm_txq_db(sc, nm_txq); 1039 return; 1040 } 1041 1042 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) { 1043 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 1044 F_FW_WR_EQUIQ); 1045 nm_txq->equeqidx = nm_txq->pidx; 1046 nm_txq->equiqidx = nm_txq->pidx; 1047 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) { 1048 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 1049 nm_txq->equeqidx = nm_txq->pidx; 1050 } 1051 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC) 1052 ring_nm_txq_db(sc, nm_txq); 1053 } 1054 1055 /* Will get called again. */ 1056 MPASS(npkt_remaining); 1057 } 1058 1059 /* How many contiguous free descriptors starting at pidx */ 1060 static inline int 1061 contiguous_ndesc_available(struct sge_nm_txq *nm_txq) 1062 { 1063 1064 if (nm_txq->cidx > nm_txq->pidx) 1065 return (nm_txq->cidx - nm_txq->pidx - 1); 1066 else if (nm_txq->cidx > 0) 1067 return (nm_txq->sidx - nm_txq->pidx); 1068 else 1069 return (nm_txq->sidx - nm_txq->pidx - 1); 1070 } 1071 1072 static int 1073 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq) 1074 { 1075 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 1076 uint16_t hw_cidx = spg->cidx; /* snapshot */ 1077 struct fw_eth_tx_pkts_wr *wr; 1078 int n = 0; 1079 1080 hw_cidx = be16toh(hw_cidx); 1081 1082 while (nm_txq->cidx != hw_cidx) { 1083 wr = (void *)&nm_txq->desc[nm_txq->cidx]; 1084 1085 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)) || 1086 wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR))); 1087 MPASS(wr->type == 1); 1088 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR); 1089 1090 n += wr->npkt; 1091 nm_txq->cidx += npkt_to_ndesc(wr->npkt); 1092 1093 /* 1094 * We never sent a WR that wrapped around so the credits coming 1095 * back, WR by WR, should never cause the cidx to wrap around 1096 * either. 1097 */ 1098 MPASS(nm_txq->cidx <= nm_txq->sidx); 1099 if (__predict_false(nm_txq->cidx == nm_txq->sidx)) 1100 nm_txq->cidx = 0; 1101 } 1102 1103 return (n); 1104 } 1105 1106 static int 1107 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags) 1108 { 1109 struct netmap_adapter *na = kring->na; 1110 struct ifnet *ifp = na->ifp; 1111 struct vi_info *vi = ifp->if_softc; 1112 struct adapter *sc = vi->adapter; 1113 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id]; 1114 const u_int head = kring->rhead; 1115 u_int reclaimed = 0; 1116 int n, d, npkt_remaining, ndesc_remaining; 1117 1118 /* 1119 * Tx was at kring->nr_hwcur last time around and now we need to advance 1120 * to kring->rhead. Note that the driver's pidx moves independent of 1121 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation 1122 * between descriptors and frames isn't 1:1). 1123 */ 1124 1125 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 1126 kring->nkr_num_slots - kring->nr_hwcur + head; 1127 while (npkt_remaining) { 1128 reclaimed += reclaim_nm_tx_desc(nm_txq); 1129 ndesc_remaining = contiguous_ndesc_available(nm_txq); 1130 /* Can't run out of descriptors with packets still remaining */ 1131 MPASS(ndesc_remaining > 0); 1132 1133 /* # of desc needed to tx all remaining packets */ 1134 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC; 1135 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR) 1136 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR); 1137 1138 if (d <= ndesc_remaining) 1139 n = npkt_remaining; 1140 else { 1141 /* Can't send all, calculate how many can be sent */ 1142 n = (ndesc_remaining / SGE_MAX_WR_NDESC) * 1143 MAX_NPKT_IN_TYPE1_WR; 1144 if (ndesc_remaining % SGE_MAX_WR_NDESC) 1145 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC); 1146 } 1147 1148 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */ 1149 npkt_remaining -= n; 1150 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining); 1151 } 1152 MPASS(npkt_remaining == 0); 1153 MPASS(kring->nr_hwcur == head); 1154 MPASS(nm_txq->dbidx == nm_txq->pidx); 1155 1156 /* 1157 * Second part: reclaim buffers for completed transmissions. 1158 */ 1159 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) { 1160 reclaimed += reclaim_nm_tx_desc(nm_txq); 1161 kring->nr_hwtail += reclaimed; 1162 if (kring->nr_hwtail >= kring->nkr_num_slots) 1163 kring->nr_hwtail -= kring->nkr_num_slots; 1164 } 1165 1166 return (0); 1167 } 1168 1169 static int 1170 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags) 1171 { 1172 struct netmap_adapter *na = kring->na; 1173 struct netmap_ring *ring = kring->ring; 1174 struct ifnet *ifp = na->ifp; 1175 struct vi_info *vi = ifp->if_softc; 1176 struct adapter *sc = vi->adapter; 1177 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id]; 1178 u_int const head = kring->rhead; 1179 u_int n; 1180 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1181 1182 if (black_hole) 1183 return (0); /* No updates ever. */ 1184 1185 if (netmap_no_pendintr || force_update) { 1186 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx); 1187 kring->nr_kflags &= ~NKR_PENDINTR; 1188 } 1189 1190 if (nm_rxq->fl_db_saved > 0 && starve_fl == 0) { 1191 wmb(); 1192 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1193 nm_rxq->fl_db_val | V_PIDX(nm_rxq->fl_db_saved)); 1194 nm_rxq->fl_db_saved = 0; 1195 } 1196 1197 /* Userspace done with buffers from kring->nr_hwcur to head */ 1198 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 1199 kring->nkr_num_slots - kring->nr_hwcur + head; 1200 n &= ~7U; 1201 if (n > 0) { 1202 u_int fl_pidx = nm_rxq->fl_pidx; 1203 struct netmap_slot *slot = &ring->slot[fl_pidx]; 1204 uint64_t ba; 1205 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx; 1206 1207 /* 1208 * We always deal with 8 buffers at a time. We must have 1209 * stopped at an 8B boundary (fl_pidx) last time around and we 1210 * must have a multiple of 8B buffers to give to the freelist. 1211 */ 1212 MPASS((fl_pidx & 7) == 0); 1213 MPASS((n & 7) == 0); 1214 1215 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots); 1216 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx2); 1217 1218 while (n > 0) { 1219 for (i = 0; i < 8; i++, fl_pidx++, slot++) { 1220 PNMB(na, slot, &ba); 1221 MPASS(ba != 0); 1222 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx); 1223 slot->flags &= ~NS_BUF_CHANGED; 1224 MPASS(fl_pidx <= nm_rxq->fl_sidx2); 1225 } 1226 n -= 8; 1227 if (fl_pidx == nm_rxq->fl_sidx2) { 1228 fl_pidx = 0; 1229 slot = &ring->slot[0]; 1230 } 1231 if (++dbinc == nm_rxq->fl_db_threshold) { 1232 wmb(); 1233 if (starve_fl) 1234 nm_rxq->fl_db_saved += dbinc; 1235 else { 1236 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1237 nm_rxq->fl_db_val | V_PIDX(dbinc)); 1238 } 1239 dbinc = 0; 1240 } 1241 } 1242 MPASS(nm_rxq->fl_pidx == fl_pidx); 1243 1244 if (dbinc > 0) { 1245 wmb(); 1246 if (starve_fl) 1247 nm_rxq->fl_db_saved += dbinc; 1248 else { 1249 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1250 nm_rxq->fl_db_val | V_PIDX(dbinc)); 1251 } 1252 } 1253 } 1254 1255 return (0); 1256 } 1257 1258 void 1259 cxgbe_nm_attach(struct vi_info *vi) 1260 { 1261 struct port_info *pi; 1262 struct adapter *sc; 1263 struct netmap_adapter na; 1264 1265 MPASS(vi->nnmrxq > 0); 1266 MPASS(vi->ifp != NULL); 1267 1268 pi = vi->pi; 1269 sc = pi->adapter; 1270 1271 bzero(&na, sizeof(na)); 1272 1273 na.ifp = vi->ifp; 1274 na.na_flags = NAF_BDG_MAYSLEEP; 1275 1276 /* Netmap doesn't know about the space reserved for the status page. */ 1277 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE; 1278 1279 /* 1280 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So 1281 * num_rx_desc is based on the number of buffers that can be held in the 1282 * freelist, and not the number of entries in the iq. (These two are 1283 * not exactly the same due to the space taken up by the status page). 1284 */ 1285 na.num_rx_desc = rounddown(vi->qsize_rxq, 8); 1286 na.nm_txsync = cxgbe_netmap_txsync; 1287 na.nm_rxsync = cxgbe_netmap_rxsync; 1288 na.nm_register = cxgbe_netmap_reg; 1289 na.num_tx_rings = vi->nnmtxq; 1290 na.num_rx_rings = vi->nnmrxq; 1291 na.rx_buf_maxsize = MAX_MTU; 1292 netmap_attach(&na); /* This adds IFCAP_NETMAP to if_capabilities */ 1293 } 1294 1295 void 1296 cxgbe_nm_detach(struct vi_info *vi) 1297 { 1298 1299 MPASS(vi->nnmrxq > 0); 1300 MPASS(vi->ifp != NULL); 1301 1302 netmap_detach(vi->ifp); 1303 } 1304 1305 static inline const void * 1306 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl) 1307 { 1308 1309 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL); 1310 1311 /* data[0] is RSS header */ 1312 return (&cpl->data[1]); 1313 } 1314 1315 static void 1316 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp, 1317 const struct cpl_sge_egr_update *egr) 1318 { 1319 uint32_t oq; 1320 struct sge_nm_txq *nm_txq; 1321 1322 oq = be32toh(egr->opcode_qid); 1323 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE); 1324 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start]; 1325 1326 netmap_tx_irq(ifp, nm_txq->nid); 1327 } 1328 1329 void 1330 service_nm_rxq(struct sge_nm_rxq *nm_rxq) 1331 { 1332 struct vi_info *vi = nm_rxq->vi; 1333 struct adapter *sc = vi->adapter; 1334 struct ifnet *ifp = vi->ifp; 1335 struct netmap_adapter *na = NA(ifp); 1336 struct netmap_kring *kring = na->rx_rings[nm_rxq->nid]; 1337 struct netmap_ring *ring = kring->ring; 1338 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx]; 1339 const void *cpl; 1340 uint32_t lq; 1341 u_int work = 0; 1342 uint8_t opcode; 1343 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx); 1344 u_int fl_credits = fl_cidx & 7; 1345 u_int ndesc = 0; /* desc processed since last cidx update */ 1346 u_int nframes = 0; /* frames processed since last netmap wakeup */ 1347 1348 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) { 1349 1350 rmb(); 1351 1352 lq = be32toh(d->rsp.pldbuflen_qid); 1353 opcode = d->rss.opcode; 1354 cpl = &d->cpl[0]; 1355 1356 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) { 1357 case X_RSPD_TYPE_FLBUF: 1358 1359 /* fall through */ 1360 1361 case X_RSPD_TYPE_CPL: 1362 MPASS(opcode < NUM_CPL_CMDS); 1363 1364 switch (opcode) { 1365 case CPL_FW4_MSG: 1366 case CPL_FW6_MSG: 1367 cpl = unwrap_nm_fw6_msg(cpl); 1368 /* fall through */ 1369 case CPL_SGE_EGR_UPDATE: 1370 handle_nm_sge_egr_update(sc, ifp, cpl); 1371 break; 1372 case CPL_RX_PKT: 1373 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - 1374 sc->params.sge.fl_pktshift; 1375 ring->slot[fl_cidx].flags = 0; 1376 nframes++; 1377 if (!(lq & F_RSPD_NEWBUF)) { 1378 MPASS(black_hole == 2); 1379 break; 1380 } 1381 fl_credits++; 1382 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx)) 1383 fl_cidx = 0; 1384 break; 1385 default: 1386 panic("%s: unexpected opcode 0x%x on nm_rxq %p", 1387 __func__, opcode, nm_rxq); 1388 } 1389 break; 1390 1391 case X_RSPD_TYPE_INTR: 1392 /* Not equipped to handle forwarded interrupts. */ 1393 panic("%s: netmap queue received interrupt for iq %u\n", 1394 __func__, lq); 1395 1396 default: 1397 panic("%s: illegal response type %d on nm_rxq %p", 1398 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq); 1399 } 1400 1401 d++; 1402 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) { 1403 nm_rxq->iq_cidx = 0; 1404 d = &nm_rxq->iq_desc[0]; 1405 nm_rxq->iq_gen ^= F_RSPD_GEN; 1406 } 1407 1408 if (__predict_false(++nframes == rx_nframes) && !black_hole) { 1409 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1410 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1411 nframes = 0; 1412 } 1413 1414 if (__predict_false(++ndesc == rx_ndesc)) { 1415 if (black_hole && fl_credits >= 8) { 1416 fl_credits /= 8; 1417 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, 1418 nm_rxq->fl_sidx); 1419 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1420 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1421 fl_credits = fl_cidx & 7; 1422 } 1423 t4_write_reg(sc, sc->sge_gts_reg, 1424 V_CIDXINC(ndesc) | 1425 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 1426 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1427 ndesc = 0; 1428 } 1429 } 1430 1431 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1432 if (black_hole) { 1433 fl_credits /= 8; 1434 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx); 1435 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1436 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1437 } else if (nframes > 0) 1438 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1439 1440 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndesc) | 1441 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) | 1442 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 1443 } 1444 #endif
Cache object: c7e6e1048483cacf95e4132400f7fe62
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