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FreeBSD/Linux Kernel Cross Reference
sys/dev/cxgbe/t4_sge.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_kern_tls.h" 36 #include "opt_ratelimit.h" 37 38 #include <sys/types.h> 39 #include <sys/eventhandler.h> 40 #include <sys/mbuf.h> 41 #include <sys/socket.h> 42 #include <sys/kernel.h> 43 #include <sys/ktls.h> 44 #include <sys/malloc.h> 45 #include <sys/msan.h> 46 #include <sys/queue.h> 47 #include <sys/sbuf.h> 48 #include <sys/taskqueue.h> 49 #include <sys/time.h> 50 #include <sys/sglist.h> 51 #include <sys/sysctl.h> 52 #include <sys/smp.h> 53 #include <sys/socketvar.h> 54 #include <sys/counter.h> 55 #include <net/bpf.h> 56 #include <net/ethernet.h> 57 #include <net/if.h> 58 #include <net/if_vlan_var.h> 59 #include <net/if_vxlan.h> 60 #include <netinet/in.h> 61 #include <netinet/ip.h> 62 #include <netinet/ip6.h> 63 #include <netinet/tcp.h> 64 #include <netinet/udp.h> 65 #include <machine/in_cksum.h> 66 #include <machine/md_var.h> 67 #include <vm/vm.h> 68 #include <vm/pmap.h> 69 #ifdef DEV_NETMAP 70 #include <machine/bus.h> 71 #include <sys/selinfo.h> 72 #include <net/if_var.h> 73 #include <net/netmap.h> 74 #include <dev/netmap/netmap_kern.h> 75 #endif 76 77 #include "common/common.h" 78 #include "common/t4_regs.h" 79 #include "common/t4_regs_values.h" 80 #include "common/t4_msg.h" 81 #include "t4_l2t.h" 82 #include "t4_mp_ring.h" 83 84 #ifdef T4_PKT_TIMESTAMP 85 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 86 #else 87 #define RX_COPY_THRESHOLD MINCLSIZE 88 #endif 89 90 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 91 #define MC_NOMAP 0x01 92 #define MC_RAW_WR 0x02 93 #define MC_TLS 0x04 94 95 /* 96 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 97 * 0-7 are valid values. 98 */ 99 static int fl_pktshift = 0; 100 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 101 "payload DMA offset in rx buffer (bytes)"); 102 103 /* 104 * Pad ethernet payload up to this boundary. 105 * -1: driver should figure out a good value. 106 * 0: disable padding. 107 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 108 */ 109 int fl_pad = -1; 110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 111 "payload pad boundary (bytes)"); 112 113 /* 114 * Status page length. 115 * -1: driver should figure out a good value. 116 * 64 or 128 are the only other valid values. 117 */ 118 static int spg_len = -1; 119 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 120 "status page size (bytes)"); 121 122 /* 123 * Congestion drops. 124 * -1: no congestion feedback (not recommended). 125 * 0: backpressure the channel instead of dropping packets right away. 126 * 1: no backpressure, drop packets for the congested queue immediately. 127 * 2: both backpressure and drop. 128 */ 129 static int cong_drop = 0; 130 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 131 "Congestion control for NIC RX queues (0 = backpressure, 1 = drop, 2 = both"); 132 #ifdef TCP_OFFLOAD 133 static int ofld_cong_drop = 0; 134 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ofld_cong_drop, CTLFLAG_RDTUN, &ofld_cong_drop, 0, 135 "Congestion control for TOE RX queues (0 = backpressure, 1 = drop, 2 = both"); 136 #endif 137 138 /* 139 * Deliver multiple frames in the same free list buffer if they fit. 140 * -1: let the driver decide whether to enable buffer packing or not. 141 * 0: disable buffer packing. 142 * 1: enable buffer packing. 143 */ 144 static int buffer_packing = -1; 145 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 146 0, "Enable buffer packing"); 147 148 /* 149 * Start next frame in a packed buffer at this boundary. 150 * -1: driver should figure out a good value. 151 * T4: driver will ignore this and use the same value as fl_pad above. 152 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 153 */ 154 static int fl_pack = -1; 155 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 156 "payload pack boundary (bytes)"); 157 158 /* 159 * Largest rx cluster size that the driver is allowed to allocate. 160 */ 161 static int largest_rx_cluster = MJUM16BYTES; 162 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 163 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 164 165 /* 166 * Size of cluster allocation that's most likely to succeed. The driver will 167 * fall back to this size if it fails to allocate clusters larger than this. 168 */ 169 static int safest_rx_cluster = PAGE_SIZE; 170 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 171 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 172 173 #ifdef RATELIMIT 174 /* 175 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 176 * for rewriting. -1 and 0-3 are all valid values. 177 * -1: hardware should leave the TCP timestamps alone. 178 * 0: 1ms 179 * 1: 100us 180 * 2: 10us 181 * 3: 1us 182 */ 183 static int tsclk = -1; 184 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 185 "Control TCP timestamp rewriting when using pacing"); 186 187 static int eo_max_backlog = 1024 * 1024; 188 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 189 0, "Maximum backlog of ratelimited data per flow"); 190 #endif 191 192 /* 193 * The interrupt holdoff timers are multiplied by this value on T6+. 194 * 1 and 3-17 (both inclusive) are legal values. 195 */ 196 static int tscale = 1; 197 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 198 "Interrupt holdoff timer scale on T6+"); 199 200 /* 201 * Number of LRO entries in the lro_ctrl structure per rx queue. 202 */ 203 static int lro_entries = TCP_LRO_ENTRIES; 204 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 205 "Number of LRO entries per RX queue"); 206 207 /* 208 * This enables presorting of frames before they're fed into tcp_lro_rx. 209 */ 210 static int lro_mbufs = 0; 211 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 212 "Enable presorting of LRO frames"); 213 214 static counter_u64_t pullups; 215 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups, 216 "Number of mbuf pullups performed"); 217 218 static counter_u64_t defrags; 219 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags, 220 "Number of mbuf defrags performed"); 221 222 static int t4_tx_coalesce = 1; 223 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0, 224 "tx coalescing allowed"); 225 226 /* 227 * The driver will make aggressive attempts at tx coalescing if it sees these 228 * many packets eligible for coalescing in quick succession, with no more than 229 * the specified gap in between the eth_tx calls that delivered the packets. 230 */ 231 static int t4_tx_coalesce_pkts = 32; 232 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN, 233 &t4_tx_coalesce_pkts, 0, 234 "# of consecutive packets (1 - 255) that will trigger tx coalescing"); 235 static int t4_tx_coalesce_gap = 5; 236 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN, 237 &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)"); 238 239 static int service_iq(struct sge_iq *, int); 240 static int service_iq_fl(struct sge_iq *, int); 241 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 242 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *, 243 u_int); 244 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 245 int, int, int); 246 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 247 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 248 struct sge_iq *, char *); 249 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 250 struct sysctl_ctx_list *, struct sysctl_oid *); 251 static void free_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 252 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 253 struct sge_iq *); 254 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 255 struct sysctl_oid *, struct sge_fl *); 256 static int alloc_iq_fl_hwq(struct vi_info *, struct sge_iq *, struct sge_fl *); 257 static int free_iq_fl_hwq(struct adapter *, struct sge_iq *, struct sge_fl *); 258 static int alloc_fwq(struct adapter *); 259 static void free_fwq(struct adapter *); 260 static int alloc_ctrlq(struct adapter *, int); 261 static void free_ctrlq(struct adapter *, int); 262 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, int); 263 static void free_rxq(struct vi_info *, struct sge_rxq *); 264 static void add_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 265 struct sge_rxq *); 266 #ifdef TCP_OFFLOAD 267 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 268 int); 269 static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 270 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 271 struct sge_ofld_rxq *); 272 #endif 273 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 274 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 275 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 276 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 277 #endif 278 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *, 279 struct sysctl_oid *); 280 static void free_eq(struct adapter *, struct sge_eq *); 281 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *, 282 struct sysctl_oid *, struct sge_eq *); 283 static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 284 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 285 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 286 struct sysctl_ctx_list *, struct sysctl_oid *); 287 static void free_wrq(struct adapter *, struct sge_wrq *); 288 static void add_wrq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 289 struct sge_wrq *); 290 static int alloc_txq(struct vi_info *, struct sge_txq *, int); 291 static void free_txq(struct vi_info *, struct sge_txq *); 292 static void add_txq_sysctls(struct vi_info *, struct sysctl_ctx_list *, 293 struct sysctl_oid *, struct sge_txq *); 294 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 295 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int); 296 static void free_ofld_txq(struct vi_info *, struct sge_ofld_txq *); 297 static void add_ofld_txq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 298 struct sge_ofld_txq *); 299 #endif 300 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 301 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 302 static int refill_fl(struct adapter *, struct sge_fl *, int); 303 static void refill_sfl(void *); 304 static int find_refill_source(struct adapter *, int, bool); 305 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 306 307 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 308 static inline u_int txpkt_len16(u_int, const u_int); 309 static inline u_int txpkt_vm_len16(u_int, const u_int); 310 static inline void calculate_mbuf_len16(struct mbuf *, bool); 311 static inline u_int txpkts0_len16(u_int); 312 static inline u_int txpkts1_len16(void); 313 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 314 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *, 315 u_int); 316 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 317 struct mbuf *); 318 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *, 319 int, bool *); 320 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *, 321 int, bool *); 322 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *); 323 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *); 324 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 325 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 326 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 327 static inline uint16_t read_hw_cidx(struct sge_eq *); 328 static inline u_int reclaimable_tx_desc(struct sge_eq *); 329 static inline u_int total_available_tx_desc(struct sge_eq *); 330 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 331 static void tx_reclaim(void *, int); 332 static __be64 get_flit(struct sglist_seg *, int, int); 333 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 334 struct mbuf *); 335 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 336 struct mbuf *); 337 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 338 static void wrq_tx_drain(void *, int); 339 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 340 341 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 342 #ifdef RATELIMIT 343 #if defined(INET) || defined(INET6) 344 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 345 #endif 346 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 347 struct mbuf *); 348 #endif 349 350 static counter_u64_t extfree_refs; 351 static counter_u64_t extfree_rels; 352 353 an_handler_t t4_an_handler; 354 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 355 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 356 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 357 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 358 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 359 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 360 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 361 362 void 363 t4_register_an_handler(an_handler_t h) 364 { 365 uintptr_t *loc; 366 367 MPASS(h == NULL || t4_an_handler == NULL); 368 369 loc = (uintptr_t *)&t4_an_handler; 370 atomic_store_rel_ptr(loc, (uintptr_t)h); 371 } 372 373 void 374 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 375 { 376 uintptr_t *loc; 377 378 MPASS(type < nitems(t4_fw_msg_handler)); 379 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 380 /* 381 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 382 * handler dispatch table. Reject any attempt to install a handler for 383 * this subtype. 384 */ 385 MPASS(type != FW_TYPE_RSSCPL); 386 MPASS(type != FW6_TYPE_RSSCPL); 387 388 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 389 atomic_store_rel_ptr(loc, (uintptr_t)h); 390 } 391 392 void 393 t4_register_cpl_handler(int opcode, cpl_handler_t h) 394 { 395 uintptr_t *loc; 396 397 MPASS(opcode < nitems(t4_cpl_handler)); 398 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 399 400 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 401 atomic_store_rel_ptr(loc, (uintptr_t)h); 402 } 403 404 static int 405 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 406 struct mbuf *m) 407 { 408 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 409 u_int tid; 410 int cookie; 411 412 MPASS(m == NULL); 413 414 tid = GET_TID(cpl); 415 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 416 /* 417 * The return code for filter-write is put in the CPL cookie so 418 * we have to rely on the hardware tid (is_ftid) to determine 419 * that this is a response to a filter. 420 */ 421 cookie = CPL_COOKIE_FILTER; 422 } else { 423 cookie = G_COOKIE(cpl->cookie); 424 } 425 MPASS(cookie > CPL_COOKIE_RESERVED); 426 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 427 428 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 429 } 430 431 static int 432 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 433 struct mbuf *m) 434 { 435 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 436 unsigned int cookie; 437 438 MPASS(m == NULL); 439 440 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 441 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 442 } 443 444 static int 445 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 446 struct mbuf *m) 447 { 448 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 449 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 450 451 MPASS(m == NULL); 452 MPASS(cookie != CPL_COOKIE_RESERVED); 453 454 return (act_open_rpl_handlers[cookie](iq, rss, m)); 455 } 456 457 static int 458 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 459 struct mbuf *m) 460 { 461 struct adapter *sc = iq->adapter; 462 u_int cookie; 463 464 MPASS(m == NULL); 465 if (is_hashfilter(sc)) 466 cookie = CPL_COOKIE_HASHFILTER; 467 else 468 cookie = CPL_COOKIE_TOM; 469 470 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 471 } 472 473 static int 474 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 475 { 476 struct adapter *sc = iq->adapter; 477 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 478 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 479 u_int cookie; 480 481 MPASS(m == NULL); 482 if (is_etid(sc, tid)) 483 cookie = CPL_COOKIE_ETHOFLD; 484 else 485 cookie = CPL_COOKIE_TOM; 486 487 return (fw4_ack_handlers[cookie](iq, rss, m)); 488 } 489 490 static void 491 t4_init_shared_cpl_handlers(void) 492 { 493 494 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 495 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 496 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 497 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 498 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 499 } 500 501 void 502 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 503 { 504 uintptr_t *loc; 505 506 MPASS(opcode < nitems(t4_cpl_handler)); 507 MPASS(cookie > CPL_COOKIE_RESERVED); 508 MPASS(cookie < NUM_CPL_COOKIES); 509 MPASS(t4_cpl_handler[opcode] != NULL); 510 511 switch (opcode) { 512 case CPL_SET_TCB_RPL: 513 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 514 break; 515 case CPL_L2T_WRITE_RPL: 516 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 517 break; 518 case CPL_ACT_OPEN_RPL: 519 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 520 break; 521 case CPL_ABORT_RPL_RSS: 522 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 523 break; 524 case CPL_FW4_ACK: 525 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 526 break; 527 default: 528 MPASS(0); 529 return; 530 } 531 MPASS(h == NULL || *loc == (uintptr_t)NULL); 532 atomic_store_rel_ptr(loc, (uintptr_t)h); 533 } 534 535 /* 536 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 537 */ 538 void 539 t4_sge_modload(void) 540 { 541 542 if (fl_pktshift < 0 || fl_pktshift > 7) { 543 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 544 " using 0 instead.\n", fl_pktshift); 545 fl_pktshift = 0; 546 } 547 548 if (spg_len != 64 && spg_len != 128) { 549 int len; 550 551 #if defined(__i386__) || defined(__amd64__) 552 len = cpu_clflush_line_size > 64 ? 128 : 64; 553 #else 554 len = 64; 555 #endif 556 if (spg_len != -1) { 557 printf("Invalid hw.cxgbe.spg_len value (%d)," 558 " using %d instead.\n", spg_len, len); 559 } 560 spg_len = len; 561 } 562 563 if (cong_drop < -1 || cong_drop > 2) { 564 printf("Invalid hw.cxgbe.cong_drop value (%d)," 565 " using 0 instead.\n", cong_drop); 566 cong_drop = 0; 567 } 568 #ifdef TCP_OFFLOAD 569 if (ofld_cong_drop < -1 || ofld_cong_drop > 2) { 570 printf("Invalid hw.cxgbe.ofld_cong_drop value (%d)," 571 " using 0 instead.\n", ofld_cong_drop); 572 ofld_cong_drop = 0; 573 } 574 #endif 575 576 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 577 printf("Invalid hw.cxgbe.tscale value (%d)," 578 " using 1 instead.\n", tscale); 579 tscale = 1; 580 } 581 582 if (largest_rx_cluster != MCLBYTES && 583 largest_rx_cluster != MJUMPAGESIZE && 584 largest_rx_cluster != MJUM9BYTES && 585 largest_rx_cluster != MJUM16BYTES) { 586 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d)," 587 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES); 588 largest_rx_cluster = MJUM16BYTES; 589 } 590 591 if (safest_rx_cluster != MCLBYTES && 592 safest_rx_cluster != MJUMPAGESIZE && 593 safest_rx_cluster != MJUM9BYTES && 594 safest_rx_cluster != MJUM16BYTES) { 595 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d)," 596 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE); 597 safest_rx_cluster = MJUMPAGESIZE; 598 } 599 600 extfree_refs = counter_u64_alloc(M_WAITOK); 601 extfree_rels = counter_u64_alloc(M_WAITOK); 602 pullups = counter_u64_alloc(M_WAITOK); 603 defrags = counter_u64_alloc(M_WAITOK); 604 counter_u64_zero(extfree_refs); 605 counter_u64_zero(extfree_rels); 606 counter_u64_zero(pullups); 607 counter_u64_zero(defrags); 608 609 t4_init_shared_cpl_handlers(); 610 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 611 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 612 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 613 #ifdef RATELIMIT 614 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 615 CPL_COOKIE_ETHOFLD); 616 #endif 617 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 618 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 619 } 620 621 void 622 t4_sge_modunload(void) 623 { 624 625 counter_u64_free(extfree_refs); 626 counter_u64_free(extfree_rels); 627 counter_u64_free(pullups); 628 counter_u64_free(defrags); 629 } 630 631 uint64_t 632 t4_sge_extfree_refs(void) 633 { 634 uint64_t refs, rels; 635 636 rels = counter_u64_fetch(extfree_rels); 637 refs = counter_u64_fetch(extfree_refs); 638 639 return (refs - rels); 640 } 641 642 /* max 4096 */ 643 #define MAX_PACK_BOUNDARY 512 644 645 static inline void 646 setup_pad_and_pack_boundaries(struct adapter *sc) 647 { 648 uint32_t v, m; 649 int pad, pack, pad_shift; 650 651 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 652 X_INGPADBOUNDARY_SHIFT; 653 pad = fl_pad; 654 if (fl_pad < (1 << pad_shift) || 655 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 656 !powerof2(fl_pad)) { 657 /* 658 * If there is any chance that we might use buffer packing and 659 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 660 * it to the minimum allowed in all other cases. 661 */ 662 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 663 664 /* 665 * For fl_pad = 0 we'll still write a reasonable value to the 666 * register but all the freelists will opt out of padding. 667 * We'll complain here only if the user tried to set it to a 668 * value greater than 0 that was invalid. 669 */ 670 if (fl_pad > 0) { 671 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 672 " (%d), using %d instead.\n", fl_pad, pad); 673 } 674 } 675 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 676 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 677 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 678 679 if (is_t4(sc)) { 680 if (fl_pack != -1 && fl_pack != pad) { 681 /* Complain but carry on. */ 682 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 683 " using %d instead.\n", fl_pack, pad); 684 } 685 return; 686 } 687 688 pack = fl_pack; 689 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 690 !powerof2(fl_pack)) { 691 if (sc->params.pci.mps > MAX_PACK_BOUNDARY) 692 pack = MAX_PACK_BOUNDARY; 693 else 694 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 695 MPASS(powerof2(pack)); 696 if (pack < 16) 697 pack = 16; 698 if (pack == 32) 699 pack = 64; 700 if (pack > 4096) 701 pack = 4096; 702 if (fl_pack != -1) { 703 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 704 " (%d), using %d instead.\n", fl_pack, pack); 705 } 706 } 707 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 708 if (pack == 16) 709 v = V_INGPACKBOUNDARY(0); 710 else 711 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 712 713 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 714 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 715 } 716 717 /* 718 * adap->params.vpd.cclk must be set up before this is called. 719 */ 720 void 721 t4_tweak_chip_settings(struct adapter *sc) 722 { 723 int i, reg; 724 uint32_t v, m; 725 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 726 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 727 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 728 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 729 static int sw_buf_sizes[] = { 730 MCLBYTES, 731 MJUMPAGESIZE, 732 MJUM9BYTES, 733 MJUM16BYTES 734 }; 735 736 KASSERT(sc->flags & MASTER_PF, 737 ("%s: trying to change chip settings when not master.", __func__)); 738 739 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 740 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 741 V_EGRSTATUSPAGESIZE(spg_len == 128); 742 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 743 744 setup_pad_and_pack_boundaries(sc); 745 746 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 747 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 748 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 749 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 750 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 751 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 752 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 753 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 754 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 755 756 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 757 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 758 reg = A_SGE_FL_BUFFER_SIZE2; 759 for (i = 0; i < nitems(sw_buf_sizes); i++) { 760 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 761 t4_write_reg(sc, reg, sw_buf_sizes[i]); 762 reg += 4; 763 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 764 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE); 765 reg += 4; 766 } 767 768 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 769 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 770 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 771 772 KASSERT(intr_timer[0] <= timer_max, 773 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 774 timer_max)); 775 for (i = 1; i < nitems(intr_timer); i++) { 776 KASSERT(intr_timer[i] >= intr_timer[i - 1], 777 ("%s: timers not listed in increasing order (%d)", 778 __func__, i)); 779 780 while (intr_timer[i] > timer_max) { 781 if (i == nitems(intr_timer) - 1) { 782 intr_timer[i] = timer_max; 783 break; 784 } 785 intr_timer[i] += intr_timer[i - 1]; 786 intr_timer[i] /= 2; 787 } 788 } 789 790 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 791 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 792 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 793 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 794 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 795 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 796 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 797 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 798 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 799 800 if (chip_id(sc) >= CHELSIO_T6) { 801 m = V_TSCALE(M_TSCALE); 802 if (tscale == 1) 803 v = 0; 804 else 805 v = V_TSCALE(tscale - 2); 806 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 807 808 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 809 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 810 V_WRTHRTHRESH(M_WRTHRTHRESH); 811 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 812 v &= ~m; 813 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 814 V_WRTHRTHRESH(16); 815 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 816 } 817 } 818 819 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 820 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 821 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 822 823 /* 824 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 825 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 826 * may have to deal with is MAXPHYS + 1 page. 827 */ 828 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 829 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 830 831 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 832 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 833 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 834 835 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 836 F_RESETDDPOFFSET; 837 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 838 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 839 } 840 841 /* 842 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its 843 * address mut be 16B aligned. If padding is in use the buffer's start and end 844 * need to be aligned to the pad boundary as well. We'll just make sure that 845 * the size is a multiple of the pad boundary here, it is up to the buffer 846 * allocation code to make sure the start of the buffer is aligned. 847 */ 848 static inline int 849 hwsz_ok(struct adapter *sc, int hwsz) 850 { 851 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 852 853 return (hwsz >= 64 && (hwsz & mask) == 0); 854 } 855 856 /* 857 * Initialize the rx buffer sizes and figure out which zones the buffers will 858 * be allocated from. 859 */ 860 void 861 t4_init_rx_buf_info(struct adapter *sc) 862 { 863 struct sge *s = &sc->sge; 864 struct sge_params *sp = &sc->params.sge; 865 int i, j, n; 866 static int sw_buf_sizes[] = { /* Sorted by size */ 867 MCLBYTES, 868 MJUMPAGESIZE, 869 MJUM9BYTES, 870 MJUM16BYTES 871 }; 872 struct rx_buf_info *rxb; 873 874 s->safe_zidx = -1; 875 rxb = &s->rx_buf_info[0]; 876 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 877 rxb->size1 = sw_buf_sizes[i]; 878 rxb->zone = m_getzone(rxb->size1); 879 rxb->type = m_gettype(rxb->size1); 880 rxb->size2 = 0; 881 rxb->hwidx1 = -1; 882 rxb->hwidx2 = -1; 883 for (j = 0; j < SGE_FLBUF_SIZES; j++) { 884 int hwsize = sp->sge_fl_buffer_size[j]; 885 886 if (!hwsz_ok(sc, hwsize)) 887 continue; 888 889 /* hwidx for size1 */ 890 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize) 891 rxb->hwidx1 = j; 892 893 /* hwidx for size2 (buffer packing) */ 894 if (rxb->size1 - CL_METADATA_SIZE < hwsize) 895 continue; 896 n = rxb->size1 - hwsize - CL_METADATA_SIZE; 897 if (n == 0) { 898 rxb->hwidx2 = j; 899 rxb->size2 = hwsize; 900 break; /* stop looking */ 901 } 902 if (rxb->hwidx2 != -1) { 903 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] - 904 hwsize - CL_METADATA_SIZE) { 905 rxb->hwidx2 = j; 906 rxb->size2 = hwsize; 907 } 908 } else if (n <= 2 * CL_METADATA_SIZE) { 909 rxb->hwidx2 = j; 910 rxb->size2 = hwsize; 911 } 912 } 913 if (rxb->hwidx2 != -1) 914 sc->flags |= BUF_PACKING_OK; 915 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster) 916 s->safe_zidx = i; 917 } 918 } 919 920 /* 921 * Verify some basic SGE settings for the PF and VF driver, and other 922 * miscellaneous settings for the PF driver. 923 */ 924 int 925 t4_verify_chip_settings(struct adapter *sc) 926 { 927 struct sge_params *sp = &sc->params.sge; 928 uint32_t m, v, r; 929 int rc = 0; 930 const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 931 932 m = F_RXPKTCPLMODE; 933 v = F_RXPKTCPLMODE; 934 r = sp->sge_control; 935 if ((r & m) != v) { 936 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 937 rc = EINVAL; 938 } 939 940 /* 941 * If this changes then every single use of PAGE_SHIFT in the driver 942 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 943 */ 944 if (sp->page_shift != PAGE_SHIFT) { 945 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 946 rc = EINVAL; 947 } 948 949 if (sc->flags & IS_VF) 950 return (0); 951 952 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 953 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 954 if (r != v) { 955 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 956 if (sc->vres.ddp.size != 0) 957 rc = EINVAL; 958 } 959 960 m = v = F_TDDPTAGTCB; 961 r = t4_read_reg(sc, A_ULP_RX_CTL); 962 if ((r & m) != v) { 963 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 964 if (sc->vres.ddp.size != 0) 965 rc = EINVAL; 966 } 967 968 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 969 F_RESETDDPOFFSET; 970 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 971 r = t4_read_reg(sc, A_TP_PARA_REG5); 972 if ((r & m) != v) { 973 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 974 if (sc->vres.ddp.size != 0) 975 rc = EINVAL; 976 } 977 978 return (rc); 979 } 980 981 int 982 t4_create_dma_tag(struct adapter *sc) 983 { 984 int rc; 985 986 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 987 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 988 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 989 NULL, &sc->dmat); 990 if (rc != 0) { 991 device_printf(sc->dev, 992 "failed to create main DMA tag: %d\n", rc); 993 } 994 995 return (rc); 996 } 997 998 void 999 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 1000 struct sysctl_oid_list *children) 1001 { 1002 struct sge_params *sp = &sc->params.sge; 1003 1004 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 1005 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 1006 sysctl_bufsizes, "A", "freelist buffer sizes"); 1007 1008 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 1009 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 1010 1011 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 1012 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 1013 1014 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 1015 NULL, sp->spg_len, "status page size (bytes)"); 1016 1017 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1018 NULL, cong_drop, "congestion drop setting"); 1019 #ifdef TCP_OFFLOAD 1020 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ofld_cong_drop", CTLFLAG_RD, 1021 NULL, ofld_cong_drop, "congestion drop setting"); 1022 #endif 1023 1024 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1025 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1026 } 1027 1028 int 1029 t4_destroy_dma_tag(struct adapter *sc) 1030 { 1031 if (sc->dmat) 1032 bus_dma_tag_destroy(sc->dmat); 1033 1034 return (0); 1035 } 1036 1037 /* 1038 * Allocate and initialize the firmware event queue, control queues, and special 1039 * purpose rx queues owned by the adapter. 1040 * 1041 * Returns errno on failure. Resources allocated up to that point may still be 1042 * allocated. Caller is responsible for cleanup in case this function fails. 1043 */ 1044 int 1045 t4_setup_adapter_queues(struct adapter *sc) 1046 { 1047 int rc, i; 1048 1049 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1050 1051 /* 1052 * Firmware event queue 1053 */ 1054 rc = alloc_fwq(sc); 1055 if (rc != 0) 1056 return (rc); 1057 1058 /* 1059 * That's all for the VF driver. 1060 */ 1061 if (sc->flags & IS_VF) 1062 return (rc); 1063 1064 /* 1065 * XXX: General purpose rx queues, one per port. 1066 */ 1067 1068 /* 1069 * Control queues, one per port. 1070 */ 1071 for_each_port(sc, i) { 1072 rc = alloc_ctrlq(sc, i); 1073 if (rc != 0) 1074 return (rc); 1075 } 1076 1077 return (rc); 1078 } 1079 1080 /* 1081 * Idempotent 1082 */ 1083 int 1084 t4_teardown_adapter_queues(struct adapter *sc) 1085 { 1086 int i; 1087 1088 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1089 1090 if (sc->sge.ctrlq != NULL) { 1091 MPASS(!(sc->flags & IS_VF)); /* VFs don't allocate ctrlq. */ 1092 for_each_port(sc, i) 1093 free_ctrlq(sc, i); 1094 } 1095 free_fwq(sc); 1096 1097 return (0); 1098 } 1099 1100 /* Maximum payload that could arrive with a single iq descriptor. */ 1101 static inline int 1102 max_rx_payload(struct adapter *sc, struct ifnet *ifp, const bool ofld) 1103 { 1104 int maxp; 1105 1106 /* large enough even when hw VLAN extraction is disabled */ 1107 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1108 ETHER_VLAN_ENCAP_LEN + ifp->if_mtu; 1109 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 1110 maxp < sc->params.tp.max_rx_pdu) 1111 maxp = sc->params.tp.max_rx_pdu; 1112 return (maxp); 1113 } 1114 1115 int 1116 t4_setup_vi_queues(struct vi_info *vi) 1117 { 1118 int rc = 0, i, intr_idx; 1119 struct sge_rxq *rxq; 1120 struct sge_txq *txq; 1121 #ifdef TCP_OFFLOAD 1122 struct sge_ofld_rxq *ofld_rxq; 1123 #endif 1124 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1125 struct sge_ofld_txq *ofld_txq; 1126 #endif 1127 #ifdef DEV_NETMAP 1128 int saved_idx, iqidx; 1129 struct sge_nm_rxq *nm_rxq; 1130 struct sge_nm_txq *nm_txq; 1131 #endif 1132 struct adapter *sc = vi->adapter; 1133 struct ifnet *ifp = vi->ifp; 1134 int maxp; 1135 1136 /* Interrupt vector to start from (when using multiple vectors) */ 1137 intr_idx = vi->first_intr; 1138 1139 #ifdef DEV_NETMAP 1140 saved_idx = intr_idx; 1141 if (ifp->if_capabilities & IFCAP_NETMAP) { 1142 1143 /* netmap is supported with direct interrupts only. */ 1144 MPASS(!forwarding_intr_to_fwq(sc)); 1145 MPASS(vi->first_intr >= 0); 1146 1147 /* 1148 * We don't have buffers to back the netmap rx queues 1149 * right now so we create the queues in a way that 1150 * doesn't set off any congestion signal in the chip. 1151 */ 1152 for_each_nm_rxq(vi, i, nm_rxq) { 1153 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i); 1154 if (rc != 0) 1155 goto done; 1156 intr_idx++; 1157 } 1158 1159 for_each_nm_txq(vi, i, nm_txq) { 1160 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1161 rc = alloc_nm_txq(vi, nm_txq, iqidx, i); 1162 if (rc != 0) 1163 goto done; 1164 } 1165 } 1166 1167 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1168 intr_idx = saved_idx; 1169 #endif 1170 1171 /* 1172 * Allocate rx queues first because a default iqid is required when 1173 * creating a tx queue. 1174 */ 1175 maxp = max_rx_payload(sc, ifp, false); 1176 for_each_rxq(vi, i, rxq) { 1177 rc = alloc_rxq(vi, rxq, i, intr_idx, maxp); 1178 if (rc != 0) 1179 goto done; 1180 if (!forwarding_intr_to_fwq(sc)) 1181 intr_idx++; 1182 } 1183 #ifdef DEV_NETMAP 1184 if (ifp->if_capabilities & IFCAP_NETMAP) 1185 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1186 #endif 1187 #ifdef TCP_OFFLOAD 1188 maxp = max_rx_payload(sc, ifp, true); 1189 for_each_ofld_rxq(vi, i, ofld_rxq) { 1190 rc = alloc_ofld_rxq(vi, ofld_rxq, i, intr_idx, maxp); 1191 if (rc != 0) 1192 goto done; 1193 if (!forwarding_intr_to_fwq(sc)) 1194 intr_idx++; 1195 } 1196 #endif 1197 1198 /* 1199 * Now the tx queues. 1200 */ 1201 for_each_txq(vi, i, txq) { 1202 rc = alloc_txq(vi, txq, i); 1203 if (rc != 0) 1204 goto done; 1205 } 1206 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1207 for_each_ofld_txq(vi, i, ofld_txq) { 1208 rc = alloc_ofld_txq(vi, ofld_txq, i); 1209 if (rc != 0) 1210 goto done; 1211 } 1212 #endif 1213 done: 1214 if (rc) 1215 t4_teardown_vi_queues(vi); 1216 1217 return (rc); 1218 } 1219 1220 /* 1221 * Idempotent 1222 */ 1223 int 1224 t4_teardown_vi_queues(struct vi_info *vi) 1225 { 1226 int i; 1227 struct sge_rxq *rxq; 1228 struct sge_txq *txq; 1229 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1230 struct sge_ofld_txq *ofld_txq; 1231 #endif 1232 #ifdef TCP_OFFLOAD 1233 struct sge_ofld_rxq *ofld_rxq; 1234 #endif 1235 #ifdef DEV_NETMAP 1236 struct sge_nm_rxq *nm_rxq; 1237 struct sge_nm_txq *nm_txq; 1238 #endif 1239 1240 #ifdef DEV_NETMAP 1241 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1242 for_each_nm_txq(vi, i, nm_txq) { 1243 free_nm_txq(vi, nm_txq); 1244 } 1245 1246 for_each_nm_rxq(vi, i, nm_rxq) { 1247 free_nm_rxq(vi, nm_rxq); 1248 } 1249 } 1250 #endif 1251 1252 /* 1253 * Take down all the tx queues first, as they reference the rx queues 1254 * (for egress updates, etc.). 1255 */ 1256 1257 for_each_txq(vi, i, txq) { 1258 free_txq(vi, txq); 1259 } 1260 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1261 for_each_ofld_txq(vi, i, ofld_txq) { 1262 free_ofld_txq(vi, ofld_txq); 1263 } 1264 #endif 1265 1266 /* 1267 * Then take down the rx queues. 1268 */ 1269 1270 for_each_rxq(vi, i, rxq) { 1271 free_rxq(vi, rxq); 1272 } 1273 #ifdef TCP_OFFLOAD 1274 for_each_ofld_rxq(vi, i, ofld_rxq) { 1275 free_ofld_rxq(vi, ofld_rxq); 1276 } 1277 #endif 1278 1279 return (0); 1280 } 1281 1282 /* 1283 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1284 * unusual scenario. 1285 * 1286 * a) Deals with errors, if any. 1287 * b) Services firmware event queue, which is taking interrupts for all other 1288 * queues. 1289 */ 1290 void 1291 t4_intr_all(void *arg) 1292 { 1293 struct adapter *sc = arg; 1294 struct sge_iq *fwq = &sc->sge.fwq; 1295 1296 MPASS(sc->intr_count == 1); 1297 1298 if (sc->intr_type == INTR_INTX) 1299 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1300 1301 t4_intr_err(arg); 1302 t4_intr_evt(fwq); 1303 } 1304 1305 /* 1306 * Interrupt handler for errors (installed directly when multiple interrupts are 1307 * being used, or called by t4_intr_all). 1308 */ 1309 void 1310 t4_intr_err(void *arg) 1311 { 1312 struct adapter *sc = arg; 1313 uint32_t v; 1314 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 1315 1316 if (atomic_load_int(&sc->error_flags) & ADAP_FATAL_ERR) 1317 return; 1318 1319 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1320 if (v & F_PFSW) { 1321 sc->swintr++; 1322 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1323 } 1324 1325 if (t4_slow_intr_handler(sc, verbose)) 1326 t4_fatal_err(sc, false); 1327 } 1328 1329 /* 1330 * Interrupt handler for iq-only queues. The firmware event queue is the only 1331 * such queue right now. 1332 */ 1333 void 1334 t4_intr_evt(void *arg) 1335 { 1336 struct sge_iq *iq = arg; 1337 1338 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1339 service_iq(iq, 0); 1340 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1341 } 1342 } 1343 1344 /* 1345 * Interrupt handler for iq+fl queues. 1346 */ 1347 void 1348 t4_intr(void *arg) 1349 { 1350 struct sge_iq *iq = arg; 1351 1352 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1353 service_iq_fl(iq, 0); 1354 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1355 } 1356 } 1357 1358 #ifdef DEV_NETMAP 1359 /* 1360 * Interrupt handler for netmap rx queues. 1361 */ 1362 void 1363 t4_nm_intr(void *arg) 1364 { 1365 struct sge_nm_rxq *nm_rxq = arg; 1366 1367 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1368 service_nm_rxq(nm_rxq); 1369 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1370 } 1371 } 1372 1373 /* 1374 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1375 */ 1376 void 1377 t4_vi_intr(void *arg) 1378 { 1379 struct irq *irq = arg; 1380 1381 MPASS(irq->nm_rxq != NULL); 1382 t4_nm_intr(irq->nm_rxq); 1383 1384 MPASS(irq->rxq != NULL); 1385 t4_intr(irq->rxq); 1386 } 1387 #endif 1388 1389 /* 1390 * Deals with interrupts on an iq-only (no freelist) queue. 1391 */ 1392 static int 1393 service_iq(struct sge_iq *iq, int budget) 1394 { 1395 struct sge_iq *q; 1396 struct adapter *sc = iq->adapter; 1397 struct iq_desc *d = &iq->desc[iq->cidx]; 1398 int ndescs = 0, limit; 1399 int rsp_type; 1400 uint32_t lq; 1401 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1402 1403 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1404 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1405 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1406 iq->flags)); 1407 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1408 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1409 1410 limit = budget ? budget : iq->qsize / 16; 1411 1412 /* 1413 * We always come back and check the descriptor ring for new indirect 1414 * interrupts and other responses after running a single handler. 1415 */ 1416 for (;;) { 1417 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1418 1419 rmb(); 1420 1421 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1422 lq = be32toh(d->rsp.pldbuflen_qid); 1423 1424 switch (rsp_type) { 1425 case X_RSPD_TYPE_FLBUF: 1426 panic("%s: data for an iq (%p) with no freelist", 1427 __func__, iq); 1428 1429 /* NOTREACHED */ 1430 1431 case X_RSPD_TYPE_CPL: 1432 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1433 ("%s: bad opcode %02x.", __func__, 1434 d->rss.opcode)); 1435 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1436 break; 1437 1438 case X_RSPD_TYPE_INTR: 1439 /* 1440 * There are 1K interrupt-capable queues (qids 0 1441 * through 1023). A response type indicating a 1442 * forwarded interrupt with a qid >= 1K is an 1443 * iWARP async notification. 1444 */ 1445 if (__predict_true(lq >= 1024)) { 1446 t4_an_handler(iq, &d->rsp); 1447 break; 1448 } 1449 1450 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1451 sc->sge.iq_base]; 1452 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1453 IQS_BUSY)) { 1454 if (service_iq_fl(q, q->qsize / 16) == 0) { 1455 (void) atomic_cmpset_int(&q->state, 1456 IQS_BUSY, IQS_IDLE); 1457 } else { 1458 STAILQ_INSERT_TAIL(&iql, q, 1459 link); 1460 } 1461 } 1462 break; 1463 1464 default: 1465 KASSERT(0, 1466 ("%s: illegal response type %d on iq %p", 1467 __func__, rsp_type, iq)); 1468 log(LOG_ERR, 1469 "%s: illegal response type %d on iq %p", 1470 device_get_nameunit(sc->dev), rsp_type, iq); 1471 break; 1472 } 1473 1474 d++; 1475 if (__predict_false(++iq->cidx == iq->sidx)) { 1476 iq->cidx = 0; 1477 iq->gen ^= F_RSPD_GEN; 1478 d = &iq->desc[0]; 1479 } 1480 if (__predict_false(++ndescs == limit)) { 1481 t4_write_reg(sc, sc->sge_gts_reg, 1482 V_CIDXINC(ndescs) | 1483 V_INGRESSQID(iq->cntxt_id) | 1484 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1485 ndescs = 0; 1486 1487 if (budget) { 1488 return (EINPROGRESS); 1489 } 1490 } 1491 } 1492 1493 if (STAILQ_EMPTY(&iql)) 1494 break; 1495 1496 /* 1497 * Process the head only, and send it to the back of the list if 1498 * it's still not done. 1499 */ 1500 q = STAILQ_FIRST(&iql); 1501 STAILQ_REMOVE_HEAD(&iql, link); 1502 if (service_iq_fl(q, q->qsize / 8) == 0) 1503 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1504 else 1505 STAILQ_INSERT_TAIL(&iql, q, link); 1506 } 1507 1508 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1509 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1510 1511 return (0); 1512 } 1513 1514 #if defined(INET) || defined(INET6) 1515 static inline int 1516 sort_before_lro(struct lro_ctrl *lro) 1517 { 1518 1519 return (lro->lro_mbuf_max != 0); 1520 } 1521 #endif 1522 1523 #define CGBE_SHIFT_SCALE 10 1524 1525 static inline uint64_t 1526 t4_tstmp_to_ns(struct adapter *sc, uint64_t lf) 1527 { 1528 struct clock_sync *cur, dcur; 1529 uint64_t hw_clocks; 1530 uint64_t hw_clk_div; 1531 sbintime_t sbt_cur_to_prev, sbt; 1532 uint64_t hw_tstmp = lf & 0xfffffffffffffffULL; /* 60b, not 64b. */ 1533 seqc_t gen; 1534 1535 for (;;) { 1536 cur = &sc->cal_info[sc->cal_current]; 1537 gen = seqc_read(&cur->gen); 1538 if (gen == 0) 1539 return (0); 1540 dcur = *cur; 1541 if (seqc_consistent(&cur->gen, gen)) 1542 break; 1543 } 1544 1545 /* 1546 * Our goal here is to have a result that is: 1547 * 1548 * ( (cur_time - prev_time) ) 1549 * ((hw_tstmp - hw_prev) * ----------------------------- ) + prev_time 1550 * ( (hw_cur - hw_prev) ) 1551 * 1552 * With the constraints that we cannot use float and we 1553 * don't want to overflow the uint64_t numbers we are using. 1554 */ 1555 hw_clocks = hw_tstmp - dcur.hw_prev; 1556 sbt_cur_to_prev = (dcur.sbt_cur - dcur.sbt_prev); 1557 hw_clk_div = dcur.hw_cur - dcur.hw_prev; 1558 sbt = hw_clocks * sbt_cur_to_prev / hw_clk_div + dcur.sbt_prev; 1559 return (sbttons(sbt)); 1560 } 1561 1562 static inline void 1563 move_to_next_rxbuf(struct sge_fl *fl) 1564 { 1565 1566 fl->rx_offset = 0; 1567 if (__predict_false((++fl->cidx & 7) == 0)) { 1568 uint16_t cidx = fl->cidx >> 3; 1569 1570 if (__predict_false(cidx == fl->sidx)) 1571 fl->cidx = cidx = 0; 1572 fl->hw_cidx = cidx; 1573 } 1574 } 1575 1576 /* 1577 * Deals with interrupts on an iq+fl queue. 1578 */ 1579 static int 1580 service_iq_fl(struct sge_iq *iq, int budget) 1581 { 1582 struct sge_rxq *rxq = iq_to_rxq(iq); 1583 struct sge_fl *fl; 1584 struct adapter *sc = iq->adapter; 1585 struct iq_desc *d = &iq->desc[iq->cidx]; 1586 int ndescs, limit; 1587 int rsp_type, starved; 1588 uint32_t lq; 1589 uint16_t fl_hw_cidx; 1590 struct mbuf *m0; 1591 #if defined(INET) || defined(INET6) 1592 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1593 struct lro_ctrl *lro = &rxq->lro; 1594 #endif 1595 1596 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1597 MPASS(iq->flags & IQ_HAS_FL); 1598 1599 ndescs = 0; 1600 #if defined(INET) || defined(INET6) 1601 if (iq->flags & IQ_ADJ_CREDIT) { 1602 MPASS(sort_before_lro(lro)); 1603 iq->flags &= ~IQ_ADJ_CREDIT; 1604 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1605 tcp_lro_flush_all(lro); 1606 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1607 V_INGRESSQID((u32)iq->cntxt_id) | 1608 V_SEINTARM(iq->intr_params)); 1609 return (0); 1610 } 1611 ndescs = 1; 1612 } 1613 #else 1614 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1615 #endif 1616 1617 limit = budget ? budget : iq->qsize / 16; 1618 fl = &rxq->fl; 1619 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1620 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1621 1622 rmb(); 1623 1624 m0 = NULL; 1625 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1626 lq = be32toh(d->rsp.pldbuflen_qid); 1627 1628 switch (rsp_type) { 1629 case X_RSPD_TYPE_FLBUF: 1630 if (lq & F_RSPD_NEWBUF) { 1631 if (fl->rx_offset > 0) 1632 move_to_next_rxbuf(fl); 1633 lq = G_RSPD_LEN(lq); 1634 } 1635 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) { 1636 FL_LOCK(fl); 1637 refill_fl(sc, fl, 64); 1638 FL_UNLOCK(fl); 1639 fl_hw_cidx = fl->hw_cidx; 1640 } 1641 1642 if (d->rss.opcode == CPL_RX_PKT) { 1643 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0)) 1644 break; 1645 goto out; 1646 } 1647 m0 = get_fl_payload(sc, fl, lq); 1648 if (__predict_false(m0 == NULL)) 1649 goto out; 1650 1651 /* fall through */ 1652 1653 case X_RSPD_TYPE_CPL: 1654 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1655 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1656 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1657 break; 1658 1659 case X_RSPD_TYPE_INTR: 1660 1661 /* 1662 * There are 1K interrupt-capable queues (qids 0 1663 * through 1023). A response type indicating a 1664 * forwarded interrupt with a qid >= 1K is an 1665 * iWARP async notification. That is the only 1666 * acceptable indirect interrupt on this queue. 1667 */ 1668 if (__predict_false(lq < 1024)) { 1669 panic("%s: indirect interrupt on iq_fl %p " 1670 "with qid %u", __func__, iq, lq); 1671 } 1672 1673 t4_an_handler(iq, &d->rsp); 1674 break; 1675 1676 default: 1677 KASSERT(0, ("%s: illegal response type %d on iq %p", 1678 __func__, rsp_type, iq)); 1679 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1680 device_get_nameunit(sc->dev), rsp_type, iq); 1681 break; 1682 } 1683 1684 d++; 1685 if (__predict_false(++iq->cidx == iq->sidx)) { 1686 iq->cidx = 0; 1687 iq->gen ^= F_RSPD_GEN; 1688 d = &iq->desc[0]; 1689 } 1690 if (__predict_false(++ndescs == limit)) { 1691 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1692 V_INGRESSQID(iq->cntxt_id) | 1693 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1694 1695 #if defined(INET) || defined(INET6) 1696 if (iq->flags & IQ_LRO_ENABLED && 1697 !sort_before_lro(lro) && 1698 sc->lro_timeout != 0) { 1699 tcp_lro_flush_inactive(lro, &lro_timeout); 1700 } 1701 #endif 1702 if (budget) 1703 return (EINPROGRESS); 1704 ndescs = 0; 1705 } 1706 } 1707 out: 1708 #if defined(INET) || defined(INET6) 1709 if (iq->flags & IQ_LRO_ENABLED) { 1710 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1711 MPASS(sort_before_lro(lro)); 1712 /* hold back one credit and don't flush LRO state */ 1713 iq->flags |= IQ_ADJ_CREDIT; 1714 ndescs--; 1715 } else { 1716 tcp_lro_flush_all(lro); 1717 } 1718 } 1719 #endif 1720 1721 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1722 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1723 1724 FL_LOCK(fl); 1725 starved = refill_fl(sc, fl, 64); 1726 FL_UNLOCK(fl); 1727 if (__predict_false(starved != 0)) 1728 add_fl_to_sfl(sc, fl); 1729 1730 return (0); 1731 } 1732 1733 static inline struct cluster_metadata * 1734 cl_metadata(struct fl_sdesc *sd) 1735 { 1736 1737 return ((void *)(sd->cl + sd->moff)); 1738 } 1739 1740 static void 1741 rxb_free(struct mbuf *m) 1742 { 1743 struct cluster_metadata *clm = m->m_ext.ext_arg1; 1744 1745 uma_zfree(clm->zone, clm->cl); 1746 counter_u64_add(extfree_rels, 1); 1747 } 1748 1749 /* 1750 * The mbuf returned comes from zone_muf and carries the payload in one of these 1751 * ways 1752 * a) complete frame inside the mbuf 1753 * b) m_cljset (for clusters without metadata) 1754 * d) m_extaddref (cluster with metadata) 1755 */ 1756 static struct mbuf * 1757 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1758 int remaining) 1759 { 1760 struct mbuf *m; 1761 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1762 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1763 struct cluster_metadata *clm; 1764 int len, blen; 1765 caddr_t payload; 1766 1767 if (fl->flags & FL_BUF_PACKING) { 1768 u_int l, pad; 1769 1770 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1771 len = min(remaining, blen); 1772 payload = sd->cl + fl->rx_offset; 1773 1774 l = fr_offset + len; 1775 pad = roundup2(l, fl->buf_boundary) - l; 1776 if (fl->rx_offset + len + pad < rxb->size2) 1777 blen = len + pad; 1778 MPASS(fl->rx_offset + blen <= rxb->size2); 1779 } else { 1780 MPASS(fl->rx_offset == 0); /* not packing */ 1781 blen = rxb->size1; 1782 len = min(remaining, blen); 1783 payload = sd->cl; 1784 } 1785 1786 if (fr_offset == 0) { 1787 m = m_gethdr(M_NOWAIT, MT_DATA); 1788 if (__predict_false(m == NULL)) 1789 return (NULL); 1790 m->m_pkthdr.len = remaining; 1791 } else { 1792 m = m_get(M_NOWAIT, MT_DATA); 1793 if (__predict_false(m == NULL)) 1794 return (NULL); 1795 } 1796 m->m_len = len; 1797 kmsan_mark(payload, len, KMSAN_STATE_INITED); 1798 1799 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1800 /* copy data to mbuf */ 1801 bcopy(payload, mtod(m, caddr_t), len); 1802 if (fl->flags & FL_BUF_PACKING) { 1803 fl->rx_offset += blen; 1804 MPASS(fl->rx_offset <= rxb->size2); 1805 if (fl->rx_offset < rxb->size2) 1806 return (m); /* without advancing the cidx */ 1807 } 1808 } else if (fl->flags & FL_BUF_PACKING) { 1809 clm = cl_metadata(sd); 1810 if (sd->nmbuf++ == 0) { 1811 clm->refcount = 1; 1812 clm->zone = rxb->zone; 1813 clm->cl = sd->cl; 1814 counter_u64_add(extfree_refs, 1); 1815 } 1816 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm, 1817 NULL); 1818 1819 fl->rx_offset += blen; 1820 MPASS(fl->rx_offset <= rxb->size2); 1821 if (fl->rx_offset < rxb->size2) 1822 return (m); /* without advancing the cidx */ 1823 } else { 1824 m_cljset(m, sd->cl, rxb->type); 1825 sd->cl = NULL; /* consumed, not a recycle candidate */ 1826 } 1827 1828 move_to_next_rxbuf(fl); 1829 1830 return (m); 1831 } 1832 1833 static struct mbuf * 1834 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen) 1835 { 1836 struct mbuf *m0, *m, **pnext; 1837 u_int remaining; 1838 1839 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1840 M_ASSERTPKTHDR(fl->m0); 1841 MPASS(fl->m0->m_pkthdr.len == plen); 1842 MPASS(fl->remaining < plen); 1843 1844 m0 = fl->m0; 1845 pnext = fl->pnext; 1846 remaining = fl->remaining; 1847 fl->flags &= ~FL_BUF_RESUME; 1848 goto get_segment; 1849 } 1850 1851 /* 1852 * Payload starts at rx_offset in the current hw buffer. Its length is 1853 * 'len' and it may span multiple hw buffers. 1854 */ 1855 1856 m0 = get_scatter_segment(sc, fl, 0, plen); 1857 if (m0 == NULL) 1858 return (NULL); 1859 remaining = plen - m0->m_len; 1860 pnext = &m0->m_next; 1861 while (remaining > 0) { 1862 get_segment: 1863 MPASS(fl->rx_offset == 0); 1864 m = get_scatter_segment(sc, fl, plen - remaining, remaining); 1865 if (__predict_false(m == NULL)) { 1866 fl->m0 = m0; 1867 fl->pnext = pnext; 1868 fl->remaining = remaining; 1869 fl->flags |= FL_BUF_RESUME; 1870 return (NULL); 1871 } 1872 *pnext = m; 1873 pnext = &m->m_next; 1874 remaining -= m->m_len; 1875 } 1876 *pnext = NULL; 1877 1878 M_ASSERTPKTHDR(m0); 1879 return (m0); 1880 } 1881 1882 static int 1883 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1884 int remaining) 1885 { 1886 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1887 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1888 int len, blen; 1889 1890 if (fl->flags & FL_BUF_PACKING) { 1891 u_int l, pad; 1892 1893 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1894 len = min(remaining, blen); 1895 1896 l = fr_offset + len; 1897 pad = roundup2(l, fl->buf_boundary) - l; 1898 if (fl->rx_offset + len + pad < rxb->size2) 1899 blen = len + pad; 1900 fl->rx_offset += blen; 1901 MPASS(fl->rx_offset <= rxb->size2); 1902 if (fl->rx_offset < rxb->size2) 1903 return (len); /* without advancing the cidx */ 1904 } else { 1905 MPASS(fl->rx_offset == 0); /* not packing */ 1906 blen = rxb->size1; 1907 len = min(remaining, blen); 1908 } 1909 move_to_next_rxbuf(fl); 1910 return (len); 1911 } 1912 1913 static inline void 1914 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen) 1915 { 1916 int remaining, fr_offset, len; 1917 1918 fr_offset = 0; 1919 remaining = plen; 1920 while (remaining > 0) { 1921 len = skip_scatter_segment(sc, fl, fr_offset, remaining); 1922 fr_offset += len; 1923 remaining -= len; 1924 } 1925 } 1926 1927 static inline int 1928 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen) 1929 { 1930 int len; 1931 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1932 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1933 1934 if (fl->flags & FL_BUF_PACKING) 1935 len = rxb->size2 - fl->rx_offset; 1936 else 1937 len = rxb->size1; 1938 1939 return (min(plen, len)); 1940 } 1941 1942 static int 1943 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d, 1944 u_int plen) 1945 { 1946 struct mbuf *m0; 1947 struct ifnet *ifp = rxq->ifp; 1948 struct sge_fl *fl = &rxq->fl; 1949 struct vi_info *vi = ifp->if_softc; 1950 const struct cpl_rx_pkt *cpl; 1951 #if defined(INET) || defined(INET6) 1952 struct lro_ctrl *lro = &rxq->lro; 1953 #endif 1954 uint16_t err_vec, tnl_type, tnlhdr_len; 1955 static const int sw_hashtype[4][2] = { 1956 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1957 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1958 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1959 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1960 }; 1961 static const int sw_csum_flags[2][2] = { 1962 { 1963 /* IP, inner IP */ 1964 CSUM_ENCAP_VXLAN | 1965 CSUM_L3_CALC | CSUM_L3_VALID | 1966 CSUM_L4_CALC | CSUM_L4_VALID | 1967 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1968 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1969 1970 /* IP, inner IP6 */ 1971 CSUM_ENCAP_VXLAN | 1972 CSUM_L3_CALC | CSUM_L3_VALID | 1973 CSUM_L4_CALC | CSUM_L4_VALID | 1974 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1975 }, 1976 { 1977 /* IP6, inner IP */ 1978 CSUM_ENCAP_VXLAN | 1979 CSUM_L4_CALC | CSUM_L4_VALID | 1980 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1981 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1982 1983 /* IP6, inner IP6 */ 1984 CSUM_ENCAP_VXLAN | 1985 CSUM_L4_CALC | CSUM_L4_VALID | 1986 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1987 }, 1988 }; 1989 1990 MPASS(plen > sc->params.sge.fl_pktshift); 1991 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) && 1992 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) { 1993 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1994 caddr_t frame; 1995 int rc, slen; 1996 1997 slen = get_segment_len(sc, fl, plen) - 1998 sc->params.sge.fl_pktshift; 1999 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift; 2000 CURVNET_SET_QUIET(ifp->if_vnet); 2001 rc = pfil_run_hooks(vi->pfil, frame, ifp, 2002 slen | PFIL_MEMPTR | PFIL_IN, NULL); 2003 CURVNET_RESTORE(); 2004 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) { 2005 skip_fl_payload(sc, fl, plen); 2006 return (0); 2007 } 2008 if (rc == PFIL_REALLOCED) { 2009 skip_fl_payload(sc, fl, plen); 2010 m0 = pfil_mem2mbuf(frame); 2011 goto have_mbuf; 2012 } 2013 } 2014 2015 m0 = get_fl_payload(sc, fl, plen); 2016 if (__predict_false(m0 == NULL)) 2017 return (ENOMEM); 2018 2019 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 2020 m0->m_len -= sc->params.sge.fl_pktshift; 2021 m0->m_data += sc->params.sge.fl_pktshift; 2022 2023 have_mbuf: 2024 m0->m_pkthdr.rcvif = ifp; 2025 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]); 2026 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val); 2027 2028 cpl = (const void *)(&d->rss + 1); 2029 if (sc->params.tp.rx_pkt_encap) { 2030 const uint16_t ev = be16toh(cpl->err_vec); 2031 2032 err_vec = G_T6_COMPR_RXERR_VEC(ev); 2033 tnl_type = G_T6_RX_TNL_TYPE(ev); 2034 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev); 2035 } else { 2036 err_vec = be16toh(cpl->err_vec); 2037 tnl_type = 0; 2038 tnlhdr_len = 0; 2039 } 2040 if (cpl->csum_calc && err_vec == 0) { 2041 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6)); 2042 2043 /* checksum(s) calculated and found to be correct. */ 2044 2045 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^ 2046 (cpl->l2info & htobe32(F_RXF_IP6))); 2047 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2048 if (tnl_type == 0) { 2049 if (!ipv6 && ifp->if_capenable & IFCAP_RXCSUM) { 2050 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2051 CSUM_L3_VALID | CSUM_L4_CALC | 2052 CSUM_L4_VALID; 2053 } else if (ipv6 && ifp->if_capenable & IFCAP_RXCSUM_IPV6) { 2054 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2055 CSUM_L4_VALID; 2056 } 2057 rxq->rxcsum++; 2058 } else { 2059 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN); 2060 2061 M_HASHTYPE_SETINNER(m0); 2062 if (__predict_false(cpl->ip_frag)) { 2063 /* 2064 * csum_data is for the inner frame (which is an 2065 * IP fragment) and is not 0xffff. There is no 2066 * way to pass the inner csum_data to the stack. 2067 * We don't want the stack to use the inner 2068 * csum_data to validate the outer frame or it 2069 * will get rejected. So we fix csum_data here 2070 * and let sw do the checksum of inner IP 2071 * fragments. 2072 * 2073 * XXX: Need 32b for csum_data2 in an rx mbuf. 2074 * Maybe stuff it into rcv_tstmp? 2075 */ 2076 m0->m_pkthdr.csum_data = 0xffff; 2077 if (ipv6) { 2078 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2079 CSUM_L4_VALID; 2080 } else { 2081 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2082 CSUM_L3_VALID | CSUM_L4_CALC | 2083 CSUM_L4_VALID; 2084 } 2085 } else { 2086 int outer_ipv6; 2087 2088 MPASS(m0->m_pkthdr.csum_data == 0xffff); 2089 2090 outer_ipv6 = tnlhdr_len >= 2091 sizeof(struct ether_header) + 2092 sizeof(struct ip6_hdr); 2093 m0->m_pkthdr.csum_flags = 2094 sw_csum_flags[outer_ipv6][ipv6]; 2095 } 2096 rxq->vxlan_rxcsum++; 2097 } 2098 } 2099 2100 if (cpl->vlan_ex) { 2101 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2102 m0->m_flags |= M_VLANTAG; 2103 rxq->vlan_extraction++; 2104 } 2105 2106 if (rxq->iq.flags & IQ_RX_TIMESTAMP) { 2107 /* 2108 * Fill up rcv_tstmp but do not set M_TSTMP as 2109 * long as we get a non-zero back from t4_tstmp_to_ns(). 2110 */ 2111 m0->m_pkthdr.rcv_tstmp = t4_tstmp_to_ns(sc, 2112 be64toh(d->rsp.u.last_flit)); 2113 if (m0->m_pkthdr.rcv_tstmp != 0) 2114 m0->m_flags |= M_TSTMP; 2115 } 2116 2117 #ifdef NUMA 2118 m0->m_pkthdr.numa_domain = ifp->if_numa_domain; 2119 #endif 2120 #if defined(INET) || defined(INET6) 2121 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 && 2122 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 || 2123 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) { 2124 if (sort_before_lro(lro)) { 2125 tcp_lro_queue_mbuf(lro, m0); 2126 return (0); /* queued for sort, then LRO */ 2127 } 2128 if (tcp_lro_rx(lro, m0, 0) == 0) 2129 return (0); /* queued for LRO */ 2130 } 2131 #endif 2132 ifp->if_input(ifp, m0); 2133 2134 return (0); 2135 } 2136 2137 /* 2138 * Must drain the wrq or make sure that someone else will. 2139 */ 2140 static void 2141 wrq_tx_drain(void *arg, int n) 2142 { 2143 struct sge_wrq *wrq = arg; 2144 struct sge_eq *eq = &wrq->eq; 2145 2146 EQ_LOCK(eq); 2147 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2148 drain_wrq_wr_list(wrq->adapter, wrq); 2149 EQ_UNLOCK(eq); 2150 } 2151 2152 static void 2153 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2154 { 2155 struct sge_eq *eq = &wrq->eq; 2156 u_int available, dbdiff; /* # of hardware descriptors */ 2157 u_int n; 2158 struct wrqe *wr; 2159 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2160 2161 EQ_LOCK_ASSERT_OWNED(eq); 2162 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2163 wr = STAILQ_FIRST(&wrq->wr_list); 2164 MPASS(wr != NULL); /* Must be called with something useful to do */ 2165 MPASS(eq->pidx == eq->dbidx); 2166 dbdiff = 0; 2167 2168 do { 2169 eq->cidx = read_hw_cidx(eq); 2170 if (eq->pidx == eq->cidx) 2171 available = eq->sidx - 1; 2172 else 2173 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2174 2175 MPASS(wr->wrq == wrq); 2176 n = howmany(wr->wr_len, EQ_ESIZE); 2177 if (available < n) 2178 break; 2179 2180 dst = (void *)&eq->desc[eq->pidx]; 2181 if (__predict_true(eq->sidx - eq->pidx > n)) { 2182 /* Won't wrap, won't end exactly at the status page. */ 2183 bcopy(&wr->wr[0], dst, wr->wr_len); 2184 eq->pidx += n; 2185 } else { 2186 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2187 2188 bcopy(&wr->wr[0], dst, first_portion); 2189 if (wr->wr_len > first_portion) { 2190 bcopy(&wr->wr[first_portion], &eq->desc[0], 2191 wr->wr_len - first_portion); 2192 } 2193 eq->pidx = n - (eq->sidx - eq->pidx); 2194 } 2195 wrq->tx_wrs_copied++; 2196 2197 if (available < eq->sidx / 4 && 2198 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2199 /* 2200 * XXX: This is not 100% reliable with some 2201 * types of WRs. But this is a very unusual 2202 * situation for an ofld/ctrl queue anyway. 2203 */ 2204 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2205 F_FW_WR_EQUEQ); 2206 } 2207 2208 dbdiff += n; 2209 if (dbdiff >= 16) { 2210 ring_eq_db(sc, eq, dbdiff); 2211 dbdiff = 0; 2212 } 2213 2214 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2215 free_wrqe(wr); 2216 MPASS(wrq->nwr_pending > 0); 2217 wrq->nwr_pending--; 2218 MPASS(wrq->ndesc_needed >= n); 2219 wrq->ndesc_needed -= n; 2220 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2221 2222 if (dbdiff) 2223 ring_eq_db(sc, eq, dbdiff); 2224 } 2225 2226 /* 2227 * Doesn't fail. Holds on to work requests it can't send right away. 2228 */ 2229 void 2230 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2231 { 2232 #ifdef INVARIANTS 2233 struct sge_eq *eq = &wrq->eq; 2234 #endif 2235 2236 EQ_LOCK_ASSERT_OWNED(eq); 2237 MPASS(wr != NULL); 2238 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2239 MPASS((wr->wr_len & 0x7) == 0); 2240 2241 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2242 wrq->nwr_pending++; 2243 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2244 2245 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2246 return; /* commit_wrq_wr will drain wr_list as well. */ 2247 2248 drain_wrq_wr_list(sc, wrq); 2249 2250 /* Doorbell must have caught up to the pidx. */ 2251 MPASS(eq->pidx == eq->dbidx); 2252 } 2253 2254 void 2255 t4_update_fl_bufsize(struct ifnet *ifp) 2256 { 2257 struct vi_info *vi = ifp->if_softc; 2258 struct adapter *sc = vi->adapter; 2259 struct sge_rxq *rxq; 2260 #ifdef TCP_OFFLOAD 2261 struct sge_ofld_rxq *ofld_rxq; 2262 #endif 2263 struct sge_fl *fl; 2264 int i, maxp; 2265 2266 maxp = max_rx_payload(sc, ifp, false); 2267 for_each_rxq(vi, i, rxq) { 2268 fl = &rxq->fl; 2269 2270 FL_LOCK(fl); 2271 fl->zidx = find_refill_source(sc, maxp, 2272 fl->flags & FL_BUF_PACKING); 2273 FL_UNLOCK(fl); 2274 } 2275 #ifdef TCP_OFFLOAD 2276 maxp = max_rx_payload(sc, ifp, true); 2277 for_each_ofld_rxq(vi, i, ofld_rxq) { 2278 fl = &ofld_rxq->fl; 2279 2280 FL_LOCK(fl); 2281 fl->zidx = find_refill_source(sc, maxp, 2282 fl->flags & FL_BUF_PACKING); 2283 FL_UNLOCK(fl); 2284 } 2285 #endif 2286 } 2287 2288 static inline int 2289 mbuf_nsegs(struct mbuf *m) 2290 { 2291 2292 M_ASSERTPKTHDR(m); 2293 KASSERT(m->m_pkthdr.inner_l5hlen > 0, 2294 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2295 2296 return (m->m_pkthdr.inner_l5hlen); 2297 } 2298 2299 static inline void 2300 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2301 { 2302 2303 M_ASSERTPKTHDR(m); 2304 m->m_pkthdr.inner_l5hlen = nsegs; 2305 } 2306 2307 static inline int 2308 mbuf_cflags(struct mbuf *m) 2309 { 2310 2311 M_ASSERTPKTHDR(m); 2312 return (m->m_pkthdr.PH_loc.eight[4]); 2313 } 2314 2315 static inline void 2316 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2317 { 2318 2319 M_ASSERTPKTHDR(m); 2320 m->m_pkthdr.PH_loc.eight[4] = flags; 2321 } 2322 2323 static inline int 2324 mbuf_len16(struct mbuf *m) 2325 { 2326 int n; 2327 2328 M_ASSERTPKTHDR(m); 2329 n = m->m_pkthdr.PH_loc.eight[0]; 2330 if (!(mbuf_cflags(m) & MC_TLS)) 2331 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2332 2333 return (n); 2334 } 2335 2336 static inline void 2337 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2338 { 2339 2340 M_ASSERTPKTHDR(m); 2341 if (!(mbuf_cflags(m) & MC_TLS)) 2342 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16); 2343 m->m_pkthdr.PH_loc.eight[0] = len16; 2344 } 2345 2346 #ifdef RATELIMIT 2347 static inline int 2348 mbuf_eo_nsegs(struct mbuf *m) 2349 { 2350 2351 M_ASSERTPKTHDR(m); 2352 return (m->m_pkthdr.PH_loc.eight[1]); 2353 } 2354 2355 #if defined(INET) || defined(INET6) 2356 static inline void 2357 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2358 { 2359 2360 M_ASSERTPKTHDR(m); 2361 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2362 } 2363 #endif 2364 2365 static inline int 2366 mbuf_eo_len16(struct mbuf *m) 2367 { 2368 int n; 2369 2370 M_ASSERTPKTHDR(m); 2371 n = m->m_pkthdr.PH_loc.eight[2]; 2372 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2373 2374 return (n); 2375 } 2376 2377 #if defined(INET) || defined(INET6) 2378 static inline void 2379 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2380 { 2381 2382 M_ASSERTPKTHDR(m); 2383 m->m_pkthdr.PH_loc.eight[2] = len16; 2384 } 2385 #endif 2386 2387 static inline int 2388 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2389 { 2390 2391 M_ASSERTPKTHDR(m); 2392 return (m->m_pkthdr.PH_loc.eight[3]); 2393 } 2394 2395 #if defined(INET) || defined(INET6) 2396 static inline void 2397 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2398 { 2399 2400 M_ASSERTPKTHDR(m); 2401 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2402 } 2403 #endif 2404 2405 static inline int 2406 needs_eo(struct m_snd_tag *mst) 2407 { 2408 2409 return (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_RATE_LIMIT); 2410 } 2411 #endif 2412 2413 /* 2414 * Try to allocate an mbuf to contain a raw work request. To make it 2415 * easy to construct the work request, don't allocate a chain but a 2416 * single mbuf. 2417 */ 2418 struct mbuf * 2419 alloc_wr_mbuf(int len, int how) 2420 { 2421 struct mbuf *m; 2422 2423 if (len <= MHLEN) 2424 m = m_gethdr(how, MT_DATA); 2425 else if (len <= MCLBYTES) 2426 m = m_getcl(how, MT_DATA, M_PKTHDR); 2427 else 2428 m = NULL; 2429 if (m == NULL) 2430 return (NULL); 2431 m->m_pkthdr.len = len; 2432 m->m_len = len; 2433 set_mbuf_cflags(m, MC_RAW_WR); 2434 set_mbuf_len16(m, howmany(len, 16)); 2435 return (m); 2436 } 2437 2438 static inline bool 2439 needs_hwcsum(struct mbuf *m) 2440 { 2441 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | 2442 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2443 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP | 2444 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP | 2445 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO; 2446 2447 M_ASSERTPKTHDR(m); 2448 2449 return (m->m_pkthdr.csum_flags & csum_flags); 2450 } 2451 2452 static inline bool 2453 needs_tso(struct mbuf *m) 2454 { 2455 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO | 2456 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2457 2458 M_ASSERTPKTHDR(m); 2459 2460 return (m->m_pkthdr.csum_flags & csum_flags); 2461 } 2462 2463 static inline bool 2464 needs_vxlan_csum(struct mbuf *m) 2465 { 2466 2467 M_ASSERTPKTHDR(m); 2468 2469 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN); 2470 } 2471 2472 static inline bool 2473 needs_vxlan_tso(struct mbuf *m) 2474 { 2475 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO | 2476 CSUM_INNER_IP6_TSO; 2477 2478 M_ASSERTPKTHDR(m); 2479 2480 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 && 2481 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN); 2482 } 2483 2484 #if defined(INET) || defined(INET6) 2485 static inline bool 2486 needs_inner_tcp_csum(struct mbuf *m) 2487 { 2488 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2489 2490 M_ASSERTPKTHDR(m); 2491 2492 return (m->m_pkthdr.csum_flags & csum_flags); 2493 } 2494 #endif 2495 2496 static inline bool 2497 needs_l3_csum(struct mbuf *m) 2498 { 2499 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP | 2500 CSUM_INNER_IP_TSO; 2501 2502 M_ASSERTPKTHDR(m); 2503 2504 return (m->m_pkthdr.csum_flags & csum_flags); 2505 } 2506 2507 static inline bool 2508 needs_outer_tcp_csum(struct mbuf *m) 2509 { 2510 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP | 2511 CSUM_IP6_TSO; 2512 2513 M_ASSERTPKTHDR(m); 2514 2515 return (m->m_pkthdr.csum_flags & csum_flags); 2516 } 2517 2518 #ifdef RATELIMIT 2519 static inline bool 2520 needs_outer_l4_csum(struct mbuf *m) 2521 { 2522 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO | 2523 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO; 2524 2525 M_ASSERTPKTHDR(m); 2526 2527 return (m->m_pkthdr.csum_flags & csum_flags); 2528 } 2529 2530 static inline bool 2531 needs_outer_udp_csum(struct mbuf *m) 2532 { 2533 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP; 2534 2535 M_ASSERTPKTHDR(m); 2536 2537 return (m->m_pkthdr.csum_flags & csum_flags); 2538 } 2539 #endif 2540 2541 static inline bool 2542 needs_vlan_insertion(struct mbuf *m) 2543 { 2544 2545 M_ASSERTPKTHDR(m); 2546 2547 return (m->m_flags & M_VLANTAG); 2548 } 2549 2550 #if defined(INET) || defined(INET6) 2551 static void * 2552 m_advance(struct mbuf **pm, int *poffset, int len) 2553 { 2554 struct mbuf *m = *pm; 2555 int offset = *poffset; 2556 uintptr_t p = 0; 2557 2558 MPASS(len > 0); 2559 2560 for (;;) { 2561 if (offset + len < m->m_len) { 2562 offset += len; 2563 p = mtod(m, uintptr_t) + offset; 2564 break; 2565 } 2566 len -= m->m_len - offset; 2567 m = m->m_next; 2568 offset = 0; 2569 MPASS(m != NULL); 2570 } 2571 *poffset = offset; 2572 *pm = m; 2573 return ((void *)p); 2574 } 2575 #endif 2576 2577 static inline int 2578 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr) 2579 { 2580 vm_paddr_t paddr; 2581 int i, len, off, pglen, pgoff, seglen, segoff; 2582 int nsegs = 0; 2583 2584 M_ASSERTEXTPG(m); 2585 off = mtod(m, vm_offset_t); 2586 len = m->m_len; 2587 off += skip; 2588 len -= skip; 2589 2590 if (m->m_epg_hdrlen != 0) { 2591 if (off >= m->m_epg_hdrlen) { 2592 off -= m->m_epg_hdrlen; 2593 } else { 2594 seglen = m->m_epg_hdrlen - off; 2595 segoff = off; 2596 seglen = min(seglen, len); 2597 off = 0; 2598 len -= seglen; 2599 paddr = pmap_kextract( 2600 (vm_offset_t)&m->m_epg_hdr[segoff]); 2601 if (*nextaddr != paddr) 2602 nsegs++; 2603 *nextaddr = paddr + seglen; 2604 } 2605 } 2606 pgoff = m->m_epg_1st_off; 2607 for (i = 0; i < m->m_epg_npgs && len > 0; i++) { 2608 pglen = m_epg_pagelen(m, i, pgoff); 2609 if (off >= pglen) { 2610 off -= pglen; 2611 pgoff = 0; 2612 continue; 2613 } 2614 seglen = pglen - off; 2615 segoff = pgoff + off; 2616 off = 0; 2617 seglen = min(seglen, len); 2618 len -= seglen; 2619 paddr = m->m_epg_pa[i] + segoff; 2620 if (*nextaddr != paddr) 2621 nsegs++; 2622 *nextaddr = paddr + seglen; 2623 pgoff = 0; 2624 }; 2625 if (len != 0) { 2626 seglen = min(len, m->m_epg_trllen - off); 2627 len -= seglen; 2628 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]); 2629 if (*nextaddr != paddr) 2630 nsegs++; 2631 *nextaddr = paddr + seglen; 2632 } 2633 2634 return (nsegs); 2635 } 2636 2637 2638 /* 2639 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2640 * must have at least one mbuf that's not empty. It is possible for this 2641 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2642 */ 2643 static inline int 2644 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags) 2645 { 2646 vm_paddr_t nextaddr, paddr; 2647 vm_offset_t va; 2648 int len, nsegs; 2649 2650 M_ASSERTPKTHDR(m); 2651 MPASS(m->m_pkthdr.len > 0); 2652 MPASS(m->m_pkthdr.len >= skip); 2653 2654 nsegs = 0; 2655 nextaddr = 0; 2656 for (; m; m = m->m_next) { 2657 len = m->m_len; 2658 if (__predict_false(len == 0)) 2659 continue; 2660 if (skip >= len) { 2661 skip -= len; 2662 continue; 2663 } 2664 if ((m->m_flags & M_EXTPG) != 0) { 2665 *cflags |= MC_NOMAP; 2666 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr); 2667 skip = 0; 2668 continue; 2669 } 2670 va = mtod(m, vm_offset_t) + skip; 2671 len -= skip; 2672 skip = 0; 2673 paddr = pmap_kextract(va); 2674 nsegs += sglist_count((void *)(uintptr_t)va, len); 2675 if (paddr == nextaddr) 2676 nsegs--; 2677 nextaddr = pmap_kextract(va + len - 1) + 1; 2678 } 2679 2680 return (nsegs); 2681 } 2682 2683 /* 2684 * The maximum number of segments that can fit in a WR. 2685 */ 2686 static int 2687 max_nsegs_allowed(struct mbuf *m, bool vm_wr) 2688 { 2689 2690 if (vm_wr) { 2691 if (needs_tso(m)) 2692 return (TX_SGL_SEGS_VM_TSO); 2693 return (TX_SGL_SEGS_VM); 2694 } 2695 2696 if (needs_tso(m)) { 2697 if (needs_vxlan_tso(m)) 2698 return (TX_SGL_SEGS_VXLAN_TSO); 2699 else 2700 return (TX_SGL_SEGS_TSO); 2701 } 2702 2703 return (TX_SGL_SEGS); 2704 } 2705 2706 static struct timeval txerr_ratecheck = {0}; 2707 static const struct timeval txerr_interval = {3, 0}; 2708 2709 /* 2710 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2711 * a) caller can assume it's been freed if this function returns with an error. 2712 * b) it may get defragged up if the gather list is too long for the hardware. 2713 */ 2714 int 2715 parse_pkt(struct mbuf **mp, bool vm_wr) 2716 { 2717 struct mbuf *m0 = *mp, *m; 2718 int rc, nsegs, defragged = 0; 2719 struct ether_header *eh; 2720 #ifdef INET 2721 void *l3hdr; 2722 #endif 2723 #if defined(INET) || defined(INET6) 2724 int offset; 2725 struct tcphdr *tcp; 2726 #endif 2727 #if defined(KERN_TLS) || defined(RATELIMIT) 2728 struct m_snd_tag *mst; 2729 #endif 2730 uint16_t eh_type; 2731 uint8_t cflags; 2732 2733 cflags = 0; 2734 M_ASSERTPKTHDR(m0); 2735 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2736 rc = EINVAL; 2737 fail: 2738 m_freem(m0); 2739 *mp = NULL; 2740 return (rc); 2741 } 2742 restart: 2743 /* 2744 * First count the number of gather list segments in the payload. 2745 * Defrag the mbuf if nsegs exceeds the hardware limit. 2746 */ 2747 M_ASSERTPKTHDR(m0); 2748 MPASS(m0->m_pkthdr.len > 0); 2749 nsegs = count_mbuf_nsegs(m0, 0, &cflags); 2750 #if defined(KERN_TLS) || defined(RATELIMIT) 2751 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG) 2752 mst = m0->m_pkthdr.snd_tag; 2753 else 2754 mst = NULL; 2755 #endif 2756 #ifdef KERN_TLS 2757 if (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_TLS) { 2758 int len16; 2759 2760 cflags |= MC_TLS; 2761 set_mbuf_cflags(m0, cflags); 2762 rc = t6_ktls_parse_pkt(m0, &nsegs, &len16); 2763 if (rc != 0) 2764 goto fail; 2765 set_mbuf_nsegs(m0, nsegs); 2766 set_mbuf_len16(m0, len16); 2767 return (0); 2768 } 2769 #endif 2770 if (nsegs > max_nsegs_allowed(m0, vm_wr)) { 2771 if (defragged++ > 0) { 2772 rc = EFBIG; 2773 goto fail; 2774 } 2775 counter_u64_add(defrags, 1); 2776 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) { 2777 rc = ENOMEM; 2778 goto fail; 2779 } 2780 *mp = m0 = m; /* update caller's copy after defrag */ 2781 goto restart; 2782 } 2783 2784 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN && 2785 !(cflags & MC_NOMAP))) { 2786 counter_u64_add(pullups, 1); 2787 m0 = m_pullup(m0, m0->m_pkthdr.len); 2788 if (m0 == NULL) { 2789 /* Should have left well enough alone. */ 2790 rc = EFBIG; 2791 goto fail; 2792 } 2793 *mp = m0; /* update caller's copy after pullup */ 2794 goto restart; 2795 } 2796 set_mbuf_nsegs(m0, nsegs); 2797 set_mbuf_cflags(m0, cflags); 2798 calculate_mbuf_len16(m0, vm_wr); 2799 2800 #ifdef RATELIMIT 2801 /* 2802 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2803 * checksumming is enabled. needs_outer_l4_csum happens to check for 2804 * all the right things. 2805 */ 2806 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) { 2807 m_snd_tag_rele(m0->m_pkthdr.snd_tag); 2808 m0->m_pkthdr.snd_tag = NULL; 2809 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 2810 mst = NULL; 2811 } 2812 #endif 2813 2814 if (!needs_hwcsum(m0) 2815 #ifdef RATELIMIT 2816 && !needs_eo(mst) 2817 #endif 2818 ) 2819 return (0); 2820 2821 m = m0; 2822 eh = mtod(m, struct ether_header *); 2823 eh_type = ntohs(eh->ether_type); 2824 if (eh_type == ETHERTYPE_VLAN) { 2825 struct ether_vlan_header *evh = (void *)eh; 2826 2827 eh_type = ntohs(evh->evl_proto); 2828 m0->m_pkthdr.l2hlen = sizeof(*evh); 2829 } else 2830 m0->m_pkthdr.l2hlen = sizeof(*eh); 2831 2832 #if defined(INET) || defined(INET6) 2833 offset = 0; 2834 #ifdef INET 2835 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2836 #else 2837 m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2838 #endif 2839 #endif 2840 2841 switch (eh_type) { 2842 #ifdef INET6 2843 case ETHERTYPE_IPV6: 2844 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr); 2845 break; 2846 #endif 2847 #ifdef INET 2848 case ETHERTYPE_IP: 2849 { 2850 struct ip *ip = l3hdr; 2851 2852 if (needs_vxlan_csum(m0)) { 2853 /* Driver will do the outer IP hdr checksum. */ 2854 ip->ip_sum = 0; 2855 if (needs_vxlan_tso(m0)) { 2856 const uint16_t ipl = ip->ip_len; 2857 2858 ip->ip_len = 0; 2859 ip->ip_sum = ~in_cksum_hdr(ip); 2860 ip->ip_len = ipl; 2861 } else 2862 ip->ip_sum = in_cksum_hdr(ip); 2863 } 2864 m0->m_pkthdr.l3hlen = ip->ip_hl << 2; 2865 break; 2866 } 2867 #endif 2868 default: 2869 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2870 log(LOG_ERR, "%s: ethertype 0x%04x unknown. " 2871 "if_cxgbe must be compiled with the same " 2872 "INET/INET6 options as the kernel.\n", __func__, 2873 eh_type); 2874 } 2875 rc = EINVAL; 2876 goto fail; 2877 } 2878 2879 #if defined(INET) || defined(INET6) 2880 if (needs_vxlan_csum(m0)) { 2881 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2882 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header); 2883 2884 /* Inner headers. */ 2885 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen + 2886 sizeof(struct udphdr) + sizeof(struct vxlan_header)); 2887 eh_type = ntohs(eh->ether_type); 2888 if (eh_type == ETHERTYPE_VLAN) { 2889 struct ether_vlan_header *evh = (void *)eh; 2890 2891 eh_type = ntohs(evh->evl_proto); 2892 m0->m_pkthdr.inner_l2hlen = sizeof(*evh); 2893 } else 2894 m0->m_pkthdr.inner_l2hlen = sizeof(*eh); 2895 #ifdef INET 2896 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2897 #else 2898 m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2899 #endif 2900 2901 switch (eh_type) { 2902 #ifdef INET6 2903 case ETHERTYPE_IPV6: 2904 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr); 2905 break; 2906 #endif 2907 #ifdef INET 2908 case ETHERTYPE_IP: 2909 { 2910 struct ip *ip = l3hdr; 2911 2912 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2; 2913 break; 2914 } 2915 #endif 2916 default: 2917 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2918 log(LOG_ERR, "%s: VXLAN hw offload requested" 2919 "with unknown ethertype 0x%04x. if_cxgbe " 2920 "must be compiled with the same INET/INET6 " 2921 "options as the kernel.\n", __func__, 2922 eh_type); 2923 } 2924 rc = EINVAL; 2925 goto fail; 2926 } 2927 if (needs_inner_tcp_csum(m0)) { 2928 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen); 2929 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4; 2930 } 2931 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0); 2932 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP | 2933 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP | 2934 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | 2935 CSUM_ENCAP_VXLAN; 2936 } 2937 2938 if (needs_outer_tcp_csum(m0)) { 2939 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2940 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2941 #ifdef RATELIMIT 2942 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2943 set_mbuf_eo_tsclk_tsoff(m0, 2944 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2945 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2946 } else 2947 set_mbuf_eo_tsclk_tsoff(m0, 0); 2948 } else if (needs_outer_udp_csum(m0)) { 2949 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2950 #endif 2951 } 2952 #ifdef RATELIMIT 2953 if (needs_eo(mst)) { 2954 u_int immhdrs; 2955 2956 /* EO WRs have the headers in the WR and not the GL. */ 2957 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2958 m0->m_pkthdr.l4hlen; 2959 cflags = 0; 2960 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags); 2961 MPASS(cflags == mbuf_cflags(m0)); 2962 set_mbuf_eo_nsegs(m0, nsegs); 2963 set_mbuf_eo_len16(m0, 2964 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2965 } 2966 #endif 2967 #endif 2968 MPASS(m0 == *mp); 2969 return (0); 2970 } 2971 2972 void * 2973 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2974 { 2975 struct sge_eq *eq = &wrq->eq; 2976 struct adapter *sc = wrq->adapter; 2977 int ndesc, available; 2978 struct wrqe *wr; 2979 void *w; 2980 2981 MPASS(len16 > 0); 2982 ndesc = tx_len16_to_desc(len16); 2983 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2984 2985 EQ_LOCK(eq); 2986 2987 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2988 drain_wrq_wr_list(sc, wrq); 2989 2990 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2991 slowpath: 2992 EQ_UNLOCK(eq); 2993 wr = alloc_wrqe(len16 * 16, wrq); 2994 if (__predict_false(wr == NULL)) 2995 return (NULL); 2996 cookie->pidx = -1; 2997 cookie->ndesc = ndesc; 2998 return (&wr->wr); 2999 } 3000 3001 eq->cidx = read_hw_cidx(eq); 3002 if (eq->pidx == eq->cidx) 3003 available = eq->sidx - 1; 3004 else 3005 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3006 if (available < ndesc) 3007 goto slowpath; 3008 3009 cookie->pidx = eq->pidx; 3010 cookie->ndesc = ndesc; 3011 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 3012 3013 w = &eq->desc[eq->pidx]; 3014 IDXINCR(eq->pidx, ndesc, eq->sidx); 3015 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 3016 w = &wrq->ss[0]; 3017 wrq->ss_pidx = cookie->pidx; 3018 wrq->ss_len = len16 * 16; 3019 } 3020 3021 EQ_UNLOCK(eq); 3022 3023 return (w); 3024 } 3025 3026 void 3027 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 3028 { 3029 struct sge_eq *eq = &wrq->eq; 3030 struct adapter *sc = wrq->adapter; 3031 int ndesc, pidx; 3032 struct wrq_cookie *prev, *next; 3033 3034 if (cookie->pidx == -1) { 3035 struct wrqe *wr = __containerof(w, struct wrqe, wr); 3036 3037 t4_wrq_tx(sc, wr); 3038 return; 3039 } 3040 3041 if (__predict_false(w == &wrq->ss[0])) { 3042 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 3043 3044 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 3045 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 3046 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 3047 wrq->tx_wrs_ss++; 3048 } else 3049 wrq->tx_wrs_direct++; 3050 3051 EQ_LOCK(eq); 3052 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 3053 pidx = cookie->pidx; 3054 MPASS(pidx >= 0 && pidx < eq->sidx); 3055 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 3056 next = TAILQ_NEXT(cookie, link); 3057 if (prev == NULL) { 3058 MPASS(pidx == eq->dbidx); 3059 if (next == NULL || ndesc >= 16) { 3060 int available; 3061 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 3062 3063 /* 3064 * Note that the WR via which we'll request tx updates 3065 * is at pidx and not eq->pidx, which has moved on 3066 * already. 3067 */ 3068 dst = (void *)&eq->desc[pidx]; 3069 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3070 if (available < eq->sidx / 4 && 3071 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3072 /* 3073 * XXX: This is not 100% reliable with some 3074 * types of WRs. But this is a very unusual 3075 * situation for an ofld/ctrl queue anyway. 3076 */ 3077 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 3078 F_FW_WR_EQUEQ); 3079 } 3080 3081 ring_eq_db(wrq->adapter, eq, ndesc); 3082 } else { 3083 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 3084 next->pidx = pidx; 3085 next->ndesc += ndesc; 3086 } 3087 } else { 3088 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 3089 prev->ndesc += ndesc; 3090 } 3091 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 3092 3093 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 3094 drain_wrq_wr_list(sc, wrq); 3095 3096 #ifdef INVARIANTS 3097 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 3098 /* Doorbell must have caught up to the pidx. */ 3099 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 3100 } 3101 #endif 3102 EQ_UNLOCK(eq); 3103 } 3104 3105 static u_int 3106 can_resume_eth_tx(struct mp_ring *r) 3107 { 3108 struct sge_eq *eq = r->cookie; 3109 3110 return (total_available_tx_desc(eq) > eq->sidx / 8); 3111 } 3112 3113 static inline bool 3114 cannot_use_txpkts(struct mbuf *m) 3115 { 3116 /* maybe put a GL limit too, to avoid silliness? */ 3117 3118 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0); 3119 } 3120 3121 static inline int 3122 discard_tx(struct sge_eq *eq) 3123 { 3124 3125 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 3126 } 3127 3128 static inline int 3129 wr_can_update_eq(void *p) 3130 { 3131 struct fw_eth_tx_pkts_wr *wr = p; 3132 3133 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 3134 case FW_ULPTX_WR: 3135 case FW_ETH_TX_PKT_WR: 3136 case FW_ETH_TX_PKTS_WR: 3137 case FW_ETH_TX_PKTS2_WR: 3138 case FW_ETH_TX_PKT_VM_WR: 3139 case FW_ETH_TX_PKTS_VM_WR: 3140 return (1); 3141 default: 3142 return (0); 3143 } 3144 } 3145 3146 static inline void 3147 set_txupdate_flags(struct sge_txq *txq, u_int avail, 3148 struct fw_eth_tx_pkt_wr *wr) 3149 { 3150 struct sge_eq *eq = &txq->eq; 3151 struct txpkts *txp = &txq->txp; 3152 3153 if ((txp->npkt > 0 || avail < eq->sidx / 2) && 3154 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3155 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3156 eq->equeqidx = eq->pidx; 3157 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 3158 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 3159 eq->equeqidx = eq->pidx; 3160 } 3161 } 3162 3163 #if defined(__i386__) || defined(__amd64__) 3164 extern uint64_t tsc_freq; 3165 #endif 3166 3167 static inline bool 3168 record_eth_tx_time(struct sge_txq *txq) 3169 { 3170 const uint64_t cycles = get_cyclecount(); 3171 const uint64_t last_tx = txq->last_tx; 3172 #if defined(__i386__) || defined(__amd64__) 3173 const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000; 3174 #else 3175 const uint64_t itg = 0; 3176 #endif 3177 3178 MPASS(cycles >= last_tx); 3179 txq->last_tx = cycles; 3180 return (cycles - last_tx < itg); 3181 } 3182 3183 /* 3184 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 3185 * be consumed. Return the actual number consumed. 0 indicates a stall. 3186 */ 3187 static u_int 3188 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing) 3189 { 3190 struct sge_txq *txq = r->cookie; 3191 struct ifnet *ifp = txq->ifp; 3192 struct sge_eq *eq = &txq->eq; 3193 struct txpkts *txp = &txq->txp; 3194 struct vi_info *vi = ifp->if_softc; 3195 struct adapter *sc = vi->adapter; 3196 u_int total, remaining; /* # of packets */ 3197 u_int n, avail, dbdiff; /* # of hardware descriptors */ 3198 int i, rc; 3199 struct mbuf *m0; 3200 bool snd, recent_tx; 3201 void *wr; /* start of the last WR written to the ring */ 3202 3203 TXQ_LOCK_ASSERT_OWNED(txq); 3204 recent_tx = record_eth_tx_time(txq); 3205 3206 remaining = IDXDIFF(pidx, cidx, r->size); 3207 if (__predict_false(discard_tx(eq))) { 3208 for (i = 0; i < txp->npkt; i++) 3209 m_freem(txp->mb[i]); 3210 txp->npkt = 0; 3211 while (cidx != pidx) { 3212 m0 = r->items[cidx]; 3213 m_freem(m0); 3214 if (++cidx == r->size) 3215 cidx = 0; 3216 } 3217 reclaim_tx_descs(txq, eq->sidx); 3218 *coalescing = false; 3219 return (remaining); /* emptied */ 3220 } 3221 3222 /* How many hardware descriptors do we have readily available. */ 3223 if (eq->pidx == eq->cidx) 3224 avail = eq->sidx - 1; 3225 else 3226 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3227 3228 total = 0; 3229 if (remaining == 0) { 3230 txp->score = 0; 3231 txq->txpkts_flush++; 3232 goto send_txpkts; 3233 } 3234 3235 dbdiff = 0; 3236 MPASS(remaining > 0); 3237 while (remaining > 0) { 3238 m0 = r->items[cidx]; 3239 M_ASSERTPKTHDR(m0); 3240 MPASS(m0->m_nextpkt == NULL); 3241 3242 if (avail < 2 * SGE_MAX_WR_NDESC) 3243 avail += reclaim_tx_descs(txq, 64); 3244 3245 if (t4_tx_coalesce == 0 && txp->npkt == 0) 3246 goto skip_coalescing; 3247 if (cannot_use_txpkts(m0)) 3248 txp->score = 0; 3249 else if (recent_tx) { 3250 if (++txp->score == 0) 3251 txp->score = UINT8_MAX; 3252 } else 3253 txp->score = 1; 3254 if (txp->npkt > 0 || remaining > 1 || 3255 txp->score >= t4_tx_coalesce_pkts || 3256 atomic_load_int(&txq->eq.equiq) != 0) { 3257 if (vi->flags & TX_USES_VM_WR) 3258 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd); 3259 else 3260 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd); 3261 } else { 3262 snd = false; 3263 rc = EINVAL; 3264 } 3265 if (snd) { 3266 MPASS(txp->npkt > 0); 3267 for (i = 0; i < txp->npkt; i++) 3268 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3269 if (txp->npkt > 1) { 3270 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3271 if (vi->flags & TX_USES_VM_WR) 3272 n = write_txpkts_vm_wr(sc, txq); 3273 else 3274 n = write_txpkts_wr(sc, txq); 3275 } else { 3276 MPASS(avail >= 3277 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3278 if (vi->flags & TX_USES_VM_WR) 3279 n = write_txpkt_vm_wr(sc, txq, 3280 txp->mb[0]); 3281 else 3282 n = write_txpkt_wr(sc, txq, txp->mb[0], 3283 avail); 3284 } 3285 MPASS(n <= SGE_MAX_WR_NDESC); 3286 avail -= n; 3287 dbdiff += n; 3288 wr = &eq->desc[eq->pidx]; 3289 IDXINCR(eq->pidx, n, eq->sidx); 3290 txp->npkt = 0; /* emptied */ 3291 } 3292 if (rc == 0) { 3293 /* m0 was coalesced into txq->txpkts. */ 3294 goto next_mbuf; 3295 } 3296 if (rc == EAGAIN) { 3297 /* 3298 * m0 is suitable for tx coalescing but could not be 3299 * combined with the existing txq->txpkts, which has now 3300 * been transmitted. Start a new txpkts with m0. 3301 */ 3302 MPASS(snd); 3303 MPASS(txp->npkt == 0); 3304 continue; 3305 } 3306 3307 MPASS(rc != 0 && rc != EAGAIN); 3308 MPASS(txp->npkt == 0); 3309 skip_coalescing: 3310 n = tx_len16_to_desc(mbuf_len16(m0)); 3311 if (__predict_false(avail < n)) { 3312 avail += reclaim_tx_descs(txq, min(n, 32)); 3313 if (avail < n) 3314 break; /* out of descriptors */ 3315 } 3316 3317 wr = &eq->desc[eq->pidx]; 3318 if (mbuf_cflags(m0) & MC_RAW_WR) { 3319 n = write_raw_wr(txq, wr, m0, avail); 3320 #ifdef KERN_TLS 3321 } else if (mbuf_cflags(m0) & MC_TLS) { 3322 ETHER_BPF_MTAP(ifp, m0); 3323 n = t6_ktls_write_wr(txq, wr, m0, mbuf_nsegs(m0), 3324 avail); 3325 #endif 3326 } else { 3327 ETHER_BPF_MTAP(ifp, m0); 3328 if (vi->flags & TX_USES_VM_WR) 3329 n = write_txpkt_vm_wr(sc, txq, m0); 3330 else 3331 n = write_txpkt_wr(sc, txq, m0, avail); 3332 } 3333 MPASS(n >= 1 && n <= avail); 3334 if (!(mbuf_cflags(m0) & MC_TLS)) 3335 MPASS(n <= SGE_MAX_WR_NDESC); 3336 3337 avail -= n; 3338 dbdiff += n; 3339 IDXINCR(eq->pidx, n, eq->sidx); 3340 3341 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */ 3342 if (wr_can_update_eq(wr)) 3343 set_txupdate_flags(txq, avail, wr); 3344 ring_eq_db(sc, eq, dbdiff); 3345 avail += reclaim_tx_descs(txq, 32); 3346 dbdiff = 0; 3347 } 3348 next_mbuf: 3349 total++; 3350 remaining--; 3351 if (__predict_false(++cidx == r->size)) 3352 cidx = 0; 3353 } 3354 if (dbdiff != 0) { 3355 if (wr_can_update_eq(wr)) 3356 set_txupdate_flags(txq, avail, wr); 3357 ring_eq_db(sc, eq, dbdiff); 3358 reclaim_tx_descs(txq, 32); 3359 } else if (eq->pidx == eq->cidx && txp->npkt > 0 && 3360 atomic_load_int(&txq->eq.equiq) == 0) { 3361 /* 3362 * If nothing was submitted to the chip for tx (it was coalesced 3363 * into txpkts instead) and there is no tx update outstanding 3364 * then we need to send txpkts now. 3365 */ 3366 send_txpkts: 3367 MPASS(txp->npkt > 0); 3368 for (i = 0; i < txp->npkt; i++) 3369 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3370 if (txp->npkt > 1) { 3371 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3372 if (vi->flags & TX_USES_VM_WR) 3373 n = write_txpkts_vm_wr(sc, txq); 3374 else 3375 n = write_txpkts_wr(sc, txq); 3376 } else { 3377 MPASS(avail >= 3378 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3379 if (vi->flags & TX_USES_VM_WR) 3380 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]); 3381 else 3382 n = write_txpkt_wr(sc, txq, txp->mb[0], avail); 3383 } 3384 MPASS(n <= SGE_MAX_WR_NDESC); 3385 wr = &eq->desc[eq->pidx]; 3386 IDXINCR(eq->pidx, n, eq->sidx); 3387 txp->npkt = 0; /* emptied */ 3388 3389 MPASS(wr_can_update_eq(wr)); 3390 set_txupdate_flags(txq, avail - n, wr); 3391 ring_eq_db(sc, eq, n); 3392 reclaim_tx_descs(txq, 32); 3393 } 3394 *coalescing = txp->npkt > 0; 3395 3396 return (total); 3397 } 3398 3399 static inline void 3400 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 3401 int qsize, int intr_idx, int cong, int qtype) 3402 { 3403 3404 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 3405 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 3406 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 3407 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 3408 KASSERT(intr_idx >= -1 && intr_idx < sc->intr_count, 3409 ("%s: bad intr_idx %d", __func__, intr_idx)); 3410 KASSERT(qtype == FW_IQ_IQTYPE_OTHER || qtype == FW_IQ_IQTYPE_NIC || 3411 qtype == FW_IQ_IQTYPE_OFLD, ("%s: bad qtype %d", __func__, qtype)); 3412 3413 iq->flags = 0; 3414 iq->state = IQS_DISABLED; 3415 iq->adapter = sc; 3416 iq->qtype = qtype; 3417 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 3418 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 3419 if (pktc_idx >= 0) { 3420 iq->intr_params |= F_QINTR_CNT_EN; 3421 iq->intr_pktc_idx = pktc_idx; 3422 } 3423 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 3424 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 3425 iq->intr_idx = intr_idx; 3426 iq->cong_drop = cong; 3427 } 3428 3429 static inline void 3430 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 3431 { 3432 struct sge_params *sp = &sc->params.sge; 3433 3434 fl->qsize = qsize; 3435 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3436 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 3437 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3438 if (sc->flags & BUF_PACKING_OK && 3439 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 3440 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 3441 fl->flags |= FL_BUF_PACKING; 3442 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING); 3443 fl->safe_zidx = sc->sge.safe_zidx; 3444 if (fl->flags & FL_BUF_PACKING) { 3445 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3446 fl->buf_boundary = sp->pack_boundary; 3447 } else { 3448 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3449 fl->buf_boundary = 16; 3450 } 3451 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3452 fl->buf_boundary = sp->pad_boundary; 3453 } 3454 3455 static inline void 3456 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 3457 uint8_t tx_chan, struct sge_iq *iq, char *name) 3458 { 3459 KASSERT(eqtype >= EQ_CTRL && eqtype <= EQ_OFLD, 3460 ("%s: bad qtype %d", __func__, eqtype)); 3461 3462 eq->type = eqtype; 3463 eq->tx_chan = tx_chan; 3464 eq->iq = iq; 3465 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3466 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 3467 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3468 } 3469 3470 int 3471 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 3472 bus_dmamap_t *map, bus_addr_t *pa, void **va) 3473 { 3474 int rc; 3475 3476 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 3477 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 3478 if (rc != 0) { 3479 CH_ERR(sc, "cannot allocate DMA tag: %d\n", rc); 3480 goto done; 3481 } 3482 3483 rc = bus_dmamem_alloc(*tag, va, 3484 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3485 if (rc != 0) { 3486 CH_ERR(sc, "cannot allocate DMA memory: %d\n", rc); 3487 goto done; 3488 } 3489 3490 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3491 if (rc != 0) { 3492 CH_ERR(sc, "cannot load DMA map: %d\n", rc); 3493 goto done; 3494 } 3495 done: 3496 if (rc) 3497 free_ring(sc, *tag, *map, *pa, *va); 3498 3499 return (rc); 3500 } 3501 3502 int 3503 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3504 bus_addr_t pa, void *va) 3505 { 3506 if (pa) 3507 bus_dmamap_unload(tag, map); 3508 if (va) 3509 bus_dmamem_free(tag, va, map); 3510 if (tag) 3511 bus_dma_tag_destroy(tag); 3512 3513 return (0); 3514 } 3515 3516 /* 3517 * Allocates the software resources (mainly memory and sysctl nodes) for an 3518 * ingress queue and an optional freelist. 3519 * 3520 * Sets IQ_SW_ALLOCATED and returns 0 on success. 3521 */ 3522 static int 3523 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3524 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 3525 { 3526 int rc; 3527 size_t len; 3528 struct adapter *sc = vi->adapter; 3529 3530 MPASS(!(iq->flags & IQ_SW_ALLOCATED)); 3531 3532 len = iq->qsize * IQ_ESIZE; 3533 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3534 (void **)&iq->desc); 3535 if (rc != 0) 3536 return (rc); 3537 3538 if (fl) { 3539 len = fl->qsize * EQ_ESIZE; 3540 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3541 &fl->ba, (void **)&fl->desc); 3542 if (rc) { 3543 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, 3544 iq->desc); 3545 return (rc); 3546 } 3547 3548 /* Allocate space for one software descriptor per buffer. */ 3549 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), 3550 M_CXGBE, M_ZERO | M_WAITOK); 3551 3552 add_fl_sysctls(sc, ctx, oid, fl); 3553 iq->flags |= IQ_HAS_FL; 3554 } 3555 add_iq_sysctls(ctx, oid, iq); 3556 iq->flags |= IQ_SW_ALLOCATED; 3557 3558 return (0); 3559 } 3560 3561 /* 3562 * Frees all software resources (memory and locks) associated with an ingress 3563 * queue and an optional freelist. 3564 */ 3565 static void 3566 free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3567 { 3568 MPASS(iq->flags & IQ_SW_ALLOCATED); 3569 3570 if (fl) { 3571 MPASS(iq->flags & IQ_HAS_FL); 3572 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc); 3573 free_fl_buffers(sc, fl); 3574 free(fl->sdesc, M_CXGBE); 3575 mtx_destroy(&fl->fl_lock); 3576 bzero(fl, sizeof(*fl)); 3577 } 3578 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3579 bzero(iq, sizeof(*iq)); 3580 } 3581 3582 /* 3583 * Allocates a hardware ingress queue and an optional freelist that will be 3584 * associated with it. 3585 * 3586 * Returns errno on failure. Resources allocated up to that point may still be 3587 * allocated. Caller is responsible for cleanup in case this function fails. 3588 */ 3589 static int 3590 alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3591 { 3592 int rc, cntxt_id, cong_map; 3593 struct fw_iq_cmd c; 3594 struct adapter *sc = vi->adapter; 3595 struct port_info *pi = vi->pi; 3596 __be32 v = 0; 3597 3598 MPASS (!(iq->flags & IQ_HW_ALLOCATED)); 3599 3600 bzero(&c, sizeof(c)); 3601 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3602 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3603 V_FW_IQ_CMD_VFN(0)); 3604 3605 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3606 FW_LEN16(c)); 3607 3608 /* Special handling for firmware event queue */ 3609 if (iq == &sc->sge.fwq) 3610 v |= F_FW_IQ_CMD_IQASYNCH; 3611 3612 if (iq->intr_idx < 0) { 3613 /* Forwarded interrupts, all headed to fwq */ 3614 v |= F_FW_IQ_CMD_IQANDST; 3615 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3616 } else { 3617 KASSERT(iq->intr_idx < sc->intr_count, 3618 ("%s: invalid direct intr_idx %d", __func__, iq->intr_idx)); 3619 v |= V_FW_IQ_CMD_IQANDSTINDEX(iq->intr_idx); 3620 } 3621 3622 bzero(iq->desc, iq->qsize * IQ_ESIZE); 3623 c.type_to_iqandstindex = htobe32(v | 3624 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3625 V_FW_IQ_CMD_VIID(vi->viid) | 3626 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3627 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 3628 F_FW_IQ_CMD_IQGTSMODE | 3629 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3630 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3631 c.iqsize = htobe16(iq->qsize); 3632 c.iqaddr = htobe64(iq->ba); 3633 c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_IQTYPE(iq->qtype)); 3634 if (iq->cong_drop != -1) { 3635 cong_map = iq->qtype == IQ_ETH ? pi->rx_e_chan_map : 0; 3636 c.iqns_to_fl0congen |= htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3637 } 3638 3639 if (fl) { 3640 bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len); 3641 c.iqns_to_fl0congen |= 3642 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3643 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3644 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3645 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3646 0)); 3647 if (iq->cong_drop != -1) { 3648 c.iqns_to_fl0congen |= 3649 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) | 3650 F_FW_IQ_CMD_FL0CONGCIF | 3651 F_FW_IQ_CMD_FL0CONGEN); 3652 } 3653 c.fl0dcaen_to_fl0cidxfthresh = 3654 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3655 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 3656 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3657 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3658 c.fl0size = htobe16(fl->qsize); 3659 c.fl0addr = htobe64(fl->ba); 3660 } 3661 3662 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3663 if (rc != 0) { 3664 CH_ERR(sc, "failed to create hw ingress queue: %d\n", rc); 3665 return (rc); 3666 } 3667 3668 iq->cidx = 0; 3669 iq->gen = F_RSPD_GEN; 3670 iq->cntxt_id = be16toh(c.iqid); 3671 iq->abs_id = be16toh(c.physiqid); 3672 3673 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3674 if (cntxt_id >= sc->sge.iqmap_sz) { 3675 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3676 cntxt_id, sc->sge.iqmap_sz - 1); 3677 } 3678 sc->sge.iqmap[cntxt_id] = iq; 3679 3680 if (fl) { 3681 u_int qid; 3682 #ifdef INVARIANTS 3683 int i; 3684 3685 MPASS(!(fl->flags & FL_BUF_RESUME)); 3686 for (i = 0; i < fl->sidx * 8; i++) 3687 MPASS(fl->sdesc[i].cl == NULL); 3688 #endif 3689 fl->cntxt_id = be16toh(c.fl0id); 3690 fl->pidx = fl->cidx = fl->hw_cidx = fl->dbidx = 0; 3691 fl->rx_offset = 0; 3692 fl->flags &= ~(FL_STARVING | FL_DOOMED); 3693 3694 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3695 if (cntxt_id >= sc->sge.eqmap_sz) { 3696 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3697 __func__, cntxt_id, sc->sge.eqmap_sz - 1); 3698 } 3699 sc->sge.eqmap[cntxt_id] = (void *)fl; 3700 3701 qid = fl->cntxt_id; 3702 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3703 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3704 uint32_t mask = (1 << s_qpp) - 1; 3705 volatile uint8_t *udb; 3706 3707 udb = sc->udbs_base + UDBS_DB_OFFSET; 3708 udb += (qid >> s_qpp) << PAGE_SHIFT; 3709 qid &= mask; 3710 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3711 udb += qid << UDBS_SEG_SHIFT; 3712 qid = 0; 3713 } 3714 fl->udb = (volatile void *)udb; 3715 } 3716 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3717 3718 FL_LOCK(fl); 3719 /* Enough to make sure the SGE doesn't think it's starved */ 3720 refill_fl(sc, fl, fl->lowat); 3721 FL_UNLOCK(fl); 3722 } 3723 3724 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && 3725 iq->cong_drop != -1) { 3726 t4_sge_set_conm_context(sc, iq->cntxt_id, iq->cong_drop, 3727 cong_map); 3728 } 3729 3730 /* Enable IQ interrupts */ 3731 atomic_store_rel_int(&iq->state, IQS_IDLE); 3732 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3733 V_INGRESSQID(iq->cntxt_id)); 3734 3735 iq->flags |= IQ_HW_ALLOCATED; 3736 3737 return (0); 3738 } 3739 3740 static int 3741 free_iq_fl_hwq(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3742 { 3743 int rc; 3744 3745 MPASS(iq->flags & IQ_HW_ALLOCATED); 3746 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 3747 iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff); 3748 if (rc != 0) { 3749 CH_ERR(sc, "failed to free iq %p: %d\n", iq, rc); 3750 return (rc); 3751 } 3752 iq->flags &= ~IQ_HW_ALLOCATED; 3753 3754 return (0); 3755 } 3756 3757 static void 3758 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3759 struct sge_iq *iq) 3760 { 3761 struct sysctl_oid_list *children; 3762 3763 if (ctx == NULL || oid == NULL) 3764 return; 3765 3766 children = SYSCTL_CHILDREN(oid); 3767 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3768 "bus address of descriptor ring"); 3769 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3770 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3771 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3772 &iq->abs_id, 0, "absolute id of the queue"); 3773 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3774 &iq->cntxt_id, 0, "SGE context id of the queue"); 3775 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx, 3776 0, "consumer index"); 3777 } 3778 3779 static void 3780 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3781 struct sysctl_oid *oid, struct sge_fl *fl) 3782 { 3783 struct sysctl_oid_list *children; 3784 3785 if (ctx == NULL || oid == NULL) 3786 return; 3787 3788 children = SYSCTL_CHILDREN(oid); 3789 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 3790 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 3791 children = SYSCTL_CHILDREN(oid); 3792 3793 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3794 &fl->ba, "bus address of descriptor ring"); 3795 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3796 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3797 "desc ring size in bytes"); 3798 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3799 &fl->cntxt_id, 0, "SGE context id of the freelist"); 3800 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3801 fl_pad ? 1 : 0, "padding enabled"); 3802 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3803 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3804 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3805 0, "consumer index"); 3806 if (fl->flags & FL_BUF_PACKING) { 3807 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3808 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3809 } 3810 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3811 0, "producer index"); 3812 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3813 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3814 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3815 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3816 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3817 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3818 } 3819 3820 /* 3821 * Idempotent. 3822 */ 3823 static int 3824 alloc_fwq(struct adapter *sc) 3825 { 3826 int rc, intr_idx; 3827 struct sge_iq *fwq = &sc->sge.fwq; 3828 struct vi_info *vi = &sc->port[0]->vi[0]; 3829 3830 if (!(fwq->flags & IQ_SW_ALLOCATED)) { 3831 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3832 3833 if (sc->flags & IS_VF) 3834 intr_idx = 0; 3835 else 3836 intr_idx = sc->intr_count > 1 ? 1 : 0; 3837 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, intr_idx, -1, IQ_OTHER); 3838 rc = alloc_iq_fl(vi, fwq, NULL, &sc->ctx, sc->fwq_oid); 3839 if (rc != 0) { 3840 CH_ERR(sc, "failed to allocate fwq: %d\n", rc); 3841 return (rc); 3842 } 3843 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3844 } 3845 3846 if (!(fwq->flags & IQ_HW_ALLOCATED)) { 3847 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3848 3849 rc = alloc_iq_fl_hwq(vi, fwq, NULL); 3850 if (rc != 0) { 3851 CH_ERR(sc, "failed to create hw fwq: %d\n", rc); 3852 return (rc); 3853 } 3854 MPASS(fwq->flags & IQ_HW_ALLOCATED); 3855 } 3856 3857 return (0); 3858 } 3859 3860 /* 3861 * Idempotent. 3862 */ 3863 static void 3864 free_fwq(struct adapter *sc) 3865 { 3866 struct sge_iq *fwq = &sc->sge.fwq; 3867 3868 if (fwq->flags & IQ_HW_ALLOCATED) { 3869 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3870 free_iq_fl_hwq(sc, fwq, NULL); 3871 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3872 } 3873 3874 if (fwq->flags & IQ_SW_ALLOCATED) { 3875 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3876 free_iq_fl(sc, fwq, NULL); 3877 MPASS(!(fwq->flags & IQ_SW_ALLOCATED)); 3878 } 3879 } 3880 3881 /* 3882 * Idempotent. 3883 */ 3884 static int 3885 alloc_ctrlq(struct adapter *sc, int idx) 3886 { 3887 int rc; 3888 char name[16]; 3889 struct sysctl_oid *oid; 3890 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3891 3892 MPASS(idx < sc->params.nports); 3893 3894 if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) { 3895 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3896 3897 snprintf(name, sizeof(name), "%d", idx); 3898 oid = SYSCTL_ADD_NODE(&sc->ctx, SYSCTL_CHILDREN(sc->ctrlq_oid), 3899 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3900 "ctrl queue"); 3901 3902 snprintf(name, sizeof(name), "%s ctrlq%d", 3903 device_get_nameunit(sc->dev), idx); 3904 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, 3905 sc->port[idx]->tx_chan, &sc->sge.fwq, name); 3906 rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid); 3907 if (rc != 0) { 3908 CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc); 3909 sysctl_remove_oid(oid, 1, 1); 3910 return (rc); 3911 } 3912 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3913 } 3914 3915 if (!(ctrlq->eq.flags & EQ_HW_ALLOCATED)) { 3916 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3917 3918 rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq); 3919 if (rc != 0) { 3920 CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc); 3921 return (rc); 3922 } 3923 MPASS(ctrlq->eq.flags & EQ_HW_ALLOCATED); 3924 } 3925 3926 return (0); 3927 } 3928 3929 /* 3930 * Idempotent. 3931 */ 3932 static void 3933 free_ctrlq(struct adapter *sc, int idx) 3934 { 3935 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3936 3937 if (ctrlq->eq.flags & EQ_HW_ALLOCATED) { 3938 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3939 free_eq_hwq(sc, NULL, &ctrlq->eq); 3940 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3941 } 3942 3943 if (ctrlq->eq.flags & EQ_SW_ALLOCATED) { 3944 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3945 free_wrq(sc, ctrlq); 3946 MPASS(!(ctrlq->eq.flags & EQ_SW_ALLOCATED)); 3947 } 3948 } 3949 3950 int 3951 t4_sge_set_conm_context(struct adapter *sc, int cntxt_id, int cong_drop, 3952 int cong_map) 3953 { 3954 const int cng_ch_bits_log = sc->chip_params->cng_ch_bits_log; 3955 uint32_t param, val; 3956 uint16_t ch_map; 3957 int cong_mode, rc, i; 3958 3959 if (chip_id(sc) < CHELSIO_T5) 3960 return (ENOTSUP); 3961 3962 /* Convert the driver knob to the mode understood by the firmware. */ 3963 switch (cong_drop) { 3964 case -1: 3965 cong_mode = X_CONMCTXT_CNGTPMODE_DISABLE; 3966 break; 3967 case 0: 3968 cong_mode = X_CONMCTXT_CNGTPMODE_CHANNEL; 3969 break; 3970 case 1: 3971 cong_mode = X_CONMCTXT_CNGTPMODE_QUEUE; 3972 break; 3973 case 2: 3974 cong_mode = X_CONMCTXT_CNGTPMODE_BOTH; 3975 break; 3976 default: 3977 MPASS(0); 3978 CH_ERR(sc, "cong_drop = %d is invalid (ingress queue %d).\n", 3979 cong_drop, cntxt_id); 3980 return (EINVAL); 3981 } 3982 3983 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3984 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3985 V_FW_PARAMS_PARAM_YZ(cntxt_id); 3986 val = V_CONMCTXT_CNGTPMODE(cong_mode); 3987 if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL || 3988 cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) { 3989 for (i = 0, ch_map = 0; i < 4; i++) { 3990 if (cong_map & (1 << i)) 3991 ch_map |= 1 << (i << cng_ch_bits_log); 3992 } 3993 val |= V_CONMCTXT_CNGCHMAP(ch_map); 3994 } 3995 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3996 if (rc != 0) { 3997 CH_ERR(sc, "failed to set congestion manager context " 3998 "for ingress queue %d: %d\n", cntxt_id, rc); 3999 } 4000 4001 return (rc); 4002 } 4003 4004 /* 4005 * Idempotent. 4006 */ 4007 static int 4008 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx, 4009 int maxp) 4010 { 4011 int rc; 4012 struct adapter *sc = vi->adapter; 4013 struct ifnet *ifp = vi->ifp; 4014 struct sysctl_oid *oid; 4015 char name[16]; 4016 4017 if (!(rxq->iq.flags & IQ_SW_ALLOCATED)) { 4018 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4019 #if defined(INET) || defined(INET6) 4020 rc = tcp_lro_init_args(&rxq->lro, ifp, lro_entries, lro_mbufs); 4021 if (rc != 0) 4022 return (rc); 4023 MPASS(rxq->lro.ifp == ifp); /* also indicates LRO init'ed */ 4024 #endif 4025 rxq->ifp = ifp; 4026 4027 snprintf(name, sizeof(name), "%d", idx); 4028 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->rxq_oid), 4029 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 4030 "rx queue"); 4031 4032 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq, 4033 intr_idx, cong_drop, IQ_ETH); 4034 #if defined(INET) || defined(INET6) 4035 if (ifp->if_capenable & IFCAP_LRO) 4036 rxq->iq.flags |= IQ_LRO_ENABLED; 4037 #endif 4038 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 4039 rxq->iq.flags |= IQ_RX_TIMESTAMP; 4040 snprintf(name, sizeof(name), "%s rxq%d-fl", 4041 device_get_nameunit(vi->dev), idx); 4042 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 4043 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, &vi->ctx, oid); 4044 if (rc != 0) { 4045 CH_ERR(vi, "failed to allocate rxq%d: %d\n", idx, rc); 4046 sysctl_remove_oid(oid, 1, 1); 4047 #if defined(INET) || defined(INET6) 4048 tcp_lro_free(&rxq->lro); 4049 rxq->lro.ifp = NULL; 4050 #endif 4051 return (rc); 4052 } 4053 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4054 add_rxq_sysctls(&vi->ctx, oid, rxq); 4055 } 4056 4057 if (!(rxq->iq.flags & IQ_HW_ALLOCATED)) { 4058 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4059 rc = alloc_iq_fl_hwq(vi, &rxq->iq, &rxq->fl); 4060 if (rc != 0) { 4061 CH_ERR(vi, "failed to create hw rxq%d: %d\n", idx, rc); 4062 return (rc); 4063 } 4064 MPASS(rxq->iq.flags & IQ_HW_ALLOCATED); 4065 4066 if (idx == 0) 4067 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 4068 else 4069 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 4070 ("iq_base mismatch")); 4071 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 4072 ("PF with non-zero iq_base")); 4073 4074 /* 4075 * The freelist is just barely above the starvation threshold 4076 * right now, fill it up a bit more. 4077 */ 4078 FL_LOCK(&rxq->fl); 4079 refill_fl(sc, &rxq->fl, 128); 4080 FL_UNLOCK(&rxq->fl); 4081 } 4082 4083 return (0); 4084 } 4085 4086 /* 4087 * Idempotent. 4088 */ 4089 static void 4090 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 4091 { 4092 if (rxq->iq.flags & IQ_HW_ALLOCATED) { 4093 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4094 free_iq_fl_hwq(vi->adapter, &rxq->iq, &rxq->fl); 4095 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4096 } 4097 4098 if (rxq->iq.flags & IQ_SW_ALLOCATED) { 4099 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4100 #if defined(INET) || defined(INET6) 4101 tcp_lro_free(&rxq->lro); 4102 #endif 4103 free_iq_fl(vi->adapter, &rxq->iq, &rxq->fl); 4104 MPASS(!(rxq->iq.flags & IQ_SW_ALLOCATED)); 4105 bzero(rxq, sizeof(*rxq)); 4106 } 4107 } 4108 4109 static void 4110 add_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4111 struct sge_rxq *rxq) 4112 { 4113 struct sysctl_oid_list *children; 4114 4115 if (ctx == NULL || oid == NULL) 4116 return; 4117 4118 children = SYSCTL_CHILDREN(oid); 4119 #if defined(INET) || defined(INET6) 4120 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 4121 &rxq->lro.lro_queued, 0, NULL); 4122 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 4123 &rxq->lro.lro_flushed, 0, NULL); 4124 #endif 4125 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 4126 &rxq->rxcsum, "# of times hardware assisted with checksum"); 4127 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD, 4128 &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag"); 4129 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_rxcsum", CTLFLAG_RD, 4130 &rxq->vxlan_rxcsum, 4131 "# of times hardware assisted with inner checksum (VXLAN)"); 4132 } 4133 4134 #ifdef TCP_OFFLOAD 4135 /* 4136 * Idempotent. 4137 */ 4138 static int 4139 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, int idx, 4140 int intr_idx, int maxp) 4141 { 4142 int rc; 4143 struct adapter *sc = vi->adapter; 4144 struct sysctl_oid *oid; 4145 char name[16]; 4146 4147 if (!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)) { 4148 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4149 4150 snprintf(name, sizeof(name), "%d", idx); 4151 oid = SYSCTL_ADD_NODE(&vi->ctx, 4152 SYSCTL_CHILDREN(vi->ofld_rxq_oid), OID_AUTO, name, 4153 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload rx queue"); 4154 4155 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 4156 vi->qsize_rxq, intr_idx, ofld_cong_drop, IQ_OFLD); 4157 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 4158 device_get_nameunit(vi->dev), idx); 4159 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 4160 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, &vi->ctx, 4161 oid); 4162 if (rc != 0) { 4163 CH_ERR(vi, "failed to allocate ofld_rxq%d: %d\n", idx, 4164 rc); 4165 sysctl_remove_oid(oid, 1, 1); 4166 return (rc); 4167 } 4168 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4169 ofld_rxq->rx_iscsi_ddp_setup_ok = counter_u64_alloc(M_WAITOK); 4170 ofld_rxq->rx_iscsi_ddp_setup_error = 4171 counter_u64_alloc(M_WAITOK); 4172 add_ofld_rxq_sysctls(&vi->ctx, oid, ofld_rxq); 4173 } 4174 4175 if (!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)) { 4176 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4177 rc = alloc_iq_fl_hwq(vi, &ofld_rxq->iq, &ofld_rxq->fl); 4178 if (rc != 0) { 4179 CH_ERR(vi, "failed to create hw ofld_rxq%d: %d\n", idx, 4180 rc); 4181 return (rc); 4182 } 4183 MPASS(ofld_rxq->iq.flags & IQ_HW_ALLOCATED); 4184 } 4185 return (rc); 4186 } 4187 4188 /* 4189 * Idempotent. 4190 */ 4191 static void 4192 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 4193 { 4194 if (ofld_rxq->iq.flags & IQ_HW_ALLOCATED) { 4195 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4196 free_iq_fl_hwq(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4197 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4198 } 4199 4200 if (ofld_rxq->iq.flags & IQ_SW_ALLOCATED) { 4201 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4202 free_iq_fl(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4203 MPASS(!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)); 4204 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_ok); 4205 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_error); 4206 bzero(ofld_rxq, sizeof(*ofld_rxq)); 4207 } 4208 } 4209 4210 static void 4211 add_ofld_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4212 struct sge_ofld_rxq *ofld_rxq) 4213 { 4214 struct sysctl_oid_list *children; 4215 4216 if (ctx == NULL || oid == NULL) 4217 return; 4218 4219 children = SYSCTL_CHILDREN(oid); 4220 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4221 "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records, 4222 "# of TOE TLS records received"); 4223 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4224 "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets, 4225 "# of payload octets in received TOE TLS records"); 4226 4227 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "iscsi", 4228 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE iSCSI statistics"); 4229 children = SYSCTL_CHILDREN(oid); 4230 4231 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_ok", 4232 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_ok, 4233 "# of times DDP buffer was setup successfully."); 4234 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_error", 4235 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_error, 4236 "# of times DDP buffer setup failed."); 4237 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_octets", 4238 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_octets, 0, 4239 "# of octets placed directly"); 4240 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_pdus", 4241 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_pdus, 0, 4242 "# of PDUs with data placed directly."); 4243 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_octets", 4244 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_octets, 0, 4245 "# of data octets delivered in freelist"); 4246 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_pdus", 4247 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_pdus, 0, 4248 "# of PDUs with data delivered in freelist"); 4249 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "padding_errors", 4250 CTLFLAG_RD, &ofld_rxq->rx_iscsi_padding_errors, 0, 4251 "# of PDUs with invalid padding"); 4252 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "header_digest_errors", 4253 CTLFLAG_RD, &ofld_rxq->rx_iscsi_header_digest_errors, 0, 4254 "# of PDUs with invalid header digests"); 4255 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "data_digest_errors", 4256 CTLFLAG_RD, &ofld_rxq->rx_iscsi_data_digest_errors, 0, 4257 "# of PDUs with invalid data digests"); 4258 } 4259 #endif 4260 4261 /* 4262 * Returns a reasonable automatic cidx flush threshold for a given queue size. 4263 */ 4264 static u_int 4265 qsize_to_fthresh(int qsize) 4266 { 4267 u_int fthresh; 4268 4269 while (!powerof2(qsize)) 4270 qsize++; 4271 fthresh = ilog2(qsize); 4272 if (fthresh > X_CIDXFLUSHTHRESH_128) 4273 fthresh = X_CIDXFLUSHTHRESH_128; 4274 4275 return (fthresh); 4276 } 4277 4278 static int 4279 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 4280 { 4281 int rc, cntxt_id; 4282 struct fw_eq_ctrl_cmd c; 4283 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4284 4285 bzero(&c, sizeof(c)); 4286 4287 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 4288 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 4289 V_FW_EQ_CTRL_CMD_VFN(0)); 4290 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 4291 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 4292 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 4293 c.physeqid_pkd = htobe32(0); 4294 c.fetchszm_to_iqid = 4295 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4296 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 4297 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 4298 c.dcaen_to_eqsize = 4299 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4300 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4301 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4302 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4303 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 4304 c.eqaddr = htobe64(eq->ba); 4305 4306 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4307 if (rc != 0) { 4308 CH_ERR(sc, "failed to create hw ctrlq for tx_chan %d: %d\n", 4309 eq->tx_chan, rc); 4310 return (rc); 4311 } 4312 4313 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 4314 eq->abs_id = G_FW_EQ_CTRL_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4315 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4316 if (cntxt_id >= sc->sge.eqmap_sz) 4317 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4318 cntxt_id, sc->sge.eqmap_sz - 1); 4319 sc->sge.eqmap[cntxt_id] = eq; 4320 4321 return (rc); 4322 } 4323 4324 static int 4325 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4326 { 4327 int rc, cntxt_id; 4328 struct fw_eq_eth_cmd c; 4329 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4330 4331 bzero(&c, sizeof(c)); 4332 4333 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 4334 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 4335 V_FW_EQ_ETH_CMD_VFN(0)); 4336 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 4337 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 4338 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 4339 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 4340 c.fetchszm_to_iqid = 4341 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 4342 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 4343 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 4344 c.dcaen_to_eqsize = 4345 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4346 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4347 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4348 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 4349 c.eqaddr = htobe64(eq->ba); 4350 4351 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4352 if (rc != 0) { 4353 device_printf(vi->dev, 4354 "failed to create Ethernet egress queue: %d\n", rc); 4355 return (rc); 4356 } 4357 4358 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 4359 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4360 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4361 if (cntxt_id >= sc->sge.eqmap_sz) 4362 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4363 cntxt_id, sc->sge.eqmap_sz - 1); 4364 sc->sge.eqmap[cntxt_id] = eq; 4365 4366 return (rc); 4367 } 4368 4369 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4370 static int 4371 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4372 { 4373 int rc, cntxt_id; 4374 struct fw_eq_ofld_cmd c; 4375 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4376 4377 bzero(&c, sizeof(c)); 4378 4379 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 4380 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 4381 V_FW_EQ_OFLD_CMD_VFN(0)); 4382 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 4383 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 4384 c.fetchszm_to_iqid = 4385 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4386 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 4387 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 4388 c.dcaen_to_eqsize = 4389 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4390 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4391 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4392 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4393 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 4394 c.eqaddr = htobe64(eq->ba); 4395 4396 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4397 if (rc != 0) { 4398 device_printf(vi->dev, 4399 "failed to create egress queue for TCP offload: %d\n", rc); 4400 return (rc); 4401 } 4402 4403 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 4404 eq->abs_id = G_FW_EQ_OFLD_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4405 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4406 if (cntxt_id >= sc->sge.eqmap_sz) 4407 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4408 cntxt_id, sc->sge.eqmap_sz - 1); 4409 sc->sge.eqmap[cntxt_id] = eq; 4410 4411 return (rc); 4412 } 4413 #endif 4414 4415 /* SW only */ 4416 static int 4417 alloc_eq(struct adapter *sc, struct sge_eq *eq, struct sysctl_ctx_list *ctx, 4418 struct sysctl_oid *oid) 4419 { 4420 int rc, qsize; 4421 size_t len; 4422 4423 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4424 4425 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4426 len = qsize * EQ_ESIZE; 4427 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba, 4428 (void **)&eq->desc); 4429 if (rc) 4430 return (rc); 4431 if (ctx != NULL && oid != NULL) 4432 add_eq_sysctls(sc, ctx, oid, eq); 4433 eq->flags |= EQ_SW_ALLOCATED; 4434 4435 return (0); 4436 } 4437 4438 /* SW only */ 4439 static void 4440 free_eq(struct adapter *sc, struct sge_eq *eq) 4441 { 4442 MPASS(eq->flags & EQ_SW_ALLOCATED); 4443 if (eq->type == EQ_ETH) 4444 MPASS(eq->pidx == eq->cidx); 4445 4446 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 4447 mtx_destroy(&eq->eq_lock); 4448 bzero(eq, sizeof(*eq)); 4449 } 4450 4451 static void 4452 add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 4453 struct sysctl_oid *oid, struct sge_eq *eq) 4454 { 4455 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4456 4457 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &eq->ba, 4458 "bus address of descriptor ring"); 4459 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4460 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4461 "desc ring size in bytes"); 4462 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4463 &eq->abs_id, 0, "absolute id of the queue"); 4464 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4465 &eq->cntxt_id, 0, "SGE context id of the queue"); 4466 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &eq->cidx, 4467 0, "consumer index"); 4468 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &eq->pidx, 4469 0, "producer index"); 4470 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4471 eq->sidx, "status page index"); 4472 } 4473 4474 static int 4475 alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4476 { 4477 int rc; 4478 4479 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4480 4481 eq->iqid = eq->iq->cntxt_id; 4482 eq->pidx = eq->cidx = eq->dbidx = 0; 4483 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 4484 eq->equeqidx = 0; 4485 eq->doorbells = sc->doorbells; 4486 bzero(eq->desc, eq->sidx * EQ_ESIZE + sc->params.sge.spg_len); 4487 4488 switch (eq->type) { 4489 case EQ_CTRL: 4490 rc = ctrl_eq_alloc(sc, eq); 4491 break; 4492 4493 case EQ_ETH: 4494 rc = eth_eq_alloc(sc, vi, eq); 4495 break; 4496 4497 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4498 case EQ_OFLD: 4499 rc = ofld_eq_alloc(sc, vi, eq); 4500 break; 4501 #endif 4502 4503 default: 4504 panic("%s: invalid eq type %d.", __func__, eq->type); 4505 } 4506 if (rc != 0) { 4507 CH_ERR(sc, "failed to allocate egress queue(%d): %d\n", 4508 eq->type, rc); 4509 return (rc); 4510 } 4511 4512 if (isset(&eq->doorbells, DOORBELL_UDB) || 4513 isset(&eq->doorbells, DOORBELL_UDBWC) || 4514 isset(&eq->doorbells, DOORBELL_WCWR)) { 4515 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 4516 uint32_t mask = (1 << s_qpp) - 1; 4517 volatile uint8_t *udb; 4518 4519 udb = sc->udbs_base + UDBS_DB_OFFSET; 4520 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 4521 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 4522 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 4523 clrbit(&eq->doorbells, DOORBELL_WCWR); 4524 else { 4525 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 4526 eq->udb_qid = 0; 4527 } 4528 eq->udb = (volatile void *)udb; 4529 } 4530 4531 eq->flags |= EQ_HW_ALLOCATED; 4532 return (0); 4533 } 4534 4535 static int 4536 free_eq_hwq(struct adapter *sc, struct vi_info *vi __unused, struct sge_eq *eq) 4537 { 4538 int rc; 4539 4540 MPASS(eq->flags & EQ_HW_ALLOCATED); 4541 4542 switch (eq->type) { 4543 case EQ_CTRL: 4544 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4545 break; 4546 case EQ_ETH: 4547 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4548 break; 4549 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4550 case EQ_OFLD: 4551 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4552 break; 4553 #endif 4554 default: 4555 panic("%s: invalid eq type %d.", __func__, eq->type); 4556 } 4557 if (rc != 0) { 4558 CH_ERR(sc, "failed to free eq (type %d): %d\n", eq->type, rc); 4559 return (rc); 4560 } 4561 eq->flags &= ~EQ_HW_ALLOCATED; 4562 4563 return (0); 4564 } 4565 4566 static int 4567 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 4568 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 4569 { 4570 struct sge_eq *eq = &wrq->eq; 4571 int rc; 4572 4573 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4574 4575 rc = alloc_eq(sc, eq, ctx, oid); 4576 if (rc) 4577 return (rc); 4578 MPASS(eq->flags & EQ_SW_ALLOCATED); 4579 /* Can't fail after this. */ 4580 4581 wrq->adapter = sc; 4582 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 4583 TAILQ_INIT(&wrq->incomplete_wrs); 4584 STAILQ_INIT(&wrq->wr_list); 4585 wrq->nwr_pending = 0; 4586 wrq->ndesc_needed = 0; 4587 add_wrq_sysctls(ctx, oid, wrq); 4588 4589 return (0); 4590 } 4591 4592 static void 4593 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4594 { 4595 free_eq(sc, &wrq->eq); 4596 MPASS(wrq->nwr_pending == 0); 4597 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 4598 MPASS(STAILQ_EMPTY(&wrq->wr_list)); 4599 bzero(wrq, sizeof(*wrq)); 4600 } 4601 4602 static void 4603 add_wrq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4604 struct sge_wrq *wrq) 4605 { 4606 struct sysctl_oid_list *children; 4607 4608 if (ctx == NULL || oid == NULL) 4609 return; 4610 4611 children = SYSCTL_CHILDREN(oid); 4612 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 4613 &wrq->tx_wrs_direct, "# of work requests (direct)"); 4614 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 4615 &wrq->tx_wrs_copied, "# of work requests (copied)"); 4616 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 4617 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 4618 } 4619 4620 /* 4621 * Idempotent. 4622 */ 4623 static int 4624 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx) 4625 { 4626 int rc, iqidx; 4627 struct port_info *pi = vi->pi; 4628 struct adapter *sc = vi->adapter; 4629 struct sge_eq *eq = &txq->eq; 4630 struct txpkts *txp; 4631 char name[16]; 4632 struct sysctl_oid *oid; 4633 4634 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4635 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4636 4637 snprintf(name, sizeof(name), "%d", idx); 4638 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->txq_oid), 4639 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 4640 "tx queue"); 4641 4642 iqidx = vi->first_rxq + (idx % vi->nrxq); 4643 snprintf(name, sizeof(name), "%s txq%d", 4644 device_get_nameunit(vi->dev), idx); 4645 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 4646 &sc->sge.rxq[iqidx].iq, name); 4647 4648 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, 4649 can_resume_eth_tx, M_CXGBE, &eq->eq_lock, M_WAITOK); 4650 if (rc != 0) { 4651 CH_ERR(vi, "failed to allocate mp_ring for txq%d: %d\n", 4652 idx, rc); 4653 failed: 4654 sysctl_remove_oid(oid, 1, 1); 4655 return (rc); 4656 } 4657 4658 rc = alloc_eq(sc, eq, &vi->ctx, oid); 4659 if (rc) { 4660 CH_ERR(vi, "failed to allocate txq%d: %d\n", idx, rc); 4661 mp_ring_free(txq->r); 4662 goto failed; 4663 } 4664 MPASS(eq->flags & EQ_SW_ALLOCATED); 4665 /* Can't fail after this point. */ 4666 4667 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4668 txq->ifp = vi->ifp; 4669 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4670 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4671 M_ZERO | M_WAITOK); 4672 4673 add_txq_sysctls(vi, &vi->ctx, oid, txq); 4674 } 4675 4676 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4677 MPASS(eq->flags & EQ_SW_ALLOCATED); 4678 rc = alloc_eq_hwq(sc, vi, eq); 4679 if (rc != 0) { 4680 CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc); 4681 return (rc); 4682 } 4683 MPASS(eq->flags & EQ_HW_ALLOCATED); 4684 /* Can't fail after this point. */ 4685 4686 if (idx == 0) 4687 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4688 else 4689 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4690 ("eq_base mismatch")); 4691 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4692 ("PF with non-zero eq_base")); 4693 4694 txp = &txq->txp; 4695 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr); 4696 txq->txp.max_npkt = min(nitems(txp->mb), 4697 sc->params.max_pkts_per_eth_tx_pkts_wr); 4698 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF)) 4699 txq->txp.max_npkt--; 4700 4701 if (vi->flags & TX_USES_VM_WR) 4702 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4703 V_TXPKT_INTF(pi->tx_chan)); 4704 else 4705 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4706 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 4707 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4708 4709 txq->tc_idx = -1; 4710 } 4711 4712 return (0); 4713 } 4714 4715 /* 4716 * Idempotent. 4717 */ 4718 static void 4719 free_txq(struct vi_info *vi, struct sge_txq *txq) 4720 { 4721 struct adapter *sc = vi->adapter; 4722 struct sge_eq *eq = &txq->eq; 4723 4724 if (eq->flags & EQ_HW_ALLOCATED) { 4725 MPASS(eq->flags & EQ_SW_ALLOCATED); 4726 free_eq_hwq(sc, NULL, eq); 4727 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4728 } 4729 4730 if (eq->flags & EQ_SW_ALLOCATED) { 4731 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4732 sglist_free(txq->gl); 4733 free(txq->sdesc, M_CXGBE); 4734 mp_ring_free(txq->r); 4735 free_eq(sc, eq); 4736 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4737 bzero(txq, sizeof(*txq)); 4738 } 4739 } 4740 4741 static void 4742 add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx, 4743 struct sysctl_oid *oid, struct sge_txq *txq) 4744 { 4745 struct adapter *sc; 4746 struct sysctl_oid_list *children; 4747 4748 if (ctx == NULL || oid == NULL) 4749 return; 4750 4751 sc = vi->adapter; 4752 children = SYSCTL_CHILDREN(oid); 4753 4754 mp_ring_sysctls(txq->r, ctx, children); 4755 4756 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tc", 4757 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, txq - sc->sge.txq, 4758 sysctl_tc, "I", "traffic class (-1 means none)"); 4759 4760 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4761 &txq->txcsum, "# of times hardware assisted with checksum"); 4762 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD, 4763 &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag"); 4764 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4765 &txq->tso_wrs, "# of TSO work requests"); 4766 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4767 &txq->imm_wrs, "# of work requests with immediate data"); 4768 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4769 &txq->sgl_wrs, "# of work requests with direct SGL"); 4770 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4771 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4772 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_wrs", CTLFLAG_RD, 4773 &txq->txpkts0_wrs, "# of txpkts (type 0) work requests"); 4774 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_wrs", CTLFLAG_RD, 4775 &txq->txpkts1_wrs, "# of txpkts (type 1) work requests"); 4776 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_pkts", CTLFLAG_RD, 4777 &txq->txpkts0_pkts, 4778 "# of frames tx'd using type0 txpkts work requests"); 4779 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_pkts", CTLFLAG_RD, 4780 &txq->txpkts1_pkts, 4781 "# of frames tx'd using type1 txpkts work requests"); 4782 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts_flush", CTLFLAG_RD, 4783 &txq->txpkts_flush, 4784 "# of times txpkts had to be flushed out by an egress-update"); 4785 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4786 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4787 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_tso_wrs", CTLFLAG_RD, 4788 &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests"); 4789 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_txcsum", CTLFLAG_RD, 4790 &txq->vxlan_txcsum, 4791 "# of times hardware assisted with inner checksums (VXLAN)"); 4792 4793 #ifdef KERN_TLS 4794 if (is_ktls(sc)) { 4795 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_records", 4796 CTLFLAG_RD, &txq->kern_tls_records, 4797 "# of NIC TLS records transmitted"); 4798 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_short", 4799 CTLFLAG_RD, &txq->kern_tls_short, 4800 "# of short NIC TLS records transmitted"); 4801 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_partial", 4802 CTLFLAG_RD, &txq->kern_tls_partial, 4803 "# of partial NIC TLS records transmitted"); 4804 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_full", 4805 CTLFLAG_RD, &txq->kern_tls_full, 4806 "# of full NIC TLS records transmitted"); 4807 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_octets", 4808 CTLFLAG_RD, &txq->kern_tls_octets, 4809 "# of payload octets in transmitted NIC TLS records"); 4810 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste", 4811 CTLFLAG_RD, &txq->kern_tls_waste, 4812 "# of octets DMAd but not transmitted in NIC TLS records"); 4813 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_options", 4814 CTLFLAG_RD, &txq->kern_tls_options, 4815 "# of NIC TLS options-only packets transmitted"); 4816 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header", 4817 CTLFLAG_RD, &txq->kern_tls_header, 4818 "# of NIC TLS header-only packets transmitted"); 4819 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin", 4820 CTLFLAG_RD, &txq->kern_tls_fin, 4821 "# of NIC TLS FIN-only packets transmitted"); 4822 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short", 4823 CTLFLAG_RD, &txq->kern_tls_fin_short, 4824 "# of NIC TLS padded FIN packets on short TLS records"); 4825 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc", 4826 CTLFLAG_RD, &txq->kern_tls_cbc, 4827 "# of NIC TLS sessions using AES-CBC"); 4828 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_gcm", 4829 CTLFLAG_RD, &txq->kern_tls_gcm, 4830 "# of NIC TLS sessions using AES-GCM"); 4831 } 4832 #endif 4833 } 4834 4835 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4836 /* 4837 * Idempotent. 4838 */ 4839 static int 4840 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx) 4841 { 4842 struct sysctl_oid *oid; 4843 struct port_info *pi = vi->pi; 4844 struct adapter *sc = vi->adapter; 4845 struct sge_eq *eq = &ofld_txq->wrq.eq; 4846 int rc, iqidx; 4847 char name[16]; 4848 4849 MPASS(idx >= 0); 4850 MPASS(idx < vi->nofldtxq); 4851 4852 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4853 snprintf(name, sizeof(name), "%d", idx); 4854 oid = SYSCTL_ADD_NODE(&vi->ctx, 4855 SYSCTL_CHILDREN(vi->ofld_txq_oid), OID_AUTO, name, 4856 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue"); 4857 4858 snprintf(name, sizeof(name), "%s ofld_txq%d", 4859 device_get_nameunit(vi->dev), idx); 4860 if (vi->nofldrxq > 0) { 4861 iqidx = vi->first_ofld_rxq + (idx % vi->nofldrxq); 4862 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 4863 &sc->sge.ofld_rxq[iqidx].iq, name); 4864 } else { 4865 iqidx = vi->first_rxq + (idx % vi->nrxq); 4866 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 4867 &sc->sge.rxq[iqidx].iq, name); 4868 } 4869 4870 rc = alloc_wrq(sc, vi, &ofld_txq->wrq, &vi->ctx, oid); 4871 if (rc != 0) { 4872 CH_ERR(vi, "failed to allocate ofld_txq%d: %d\n", idx, 4873 rc); 4874 sysctl_remove_oid(oid, 1, 1); 4875 return (rc); 4876 } 4877 MPASS(eq->flags & EQ_SW_ALLOCATED); 4878 /* Can't fail after this point. */ 4879 4880 ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK); 4881 ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK); 4882 ofld_txq->tx_iscsi_iso_wrs = counter_u64_alloc(M_WAITOK); 4883 ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK); 4884 ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK); 4885 add_ofld_txq_sysctls(&vi->ctx, oid, ofld_txq); 4886 } 4887 4888 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4889 rc = alloc_eq_hwq(sc, vi, eq); 4890 if (rc != 0) { 4891 CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx, 4892 rc); 4893 return (rc); 4894 } 4895 MPASS(eq->flags & EQ_HW_ALLOCATED); 4896 } 4897 4898 return (0); 4899 } 4900 4901 /* 4902 * Idempotent. 4903 */ 4904 static void 4905 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq) 4906 { 4907 struct adapter *sc = vi->adapter; 4908 struct sge_eq *eq = &ofld_txq->wrq.eq; 4909 4910 if (eq->flags & EQ_HW_ALLOCATED) { 4911 MPASS(eq->flags & EQ_SW_ALLOCATED); 4912 free_eq_hwq(sc, NULL, eq); 4913 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4914 } 4915 4916 if (eq->flags & EQ_SW_ALLOCATED) { 4917 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4918 counter_u64_free(ofld_txq->tx_iscsi_pdus); 4919 counter_u64_free(ofld_txq->tx_iscsi_octets); 4920 counter_u64_free(ofld_txq->tx_iscsi_iso_wrs); 4921 counter_u64_free(ofld_txq->tx_toe_tls_records); 4922 counter_u64_free(ofld_txq->tx_toe_tls_octets); 4923 free_wrq(sc, &ofld_txq->wrq); 4924 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4925 bzero(ofld_txq, sizeof(*ofld_txq)); 4926 } 4927 } 4928 4929 static void 4930 add_ofld_txq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4931 struct sge_ofld_txq *ofld_txq) 4932 { 4933 struct sysctl_oid_list *children; 4934 4935 if (ctx == NULL || oid == NULL) 4936 return; 4937 4938 children = SYSCTL_CHILDREN(oid); 4939 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_pdus", 4940 CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus, 4941 "# of iSCSI PDUs transmitted"); 4942 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_octets", 4943 CTLFLAG_RD, &ofld_txq->tx_iscsi_octets, 4944 "# of payload octets in transmitted iSCSI PDUs"); 4945 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_iso_wrs", 4946 CTLFLAG_RD, &ofld_txq->tx_iscsi_iso_wrs, 4947 "# of iSCSI segmentation offload work requests"); 4948 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_records", 4949 CTLFLAG_RD, &ofld_txq->tx_toe_tls_records, 4950 "# of TOE TLS records transmitted"); 4951 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_octets", 4952 CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets, 4953 "# of payload octets in transmitted TOE TLS records"); 4954 } 4955 #endif 4956 4957 static void 4958 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4959 { 4960 bus_addr_t *ba = arg; 4961 4962 KASSERT(nseg == 1, 4963 ("%s meant for single segment mappings only.", __func__)); 4964 4965 *ba = error ? 0 : segs->ds_addr; 4966 } 4967 4968 static inline void 4969 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4970 { 4971 uint32_t n, v; 4972 4973 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx); 4974 MPASS(n > 0); 4975 4976 wmb(); 4977 v = fl->dbval | V_PIDX(n); 4978 if (fl->udb) 4979 *fl->udb = htole32(v); 4980 else 4981 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4982 IDXINCR(fl->dbidx, n, fl->sidx); 4983 } 4984 4985 /* 4986 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4987 * recycled do not count towards this allocation budget. 4988 * 4989 * Returns non-zero to indicate that this freelist should be added to the list 4990 * of starving freelists. 4991 */ 4992 static int 4993 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4994 { 4995 __be64 *d; 4996 struct fl_sdesc *sd; 4997 uintptr_t pa; 4998 caddr_t cl; 4999 struct rx_buf_info *rxb; 5000 struct cluster_metadata *clm; 5001 uint16_t max_pidx, zidx = fl->zidx; 5002 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 5003 5004 FL_LOCK_ASSERT_OWNED(fl); 5005 5006 /* 5007 * We always stop at the beginning of the hardware descriptor that's just 5008 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 5009 * which would mean an empty freelist to the chip. 5010 */ 5011 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 5012 if (fl->pidx == max_pidx * 8) 5013 return (0); 5014 5015 d = &fl->desc[fl->pidx]; 5016 sd = &fl->sdesc[fl->pidx]; 5017 rxb = &sc->sge.rx_buf_info[zidx]; 5018 5019 while (n > 0) { 5020 5021 if (sd->cl != NULL) { 5022 5023 if (sd->nmbuf == 0) { 5024 /* 5025 * Fast recycle without involving any atomics on 5026 * the cluster's metadata (if the cluster has 5027 * metadata). This happens when all frames 5028 * received in the cluster were small enough to 5029 * fit within a single mbuf each. 5030 */ 5031 fl->cl_fast_recycled++; 5032 goto recycled; 5033 } 5034 5035 /* 5036 * Cluster is guaranteed to have metadata. Clusters 5037 * without metadata always take the fast recycle path 5038 * when they're recycled. 5039 */ 5040 clm = cl_metadata(sd); 5041 MPASS(clm != NULL); 5042 5043 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5044 fl->cl_recycled++; 5045 counter_u64_add(extfree_rels, 1); 5046 goto recycled; 5047 } 5048 sd->cl = NULL; /* gave up my reference */ 5049 } 5050 MPASS(sd->cl == NULL); 5051 cl = uma_zalloc(rxb->zone, M_NOWAIT); 5052 if (__predict_false(cl == NULL)) { 5053 if (zidx != fl->safe_zidx) { 5054 zidx = fl->safe_zidx; 5055 rxb = &sc->sge.rx_buf_info[zidx]; 5056 cl = uma_zalloc(rxb->zone, M_NOWAIT); 5057 } 5058 if (cl == NULL) 5059 break; 5060 } 5061 fl->cl_allocated++; 5062 n--; 5063 5064 pa = pmap_kextract((vm_offset_t)cl); 5065 sd->cl = cl; 5066 sd->zidx = zidx; 5067 5068 if (fl->flags & FL_BUF_PACKING) { 5069 *d = htobe64(pa | rxb->hwidx2); 5070 sd->moff = rxb->size2; 5071 } else { 5072 *d = htobe64(pa | rxb->hwidx1); 5073 sd->moff = 0; 5074 } 5075 recycled: 5076 sd->nmbuf = 0; 5077 d++; 5078 sd++; 5079 if (__predict_false((++fl->pidx & 7) == 0)) { 5080 uint16_t pidx = fl->pidx >> 3; 5081 5082 if (__predict_false(pidx == fl->sidx)) { 5083 fl->pidx = 0; 5084 pidx = 0; 5085 sd = fl->sdesc; 5086 d = fl->desc; 5087 } 5088 if (n < 8 || pidx == max_pidx) 5089 break; 5090 5091 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 5092 ring_fl_db(sc, fl); 5093 } 5094 } 5095 5096 if ((fl->pidx >> 3) != fl->dbidx) 5097 ring_fl_db(sc, fl); 5098 5099 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 5100 } 5101 5102 /* 5103 * Attempt to refill all starving freelists. 5104 */ 5105 static void 5106 refill_sfl(void *arg) 5107 { 5108 struct adapter *sc = arg; 5109 struct sge_fl *fl, *fl_temp; 5110 5111 mtx_assert(&sc->sfl_lock, MA_OWNED); 5112 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 5113 FL_LOCK(fl); 5114 refill_fl(sc, fl, 64); 5115 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 5116 TAILQ_REMOVE(&sc->sfl, fl, link); 5117 fl->flags &= ~FL_STARVING; 5118 } 5119 FL_UNLOCK(fl); 5120 } 5121 5122 if (!TAILQ_EMPTY(&sc->sfl)) 5123 callout_schedule(&sc->sfl_callout, hz / 5); 5124 } 5125 5126 /* 5127 * Release the driver's reference on all buffers in the given freelist. Buffers 5128 * with kernel references cannot be freed and will prevent the driver from being 5129 * unloaded safely. 5130 */ 5131 void 5132 free_fl_buffers(struct adapter *sc, struct sge_fl *fl) 5133 { 5134 struct fl_sdesc *sd; 5135 struct cluster_metadata *clm; 5136 int i; 5137 5138 sd = fl->sdesc; 5139 for (i = 0; i < fl->sidx * 8; i++, sd++) { 5140 if (sd->cl == NULL) 5141 continue; 5142 5143 if (sd->nmbuf == 0) 5144 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl); 5145 else if (fl->flags & FL_BUF_PACKING) { 5146 clm = cl_metadata(sd); 5147 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5148 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, 5149 sd->cl); 5150 counter_u64_add(extfree_rels, 1); 5151 } 5152 } 5153 sd->cl = NULL; 5154 } 5155 5156 if (fl->flags & FL_BUF_RESUME) { 5157 m_freem(fl->m0); 5158 fl->flags &= ~FL_BUF_RESUME; 5159 } 5160 } 5161 5162 static inline void 5163 get_pkt_gl(struct mbuf *m, struct sglist *gl) 5164 { 5165 int rc; 5166 5167 M_ASSERTPKTHDR(m); 5168 5169 sglist_reset(gl); 5170 rc = sglist_append_mbuf(gl, m); 5171 if (__predict_false(rc != 0)) { 5172 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 5173 "with %d.", __func__, m, mbuf_nsegs(m), rc); 5174 } 5175 5176 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 5177 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 5178 mbuf_nsegs(m), gl->sg_nseg)); 5179 #if 0 /* vm_wr not readily available here. */ 5180 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr), 5181 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 5182 gl->sg_nseg, max_nsegs_allowed(m, vm_wr))); 5183 #endif 5184 } 5185 5186 /* 5187 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5188 */ 5189 static inline u_int 5190 txpkt_len16(u_int nsegs, const u_int extra) 5191 { 5192 u_int n; 5193 5194 MPASS(nsegs > 0); 5195 5196 nsegs--; /* first segment is part of ulptx_sgl */ 5197 n = extra + sizeof(struct fw_eth_tx_pkt_wr) + 5198 sizeof(struct cpl_tx_pkt_core) + 5199 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5200 5201 return (howmany(n, 16)); 5202 } 5203 5204 /* 5205 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 5206 * request header. 5207 */ 5208 static inline u_int 5209 txpkt_vm_len16(u_int nsegs, const u_int extra) 5210 { 5211 u_int n; 5212 5213 MPASS(nsegs > 0); 5214 5215 nsegs--; /* first segment is part of ulptx_sgl */ 5216 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) + 5217 sizeof(struct cpl_tx_pkt_core) + 5218 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5219 5220 return (howmany(n, 16)); 5221 } 5222 5223 static inline void 5224 calculate_mbuf_len16(struct mbuf *m, bool vm_wr) 5225 { 5226 const int lso = sizeof(struct cpl_tx_pkt_lso_core); 5227 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso); 5228 5229 if (vm_wr) { 5230 if (needs_tso(m)) 5231 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso)); 5232 else 5233 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0)); 5234 return; 5235 } 5236 5237 if (needs_tso(m)) { 5238 if (needs_vxlan_tso(m)) 5239 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso)); 5240 else 5241 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso)); 5242 } else 5243 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0)); 5244 } 5245 5246 /* 5247 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 5248 * request header. 5249 */ 5250 static inline u_int 5251 txpkts0_len16(u_int nsegs) 5252 { 5253 u_int n; 5254 5255 MPASS(nsegs > 0); 5256 5257 nsegs--; /* first segment is part of ulptx_sgl */ 5258 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 5259 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 5260 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5261 5262 return (howmany(n, 16)); 5263 } 5264 5265 /* 5266 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 5267 * request header. 5268 */ 5269 static inline u_int 5270 txpkts1_len16(void) 5271 { 5272 u_int n; 5273 5274 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 5275 5276 return (howmany(n, 16)); 5277 } 5278 5279 static inline u_int 5280 imm_payload(u_int ndesc) 5281 { 5282 u_int n; 5283 5284 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 5285 sizeof(struct cpl_tx_pkt_core); 5286 5287 return (n); 5288 } 5289 5290 static inline uint64_t 5291 csum_to_ctrl(struct adapter *sc, struct mbuf *m) 5292 { 5293 uint64_t ctrl; 5294 int csum_type, l2hlen, l3hlen; 5295 int x, y; 5296 static const int csum_types[3][2] = { 5297 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6}, 5298 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6}, 5299 {TX_CSUM_IP, 0} 5300 }; 5301 5302 M_ASSERTPKTHDR(m); 5303 5304 if (!needs_hwcsum(m)) 5305 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 5306 5307 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN); 5308 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip)); 5309 5310 if (needs_vxlan_csum(m)) { 5311 MPASS(m->m_pkthdr.l4hlen > 0); 5312 MPASS(m->m_pkthdr.l5hlen > 0); 5313 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN); 5314 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip)); 5315 5316 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen + 5317 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen + 5318 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN; 5319 l3hlen = m->m_pkthdr.inner_l3hlen; 5320 } else { 5321 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN; 5322 l3hlen = m->m_pkthdr.l3hlen; 5323 } 5324 5325 ctrl = 0; 5326 if (!needs_l3_csum(m)) 5327 ctrl |= F_TXPKT_IPCSUM_DIS; 5328 5329 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP | 5330 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP)) 5331 x = 0; /* TCP */ 5332 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP | 5333 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP)) 5334 x = 1; /* UDP */ 5335 else 5336 x = 2; 5337 5338 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP | 5339 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP)) 5340 y = 0; /* IPv4 */ 5341 else { 5342 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | 5343 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP)); 5344 y = 1; /* IPv6 */ 5345 } 5346 /* 5347 * needs_hwcsum returned true earlier so there must be some kind of 5348 * checksum to calculate. 5349 */ 5350 csum_type = csum_types[x][y]; 5351 MPASS(csum_type != 0); 5352 if (csum_type == TX_CSUM_IP) 5353 ctrl |= F_TXPKT_L4CSUM_DIS; 5354 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen); 5355 if (chip_id(sc) <= CHELSIO_T5) 5356 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen); 5357 else 5358 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen); 5359 5360 return (ctrl); 5361 } 5362 5363 static inline void * 5364 write_lso_cpl(void *cpl, struct mbuf *m0) 5365 { 5366 struct cpl_tx_pkt_lso_core *lso; 5367 uint32_t ctrl; 5368 5369 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5370 m0->m_pkthdr.l4hlen > 0, 5371 ("%s: mbuf %p needs TSO but missing header lengths", 5372 __func__, m0)); 5373 5374 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5375 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5376 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5377 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5378 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5379 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5380 ctrl |= F_LSO_IPV6; 5381 5382 lso = cpl; 5383 lso->lso_ctrl = htobe32(ctrl); 5384 lso->ipid_ofst = htobe16(0); 5385 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5386 lso->seqno_offset = htobe32(0); 5387 lso->len = htobe32(m0->m_pkthdr.len); 5388 5389 return (lso + 1); 5390 } 5391 5392 static void * 5393 write_tnl_lso_cpl(void *cpl, struct mbuf *m0) 5394 { 5395 struct cpl_tx_tnl_lso *tnl_lso = cpl; 5396 uint32_t ctrl; 5397 5398 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 && 5399 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 && 5400 m0->m_pkthdr.inner_l5hlen > 0, 5401 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths", 5402 __func__, m0)); 5403 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5404 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0, 5405 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths", 5406 __func__, m0)); 5407 5408 /* Outer headers. */ 5409 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) | 5410 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST | 5411 V_CPL_TX_TNL_LSO_ETHHDRLENOUT( 5412 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5413 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) | 5414 F_CPL_TX_TNL_LSO_IPLENSETOUT; 5415 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5416 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT; 5417 else { 5418 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT | 5419 F_CPL_TX_TNL_LSO_IPIDINCOUT; 5420 } 5421 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl); 5422 tnl_lso->IpIdOffsetOut = 0; 5423 tnl_lso->UdpLenSetOut_to_TnlHdrLen = 5424 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT | 5425 F_CPL_TX_TNL_LSO_UDPLENSETOUT | 5426 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen + 5427 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen + 5428 m0->m_pkthdr.l5hlen) | 5429 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN)); 5430 tnl_lso->r1 = 0; 5431 5432 /* Inner headers. */ 5433 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN( 5434 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) | 5435 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) | 5436 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2); 5437 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr)) 5438 ctrl |= F_CPL_TX_TNL_LSO_IPV6; 5439 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl); 5440 tnl_lso->IpIdOffset = 0; 5441 tnl_lso->IpIdSplit_to_Mss = 5442 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz)); 5443 tnl_lso->TCPSeqOffset = 0; 5444 tnl_lso->EthLenOffset_Size = 5445 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len)); 5446 5447 return (tnl_lso + 1); 5448 } 5449 5450 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */ 5451 5452 /* 5453 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 5454 * software descriptor, and advance the pidx. It is guaranteed that enough 5455 * descriptors are available. 5456 * 5457 * The return value is the # of hardware descriptors used. 5458 */ 5459 static u_int 5460 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0) 5461 { 5462 struct sge_eq *eq; 5463 struct fw_eth_tx_pkt_vm_wr *wr; 5464 struct tx_sdesc *txsd; 5465 struct cpl_tx_pkt_core *cpl; 5466 uint32_t ctrl; /* used in many unrelated places */ 5467 uint64_t ctrl1; 5468 int len16, ndesc, pktlen; 5469 caddr_t dst; 5470 5471 TXQ_LOCK_ASSERT_OWNED(txq); 5472 M_ASSERTPKTHDR(m0); 5473 5474 len16 = mbuf_len16(m0); 5475 pktlen = m0->m_pkthdr.len; 5476 ctrl = sizeof(struct cpl_tx_pkt_core); 5477 if (needs_tso(m0)) 5478 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5479 ndesc = tx_len16_to_desc(len16); 5480 5481 /* Firmware work request header */ 5482 eq = &txq->eq; 5483 wr = (void *)&eq->desc[eq->pidx]; 5484 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 5485 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5486 5487 ctrl = V_FW_WR_LEN16(len16); 5488 wr->equiq_to_len16 = htobe32(ctrl); 5489 wr->r3[0] = 0; 5490 wr->r3[1] = 0; 5491 5492 /* 5493 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 5494 * vlantci is ignored unless the ethtype is 0x8100, so it's 5495 * simpler to always copy it rather than making it 5496 * conditional. Also, it seems that we do not have to set 5497 * vlantci or fake the ethtype when doing VLAN tag insertion. 5498 */ 5499 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst); 5500 5501 if (needs_tso(m0)) { 5502 cpl = write_lso_cpl(wr + 1, m0); 5503 txq->tso_wrs++; 5504 } else 5505 cpl = (void *)(wr + 1); 5506 5507 /* Checksum offload */ 5508 ctrl1 = csum_to_ctrl(sc, m0); 5509 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5510 txq->txcsum++; /* some hardware assistance provided */ 5511 5512 /* VLAN tag insertion */ 5513 if (needs_vlan_insertion(m0)) { 5514 ctrl1 |= F_TXPKT_VLAN_VLD | 5515 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5516 txq->vlan_insertion++; 5517 } 5518 5519 /* CPL header */ 5520 cpl->ctrl0 = txq->cpl_ctrl0; 5521 cpl->pack = 0; 5522 cpl->len = htobe16(pktlen); 5523 cpl->ctrl1 = htobe64(ctrl1); 5524 5525 /* SGL */ 5526 dst = (void *)(cpl + 1); 5527 5528 /* 5529 * A packet using TSO will use up an entire descriptor for the 5530 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 5531 * If this descriptor is the last descriptor in the ring, wrap 5532 * around to the front of the ring explicitly for the start of 5533 * the sgl. 5534 */ 5535 if (dst == (void *)&eq->desc[eq->sidx]) { 5536 dst = (void *)&eq->desc[0]; 5537 write_gl_to_txd(txq, m0, &dst, 0); 5538 } else 5539 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5540 txq->sgl_wrs++; 5541 txq->txpkt_wrs++; 5542 5543 txsd = &txq->sdesc[eq->pidx]; 5544 txsd->m = m0; 5545 txsd->desc_used = ndesc; 5546 5547 return (ndesc); 5548 } 5549 5550 /* 5551 * Write a raw WR to the hardware descriptors, update the software 5552 * descriptor, and advance the pidx. It is guaranteed that enough 5553 * descriptors are available. 5554 * 5555 * The return value is the # of hardware descriptors used. 5556 */ 5557 static u_int 5558 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 5559 { 5560 struct sge_eq *eq = &txq->eq; 5561 struct tx_sdesc *txsd; 5562 struct mbuf *m; 5563 caddr_t dst; 5564 int len16, ndesc; 5565 5566 len16 = mbuf_len16(m0); 5567 ndesc = tx_len16_to_desc(len16); 5568 MPASS(ndesc <= available); 5569 5570 dst = wr; 5571 for (m = m0; m != NULL; m = m->m_next) 5572 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5573 5574 txq->raw_wrs++; 5575 5576 txsd = &txq->sdesc[eq->pidx]; 5577 txsd->m = m0; 5578 txsd->desc_used = ndesc; 5579 5580 return (ndesc); 5581 } 5582 5583 /* 5584 * Write a txpkt WR for this packet to the hardware descriptors, update the 5585 * software descriptor, and advance the pidx. It is guaranteed that enough 5586 * descriptors are available. 5587 * 5588 * The return value is the # of hardware descriptors used. 5589 */ 5590 static u_int 5591 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0, 5592 u_int available) 5593 { 5594 struct sge_eq *eq; 5595 struct fw_eth_tx_pkt_wr *wr; 5596 struct tx_sdesc *txsd; 5597 struct cpl_tx_pkt_core *cpl; 5598 uint32_t ctrl; /* used in many unrelated places */ 5599 uint64_t ctrl1; 5600 int len16, ndesc, pktlen, nsegs; 5601 caddr_t dst; 5602 5603 TXQ_LOCK_ASSERT_OWNED(txq); 5604 M_ASSERTPKTHDR(m0); 5605 5606 len16 = mbuf_len16(m0); 5607 nsegs = mbuf_nsegs(m0); 5608 pktlen = m0->m_pkthdr.len; 5609 ctrl = sizeof(struct cpl_tx_pkt_core); 5610 if (needs_tso(m0)) { 5611 if (needs_vxlan_tso(m0)) 5612 ctrl += sizeof(struct cpl_tx_tnl_lso); 5613 else 5614 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5615 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) && 5616 available >= 2) { 5617 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 5618 ctrl += pktlen; 5619 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 5620 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 5621 nsegs = 0; 5622 } 5623 ndesc = tx_len16_to_desc(len16); 5624 MPASS(ndesc <= available); 5625 5626 /* Firmware work request header */ 5627 eq = &txq->eq; 5628 wr = (void *)&eq->desc[eq->pidx]; 5629 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 5630 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5631 5632 ctrl = V_FW_WR_LEN16(len16); 5633 wr->equiq_to_len16 = htobe32(ctrl); 5634 wr->r3 = 0; 5635 5636 if (needs_tso(m0)) { 5637 if (needs_vxlan_tso(m0)) { 5638 cpl = write_tnl_lso_cpl(wr + 1, m0); 5639 txq->vxlan_tso_wrs++; 5640 } else { 5641 cpl = write_lso_cpl(wr + 1, m0); 5642 txq->tso_wrs++; 5643 } 5644 } else 5645 cpl = (void *)(wr + 1); 5646 5647 /* Checksum offload */ 5648 ctrl1 = csum_to_ctrl(sc, m0); 5649 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5650 /* some hardware assistance provided */ 5651 if (needs_vxlan_csum(m0)) 5652 txq->vxlan_txcsum++; 5653 else 5654 txq->txcsum++; 5655 } 5656 5657 /* VLAN tag insertion */ 5658 if (needs_vlan_insertion(m0)) { 5659 ctrl1 |= F_TXPKT_VLAN_VLD | 5660 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5661 txq->vlan_insertion++; 5662 } 5663 5664 /* CPL header */ 5665 cpl->ctrl0 = txq->cpl_ctrl0; 5666 cpl->pack = 0; 5667 cpl->len = htobe16(pktlen); 5668 cpl->ctrl1 = htobe64(ctrl1); 5669 5670 /* SGL */ 5671 dst = (void *)(cpl + 1); 5672 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx])) 5673 dst = (caddr_t)&eq->desc[0]; 5674 if (nsegs > 0) { 5675 5676 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5677 txq->sgl_wrs++; 5678 } else { 5679 struct mbuf *m; 5680 5681 for (m = m0; m != NULL; m = m->m_next) { 5682 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5683 #ifdef INVARIANTS 5684 pktlen -= m->m_len; 5685 #endif 5686 } 5687 #ifdef INVARIANTS 5688 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 5689 #endif 5690 txq->imm_wrs++; 5691 } 5692 5693 txq->txpkt_wrs++; 5694 5695 txsd = &txq->sdesc[eq->pidx]; 5696 txsd->m = m0; 5697 txsd->desc_used = ndesc; 5698 5699 return (ndesc); 5700 } 5701 5702 static inline bool 5703 cmp_l2hdr(struct txpkts *txp, struct mbuf *m) 5704 { 5705 int len; 5706 5707 MPASS(txp->npkt > 0); 5708 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5709 5710 if (txp->ethtype == be16toh(ETHERTYPE_VLAN)) 5711 len = VM_TX_L2HDR_LEN; 5712 else 5713 len = sizeof(struct ether_header); 5714 5715 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0); 5716 } 5717 5718 static inline void 5719 save_l2hdr(struct txpkts *txp, struct mbuf *m) 5720 { 5721 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5722 5723 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN); 5724 } 5725 5726 static int 5727 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5728 int avail, bool *send) 5729 { 5730 struct txpkts *txp = &txq->txp; 5731 5732 /* Cannot have TSO and coalesce at the same time. */ 5733 if (cannot_use_txpkts(m)) { 5734 cannot_coalesce: 5735 *send = txp->npkt > 0; 5736 return (EINVAL); 5737 } 5738 5739 /* VF allows coalescing of type 1 (1 GL) only */ 5740 if (mbuf_nsegs(m) > 1) 5741 goto cannot_coalesce; 5742 5743 *send = false; 5744 if (txp->npkt > 0) { 5745 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5746 MPASS(txp->npkt < txp->max_npkt); 5747 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5748 5749 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) { 5750 retry_after_send: 5751 *send = true; 5752 return (EAGAIN); 5753 } 5754 if (m->m_pkthdr.len + txp->plen > 65535) 5755 goto retry_after_send; 5756 if (cmp_l2hdr(txp, m)) 5757 goto retry_after_send; 5758 5759 txp->len16 += txpkts1_len16(); 5760 txp->plen += m->m_pkthdr.len; 5761 txp->mb[txp->npkt++] = m; 5762 if (txp->npkt == txp->max_npkt) 5763 *send = true; 5764 } else { 5765 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) + 5766 txpkts1_len16(); 5767 if (tx_len16_to_desc(txp->len16) > avail) 5768 goto cannot_coalesce; 5769 txp->npkt = 1; 5770 txp->wr_type = 1; 5771 txp->plen = m->m_pkthdr.len; 5772 txp->mb[0] = m; 5773 save_l2hdr(txp, m); 5774 } 5775 return (0); 5776 } 5777 5778 static int 5779 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5780 int avail, bool *send) 5781 { 5782 struct txpkts *txp = &txq->txp; 5783 int nsegs; 5784 5785 MPASS(!(sc->flags & IS_VF)); 5786 5787 /* Cannot have TSO and coalesce at the same time. */ 5788 if (cannot_use_txpkts(m)) { 5789 cannot_coalesce: 5790 *send = txp->npkt > 0; 5791 return (EINVAL); 5792 } 5793 5794 *send = false; 5795 nsegs = mbuf_nsegs(m); 5796 if (txp->npkt == 0) { 5797 if (m->m_pkthdr.len > 65535) 5798 goto cannot_coalesce; 5799 if (nsegs > 1) { 5800 txp->wr_type = 0; 5801 txp->len16 = 5802 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5803 txpkts0_len16(nsegs); 5804 } else { 5805 txp->wr_type = 1; 5806 txp->len16 = 5807 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5808 txpkts1_len16(); 5809 } 5810 if (tx_len16_to_desc(txp->len16) > avail) 5811 goto cannot_coalesce; 5812 txp->npkt = 1; 5813 txp->plen = m->m_pkthdr.len; 5814 txp->mb[0] = m; 5815 } else { 5816 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5817 MPASS(txp->npkt < txp->max_npkt); 5818 5819 if (m->m_pkthdr.len + txp->plen > 65535) { 5820 retry_after_send: 5821 *send = true; 5822 return (EAGAIN); 5823 } 5824 5825 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 5826 if (txp->wr_type == 0) { 5827 if (tx_len16_to_desc(txp->len16 + 5828 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC)) 5829 goto retry_after_send; 5830 txp->len16 += txpkts0_len16(nsegs); 5831 } else { 5832 if (nsegs != 1) 5833 goto retry_after_send; 5834 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > 5835 avail) 5836 goto retry_after_send; 5837 txp->len16 += txpkts1_len16(); 5838 } 5839 5840 txp->plen += m->m_pkthdr.len; 5841 txp->mb[txp->npkt++] = m; 5842 if (txp->npkt == txp->max_npkt) 5843 *send = true; 5844 } 5845 return (0); 5846 } 5847 5848 /* 5849 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 5850 * the software descriptor, and advance the pidx. It is guaranteed that enough 5851 * descriptors are available. 5852 * 5853 * The return value is the # of hardware descriptors used. 5854 */ 5855 static u_int 5856 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq) 5857 { 5858 const struct txpkts *txp = &txq->txp; 5859 struct sge_eq *eq = &txq->eq; 5860 struct fw_eth_tx_pkts_wr *wr; 5861 struct tx_sdesc *txsd; 5862 struct cpl_tx_pkt_core *cpl; 5863 uint64_t ctrl1; 5864 int ndesc, i, checkwrap; 5865 struct mbuf *m, *last; 5866 void *flitp; 5867 5868 TXQ_LOCK_ASSERT_OWNED(txq); 5869 MPASS(txp->npkt > 0); 5870 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5871 5872 wr = (void *)&eq->desc[eq->pidx]; 5873 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 5874 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5875 wr->plen = htobe16(txp->plen); 5876 wr->npkt = txp->npkt; 5877 wr->r3 = 0; 5878 wr->type = txp->wr_type; 5879 flitp = wr + 1; 5880 5881 /* 5882 * At this point we are 16B into a hardware descriptor. If checkwrap is 5883 * set then we know the WR is going to wrap around somewhere. We'll 5884 * check for that at appropriate points. 5885 */ 5886 ndesc = tx_len16_to_desc(txp->len16); 5887 last = NULL; 5888 checkwrap = eq->sidx - ndesc < eq->pidx; 5889 for (i = 0; i < txp->npkt; i++) { 5890 m = txp->mb[i]; 5891 if (txp->wr_type == 0) { 5892 struct ulp_txpkt *ulpmc; 5893 struct ulptx_idata *ulpsc; 5894 5895 /* ULP master command */ 5896 ulpmc = flitp; 5897 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 5898 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 5899 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m))); 5900 5901 /* ULP subcommand */ 5902 ulpsc = (void *)(ulpmc + 1); 5903 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 5904 F_ULP_TX_SC_MORE); 5905 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 5906 5907 cpl = (void *)(ulpsc + 1); 5908 if (checkwrap && 5909 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 5910 cpl = (void *)&eq->desc[0]; 5911 } else { 5912 cpl = flitp; 5913 } 5914 5915 /* Checksum offload */ 5916 ctrl1 = csum_to_ctrl(sc, m); 5917 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5918 /* some hardware assistance provided */ 5919 if (needs_vxlan_csum(m)) 5920 txq->vxlan_txcsum++; 5921 else 5922 txq->txcsum++; 5923 } 5924 5925 /* VLAN tag insertion */ 5926 if (needs_vlan_insertion(m)) { 5927 ctrl1 |= F_TXPKT_VLAN_VLD | 5928 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5929 txq->vlan_insertion++; 5930 } 5931 5932 /* CPL header */ 5933 cpl->ctrl0 = txq->cpl_ctrl0; 5934 cpl->pack = 0; 5935 cpl->len = htobe16(m->m_pkthdr.len); 5936 cpl->ctrl1 = htobe64(ctrl1); 5937 5938 flitp = cpl + 1; 5939 if (checkwrap && 5940 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5941 flitp = (void *)&eq->desc[0]; 5942 5943 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 5944 5945 if (last != NULL) 5946 last->m_nextpkt = m; 5947 last = m; 5948 } 5949 5950 txq->sgl_wrs++; 5951 if (txp->wr_type == 0) { 5952 txq->txpkts0_pkts += txp->npkt; 5953 txq->txpkts0_wrs++; 5954 } else { 5955 txq->txpkts1_pkts += txp->npkt; 5956 txq->txpkts1_wrs++; 5957 } 5958 5959 txsd = &txq->sdesc[eq->pidx]; 5960 txsd->m = txp->mb[0]; 5961 txsd->desc_used = ndesc; 5962 5963 return (ndesc); 5964 } 5965 5966 static u_int 5967 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq) 5968 { 5969 const struct txpkts *txp = &txq->txp; 5970 struct sge_eq *eq = &txq->eq; 5971 struct fw_eth_tx_pkts_vm_wr *wr; 5972 struct tx_sdesc *txsd; 5973 struct cpl_tx_pkt_core *cpl; 5974 uint64_t ctrl1; 5975 int ndesc, i; 5976 struct mbuf *m, *last; 5977 void *flitp; 5978 5979 TXQ_LOCK_ASSERT_OWNED(txq); 5980 MPASS(txp->npkt > 0); 5981 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5982 MPASS(txp->mb[0] != NULL); 5983 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5984 5985 wr = (void *)&eq->desc[eq->pidx]; 5986 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR)); 5987 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5988 wr->r3 = 0; 5989 wr->plen = htobe16(txp->plen); 5990 wr->npkt = txp->npkt; 5991 wr->r4 = 0; 5992 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16); 5993 flitp = wr + 1; 5994 5995 /* 5996 * At this point we are 32B into a hardware descriptor. Each mbuf in 5997 * the WR will take 32B so we check for the end of the descriptor ring 5998 * before writing odd mbufs (mb[1], 3, 5, ..) 5999 */ 6000 ndesc = tx_len16_to_desc(txp->len16); 6001 last = NULL; 6002 for (i = 0; i < txp->npkt; i++) { 6003 m = txp->mb[i]; 6004 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 6005 flitp = &eq->desc[0]; 6006 cpl = flitp; 6007 6008 /* Checksum offload */ 6009 ctrl1 = csum_to_ctrl(sc, m); 6010 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 6011 txq->txcsum++; /* some hardware assistance provided */ 6012 6013 /* VLAN tag insertion */ 6014 if (needs_vlan_insertion(m)) { 6015 ctrl1 |= F_TXPKT_VLAN_VLD | 6016 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 6017 txq->vlan_insertion++; 6018 } 6019 6020 /* CPL header */ 6021 cpl->ctrl0 = txq->cpl_ctrl0; 6022 cpl->pack = 0; 6023 cpl->len = htobe16(m->m_pkthdr.len); 6024 cpl->ctrl1 = htobe64(ctrl1); 6025 6026 flitp = cpl + 1; 6027 MPASS(mbuf_nsegs(m) == 1); 6028 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0); 6029 6030 if (last != NULL) 6031 last->m_nextpkt = m; 6032 last = m; 6033 } 6034 6035 txq->sgl_wrs++; 6036 txq->txpkts1_pkts += txp->npkt; 6037 txq->txpkts1_wrs++; 6038 6039 txsd = &txq->sdesc[eq->pidx]; 6040 txsd->m = txp->mb[0]; 6041 txsd->desc_used = ndesc; 6042 6043 return (ndesc); 6044 } 6045 6046 /* 6047 * If the SGL ends on an address that is not 16 byte aligned, this function will 6048 * add a 0 filled flit at the end. 6049 */ 6050 static void 6051 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 6052 { 6053 struct sge_eq *eq = &txq->eq; 6054 struct sglist *gl = txq->gl; 6055 struct sglist_seg *seg; 6056 __be64 *flitp, *wrap; 6057 struct ulptx_sgl *usgl; 6058 int i, nflits, nsegs; 6059 6060 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 6061 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 6062 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6063 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6064 6065 get_pkt_gl(m, gl); 6066 nsegs = gl->sg_nseg; 6067 MPASS(nsegs > 0); 6068 6069 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 6070 flitp = (__be64 *)(*to); 6071 wrap = (__be64 *)(&eq->desc[eq->sidx]); 6072 seg = &gl->sg_segs[0]; 6073 usgl = (void *)flitp; 6074 6075 /* 6076 * We start at a 16 byte boundary somewhere inside the tx descriptor 6077 * ring, so we're at least 16 bytes away from the status page. There is 6078 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 6079 */ 6080 6081 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6082 V_ULPTX_NSGE(nsegs)); 6083 usgl->len0 = htobe32(seg->ss_len); 6084 usgl->addr0 = htobe64(seg->ss_paddr); 6085 seg++; 6086 6087 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 6088 6089 /* Won't wrap around at all */ 6090 6091 for (i = 0; i < nsegs - 1; i++, seg++) { 6092 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 6093 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 6094 } 6095 if (i & 1) 6096 usgl->sge[i / 2].len[1] = htobe32(0); 6097 flitp += nflits; 6098 } else { 6099 6100 /* Will wrap somewhere in the rest of the SGL */ 6101 6102 /* 2 flits already written, write the rest flit by flit */ 6103 flitp = (void *)(usgl + 1); 6104 for (i = 0; i < nflits - 2; i++) { 6105 if (flitp == wrap) 6106 flitp = (void *)eq->desc; 6107 *flitp++ = get_flit(seg, nsegs - 1, i); 6108 } 6109 } 6110 6111 if (nflits & 1) { 6112 MPASS(((uintptr_t)flitp) & 0xf); 6113 *flitp++ = 0; 6114 } 6115 6116 MPASS((((uintptr_t)flitp) & 0xf) == 0); 6117 if (__predict_false(flitp == wrap)) 6118 *to = (void *)eq->desc; 6119 else 6120 *to = (void *)flitp; 6121 } 6122 6123 static inline void 6124 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 6125 { 6126 6127 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6128 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6129 6130 if (__predict_true((uintptr_t)(*to) + len <= 6131 (uintptr_t)&eq->desc[eq->sidx])) { 6132 bcopy(from, *to, len); 6133 (*to) += len; 6134 } else { 6135 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 6136 6137 bcopy(from, *to, portion); 6138 from += portion; 6139 portion = len - portion; /* remaining */ 6140 bcopy(from, (void *)eq->desc, portion); 6141 (*to) = (caddr_t)eq->desc + portion; 6142 } 6143 } 6144 6145 static inline void 6146 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 6147 { 6148 u_int db; 6149 6150 MPASS(n > 0); 6151 6152 db = eq->doorbells; 6153 if (n > 1) 6154 clrbit(&db, DOORBELL_WCWR); 6155 wmb(); 6156 6157 switch (ffs(db) - 1) { 6158 case DOORBELL_UDB: 6159 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6160 break; 6161 6162 case DOORBELL_WCWR: { 6163 volatile uint64_t *dst, *src; 6164 int i; 6165 6166 /* 6167 * Queues whose 128B doorbell segment fits in the page do not 6168 * use relative qid (udb_qid is always 0). Only queues with 6169 * doorbell segments can do WCWR. 6170 */ 6171 KASSERT(eq->udb_qid == 0 && n == 1, 6172 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 6173 __func__, eq->doorbells, n, eq->dbidx, eq)); 6174 6175 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 6176 UDBS_DB_OFFSET); 6177 i = eq->dbidx; 6178 src = (void *)&eq->desc[i]; 6179 while (src != (void *)&eq->desc[i + 1]) 6180 *dst++ = *src++; 6181 wmb(); 6182 break; 6183 } 6184 6185 case DOORBELL_UDBWC: 6186 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6187 wmb(); 6188 break; 6189 6190 case DOORBELL_KDB: 6191 t4_write_reg(sc, sc->sge_kdoorbell_reg, 6192 V_QID(eq->cntxt_id) | V_PIDX(n)); 6193 break; 6194 } 6195 6196 IDXINCR(eq->dbidx, n, eq->sidx); 6197 } 6198 6199 static inline u_int 6200 reclaimable_tx_desc(struct sge_eq *eq) 6201 { 6202 uint16_t hw_cidx; 6203 6204 hw_cidx = read_hw_cidx(eq); 6205 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 6206 } 6207 6208 static inline u_int 6209 total_available_tx_desc(struct sge_eq *eq) 6210 { 6211 uint16_t hw_cidx, pidx; 6212 6213 hw_cidx = read_hw_cidx(eq); 6214 pidx = eq->pidx; 6215 6216 if (pidx == hw_cidx) 6217 return (eq->sidx - 1); 6218 else 6219 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 6220 } 6221 6222 static inline uint16_t 6223 read_hw_cidx(struct sge_eq *eq) 6224 { 6225 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 6226 uint16_t cidx = spg->cidx; /* stable snapshot */ 6227 6228 return (be16toh(cidx)); 6229 } 6230 6231 /* 6232 * Reclaim 'n' descriptors approximately. 6233 */ 6234 static u_int 6235 reclaim_tx_descs(struct sge_txq *txq, u_int n) 6236 { 6237 struct tx_sdesc *txsd; 6238 struct sge_eq *eq = &txq->eq; 6239 u_int can_reclaim, reclaimed; 6240 6241 TXQ_LOCK_ASSERT_OWNED(txq); 6242 MPASS(n > 0); 6243 6244 reclaimed = 0; 6245 can_reclaim = reclaimable_tx_desc(eq); 6246 while (can_reclaim && reclaimed < n) { 6247 int ndesc; 6248 struct mbuf *m, *nextpkt; 6249 6250 txsd = &txq->sdesc[eq->cidx]; 6251 ndesc = txsd->desc_used; 6252 6253 /* Firmware doesn't return "partial" credits. */ 6254 KASSERT(can_reclaim >= ndesc, 6255 ("%s: unexpected number of credits: %d, %d", 6256 __func__, can_reclaim, ndesc)); 6257 KASSERT(ndesc != 0, 6258 ("%s: descriptor with no credits: cidx %d", 6259 __func__, eq->cidx)); 6260 6261 for (m = txsd->m; m != NULL; m = nextpkt) { 6262 nextpkt = m->m_nextpkt; 6263 m->m_nextpkt = NULL; 6264 m_freem(m); 6265 } 6266 reclaimed += ndesc; 6267 can_reclaim -= ndesc; 6268 IDXINCR(eq->cidx, ndesc, eq->sidx); 6269 } 6270 6271 return (reclaimed); 6272 } 6273 6274 static void 6275 tx_reclaim(void *arg, int n) 6276 { 6277 struct sge_txq *txq = arg; 6278 struct sge_eq *eq = &txq->eq; 6279 6280 do { 6281 if (TXQ_TRYLOCK(txq) == 0) 6282 break; 6283 n = reclaim_tx_descs(txq, 32); 6284 if (eq->cidx == eq->pidx) 6285 eq->equeqidx = eq->pidx; 6286 TXQ_UNLOCK(txq); 6287 } while (n > 0); 6288 } 6289 6290 static __be64 6291 get_flit(struct sglist_seg *segs, int nsegs, int idx) 6292 { 6293 int i = (idx / 3) * 2; 6294 6295 switch (idx % 3) { 6296 case 0: { 6297 uint64_t rc; 6298 6299 rc = (uint64_t)segs[i].ss_len << 32; 6300 if (i + 1 < nsegs) 6301 rc |= (uint64_t)(segs[i + 1].ss_len); 6302 6303 return (htobe64(rc)); 6304 } 6305 case 1: 6306 return (htobe64(segs[i].ss_paddr)); 6307 case 2: 6308 return (htobe64(segs[i + 1].ss_paddr)); 6309 } 6310 6311 return (0); 6312 } 6313 6314 static int 6315 find_refill_source(struct adapter *sc, int maxp, bool packing) 6316 { 6317 int i, zidx = -1; 6318 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6319 6320 if (packing) { 6321 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6322 if (rxb->hwidx2 == -1) 6323 continue; 6324 if (rxb->size1 < PAGE_SIZE && 6325 rxb->size1 < largest_rx_cluster) 6326 continue; 6327 if (rxb->size1 > largest_rx_cluster) 6328 break; 6329 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE); 6330 if (rxb->size2 >= maxp) 6331 return (i); 6332 zidx = i; 6333 } 6334 } else { 6335 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6336 if (rxb->hwidx1 == -1) 6337 continue; 6338 if (rxb->size1 > largest_rx_cluster) 6339 break; 6340 if (rxb->size1 >= maxp) 6341 return (i); 6342 zidx = i; 6343 } 6344 } 6345 6346 return (zidx); 6347 } 6348 6349 static void 6350 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 6351 { 6352 mtx_lock(&sc->sfl_lock); 6353 FL_LOCK(fl); 6354 if ((fl->flags & FL_DOOMED) == 0) { 6355 fl->flags |= FL_STARVING; 6356 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 6357 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 6358 } 6359 FL_UNLOCK(fl); 6360 mtx_unlock(&sc->sfl_lock); 6361 } 6362 6363 static void 6364 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 6365 { 6366 struct sge_wrq *wrq = (void *)eq; 6367 6368 atomic_readandclear_int(&eq->equiq); 6369 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 6370 } 6371 6372 static void 6373 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 6374 { 6375 struct sge_txq *txq = (void *)eq; 6376 6377 MPASS(eq->type == EQ_ETH); 6378 6379 atomic_readandclear_int(&eq->equiq); 6380 if (mp_ring_is_idle(txq->r)) 6381 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 6382 else 6383 mp_ring_check_drainage(txq->r, 64); 6384 } 6385 6386 static int 6387 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 6388 struct mbuf *m) 6389 { 6390 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 6391 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 6392 struct adapter *sc = iq->adapter; 6393 struct sge *s = &sc->sge; 6394 struct sge_eq *eq; 6395 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 6396 &handle_wrq_egr_update, &handle_eth_egr_update, 6397 &handle_wrq_egr_update}; 6398 6399 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6400 rss->opcode)); 6401 6402 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 6403 (*h[eq->type])(sc, eq); 6404 6405 return (0); 6406 } 6407 6408 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 6409 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 6410 offsetof(struct cpl_fw6_msg, data)); 6411 6412 static int 6413 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 6414 { 6415 struct adapter *sc = iq->adapter; 6416 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 6417 6418 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6419 rss->opcode)); 6420 6421 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 6422 const struct rss_header *rss2; 6423 6424 rss2 = (const struct rss_header *)&cpl->data[0]; 6425 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 6426 } 6427 6428 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 6429 } 6430 6431 /** 6432 * t4_handle_wrerr_rpl - process a FW work request error message 6433 * @adap: the adapter 6434 * @rpl: start of the FW message 6435 */ 6436 static int 6437 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 6438 { 6439 u8 opcode = *(const u8 *)rpl; 6440 const struct fw_error_cmd *e = (const void *)rpl; 6441 unsigned int i; 6442 6443 if (opcode != FW_ERROR_CMD) { 6444 log(LOG_ERR, 6445 "%s: Received WRERR_RPL message with opcode %#x\n", 6446 device_get_nameunit(adap->dev), opcode); 6447 return (EINVAL); 6448 } 6449 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 6450 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 6451 "non-fatal"); 6452 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 6453 case FW_ERROR_TYPE_EXCEPTION: 6454 log(LOG_ERR, "exception info:\n"); 6455 for (i = 0; i < nitems(e->u.exception.info); i++) 6456 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 6457 be32toh(e->u.exception.info[i])); 6458 log(LOG_ERR, "\n"); 6459 break; 6460 case FW_ERROR_TYPE_HWMODULE: 6461 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 6462 be32toh(e->u.hwmodule.regaddr), 6463 be32toh(e->u.hwmodule.regval)); 6464 break; 6465 case FW_ERROR_TYPE_WR: 6466 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 6467 be16toh(e->u.wr.cidx), 6468 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 6469 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 6470 be32toh(e->u.wr.eqid)); 6471 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 6472 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 6473 e->u.wr.wrhdr[i]); 6474 log(LOG_ERR, "\n"); 6475 break; 6476 case FW_ERROR_TYPE_ACL: 6477 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 6478 be16toh(e->u.acl.cidx), 6479 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 6480 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 6481 be32toh(e->u.acl.eqid), 6482 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 6483 "MAC"); 6484 for (i = 0; i < nitems(e->u.acl.val); i++) 6485 log(LOG_ERR, " %02x", e->u.acl.val[i]); 6486 log(LOG_ERR, "\n"); 6487 break; 6488 default: 6489 log(LOG_ERR, "type %#x\n", 6490 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 6491 return (EINVAL); 6492 } 6493 return (0); 6494 } 6495 6496 static inline bool 6497 bufidx_used(struct adapter *sc, int idx) 6498 { 6499 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6500 int i; 6501 6502 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6503 if (rxb->size1 > largest_rx_cluster) 6504 continue; 6505 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx) 6506 return (true); 6507 } 6508 6509 return (false); 6510 } 6511 6512 static int 6513 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 6514 { 6515 struct adapter *sc = arg1; 6516 struct sge_params *sp = &sc->params.sge; 6517 int i, rc; 6518 struct sbuf sb; 6519 char c; 6520 6521 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND); 6522 for (i = 0; i < SGE_FLBUF_SIZES; i++) { 6523 if (bufidx_used(sc, i)) 6524 c = '*'; 6525 else 6526 c = '\0'; 6527 6528 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c); 6529 } 6530 sbuf_trim(&sb); 6531 sbuf_finish(&sb); 6532 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 6533 sbuf_delete(&sb); 6534 return (rc); 6535 } 6536 6537 #ifdef RATELIMIT 6538 #if defined(INET) || defined(INET6) 6539 /* 6540 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 6541 */ 6542 static inline u_int 6543 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 6544 { 6545 u_int n; 6546 6547 MPASS(immhdrs > 0); 6548 6549 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 6550 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 6551 if (__predict_false(nsegs == 0)) 6552 goto done; 6553 6554 nsegs--; /* first segment is part of ulptx_sgl */ 6555 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 6556 if (tso) 6557 n += sizeof(struct cpl_tx_pkt_lso_core); 6558 6559 done: 6560 return (howmany(n, 16)); 6561 } 6562 #endif 6563 6564 #define ETID_FLOWC_NPARAMS 6 6565 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 6566 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 6567 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 6568 6569 static int 6570 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi, 6571 struct vi_info *vi) 6572 { 6573 struct wrq_cookie cookie; 6574 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 6575 struct fw_flowc_wr *flowc; 6576 6577 mtx_assert(&cst->lock, MA_OWNED); 6578 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 6579 EO_FLOWC_PENDING); 6580 6581 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie); 6582 if (__predict_false(flowc == NULL)) 6583 return (ENOMEM); 6584 6585 bzero(flowc, ETID_FLOWC_LEN); 6586 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6587 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 6588 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 6589 V_FW_WR_FLOWID(cst->etid)); 6590 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 6591 flowc->mnemval[0].val = htobe32(pfvf); 6592 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 6593 flowc->mnemval[1].val = htobe32(pi->tx_chan); 6594 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 6595 flowc->mnemval[2].val = htobe32(pi->tx_chan); 6596 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 6597 flowc->mnemval[3].val = htobe32(cst->iqid); 6598 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 6599 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 6600 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 6601 flowc->mnemval[5].val = htobe32(cst->schedcl); 6602 6603 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6604 6605 cst->flags &= ~EO_FLOWC_PENDING; 6606 cst->flags |= EO_FLOWC_RPL_PENDING; 6607 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 6608 cst->tx_credits -= ETID_FLOWC_LEN16; 6609 6610 return (0); 6611 } 6612 6613 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 6614 6615 void 6616 send_etid_flush_wr(struct cxgbe_rate_tag *cst) 6617 { 6618 struct fw_flowc_wr *flowc; 6619 struct wrq_cookie cookie; 6620 6621 mtx_assert(&cst->lock, MA_OWNED); 6622 6623 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie); 6624 if (__predict_false(flowc == NULL)) 6625 CXGBE_UNIMPLEMENTED(__func__); 6626 6627 bzero(flowc, ETID_FLUSH_LEN16 * 16); 6628 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6629 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 6630 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 6631 V_FW_WR_FLOWID(cst->etid)); 6632 6633 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6634 6635 cst->flags |= EO_FLUSH_RPL_PENDING; 6636 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 6637 cst->tx_credits -= ETID_FLUSH_LEN16; 6638 cst->ncompl++; 6639 } 6640 6641 static void 6642 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr, 6643 struct mbuf *m0, int compl) 6644 { 6645 struct cpl_tx_pkt_core *cpl; 6646 uint64_t ctrl1; 6647 uint32_t ctrl; /* used in many unrelated places */ 6648 int len16, pktlen, nsegs, immhdrs; 6649 uintptr_t p; 6650 struct ulptx_sgl *usgl; 6651 struct sglist sg; 6652 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 6653 6654 mtx_assert(&cst->lock, MA_OWNED); 6655 M_ASSERTPKTHDR(m0); 6656 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 6657 m0->m_pkthdr.l4hlen > 0, 6658 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 6659 6660 len16 = mbuf_eo_len16(m0); 6661 nsegs = mbuf_eo_nsegs(m0); 6662 pktlen = m0->m_pkthdr.len; 6663 ctrl = sizeof(struct cpl_tx_pkt_core); 6664 if (needs_tso(m0)) 6665 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 6666 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 6667 ctrl += immhdrs; 6668 6669 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 6670 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 6671 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 6672 V_FW_WR_FLOWID(cst->etid)); 6673 wr->r3 = 0; 6674 if (needs_outer_udp_csum(m0)) { 6675 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 6676 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 6677 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6678 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 6679 wr->u.udpseg.rtplen = 0; 6680 wr->u.udpseg.r4 = 0; 6681 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 6682 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 6683 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 6684 cpl = (void *)(wr + 1); 6685 } else { 6686 MPASS(needs_outer_tcp_csum(m0)); 6687 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 6688 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 6689 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6690 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 6691 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 6692 wr->u.tcpseg.r4 = 0; 6693 wr->u.tcpseg.r5 = 0; 6694 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 6695 6696 if (needs_tso(m0)) { 6697 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 6698 6699 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 6700 6701 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 6702 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 6703 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 6704 ETHER_HDR_LEN) >> 2) | 6705 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 6706 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 6707 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 6708 ctrl |= F_LSO_IPV6; 6709 lso->lso_ctrl = htobe32(ctrl); 6710 lso->ipid_ofst = htobe16(0); 6711 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 6712 lso->seqno_offset = htobe32(0); 6713 lso->len = htobe32(pktlen); 6714 6715 cpl = (void *)(lso + 1); 6716 } else { 6717 wr->u.tcpseg.mss = htobe16(0xffff); 6718 cpl = (void *)(wr + 1); 6719 } 6720 } 6721 6722 /* Checksum offload must be requested for ethofld. */ 6723 MPASS(needs_outer_l4_csum(m0)); 6724 ctrl1 = csum_to_ctrl(cst->adapter, m0); 6725 6726 /* VLAN tag insertion */ 6727 if (needs_vlan_insertion(m0)) { 6728 ctrl1 |= F_TXPKT_VLAN_VLD | 6729 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 6730 } 6731 6732 /* CPL header */ 6733 cpl->ctrl0 = cst->ctrl0; 6734 cpl->pack = 0; 6735 cpl->len = htobe16(pktlen); 6736 cpl->ctrl1 = htobe64(ctrl1); 6737 6738 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 6739 p = (uintptr_t)(cpl + 1); 6740 m_copydata(m0, 0, immhdrs, (void *)p); 6741 6742 /* SGL */ 6743 if (nsegs > 0) { 6744 int i, pad; 6745 6746 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 6747 p += immhdrs; 6748 pad = 16 - (immhdrs & 0xf); 6749 bzero((void *)p, pad); 6750 6751 usgl = (void *)(p + pad); 6752 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6753 V_ULPTX_NSGE(nsegs)); 6754 6755 sglist_init(&sg, nitems(segs), segs); 6756 for (; m0 != NULL; m0 = m0->m_next) { 6757 if (__predict_false(m0->m_len == 0)) 6758 continue; 6759 if (immhdrs >= m0->m_len) { 6760 immhdrs -= m0->m_len; 6761 continue; 6762 } 6763 if (m0->m_flags & M_EXTPG) 6764 sglist_append_mbuf_epg(&sg, m0, 6765 mtod(m0, vm_offset_t), m0->m_len); 6766 else 6767 sglist_append(&sg, mtod(m0, char *) + immhdrs, 6768 m0->m_len - immhdrs); 6769 immhdrs = 0; 6770 } 6771 MPASS(sg.sg_nseg == nsegs); 6772 6773 /* 6774 * Zero pad last 8B in case the WR doesn't end on a 16B 6775 * boundary. 6776 */ 6777 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 6778 6779 usgl->len0 = htobe32(segs[0].ss_len); 6780 usgl->addr0 = htobe64(segs[0].ss_paddr); 6781 for (i = 0; i < nsegs - 1; i++) { 6782 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 6783 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 6784 } 6785 if (i & 1) 6786 usgl->sge[i / 2].len[1] = htobe32(0); 6787 } 6788 6789 } 6790 6791 static void 6792 ethofld_tx(struct cxgbe_rate_tag *cst) 6793 { 6794 struct mbuf *m; 6795 struct wrq_cookie cookie; 6796 int next_credits, compl; 6797 struct fw_eth_tx_eo_wr *wr; 6798 6799 mtx_assert(&cst->lock, MA_OWNED); 6800 6801 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 6802 M_ASSERTPKTHDR(m); 6803 6804 /* How many len16 credits do we need to send this mbuf. */ 6805 next_credits = mbuf_eo_len16(m); 6806 MPASS(next_credits > 0); 6807 if (next_credits > cst->tx_credits) { 6808 /* 6809 * Tx will make progress eventually because there is at 6810 * least one outstanding fw4_ack that will return 6811 * credits and kick the tx. 6812 */ 6813 MPASS(cst->ncompl > 0); 6814 return; 6815 } 6816 wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie); 6817 if (__predict_false(wr == NULL)) { 6818 /* XXX: wishful thinking, not a real assertion. */ 6819 MPASS(cst->ncompl > 0); 6820 return; 6821 } 6822 cst->tx_credits -= next_credits; 6823 cst->tx_nocompl += next_credits; 6824 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 6825 ETHER_BPF_MTAP(cst->com.ifp, m); 6826 write_ethofld_wr(cst, wr, m, compl); 6827 commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie); 6828 if (compl) { 6829 cst->ncompl++; 6830 cst->tx_nocompl = 0; 6831 } 6832 (void) mbufq_dequeue(&cst->pending_tx); 6833 6834 /* 6835 * Drop the mbuf's reference on the tag now rather 6836 * than waiting until m_freem(). This ensures that 6837 * cxgbe_rate_tag_free gets called when the inp drops 6838 * its reference on the tag and there are no more 6839 * mbufs in the pending_tx queue and can flush any 6840 * pending requests. Otherwise if the last mbuf 6841 * doesn't request a completion the etid will never be 6842 * released. 6843 */ 6844 m->m_pkthdr.snd_tag = NULL; 6845 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 6846 m_snd_tag_rele(&cst->com); 6847 6848 mbufq_enqueue(&cst->pending_fwack, m); 6849 } 6850 } 6851 6852 int 6853 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 6854 { 6855 struct cxgbe_rate_tag *cst; 6856 int rc; 6857 6858 MPASS(m0->m_nextpkt == NULL); 6859 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG); 6860 MPASS(m0->m_pkthdr.snd_tag != NULL); 6861 cst = mst_to_crt(m0->m_pkthdr.snd_tag); 6862 6863 mtx_lock(&cst->lock); 6864 MPASS(cst->flags & EO_SND_TAG_REF); 6865 6866 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 6867 struct vi_info *vi = ifp->if_softc; 6868 struct port_info *pi = vi->pi; 6869 struct adapter *sc = pi->adapter; 6870 const uint32_t rss_mask = vi->rss_size - 1; 6871 uint32_t rss_hash; 6872 6873 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 6874 if (M_HASHTYPE_ISHASH(m0)) 6875 rss_hash = m0->m_pkthdr.flowid; 6876 else 6877 rss_hash = arc4random(); 6878 /* We assume RSS hashing */ 6879 cst->iqid = vi->rss[rss_hash & rss_mask]; 6880 cst->eo_txq += rss_hash % vi->nofldtxq; 6881 rc = send_etid_flowc_wr(cst, pi, vi); 6882 if (rc != 0) 6883 goto done; 6884 } 6885 6886 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 6887 rc = ENOBUFS; 6888 goto done; 6889 } 6890 6891 mbufq_enqueue(&cst->pending_tx, m0); 6892 cst->plen += m0->m_pkthdr.len; 6893 6894 /* 6895 * Hold an extra reference on the tag while generating work 6896 * requests to ensure that we don't try to free the tag during 6897 * ethofld_tx() in case we are sending the final mbuf after 6898 * the inp was freed. 6899 */ 6900 m_snd_tag_ref(&cst->com); 6901 ethofld_tx(cst); 6902 mtx_unlock(&cst->lock); 6903 m_snd_tag_rele(&cst->com); 6904 return (0); 6905 6906 done: 6907 mtx_unlock(&cst->lock); 6908 if (__predict_false(rc != 0)) 6909 m_freem(m0); 6910 return (rc); 6911 } 6912 6913 static int 6914 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 6915 { 6916 struct adapter *sc = iq->adapter; 6917 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 6918 struct mbuf *m; 6919 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 6920 struct cxgbe_rate_tag *cst; 6921 uint8_t credits = cpl->credits; 6922 6923 cst = lookup_etid(sc, etid); 6924 mtx_lock(&cst->lock); 6925 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 6926 MPASS(credits >= ETID_FLOWC_LEN16); 6927 credits -= ETID_FLOWC_LEN16; 6928 cst->flags &= ~EO_FLOWC_RPL_PENDING; 6929 } 6930 6931 KASSERT(cst->ncompl > 0, 6932 ("%s: etid %u (%p) wasn't expecting completion.", 6933 __func__, etid, cst)); 6934 cst->ncompl--; 6935 6936 while (credits > 0) { 6937 m = mbufq_dequeue(&cst->pending_fwack); 6938 if (__predict_false(m == NULL)) { 6939 /* 6940 * The remaining credits are for the final flush that 6941 * was issued when the tag was freed by the kernel. 6942 */ 6943 MPASS((cst->flags & 6944 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 6945 EO_FLUSH_RPL_PENDING); 6946 MPASS(credits == ETID_FLUSH_LEN16); 6947 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6948 MPASS(cst->ncompl == 0); 6949 6950 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6951 cst->tx_credits += cpl->credits; 6952 cxgbe_rate_tag_free_locked(cst); 6953 return (0); /* cst is gone. */ 6954 } 6955 KASSERT(m != NULL, 6956 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6957 credits)); 6958 KASSERT(credits >= mbuf_eo_len16(m), 6959 ("%s: too few credits (%u, %u, %u)", __func__, 6960 cpl->credits, credits, mbuf_eo_len16(m))); 6961 credits -= mbuf_eo_len16(m); 6962 cst->plen -= m->m_pkthdr.len; 6963 m_freem(m); 6964 } 6965 6966 cst->tx_credits += cpl->credits; 6967 MPASS(cst->tx_credits <= cst->tx_total); 6968 6969 if (cst->flags & EO_SND_TAG_REF) { 6970 /* 6971 * As with ethofld_transmit(), hold an extra reference 6972 * so that the tag is stable across ethold_tx(). 6973 */ 6974 m_snd_tag_ref(&cst->com); 6975 m = mbufq_first(&cst->pending_tx); 6976 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6977 ethofld_tx(cst); 6978 mtx_unlock(&cst->lock); 6979 m_snd_tag_rele(&cst->com); 6980 } else { 6981 /* 6982 * There shouldn't be any pending packets if the tag 6983 * was freed by the kernel since any pending packet 6984 * should hold a reference to the tag. 6985 */ 6986 MPASS(mbufq_first(&cst->pending_tx) == NULL); 6987 mtx_unlock(&cst->lock); 6988 } 6989 6990 return (0); 6991 } 6992 #endif
Cache object: 59126a99128088a7d5dc5ddc407062a5
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