The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/dc/dcphy.c

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    1 /*-
    2  * Copyright (c) 1997, 1998, 1999
    3  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: releng/8.4/sys/dev/dc/dcphy.c 230718 2012-01-29 01:35:14Z marius $");
   35 
   36 /*
   37  * Pseudo-driver for internal NWAY support on DEC 21143 and workalike
   38  * controllers.  Technically we're abusing the miibus code to handle
   39  * media selection and NWAY support here since there is no MII
   40  * interface.  However the logical operations are roughly the same,
   41  * and the alternative is to create a fake MII interface in the driver,
   42  * which is harder to do.
   43  */
   44 
   45 #include <sys/param.h>
   46 #include <sys/systm.h>
   47 #include <sys/kernel.h>
   48 #include <sys/socket.h>
   49 #include <sys/errno.h>
   50 #include <sys/lock.h>
   51 #include <sys/module.h>
   52 #include <sys/mutex.h>
   53 #include <sys/bus.h>
   54 
   55 #include <net/if.h>
   56 #include <net/if_arp.h>
   57 #include <net/if_media.h>
   58 
   59 #include <dev/mii/mii.h>
   60 #include <dev/mii/miivar.h>
   61 #include "miidevs.h"
   62 
   63 #include <machine/bus.h>
   64 #include <machine/resource.h>
   65 #include <sys/bus.h>
   66 
   67 #include <dev/pci/pcivar.h>
   68 
   69 #include <dev/dc/if_dcreg.h>
   70 
   71 #include "miibus_if.h"
   72 
   73 #define DC_SETBIT(sc, reg, x)                           \
   74         CSR_WRITE_4(sc, reg,                            \
   75                 CSR_READ_4(sc, reg) | x)
   76 
   77 #define DC_CLRBIT(sc, reg, x)                           \
   78         CSR_WRITE_4(sc, reg,                            \
   79                 CSR_READ_4(sc, reg) & ~x)
   80 
   81 #define MIIF_AUTOTIMEOUT        0x0004
   82 
   83 /*
   84  * This is the subsystem ID for the built-in 21143 ethernet
   85  * in several Compaq Presario systems.  Apparently these are
   86  * 10Mbps only, so we need to treat them specially.
   87  */
   88 #define COMPAQ_PRESARIO_ID      0xb0bb0e11
   89 
   90 static int dcphy_probe(device_t);
   91 static int dcphy_attach(device_t);
   92 
   93 static device_method_t dcphy_methods[] = {
   94         /* device interface */
   95         DEVMETHOD(device_probe,         dcphy_probe),
   96         DEVMETHOD(device_attach,        dcphy_attach),
   97         DEVMETHOD(device_detach,        mii_phy_detach),
   98         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
   99         DEVMETHOD_END
  100 };
  101 
  102 static devclass_t dcphy_devclass;
  103 
  104 static driver_t dcphy_driver = {
  105         "dcphy",
  106         dcphy_methods,
  107         sizeof(struct mii_softc)
  108 };
  109 
  110 DRIVER_MODULE(dcphy, miibus, dcphy_driver, dcphy_devclass, 0, 0);
  111 
  112 static int      dcphy_service(struct mii_softc *, struct mii_data *, int);
  113 static void     dcphy_status(struct mii_softc *);
  114 static void     dcphy_reset(struct mii_softc *);
  115 static int      dcphy_auto(struct mii_softc *);
  116 
  117 static int
  118 dcphy_probe(device_t dev)
  119 {
  120         struct mii_attach_args *ma;
  121 
  122         ma = device_get_ivars(dev);
  123 
  124         /*
  125          * The dc driver will report the 21143 vendor and device
  126          * ID to let us know that it wants us to attach.
  127          */
  128         if (ma->mii_id1 != DC_VENDORID_DEC ||
  129             ma->mii_id2 != DC_DEVICEID_21143)
  130                 return (ENXIO);
  131 
  132         device_set_desc(dev, "Intel 21143 NWAY media interface");
  133 
  134         return (BUS_PROBE_DEFAULT);
  135 }
  136 
  137 static int
  138 dcphy_attach(device_t dev)
  139 {
  140         struct mii_softc *sc;
  141         struct mii_attach_args *ma;
  142         struct mii_data *mii;
  143         struct dc_softc         *dc_sc;
  144         device_t brdev;
  145 
  146         sc = device_get_softc(dev);
  147         ma = device_get_ivars(dev);
  148         sc->mii_dev = device_get_parent(dev);
  149         mii = ma->mii_data;
  150         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
  151 
  152         sc->mii_flags = miibus_get_flags(dev);
  153         sc->mii_inst = mii->mii_instance++;
  154         sc->mii_phy = ma->mii_phyno;
  155         sc->mii_service = dcphy_service;
  156         sc->mii_pdata = mii;
  157 
  158         /*
  159          * Apparently, we can neither isolate nor do loopback.
  160          */
  161         sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP | MIIF_NOMANPAUSE;
  162 
  163         /*dcphy_reset(sc);*/
  164         dc_sc = mii->mii_ifp->if_softc;
  165         CSR_WRITE_4(dc_sc, DC_10BTSTAT, 0);
  166         CSR_WRITE_4(dc_sc, DC_10BTCTRL, 0);
  167 
  168         brdev = device_get_parent(sc->mii_dev);
  169         switch (pci_get_subdevice(brdev) << 16 | pci_get_subvendor(brdev)) {
  170         case COMPAQ_PRESARIO_ID:
  171                 /* Example of how to only allow 10Mbps modes. */
  172                 sc->mii_capabilities = BMSR_ANEG | BMSR_10TFDX | BMSR_10THDX;
  173                 break;
  174         default:
  175                 if (dc_sc->dc_pmode == DC_PMODE_SIA)
  176                         sc->mii_capabilities =
  177                             BMSR_ANEG | BMSR_10TFDX | BMSR_10THDX;
  178                 else
  179                         sc->mii_capabilities =
  180                             BMSR_ANEG | BMSR_100TXFDX | BMSR_100TXHDX |
  181                             BMSR_10TFDX | BMSR_10THDX;
  182                 break;
  183         }
  184 
  185         sc->mii_capabilities &= ma->mii_capmask;
  186         device_printf(dev, " ");
  187         mii_phy_add_media(sc);
  188         printf("\n");
  189 
  190         MIIBUS_MEDIAINIT(sc->mii_dev);
  191         return (0);
  192 }
  193 
  194 static int
  195 dcphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
  196 {
  197         struct dc_softc         *dc_sc;
  198         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
  199         int reg;
  200         u_int32_t               mode;
  201 
  202         dc_sc = mii->mii_ifp->if_softc;
  203 
  204         switch (cmd) {
  205         case MII_POLLSTAT:
  206                 break;
  207 
  208         case MII_MEDIACHG:
  209                 /*
  210                  * If the interface is not up, don't do anything.
  211                  */
  212                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
  213                         break;
  214 
  215                 mii->mii_media_active = IFM_NONE;
  216                 mode = CSR_READ_4(dc_sc, DC_NETCFG);
  217                 mode &= ~(DC_NETCFG_FULLDUPLEX | DC_NETCFG_PORTSEL |
  218                     DC_NETCFG_PCS | DC_NETCFG_SCRAMBLER | DC_NETCFG_SPEEDSEL);
  219 
  220                 switch (IFM_SUBTYPE(ife->ifm_media)) {
  221                 case IFM_AUTO:
  222                         /*dcphy_reset(sc);*/
  223                         (void) dcphy_auto(sc);
  224                         break;
  225                 case IFM_100_TX:
  226                         dcphy_reset(sc);
  227                         DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
  228                         mode |= DC_NETCFG_PORTSEL | DC_NETCFG_PCS |
  229                             DC_NETCFG_SCRAMBLER;
  230                         if ((ife->ifm_media & IFM_FDX) != 0)
  231                                 mode |= DC_NETCFG_FULLDUPLEX;
  232                         else
  233                                 mode &= ~DC_NETCFG_FULLDUPLEX;
  234                         CSR_WRITE_4(dc_sc, DC_NETCFG, mode);
  235                         break;
  236                 case IFM_10_T:
  237                         DC_CLRBIT(dc_sc, DC_SIARESET, DC_SIA_RESET);
  238                         DC_CLRBIT(dc_sc, DC_10BTCTRL, 0xFFFF);
  239                         if ((ife->ifm_media & IFM_FDX) != 0)
  240                                 DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3D);
  241                         else
  242                                 DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3F);
  243                         DC_SETBIT(dc_sc, DC_SIARESET, DC_SIA_RESET);
  244                         DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
  245                         mode &= ~DC_NETCFG_PORTSEL;
  246                         mode |= DC_NETCFG_SPEEDSEL;
  247                         if ((ife->ifm_media & IFM_FDX) != 0)
  248                                 mode |= DC_NETCFG_FULLDUPLEX;
  249                         else
  250                                 mode &= ~DC_NETCFG_FULLDUPLEX;
  251                         CSR_WRITE_4(dc_sc, DC_NETCFG, mode);
  252                         break;
  253                 default:
  254                         return (EINVAL);
  255                 }
  256                 break;
  257 
  258         case MII_TICK:
  259                 /*
  260                  * Is the interface even up?
  261                  */
  262                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
  263                         return (0);
  264 
  265                 /*
  266                  * Only used for autonegotiation.
  267                  */
  268                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
  269                         break;
  270 
  271                 reg = CSR_READ_4(dc_sc, DC_10BTSTAT);
  272                 if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))
  273                         break;
  274 
  275                 /*
  276                  * Only retry autonegotiation every 5 seconds.
  277                  *
  278                  * Otherwise, fall through to calling dcphy_status()
  279                  * since real Intel 21143 chips don't show valid link
  280                  * status until autonegotiation is switched off, and
  281                  * that only happens in dcphy_status().  Without this,
  282                  * successful autonegotiation is never recognised on
  283                  * these chips.
  284                  */
  285                 if (++sc->mii_ticks <= 50)
  286                         break;
  287 
  288                 sc->mii_ticks = 0;
  289                 dcphy_auto(sc);
  290 
  291                 break;
  292         }
  293 
  294         /* Update the media status. */
  295         dcphy_status(sc);
  296 
  297         /* Callback if something changed. */
  298         mii_phy_update(sc, cmd);
  299         return (0);
  300 }
  301 
  302 static void
  303 dcphy_status(struct mii_softc *sc)
  304 {
  305         struct mii_data *mii = sc->mii_pdata;
  306         int anlpar, tstat;
  307         struct dc_softc         *dc_sc;
  308 
  309         dc_sc = mii->mii_ifp->if_softc;
  310 
  311         mii->mii_media_status = IFM_AVALID;
  312         mii->mii_media_active = IFM_ETHER;
  313 
  314         if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
  315                 return;
  316 
  317         tstat = CSR_READ_4(dc_sc, DC_10BTSTAT);
  318         if (!(tstat & DC_TSTAT_LS10) || !(tstat & DC_TSTAT_LS100))
  319                 mii->mii_media_status |= IFM_ACTIVE;
  320 
  321         if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) {
  322                 /* Erg, still trying, I guess... */
  323                 if ((tstat & DC_TSTAT_ANEGSTAT) != DC_ASTAT_AUTONEGCMP) {
  324                         if ((DC_IS_MACRONIX(dc_sc) || DC_IS_PNICII(dc_sc)) &&
  325                             (tstat & DC_TSTAT_ANEGSTAT) == DC_ASTAT_DISABLE)
  326                                 goto skip;
  327                         mii->mii_media_active |= IFM_NONE;
  328                         return;
  329                 }
  330 
  331                 if (tstat & DC_TSTAT_LP_CAN_NWAY) {
  332                         anlpar = tstat >> 16;
  333                         if (anlpar & ANLPAR_TX_FD &&
  334                             sc->mii_capabilities & BMSR_100TXFDX)
  335                                 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
  336                         else if (anlpar & ANLPAR_T4 &&
  337                             sc->mii_capabilities & BMSR_100T4)
  338                                 mii->mii_media_active |= IFM_100_T4 | IFM_HDX;
  339                         else if (anlpar & ANLPAR_TX &&
  340                             sc->mii_capabilities & BMSR_100TXHDX)
  341                                 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
  342                         else if (anlpar & ANLPAR_10_FD)
  343                                 mii->mii_media_active |= IFM_10_T | IFM_FDX;
  344                         else if (anlpar & ANLPAR_10)
  345                                 mii->mii_media_active |= IFM_10_T | IFM_HDX;
  346                         else
  347                                 mii->mii_media_active |= IFM_NONE;
  348                         if (DC_IS_INTEL(dc_sc))
  349                                 DC_CLRBIT(dc_sc, DC_10BTCTRL,
  350                                     DC_TCTL_AUTONEGENBL);
  351                         return;
  352                 }
  353 
  354                 /*
  355                  * If the other side doesn't support NWAY, then the
  356                  * best we can do is determine if we have a 10Mbps or
  357                  * 100Mbps link.  There's no way to know if the link
  358                  * is full or half duplex, so we default to half duplex
  359                  * and hope that the user is clever enough to manually
  360                  * change the media settings if we're wrong.
  361                  */
  362                 if (!(tstat & DC_TSTAT_LS100))
  363                         mii->mii_media_active |= IFM_100_TX | IFM_HDX;
  364                 else if (!(tstat & DC_TSTAT_LS10))
  365                         mii->mii_media_active |= IFM_10_T | IFM_HDX;
  366                 else
  367                         mii->mii_media_active |= IFM_NONE;
  368                 if (DC_IS_INTEL(dc_sc))
  369                         DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
  370                 return;
  371         }
  372 
  373 skip:
  374         if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)
  375                 mii->mii_media_active |= IFM_10_T;
  376         else
  377                 mii->mii_media_active |= IFM_100_TX;
  378         if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
  379                 mii->mii_media_active |= IFM_FDX;
  380         else
  381                 mii->mii_media_active |= IFM_HDX;
  382 }
  383 
  384 static int
  385 dcphy_auto(struct mii_softc *mii)
  386 {
  387         struct dc_softc         *sc;
  388 
  389         sc = mii->mii_pdata->mii_ifp->if_softc;
  390 
  391         DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
  392         DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
  393         DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
  394         if (mii->mii_capabilities & BMSR_100TXHDX)
  395                 CSR_WRITE_4(sc, DC_10BTCTRL, 0x3FFFF);
  396         else
  397                 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFF);
  398         DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
  399         DC_SETBIT(sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
  400         DC_SETBIT(sc, DC_10BTSTAT, DC_ASTAT_TXDISABLE);
  401 
  402         return (EJUSTRETURN);
  403 }
  404 
  405 static void
  406 dcphy_reset(struct mii_softc *mii)
  407 {
  408         struct dc_softc         *sc;
  409 
  410         sc = mii->mii_pdata->mii_ifp->if_softc;
  411 
  412         DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
  413         DELAY(1000);
  414         DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
  415 }

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