Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/dc/if_dc.c
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1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/8.4/sys/dev/dc/if_dc.c 242909 2012-11-12 07:47:19Z dim $"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN983 (www.admtek.com.tw) 47 * ADMtek CardBus AN985 (www.admtek.com.tw) 48 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985 49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 50 * Accton EN1217 (www.accton.com) 51 * Xircom X3201 (www.xircom.com) 52 * Abocom FE2500 53 * Conexant LANfinity (www.conexant.com) 54 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 55 * 56 * Datasheets for the 21143 are available at developer.intel.com. 57 * Datasheets for the clone parts can be found at their respective sites. 58 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 59 * The PNIC II is essentially a Macronix 98715A chip; the only difference 60 * worth noting is that its multicast hash table is only 128 bits wide 61 * instead of 512. 62 * 63 * Written by Bill Paul <wpaul@ee.columbia.edu> 64 * Electrical Engineering Department 65 * Columbia University, New York City 66 */ 67 /* 68 * The Intel 21143 is the successor to the DEC 21140. It is basically 69 * the same as the 21140 but with a few new features. The 21143 supports 70 * three kinds of media attachments: 71 * 72 * o MII port, for 10Mbps and 100Mbps support and NWAY 73 * autonegotiation provided by an external PHY. 74 * o SYM port, for symbol mode 100Mbps support. 75 * o 10baseT port. 76 * o AUI/BNC port. 77 * 78 * The 100Mbps SYM port and 10baseT port can be used together in 79 * combination with the internal NWAY support to create a 10/100 80 * autosensing configuration. 81 * 82 * Note that not all tulip workalikes are handled in this driver: we only 83 * deal with those which are relatively well behaved. The Winbond is 84 * handled separately due to its different register offsets and the 85 * special handling needed for its various bugs. The PNIC is handled 86 * here, but I'm not thrilled about it. 87 * 88 * All of the workalike chips use some form of MII transceiver support 89 * with the exception of the Macronix chips, which also have a SYM port. 90 * The ASIX AX88140A is also documented to have a SYM port, but all 91 * the cards I've seen use an MII transceiver, probably because the 92 * AX88140A doesn't support internal NWAY. 93 */ 94 95 #ifdef HAVE_KERNEL_OPTION_HEADERS 96 #include "opt_device_polling.h" 97 #endif 98 99 #include <sys/param.h> 100 #include <sys/endian.h> 101 #include <sys/systm.h> 102 #include <sys/sockio.h> 103 #include <sys/mbuf.h> 104 #include <sys/malloc.h> 105 #include <sys/kernel.h> 106 #include <sys/module.h> 107 #include <sys/socket.h> 108 109 #include <net/if.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <sys/bus.h> 122 #include <sys/rman.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/mii_bitbang.h> 126 #include <dev/mii/miivar.h> 127 128 #include <dev/pci/pcireg.h> 129 #include <dev/pci/pcivar.h> 130 131 #define DC_USEIOSPACE 132 133 #include <dev/dc/if_dcreg.h> 134 135 #ifdef __sparc64__ 136 #include <dev/ofw/openfirm.h> 137 #include <machine/ofw_machdep.h> 138 #endif 139 140 MODULE_DEPEND(dc, pci, 1, 1, 1); 141 MODULE_DEPEND(dc, ether, 1, 1, 1); 142 MODULE_DEPEND(dc, miibus, 1, 1, 1); 143 144 /* 145 * "device miibus" is required in kernel config. See GENERIC if you get 146 * errors here. 147 */ 148 #include "miibus_if.h" 149 150 /* 151 * Various supported device vendors/types and their names. 152 */ 153 static const struct dc_type dc_devs[] = { 154 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 155 "Intel 21143 10/100BaseTX" }, 156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 157 "Davicom DM9009 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 159 "Davicom DM9100 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 161 "Davicom DM9102A 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 163 "Davicom DM9102 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 165 "ADMtek AL981 10/100BaseTX" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, 167 "ADMtek AN983 10/100BaseTX" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 169 "ADMtek AN985 CardBus 10/100BaseTX or clone" }, 170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 171 "ADMtek ADM9511 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 173 "ADMtek ADM9513 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 175 "ASIX AX88141 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 177 "ASIX AX88140A 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 179 "Macronix 98713A 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 181 "Macronix 98713 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 185 "Compex RL100-TX 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 187 "Macronix 98725 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 189 "Macronix 98715AEC-C 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 191 "Macronix 98715/98715A 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 193 "Macronix 98727/98732 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 195 "LC82C115 PNIC II 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 197 "82c169 PNIC 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 199 "82c168 PNIC 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 201 "Accton EN1217 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 203 "Accton EN2242 MiniPCI 10/100BaseTX" }, 204 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 205 "Xircom X3201 10/100BaseTX" }, 206 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 207 "Neteasy DRP-32TXD Cardbus 10/100" }, 208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 209 "Abocom FE2500 10/100BaseTX" }, 210 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 211 "Abocom FE2500MX 10/100BaseTX" }, 212 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 213 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 214 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 215 "Hawking CB102 CardBus 10/100" }, 216 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 217 "PlaneX FNW-3602-T CardBus 10/100" }, 218 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 219 "3Com OfficeConnect 10/100B" }, 220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 221 "Microsoft MN-120 CardBus 10/100" }, 222 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 223 "Microsoft MN-130 10/100" }, 224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 225 "Linksys PCMPC200 CardBus 10/100" }, 226 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 227 "Linksys PCMPC200 CardBus 10/100" }, 228 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0, 229 "ULi M5261 FastEthernet" }, 230 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0, 231 "ULi M5263 FastEthernet" }, 232 { 0, 0, NULL } 233 }; 234 235 static int dc_probe(device_t); 236 static int dc_attach(device_t); 237 static int dc_detach(device_t); 238 static int dc_suspend(device_t); 239 static int dc_resume(device_t); 240 static const struct dc_type *dc_devtype(device_t); 241 static void dc_discard_rxbuf(struct dc_softc *, int); 242 static int dc_newbuf(struct dc_softc *, int); 243 static int dc_encap(struct dc_softc *, struct mbuf **); 244 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 245 static int dc_rx_resync(struct dc_softc *); 246 static int dc_rxeof(struct dc_softc *); 247 static void dc_txeof(struct dc_softc *); 248 static void dc_tick(void *); 249 static void dc_tx_underrun(struct dc_softc *); 250 static void dc_intr(void *); 251 static void dc_start(struct ifnet *); 252 static void dc_start_locked(struct ifnet *); 253 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 254 static void dc_init(void *); 255 static void dc_init_locked(struct dc_softc *); 256 static void dc_stop(struct dc_softc *); 257 static void dc_watchdog(void *); 258 static int dc_shutdown(device_t); 259 static int dc_ifmedia_upd(struct ifnet *); 260 static int dc_ifmedia_upd_locked(struct dc_softc *); 261 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 262 263 static int dc_dma_alloc(struct dc_softc *); 264 static void dc_dma_free(struct dc_softc *); 265 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int); 266 267 static void dc_delay(struct dc_softc *); 268 static void dc_eeprom_idle(struct dc_softc *); 269 static void dc_eeprom_putbyte(struct dc_softc *, int); 270 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *); 271 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *); 272 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *); 273 static void dc_eeprom_width(struct dc_softc *); 274 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 275 276 static int dc_miibus_readreg(device_t, int, int); 277 static int dc_miibus_writereg(device_t, int, int, int); 278 static void dc_miibus_statchg(device_t); 279 static void dc_miibus_mediainit(device_t); 280 281 static void dc_setcfg(struct dc_softc *, int); 282 static void dc_netcfg_wait(struct dc_softc *); 283 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 284 static uint32_t dc_mchash_be(const uint8_t *); 285 static void dc_setfilt_21143(struct dc_softc *); 286 static void dc_setfilt_asix(struct dc_softc *); 287 static void dc_setfilt_admtek(struct dc_softc *); 288 static void dc_setfilt_uli(struct dc_softc *); 289 static void dc_setfilt_xircom(struct dc_softc *); 290 291 static void dc_setfilt(struct dc_softc *); 292 293 static void dc_reset(struct dc_softc *); 294 static int dc_list_rx_init(struct dc_softc *); 295 static int dc_list_tx_init(struct dc_softc *); 296 297 static int dc_read_srom(struct dc_softc *, int); 298 static int dc_parse_21143_srom(struct dc_softc *); 299 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 300 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 301 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 302 static void dc_apply_fixup(struct dc_softc *, int); 303 static int dc_check_multiport(struct dc_softc *); 304 305 /* 306 * MII bit-bang glue 307 */ 308 static uint32_t dc_mii_bitbang_read(device_t); 309 static void dc_mii_bitbang_write(device_t, uint32_t); 310 311 static const struct mii_bitbang_ops dc_mii_bitbang_ops = { 312 dc_mii_bitbang_read, 313 dc_mii_bitbang_write, 314 { 315 DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 316 DC_SIO_MII_DATAIN, /* MII_BIT_MDI */ 317 DC_SIO_MII_CLK, /* MII_BIT_MDC */ 318 0, /* MII_BIT_DIR_HOST_PHY */ 319 DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */ 320 } 321 }; 322 323 #ifdef DC_USEIOSPACE 324 #define DC_RES SYS_RES_IOPORT 325 #define DC_RID DC_PCI_CFBIO 326 #else 327 #define DC_RES SYS_RES_MEMORY 328 #define DC_RID DC_PCI_CFBMA 329 #endif 330 331 static device_method_t dc_methods[] = { 332 /* Device interface */ 333 DEVMETHOD(device_probe, dc_probe), 334 DEVMETHOD(device_attach, dc_attach), 335 DEVMETHOD(device_detach, dc_detach), 336 DEVMETHOD(device_suspend, dc_suspend), 337 DEVMETHOD(device_resume, dc_resume), 338 DEVMETHOD(device_shutdown, dc_shutdown), 339 340 /* MII interface */ 341 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 342 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 343 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 344 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 345 346 DEVMETHOD_END 347 }; 348 349 static driver_t dc_driver = { 350 "dc", 351 dc_methods, 352 sizeof(struct dc_softc) 353 }; 354 355 static devclass_t dc_devclass; 356 357 DRIVER_MODULE_ORDERED(dc, pci, dc_driver, dc_devclass, NULL, NULL, 358 SI_ORDER_ANY); 359 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, NULL, NULL); 360 361 #define DC_SETBIT(sc, reg, x) \ 362 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 363 364 #define DC_CLRBIT(sc, reg, x) \ 365 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 366 367 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 368 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 369 370 static void 371 dc_delay(struct dc_softc *sc) 372 { 373 int idx; 374 375 for (idx = (300 / 33) + 1; idx > 0; idx--) 376 CSR_READ_4(sc, DC_BUSCTL); 377 } 378 379 static void 380 dc_eeprom_width(struct dc_softc *sc) 381 { 382 int i; 383 384 /* Force EEPROM to idle state. */ 385 dc_eeprom_idle(sc); 386 387 /* Enter EEPROM access mode. */ 388 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 389 dc_delay(sc); 390 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 391 dc_delay(sc); 392 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 393 dc_delay(sc); 394 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 395 dc_delay(sc); 396 397 for (i = 3; i--;) { 398 if (6 & (1 << i)) 399 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 400 else 401 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 402 dc_delay(sc); 403 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 404 dc_delay(sc); 405 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 406 dc_delay(sc); 407 } 408 409 for (i = 1; i <= 12; i++) { 410 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 411 dc_delay(sc); 412 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 413 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 414 dc_delay(sc); 415 break; 416 } 417 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 418 dc_delay(sc); 419 } 420 421 /* Turn off EEPROM access mode. */ 422 dc_eeprom_idle(sc); 423 424 if (i < 4 || i > 12) 425 sc->dc_romwidth = 6; 426 else 427 sc->dc_romwidth = i; 428 429 /* Enter EEPROM access mode. */ 430 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 431 dc_delay(sc); 432 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 433 dc_delay(sc); 434 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 435 dc_delay(sc); 436 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 437 dc_delay(sc); 438 439 /* Turn off EEPROM access mode. */ 440 dc_eeprom_idle(sc); 441 } 442 443 static void 444 dc_eeprom_idle(struct dc_softc *sc) 445 { 446 int i; 447 448 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 449 dc_delay(sc); 450 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 451 dc_delay(sc); 452 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 453 dc_delay(sc); 454 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 455 dc_delay(sc); 456 457 for (i = 0; i < 25; i++) { 458 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 459 dc_delay(sc); 460 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 461 dc_delay(sc); 462 } 463 464 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 465 dc_delay(sc); 466 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 467 dc_delay(sc); 468 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 469 } 470 471 /* 472 * Send a read command and address to the EEPROM, check for ACK. 473 */ 474 static void 475 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 476 { 477 int d, i; 478 479 d = DC_EECMD_READ >> 6; 480 for (i = 3; i--; ) { 481 if (d & (1 << i)) 482 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 483 else 484 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 485 dc_delay(sc); 486 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 487 dc_delay(sc); 488 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 489 dc_delay(sc); 490 } 491 492 /* 493 * Feed in each bit and strobe the clock. 494 */ 495 for (i = sc->dc_romwidth; i--;) { 496 if (addr & (1 << i)) { 497 SIO_SET(DC_SIO_EE_DATAIN); 498 } else { 499 SIO_CLR(DC_SIO_EE_DATAIN); 500 } 501 dc_delay(sc); 502 SIO_SET(DC_SIO_EE_CLK); 503 dc_delay(sc); 504 SIO_CLR(DC_SIO_EE_CLK); 505 dc_delay(sc); 506 } 507 } 508 509 /* 510 * Read a word of data stored in the EEPROM at address 'addr.' 511 * The PNIC 82c168/82c169 has its own non-standard way to read 512 * the EEPROM. 513 */ 514 static void 515 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest) 516 { 517 int i; 518 uint32_t r; 519 520 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 521 522 for (i = 0; i < DC_TIMEOUT; i++) { 523 DELAY(1); 524 r = CSR_READ_4(sc, DC_SIO); 525 if (!(r & DC_PN_SIOCTL_BUSY)) { 526 *dest = (uint16_t)(r & 0xFFFF); 527 return; 528 } 529 } 530 } 531 532 /* 533 * Read a word of data stored in the EEPROM at address 'addr.' 534 * The Xircom X3201 has its own non-standard way to read 535 * the EEPROM, too. 536 */ 537 static void 538 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest) 539 { 540 541 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 542 543 addr *= 2; 544 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 545 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 546 addr += 1; 547 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 548 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 549 550 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 551 } 552 553 /* 554 * Read a word of data stored in the EEPROM at address 'addr.' 555 */ 556 static void 557 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest) 558 { 559 int i; 560 uint16_t word = 0; 561 562 /* Force EEPROM to idle state. */ 563 dc_eeprom_idle(sc); 564 565 /* Enter EEPROM access mode. */ 566 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 567 dc_delay(sc); 568 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 569 dc_delay(sc); 570 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 571 dc_delay(sc); 572 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 573 dc_delay(sc); 574 575 /* 576 * Send address of word we want to read. 577 */ 578 dc_eeprom_putbyte(sc, addr); 579 580 /* 581 * Start reading bits from EEPROM. 582 */ 583 for (i = 0x8000; i; i >>= 1) { 584 SIO_SET(DC_SIO_EE_CLK); 585 dc_delay(sc); 586 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 587 word |= i; 588 dc_delay(sc); 589 SIO_CLR(DC_SIO_EE_CLK); 590 dc_delay(sc); 591 } 592 593 /* Turn off EEPROM access mode. */ 594 dc_eeprom_idle(sc); 595 596 *dest = word; 597 } 598 599 /* 600 * Read a sequence of words from the EEPROM. 601 */ 602 static void 603 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 604 { 605 int i; 606 uint16_t word = 0, *ptr; 607 608 for (i = 0; i < cnt; i++) { 609 if (DC_IS_PNIC(sc)) 610 dc_eeprom_getword_pnic(sc, off + i, &word); 611 else if (DC_IS_XIRCOM(sc)) 612 dc_eeprom_getword_xircom(sc, off + i, &word); 613 else 614 dc_eeprom_getword(sc, off + i, &word); 615 ptr = (uint16_t *)(dest + (i * 2)); 616 if (be) 617 *ptr = be16toh(word); 618 else 619 *ptr = le16toh(word); 620 } 621 } 622 623 /* 624 * Write the MII serial port for the MII bit-bang module. 625 */ 626 static void 627 dc_mii_bitbang_write(device_t dev, uint32_t val) 628 { 629 struct dc_softc *sc; 630 631 sc = device_get_softc(dev); 632 633 CSR_WRITE_4(sc, DC_SIO, val); 634 CSR_BARRIER_4(sc, DC_SIO, 635 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 636 } 637 638 /* 639 * Read the MII serial port for the MII bit-bang module. 640 */ 641 static uint32_t 642 dc_mii_bitbang_read(device_t dev) 643 { 644 struct dc_softc *sc; 645 uint32_t val; 646 647 sc = device_get_softc(dev); 648 649 val = CSR_READ_4(sc, DC_SIO); 650 CSR_BARRIER_4(sc, DC_SIO, 651 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 652 653 return (val); 654 } 655 656 static int 657 dc_miibus_readreg(device_t dev, int phy, int reg) 658 { 659 struct dc_softc *sc; 660 int i, rval, phy_reg = 0; 661 662 sc = device_get_softc(dev); 663 664 if (sc->dc_pmode != DC_PMODE_MII) { 665 if (phy == (MII_NPHY - 1)) { 666 switch (reg) { 667 case MII_BMSR: 668 /* 669 * Fake something to make the probe 670 * code think there's a PHY here. 671 */ 672 return (BMSR_MEDIAMASK); 673 break; 674 case MII_PHYIDR1: 675 if (DC_IS_PNIC(sc)) 676 return (DC_VENDORID_LO); 677 return (DC_VENDORID_DEC); 678 break; 679 case MII_PHYIDR2: 680 if (DC_IS_PNIC(sc)) 681 return (DC_DEVICEID_82C168); 682 return (DC_DEVICEID_21143); 683 break; 684 default: 685 return (0); 686 break; 687 } 688 } else 689 return (0); 690 } 691 692 if (DC_IS_PNIC(sc)) { 693 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 694 (phy << 23) | (reg << 18)); 695 for (i = 0; i < DC_TIMEOUT; i++) { 696 DELAY(1); 697 rval = CSR_READ_4(sc, DC_PN_MII); 698 if (!(rval & DC_PN_MII_BUSY)) { 699 rval &= 0xFFFF; 700 return (rval == 0xFFFF ? 0 : rval); 701 } 702 } 703 return (0); 704 } 705 706 if (sc->dc_type == DC_TYPE_ULI_M5263) { 707 CSR_WRITE_4(sc, DC_ROM, 708 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 709 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 710 DC_ULI_PHY_OP_READ); 711 for (i = 0; i < DC_TIMEOUT; i++) { 712 DELAY(1); 713 rval = CSR_READ_4(sc, DC_ROM); 714 if ((rval & DC_ULI_PHY_OP_DONE) != 0) { 715 return (rval & DC_ULI_PHY_DATA_MASK); 716 } 717 } 718 if (i == DC_TIMEOUT) 719 device_printf(dev, "phy read timed out\n"); 720 return (0); 721 } 722 723 if (DC_IS_COMET(sc)) { 724 switch (reg) { 725 case MII_BMCR: 726 phy_reg = DC_AL_BMCR; 727 break; 728 case MII_BMSR: 729 phy_reg = DC_AL_BMSR; 730 break; 731 case MII_PHYIDR1: 732 phy_reg = DC_AL_VENID; 733 break; 734 case MII_PHYIDR2: 735 phy_reg = DC_AL_DEVID; 736 break; 737 case MII_ANAR: 738 phy_reg = DC_AL_ANAR; 739 break; 740 case MII_ANLPAR: 741 phy_reg = DC_AL_LPAR; 742 break; 743 case MII_ANER: 744 phy_reg = DC_AL_ANER; 745 break; 746 default: 747 device_printf(dev, "phy_read: bad phy register %x\n", 748 reg); 749 return (0); 750 break; 751 } 752 753 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 754 if (rval == 0xFFFF) 755 return (0); 756 return (rval); 757 } 758 759 if (sc->dc_type == DC_TYPE_98713) { 760 phy_reg = CSR_READ_4(sc, DC_NETCFG); 761 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 762 } 763 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg); 764 if (sc->dc_type == DC_TYPE_98713) 765 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 766 767 return (rval); 768 } 769 770 static int 771 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 772 { 773 struct dc_softc *sc; 774 int i, phy_reg = 0; 775 776 sc = device_get_softc(dev); 777 778 if (DC_IS_PNIC(sc)) { 779 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 780 (phy << 23) | (reg << 10) | data); 781 for (i = 0; i < DC_TIMEOUT; i++) { 782 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 783 break; 784 } 785 return (0); 786 } 787 788 if (sc->dc_type == DC_TYPE_ULI_M5263) { 789 CSR_WRITE_4(sc, DC_ROM, 790 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 791 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 792 ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) | 793 DC_ULI_PHY_OP_WRITE); 794 DELAY(1); 795 return (0); 796 } 797 798 if (DC_IS_COMET(sc)) { 799 switch (reg) { 800 case MII_BMCR: 801 phy_reg = DC_AL_BMCR; 802 break; 803 case MII_BMSR: 804 phy_reg = DC_AL_BMSR; 805 break; 806 case MII_PHYIDR1: 807 phy_reg = DC_AL_VENID; 808 break; 809 case MII_PHYIDR2: 810 phy_reg = DC_AL_DEVID; 811 break; 812 case MII_ANAR: 813 phy_reg = DC_AL_ANAR; 814 break; 815 case MII_ANLPAR: 816 phy_reg = DC_AL_LPAR; 817 break; 818 case MII_ANER: 819 phy_reg = DC_AL_ANER; 820 break; 821 default: 822 device_printf(dev, "phy_write: bad phy register %x\n", 823 reg); 824 return (0); 825 break; 826 } 827 828 CSR_WRITE_4(sc, phy_reg, data); 829 return (0); 830 } 831 832 if (sc->dc_type == DC_TYPE_98713) { 833 phy_reg = CSR_READ_4(sc, DC_NETCFG); 834 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 835 } 836 mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data); 837 if (sc->dc_type == DC_TYPE_98713) 838 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 839 840 return (0); 841 } 842 843 static void 844 dc_miibus_statchg(device_t dev) 845 { 846 struct dc_softc *sc; 847 struct ifnet *ifp; 848 struct mii_data *mii; 849 struct ifmedia *ifm; 850 851 sc = device_get_softc(dev); 852 853 mii = device_get_softc(sc->dc_miibus); 854 ifp = sc->dc_ifp; 855 if (mii == NULL || ifp == NULL || 856 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 857 return; 858 859 ifm = &mii->mii_media; 860 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 861 dc_setcfg(sc, ifm->ifm_media); 862 return; 863 } else if (!DC_IS_ADMTEK(sc)) 864 dc_setcfg(sc, mii->mii_media_active); 865 866 sc->dc_link = 0; 867 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 868 (IFM_ACTIVE | IFM_AVALID)) { 869 switch (IFM_SUBTYPE(mii->mii_media_active)) { 870 case IFM_10_T: 871 case IFM_100_TX: 872 sc->dc_link = 1; 873 break; 874 } 875 } 876 } 877 878 /* 879 * Special support for DM9102A cards with HomePNA PHYs. Note: 880 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 881 * to be impossible to talk to the management interface of the DM9801 882 * PHY (its MDIO pin is not connected to anything). Consequently, 883 * the driver has to just 'know' about the additional mode and deal 884 * with it itself. *sigh* 885 */ 886 static void 887 dc_miibus_mediainit(device_t dev) 888 { 889 struct dc_softc *sc; 890 struct mii_data *mii; 891 struct ifmedia *ifm; 892 int rev; 893 894 rev = pci_get_revid(dev); 895 896 sc = device_get_softc(dev); 897 mii = device_get_softc(sc->dc_miibus); 898 ifm = &mii->mii_media; 899 900 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 901 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 902 } 903 904 #define DC_BITS_512 9 905 #define DC_BITS_128 7 906 #define DC_BITS_64 6 907 908 static uint32_t 909 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 910 { 911 uint32_t crc; 912 913 /* Compute CRC for the address value. */ 914 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 915 916 /* 917 * The hash table on the PNIC II and the MX98715AEC-C/D/E 918 * chips is only 128 bits wide. 919 */ 920 if (sc->dc_flags & DC_128BIT_HASH) 921 return (crc & ((1 << DC_BITS_128) - 1)); 922 923 /* The hash table on the MX98715BEC is only 64 bits wide. */ 924 if (sc->dc_flags & DC_64BIT_HASH) 925 return (crc & ((1 << DC_BITS_64) - 1)); 926 927 /* Xircom's hash filtering table is different (read: weird) */ 928 /* Xircom uses the LEAST significant bits */ 929 if (DC_IS_XIRCOM(sc)) { 930 if ((crc & 0x180) == 0x180) 931 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 932 else 933 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 934 (12 << 4)); 935 } 936 937 return (crc & ((1 << DC_BITS_512) - 1)); 938 } 939 940 /* 941 * Calculate CRC of a multicast group address, return the lower 6 bits. 942 */ 943 static uint32_t 944 dc_mchash_be(const uint8_t *addr) 945 { 946 uint32_t crc; 947 948 /* Compute CRC for the address value. */ 949 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 950 951 /* Return the filter bit position. */ 952 return ((crc >> 26) & 0x0000003F); 953 } 954 955 /* 956 * 21143-style RX filter setup routine. Filter programming is done by 957 * downloading a special setup frame into the TX engine. 21143, Macronix, 958 * PNIC, PNIC II and Davicom chips are programmed this way. 959 * 960 * We always program the chip using 'hash perfect' mode, i.e. one perfect 961 * address (our node address) and a 512-bit hash filter for multicast 962 * frames. We also sneak the broadcast address into the hash filter since 963 * we need that too. 964 */ 965 static void 966 dc_setfilt_21143(struct dc_softc *sc) 967 { 968 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 969 struct dc_desc *sframe; 970 uint32_t h, *sp; 971 struct ifmultiaddr *ifma; 972 struct ifnet *ifp; 973 int i; 974 975 ifp = sc->dc_ifp; 976 977 i = sc->dc_cdata.dc_tx_prod; 978 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 979 sc->dc_cdata.dc_tx_cnt++; 980 sframe = &sc->dc_ldata.dc_tx_list[i]; 981 sp = sc->dc_cdata.dc_sbuf; 982 bzero(sp, DC_SFRAME_LEN); 983 984 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 985 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 986 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 987 988 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 989 990 /* If we want promiscuous mode, set the allframes bit. */ 991 if (ifp->if_flags & IFF_PROMISC) 992 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 993 else 994 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 995 996 if (ifp->if_flags & IFF_ALLMULTI) 997 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 998 else 999 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1000 1001 if_maddr_rlock(ifp); 1002 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1003 if (ifma->ifma_addr->sa_family != AF_LINK) 1004 continue; 1005 h = dc_mchash_le(sc, 1006 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1007 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1008 } 1009 if_maddr_runlock(ifp); 1010 1011 if (ifp->if_flags & IFF_BROADCAST) { 1012 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1013 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1014 } 1015 1016 /* Set our MAC address. */ 1017 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1018 sp[39] = DC_SP_MAC(eaddr[0]); 1019 sp[40] = DC_SP_MAC(eaddr[1]); 1020 sp[41] = DC_SP_MAC(eaddr[2]); 1021 1022 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1023 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1024 BUS_DMASYNC_PREWRITE); 1025 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1026 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1027 1028 /* 1029 * The PNIC takes an exceedingly long time to process its 1030 * setup frame; wait 10ms after posting the setup frame 1031 * before proceeding, just so it has time to swallow its 1032 * medicine. 1033 */ 1034 DELAY(10000); 1035 1036 sc->dc_wdog_timer = 5; 1037 } 1038 1039 static void 1040 dc_setfilt_admtek(struct dc_softc *sc) 1041 { 1042 uint8_t eaddr[ETHER_ADDR_LEN]; 1043 struct ifnet *ifp; 1044 struct ifmultiaddr *ifma; 1045 int h = 0; 1046 uint32_t hashes[2] = { 0, 0 }; 1047 1048 ifp = sc->dc_ifp; 1049 1050 /* Init our MAC address. */ 1051 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1052 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1053 eaddr[1] << 8 | eaddr[0]); 1054 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1055 1056 /* If we want promiscuous mode, set the allframes bit. */ 1057 if (ifp->if_flags & IFF_PROMISC) 1058 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1059 else 1060 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1061 1062 if (ifp->if_flags & IFF_ALLMULTI) 1063 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1064 else 1065 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1066 1067 /* First, zot all the existing hash bits. */ 1068 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1069 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1070 1071 /* 1072 * If we're already in promisc or allmulti mode, we 1073 * don't have to bother programming the multicast filter. 1074 */ 1075 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1076 return; 1077 1078 /* Now program new ones. */ 1079 if_maddr_rlock(ifp); 1080 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1081 if (ifma->ifma_addr->sa_family != AF_LINK) 1082 continue; 1083 if (DC_IS_CENTAUR(sc)) 1084 h = dc_mchash_le(sc, 1085 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1086 else 1087 h = dc_mchash_be( 1088 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1089 if (h < 32) 1090 hashes[0] |= (1 << h); 1091 else 1092 hashes[1] |= (1 << (h - 32)); 1093 } 1094 if_maddr_runlock(ifp); 1095 1096 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1097 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1098 } 1099 1100 static void 1101 dc_setfilt_asix(struct dc_softc *sc) 1102 { 1103 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1104 struct ifnet *ifp; 1105 struct ifmultiaddr *ifma; 1106 int h = 0; 1107 uint32_t hashes[2] = { 0, 0 }; 1108 1109 ifp = sc->dc_ifp; 1110 1111 /* Init our MAC address. */ 1112 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1113 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1114 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1115 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1116 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1117 1118 /* If we want promiscuous mode, set the allframes bit. */ 1119 if (ifp->if_flags & IFF_PROMISC) 1120 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1121 else 1122 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1123 1124 if (ifp->if_flags & IFF_ALLMULTI) 1125 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1126 else 1127 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1128 1129 /* 1130 * The ASIX chip has a special bit to enable reception 1131 * of broadcast frames. 1132 */ 1133 if (ifp->if_flags & IFF_BROADCAST) 1134 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1135 else 1136 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1137 1138 /* first, zot all the existing hash bits */ 1139 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1140 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1141 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1142 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1143 1144 /* 1145 * If we're already in promisc or allmulti mode, we 1146 * don't have to bother programming the multicast filter. 1147 */ 1148 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1149 return; 1150 1151 /* now program new ones */ 1152 if_maddr_rlock(ifp); 1153 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1154 if (ifma->ifma_addr->sa_family != AF_LINK) 1155 continue; 1156 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1157 if (h < 32) 1158 hashes[0] |= (1 << h); 1159 else 1160 hashes[1] |= (1 << (h - 32)); 1161 } 1162 if_maddr_runlock(ifp); 1163 1164 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1165 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1166 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1167 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1168 } 1169 1170 static void 1171 dc_setfilt_uli(struct dc_softc *sc) 1172 { 1173 uint8_t eaddr[ETHER_ADDR_LEN]; 1174 struct ifnet *ifp; 1175 struct ifmultiaddr *ifma; 1176 struct dc_desc *sframe; 1177 uint32_t filter, *sp; 1178 uint8_t *ma; 1179 int i, mcnt; 1180 1181 ifp = sc->dc_ifp; 1182 1183 i = sc->dc_cdata.dc_tx_prod; 1184 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1185 sc->dc_cdata.dc_tx_cnt++; 1186 sframe = &sc->dc_ldata.dc_tx_list[i]; 1187 sp = sc->dc_cdata.dc_sbuf; 1188 bzero(sp, DC_SFRAME_LEN); 1189 1190 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1191 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1192 DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT); 1193 1194 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1195 1196 /* Set station address. */ 1197 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1198 *sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]); 1199 *sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]); 1200 *sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]); 1201 1202 /* Set broadcast address. */ 1203 *sp++ = DC_SP_MAC(0xFFFF); 1204 *sp++ = DC_SP_MAC(0xFFFF); 1205 *sp++ = DC_SP_MAC(0xFFFF); 1206 1207 /* Extract current filter configuration. */ 1208 filter = CSR_READ_4(sc, DC_NETCFG); 1209 filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI); 1210 1211 /* Now build perfect filters. */ 1212 mcnt = 0; 1213 if_maddr_rlock(ifp); 1214 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1215 if (ifma->ifma_addr->sa_family != AF_LINK) 1216 continue; 1217 if (mcnt >= DC_ULI_FILTER_NPERF) { 1218 filter |= DC_NETCFG_RX_ALLMULTI; 1219 break; 1220 } 1221 ma = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1222 *sp++ = DC_SP_MAC(ma[1] << 8 | ma[0]); 1223 *sp++ = DC_SP_MAC(ma[3] << 8 | ma[2]); 1224 *sp++ = DC_SP_MAC(ma[5] << 8 | ma[4]); 1225 mcnt++; 1226 } 1227 if_maddr_runlock(ifp); 1228 1229 for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) { 1230 *sp++ = DC_SP_MAC(0xFFFF); 1231 *sp++ = DC_SP_MAC(0xFFFF); 1232 *sp++ = DC_SP_MAC(0xFFFF); 1233 } 1234 1235 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1236 CSR_WRITE_4(sc, DC_NETCFG, 1237 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1238 if (ifp->if_flags & IFF_PROMISC) 1239 filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI; 1240 if (ifp->if_flags & IFF_ALLMULTI) 1241 filter |= DC_NETCFG_RX_ALLMULTI; 1242 CSR_WRITE_4(sc, DC_NETCFG, 1243 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1244 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1245 CSR_WRITE_4(sc, DC_NETCFG, filter); 1246 1247 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1248 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1249 BUS_DMASYNC_PREWRITE); 1250 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1251 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1252 1253 /* 1254 * Wait some time... 1255 */ 1256 DELAY(1000); 1257 1258 sc->dc_wdog_timer = 5; 1259 } 1260 1261 static void 1262 dc_setfilt_xircom(struct dc_softc *sc) 1263 { 1264 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1265 struct ifnet *ifp; 1266 struct ifmultiaddr *ifma; 1267 struct dc_desc *sframe; 1268 uint32_t h, *sp; 1269 int i; 1270 1271 ifp = sc->dc_ifp; 1272 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1273 1274 i = sc->dc_cdata.dc_tx_prod; 1275 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1276 sc->dc_cdata.dc_tx_cnt++; 1277 sframe = &sc->dc_ldata.dc_tx_list[i]; 1278 sp = sc->dc_cdata.dc_sbuf; 1279 bzero(sp, DC_SFRAME_LEN); 1280 1281 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1282 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1283 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1284 1285 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1286 1287 /* If we want promiscuous mode, set the allframes bit. */ 1288 if (ifp->if_flags & IFF_PROMISC) 1289 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1290 else 1291 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1292 1293 if (ifp->if_flags & IFF_ALLMULTI) 1294 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1295 else 1296 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1297 1298 if_maddr_rlock(ifp); 1299 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1300 if (ifma->ifma_addr->sa_family != AF_LINK) 1301 continue; 1302 h = dc_mchash_le(sc, 1303 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1304 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1305 } 1306 if_maddr_runlock(ifp); 1307 1308 if (ifp->if_flags & IFF_BROADCAST) { 1309 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1310 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1311 } 1312 1313 /* Set our MAC address. */ 1314 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1315 sp[0] = DC_SP_MAC(eaddr[0]); 1316 sp[1] = DC_SP_MAC(eaddr[1]); 1317 sp[2] = DC_SP_MAC(eaddr[2]); 1318 1319 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1320 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1321 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1322 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1323 BUS_DMASYNC_PREWRITE); 1324 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1325 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1326 1327 /* 1328 * Wait some time... 1329 */ 1330 DELAY(1000); 1331 1332 sc->dc_wdog_timer = 5; 1333 } 1334 1335 static void 1336 dc_setfilt(struct dc_softc *sc) 1337 { 1338 1339 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1340 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1341 dc_setfilt_21143(sc); 1342 1343 if (DC_IS_ASIX(sc)) 1344 dc_setfilt_asix(sc); 1345 1346 if (DC_IS_ADMTEK(sc)) 1347 dc_setfilt_admtek(sc); 1348 1349 if (DC_IS_ULI(sc)) 1350 dc_setfilt_uli(sc); 1351 1352 if (DC_IS_XIRCOM(sc)) 1353 dc_setfilt_xircom(sc); 1354 } 1355 1356 static void 1357 dc_netcfg_wait(struct dc_softc *sc) 1358 { 1359 uint32_t isr; 1360 int i; 1361 1362 for (i = 0; i < DC_TIMEOUT; i++) { 1363 isr = CSR_READ_4(sc, DC_ISR); 1364 if (isr & DC_ISR_TX_IDLE && 1365 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1366 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1367 break; 1368 DELAY(10); 1369 } 1370 if (i == DC_TIMEOUT) { 1371 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1372 device_printf(sc->dc_dev, 1373 "%s: failed to force tx to idle state\n", __func__); 1374 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1375 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1376 !DC_HAS_BROKEN_RXSTATE(sc)) 1377 device_printf(sc->dc_dev, 1378 "%s: failed to force rx to idle state\n", __func__); 1379 } 1380 } 1381 1382 /* 1383 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1384 * the netconfig register, we first have to put the transmit and/or 1385 * receive logic in the idle state. 1386 */ 1387 static void 1388 dc_setcfg(struct dc_softc *sc, int media) 1389 { 1390 int restart = 0, watchdogreg; 1391 1392 if (IFM_SUBTYPE(media) == IFM_NONE) 1393 return; 1394 1395 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1396 restart = 1; 1397 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1398 dc_netcfg_wait(sc); 1399 } 1400 1401 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1402 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1403 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1404 if (sc->dc_pmode == DC_PMODE_MII) { 1405 if (DC_IS_INTEL(sc)) { 1406 /* There's a write enable bit here that reads as 1. */ 1407 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1408 watchdogreg &= ~DC_WDOG_CTLWREN; 1409 watchdogreg |= DC_WDOG_JABBERDIS; 1410 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1411 } else { 1412 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1413 } 1414 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1415 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1416 if (sc->dc_type == DC_TYPE_98713) 1417 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1418 DC_NETCFG_SCRAMBLER)); 1419 if (!DC_IS_DAVICOM(sc)) 1420 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1421 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1422 } else { 1423 if (DC_IS_PNIC(sc)) { 1424 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1425 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1426 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1427 } 1428 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1429 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1430 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1431 } 1432 } 1433 1434 if (IFM_SUBTYPE(media) == IFM_10_T) { 1435 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1436 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1437 if (sc->dc_pmode == DC_PMODE_MII) { 1438 /* There's a write enable bit here that reads as 1. */ 1439 if (DC_IS_INTEL(sc)) { 1440 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1441 watchdogreg &= ~DC_WDOG_CTLWREN; 1442 watchdogreg |= DC_WDOG_JABBERDIS; 1443 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1444 } else { 1445 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1446 } 1447 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1448 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1449 if (sc->dc_type == DC_TYPE_98713) 1450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1451 if (!DC_IS_DAVICOM(sc)) 1452 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1453 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1454 } else { 1455 if (DC_IS_PNIC(sc)) { 1456 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1457 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1458 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1459 } 1460 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1461 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1462 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1463 if (DC_IS_INTEL(sc)) { 1464 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1465 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1466 if ((media & IFM_GMASK) == IFM_FDX) 1467 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1468 else 1469 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1470 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1471 DC_CLRBIT(sc, DC_10BTCTRL, 1472 DC_TCTL_AUTONEGENBL); 1473 DELAY(20000); 1474 } 1475 } 1476 } 1477 1478 /* 1479 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1480 * PHY and we want HomePNA mode, set the portsel bit to turn 1481 * on the external MII port. 1482 */ 1483 if (DC_IS_DAVICOM(sc)) { 1484 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1485 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1486 sc->dc_link = 1; 1487 } else { 1488 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1489 } 1490 } 1491 1492 if ((media & IFM_GMASK) == IFM_FDX) { 1493 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1494 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1495 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1496 } else { 1497 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1498 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1499 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1500 } 1501 1502 if (restart) 1503 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1504 } 1505 1506 static void 1507 dc_reset(struct dc_softc *sc) 1508 { 1509 int i; 1510 1511 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1512 1513 for (i = 0; i < DC_TIMEOUT; i++) { 1514 DELAY(10); 1515 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1516 break; 1517 } 1518 1519 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1520 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) { 1521 DELAY(10000); 1522 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1523 i = 0; 1524 } 1525 1526 if (i == DC_TIMEOUT) 1527 device_printf(sc->dc_dev, "reset never completed!\n"); 1528 1529 /* Wait a little while for the chip to get its brains in order. */ 1530 DELAY(1000); 1531 1532 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1533 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1534 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1535 1536 /* 1537 * Bring the SIA out of reset. In some cases, it looks 1538 * like failing to unreset the SIA soon enough gets it 1539 * into a state where it will never come out of reset 1540 * until we reset the whole chip again. 1541 */ 1542 if (DC_IS_INTEL(sc)) { 1543 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1544 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF); 1545 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1546 } 1547 } 1548 1549 static const struct dc_type * 1550 dc_devtype(device_t dev) 1551 { 1552 const struct dc_type *t; 1553 uint32_t devid; 1554 uint8_t rev; 1555 1556 t = dc_devs; 1557 devid = pci_get_devid(dev); 1558 rev = pci_get_revid(dev); 1559 1560 while (t->dc_name != NULL) { 1561 if (devid == t->dc_devid && rev >= t->dc_minrev) 1562 return (t); 1563 t++; 1564 } 1565 1566 return (NULL); 1567 } 1568 1569 /* 1570 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1571 * IDs against our list and return a device name if we find a match. 1572 * We do a little bit of extra work to identify the exact type of 1573 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1574 * but different revision IDs. The same is true for 98715/98715A 1575 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1576 * cases, the exact chip revision affects driver behavior. 1577 */ 1578 static int 1579 dc_probe(device_t dev) 1580 { 1581 const struct dc_type *t; 1582 1583 t = dc_devtype(dev); 1584 1585 if (t != NULL) { 1586 device_set_desc(dev, t->dc_name); 1587 return (BUS_PROBE_DEFAULT); 1588 } 1589 1590 return (ENXIO); 1591 } 1592 1593 static void 1594 dc_apply_fixup(struct dc_softc *sc, int media) 1595 { 1596 struct dc_mediainfo *m; 1597 uint8_t *p; 1598 int i; 1599 uint32_t reg; 1600 1601 m = sc->dc_mi; 1602 1603 while (m != NULL) { 1604 if (m->dc_media == media) 1605 break; 1606 m = m->dc_next; 1607 } 1608 1609 if (m == NULL) 1610 return; 1611 1612 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1613 reg = (p[0] | (p[1] << 8)) << 16; 1614 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1615 } 1616 1617 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1618 reg = (p[0] | (p[1] << 8)) << 16; 1619 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1620 } 1621 } 1622 1623 static int 1624 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1625 { 1626 struct dc_mediainfo *m; 1627 1628 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1629 if (m == NULL) { 1630 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1631 return (ENOMEM); 1632 } 1633 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1634 case DC_SIA_CODE_10BT: 1635 m->dc_media = IFM_10_T; 1636 break; 1637 case DC_SIA_CODE_10BT_FDX: 1638 m->dc_media = IFM_10_T | IFM_FDX; 1639 break; 1640 case DC_SIA_CODE_10B2: 1641 m->dc_media = IFM_10_2; 1642 break; 1643 case DC_SIA_CODE_10B5: 1644 m->dc_media = IFM_10_5; 1645 break; 1646 default: 1647 break; 1648 } 1649 1650 /* 1651 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1652 * Things apparently already work for cards that do 1653 * supply Media Specific Data. 1654 */ 1655 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1656 m->dc_gp_len = 2; 1657 m->dc_gp_ptr = 1658 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1659 } else { 1660 m->dc_gp_len = 2; 1661 m->dc_gp_ptr = 1662 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1663 } 1664 1665 m->dc_next = sc->dc_mi; 1666 sc->dc_mi = m; 1667 1668 sc->dc_pmode = DC_PMODE_SIA; 1669 return (0); 1670 } 1671 1672 static int 1673 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1674 { 1675 struct dc_mediainfo *m; 1676 1677 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1678 if (m == NULL) { 1679 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1680 return (ENOMEM); 1681 } 1682 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1683 m->dc_media = IFM_100_TX; 1684 1685 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1686 m->dc_media = IFM_100_TX | IFM_FDX; 1687 1688 m->dc_gp_len = 2; 1689 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl; 1690 1691 m->dc_next = sc->dc_mi; 1692 sc->dc_mi = m; 1693 1694 sc->dc_pmode = DC_PMODE_SYM; 1695 return (0); 1696 } 1697 1698 static int 1699 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1700 { 1701 struct dc_mediainfo *m; 1702 uint8_t *p; 1703 1704 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1705 if (m == NULL) { 1706 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1707 return (ENOMEM); 1708 } 1709 /* We abuse IFM_AUTO to represent MII. */ 1710 m->dc_media = IFM_AUTO; 1711 m->dc_gp_len = l->dc_gpr_len; 1712 1713 p = (uint8_t *)l; 1714 p += sizeof(struct dc_eblock_mii); 1715 m->dc_gp_ptr = p; 1716 p += 2 * l->dc_gpr_len; 1717 m->dc_reset_len = *p; 1718 p++; 1719 m->dc_reset_ptr = p; 1720 1721 m->dc_next = sc->dc_mi; 1722 sc->dc_mi = m; 1723 return (0); 1724 } 1725 1726 static int 1727 dc_read_srom(struct dc_softc *sc, int bits) 1728 { 1729 int size; 1730 1731 size = DC_ROM_SIZE(bits); 1732 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 1733 if (sc->dc_srom == NULL) { 1734 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n"); 1735 return (ENOMEM); 1736 } 1737 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1738 return (0); 1739 } 1740 1741 static int 1742 dc_parse_21143_srom(struct dc_softc *sc) 1743 { 1744 struct dc_leaf_hdr *lhdr; 1745 struct dc_eblock_hdr *hdr; 1746 int error, have_mii, i, loff; 1747 char *ptr; 1748 1749 have_mii = 0; 1750 loff = sc->dc_srom[27]; 1751 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1752 1753 ptr = (char *)lhdr; 1754 ptr += sizeof(struct dc_leaf_hdr) - 1; 1755 /* 1756 * Look if we got a MII media block. 1757 */ 1758 for (i = 0; i < lhdr->dc_mcnt; i++) { 1759 hdr = (struct dc_eblock_hdr *)ptr; 1760 if (hdr->dc_type == DC_EBLOCK_MII) 1761 have_mii++; 1762 1763 ptr += (hdr->dc_len & 0x7F); 1764 ptr++; 1765 } 1766 1767 /* 1768 * Do the same thing again. Only use SIA and SYM media 1769 * blocks if no MII media block is available. 1770 */ 1771 ptr = (char *)lhdr; 1772 ptr += sizeof(struct dc_leaf_hdr) - 1; 1773 error = 0; 1774 for (i = 0; i < lhdr->dc_mcnt; i++) { 1775 hdr = (struct dc_eblock_hdr *)ptr; 1776 switch (hdr->dc_type) { 1777 case DC_EBLOCK_MII: 1778 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1779 break; 1780 case DC_EBLOCK_SIA: 1781 if (! have_mii) 1782 error = dc_decode_leaf_sia(sc, 1783 (struct dc_eblock_sia *)hdr); 1784 break; 1785 case DC_EBLOCK_SYM: 1786 if (! have_mii) 1787 error = dc_decode_leaf_sym(sc, 1788 (struct dc_eblock_sym *)hdr); 1789 break; 1790 default: 1791 /* Don't care. Yet. */ 1792 break; 1793 } 1794 ptr += (hdr->dc_len & 0x7F); 1795 ptr++; 1796 } 1797 return (error); 1798 } 1799 1800 static void 1801 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1802 { 1803 bus_addr_t *paddr; 1804 1805 KASSERT(nseg == 1, 1806 ("%s: wrong number of segments (%d)", __func__, nseg)); 1807 paddr = arg; 1808 *paddr = segs->ds_addr; 1809 } 1810 1811 static int 1812 dc_dma_alloc(struct dc_softc *sc) 1813 { 1814 int error, i; 1815 1816 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0, 1817 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1818 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1819 NULL, NULL, &sc->dc_ptag); 1820 if (error) { 1821 device_printf(sc->dc_dev, 1822 "failed to allocate parent DMA tag\n"); 1823 goto fail; 1824 } 1825 1826 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1827 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1828 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1, 1829 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag); 1830 if (error) { 1831 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n"); 1832 goto fail; 1833 } 1834 1835 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1836 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1, 1837 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag); 1838 if (error) { 1839 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n"); 1840 goto fail; 1841 } 1842 1843 /* RX descriptor list. */ 1844 error = bus_dmamem_alloc(sc->dc_rx_ltag, 1845 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT | 1846 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap); 1847 if (error) { 1848 device_printf(sc->dc_dev, 1849 "failed to allocate DMA'able memory for RX list\n"); 1850 goto fail; 1851 } 1852 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap, 1853 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr, 1854 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT); 1855 if (error) { 1856 device_printf(sc->dc_dev, 1857 "failed to load DMA'able memory for RX list\n"); 1858 goto fail; 1859 } 1860 /* TX descriptor list. */ 1861 error = bus_dmamem_alloc(sc->dc_tx_ltag, 1862 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT | 1863 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap); 1864 if (error) { 1865 device_printf(sc->dc_dev, 1866 "failed to allocate DMA'able memory for TX list\n"); 1867 goto fail; 1868 } 1869 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap, 1870 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr, 1871 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT); 1872 if (error) { 1873 device_printf(sc->dc_dev, 1874 "cannot load DMA'able memory for TX list\n"); 1875 goto fail; 1876 } 1877 1878 /* 1879 * Allocate a busdma tag and DMA safe memory for the multicast 1880 * setup frame. 1881 */ 1882 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1883 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1884 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1885 0, NULL, NULL, &sc->dc_stag); 1886 if (error) { 1887 device_printf(sc->dc_dev, 1888 "failed to create DMA tag for setup frame\n"); 1889 goto fail; 1890 } 1891 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 1892 BUS_DMA_NOWAIT, &sc->dc_smap); 1893 if (error) { 1894 device_printf(sc->dc_dev, 1895 "failed to allocate DMA'able memory for setup frame\n"); 1896 goto fail; 1897 } 1898 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 1899 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 1900 if (error) { 1901 device_printf(sc->dc_dev, 1902 "cannot load DMA'able memory for setup frame\n"); 1903 goto fail; 1904 } 1905 1906 /* Allocate a busdma tag for RX mbufs. */ 1907 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0, 1908 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1909 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag); 1910 if (error) { 1911 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n"); 1912 goto fail; 1913 } 1914 1915 /* Allocate a busdma tag for TX mbufs. */ 1916 error = bus_dma_tag_create(sc->dc_ptag, 1, 0, 1917 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1918 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 1919 0, NULL, NULL, &sc->dc_tx_mtag); 1920 if (error) { 1921 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n"); 1922 goto fail; 1923 } 1924 1925 /* Create the TX/RX busdma maps. */ 1926 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1927 error = bus_dmamap_create(sc->dc_tx_mtag, 0, 1928 &sc->dc_cdata.dc_tx_map[i]); 1929 if (error) { 1930 device_printf(sc->dc_dev, 1931 "failed to create TX mbuf dmamap\n"); 1932 goto fail; 1933 } 1934 } 1935 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1936 error = bus_dmamap_create(sc->dc_rx_mtag, 0, 1937 &sc->dc_cdata.dc_rx_map[i]); 1938 if (error) { 1939 device_printf(sc->dc_dev, 1940 "failed to create RX mbuf dmamap\n"); 1941 goto fail; 1942 } 1943 } 1944 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap); 1945 if (error) { 1946 device_printf(sc->dc_dev, 1947 "failed to create spare RX mbuf dmamap\n"); 1948 goto fail; 1949 } 1950 1951 fail: 1952 return (error); 1953 } 1954 1955 static void 1956 dc_dma_free(struct dc_softc *sc) 1957 { 1958 int i; 1959 1960 /* RX buffers. */ 1961 if (sc->dc_rx_mtag != NULL) { 1962 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1963 if (sc->dc_cdata.dc_rx_map[i] != NULL) 1964 bus_dmamap_destroy(sc->dc_rx_mtag, 1965 sc->dc_cdata.dc_rx_map[i]); 1966 } 1967 if (sc->dc_sparemap != NULL) 1968 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap); 1969 bus_dma_tag_destroy(sc->dc_rx_mtag); 1970 } 1971 1972 /* TX buffers. */ 1973 if (sc->dc_rx_mtag != NULL) { 1974 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1975 if (sc->dc_cdata.dc_tx_map[i] != NULL) 1976 bus_dmamap_destroy(sc->dc_tx_mtag, 1977 sc->dc_cdata.dc_tx_map[i]); 1978 } 1979 bus_dma_tag_destroy(sc->dc_tx_mtag); 1980 } 1981 1982 /* RX descriptor list. */ 1983 if (sc->dc_rx_ltag) { 1984 if (sc->dc_rx_lmap != NULL) 1985 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap); 1986 if (sc->dc_rx_lmap != NULL && sc->dc_ldata.dc_rx_list != NULL) 1987 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list, 1988 sc->dc_rx_lmap); 1989 bus_dma_tag_destroy(sc->dc_rx_ltag); 1990 } 1991 1992 /* TX descriptor list. */ 1993 if (sc->dc_tx_ltag) { 1994 if (sc->dc_tx_lmap != NULL) 1995 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap); 1996 if (sc->dc_tx_lmap != NULL && sc->dc_ldata.dc_tx_list != NULL) 1997 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list, 1998 sc->dc_tx_lmap); 1999 bus_dma_tag_destroy(sc->dc_tx_ltag); 2000 } 2001 2002 /* multicast setup frame. */ 2003 if (sc->dc_stag) { 2004 if (sc->dc_smap != NULL) 2005 bus_dmamap_unload(sc->dc_stag, sc->dc_smap); 2006 if (sc->dc_smap != NULL && sc->dc_cdata.dc_sbuf != NULL) 2007 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, 2008 sc->dc_smap); 2009 bus_dma_tag_destroy(sc->dc_stag); 2010 } 2011 } 2012 2013 /* 2014 * Attach the interface. Allocate softc structures, do ifmedia 2015 * setup and ethernet/BPF attach. 2016 */ 2017 static int 2018 dc_attach(device_t dev) 2019 { 2020 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 2021 uint32_t command; 2022 struct dc_softc *sc; 2023 struct ifnet *ifp; 2024 struct dc_mediainfo *m; 2025 uint32_t reg, revision; 2026 uint16_t *srom; 2027 int error, mac_offset, n, phy, rid, tmp; 2028 uint8_t *mac; 2029 2030 sc = device_get_softc(dev); 2031 sc->dc_dev = dev; 2032 2033 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2034 MTX_DEF); 2035 2036 /* 2037 * Map control/status registers. 2038 */ 2039 pci_enable_busmaster(dev); 2040 2041 rid = DC_RID; 2042 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 2043 2044 if (sc->dc_res == NULL) { 2045 device_printf(dev, "couldn't map ports/memory\n"); 2046 error = ENXIO; 2047 goto fail; 2048 } 2049 2050 sc->dc_btag = rman_get_bustag(sc->dc_res); 2051 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 2052 2053 /* Allocate interrupt. */ 2054 rid = 0; 2055 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2056 RF_SHAREABLE | RF_ACTIVE); 2057 2058 if (sc->dc_irq == NULL) { 2059 device_printf(dev, "couldn't map interrupt\n"); 2060 error = ENXIO; 2061 goto fail; 2062 } 2063 2064 /* Need this info to decide on a chip type. */ 2065 sc->dc_info = dc_devtype(dev); 2066 revision = pci_get_revid(dev); 2067 2068 error = 0; 2069 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 2070 if (sc->dc_info->dc_devid != 2071 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 2072 sc->dc_info->dc_devid != 2073 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 2074 dc_eeprom_width(sc); 2075 2076 switch (sc->dc_info->dc_devid) { 2077 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 2078 sc->dc_type = DC_TYPE_21143; 2079 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2080 sc->dc_flags |= DC_REDUCED_MII_POLL; 2081 /* Save EEPROM contents so we can parse them later. */ 2082 error = dc_read_srom(sc, sc->dc_romwidth); 2083 if (error != 0) 2084 goto fail; 2085 break; 2086 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 2087 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 2088 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 2089 sc->dc_type = DC_TYPE_DM9102; 2090 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 2091 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 2092 sc->dc_flags |= DC_TX_ALIGN; 2093 sc->dc_pmode = DC_PMODE_MII; 2094 2095 /* Increase the latency timer value. */ 2096 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 2097 break; 2098 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 2099 sc->dc_type = DC_TYPE_AL981; 2100 sc->dc_flags |= DC_TX_USE_TX_INTR; 2101 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2102 sc->dc_pmode = DC_PMODE_MII; 2103 error = dc_read_srom(sc, sc->dc_romwidth); 2104 if (error != 0) 2105 goto fail; 2106 break; 2107 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): 2108 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 2109 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 2110 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 2111 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 2112 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 2113 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 2114 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 2115 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 2116 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 2117 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 2118 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 2119 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 2120 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 2121 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 2122 sc->dc_type = DC_TYPE_AN983; 2123 sc->dc_flags |= DC_64BIT_HASH; 2124 sc->dc_flags |= DC_TX_USE_TX_INTR; 2125 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2126 sc->dc_pmode = DC_PMODE_MII; 2127 /* Don't read SROM for - auto-loaded on reset */ 2128 break; 2129 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 2130 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 2131 if (revision < DC_REVISION_98713A) { 2132 sc->dc_type = DC_TYPE_98713; 2133 } 2134 if (revision >= DC_REVISION_98713A) { 2135 sc->dc_type = DC_TYPE_98713A; 2136 sc->dc_flags |= DC_21143_NWAY; 2137 } 2138 sc->dc_flags |= DC_REDUCED_MII_POLL; 2139 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2140 break; 2141 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 2142 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 2143 /* 2144 * Macronix MX98715AEC-C/D/E parts have only a 2145 * 128-bit hash table. We need to deal with these 2146 * in the same manner as the PNIC II so that we 2147 * get the right number of bits out of the 2148 * CRC routine. 2149 */ 2150 if (revision >= DC_REVISION_98715AEC_C && 2151 revision < DC_REVISION_98725) 2152 sc->dc_flags |= DC_128BIT_HASH; 2153 sc->dc_type = DC_TYPE_987x5; 2154 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2155 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2156 break; 2157 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 2158 sc->dc_type = DC_TYPE_987x5; 2159 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2160 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2161 break; 2162 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 2163 sc->dc_type = DC_TYPE_PNICII; 2164 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2165 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2166 break; 2167 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 2168 sc->dc_type = DC_TYPE_PNIC; 2169 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2170 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2171 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2172 if (sc->dc_pnic_rx_buf == NULL) { 2173 device_printf(sc->dc_dev, 2174 "Could not allocate PNIC RX buffer\n"); 2175 error = ENOMEM; 2176 goto fail; 2177 } 2178 if (revision < DC_REVISION_82C169) 2179 sc->dc_pmode = DC_PMODE_SYM; 2180 break; 2181 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 2182 sc->dc_type = DC_TYPE_ASIX; 2183 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2184 sc->dc_flags |= DC_REDUCED_MII_POLL; 2185 sc->dc_pmode = DC_PMODE_MII; 2186 break; 2187 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 2188 sc->dc_type = DC_TYPE_XIRCOM; 2189 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2190 DC_TX_ALIGN; 2191 /* 2192 * We don't actually need to coalesce, but we're doing 2193 * it to obtain a double word aligned buffer. 2194 * The DC_TX_COALESCE flag is required. 2195 */ 2196 sc->dc_pmode = DC_PMODE_MII; 2197 break; 2198 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 2199 sc->dc_type = DC_TYPE_CONEXANT; 2200 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2201 sc->dc_flags |= DC_REDUCED_MII_POLL; 2202 sc->dc_pmode = DC_PMODE_MII; 2203 error = dc_read_srom(sc, sc->dc_romwidth); 2204 if (error != 0) 2205 goto fail; 2206 break; 2207 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261): 2208 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263): 2209 if (sc->dc_info->dc_devid == 2210 DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261)) 2211 sc->dc_type = DC_TYPE_ULI_M5261; 2212 else 2213 sc->dc_type = DC_TYPE_ULI_M5263; 2214 /* TX buffers should be aligned on 4 byte boundary. */ 2215 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2216 DC_TX_ALIGN; 2217 sc->dc_pmode = DC_PMODE_MII; 2218 error = dc_read_srom(sc, sc->dc_romwidth); 2219 if (error != 0) 2220 goto fail; 2221 break; 2222 default: 2223 device_printf(dev, "unknown device: %x\n", 2224 sc->dc_info->dc_devid); 2225 break; 2226 } 2227 2228 /* Save the cache line size. */ 2229 if (DC_IS_DAVICOM(sc)) 2230 sc->dc_cachesize = 0; 2231 else 2232 sc->dc_cachesize = pci_get_cachelnsz(dev); 2233 2234 /* Reset the adapter. */ 2235 dc_reset(sc); 2236 2237 /* Take 21143 out of snooze mode */ 2238 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2239 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2240 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2241 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2242 } 2243 2244 /* 2245 * Try to learn something about the supported media. 2246 * We know that ASIX and ADMtek and Davicom devices 2247 * will *always* be using MII media, so that's a no-brainer. 2248 * The tricky ones are the Macronix/PNIC II and the 2249 * Intel 21143. 2250 */ 2251 if (DC_IS_INTEL(sc)) { 2252 error = dc_parse_21143_srom(sc); 2253 if (error != 0) 2254 goto fail; 2255 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2256 if (sc->dc_type == DC_TYPE_98713) 2257 sc->dc_pmode = DC_PMODE_MII; 2258 else 2259 sc->dc_pmode = DC_PMODE_SYM; 2260 } else if (!sc->dc_pmode) 2261 sc->dc_pmode = DC_PMODE_MII; 2262 2263 /* 2264 * Get station address from the EEPROM. 2265 */ 2266 switch(sc->dc_type) { 2267 case DC_TYPE_98713: 2268 case DC_TYPE_98713A: 2269 case DC_TYPE_987x5: 2270 case DC_TYPE_PNICII: 2271 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2272 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2273 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2274 break; 2275 case DC_TYPE_PNIC: 2276 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2277 break; 2278 case DC_TYPE_DM9102: 2279 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2280 #ifdef __sparc64__ 2281 /* 2282 * If this is an onboard dc(4) the station address read from 2283 * the EEPROM is all zero and we have to get it from the FCode. 2284 */ 2285 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2286 OF_getetheraddr(dev, (caddr_t)&eaddr); 2287 #endif 2288 break; 2289 case DC_TYPE_21143: 2290 case DC_TYPE_ASIX: 2291 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2292 break; 2293 case DC_TYPE_AL981: 2294 case DC_TYPE_AN983: 2295 reg = CSR_READ_4(sc, DC_AL_PAR0); 2296 mac = (uint8_t *)&eaddr[0]; 2297 mac[0] = (reg >> 0) & 0xff; 2298 mac[1] = (reg >> 8) & 0xff; 2299 mac[2] = (reg >> 16) & 0xff; 2300 mac[3] = (reg >> 24) & 0xff; 2301 reg = CSR_READ_4(sc, DC_AL_PAR1); 2302 mac[4] = (reg >> 0) & 0xff; 2303 mac[5] = (reg >> 8) & 0xff; 2304 break; 2305 case DC_TYPE_CONEXANT: 2306 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2307 ETHER_ADDR_LEN); 2308 break; 2309 case DC_TYPE_XIRCOM: 2310 /* The MAC comes from the CIS. */ 2311 mac = pci_get_ether(dev); 2312 if (!mac) { 2313 device_printf(dev, "No station address in CIS!\n"); 2314 error = ENXIO; 2315 goto fail; 2316 } 2317 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2318 break; 2319 case DC_TYPE_ULI_M5261: 2320 case DC_TYPE_ULI_M5263: 2321 srom = (uint16_t *)sc->dc_srom; 2322 if (srom == NULL || *srom == 0xFFFF || *srom == 0) { 2323 /* 2324 * No valid SROM present, read station address 2325 * from ID Table. 2326 */ 2327 device_printf(dev, 2328 "Reading station address from ID Table.\n"); 2329 CSR_WRITE_4(sc, DC_BUSCTL, 0x10000); 2330 CSR_WRITE_4(sc, DC_SIARESET, 0x01C0); 2331 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2332 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010); 2333 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2334 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2335 CSR_WRITE_4(sc, DC_SIARESET, 0x01B0); 2336 mac = (uint8_t *)eaddr; 2337 for (n = 0; n < ETHER_ADDR_LEN; n++) 2338 mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL); 2339 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2340 CSR_WRITE_4(sc, DC_BUSCTL, 0x0000); 2341 DELAY(10); 2342 } else 2343 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 2344 0); 2345 break; 2346 default: 2347 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2348 break; 2349 } 2350 2351 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr)); 2352 /* 2353 * If we still have invalid station address, see whether we can 2354 * find station address for chip 0. Some multi-port controllers 2355 * just store station address for chip 0 if they have a shared 2356 * SROM. 2357 */ 2358 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) || 2359 (sc->dc_eaddr[0] == 0xffffffff && 2360 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) { 2361 error = dc_check_multiport(sc); 2362 if (error == 0) { 2363 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr)); 2364 /* Extract media information. */ 2365 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) { 2366 while (sc->dc_mi != NULL) { 2367 m = sc->dc_mi->dc_next; 2368 free(sc->dc_mi, M_DEVBUF); 2369 sc->dc_mi = m; 2370 } 2371 error = dc_parse_21143_srom(sc); 2372 if (error != 0) 2373 goto fail; 2374 } 2375 } else if (error == ENOMEM) 2376 goto fail; 2377 else 2378 error = 0; 2379 } 2380 2381 if ((error = dc_dma_alloc(sc)) != 0) 2382 goto fail; 2383 2384 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2385 if (ifp == NULL) { 2386 device_printf(dev, "can not if_alloc()\n"); 2387 error = ENOSPC; 2388 goto fail; 2389 } 2390 ifp->if_softc = sc; 2391 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2392 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2393 ifp->if_ioctl = dc_ioctl; 2394 ifp->if_start = dc_start; 2395 ifp->if_init = dc_init; 2396 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2397 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2398 IFQ_SET_READY(&ifp->if_snd); 2399 2400 /* 2401 * Do MII setup. If this is a 21143, check for a PHY on the 2402 * MII bus after applying any necessary fixups to twiddle the 2403 * GPIO bits. If we don't end up finding a PHY, restore the 2404 * old selection (SIA only or SIA/SYM) and attach the dcphy 2405 * driver instead. 2406 */ 2407 tmp = 0; 2408 if (DC_IS_INTEL(sc)) { 2409 dc_apply_fixup(sc, IFM_AUTO); 2410 tmp = sc->dc_pmode; 2411 sc->dc_pmode = DC_PMODE_MII; 2412 } 2413 2414 /* 2415 * Setup General Purpose port mode and data so the tulip can talk 2416 * to the MII. This needs to be done before mii_attach so that 2417 * we can actually see them. 2418 */ 2419 if (DC_IS_XIRCOM(sc)) { 2420 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2421 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2422 DELAY(10); 2423 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2424 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2425 DELAY(10); 2426 } 2427 2428 phy = MII_PHY_ANY; 2429 /* 2430 * Note: both the AL981 and AN983 have internal PHYs, however the 2431 * AL981 provides direct access to the PHY registers while the AN983 2432 * uses a serial MII interface. The AN983's MII interface is also 2433 * buggy in that you can read from any MII address (0 to 31), but 2434 * only address 1 behaves normally. To deal with both cases, we 2435 * pretend that the PHY is at MII address 1. 2436 */ 2437 if (DC_IS_ADMTEK(sc)) 2438 phy = DC_ADMTEK_PHYADDR; 2439 2440 /* 2441 * Note: the ukphy probes of the RS7112 report a PHY at MII address 2442 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the 2443 * correct one. 2444 */ 2445 if (DC_IS_CONEXANT(sc)) 2446 phy = DC_CONEXANT_PHYADDR; 2447 2448 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2449 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 2450 2451 if (error && DC_IS_INTEL(sc)) { 2452 sc->dc_pmode = tmp; 2453 if (sc->dc_pmode != DC_PMODE_SIA) 2454 sc->dc_pmode = DC_PMODE_SYM; 2455 sc->dc_flags |= DC_21143_NWAY; 2456 /* 2457 * For non-MII cards, we need to have the 21143 2458 * drive the LEDs. Except there are some systems 2459 * like the NEC VersaPro NoteBook PC which have no 2460 * LEDs, and twiddling these bits has adverse effects 2461 * on them. (I.e. you suddenly can't get a link.) 2462 */ 2463 if (!(pci_get_subvendor(dev) == 0x1033 && 2464 pci_get_subdevice(dev) == 0x8028)) 2465 sc->dc_flags |= DC_TULIP_LEDS; 2466 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2467 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 2468 MII_OFFSET_ANY, 0); 2469 } 2470 2471 if (error) { 2472 device_printf(dev, "attaching PHYs failed\n"); 2473 goto fail; 2474 } 2475 2476 if (DC_IS_ADMTEK(sc)) { 2477 /* 2478 * Set automatic TX underrun recovery for the ADMtek chips 2479 */ 2480 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2481 } 2482 2483 /* 2484 * Tell the upper layer(s) we support long frames. 2485 */ 2486 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2487 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2488 ifp->if_capenable = ifp->if_capabilities; 2489 #ifdef DEVICE_POLLING 2490 ifp->if_capabilities |= IFCAP_POLLING; 2491 #endif 2492 2493 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2494 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2495 2496 /* 2497 * Call MI attach routine. 2498 */ 2499 ether_ifattach(ifp, (caddr_t)eaddr); 2500 2501 /* Hook interrupt last to avoid having to lock softc */ 2502 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2503 NULL, dc_intr, sc, &sc->dc_intrhand); 2504 2505 if (error) { 2506 device_printf(dev, "couldn't set up irq\n"); 2507 ether_ifdetach(ifp); 2508 goto fail; 2509 } 2510 2511 fail: 2512 if (error) 2513 dc_detach(dev); 2514 return (error); 2515 } 2516 2517 /* 2518 * Shutdown hardware and free up resources. This can be called any 2519 * time after the mutex has been initialized. It is called in both 2520 * the error case in attach and the normal detach case so it needs 2521 * to be careful about only freeing resources that have actually been 2522 * allocated. 2523 */ 2524 static int 2525 dc_detach(device_t dev) 2526 { 2527 struct dc_softc *sc; 2528 struct ifnet *ifp; 2529 struct dc_mediainfo *m; 2530 2531 sc = device_get_softc(dev); 2532 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2533 2534 ifp = sc->dc_ifp; 2535 2536 #ifdef DEVICE_POLLING 2537 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 2538 ether_poll_deregister(ifp); 2539 #endif 2540 2541 /* These should only be active if attach succeeded */ 2542 if (device_is_attached(dev)) { 2543 DC_LOCK(sc); 2544 dc_stop(sc); 2545 DC_UNLOCK(sc); 2546 callout_drain(&sc->dc_stat_ch); 2547 callout_drain(&sc->dc_wdog_ch); 2548 ether_ifdetach(ifp); 2549 } 2550 if (sc->dc_miibus) 2551 device_delete_child(dev, sc->dc_miibus); 2552 bus_generic_detach(dev); 2553 2554 if (sc->dc_intrhand) 2555 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2556 if (sc->dc_irq) 2557 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2558 if (sc->dc_res) 2559 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2560 2561 if (ifp != NULL) 2562 if_free(ifp); 2563 2564 dc_dma_free(sc); 2565 2566 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2567 2568 while (sc->dc_mi != NULL) { 2569 m = sc->dc_mi->dc_next; 2570 free(sc->dc_mi, M_DEVBUF); 2571 sc->dc_mi = m; 2572 } 2573 free(sc->dc_srom, M_DEVBUF); 2574 2575 mtx_destroy(&sc->dc_mtx); 2576 2577 return (0); 2578 } 2579 2580 /* 2581 * Initialize the transmit descriptors. 2582 */ 2583 static int 2584 dc_list_tx_init(struct dc_softc *sc) 2585 { 2586 struct dc_chain_data *cd; 2587 struct dc_list_data *ld; 2588 int i, nexti; 2589 2590 cd = &sc->dc_cdata; 2591 ld = &sc->dc_ldata; 2592 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2593 if (i == DC_TX_LIST_CNT - 1) 2594 nexti = 0; 2595 else 2596 nexti = i + 1; 2597 ld->dc_tx_list[i].dc_status = 0; 2598 ld->dc_tx_list[i].dc_ctl = 0; 2599 ld->dc_tx_list[i].dc_data = 0; 2600 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2601 cd->dc_tx_chain[i] = NULL; 2602 } 2603 2604 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2605 cd->dc_tx_pkts = 0; 2606 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 2607 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2608 return (0); 2609 } 2610 2611 /* 2612 * Initialize the RX descriptors and allocate mbufs for them. Note that 2613 * we arrange the descriptors in a closed ring, so that the last descriptor 2614 * points back to the first. 2615 */ 2616 static int 2617 dc_list_rx_init(struct dc_softc *sc) 2618 { 2619 struct dc_chain_data *cd; 2620 struct dc_list_data *ld; 2621 int i, nexti; 2622 2623 cd = &sc->dc_cdata; 2624 ld = &sc->dc_ldata; 2625 2626 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2627 if (dc_newbuf(sc, i) != 0) 2628 return (ENOBUFS); 2629 if (i == DC_RX_LIST_CNT - 1) 2630 nexti = 0; 2631 else 2632 nexti = i + 1; 2633 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2634 } 2635 2636 cd->dc_rx_prod = 0; 2637 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2638 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2639 return (0); 2640 } 2641 2642 /* 2643 * Initialize an RX descriptor and attach an MBUF cluster. 2644 */ 2645 static int 2646 dc_newbuf(struct dc_softc *sc, int i) 2647 { 2648 struct mbuf *m; 2649 bus_dmamap_t map; 2650 bus_dma_segment_t segs[1]; 2651 int error, nseg; 2652 2653 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2654 if (m == NULL) 2655 return (ENOBUFS); 2656 m->m_len = m->m_pkthdr.len = MCLBYTES; 2657 m_adj(m, sizeof(u_int64_t)); 2658 2659 /* 2660 * If this is a PNIC chip, zero the buffer. This is part 2661 * of the workaround for the receive bug in the 82c168 and 2662 * 82c169 chips. 2663 */ 2664 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2665 bzero(mtod(m, char *), m->m_len); 2666 2667 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap, 2668 m, segs, &nseg, 0); 2669 if (error) { 2670 m_freem(m); 2671 return (error); 2672 } 2673 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__, 2674 nseg)); 2675 if (sc->dc_cdata.dc_rx_chain[i] != NULL) 2676 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]); 2677 2678 map = sc->dc_cdata.dc_rx_map[i]; 2679 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2680 sc->dc_sparemap = map; 2681 sc->dc_cdata.dc_rx_chain[i] = m; 2682 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2683 BUS_DMASYNC_PREREAD); 2684 2685 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2686 sc->dc_ldata.dc_rx_list[i].dc_data = 2687 htole32(DC_ADDR_LO(segs[0].ds_addr)); 2688 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2689 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2690 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2691 return (0); 2692 } 2693 2694 /* 2695 * Grrrrr. 2696 * The PNIC chip has a terrible bug in it that manifests itself during 2697 * periods of heavy activity. The exact mode of failure if difficult to 2698 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2699 * will happen on slow machines. The bug is that sometimes instead of 2700 * uploading one complete frame during reception, it uploads what looks 2701 * like the entire contents of its FIFO memory. The frame we want is at 2702 * the end of the whole mess, but we never know exactly how much data has 2703 * been uploaded, so salvaging the frame is hard. 2704 * 2705 * There is only one way to do it reliably, and it's disgusting. 2706 * Here's what we know: 2707 * 2708 * - We know there will always be somewhere between one and three extra 2709 * descriptors uploaded. 2710 * 2711 * - We know the desired received frame will always be at the end of the 2712 * total data upload. 2713 * 2714 * - We know the size of the desired received frame because it will be 2715 * provided in the length field of the status word in the last descriptor. 2716 * 2717 * Here's what we do: 2718 * 2719 * - When we allocate buffers for the receive ring, we bzero() them. 2720 * This means that we know that the buffer contents should be all 2721 * zeros, except for data uploaded by the chip. 2722 * 2723 * - We also force the PNIC chip to upload frames that include the 2724 * ethernet CRC at the end. 2725 * 2726 * - We gather all of the bogus frame data into a single buffer. 2727 * 2728 * - We then position a pointer at the end of this buffer and scan 2729 * backwards until we encounter the first non-zero byte of data. 2730 * This is the end of the received frame. We know we will encounter 2731 * some data at the end of the frame because the CRC will always be 2732 * there, so even if the sender transmits a packet of all zeros, 2733 * we won't be fooled. 2734 * 2735 * - We know the size of the actual received frame, so we subtract 2736 * that value from the current pointer location. This brings us 2737 * to the start of the actual received packet. 2738 * 2739 * - We copy this into an mbuf and pass it on, along with the actual 2740 * frame length. 2741 * 2742 * The performance hit is tremendous, but it beats dropping frames all 2743 * the time. 2744 */ 2745 2746 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2747 static void 2748 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2749 { 2750 struct dc_desc *cur_rx; 2751 struct dc_desc *c = NULL; 2752 struct mbuf *m = NULL; 2753 unsigned char *ptr; 2754 int i, total_len; 2755 uint32_t rxstat = 0; 2756 2757 i = sc->dc_pnic_rx_bug_save; 2758 cur_rx = &sc->dc_ldata.dc_rx_list[idx]; 2759 ptr = sc->dc_pnic_rx_buf; 2760 bzero(ptr, DC_RXLEN * 5); 2761 2762 /* Copy all the bytes from the bogus buffers. */ 2763 while (1) { 2764 c = &sc->dc_ldata.dc_rx_list[i]; 2765 rxstat = le32toh(c->dc_status); 2766 m = sc->dc_cdata.dc_rx_chain[i]; 2767 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2768 ptr += DC_RXLEN; 2769 /* If this is the last buffer, break out. */ 2770 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2771 break; 2772 dc_discard_rxbuf(sc, i); 2773 DC_INC(i, DC_RX_LIST_CNT); 2774 } 2775 2776 /* Find the length of the actual receive frame. */ 2777 total_len = DC_RXBYTES(rxstat); 2778 2779 /* Scan backwards until we hit a non-zero byte. */ 2780 while (*ptr == 0x00) 2781 ptr--; 2782 2783 /* Round off. */ 2784 if ((uintptr_t)(ptr) & 0x3) 2785 ptr -= 1; 2786 2787 /* Now find the start of the frame. */ 2788 ptr -= total_len; 2789 if (ptr < sc->dc_pnic_rx_buf) 2790 ptr = sc->dc_pnic_rx_buf; 2791 2792 /* 2793 * Now copy the salvaged frame to the last mbuf and fake up 2794 * the status word to make it look like a successful 2795 * frame reception. 2796 */ 2797 bcopy(ptr, mtod(m, char *), total_len); 2798 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2799 } 2800 2801 /* 2802 * This routine searches the RX ring for dirty descriptors in the 2803 * event that the rxeof routine falls out of sync with the chip's 2804 * current descriptor pointer. This may happen sometimes as a result 2805 * of a "no RX buffer available" condition that happens when the chip 2806 * consumes all of the RX buffers before the driver has a chance to 2807 * process the RX ring. This routine may need to be called more than 2808 * once to bring the driver back in sync with the chip, however we 2809 * should still be getting RX DONE interrupts to drive the search 2810 * for new packets in the RX ring, so we should catch up eventually. 2811 */ 2812 static int 2813 dc_rx_resync(struct dc_softc *sc) 2814 { 2815 struct dc_desc *cur_rx; 2816 int i, pos; 2817 2818 pos = sc->dc_cdata.dc_rx_prod; 2819 2820 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2821 cur_rx = &sc->dc_ldata.dc_rx_list[pos]; 2822 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2823 break; 2824 DC_INC(pos, DC_RX_LIST_CNT); 2825 } 2826 2827 /* If the ring really is empty, then just return. */ 2828 if (i == DC_RX_LIST_CNT) 2829 return (0); 2830 2831 /* We've fallen behing the chip: catch it. */ 2832 sc->dc_cdata.dc_rx_prod = pos; 2833 2834 return (EAGAIN); 2835 } 2836 2837 static void 2838 dc_discard_rxbuf(struct dc_softc *sc, int i) 2839 { 2840 struct mbuf *m; 2841 2842 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2843 m = sc->dc_cdata.dc_rx_chain[i]; 2844 bzero(mtod(m, char *), m->m_len); 2845 } 2846 2847 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2848 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2849 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD | 2850 BUS_DMASYNC_PREWRITE); 2851 } 2852 2853 /* 2854 * A frame has been uploaded: pass the resulting mbuf chain up to 2855 * the higher level protocols. 2856 */ 2857 static int 2858 dc_rxeof(struct dc_softc *sc) 2859 { 2860 struct mbuf *m; 2861 struct ifnet *ifp; 2862 struct dc_desc *cur_rx; 2863 int i, total_len, rx_npkts; 2864 uint32_t rxstat; 2865 2866 DC_LOCK_ASSERT(sc); 2867 2868 ifp = sc->dc_ifp; 2869 rx_npkts = 0; 2870 2871 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD | 2872 BUS_DMASYNC_POSTWRITE); 2873 for (i = sc->dc_cdata.dc_rx_prod; 2874 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2875 DC_INC(i, DC_RX_LIST_CNT)) { 2876 #ifdef DEVICE_POLLING 2877 if (ifp->if_capenable & IFCAP_POLLING) { 2878 if (sc->rxcycles <= 0) 2879 break; 2880 sc->rxcycles--; 2881 } 2882 #endif 2883 cur_rx = &sc->dc_ldata.dc_rx_list[i]; 2884 rxstat = le32toh(cur_rx->dc_status); 2885 if ((rxstat & DC_RXSTAT_OWN) != 0) 2886 break; 2887 m = sc->dc_cdata.dc_rx_chain[i]; 2888 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2889 BUS_DMASYNC_POSTREAD); 2890 total_len = DC_RXBYTES(rxstat); 2891 rx_npkts++; 2892 2893 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2894 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2895 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2896 sc->dc_pnic_rx_bug_save = i; 2897 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) 2898 continue; 2899 dc_pnic_rx_bug_war(sc, i); 2900 rxstat = le32toh(cur_rx->dc_status); 2901 total_len = DC_RXBYTES(rxstat); 2902 } 2903 } 2904 2905 /* 2906 * If an error occurs, update stats, clear the 2907 * status word and leave the mbuf cluster in place: 2908 * it should simply get re-used next time this descriptor 2909 * comes up in the ring. However, don't report long 2910 * frames as errors since they could be vlans. 2911 */ 2912 if ((rxstat & DC_RXSTAT_RXERR)) { 2913 if (!(rxstat & DC_RXSTAT_GIANT) || 2914 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2915 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2916 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2917 ifp->if_ierrors++; 2918 if (rxstat & DC_RXSTAT_COLLSEEN) 2919 ifp->if_collisions++; 2920 dc_discard_rxbuf(sc, i); 2921 if (rxstat & DC_RXSTAT_CRCERR) 2922 continue; 2923 else { 2924 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2925 dc_init_locked(sc); 2926 return (rx_npkts); 2927 } 2928 } 2929 } 2930 2931 /* No errors; receive the packet. */ 2932 total_len -= ETHER_CRC_LEN; 2933 #ifdef __NO_STRICT_ALIGNMENT 2934 /* 2935 * On architectures without alignment problems we try to 2936 * allocate a new buffer for the receive ring, and pass up 2937 * the one where the packet is already, saving the expensive 2938 * copy done in m_devget(). 2939 * If we are on an architecture with alignment problems, or 2940 * if the allocation fails, then use m_devget and leave the 2941 * existing buffer in the receive ring. 2942 */ 2943 if (dc_newbuf(sc, i) != 0) { 2944 dc_discard_rxbuf(sc, i); 2945 ifp->if_iqdrops++; 2946 continue; 2947 } 2948 m->m_pkthdr.rcvif = ifp; 2949 m->m_pkthdr.len = m->m_len = total_len; 2950 #else 2951 { 2952 struct mbuf *m0; 2953 2954 m0 = m_devget(mtod(m, char *), total_len, 2955 ETHER_ALIGN, ifp, NULL); 2956 dc_discard_rxbuf(sc, i); 2957 if (m0 == NULL) { 2958 ifp->if_iqdrops++; 2959 continue; 2960 } 2961 m = m0; 2962 } 2963 #endif 2964 2965 ifp->if_ipackets++; 2966 DC_UNLOCK(sc); 2967 (*ifp->if_input)(ifp, m); 2968 DC_LOCK(sc); 2969 } 2970 2971 sc->dc_cdata.dc_rx_prod = i; 2972 return (rx_npkts); 2973 } 2974 2975 /* 2976 * A frame was downloaded to the chip. It's safe for us to clean up 2977 * the list buffers. 2978 */ 2979 static void 2980 dc_txeof(struct dc_softc *sc) 2981 { 2982 struct dc_desc *cur_tx; 2983 struct ifnet *ifp; 2984 int idx, setup; 2985 uint32_t ctl, txstat; 2986 2987 if (sc->dc_cdata.dc_tx_cnt == 0) 2988 return; 2989 2990 ifp = sc->dc_ifp; 2991 2992 /* 2993 * Go through our tx list and free mbufs for those 2994 * frames that have been transmitted. 2995 */ 2996 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD | 2997 BUS_DMASYNC_POSTWRITE); 2998 setup = 0; 2999 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod; 3000 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) { 3001 cur_tx = &sc->dc_ldata.dc_tx_list[idx]; 3002 txstat = le32toh(cur_tx->dc_status); 3003 ctl = le32toh(cur_tx->dc_ctl); 3004 3005 if (txstat & DC_TXSTAT_OWN) 3006 break; 3007 3008 if (sc->dc_cdata.dc_tx_chain[idx] == NULL) 3009 continue; 3010 3011 if (ctl & DC_TXCTL_SETUP) { 3012 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP); 3013 setup++; 3014 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 3015 BUS_DMASYNC_POSTWRITE); 3016 /* 3017 * Yes, the PNIC is so brain damaged 3018 * that it will sometimes generate a TX 3019 * underrun error while DMAing the RX 3020 * filter setup frame. If we detect this, 3021 * we have to send the setup frame again, 3022 * or else the filter won't be programmed 3023 * correctly. 3024 */ 3025 if (DC_IS_PNIC(sc)) { 3026 if (txstat & DC_TXSTAT_ERRSUM) 3027 dc_setfilt(sc); 3028 } 3029 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3030 continue; 3031 } 3032 3033 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 3034 /* 3035 * XXX: Why does my Xircom taunt me so? 3036 * For some reason it likes setting the CARRLOST flag 3037 * even when the carrier is there. wtf?!? 3038 * Who knows, but Conexant chips have the 3039 * same problem. Maybe they took lessons 3040 * from Xircom. 3041 */ 3042 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3043 sc->dc_pmode == DC_PMODE_MII && 3044 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3045 DC_TXSTAT_NOCARRIER))) 3046 txstat &= ~DC_TXSTAT_ERRSUM; 3047 } else { 3048 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3049 sc->dc_pmode == DC_PMODE_MII && 3050 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3051 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 3052 txstat &= ~DC_TXSTAT_ERRSUM; 3053 } 3054 3055 if (txstat & DC_TXSTAT_ERRSUM) { 3056 ifp->if_oerrors++; 3057 if (txstat & DC_TXSTAT_EXCESSCOLL) 3058 ifp->if_collisions++; 3059 if (txstat & DC_TXSTAT_LATECOLL) 3060 ifp->if_collisions++; 3061 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 3062 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3063 dc_init_locked(sc); 3064 return; 3065 } 3066 } else 3067 ifp->if_opackets++; 3068 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 3069 3070 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3071 BUS_DMASYNC_POSTWRITE); 3072 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3073 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 3074 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3075 } 3076 sc->dc_cdata.dc_tx_cons = idx; 3077 3078 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3079 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3080 if (sc->dc_cdata.dc_tx_cnt == 0) 3081 sc->dc_wdog_timer = 0; 3082 } 3083 if (setup > 0) 3084 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3085 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3086 } 3087 3088 static void 3089 dc_tick(void *xsc) 3090 { 3091 struct dc_softc *sc; 3092 struct mii_data *mii; 3093 struct ifnet *ifp; 3094 uint32_t r; 3095 3096 sc = xsc; 3097 DC_LOCK_ASSERT(sc); 3098 ifp = sc->dc_ifp; 3099 mii = device_get_softc(sc->dc_miibus); 3100 3101 /* 3102 * Reclaim transmitted frames for controllers that do 3103 * not generate TX completion interrupt for every frame. 3104 */ 3105 if (sc->dc_flags & DC_TX_USE_TX_INTR) 3106 dc_txeof(sc); 3107 3108 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 3109 if (sc->dc_flags & DC_21143_NWAY) { 3110 r = CSR_READ_4(sc, DC_10BTSTAT); 3111 if (IFM_SUBTYPE(mii->mii_media_active) == 3112 IFM_100_TX && (r & DC_TSTAT_LS100)) { 3113 sc->dc_link = 0; 3114 mii_mediachg(mii); 3115 } 3116 if (IFM_SUBTYPE(mii->mii_media_active) == 3117 IFM_10_T && (r & DC_TSTAT_LS10)) { 3118 sc->dc_link = 0; 3119 mii_mediachg(mii); 3120 } 3121 if (sc->dc_link == 0) 3122 mii_tick(mii); 3123 } else { 3124 /* 3125 * For NICs which never report DC_RXSTATE_WAIT, we 3126 * have to bite the bullet... 3127 */ 3128 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 3129 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 3130 sc->dc_cdata.dc_tx_cnt == 0) 3131 mii_tick(mii); 3132 } 3133 } else 3134 mii_tick(mii); 3135 3136 /* 3137 * When the init routine completes, we expect to be able to send 3138 * packets right away, and in fact the network code will send a 3139 * gratuitous ARP the moment the init routine marks the interface 3140 * as running. However, even though the MAC may have been initialized, 3141 * there may be a delay of a few seconds before the PHY completes 3142 * autonegotiation and the link is brought up. Any transmissions 3143 * made during that delay will be lost. Dealing with this is tricky: 3144 * we can't just pause in the init routine while waiting for the 3145 * PHY to come ready since that would bring the whole system to 3146 * a screeching halt for several seconds. 3147 * 3148 * What we do here is prevent the TX start routine from sending 3149 * any packets until a link has been established. After the 3150 * interface has been initialized, the tick routine will poll 3151 * the state of the PHY until the IFM_ACTIVE flag is set. Until 3152 * that time, packets will stay in the send queue, and once the 3153 * link comes up, they will be flushed out to the wire. 3154 */ 3155 if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3156 dc_start_locked(ifp); 3157 3158 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3159 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3160 else 3161 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3162 } 3163 3164 /* 3165 * A transmit underrun has occurred. Back off the transmit threshold, 3166 * or switch to store and forward mode if we have to. 3167 */ 3168 static void 3169 dc_tx_underrun(struct dc_softc *sc) 3170 { 3171 uint32_t netcfg, isr; 3172 int i, reinit; 3173 3174 reinit = 0; 3175 netcfg = CSR_READ_4(sc, DC_NETCFG); 3176 device_printf(sc->dc_dev, "TX underrun -- "); 3177 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) { 3178 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) { 3179 printf("using store and forward mode\n"); 3180 netcfg |= DC_NETCFG_STORENFWD; 3181 } else { 3182 printf("increasing TX threshold\n"); 3183 sc->dc_txthresh += DC_TXTHRESH_INC; 3184 netcfg &= ~DC_NETCFG_TX_THRESH; 3185 netcfg |= sc->dc_txthresh; 3186 } 3187 3188 if (DC_IS_INTEL(sc)) { 3189 /* 3190 * The real 21143 requires that the transmitter be idle 3191 * in order to change the transmit threshold or store 3192 * and forward state. 3193 */ 3194 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON); 3195 3196 for (i = 0; i < DC_TIMEOUT; i++) { 3197 isr = CSR_READ_4(sc, DC_ISR); 3198 if (isr & DC_ISR_TX_IDLE) 3199 break; 3200 DELAY(10); 3201 } 3202 if (i == DC_TIMEOUT) { 3203 device_printf(sc->dc_dev, 3204 "%s: failed to force tx to idle state\n", 3205 __func__); 3206 reinit++; 3207 } 3208 } 3209 } else { 3210 printf("resetting\n"); 3211 reinit++; 3212 } 3213 3214 if (reinit == 0) { 3215 CSR_WRITE_4(sc, DC_NETCFG, netcfg); 3216 if (DC_IS_INTEL(sc)) 3217 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON); 3218 } else { 3219 sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3220 dc_init_locked(sc); 3221 } 3222 } 3223 3224 #ifdef DEVICE_POLLING 3225 static poll_handler_t dc_poll; 3226 3227 static int 3228 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3229 { 3230 struct dc_softc *sc = ifp->if_softc; 3231 int rx_npkts = 0; 3232 3233 DC_LOCK(sc); 3234 3235 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3236 DC_UNLOCK(sc); 3237 return (rx_npkts); 3238 } 3239 3240 sc->rxcycles = count; 3241 rx_npkts = dc_rxeof(sc); 3242 dc_txeof(sc); 3243 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3244 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3245 dc_start_locked(ifp); 3246 3247 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3248 uint32_t status; 3249 3250 status = CSR_READ_4(sc, DC_ISR); 3251 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3252 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3253 DC_ISR_BUS_ERR); 3254 if (!status) { 3255 DC_UNLOCK(sc); 3256 return (rx_npkts); 3257 } 3258 /* ack what we have */ 3259 CSR_WRITE_4(sc, DC_ISR, status); 3260 3261 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3262 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3263 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3264 3265 if (dc_rx_resync(sc)) 3266 dc_rxeof(sc); 3267 } 3268 /* restart transmit unit if necessary */ 3269 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3270 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3271 3272 if (status & DC_ISR_TX_UNDERRUN) 3273 dc_tx_underrun(sc); 3274 3275 if (status & DC_ISR_BUS_ERR) { 3276 if_printf(ifp, "%s: bus error\n", __func__); 3277 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3278 dc_init_locked(sc); 3279 } 3280 } 3281 DC_UNLOCK(sc); 3282 return (rx_npkts); 3283 } 3284 #endif /* DEVICE_POLLING */ 3285 3286 static void 3287 dc_intr(void *arg) 3288 { 3289 struct dc_softc *sc; 3290 struct ifnet *ifp; 3291 uint32_t r, status; 3292 int n; 3293 3294 sc = arg; 3295 3296 if (sc->suspended) 3297 return; 3298 3299 DC_LOCK(sc); 3300 status = CSR_READ_4(sc, DC_ISR); 3301 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) { 3302 DC_UNLOCK(sc); 3303 return; 3304 } 3305 ifp = sc->dc_ifp; 3306 #ifdef DEVICE_POLLING 3307 if (ifp->if_capenable & IFCAP_POLLING) { 3308 DC_UNLOCK(sc); 3309 return; 3310 } 3311 #endif 3312 /* Disable interrupts. */ 3313 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3314 3315 for (n = 16; n > 0; n--) { 3316 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3317 break; 3318 /* Ack interrupts. */ 3319 CSR_WRITE_4(sc, DC_ISR, status); 3320 3321 if (status & DC_ISR_RX_OK) { 3322 if (dc_rxeof(sc) == 0) { 3323 while (dc_rx_resync(sc)) 3324 dc_rxeof(sc); 3325 } 3326 } 3327 3328 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3329 dc_txeof(sc); 3330 3331 if (status & DC_ISR_TX_IDLE) { 3332 dc_txeof(sc); 3333 if (sc->dc_cdata.dc_tx_cnt) { 3334 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3335 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3336 } 3337 } 3338 3339 if (status & DC_ISR_TX_UNDERRUN) 3340 dc_tx_underrun(sc); 3341 3342 if ((status & DC_ISR_RX_WATDOGTIMEO) 3343 || (status & DC_ISR_RX_NOBUF)) { 3344 r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3345 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3346 if (dc_rxeof(sc) == 0) { 3347 while (dc_rx_resync(sc)) 3348 dc_rxeof(sc); 3349 } 3350 } 3351 3352 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3353 dc_start_locked(ifp); 3354 3355 if (status & DC_ISR_BUS_ERR) { 3356 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3357 dc_init_locked(sc); 3358 DC_UNLOCK(sc); 3359 return; 3360 } 3361 status = CSR_READ_4(sc, DC_ISR); 3362 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) 3363 break; 3364 } 3365 3366 /* Re-enable interrupts. */ 3367 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3368 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3369 3370 DC_UNLOCK(sc); 3371 } 3372 3373 /* 3374 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3375 * pointers to the fragment pointers. 3376 */ 3377 static int 3378 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3379 { 3380 bus_dma_segment_t segs[DC_MAXFRAGS]; 3381 bus_dmamap_t map; 3382 struct dc_desc *f; 3383 struct mbuf *m; 3384 int cur, defragged, error, first, frag, i, idx, nseg; 3385 3386 m = NULL; 3387 defragged = 0; 3388 if (sc->dc_flags & DC_TX_COALESCE && 3389 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3390 m = m_defrag(*m_head, M_DONTWAIT); 3391 defragged = 1; 3392 } else { 3393 /* 3394 * Count the number of frags in this chain to see if we 3395 * need to m_collapse. Since the descriptor list is shared 3396 * by all packets, we'll m_collapse long chains so that they 3397 * do not use up the entire list, even if they would fit. 3398 */ 3399 i = 0; 3400 for (m = *m_head; m != NULL; m = m->m_next) 3401 i++; 3402 if (i > DC_TX_LIST_CNT / 4 || 3403 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3404 DC_TX_LIST_RSVD) { 3405 m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); 3406 defragged = 1; 3407 } 3408 } 3409 if (defragged != 0) { 3410 if (m == NULL) { 3411 m_freem(*m_head); 3412 *m_head = NULL; 3413 return (ENOBUFS); 3414 } 3415 *m_head = m; 3416 } 3417 3418 idx = sc->dc_cdata.dc_tx_prod; 3419 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3420 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3421 if (error == EFBIG) { 3422 if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, 3423 DC_MAXFRAGS)) == NULL) { 3424 m_freem(*m_head); 3425 *m_head = NULL; 3426 return (defragged != 0 ? error : ENOBUFS); 3427 } 3428 *m_head = m; 3429 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3430 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3431 if (error != 0) { 3432 m_freem(*m_head); 3433 *m_head = NULL; 3434 return (error); 3435 } 3436 } else if (error != 0) 3437 return (error); 3438 KASSERT(nseg <= DC_MAXFRAGS, 3439 ("%s: wrong number of segments (%d)", __func__, nseg)); 3440 if (nseg == 0) { 3441 m_freem(*m_head); 3442 *m_head = NULL; 3443 return (EIO); 3444 } 3445 3446 /* Check descriptor overruns. */ 3447 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3448 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3449 return (ENOBUFS); 3450 } 3451 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3452 BUS_DMASYNC_PREWRITE); 3453 3454 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3455 for (i = 0; i < nseg; i++) { 3456 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3457 (frag == (DC_TX_LIST_CNT - 1)) && 3458 (first != sc->dc_cdata.dc_tx_first)) { 3459 bus_dmamap_unload(sc->dc_tx_mtag, 3460 sc->dc_cdata.dc_tx_map[first]); 3461 m_freem(*m_head); 3462 *m_head = NULL; 3463 return (ENOBUFS); 3464 } 3465 3466 f = &sc->dc_ldata.dc_tx_list[frag]; 3467 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3468 if (i == 0) { 3469 f->dc_status = 0; 3470 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3471 } else 3472 f->dc_status = htole32(DC_TXSTAT_OWN); 3473 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr)); 3474 cur = frag; 3475 DC_INC(frag, DC_TX_LIST_CNT); 3476 } 3477 3478 sc->dc_cdata.dc_tx_prod = frag; 3479 sc->dc_cdata.dc_tx_cnt += nseg; 3480 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3481 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3482 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3483 sc->dc_ldata.dc_tx_list[first].dc_ctl |= 3484 htole32(DC_TXCTL_FINT); 3485 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3486 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3487 if (sc->dc_flags & DC_TX_USE_TX_INTR && 3488 ++sc->dc_cdata.dc_tx_pkts >= 8) { 3489 sc->dc_cdata.dc_tx_pkts = 0; 3490 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3491 } 3492 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3493 3494 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3495 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3496 3497 /* 3498 * Swap the last and the first dmamaps to ensure the map for 3499 * this transmission is placed at the last descriptor. 3500 */ 3501 map = sc->dc_cdata.dc_tx_map[cur]; 3502 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first]; 3503 sc->dc_cdata.dc_tx_map[first] = map; 3504 3505 return (0); 3506 } 3507 3508 static void 3509 dc_start(struct ifnet *ifp) 3510 { 3511 struct dc_softc *sc; 3512 3513 sc = ifp->if_softc; 3514 DC_LOCK(sc); 3515 dc_start_locked(ifp); 3516 DC_UNLOCK(sc); 3517 } 3518 3519 /* 3520 * Main transmit routine 3521 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3522 * regions directly in the transmit lists. We also save a copy of the 3523 * pointers since the transmit list fragment pointers are physical 3524 * addresses. 3525 */ 3526 static void 3527 dc_start_locked(struct ifnet *ifp) 3528 { 3529 struct dc_softc *sc; 3530 struct mbuf *m_head; 3531 int queued; 3532 3533 sc = ifp->if_softc; 3534 3535 DC_LOCK_ASSERT(sc); 3536 3537 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 3538 IFF_DRV_RUNNING || sc->dc_link == 0) 3539 return; 3540 3541 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3542 3543 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 3544 /* 3545 * If there's no way we can send any packets, return now. 3546 */ 3547 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3548 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3549 break; 3550 } 3551 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3552 if (m_head == NULL) 3553 break; 3554 3555 if (dc_encap(sc, &m_head)) { 3556 if (m_head == NULL) 3557 break; 3558 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3559 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3560 break; 3561 } 3562 3563 queued++; 3564 /* 3565 * If there's a BPF listener, bounce a copy of this frame 3566 * to him. 3567 */ 3568 BPF_MTAP(ifp, m_head); 3569 } 3570 3571 if (queued > 0) { 3572 /* Transmit */ 3573 if (!(sc->dc_flags & DC_TX_POLL)) 3574 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3575 3576 /* 3577 * Set a timeout in case the chip goes out to lunch. 3578 */ 3579 sc->dc_wdog_timer = 5; 3580 } 3581 } 3582 3583 static void 3584 dc_init(void *xsc) 3585 { 3586 struct dc_softc *sc = xsc; 3587 3588 DC_LOCK(sc); 3589 dc_init_locked(sc); 3590 DC_UNLOCK(sc); 3591 } 3592 3593 static void 3594 dc_init_locked(struct dc_softc *sc) 3595 { 3596 struct ifnet *ifp = sc->dc_ifp; 3597 struct mii_data *mii; 3598 struct ifmedia *ifm; 3599 3600 DC_LOCK_ASSERT(sc); 3601 3602 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3603 return; 3604 3605 mii = device_get_softc(sc->dc_miibus); 3606 3607 /* 3608 * Cancel pending I/O and free all RX/TX buffers. 3609 */ 3610 dc_stop(sc); 3611 dc_reset(sc); 3612 if (DC_IS_INTEL(sc)) { 3613 ifm = &mii->mii_media; 3614 dc_apply_fixup(sc, ifm->ifm_media); 3615 } 3616 3617 /* 3618 * Set cache alignment and burst length. 3619 */ 3620 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc)) 3621 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3622 else 3623 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3624 /* 3625 * Evenly share the bus between receive and transmit process. 3626 */ 3627 if (DC_IS_INTEL(sc)) 3628 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3629 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3630 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3631 } else { 3632 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3633 } 3634 if (sc->dc_flags & DC_TX_POLL) 3635 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3636 switch(sc->dc_cachesize) { 3637 case 32: 3638 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3639 break; 3640 case 16: 3641 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3642 break; 3643 case 8: 3644 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3645 break; 3646 case 0: 3647 default: 3648 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3649 break; 3650 } 3651 3652 if (sc->dc_flags & DC_TX_STORENFWD) 3653 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3654 else { 3655 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3656 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3657 } else { 3658 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3659 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3660 } 3661 } 3662 3663 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3664 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3665 3666 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3667 /* 3668 * The app notes for the 98713 and 98715A say that 3669 * in order to have the chips operate properly, a magic 3670 * number must be written to CSR16. Macronix does not 3671 * document the meaning of these bits so there's no way 3672 * to know exactly what they do. The 98713 has a magic 3673 * number all its own; the rest all use a different one. 3674 */ 3675 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3676 if (sc->dc_type == DC_TYPE_98713) 3677 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3678 else 3679 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3680 } 3681 3682 if (DC_IS_XIRCOM(sc)) { 3683 /* 3684 * setup General Purpose Port mode and data so the tulip 3685 * can talk to the MII. 3686 */ 3687 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3688 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3689 DELAY(10); 3690 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3691 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3692 DELAY(10); 3693 } 3694 3695 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3696 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3697 3698 /* Init circular RX list. */ 3699 if (dc_list_rx_init(sc) == ENOBUFS) { 3700 device_printf(sc->dc_dev, 3701 "initialization failed: no memory for rx buffers\n"); 3702 dc_stop(sc); 3703 return; 3704 } 3705 3706 /* 3707 * Init TX descriptors. 3708 */ 3709 dc_list_tx_init(sc); 3710 3711 /* 3712 * Load the address of the RX list. 3713 */ 3714 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3715 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3716 3717 /* 3718 * Enable interrupts. 3719 */ 3720 #ifdef DEVICE_POLLING 3721 /* 3722 * ... but only if we are not polling, and make sure they are off in 3723 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3724 * after a reset. 3725 */ 3726 if (ifp->if_capenable & IFCAP_POLLING) 3727 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3728 else 3729 #endif 3730 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3731 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3732 3733 /* Initialize TX jabber and RX watchdog timer. */ 3734 if (DC_IS_ULI(sc)) 3735 CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK | 3736 DC_WDOG_HOSTUNJAB); 3737 3738 /* Enable transmitter. */ 3739 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3740 3741 /* 3742 * If this is an Intel 21143 and we're not using the 3743 * MII port, program the LED control pins so we get 3744 * link and activity indications. 3745 */ 3746 if (sc->dc_flags & DC_TULIP_LEDS) { 3747 CSR_WRITE_4(sc, DC_WATCHDOG, 3748 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3749 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3750 } 3751 3752 /* 3753 * Load the RX/multicast filter. We do this sort of late 3754 * because the filter programming scheme on the 21143 and 3755 * some clones requires DMAing a setup frame via the TX 3756 * engine, and we need the transmitter enabled for that. 3757 */ 3758 dc_setfilt(sc); 3759 3760 /* Enable receiver. */ 3761 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3762 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3763 3764 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3765 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3766 3767 dc_ifmedia_upd_locked(sc); 3768 3769 /* Clear missed frames and overflow counter. */ 3770 CSR_READ_4(sc, DC_FRAMESDISCARDED); 3771 3772 /* Don't start the ticker if this is a homePNA link. */ 3773 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3774 sc->dc_link = 1; 3775 else { 3776 if (sc->dc_flags & DC_21143_NWAY) 3777 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3778 else 3779 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3780 } 3781 3782 sc->dc_wdog_timer = 0; 3783 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3784 } 3785 3786 /* 3787 * Set media options. 3788 */ 3789 static int 3790 dc_ifmedia_upd(struct ifnet *ifp) 3791 { 3792 struct dc_softc *sc; 3793 int error; 3794 3795 sc = ifp->if_softc; 3796 DC_LOCK(sc); 3797 error = dc_ifmedia_upd_locked(sc); 3798 DC_UNLOCK(sc); 3799 return (error); 3800 } 3801 3802 static int 3803 dc_ifmedia_upd_locked(struct dc_softc *sc) 3804 { 3805 struct mii_data *mii; 3806 struct ifmedia *ifm; 3807 int error; 3808 3809 DC_LOCK_ASSERT(sc); 3810 3811 sc->dc_link = 0; 3812 mii = device_get_softc(sc->dc_miibus); 3813 error = mii_mediachg(mii); 3814 if (error == 0) { 3815 ifm = &mii->mii_media; 3816 if (DC_IS_INTEL(sc)) 3817 dc_setcfg(sc, ifm->ifm_media); 3818 else if (DC_IS_DAVICOM(sc) && 3819 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3820 dc_setcfg(sc, ifm->ifm_media); 3821 } 3822 3823 return (error); 3824 } 3825 3826 /* 3827 * Report current media status. 3828 */ 3829 static void 3830 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3831 { 3832 struct dc_softc *sc; 3833 struct mii_data *mii; 3834 struct ifmedia *ifm; 3835 3836 sc = ifp->if_softc; 3837 mii = device_get_softc(sc->dc_miibus); 3838 DC_LOCK(sc); 3839 mii_pollstat(mii); 3840 ifm = &mii->mii_media; 3841 if (DC_IS_DAVICOM(sc)) { 3842 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3843 ifmr->ifm_active = ifm->ifm_media; 3844 ifmr->ifm_status = 0; 3845 DC_UNLOCK(sc); 3846 return; 3847 } 3848 } 3849 ifmr->ifm_active = mii->mii_media_active; 3850 ifmr->ifm_status = mii->mii_media_status; 3851 DC_UNLOCK(sc); 3852 } 3853 3854 static int 3855 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3856 { 3857 struct dc_softc *sc = ifp->if_softc; 3858 struct ifreq *ifr = (struct ifreq *)data; 3859 struct mii_data *mii; 3860 int error = 0; 3861 3862 switch (command) { 3863 case SIOCSIFFLAGS: 3864 DC_LOCK(sc); 3865 if (ifp->if_flags & IFF_UP) { 3866 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3867 (IFF_PROMISC | IFF_ALLMULTI); 3868 3869 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3870 if (need_setfilt) 3871 dc_setfilt(sc); 3872 } else { 3873 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3874 dc_init_locked(sc); 3875 } 3876 } else { 3877 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3878 dc_stop(sc); 3879 } 3880 sc->dc_if_flags = ifp->if_flags; 3881 DC_UNLOCK(sc); 3882 break; 3883 case SIOCADDMULTI: 3884 case SIOCDELMULTI: 3885 DC_LOCK(sc); 3886 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3887 dc_setfilt(sc); 3888 DC_UNLOCK(sc); 3889 break; 3890 case SIOCGIFMEDIA: 3891 case SIOCSIFMEDIA: 3892 mii = device_get_softc(sc->dc_miibus); 3893 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3894 break; 3895 case SIOCSIFCAP: 3896 #ifdef DEVICE_POLLING 3897 if (ifr->ifr_reqcap & IFCAP_POLLING && 3898 !(ifp->if_capenable & IFCAP_POLLING)) { 3899 error = ether_poll_register(dc_poll, ifp); 3900 if (error) 3901 return(error); 3902 DC_LOCK(sc); 3903 /* Disable interrupts */ 3904 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3905 ifp->if_capenable |= IFCAP_POLLING; 3906 DC_UNLOCK(sc); 3907 return (error); 3908 } 3909 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3910 ifp->if_capenable & IFCAP_POLLING) { 3911 error = ether_poll_deregister(ifp); 3912 /* Enable interrupts. */ 3913 DC_LOCK(sc); 3914 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3915 ifp->if_capenable &= ~IFCAP_POLLING; 3916 DC_UNLOCK(sc); 3917 return (error); 3918 } 3919 #endif /* DEVICE_POLLING */ 3920 break; 3921 default: 3922 error = ether_ioctl(ifp, command, data); 3923 break; 3924 } 3925 3926 return (error); 3927 } 3928 3929 static void 3930 dc_watchdog(void *xsc) 3931 { 3932 struct dc_softc *sc = xsc; 3933 struct ifnet *ifp; 3934 3935 DC_LOCK_ASSERT(sc); 3936 3937 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3938 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3939 return; 3940 } 3941 3942 ifp = sc->dc_ifp; 3943 ifp->if_oerrors++; 3944 device_printf(sc->dc_dev, "watchdog timeout\n"); 3945 3946 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3947 dc_init_locked(sc); 3948 3949 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3950 dc_start_locked(ifp); 3951 } 3952 3953 /* 3954 * Stop the adapter and free any mbufs allocated to the 3955 * RX and TX lists. 3956 */ 3957 static void 3958 dc_stop(struct dc_softc *sc) 3959 { 3960 struct ifnet *ifp; 3961 struct dc_list_data *ld; 3962 struct dc_chain_data *cd; 3963 int i; 3964 uint32_t ctl, netcfg; 3965 3966 DC_LOCK_ASSERT(sc); 3967 3968 ifp = sc->dc_ifp; 3969 ld = &sc->dc_ldata; 3970 cd = &sc->dc_cdata; 3971 3972 callout_stop(&sc->dc_stat_ch); 3973 callout_stop(&sc->dc_wdog_ch); 3974 sc->dc_wdog_timer = 0; 3975 sc->dc_link = 0; 3976 3977 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3978 3979 netcfg = CSR_READ_4(sc, DC_NETCFG); 3980 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3981 CSR_WRITE_4(sc, DC_NETCFG, 3982 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3983 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3984 /* Wait the completion of TX/RX SM. */ 3985 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3986 dc_netcfg_wait(sc); 3987 3988 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3989 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3990 3991 /* 3992 * Free data in the RX lists. 3993 */ 3994 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3995 if (cd->dc_rx_chain[i] != NULL) { 3996 bus_dmamap_sync(sc->dc_rx_mtag, 3997 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD); 3998 bus_dmamap_unload(sc->dc_rx_mtag, 3999 cd->dc_rx_map[i]); 4000 m_freem(cd->dc_rx_chain[i]); 4001 cd->dc_rx_chain[i] = NULL; 4002 } 4003 } 4004 bzero(ld->dc_rx_list, DC_RX_LIST_SZ); 4005 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 4006 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4007 4008 /* 4009 * Free the TX list buffers. 4010 */ 4011 for (i = 0; i < DC_TX_LIST_CNT; i++) { 4012 if (cd->dc_tx_chain[i] != NULL) { 4013 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 4014 if (ctl & DC_TXCTL_SETUP) { 4015 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 4016 BUS_DMASYNC_POSTWRITE); 4017 } else { 4018 bus_dmamap_sync(sc->dc_tx_mtag, 4019 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE); 4020 bus_dmamap_unload(sc->dc_tx_mtag, 4021 cd->dc_tx_map[i]); 4022 m_freem(cd->dc_tx_chain[i]); 4023 } 4024 cd->dc_tx_chain[i] = NULL; 4025 } 4026 } 4027 bzero(ld->dc_tx_list, DC_TX_LIST_SZ); 4028 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 4029 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4030 } 4031 4032 /* 4033 * Device suspend routine. Stop the interface and save some PCI 4034 * settings in case the BIOS doesn't restore them properly on 4035 * resume. 4036 */ 4037 static int 4038 dc_suspend(device_t dev) 4039 { 4040 struct dc_softc *sc; 4041 4042 sc = device_get_softc(dev); 4043 DC_LOCK(sc); 4044 dc_stop(sc); 4045 sc->suspended = 1; 4046 DC_UNLOCK(sc); 4047 4048 return (0); 4049 } 4050 4051 /* 4052 * Device resume routine. Restore some PCI settings in case the BIOS 4053 * doesn't, re-enable busmastering, and restart the interface if 4054 * appropriate. 4055 */ 4056 static int 4057 dc_resume(device_t dev) 4058 { 4059 struct dc_softc *sc; 4060 struct ifnet *ifp; 4061 4062 sc = device_get_softc(dev); 4063 ifp = sc->dc_ifp; 4064 4065 /* reinitialize interface if necessary */ 4066 DC_LOCK(sc); 4067 if (ifp->if_flags & IFF_UP) 4068 dc_init_locked(sc); 4069 4070 sc->suspended = 0; 4071 DC_UNLOCK(sc); 4072 4073 return (0); 4074 } 4075 4076 /* 4077 * Stop all chip I/O so that the kernel's probe routines don't 4078 * get confused by errant DMAs when rebooting. 4079 */ 4080 static int 4081 dc_shutdown(device_t dev) 4082 { 4083 struct dc_softc *sc; 4084 4085 sc = device_get_softc(dev); 4086 4087 DC_LOCK(sc); 4088 dc_stop(sc); 4089 DC_UNLOCK(sc); 4090 4091 return (0); 4092 } 4093 4094 static int 4095 dc_check_multiport(struct dc_softc *sc) 4096 { 4097 struct dc_softc *dsc; 4098 devclass_t dc; 4099 device_t child; 4100 uint8_t *eaddr; 4101 int unit; 4102 4103 dc = devclass_find("dc"); 4104 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) { 4105 child = devclass_get_device(dc, unit); 4106 if (child == NULL) 4107 continue; 4108 if (child == sc->dc_dev) 4109 continue; 4110 if (device_get_parent(child) != device_get_parent(sc->dc_dev)) 4111 continue; 4112 if (unit > device_get_unit(sc->dc_dev)) 4113 continue; 4114 if (device_is_attached(child) == 0) 4115 continue; 4116 dsc = device_get_softc(child); 4117 device_printf(sc->dc_dev, 4118 "Using station address of %s as base\n", 4119 device_get_nameunit(child)); 4120 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN); 4121 eaddr = (uint8_t *)sc->dc_eaddr; 4122 eaddr[5]++; 4123 /* Prepare SROM to parse again. */ 4124 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL && 4125 sc->dc_romwidth != 0) { 4126 free(sc->dc_srom, M_DEVBUF); 4127 sc->dc_romwidth = dsc->dc_romwidth; 4128 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth), 4129 M_DEVBUF, M_NOWAIT); 4130 if (sc->dc_srom == NULL) { 4131 device_printf(sc->dc_dev, 4132 "Could not allocate SROM buffer\n"); 4133 return (ENOMEM); 4134 } 4135 bcopy(dsc->dc_srom, sc->dc_srom, 4136 DC_ROM_SIZE(sc->dc_romwidth)); 4137 } 4138 return (0); 4139 } 4140 return (ENOENT); 4141 }
Cache object: 8714951611fa8e99a719d7044db44022
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