FreeBSD/Linux Kernel Cross Reference
sys/dev/dc/if_dcreg.h
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD$
35 */
36
37 /*
38 * 21143 and clone common register definitions.
39 */
40
41 #define DC_BUSCTL 0x00 /* bus control */
42 #define DC_TXSTART 0x08 /* tx start demand */
43 #define DC_RXSTART 0x10 /* rx start demand */
44 #define DC_RXADDR 0x18 /* rx descriptor list start addr */
45 #define DC_TXADDR 0x20 /* tx descriptor list start addr */
46 #define DC_ISR 0x28 /* interrupt status register */
47 #define DC_NETCFG 0x30 /* network config register */
48 #define DC_IMR 0x38 /* interrupt mask */
49 #define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
50 #define DC_SIO 0x48 /* MII and ROM/EEPROM access */
51 #define DC_ROM 0x50 /* ROM programming address */
52 #define DC_TIMER 0x58 /* general timer */
53 #define DC_10BTSTAT 0x60 /* SIA status */
54 #define DC_SIARESET 0x68 /* SIA connectivity */
55 #define DC_10BTCTRL 0x70 /* SIA transmit and receive */
56 #define DC_WATCHDOG 0x78 /* SIA and general purpose port */
57 #define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */
58
59 /*
60 * There are two general 'types' of MX chips that we need to be
61 * concerned with. One is the original 98713, which has its internal
62 * NWAY support controlled via the MDIO bits in the serial I/O
63 * register. The other is everything else (from the 98713A on up),
64 * which has its internal NWAY controlled via CSR13, CSR14 and CSR15,
65 * just like the 21143. This type setting also governs which of the
66 * 'magic' numbers we write to CSR16. The PNIC II falls into the
67 * 98713A/98715/98715A/98725 category.
68 */
69 #define DC_TYPE_98713 0x1
70 #define DC_TYPE_98713A 0x2
71 #define DC_TYPE_987x5 0x3
72
73 /* Other type of supported chips. */
74 #define DC_TYPE_21143 0x4 /* Intel 21143 */
75 #define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */
76 #define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */
77 #define DC_TYPE_AN983 0x7 /* ADMtek AN983 Centaur */
78 #define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */
79 #define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */
80 #define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */
81 #define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */
82 #define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */
83 #define DC_TYPE_ULI_M5261 0xD /* ALi/ULi M5261 */
84 #define DC_TYPE_ULI_M5263 0xE /* ALi/ULi M5263 */
85
86 #define DC_IS_MACRONIX(x) \
87 (x->dc_type == DC_TYPE_98713 || \
88 x->dc_type == DC_TYPE_98713A || \
89 x->dc_type == DC_TYPE_987x5)
90
91 #define DC_IS_ADMTEK(x) \
92 (x->dc_type == DC_TYPE_AL981 || \
93 x->dc_type == DC_TYPE_AN983)
94
95 #define DC_IS_ULI(x) \
96 (x->dc_type == DC_TYPE_ULI_M5261 || \
97 x->dc_type == DC_TYPE_ULI_M5263)
98
99 #define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143)
100 #define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX)
101 #define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981)
102 #define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN983)
103 #define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102)
104 #define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII)
105 #define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC)
106 #define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM)
107 #define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT)
108
109 /* MII/symbol mode port types */
110 #define DC_PMODE_MII 0x1
111 #define DC_PMODE_SYM 0x2
112 #define DC_PMODE_SIA 0x3
113
114 /*
115 * Bus control bits.
116 */
117 #define DC_BUSCTL_RESET 0x00000001
118 #define DC_BUSCTL_ARBITRATION 0x00000002
119 #define DC_BUSCTL_SKIPLEN 0x0000007C
120 #define DC_BUSCTL_BUF_BIGENDIAN 0x00000080
121 #define DC_BUSCTL_BURSTLEN 0x00003F00
122 #define DC_BUSCTL_CACHEALIGN 0x0000C000
123 #define DC_BUSCTL_TXPOLL 0x000E0000
124 #define DC_BUSCTL_DBO 0x00100000
125 #define DC_BUSCTL_MRME 0x00200000
126 #define DC_BUSCTL_MRLE 0x00800000
127 #define DC_BUSCTL_MWIE 0x01000000
128 #define DC_BUSCTL_ONNOW_ENB 0x04000000
129
130 #define DC_SKIPLEN_1LONG 0x00000004
131 #define DC_SKIPLEN_2LONG 0x00000008
132 #define DC_SKIPLEN_3LONG 0x00000010
133 #define DC_SKIPLEN_4LONG 0x00000020
134 #define DC_SKIPLEN_5LONG 0x00000040
135
136 #define DC_CACHEALIGN_NONE 0x00000000
137 #define DC_CACHEALIGN_8LONG 0x00004000
138 #define DC_CACHEALIGN_16LONG 0x00008000
139 #define DC_CACHEALIGN_32LONG 0x0000C000
140
141 #define DC_BURSTLEN_USECA 0x00000000
142 #define DC_BURSTLEN_1LONG 0x00000100
143 #define DC_BURSTLEN_2LONG 0x00000200
144 #define DC_BURSTLEN_4LONG 0x00000400
145 #define DC_BURSTLEN_8LONG 0x00000800
146 #define DC_BURSTLEN_16LONG 0x00001000
147 #define DC_BURSTLEN_32LONG 0x00002000
148
149 #define DC_TXPOLL_OFF 0x00000000
150 #define DC_TXPOLL_1 0x00020000
151 #define DC_TXPOLL_2 0x00040000
152 #define DC_TXPOLL_3 0x00060000
153 #define DC_TXPOLL_4 0x00080000
154 #define DC_TXPOLL_5 0x000A0000
155 #define DC_TXPOLL_6 0x000C0000
156 #define DC_TXPOLL_7 0x000E0000
157
158 /*
159 * Interrupt status bits.
160 */
161 #define DC_ISR_TX_OK 0x00000001
162 #define DC_ISR_TX_IDLE 0x00000002
163 #define DC_ISR_TX_NOBUF 0x00000004
164 #define DC_ISR_TX_JABBERTIMEO 0x00000008
165 #define DC_ISR_LINKGOOD 0x00000010
166 #define DC_ISR_TX_UNDERRUN 0x00000020
167 #define DC_ISR_RX_OK 0x00000040
168 #define DC_ISR_RX_NOBUF 0x00000080
169 #define DC_ISR_RX_READ 0x00000100
170 #define DC_ISR_RX_WATDOGTIMEO 0x00000200
171 #define DC_ISR_TX_EARLY 0x00000400
172 #define DC_ISR_TIMER_EXPIRED 0x00000800
173 #define DC_ISR_LINKFAIL 0x00001000
174 #define DC_ISR_BUS_ERR 0x00002000
175 #define DC_ISR_RX_EARLY 0x00004000
176 #define DC_ISR_ABNORMAL 0x00008000
177 #define DC_ISR_NORMAL 0x00010000
178 #define DC_ISR_RX_STATE 0x000E0000
179 #define DC_ISR_TX_STATE 0x00700000
180 #define DC_ISR_BUSERRTYPE 0x03800000
181 #define DC_ISR_100MBPSLINK 0x08000000
182 #define DC_ISR_MAGICKPACK 0x10000000
183
184 #define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
185 #define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
186 #define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
187 #define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
188 #define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
189 #define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
190 #define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
191 #define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
192
193 #define DC_HAS_BROKEN_RXSTATE(x) \
194 (DC_IS_CENTAUR(x) || DC_IS_CONEXANT(x) || (DC_IS_DAVICOM(x) && \
195 pci_get_revid((x)->dc_dev) >= DC_REVISION_DM9102A))
196
197 #define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */
198 #define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
199 #define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
200 #define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
201 #define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
202 #define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
203 #define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
204 #define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
205
206 /*
207 * Network config bits.
208 */
209 #define DC_NETCFG_RX_HASHPERF 0x00000001
210 #define DC_NETCFG_RX_ON 0x00000002
211 #define DC_NETCFG_RX_HASHONLY 0x00000004
212 #define DC_NETCFG_RX_BADFRAMES 0x00000008
213 #define DC_NETCFG_RX_INVFILT 0x00000010
214 #define DC_NETCFG_BACKOFFCNT 0x00000020
215 #define DC_NETCFG_RX_PROMISC 0x00000040
216 #define DC_NETCFG_RX_ALLMULTI 0x00000080
217 #define DC_NETCFG_FULLDUPLEX 0x00000200
218 #define DC_NETCFG_LOOPBACK 0x00000C00
219 #define DC_NETCFG_FORCECOLL 0x00001000
220 #define DC_NETCFG_TX_ON 0x00002000
221 #define DC_NETCFG_TX_THRESH 0x0000C000
222 #define DC_NETCFG_TX_BACKOFF 0x00020000
223 #define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
224 #define DC_NETCFG_HEARTBEAT 0x00080000
225 #define DC_NETCFG_STORENFWD 0x00200000
226 #define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
227 #define DC_NETCFG_PCS 0x00800000
228 #define DC_NETCFG_SCRAMBLER 0x01000000
229 #define DC_NETCFG_NO_RXCRC 0x02000000
230 #define DC_NETCFG_RX_ALL 0x40000000
231 #define DC_NETCFG_CAPEFFECT 0x80000000
232
233 #define DC_OPMODE_NORM 0x00000000
234 #define DC_OPMODE_INTLOOP 0x00000400
235 #define DC_OPMODE_EXTLOOP 0x00000800
236
237 #if 0
238 #define DC_TXTHRESH_72BYTES 0x00000000
239 #define DC_TXTHRESH_96BYTES 0x00004000
240 #define DC_TXTHRESH_128BYTES 0x00008000
241 #define DC_TXTHRESH_160BYTES 0x0000C000
242 #endif
243
244 #define DC_TXTHRESH_MIN 0x00000000
245 #define DC_TXTHRESH_INC 0x00004000
246 #define DC_TXTHRESH_MAX 0x0000C000
247
248
249 /*
250 * Interrupt mask bits.
251 */
252 #define DC_IMR_TX_OK 0x00000001
253 #define DC_IMR_TX_IDLE 0x00000002
254 #define DC_IMR_TX_NOBUF 0x00000004
255 #define DC_IMR_TX_JABBERTIMEO 0x00000008
256 #define DC_IMR_LINKGOOD 0x00000010
257 #define DC_IMR_TX_UNDERRUN 0x00000020
258 #define DC_IMR_RX_OK 0x00000040
259 #define DC_IMR_RX_NOBUF 0x00000080
260 #define DC_IMR_RX_READ 0x00000100
261 #define DC_IMR_RX_WATDOGTIMEO 0x00000200
262 #define DC_IMR_TX_EARLY 0x00000400
263 #define DC_IMR_TIMER_EXPIRED 0x00000800
264 #define DC_IMR_LINKFAIL 0x00001000
265 #define DC_IMR_BUS_ERR 0x00002000
266 #define DC_IMR_RX_EARLY 0x00004000
267 #define DC_IMR_ABNORMAL 0x00008000
268 #define DC_IMR_NORMAL 0x00010000
269 #define DC_IMR_100MBPSLINK 0x08000000
270 #define DC_IMR_MAGICKPACK 0x10000000
271
272 #define DC_INTRS \
273 (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\
274 DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \
275 DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/)
276 /*
277 * Serial I/O (EEPROM/ROM) bits.
278 */
279 #define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */
280 #define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */
281 #define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
282 #define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
283 #define DC_SIO_ROMDATA4 0x00000010
284 #define DC_SIO_ROMDATA5 0x00000020
285 #define DC_SIO_ROMDATA6 0x00000040
286 #define DC_SIO_ROMDATA7 0x00000080
287 #define DC_SIO_EESEL 0x00000800
288 #define DC_SIO_ROMSEL 0x00001000
289 #define DC_SIO_ROMCTL_WRITE 0x00002000
290 #define DC_SIO_ROMCTL_READ 0x00004000
291 #define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */
292 #define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
293 #define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */
294 #define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
295
296 #define DC_EECMD_WRITE 0x140
297 #define DC_EECMD_READ 0x180
298 #define DC_EECMD_ERASE 0x1c0
299
300 #define DC_EE_NODEADDR_OFFSET 0x70
301 #define DC_EE_NODEADDR 10
302
303 /*
304 * General purpose timer register
305 */
306 #define DC_TIMER_VALUE 0x0000FFFF
307 #define DC_TIMER_CONTINUOUS 0x00010000
308
309 /*
310 * 10baseT status register
311 */
312 #define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */
313 #define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */
314 #define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */
315 #define DC_TSTAT_AUTOPOLARITY 0x00000008
316 #define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */
317 #define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */
318 #define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */
319 #define DC_TSTAT_REMFAULT 0x00000800
320 #define DC_TSTAT_ANEGSTAT 0x00007000
321 #define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */
322 #define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */
323
324 #define DC_ASTAT_DISABLE 0x00000000
325 #define DC_ASTAT_TXDISABLE 0x00001000
326 #define DC_ASTAT_ABDETECT 0x00002000
327 #define DC_ASTAT_ACKDETECT 0x00003000
328 #define DC_ASTAT_CMPACKDETECT 0x00004000
329 #define DC_ASTAT_AUTONEGCMP 0x00005000
330 #define DC_ASTAT_LINKCHECK 0x00006000
331
332 /*
333 * PHY reset register
334 */
335 #define DC_SIA_RESET 0x00000001
336 #define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */
337
338 /*
339 * 10baseT control register
340 */
341 #define DC_TCTL_ENCODER_ENB 0x00000001
342 #define DC_TCTL_LOOPBACK 0x00000002
343 #define DC_TCTL_DRIVER_ENB 0x00000004
344 #define DC_TCTL_LNKPULSE_ENB 0x00000008
345 #define DC_TCTL_HALFDUPLEX 0x00000040
346 #define DC_TCTL_AUTONEGENBL 0x00000080
347 #define DC_TCTL_RX_SQUELCH 0x00000100
348 #define DC_TCTL_COLL_SQUELCH 0x00000200
349 #define DC_TCTL_COLL_DETECT 0x00000400
350 #define DC_TCTL_SQE_ENB 0x00000800
351 #define DC_TCTL_LINKTEST 0x00001000
352 #define DC_TCTL_AUTOPOLARITY 0x00002000
353 #define DC_TCTL_SET_POL_PLUS 0x00004000
354 #define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */
355 #define DC_TCTL_100BTXHALF 0x00010000
356 #define DC_TCTL_100BTXFULL 0x00020000
357 #define DC_TCTL_100BT4 0x00040000
358
359 /*
360 * Watchdog timer register
361 */
362 #define DC_WDOG_JABBERDIS 0x00000001
363 #define DC_WDOG_HOSTUNJAB 0x00000002
364 #define DC_WDOG_JABBERCLK 0x00000004
365 #define DC_WDOG_RXWDOGDIS 0x00000010
366 #define DC_WDOG_RXWDOGCLK 0x00000020
367 #define DC_WDOG_MUSTBEZERO 0x00000100
368 #define DC_WDOG_AUIBNC 0x00100000
369 #define DC_WDOG_ACTIVITY 0x00200000
370 #define DC_WDOG_RX_MATCH 0x00400000
371 #define DC_WDOG_LINK 0x00800000
372 #define DC_WDOG_CTLWREN 0x08000000
373
374 /*
375 * SIA and General Purpose Port register (X3201)
376 */
377 #define DC_SIAGP_RXMATCH 0x40000000
378 #define DC_SIAGP_INT1 0x20000000
379 #define DC_SIAGP_INT0 0x10000000
380 #define DC_SIAGP_WRITE_EN 0x08000000
381 #define DC_SIAGP_RXMATCH_EN 0x04000000
382 #define DC_SIAGP_INT1_EN 0x02000000
383 #define DC_SIAGP_INT0_EN 0x01000000
384 #define DC_SIAGP_LED3 0x00800000
385 #define DC_SIAGP_LED2 0x00400000
386 #define DC_SIAGP_LED1 0x00200000
387 #define DC_SIAGP_LED0 0x00100000
388 #define DC_SIAGP_MD_GP3_OUTPUT 0x00080000
389 #define DC_SIAGP_MD_GP2_OUTPUT 0x00040000
390 #define DC_SIAGP_MD_GP1_OUTPUT 0x00020000
391 #define DC_SIAGP_MD_GP0_OUTPUT 0x00010000
392
393 /*
394 * Size of a setup frame.
395 */
396 #define DC_SFRAME_LEN 192
397
398 /*
399 * 21x4x TX/RX list structure.
400 */
401
402 struct dc_desc {
403 uint32_t dc_status;
404 uint32_t dc_ctl;
405 uint32_t dc_ptr1;
406 uint32_t dc_ptr2;
407 };
408
409 #define dc_data dc_ptr1
410 #define dc_next dc_ptr2
411
412 #define DC_RXSTAT_FIFOOFLOW 0x00000001
413 #define DC_RXSTAT_CRCERR 0x00000002
414 #define DC_RXSTAT_DRIBBLE 0x00000004
415 #define DC_RXSTAT_MIIERE 0x00000008
416 #define DC_RXSTAT_WATCHDOG 0x00000010
417 #define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
418 #define DC_RXSTAT_COLLSEEN 0x00000040
419 #define DC_RXSTAT_GIANT 0x00000080
420 #define DC_RXSTAT_LASTFRAG 0x00000100
421 #define DC_RXSTAT_FIRSTFRAG 0x00000200
422 #define DC_RXSTAT_MULTICAST 0x00000400
423 #define DC_RXSTAT_RUNT 0x00000800
424 #define DC_RXSTAT_RXTYPE 0x00003000
425 #define DC_RXSTAT_DE 0x00004000
426 #define DC_RXSTAT_RXERR 0x00008000
427 #define DC_RXSTAT_RXLEN 0x3FFF0000
428 #define DC_RXSTAT_OWN 0x80000000
429
430 #define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16)
431 #define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN)
432
433 #define DC_RXCTL_BUFLEN1 0x00000FFF
434 #define DC_RXCTL_BUFLEN2 0x00FFF000
435 #define DC_RXCTL_RLINK 0x01000000
436 #define DC_RXCTL_RLAST 0x02000000
437
438 #define DC_TXSTAT_DEFER 0x00000001
439 #define DC_TXSTAT_UNDERRUN 0x00000002
440 #define DC_TXSTAT_LINKFAIL 0x00000003
441 #define DC_TXSTAT_COLLCNT 0x00000078
442 #define DC_TXSTAT_SQE 0x00000080
443 #define DC_TXSTAT_EXCESSCOLL 0x00000100
444 #define DC_TXSTAT_LATECOLL 0x00000200
445 #define DC_TXSTAT_NOCARRIER 0x00000400
446 #define DC_TXSTAT_CARRLOST 0x00000800
447 #define DC_TXSTAT_JABTIMEO 0x00004000
448 #define DC_TXSTAT_ERRSUM 0x00008000
449 #define DC_TXSTAT_OWN 0x80000000
450
451 #define DC_TXCTL_BUFLEN1 0x000007FF
452 #define DC_TXCTL_BUFLEN2 0x003FF800
453 #define DC_TXCTL_FILTTYPE0 0x00400000
454 #define DC_TXCTL_PAD 0x00800000
455 #define DC_TXCTL_TLINK 0x01000000
456 #define DC_TXCTL_TLAST 0x02000000
457 #define DC_TXCTL_NOCRC 0x04000000
458 #define DC_TXCTL_SETUP 0x08000000
459 #define DC_TXCTL_FILTTYPE1 0x10000000
460 #define DC_TXCTL_FIRSTFRAG 0x20000000
461 #define DC_TXCTL_LASTFRAG 0x40000000
462 #define DC_TXCTL_FINT 0x80000000
463
464 #define DC_FILTER_PERFECT 0x00000000
465 #define DC_FILTER_HASHPERF 0x00400000
466 #define DC_FILTER_INVERSE 0x10000000
467 #define DC_FILTER_HASHONLY 0x10400000
468
469 #define DC_MAXFRAGS 16
470 #ifdef DEVICE_POLLING
471 #define DC_RX_LIST_CNT 192
472 #else
473 #define DC_RX_LIST_CNT 64
474 #endif
475 #define DC_TX_LIST_CNT 256
476 #define DC_TX_LIST_RSVD 5
477 #define DC_MIN_FRAMELEN 60
478 #define DC_RXLEN 1536
479
480 #define DC_INC(x, y) (x) = (x + 1) % y
481
482 #define DC_LIST_ALIGN (sizeof(struct dc_desc))
483 #define DC_RXBUF_ALIGN 4
484
485 /* Macros to easily get the DMA address of a descriptor. */
486 #define DC_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF)
487 #define DC_RXDESC(sc, i) \
488 (DC_ADDR_LO(sc->dc_ldata.dc_rx_list_paddr + (sizeof(struct dc_desc) * i)))
489 #define DC_TXDESC(sc, i) \
490 (DC_ADDR_LO(sc->dc_ldata.dc_tx_list_paddr + (sizeof(struct dc_desc) * i)))
491
492 #if BYTE_ORDER == BIG_ENDIAN
493 #define DC_SP_MAC(x) ((x) << 16)
494 #else
495 #define DC_SP_MAC(x) (x)
496 #endif
497
498 struct dc_list_data {
499 struct dc_desc *dc_rx_list;
500 bus_addr_t dc_rx_list_paddr;
501 struct dc_desc *dc_tx_list;
502 bus_addr_t dc_tx_list_paddr;
503 };
504
505 #define DC_RX_LIST_SZ ((sizeof(struct dc_desc) * DC_RX_LIST_CNT))
506 #define DC_TX_LIST_SZ ((sizeof(struct dc_desc) * DC_TX_LIST_CNT))
507
508 struct dc_chain_data {
509 struct mbuf *dc_rx_chain[DC_RX_LIST_CNT];
510 struct mbuf *dc_tx_chain[DC_TX_LIST_CNT];
511 bus_dmamap_t dc_rx_map[DC_RX_LIST_CNT];
512 bus_dmamap_t dc_tx_map[DC_TX_LIST_CNT];
513 uint32_t *dc_sbuf;
514 uint8_t dc_pad[DC_MIN_FRAMELEN];
515 int dc_tx_pkts;
516 int dc_tx_first;
517 int dc_tx_prod;
518 int dc_tx_cons;
519 int dc_tx_cnt;
520 int dc_rx_prod;
521 };
522
523 struct dc_mediainfo {
524 int dc_media;
525 uint8_t *dc_gp_ptr;
526 uint8_t dc_gp_len;
527 uint8_t *dc_reset_ptr;
528 uint8_t dc_reset_len;
529 struct dc_mediainfo *dc_next;
530 };
531
532
533 struct dc_type {
534 uint32_t dc_devid;
535 uint8_t dc_minrev;
536 const char *dc_name;
537 };
538
539 /*
540 * Registers specific to clone devices.
541 * This mainly relates to RX filter programming: not all 21x4x clones
542 * use the standard DEC filter programming mechanism.
543 */
544
545 /*
546 * ADMtek specific registers and constants for the AL981 and AN983.
547 * The AN983 doesn't use the magic PHY registers.
548 */
549 #define DC_AL_CR 0x88 /* command register */
550 #define DC_AL_PAR0 0xA4 /* station address */
551 #define DC_AL_PAR1 0xA8 /* station address */
552 #define DC_AL_MAR0 0xAC /* multicast hash filter */
553 #define DC_AL_MAR1 0xB0 /* multicast hash filter */
554 #define DC_AL_BMCR 0xB4 /* built in PHY control */
555 #define DC_AL_BMSR 0xB8 /* built in PHY status */
556 #define DC_AL_VENID 0xBC /* built in PHY ID0 */
557 #define DC_AL_DEVID 0xC0 /* built in PHY ID1 */
558 #define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */
559 #define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */
560 #define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */
561
562 #define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */
563 #define DC_ADMTEK_PHYADDR 0x1
564 #define DC_AL_EE_NODEADDR 4
565 /* End of ADMtek specific registers */
566
567 /*
568 * ASIX specific registers.
569 */
570 #define DC_AX_FILTIDX 0x68 /* RX filter index */
571 #define DC_AX_FILTDATA 0x70 /* RX filter data */
572
573 /*
574 * Special ASIX-specific bits in the ASIX NETCFG register (CSR6).
575 */
576 #define DC_AX_NETCFG_RX_BROAD 0x00000100
577
578 /*
579 * RX Filter Index Register values
580 */
581 #define DC_AX_FILTIDX_PAR0 0x00000000
582 #define DC_AX_FILTIDX_PAR1 0x00000001
583 #define DC_AX_FILTIDX_MAR0 0x00000002
584 #define DC_AX_FILTIDX_MAR1 0x00000003
585 /* End of ASIX specific registers */
586
587 /*
588 * Macronix specific registers. The Macronix chips have a special
589 * register for reading the NWAY status, which we don't use, plus
590 * a magic packet register, which we need to tweak a bit per the
591 * Macronix application notes.
592 */
593 #define DC_MX_MAGICPACKET 0x80
594 #define DC_MX_NWAYSTAT 0xA0
595
596 /*
597 * Magic packet register
598 */
599 #define DC_MX_MPACK_DISABLE 0x00400000
600
601 /*
602 * NWAY status register.
603 */
604 #define DC_MX_NWAY_10BTHALF 0x08000000
605 #define DC_MX_NWAY_10BTFULL 0x10000000
606 #define DC_MX_NWAY_100BTHALF 0x20000000
607 #define DC_MX_NWAY_100BTFULL 0x40000000
608 #define DC_MX_NWAY_100BT4 0x80000000
609
610 /*
611 * These are magic values that must be written into CSR16
612 * (DC_MX_MAGICPACKET) in order to put the chip into proper
613 * operating mode. The magic numbers are documented in the
614 * Macronix 98715 application notes.
615 */
616 #define DC_MX_MAGIC_98713 0x0F370000
617 #define DC_MX_MAGIC_98713A 0x0B3C0000
618 #define DC_MX_MAGIC_98715 0x0B3C0000
619 #define DC_MX_MAGIC_98725 0x0B3C0000
620 /* End of Macronix specific registers */
621
622 /*
623 * PNIC 82c168/82c169 specific registers.
624 * The PNIC has its own special NWAY support, which doesn't work,
625 * and shortcut ways of reading the EEPROM and MII bus.
626 */
627 #define DC_PN_GPIO 0x60 /* general purpose pins control */
628 #define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */
629 #define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */
630 #define DC_PN_MII 0xA0 /* MII access register */
631 #define DC_PN_NWAY 0xB8 /* Internal NWAY register */
632
633 /* Serial I/O EEPROM register */
634 #define DC_PN_SIOCTL_DATA 0x0000003F
635 #define DC_PN_SIOCTL_OPCODE 0x00000300
636 #define DC_PN_SIOCTL_BUSY 0x80000000
637
638 #define DC_PN_EEOPCODE_ERASE 0x00000300
639 #define DC_PN_EEOPCODE_READ 0x00000600
640 #define DC_PN_EEOPCODE_WRITE 0x00000100
641
642 /*
643 * The first two general purpose pins control speed selection and
644 * 100Mbps loopback on the 82c168 chip. The control bits should always
645 * be set (to make the data pins outputs) and the speed selction and
646 * loopback bits set accordingly when changing media. Physically, this
647 * will set the state of a relay mounted on the card.
648 */
649 #define DC_PN_GPIO_DATA0 0x000000001
650 #define DC_PN_GPIO_DATA1 0x000000002
651 #define DC_PN_GPIO_DATA2 0x000000004
652 #define DC_PN_GPIO_DATA3 0x000000008
653 #define DC_PN_GPIO_CTL0 0x000000010
654 #define DC_PN_GPIO_CTL1 0x000000020
655 #define DC_PN_GPIO_CTL2 0x000000040
656 #define DC_PN_GPIO_CTL3 0x000000080
657 #define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */
658 #define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */
659 #define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2
660 #define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3
661 #define DC_PN_GPIO_SETBIT(sc, r) \
662 DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4)))
663 #define DC_PN_GPIO_CLRBIT(sc, r) \
664 { \
665 DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \
666 DC_CLRBIT(sc, DC_PN_GPIO, (r)); \
667 }
668
669 /* shortcut MII access register */
670 #define DC_PN_MII_DATA 0x0000FFFF
671 #define DC_PN_MII_RESERVER 0x00020000
672 #define DC_PN_MII_REGADDR 0x007C0000
673 #define DC_PN_MII_PHYADDR 0x0F800000
674 #define DC_PN_MII_OPCODE 0x30000000
675 #define DC_PN_MII_BUSY 0x80000000
676
677 #define DC_PN_MIIOPCODE_READ 0x60020000
678 #define DC_PN_MIIOPCODE_WRITE 0x50020000
679
680 /* Internal NWAY bits */
681 #define DC_PN_NWAY_RESET 0x00000001 /* reset */
682 #define DC_PN_NWAY_PDOWN 0x00000002 /* power down */
683 #define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */
684 #define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */
685 #define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */
686 #define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */
687 #define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */
688 #define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */
689 #define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */
690 #define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */
691 #define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */
692 #define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */
693 #define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */
694 #define DC_PN_NWAY_CAP10HDX 0x00002000
695 #define DC_PN_NWAY_CAP10FDX 0x00004000
696 #define DC_PN_NWAY_CAP100FDX 0x00008000
697 #define DC_PN_NWAY_CAP100HDX 0x00010000
698 #define DC_PN_NWAY_CAP100T4 0x00020000
699 #define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */
700 #define DC_PN_NWAY_REMFAULT 0x04000000
701 #define DC_PN_NWAY_LPAR10HDX 0x08000000
702 #define DC_PN_NWAY_LPAR10FDX 0x10000000
703 #define DC_PN_NWAY_LPAR100FDX 0x20000000
704 #define DC_PN_NWAY_LPAR100HDX 0x40000000
705 #define DC_PN_NWAY_LPAR100T4 0x80000000
706
707 /* End of PNIC specific registers */
708
709 /*
710 * CONEXANT specific registers.
711 */
712
713 #define DC_CONEXANT_PHYADDR 0x1
714 #define DC_CONEXANT_EE_NODEADDR 0x19A
715
716 /* End of CONEXANT specific registers */
717
718 /*
719 * ULi M5263 specific registers.
720 */
721 #define DC_ULI_FILTER_NPERF 14
722
723 #define DC_ULI_PHY_DATA_MASK 0x0000FFFF
724 #define DC_ULI_PHY_REG_MASK 0x001F0000
725 #define DC_ULI_PHY_ADDR_MASK 0x03E00000
726 #define DC_ULI_PHY_OP_WRITE 0x04000000
727 #define DC_ULI_PHY_OP_READ 0x08000000
728 #define DC_ULI_PHY_OP_DONE 0x10000000
729
730 #define DC_ULI_PHY_DATA_SHIFT 0
731 #define DC_ULI_PHY_REG_SHIFT 16
732 #define DC_ULI_PHY_ADDR_SHIFT 21
733
734 /* End of ULi M5263 specific registers */
735
736 struct dc_softc {
737 struct ifnet *dc_ifp; /* interface info */
738 device_t dc_dev; /* device info */
739 bus_space_handle_t dc_bhandle; /* bus space handle */
740 bus_space_tag_t dc_btag; /* bus space tag */
741 bus_dma_tag_t dc_ptag; /* parent DMA tag */
742 bus_dmamap_t dc_sparemap;
743 bus_dma_tag_t dc_rx_ltag; /* tag for RX descriptors */
744 bus_dmamap_t dc_rx_lmap;
745 bus_dma_tag_t dc_tx_ltag; /* tag for TX descriptors */
746 bus_dmamap_t dc_tx_lmap;
747 bus_dma_tag_t dc_stag; /* tag for the setup frame */
748 bus_dmamap_t dc_smap; /* map for the setup frame */
749 bus_addr_t dc_saddr; /* DMA address of setup frame */
750 bus_dma_tag_t dc_rx_mtag; /* tag for RX mbufs */
751 bus_dma_tag_t dc_tx_mtag; /* tag for TX mbufs */
752 void *dc_intrhand;
753 struct resource *dc_irq;
754 struct resource *dc_res;
755 const struct dc_type *dc_info; /* adapter info */
756 device_t dc_miibus;
757 uint8_t dc_type;
758 uint8_t dc_pmode;
759 uint8_t dc_link;
760 uint8_t dc_cachesize;
761 int dc_romwidth;
762 int dc_pnic_rx_bug_save;
763 unsigned char *dc_pnic_rx_buf;
764 int dc_if_flags;
765 uint32_t dc_flags;
766 uint32_t dc_txthresh;
767 uint32_t dc_eaddr[2];
768 uint8_t *dc_srom;
769 struct dc_mediainfo *dc_mi;
770 struct dc_list_data dc_ldata;
771 struct dc_chain_data dc_cdata;
772 struct callout dc_stat_ch;
773 struct callout dc_wdog_ch;
774 int dc_wdog_timer;
775 struct mtx dc_mtx;
776 #ifdef DEVICE_POLLING
777 int rxcycles; /* ... when polling */
778 #endif
779 int suspended; /* 0 = normal 1 = suspended */
780 };
781
782
783 #define DC_LOCK(_sc) mtx_lock(&(_sc)->dc_mtx)
784 #define DC_UNLOCK(_sc) mtx_unlock(&(_sc)->dc_mtx)
785 #define DC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->dc_mtx, MA_OWNED)
786
787 #define DC_TX_POLL 0x00000001
788 #define DC_TX_COALESCE 0x00000002
789 #define DC_TX_ADMTEK_WAR 0x00000004
790 #define DC_TX_USE_TX_INTR 0x00000008
791 #define DC_RX_FILTER_TULIP 0x00000010
792 #define DC_TX_INTR_FIRSTFRAG 0x00000020
793 #define DC_PNIC_RX_BUG_WAR 0x00000040
794 #define DC_TX_FIXED_RING 0x00000080
795 #define DC_TX_STORENFWD 0x00000100
796 #define DC_REDUCED_MII_POLL 0x00000200
797 #define DC_TX_INTR_ALWAYS 0x00000400
798 #define DC_21143_NWAY 0x00000800
799 #define DC_128BIT_HASH 0x00001000
800 #define DC_64BIT_HASH 0x00002000
801 #define DC_TULIP_LEDS 0x00004000
802 #define DC_TX_ALIGN 0x00010000 /* align mbuf on tx */
803
804 /*
805 * register space access macros
806 */
807 #define CSR_WRITE_4(sc, reg, val) \
808 bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)
809
810 #define CSR_READ_4(sc, reg) \
811 bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg)
812
813 #define CSR_BARRIER_4(sc, reg, flags) \
814 bus_space_barrier(sc->dc_btag, sc->dc_bhandle, reg, 4, flags)
815
816 #define DC_TIMEOUT 1000
817
818 /*
819 * General constants that are fun to know.
820 */
821
822 /*
823 * DEC PCI vendor ID
824 */
825 #define DC_VENDORID_DEC 0x1011
826
827 /*
828 * DEC/Intel 21143 PCI device ID
829 */
830 #define DC_DEVICEID_21143 0x0019
831
832 /*
833 * Macronix PCI vendor ID
834 */
835 #define DC_VENDORID_MX 0x10D9
836
837 /*
838 * Macronix PMAC device IDs.
839 */
840 #define DC_DEVICEID_98713 0x0512
841 #define DC_DEVICEID_987x5 0x0531
842 #define DC_DEVICEID_98727 0x0532
843 #define DC_DEVICEID_98732 0x0532
844
845 /* Macronix PCI revision codes. */
846 #define DC_REVISION_98713 0x00
847 #define DC_REVISION_98713A 0x10
848 #define DC_REVISION_98715 0x20
849 #define DC_REVISION_98715AEC_C 0x25
850 #define DC_REVISION_98725 0x30
851
852 /*
853 * Compex PCI vendor ID.
854 */
855 #define DC_VENDORID_CP 0x11F6
856
857 /*
858 * Compex PMAC PCI device IDs.
859 */
860 #define DC_DEVICEID_98713_CP 0x9881
861
862 /*
863 * Lite-On PNIC PCI vendor ID
864 */
865 #define DC_VENDORID_LO 0x11AD
866
867 /*
868 * 82c168/82c169 PNIC device IDs. Both chips have the same device
869 * ID but different revisions. Revision 0x10 is the 82c168, and
870 * 0x20 is the 82c169.
871 */
872 #define DC_DEVICEID_82C168 0x0002
873
874 #define DC_REVISION_82C168 0x10
875 #define DC_REVISION_82C169 0x20
876
877 /*
878 * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A
879 * with wake on lan/magic packet support.
880 */
881 #define DC_DEVICEID_82C115 0xc115
882
883 /*
884 * Davicom vendor ID.
885 */
886 #define DC_VENDORID_DAVICOM 0x1282
887
888 /*
889 * Davicom device IDs.
890 */
891 #define DC_DEVICEID_DM9009 0x9009
892 #define DC_DEVICEID_DM9100 0x9100
893 #define DC_DEVICEID_DM9102 0x9102
894
895 /*
896 * The DM9102A has the same PCI device ID as the DM9102,
897 * but a higher revision code.
898 */
899 #define DC_REVISION_DM9102 0x10
900 #define DC_REVISION_DM9102A 0x30
901
902 /*
903 * ADMtek vendor ID.
904 */
905 #define DC_VENDORID_ADMTEK 0x1317
906
907 /*
908 * ADMtek device IDs.
909 */
910 #define DC_DEVICEID_AL981 0x0981
911 #define DC_DEVICEID_AN983 0x0985
912 #define DC_DEVICEID_AN985 0x1985
913 #define DC_DEVICEID_ADM9511 0x9511
914 #define DC_DEVICEID_ADM9513 0x9513
915
916 /*
917 * 3COM PCI vendor ID
918 */
919 #define DC_VENDORID_3COM 0x10b7
920
921 /*
922 * 3COM OfficeConnect 10/100B (3CSOHO100B-TX)
923 */
924 #define DC_DEVICEID_3CSOHOB 0x9300
925
926 /*
927 * ASIX vendor ID.
928 */
929 #define DC_VENDORID_ASIX 0x125B
930
931 /*
932 * ASIX device IDs.
933 */
934 #define DC_DEVICEID_AX88140A 0x1400
935
936 /*
937 * The ASIX AX88140 and ASIX AX88141 have the same vendor and
938 * device IDs but different revision values.
939 */
940 #define DC_REVISION_88140 0x00
941 #define DC_REVISION_88141 0x10
942
943 /*
944 * Accton vendor ID.
945 */
946 #define DC_VENDORID_ACCTON 0x1113
947
948 /*
949 * Accton device IDs.
950 */
951 #define DC_DEVICEID_EN1217 0x1217
952 #define DC_DEVICEID_EN2242 0x1216
953
954 /*
955 * Xircom vendor ID
956 */
957 #define DC_VENDORID_XIRCOM 0x115d
958
959 /*
960 * Xircom device IDs.
961 */
962 #define DC_DEVICEID_X3201 0x0003
963
964 /*
965 * D-Link vendor ID
966 */
967 #define DC_VENDORID_DLINK 0x1186
968
969 /*
970 * D-Link device IDs.
971 */
972 #define DC_DEVICEID_DRP32TXD 0x1561
973
974 /*
975 * Abocom vendor ID
976 */
977 #define DC_VENDORID_ABOCOM 0x13d1
978
979 /*
980 * Abocom device IDs.
981 */
982 #define DC_DEVICEID_FE2500 0xAB02
983 #define DC_DEVICEID_FE2500MX 0xab08
984
985 /*
986 * Conexant vendor ID.
987 */
988 #define DC_VENDORID_CONEXANT 0x14f1
989
990 /*
991 * Conexant device IDs.
992 */
993 #define DC_DEVICEID_RS7112 0x1803
994
995 /*
996 * Planex vendor ID
997 */
998 #define DC_VENDORID_PLANEX 0x14ea
999
1000 /*
1001 * Planex device IDs.
1002 */
1003 #define DC_DEVICEID_FNW3602T 0xab08
1004
1005 /*
1006 * Not sure who this vendor should be, so we'll go with HAWKING until
1007 * I can locate the right one.
1008 */
1009 #define DC_VENDORID_HAWKING 0x17b3
1010
1011 /*
1012 * Sure looks like an abocom device ID, but it found on my hawking PN672TX
1013 * card. Use that for now, and upgrade later.
1014 */
1015 #define DC_DEVICEID_HAWKING_PN672TX 0xab08
1016
1017 /*
1018 * Microsoft device ID.
1019 */
1020 #define DC_VENDORID_MICROSOFT 0x1414
1021
1022 /*
1023 * Supported Microsoft PCI and CardBus NICs. These are really
1024 * ADMtek parts in disguise.
1025 */
1026
1027 #define DC_DEVICEID_MSMN120 0x0001
1028 #define DC_DEVICEID_MSMN130 0x0002
1029
1030 /*
1031 * Linksys vendor ID.
1032 */
1033 #define DC_VENDORID_LINKSYS 0x1737
1034
1035 /*
1036 * Linksys device IDs.
1037 */
1038 #define DC_DEVICEID_PCMPC200_AB08 0xab08
1039 #define DC_DEVICEID_PCMPC200_AB09 0xab09
1040
1041 /*
1042 * ULi vendor ID.
1043 */
1044 #define DC_VENDORID_ULI 0x10b9
1045
1046 /*
1047 * ULi device IDs.
1048 */
1049 #define DC_DEVICEID_M5261 0x5261
1050 #define DC_DEVICEID_M5263 0x5263
1051
1052 #define DC_DEVID(vendor, device) ((device) << 16 | (vendor))
1053
1054 /*
1055 * PCI low memory base and low I/O base register, and
1056 * other PCI registers.
1057 */
1058
1059 #define DC_PCI_CFBIO PCIR_BAR(0) /* Base I/O address */
1060 #define DC_PCI_CFBMA PCIR_BAR(1) /* Base memory address */
1061 #define DC_PCI_CFDD 0x40 /* Device and driver area */
1062 #define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */
1063 #define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */
1064 #define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */
1065 #define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */
1066 #define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */
1067
1068 #define DC_21143_PB_REV 0x00000030
1069 #define DC_21143_TB_REV 0x00000030
1070 #define DC_21143_PC_REV 0x00000030
1071 #define DC_21143_TC_REV 0x00000030
1072 #define DC_21143_PD_REV 0x00000041
1073 #define DC_21143_TD_REV 0x00000041
1074
1075 /* Configuration and driver area */
1076 #define DC_CFDD_DRVUSE 0x0000FFFF
1077 #define DC_CFDD_SNOOZE_MODE 0x40000000
1078 #define DC_CFDD_SLEEP_MODE 0x80000000
1079
1080 /* Configuration wake-up command register */
1081 #define DC_CWUC_MUST_BE_ZERO 0x00000001
1082 #define DC_CWUC_SECUREON_ENB 0x00000002
1083 #define DC_CWUC_FORCE_WUL 0x00000004
1084 #define DC_CWUC_BNC_ABILITY 0x00000008
1085 #define DC_CWUC_AUI_ABILITY 0x00000010
1086 #define DC_CWUC_TP10_ABILITY 0x00000020
1087 #define DC_CWUC_MII_ABILITY 0x00000040
1088 #define DC_CWUC_SYM_ABILITY 0x00000080
1089 #define DC_CWUC_LOCK 0x00000100
1090
1091 /*
1092 * SROM nonsense.
1093 */
1094
1095 #define DC_ROM_SIZE(bits) (2 << (bits))
1096
1097 #define DC_IB_CTLRCNT 0x13
1098 #define DC_IB_LEAF0_CNUM 0x1A
1099 #define DC_IB_LEAF0_OFFSET 0x1B
1100
1101 struct dc_info_leaf {
1102 uint16_t dc_conntype;
1103 uint8_t dc_blkcnt;
1104 uint8_t dc_rsvd;
1105 uint16_t dc_infoblk;
1106 };
1107
1108 #define DC_CTYPE_10BT 0x0000
1109 #define DC_CTYPE_10BT_NWAY 0x0100
1110 #define DC_CTYPE_10BT_FDX 0x0204
1111 #define DC_CTYPE_10B2 0x0001
1112 #define DC_CTYPE_10B5 0x0002
1113 #define DC_CTYPE_100BT 0x0003
1114 #define DC_CTYPE_100BT_FDX 0x0205
1115 #define DC_CTYPE_100T4 0x0006
1116 #define DC_CTYPE_100FX 0x0007
1117 #define DC_CTYPE_100FX_FDX 0x0208
1118 #define DC_CTYPE_MII_10BT 0x0009
1119 #define DC_CTYPE_MII_10BT_FDX 0x020A
1120 #define DC_CTYPE_MII_100BT 0x000D
1121 #define DC_CTYPE_MII_100BT_FDX 0x020E
1122 #define DC_CTYPE_MII_100T4 0x000F
1123 #define DC_CTYPE_MII_100FX 0x0010
1124 #define DC_CTYPE_MII_100FX_FDX 0x0211
1125 #define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800
1126 #define DC_CTYPE_PUP_AUTOSENSE 0x8800
1127 #define DC_CTYPE_NOMEDIA 0xFFFF
1128
1129 #define DC_EBLOCK_SIA 0x0002
1130 #define DC_EBLOCK_MII 0x0003
1131 #define DC_EBLOCK_SYM 0x0004
1132 #define DC_EBLOCK_RESET 0x0005
1133 #define DC_EBLOCK_PHY_SHUTDOWN 0x0006
1134
1135 struct dc_leaf_hdr {
1136 uint16_t dc_mtype;
1137 uint8_t dc_mcnt;
1138 uint8_t dc_rsvd;
1139 };
1140
1141 struct dc_eblock_hdr {
1142 uint8_t dc_len;
1143 uint8_t dc_type;
1144 };
1145
1146 struct dc_eblock_sia {
1147 struct dc_eblock_hdr dc_sia_hdr;
1148 uint8_t dc_sia_code;
1149 union {
1150 struct dc_sia_ext { /* if (dc_sia_code & DC_SIA_CODE_EXT) */
1151 uint8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */
1152 uint8_t dc_sia_gpio_ctl[2];
1153 uint8_t dc_sia_gpio_dat[2];
1154 } dc_sia_ext;
1155 struct dc_sia_noext {
1156 uint8_t dc_sia_gpio_ctl[2];
1157 uint8_t dc_sia_gpio_dat[2];
1158 } dc_sia_noext;
1159 } dc_un;
1160 };
1161
1162 #define DC_SIA_CODE_10BT 0x00
1163 #define DC_SIA_CODE_10B2 0x01
1164 #define DC_SIA_CODE_10B5 0x02
1165 #define DC_SIA_CODE_10BT_FDX 0x04
1166 #define DC_SIA_CODE_EXT 0x40
1167
1168 /*
1169 * Note that the first word in the gpr and reset
1170 * sequences is always a control word.
1171 */
1172 struct dc_eblock_mii {
1173 struct dc_eblock_hdr dc_mii_hdr;
1174 uint8_t dc_mii_phynum;
1175 uint8_t dc_gpr_len;
1176 /* uint16_t dc_gpr_dat[n]; */
1177 /* uint8_t dc_reset_len; */
1178 /* uint16_t dc_reset_dat[n]; */
1179 /* There are other fields after these, but we don't
1180 * care about them since they can be determined by looking
1181 * at the PHY.
1182 */
1183 };
1184
1185 struct dc_eblock_sym {
1186 struct dc_eblock_hdr dc_sym_hdr;
1187 uint8_t dc_sym_code;
1188 uint8_t dc_sym_gpio_ctl[2];
1189 uint8_t dc_sym_gpio_dat[2];
1190 uint8_t dc_sym_cmd[2];
1191 };
1192
1193 #define DC_SYM_CODE_100BT 0x03
1194 #define DC_SYM_CODE_100BT_FDX 0x05
1195 #define DC_SYM_CODE_100T4 0x06
1196 #define DC_SYM_CODE_100FX 0x07
1197 #define DC_SYM_CODE_100FX_FDX 0x08
1198
1199 struct dc_eblock_reset {
1200 struct dc_eblock_hdr dc_reset_hdr;
1201 uint8_t dc_reset_len;
1202 /* uint16_t dc_reset_dat[n]; */
1203 };
Cache object: 0b84b1d81e5bc9474d0fa007f1b62351
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